Infineon psoc6_02 2024.05.01 PSoC6_02 CM4 r0p1 little true true 3 false 8 32 BACKUP SRSS Backup Domain BACKUP 0x0 0x0 0x10000 registers n ALM1_DATE Alarm 1 Day of Month, Month 0x20 32 read-write n 0x0 0x0 ALM_DATE Alarm Day of the Month in BCD, 1-31 Leap Year corrected 0 6 read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match 7 8 read-write ALM_EN Master enable for alarm 1. 0: Alarm 1 is disabled. Fields for date and time are ignored. 1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. 31 32 read-write ALM_MON Alarm Month in BCD, 1-12 8 13 read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match 15 16 read-write ALM1_TIME Alarm 1 Seconds, Minute, Hours, Day of Week 0x1C 32 read-write n 0x0 0x0 ALM_DAY Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended 24 27 read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match 31 32 read-write ALM_HOUR Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 16 22 read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match 23 24 read-write ALM_MIN Alarm minutes in BCD, 0-59 8 15 read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match 15 16 read-write ALM_SEC Alarm seconds in BCD, 0-59 0 7 read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match 7 8 read-write ALM2_DATE Alarm 2 Day of Month, Month 0x28 32 read-write n 0x0 0x0 ALM_DATE Alarm Day of the Month in BCD, 1-31 Leap Year corrected 0 6 read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match 7 8 read-write ALM_EN Master enable for alarm 2. 0: Alarm 2 is disabled. Fields for date and time are ignored. 1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. 31 32 read-write ALM_MON Alarm Month in BCD, 1-12 8 13 read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match 15 16 read-write ALM2_TIME Alarm 2 Seconds, Minute, Hours, Day of Week 0x24 32 read-write n 0x0 0x0 ALM_DAY Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended 24 27 read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match 31 32 read-write ALM_HOUR Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 16 22 read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match 23 24 read-write ALM_MIN Alarm minutes in BCD, 0-59 8 15 read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match 15 16 read-write ALM_SEC Alarm seconds in BCD, 0-59 0 7 read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match 7 8 read-write BREG0 Backup register region 0x1000 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG1 Backup register region 0x1004 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG10 Backup register region 0x1028 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG11 Backup register region 0x102C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG12 Backup register region 0x1030 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG13 Backup register region 0x1034 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG14 Backup register region 0x1038 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG15 Backup register region 0x103C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG16 Backup register region 0x1040 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG17 Backup register region 0x1044 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG18 Backup register region 0x1048 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG19 Backup register region 0x104C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG2 Backup register region 0x1008 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG20 Backup register region 0x1050 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG21 Backup register region 0x1054 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG22 Backup register region 0x1058 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG23 Backup register region 0x105C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG24 Backup register region 0x1060 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG25 Backup register region 0x1064 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG26 Backup register region 0x1068 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG27 Backup register region 0x106C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG28 Backup register region 0x1070 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG29 Backup register region 0x1074 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG3 Backup register region 0x100C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG30 Backup register region 0x1078 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG31 Backup register region 0x107C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG32 Backup register region 0x1080 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG33 Backup register region 0x1084 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG34 Backup register region 0x1088 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG35 Backup register region 0x108C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG36 Backup register region 0x1090 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG37 Backup register region 0x1094 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG38 Backup register region 0x1098 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG39 Backup register region 0x109C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG4 Backup register region 0x1010 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG40 Backup register region 0x10A0 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG41 Backup register region 0x10A4 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG42 Backup register region 0x10A8 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG43 Backup register region 0x10AC 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG44 Backup register region 0x10B0 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG45 Backup register region 0x10B4 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG46 Backup register region 0x10B8 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG47 Backup register region 0x10BC 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG48 Backup register region 0x10C0 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG49 Backup register region 0x10C4 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG5 Backup register region 0x1014 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG50 Backup register region 0x10C8 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG51 Backup register region 0x10CC 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG52 Backup register region 0x10D0 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG53 Backup register region 0x10D4 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG54 Backup register region 0x10D8 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG55 Backup register region 0x10DC 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG56 Backup register region 0x10E0 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG57 Backup register region 0x10E4 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG58 Backup register region 0x10E8 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG59 Backup register region 0x10EC 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG6 Backup register region 0x1018 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG60 Backup register region 0x10F0 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG61 Backup register region 0x10F4 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG62 Backup register region 0x10F8 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG63 Backup register region 0x10FC 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG7 Backup register region 0x101C 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG8 Backup register region 0x1020 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write BREG9 Backup register region 0x1024 32 read-write n 0x0 0x0 BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. 0 32 read-write CAL_CTL Oscillator calibration for absolute frequency 0xC 32 read-write n 0x0 0x0 CALIB_SIGN Calibration sign: 0= Negative sign: remove pulses (it takes more clock ticks to count one second) 1= Positive sign: add pulses (it takes less clock ticks to count one second) 6 7 read-write CALIB_VAL Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. 0 6 read-write CAL_OUT Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. 31 32 read-write CTL Control 0x0 32 read-write n 0x0 0x0 CLK_SEL Clock select for BAK clock 8 10 read-write WCO Watch-crystal oscillator input. 0 ALTBAK This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. 1 EN_CHARGE_KEY When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. 24 32 read-write PRESCALER N/A 12 14 read-write VBACKUP_MEAS Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. 19 20 read-write VDDBAK_CTL Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. 17 19 read-write WCO_BYPASS Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. 16 17 read-write WCO_EN Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. 3 4 read-write INTR Interrupt request register 0x2C 32 read-write n 0x0 0x0 ALARM1 Alarm 1 Interrupt 0 1 read-write ALARM2 Alarm 2 Interrupt 1 2 read-write CENTURY Century overflow interrupt 2 3 read-write INTR_MASK Interrupt mask register 0x34 32 read-write n 0x0 0x0 ALARM1 Mask bit for corresponding bit in interrupt request register. 0 1 read-write ALARM2 Mask bit for corresponding bit in interrupt request register. 1 2 read-write CENTURY Mask bit for corresponding bit in interrupt request register. 2 3 read-write INTR_MASKED Interrupt masked request register 0x38 32 read-only n 0x0 0x0 ALARM1 Logical and of corresponding request and mask bits. 0 1 read-only ALARM2 Logical and of corresponding request and mask bits. 1 2 read-only CENTURY Logical and of corresponding request and mask bits. 2 3 read-only INTR_SET Interrupt set request register 0x30 32 read-write n 0x0 0x0 ALARM1 Write with '1' to set corresponding bit in interrupt request register. 0 1 read-write ALARM2 Write with '1' to set corresponding bit in interrupt request register. 1 2 read-write CENTURY Write with '1' to set corresponding bit in interrupt request register. 2 3 read-write OSCCNT 32kHz oscillator counter 0x3C 32 read-only n 0x0 0x0 CNT32KHZ 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. 0 8 read-only PMIC_CTL PMIC control register 0x44 32 read-write n 0x0 0x0 PMIC_ALWAYSEN Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. 0: Normal operation, PMIC_EN and PMIC_OUTEN work as described 1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. Note: This bit is a write-once bit until the next backup reset. 30 31 read-write PMIC_EN Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. 31 32 read-write PMIC_EN_OUTEN Output enable for the output driver in the PMIC_EN pad. 0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present 1: Output pad is enabled for PMIC_EN pin. 29 30 read-write POLARITY N/A 16 17 read-write UNLOCK This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code do these in separate write cycles. 8 16 read-write RESET Backup reset register 0x48 32 read-write n 0x0 0x0 RESET Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. 31 32 read-write RTC_DATE Calendar Day of Month, Month, Year 0x18 32 read-write n 0x0 0x0 RTC_DATE Calendar Day of the Month in BCD, 1-31 Automatic Leap Year Correction 0 6 read-write RTC_MON Calendar Month in BCD, 1-12 8 13 read-write RTC_YEAR Calendar year in BCD, 0-99 16 24 read-write RTC_RW RTC Read Write register 0x8 32 read-write n 0x0 0x0 READ Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. 0 1 read-write WRITE Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. Only user RTC registers that were written to will get copied, others will not be affected. When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. 1 2 read-write RTC_TIME Calendar Seconds, Minutes, Hours, Day of Week 0x14 32 read-write n 0x0 0x0 CTRL_12HR Select 12/24HR mode: 1=12HR, 0=24HR 22 23 read-write RTC_DAY Calendar Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended 24 27 read-write RTC_HOUR Calendar hours in BCD, value depending on 12/24HR mode 0=24HR: [21:16]=0-23 1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 16 22 read-write RTC_MIN Calendar minutes in BCD, 0-59 8 15 read-write RTC_SEC Calendar seconds in BCD, 0-59 0 7 read-write STATUS Status 0x10 32 read-only n 0x0 0x0 RTC_BUSY pending RTC write 0 1 read-only WCO_OK Indicates that output has transitioned. 2 3 read-only TICKS 128Hz tick counter 0x40 32 read-only n 0x0 0x0 CNT128HZ 128Hz counter (msb=2Hz) When SECONDS is written this field will be reset. 0 6 read-only TRIM Trim Register 0xFF00 32 read-write n 0x0 0x0 TRIM WCO trim 0 6 read-write CPUSS CPU subsystem (CPUSS) CPUSS 0x0 0x0 0x10000 registers n ioss_interrupts_gpio_0 GPIO Port Interrupt #0 0 ioss_interrupts_gpio_1 GPIO Port Interrupt #1 1 ioss_interrupts_gpio_2 GPIO Port Interrupt #2 2 ioss_interrupts_gpio_3 GPIO Port Interrupt #3 3 ioss_interrupts_gpio_4 GPIO Port Interrupt #4 4 ioss_interrupts_gpio_5 GPIO Port Interrupt #5 5 ioss_interrupts_gpio_6 GPIO Port Interrupt #6 6 ioss_interrupts_gpio_7 GPIO Port Interrupt #7 7 ioss_interrupts_gpio_8 GPIO Port Interrupt #8 8 ioss_interrupts_gpio_9 GPIO Port Interrupt #9 9 ioss_interrupts_gpio_10 GPIO Port Interrupt #10 10 ioss_interrupts_gpio_11 GPIO Port Interrupt #11 11 ioss_interrupts_gpio_12 GPIO Port Interrupt #12 12 ioss_interrupts_gpio_13 GPIO Port Interrupt #13 13 ioss_interrupts_gpio_14 GPIO Port Interrupt #14 14 ioss_interrupt_gpio GPIO All Ports 15 ioss_interrupt_vdd GPIO Supply Detect Interrupt 16 lpcomp_interrupt Low Power Comparator Interrupt 17 scb_8_interrupt Serial Communication Block #8 (DeepSleep capable) 18 srss_interrupt_mcwdt_0 Multi Counter Watchdog Timer interrupt 19 srss_interrupt_mcwdt_1 Multi Counter Watchdog Timer interrupt 20 srss_interrupt_backup Backup domain interrupt 21 srss_interrupt Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) 22 cpuss_interrupts_ipc_0 CPUSS Inter Process Communication Interrupt #0 23 cpuss_interrupts_ipc_1 CPUSS Inter Process Communication Interrupt #1 24 cpuss_interrupts_ipc_2 CPUSS Inter Process Communication Interrupt #2 25 cpuss_interrupts_ipc_3 CPUSS Inter Process Communication Interrupt #3 26 cpuss_interrupts_ipc_4 CPUSS Inter Process Communication Interrupt #4 27 cpuss_interrupts_ipc_5 CPUSS Inter Process Communication Interrupt #5 28 cpuss_interrupts_ipc_6 CPUSS Inter Process Communication Interrupt #6 29 cpuss_interrupts_ipc_7 CPUSS Inter Process Communication Interrupt #7 30 cpuss_interrupts_ipc_8 CPUSS Inter Process Communication Interrupt #8 31 cpuss_interrupts_ipc_9 CPUSS Inter Process Communication Interrupt #9 32 cpuss_interrupts_ipc_10 CPUSS Inter Process Communication Interrupt #10 33 cpuss_interrupts_ipc_11 CPUSS Inter Process Communication Interrupt #11 34 cpuss_interrupts_ipc_12 CPUSS Inter Process Communication Interrupt #12 35 cpuss_interrupts_ipc_13 CPUSS Inter Process Communication Interrupt #13 36 cpuss_interrupts_ipc_14 CPUSS Inter Process Communication Interrupt #14 37 cpuss_interrupts_ipc_15 CPUSS Inter Process Communication Interrupt #15 38 scb_0_interrupt Serial Communication Block #0 39 scb_1_interrupt Serial Communication Block #1 40 scb_2_interrupt Serial Communication Block #2 41 scb_3_interrupt Serial Communication Block #3 42 scb_4_interrupt Serial Communication Block #4 43 scb_5_interrupt Serial Communication Block #5 44 scb_6_interrupt Serial Communication Block #6 45 scb_7_interrupt Serial Communication Block #7 46 scb_9_interrupt Serial Communication Block #9 47 scb_10_interrupt Serial Communication Block #10 48 scb_11_interrupt Serial Communication Block #11 49 scb_12_interrupt Serial Communication Block #12 50 csd_interrupt CSD (Capsense) interrupt 51 cpuss_interrupts_dmac_0 CPUSS DMAC, Channel #0 52 cpuss_interrupts_dmac_1 CPUSS DMAC, Channel #1 53 cpuss_interrupts_dmac_2 CPUSS DMAC, Channel #2 54 cpuss_interrupts_dmac_3 CPUSS DMAC, Channel #3 55 cpuss_interrupts_dw0_0 CPUSS DataWire #0, Channel #0 56 cpuss_interrupts_dw0_1 CPUSS DataWire #0, Channel #1 57 cpuss_interrupts_dw0_2 CPUSS DataWire #0, Channel #2 58 cpuss_interrupts_dw0_3 CPUSS DataWire #0, Channel #3 59 cpuss_interrupts_dw0_4 CPUSS DataWire #0, Channel #4 60 cpuss_interrupts_dw0_5 CPUSS DataWire #0, Channel #5 61 cpuss_interrupts_dw0_6 CPUSS DataWire #0, Channel #6 62 cpuss_interrupts_dw0_7 CPUSS DataWire #0, Channel #7 63 cpuss_interrupts_dw0_8 CPUSS DataWire #0, Channel #8 64 cpuss_interrupts_dw0_9 CPUSS DataWire #0, Channel #9 65 cpuss_interrupts_dw0_10 CPUSS DataWire #0, Channel #10 66 cpuss_interrupts_dw0_11 CPUSS DataWire #0, Channel #11 67 cpuss_interrupts_dw0_12 CPUSS DataWire #0, Channel #12 68 cpuss_interrupts_dw0_13 CPUSS DataWire #0, Channel #13 69 cpuss_interrupts_dw0_14 CPUSS DataWire #0, Channel #14 70 cpuss_interrupts_dw0_15 CPUSS DataWire #0, Channel #15 71 cpuss_interrupts_dw0_16 CPUSS DataWire #0, Channel #16 72 cpuss_interrupts_dw0_17 CPUSS DataWire #0, Channel #17 73 cpuss_interrupts_dw0_18 CPUSS DataWire #0, Channel #18 74 cpuss_interrupts_dw0_19 CPUSS DataWire #0, Channel #19 75 cpuss_interrupts_dw0_20 CPUSS DataWire #0, Channel #20 76 cpuss_interrupts_dw0_21 CPUSS DataWire #0, Channel #21 77 cpuss_interrupts_dw0_22 CPUSS DataWire #0, Channel #22 78 cpuss_interrupts_dw0_23 CPUSS DataWire #0, Channel #23 79 cpuss_interrupts_dw0_24 CPUSS DataWire #0, Channel #24 80 cpuss_interrupts_dw0_25 CPUSS DataWire #0, Channel #25 81 cpuss_interrupts_dw0_26 CPUSS DataWire #0, Channel #26 82 cpuss_interrupts_dw0_27 CPUSS DataWire #0, Channel #27 83 cpuss_interrupts_dw0_28 CPUSS DataWire #0, Channel #28 84 cpuss_interrupts_dw1_0 CPUSS DataWire #1, Channel #0 85 cpuss_interrupts_dw1_1 CPUSS DataWire #1, Channel #1 86 cpuss_interrupts_dw1_2 CPUSS DataWire #1, Channel #2 87 cpuss_interrupts_dw1_3 CPUSS DataWire #1, Channel #3 88 cpuss_interrupts_dw1_4 CPUSS DataWire #1, Channel #4 89 cpuss_interrupts_dw1_5 CPUSS DataWire #1, Channel #5 90 cpuss_interrupts_dw1_6 CPUSS DataWire #1, Channel #6 91 cpuss_interrupts_dw1_7 CPUSS DataWire #1, Channel #7 92 cpuss_interrupts_dw1_8 CPUSS DataWire #1, Channel #8 93 cpuss_interrupts_dw1_9 CPUSS DataWire #1, Channel #9 94 cpuss_interrupts_dw1_10 CPUSS DataWire #1, Channel #10 95 cpuss_interrupts_dw1_11 CPUSS DataWire #1, Channel #11 96 cpuss_interrupts_dw1_12 CPUSS DataWire #1, Channel #12 97 cpuss_interrupts_dw1_13 CPUSS DataWire #1, Channel #13 98 cpuss_interrupts_dw1_14 CPUSS DataWire #1, Channel #14 99 cpuss_interrupts_dw1_15 CPUSS DataWire #1, Channel #15 100 cpuss_interrupts_dw1_16 CPUSS DataWire #1, Channel #16 101 cpuss_interrupts_dw1_17 CPUSS DataWire #1, Channel #17 102 cpuss_interrupts_dw1_18 CPUSS DataWire #1, Channel #18 103 cpuss_interrupts_dw1_19 CPUSS DataWire #1, Channel #19 104 cpuss_interrupts_dw1_20 CPUSS DataWire #1, Channel #20 105 cpuss_interrupts_dw1_21 CPUSS DataWire #1, Channel #21 106 cpuss_interrupts_dw1_22 CPUSS DataWire #1, Channel #22 107 cpuss_interrupts_dw1_23 CPUSS DataWire #1, Channel #23 108 cpuss_interrupts_dw1_24 CPUSS DataWire #1, Channel #24 109 cpuss_interrupts_dw1_25 CPUSS DataWire #1, Channel #25 110 cpuss_interrupts_dw1_26 CPUSS DataWire #1, Channel #26 111 cpuss_interrupts_dw1_27 CPUSS DataWire #1, Channel #27 112 cpuss_interrupts_dw1_28 CPUSS DataWire #1, Channel #28 113 cpuss_interrupts_fault_0 CPUSS Fault Structure Interrupt #0 114 cpuss_interrupts_fault_1 CPUSS Fault Structure Interrupt #1 115 cpuss_interrupt_crypto CRYPTO Accelerator Interrupt 116 cpuss_interrupt_fm FLASH Macro Interrupt 117 cpuss_interrupts_cm4_fp Floating Point operation fault 118 cpuss_interrupts_cm0_cti_0 CM0+ CTI #0 119 cpuss_interrupts_cm0_cti_1 CM0+ CTI #1 120 cpuss_interrupts_cm4_cti_0 CM4 CTI #0 121 cpuss_interrupts_cm4_cti_1 CM4 CTI #1 122 tcpwm_0_interrupts_0 TCPWM #0, Counter #0 123 tcpwm_0_interrupts_1 TCPWM #0, Counter #1 124 tcpwm_0_interrupts_2 TCPWM #0, Counter #2 125 tcpwm_0_interrupts_3 TCPWM #0, Counter #3 126 tcpwm_0_interrupts_4 TCPWM #0, Counter #4 127 tcpwm_0_interrupts_5 TCPWM #0, Counter #5 128 tcpwm_0_interrupts_6 TCPWM #0, Counter #6 129 tcpwm_0_interrupts_7 TCPWM #0, Counter #7 130 tcpwm_1_interrupts_0 TCPWM #1, Counter #0 131 tcpwm_1_interrupts_1 TCPWM #1, Counter #1 132 tcpwm_1_interrupts_2 TCPWM #1, Counter #2 133 tcpwm_1_interrupts_3 TCPWM #1, Counter #3 134 tcpwm_1_interrupts_4 TCPWM #1, Counter #4 135 tcpwm_1_interrupts_5 TCPWM #1, Counter #5 136 tcpwm_1_interrupts_6 TCPWM #1, Counter #6 137 tcpwm_1_interrupts_7 TCPWM #1, Counter #7 138 tcpwm_1_interrupts_8 TCPWM #1, Counter #8 139 tcpwm_1_interrupts_9 TCPWM #1, Counter #9 140 tcpwm_1_interrupts_10 TCPWM #1, Counter #10 141 tcpwm_1_interrupts_11 TCPWM #1, Counter #11 142 tcpwm_1_interrupts_12 TCPWM #1, Counter #12 143 tcpwm_1_interrupts_13 TCPWM #1, Counter #13 144 tcpwm_1_interrupts_14 TCPWM #1, Counter #14 145 tcpwm_1_interrupts_15 TCPWM #1, Counter #15 146 tcpwm_1_interrupts_16 TCPWM #1, Counter #16 147 tcpwm_1_interrupts_17 TCPWM #1, Counter #17 148 tcpwm_1_interrupts_18 TCPWM #1, Counter #18 149 tcpwm_1_interrupts_19 TCPWM #1, Counter #19 150 tcpwm_1_interrupts_20 TCPWM #1, Counter #20 151 tcpwm_1_interrupts_21 TCPWM #1, Counter #21 152 tcpwm_1_interrupts_22 TCPWM #1, Counter #22 153 tcpwm_1_interrupts_23 TCPWM #1, Counter #23 154 pass_interrupt_sar SAR ADC interrupt 155 audioss_0_interrupt_i2s I2S0 Audio interrupt 156 audioss_0_interrupt_pdm PDM0/PCM0 Audio interrupt 157 audioss_1_interrupt_i2s I2S1 Audio interrupt 158 profile_interrupt Energy Profiler interrupt 159 smif_interrupt Serial Memory Interface interrupt 160 usb_interrupt_hi USB Interrupt 161 usb_interrupt_med USB Interrupt 162 usb_interrupt_lo USB Interrupt 163 sdhc_0_interrupt_wakeup SDIO wakeup interrupt for mxsdhc 164 sdhc_0_interrupt_general Consolidated interrupt for mxsdhc for everything else 165 sdhc_1_interrupt_wakeup EEMC wakeup interrupt for mxsdhc, not used 166 sdhc_1_interrupt_general Consolidated interrupt for mxsdhc for everything else 167 AP_CTL Access port control 0x1414 32 read-write n 0x0 0x0 CM0_DISABLE Disables the CM0 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. 16 17 read-write CM0_ENABLE Enables the CM0 AP interface: '0': Disabled. '1': Enabled. 0 1 read-write CM4_DISABLE Disables the CM4 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. 17 18 read-write CM4_ENABLE Enables the CM4 AP interface: '0': Disabled. '1': Enabled. 1 2 read-write SYS_DISABLE Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. 18 19 read-write SYS_ENABLE Enables the system AP interface: '0': Disabled. '1': Enabled. 2 3 read-write BUFF_CTL Buffer control 0x1500 32 read-write n 0x0 0x0 WRITE_BUFF Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. 0 1 read-write CAL_SUP_CLR Calibration support clear and reset 0x1804 32 read-write n 0x0 0x0 DATA Read side effect: when read all bits are cleared, write 1 to clear a specific bit Note: no exception for the debug host, it also causes the read side effect 0 32 read-write CAL_SUP_SET Calibration support set and read 0x1800 32 read-write n 0x0 0x0 DATA Read without side effect, write 1 to set 0 32 read-write CM0_CLOCK_CTL CM0+ clock control 0x1008 32 read-write n 0x0 0x0 PERI_INT_DIV Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. 24 32 read-write SLOW_INT_DIV Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write CM0_CTL CM0+ control 0x1000 32 read-write n 0x0 0x0 ENABLED Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value see CPU user manual for more details). 1 2 read-write SLV_STALL Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. 0 1 read-write VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only CM0_INT0_STATUS CM0+ interrupt 0 status 0x1100 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 0. Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. 0 10 read-only SYSTEM_INT_VALID Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. 31 32 read-only CM0_INT1_STATUS CM0+ interrupt 1 status 0x1104 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM0_INT2_STATUS CM0+ interrupt 2 status 0x1108 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM0_INT3_STATUS CM0+ interrupt 3 status 0x110C 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM0_INT4_STATUS CM0+ interrupt 4 status 0x1110 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM0_INT5_STATUS CM0+ interrupt 5 status 0x1114 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM0_INT6_STATUS CM0+ interrupt 6 status 0x1118 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM0_INT7_STATUS CM0+ interrupt 7 status 0x111C 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM0_NMI_CTL0 CM0+ NMI control 0x1140 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM0_NMI_CTL1 CM0+ NMI control 0x1144 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM0_NMI_CTL2 CM0+ NMI control 0x1148 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM0_NMI_CTL3 CM0+ NMI control 0x114C 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM0_PC0_HANDLER CM0+ protection context 0 handler 0x2040 32 read-write n 0x0 0x0 ADDR Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. 0 32 read-write CM0_PC1_HANDLER CM0+ protection context 1 handler 0x2044 32 read-write n 0x0 0x0 ADDR Address of the protection context 1 handler. 0 32 read-write CM0_PC2_HANDLER CM0+ protection context 2 handler 0x2048 32 read-write n 0x0 0x0 ADDR Address of the protection context 2 handler. 0 32 read-write CM0_PC3_HANDLER CM0+ protection context 3 handler 0x204C 32 read-write n 0x0 0x0 ADDR Address of the protection context 3 handler. 0 32 read-write CM0_PC_CTL CM0+ protection context control 0x2000 32 read-write n 0x0 0x0 VALID Valid fields for the protection context handler CM0_PCi_HANDLER registers: Bit 0: Valid field for CM0_PC0_HANDLER. Bit 1: Valid field for CM0_PC1_HANDLER. Bit 2: Valid field for CM0_PC2_HANDLER. Bit 3: Valid field for CM0_PC3_HANDLER. 0 4 read-write CM0_STATUS CM0+ status 0x1004 32 read-only n 0x0 0x0 SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. 1 2 read-only SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. 0 1 read-only CM0_SYSTEM_INT_CTL0 CM0+ system interrupt control 0x8000 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1 CM0+ system interrupt control 0x8004 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL10 CM0+ system interrupt control 0x8028 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL100 CM0+ system interrupt control 0x8190 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1000 CM0+ system interrupt control 0x8FA0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1001 CM0+ system interrupt control 0x8FA4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1002 CM0+ system interrupt control 0x8FA8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1003 CM0+ system interrupt control 0x8FAC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1004 CM0+ system interrupt control 0x8FB0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1005 CM0+ system interrupt control 0x8FB4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1006 CM0+ system interrupt control 0x8FB8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1007 CM0+ system interrupt control 0x8FBC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1008 CM0+ system interrupt control 0x8FC0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1009 CM0+ system interrupt control 0x8FC4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL101 CM0+ system interrupt control 0x8194 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1010 CM0+ system interrupt control 0x8FC8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1011 CM0+ system interrupt control 0x8FCC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1012 CM0+ system interrupt control 0x8FD0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1013 CM0+ system interrupt control 0x8FD4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1014 CM0+ system interrupt control 0x8FD8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1015 CM0+ system interrupt control 0x8FDC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1016 CM0+ system interrupt control 0x8FE0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1017 CM0+ system interrupt control 0x8FE4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1018 CM0+ system interrupt control 0x8FE8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1019 CM0+ system interrupt control 0x8FEC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL102 CM0+ system interrupt control 0x8198 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1020 CM0+ system interrupt control 0x8FF0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1021 CM0+ system interrupt control 0x8FF4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL1022 CM0+ system interrupt control 0x8FF8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL103 CM0+ system interrupt control 0x819C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL104 CM0+ system interrupt control 0x81A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL105 CM0+ system interrupt control 0x81A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL106 CM0+ system interrupt control 0x81A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL107 CM0+ system interrupt control 0x81AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL108 CM0+ system interrupt control 0x81B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL109 CM0+ system interrupt control 0x81B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL11 CM0+ system interrupt control 0x802C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL110 CM0+ system interrupt control 0x81B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL111 CM0+ system interrupt control 0x81BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL112 CM0+ system interrupt control 0x81C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL113 CM0+ system interrupt control 0x81C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL114 CM0+ system interrupt control 0x81C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL115 CM0+ system interrupt control 0x81CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL116 CM0+ system interrupt control 0x81D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL117 CM0+ system interrupt control 0x81D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL118 CM0+ system interrupt control 0x81D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL119 CM0+ system interrupt control 0x81DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL12 CM0+ system interrupt control 0x8030 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL120 CM0+ system interrupt control 0x81E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL121 CM0+ system interrupt control 0x81E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL122 CM0+ system interrupt control 0x81E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL123 CM0+ system interrupt control 0x81EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL124 CM0+ system interrupt control 0x81F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL125 CM0+ system interrupt control 0x81F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL126 CM0+ system interrupt control 0x81F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL127 CM0+ system interrupt control 0x81FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL128 CM0+ system interrupt control 0x8200 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL129 CM0+ system interrupt control 0x8204 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL13 CM0+ system interrupt control 0x8034 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL130 CM0+ system interrupt control 0x8208 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL131 CM0+ system interrupt control 0x820C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL132 CM0+ system interrupt control 0x8210 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL133 CM0+ system interrupt control 0x8214 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL134 CM0+ system interrupt control 0x8218 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL135 CM0+ system interrupt control 0x821C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL136 CM0+ system interrupt control 0x8220 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL137 CM0+ system interrupt control 0x8224 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL138 CM0+ system interrupt control 0x8228 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL139 CM0+ system interrupt control 0x822C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL14 CM0+ system interrupt control 0x8038 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL140 CM0+ system interrupt control 0x8230 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL141 CM0+ system interrupt control 0x8234 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL142 CM0+ system interrupt control 0x8238 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL143 CM0+ system interrupt control 0x823C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL144 CM0+ system interrupt control 0x8240 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL145 CM0+ system interrupt control 0x8244 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL146 CM0+ system interrupt control 0x8248 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL147 CM0+ system interrupt control 0x824C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL148 CM0+ system interrupt control 0x8250 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL149 CM0+ system interrupt control 0x8254 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL15 CM0+ system interrupt control 0x803C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL150 CM0+ system interrupt control 0x8258 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL151 CM0+ system interrupt control 0x825C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL152 CM0+ system interrupt control 0x8260 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL153 CM0+ system interrupt control 0x8264 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL154 CM0+ system interrupt control 0x8268 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL155 CM0+ system interrupt control 0x826C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL156 CM0+ system interrupt control 0x8270 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL157 CM0+ system interrupt control 0x8274 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL158 CM0+ system interrupt control 0x8278 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL159 CM0+ system interrupt control 0x827C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL16 CM0+ system interrupt control 0x8040 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL160 CM0+ system interrupt control 0x8280 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL161 CM0+ system interrupt control 0x8284 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL162 CM0+ system interrupt control 0x8288 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL163 CM0+ system interrupt control 0x828C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL164 CM0+ system interrupt control 0x8290 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL165 CM0+ system interrupt control 0x8294 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL166 CM0+ system interrupt control 0x8298 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL167 CM0+ system interrupt control 0x829C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL168 CM0+ system interrupt control 0x82A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL169 CM0+ system interrupt control 0x82A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL17 CM0+ system interrupt control 0x8044 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL170 CM0+ system interrupt control 0x82A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL171 CM0+ system interrupt control 0x82AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL172 CM0+ system interrupt control 0x82B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL173 CM0+ system interrupt control 0x82B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL174 CM0+ system interrupt control 0x82B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL175 CM0+ system interrupt control 0x82BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL176 CM0+ system interrupt control 0x82C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL177 CM0+ system interrupt control 0x82C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL178 CM0+ system interrupt control 0x82C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL179 CM0+ system interrupt control 0x82CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL18 CM0+ system interrupt control 0x8048 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL180 CM0+ system interrupt control 0x82D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL181 CM0+ system interrupt control 0x82D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL182 CM0+ system interrupt control 0x82D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL183 CM0+ system interrupt control 0x82DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL184 CM0+ system interrupt control 0x82E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL185 CM0+ system interrupt control 0x82E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL186 CM0+ system interrupt control 0x82E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL187 CM0+ system interrupt control 0x82EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL188 CM0+ system interrupt control 0x82F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL189 CM0+ system interrupt control 0x82F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL19 CM0+ system interrupt control 0x804C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL190 CM0+ system interrupt control 0x82F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL191 CM0+ system interrupt control 0x82FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL192 CM0+ system interrupt control 0x8300 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL193 CM0+ system interrupt control 0x8304 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL194 CM0+ system interrupt control 0x8308 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL195 CM0+ system interrupt control 0x830C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL196 CM0+ system interrupt control 0x8310 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL197 CM0+ system interrupt control 0x8314 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL198 CM0+ system interrupt control 0x8318 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL199 CM0+ system interrupt control 0x831C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL2 CM0+ system interrupt control 0x8008 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL20 CM0+ system interrupt control 0x8050 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL200 CM0+ system interrupt control 0x8320 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL201 CM0+ system interrupt control 0x8324 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL202 CM0+ system interrupt control 0x8328 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL203 CM0+ system interrupt control 0x832C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL204 CM0+ system interrupt control 0x8330 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL205 CM0+ system interrupt control 0x8334 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL206 CM0+ system interrupt control 0x8338 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL207 CM0+ system interrupt control 0x833C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL208 CM0+ system interrupt control 0x8340 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL209 CM0+ system interrupt control 0x8344 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL21 CM0+ system interrupt control 0x8054 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL210 CM0+ system interrupt control 0x8348 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL211 CM0+ system interrupt control 0x834C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL212 CM0+ system interrupt control 0x8350 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL213 CM0+ system interrupt control 0x8354 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL214 CM0+ system interrupt control 0x8358 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL215 CM0+ system interrupt control 0x835C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL216 CM0+ system interrupt control 0x8360 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL217 CM0+ system interrupt control 0x8364 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL218 CM0+ system interrupt control 0x8368 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL219 CM0+ system interrupt control 0x836C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL22 CM0+ system interrupt control 0x8058 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL220 CM0+ system interrupt control 0x8370 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL221 CM0+ system interrupt control 0x8374 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL222 CM0+ system interrupt control 0x8378 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL223 CM0+ system interrupt control 0x837C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL224 CM0+ system interrupt control 0x8380 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL225 CM0+ system interrupt control 0x8384 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL226 CM0+ system interrupt control 0x8388 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL227 CM0+ system interrupt control 0x838C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL228 CM0+ system interrupt control 0x8390 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL229 CM0+ system interrupt control 0x8394 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL23 CM0+ system interrupt control 0x805C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL230 CM0+ system interrupt control 0x8398 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL231 CM0+ system interrupt control 0x839C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL232 CM0+ system interrupt control 0x83A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL233 CM0+ system interrupt control 0x83A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL234 CM0+ system interrupt control 0x83A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL235 CM0+ system interrupt control 0x83AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL236 CM0+ system interrupt control 0x83B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL237 CM0+ system interrupt control 0x83B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL238 CM0+ system interrupt control 0x83B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL239 CM0+ system interrupt control 0x83BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL24 CM0+ system interrupt control 0x8060 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL240 CM0+ system interrupt control 0x83C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL241 CM0+ system interrupt control 0x83C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL242 CM0+ system interrupt control 0x83C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL243 CM0+ system interrupt control 0x83CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL244 CM0+ system interrupt control 0x83D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL245 CM0+ system interrupt control 0x83D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL246 CM0+ system interrupt control 0x83D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL247 CM0+ system interrupt control 0x83DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL248 CM0+ system interrupt control 0x83E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL249 CM0+ system interrupt control 0x83E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL25 CM0+ system interrupt control 0x8064 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL250 CM0+ system interrupt control 0x83E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL251 CM0+ system interrupt control 0x83EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL252 CM0+ system interrupt control 0x83F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL253 CM0+ system interrupt control 0x83F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL254 CM0+ system interrupt control 0x83F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL255 CM0+ system interrupt control 0x83FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL256 CM0+ system interrupt control 0x8400 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL257 CM0+ system interrupt control 0x8404 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL258 CM0+ system interrupt control 0x8408 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL259 CM0+ system interrupt control 0x840C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL26 CM0+ system interrupt control 0x8068 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL260 CM0+ system interrupt control 0x8410 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL261 CM0+ system interrupt control 0x8414 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL262 CM0+ system interrupt control 0x8418 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL263 CM0+ system interrupt control 0x841C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL264 CM0+ system interrupt control 0x8420 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL265 CM0+ system interrupt control 0x8424 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL266 CM0+ system interrupt control 0x8428 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL267 CM0+ system interrupt control 0x842C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL268 CM0+ system interrupt control 0x8430 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL269 CM0+ system interrupt control 0x8434 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL27 CM0+ system interrupt control 0x806C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL270 CM0+ system interrupt control 0x8438 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL271 CM0+ system interrupt control 0x843C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL272 CM0+ system interrupt control 0x8440 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL273 CM0+ system interrupt control 0x8444 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL274 CM0+ system interrupt control 0x8448 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL275 CM0+ system interrupt control 0x844C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL276 CM0+ system interrupt control 0x8450 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL277 CM0+ system interrupt control 0x8454 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL278 CM0+ system interrupt control 0x8458 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL279 CM0+ system interrupt control 0x845C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL28 CM0+ system interrupt control 0x8070 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL280 CM0+ system interrupt control 0x8460 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL281 CM0+ system interrupt control 0x8464 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL282 CM0+ system interrupt control 0x8468 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL283 CM0+ system interrupt control 0x846C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL284 CM0+ system interrupt control 0x8470 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL285 CM0+ system interrupt control 0x8474 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL286 CM0+ system interrupt control 0x8478 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL287 CM0+ system interrupt control 0x847C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL288 CM0+ system interrupt control 0x8480 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL289 CM0+ system interrupt control 0x8484 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL29 CM0+ system interrupt control 0x8074 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL290 CM0+ system interrupt control 0x8488 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL291 CM0+ system interrupt control 0x848C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL292 CM0+ system interrupt control 0x8490 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL293 CM0+ system interrupt control 0x8494 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL294 CM0+ system interrupt control 0x8498 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL295 CM0+ system interrupt control 0x849C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL296 CM0+ system interrupt control 0x84A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL297 CM0+ system interrupt control 0x84A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL298 CM0+ system interrupt control 0x84A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL299 CM0+ system interrupt control 0x84AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL3 CM0+ system interrupt control 0x800C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL30 CM0+ system interrupt control 0x8078 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL300 CM0+ system interrupt control 0x84B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL301 CM0+ system interrupt control 0x84B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL302 CM0+ system interrupt control 0x84B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL303 CM0+ system interrupt control 0x84BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL304 CM0+ system interrupt control 0x84C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL305 CM0+ system interrupt control 0x84C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL306 CM0+ system interrupt control 0x84C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL307 CM0+ system interrupt control 0x84CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL308 CM0+ system interrupt control 0x84D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL309 CM0+ system interrupt control 0x84D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL31 CM0+ system interrupt control 0x807C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL310 CM0+ system interrupt control 0x84D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL311 CM0+ system interrupt control 0x84DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL312 CM0+ system interrupt control 0x84E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL313 CM0+ system interrupt control 0x84E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL314 CM0+ system interrupt control 0x84E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL315 CM0+ system interrupt control 0x84EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL316 CM0+ system interrupt control 0x84F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL317 CM0+ system interrupt control 0x84F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL318 CM0+ system interrupt control 0x84F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL319 CM0+ system interrupt control 0x84FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL32 CM0+ system interrupt control 0x8080 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL320 CM0+ system interrupt control 0x8500 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL321 CM0+ system interrupt control 0x8504 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL322 CM0+ system interrupt control 0x8508 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL323 CM0+ system interrupt control 0x850C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL324 CM0+ system interrupt control 0x8510 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL325 CM0+ system interrupt control 0x8514 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL326 CM0+ system interrupt control 0x8518 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL327 CM0+ system interrupt control 0x851C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL328 CM0+ system interrupt control 0x8520 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL329 CM0+ system interrupt control 0x8524 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL33 CM0+ system interrupt control 0x8084 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL330 CM0+ system interrupt control 0x8528 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL331 CM0+ system interrupt control 0x852C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL332 CM0+ system interrupt control 0x8530 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL333 CM0+ system interrupt control 0x8534 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL334 CM0+ system interrupt control 0x8538 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL335 CM0+ system interrupt control 0x853C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL336 CM0+ system interrupt control 0x8540 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL337 CM0+ system interrupt control 0x8544 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL338 CM0+ system interrupt control 0x8548 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL339 CM0+ system interrupt control 0x854C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL34 CM0+ system interrupt control 0x8088 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL340 CM0+ system interrupt control 0x8550 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL341 CM0+ system interrupt control 0x8554 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL342 CM0+ system interrupt control 0x8558 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL343 CM0+ system interrupt control 0x855C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL344 CM0+ system interrupt control 0x8560 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL345 CM0+ system interrupt control 0x8564 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL346 CM0+ system interrupt control 0x8568 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL347 CM0+ system interrupt control 0x856C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL348 CM0+ system interrupt control 0x8570 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL349 CM0+ system interrupt control 0x8574 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL35 CM0+ system interrupt control 0x808C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL350 CM0+ system interrupt control 0x8578 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL351 CM0+ system interrupt control 0x857C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL352 CM0+ system interrupt control 0x8580 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL353 CM0+ system interrupt control 0x8584 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL354 CM0+ system interrupt control 0x8588 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL355 CM0+ system interrupt control 0x858C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL356 CM0+ system interrupt control 0x8590 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL357 CM0+ system interrupt control 0x8594 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL358 CM0+ system interrupt control 0x8598 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL359 CM0+ system interrupt control 0x859C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL36 CM0+ system interrupt control 0x8090 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL360 CM0+ system interrupt control 0x85A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL361 CM0+ system interrupt control 0x85A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL362 CM0+ system interrupt control 0x85A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL363 CM0+ system interrupt control 0x85AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL364 CM0+ system interrupt control 0x85B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL365 CM0+ system interrupt control 0x85B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL366 CM0+ system interrupt control 0x85B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL367 CM0+ system interrupt control 0x85BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL368 CM0+ system interrupt control 0x85C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL369 CM0+ system interrupt control 0x85C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL37 CM0+ system interrupt control 0x8094 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL370 CM0+ system interrupt control 0x85C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL371 CM0+ system interrupt control 0x85CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL372 CM0+ system interrupt control 0x85D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL373 CM0+ system interrupt control 0x85D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL374 CM0+ system interrupt control 0x85D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL375 CM0+ system interrupt control 0x85DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL376 CM0+ system interrupt control 0x85E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL377 CM0+ system interrupt control 0x85E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL378 CM0+ system interrupt control 0x85E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL379 CM0+ system interrupt control 0x85EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL38 CM0+ system interrupt control 0x8098 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL380 CM0+ system interrupt control 0x85F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL381 CM0+ system interrupt control 0x85F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL382 CM0+ system interrupt control 0x85F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL383 CM0+ system interrupt control 0x85FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL384 CM0+ system interrupt control 0x8600 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL385 CM0+ system interrupt control 0x8604 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL386 CM0+ system interrupt control 0x8608 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL387 CM0+ system interrupt control 0x860C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL388 CM0+ system interrupt control 0x8610 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL389 CM0+ system interrupt control 0x8614 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL39 CM0+ system interrupt control 0x809C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL390 CM0+ system interrupt control 0x8618 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL391 CM0+ system interrupt control 0x861C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL392 CM0+ system interrupt control 0x8620 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL393 CM0+ system interrupt control 0x8624 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL394 CM0+ system interrupt control 0x8628 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL395 CM0+ system interrupt control 0x862C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL396 CM0+ system interrupt control 0x8630 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL397 CM0+ system interrupt control 0x8634 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL398 CM0+ system interrupt control 0x8638 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL399 CM0+ system interrupt control 0x863C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL4 CM0+ system interrupt control 0x8010 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL40 CM0+ system interrupt control 0x80A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL400 CM0+ system interrupt control 0x8640 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL401 CM0+ system interrupt control 0x8644 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL402 CM0+ system interrupt control 0x8648 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL403 CM0+ system interrupt control 0x864C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL404 CM0+ system interrupt control 0x8650 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL405 CM0+ system interrupt control 0x8654 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL406 CM0+ system interrupt control 0x8658 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL407 CM0+ system interrupt control 0x865C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL408 CM0+ system interrupt control 0x8660 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL409 CM0+ system interrupt control 0x8664 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL41 CM0+ system interrupt control 0x80A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL410 CM0+ system interrupt control 0x8668 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL411 CM0+ system interrupt control 0x866C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL412 CM0+ system interrupt control 0x8670 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL413 CM0+ system interrupt control 0x8674 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL414 CM0+ system interrupt control 0x8678 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL415 CM0+ system interrupt control 0x867C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL416 CM0+ system interrupt control 0x8680 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL417 CM0+ system interrupt control 0x8684 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL418 CM0+ system interrupt control 0x8688 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL419 CM0+ system interrupt control 0x868C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL42 CM0+ system interrupt control 0x80A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL420 CM0+ system interrupt control 0x8690 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL421 CM0+ system interrupt control 0x8694 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL422 CM0+ system interrupt control 0x8698 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL423 CM0+ system interrupt control 0x869C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL424 CM0+ system interrupt control 0x86A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL425 CM0+ system interrupt control 0x86A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL426 CM0+ system interrupt control 0x86A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL427 CM0+ system interrupt control 0x86AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL428 CM0+ system interrupt control 0x86B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL429 CM0+ system interrupt control 0x86B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL43 CM0+ system interrupt control 0x80AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL430 CM0+ system interrupt control 0x86B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL431 CM0+ system interrupt control 0x86BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL432 CM0+ system interrupt control 0x86C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL433 CM0+ system interrupt control 0x86C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL434 CM0+ system interrupt control 0x86C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL435 CM0+ system interrupt control 0x86CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL436 CM0+ system interrupt control 0x86D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL437 CM0+ system interrupt control 0x86D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL438 CM0+ system interrupt control 0x86D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL439 CM0+ system interrupt control 0x86DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL44 CM0+ system interrupt control 0x80B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL440 CM0+ system interrupt control 0x86E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL441 CM0+ system interrupt control 0x86E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL442 CM0+ system interrupt control 0x86E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL443 CM0+ system interrupt control 0x86EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL444 CM0+ system interrupt control 0x86F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL445 CM0+ system interrupt control 0x86F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL446 CM0+ system interrupt control 0x86F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL447 CM0+ system interrupt control 0x86FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL448 CM0+ system interrupt control 0x8700 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL449 CM0+ system interrupt control 0x8704 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL45 CM0+ system interrupt control 0x80B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL450 CM0+ system interrupt control 0x8708 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL451 CM0+ system interrupt control 0x870C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL452 CM0+ system interrupt control 0x8710 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL453 CM0+ system interrupt control 0x8714 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL454 CM0+ system interrupt control 0x8718 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL455 CM0+ system interrupt control 0x871C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL456 CM0+ system interrupt control 0x8720 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL457 CM0+ system interrupt control 0x8724 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL458 CM0+ system interrupt control 0x8728 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL459 CM0+ system interrupt control 0x872C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL46 CM0+ system interrupt control 0x80B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL460 CM0+ system interrupt control 0x8730 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL461 CM0+ system interrupt control 0x8734 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL462 CM0+ system interrupt control 0x8738 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL463 CM0+ system interrupt control 0x873C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL464 CM0+ system interrupt control 0x8740 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL465 CM0+ system interrupt control 0x8744 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL466 CM0+ system interrupt control 0x8748 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL467 CM0+ system interrupt control 0x874C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL468 CM0+ system interrupt control 0x8750 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL469 CM0+ system interrupt control 0x8754 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL47 CM0+ system interrupt control 0x80BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL470 CM0+ system interrupt control 0x8758 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL471 CM0+ system interrupt control 0x875C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL472 CM0+ system interrupt control 0x8760 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL473 CM0+ system interrupt control 0x8764 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL474 CM0+ system interrupt control 0x8768 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL475 CM0+ system interrupt control 0x876C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL476 CM0+ system interrupt control 0x8770 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL477 CM0+ system interrupt control 0x8774 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL478 CM0+ system interrupt control 0x8778 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL479 CM0+ system interrupt control 0x877C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL48 CM0+ system interrupt control 0x80C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL480 CM0+ system interrupt control 0x8780 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL481 CM0+ system interrupt control 0x8784 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL482 CM0+ system interrupt control 0x8788 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL483 CM0+ system interrupt control 0x878C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL484 CM0+ system interrupt control 0x8790 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL485 CM0+ system interrupt control 0x8794 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL486 CM0+ system interrupt control 0x8798 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL487 CM0+ system interrupt control 0x879C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL488 CM0+ system interrupt control 0x87A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL489 CM0+ system interrupt control 0x87A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL49 CM0+ system interrupt control 0x80C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL490 CM0+ system interrupt control 0x87A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL491 CM0+ system interrupt control 0x87AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL492 CM0+ system interrupt control 0x87B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL493 CM0+ system interrupt control 0x87B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL494 CM0+ system interrupt control 0x87B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL495 CM0+ system interrupt control 0x87BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL496 CM0+ system interrupt control 0x87C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL497 CM0+ system interrupt control 0x87C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL498 CM0+ system interrupt control 0x87C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL499 CM0+ system interrupt control 0x87CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL5 CM0+ system interrupt control 0x8014 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL50 CM0+ system interrupt control 0x80C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL500 CM0+ system interrupt control 0x87D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL501 CM0+ system interrupt control 0x87D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL502 CM0+ system interrupt control 0x87D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL503 CM0+ system interrupt control 0x87DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL504 CM0+ system interrupt control 0x87E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL505 CM0+ system interrupt control 0x87E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL506 CM0+ system interrupt control 0x87E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL507 CM0+ system interrupt control 0x87EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL508 CM0+ system interrupt control 0x87F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL509 CM0+ system interrupt control 0x87F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL51 CM0+ system interrupt control 0x80CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL510 CM0+ system interrupt control 0x87F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL511 CM0+ system interrupt control 0x87FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL512 CM0+ system interrupt control 0x8800 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL513 CM0+ system interrupt control 0x8804 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL514 CM0+ system interrupt control 0x8808 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL515 CM0+ system interrupt control 0x880C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL516 CM0+ system interrupt control 0x8810 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL517 CM0+ system interrupt control 0x8814 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL518 CM0+ system interrupt control 0x8818 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL519 CM0+ system interrupt control 0x881C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL52 CM0+ system interrupt control 0x80D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL520 CM0+ system interrupt control 0x8820 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL521 CM0+ system interrupt control 0x8824 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL522 CM0+ system interrupt control 0x8828 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL523 CM0+ system interrupt control 0x882C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL524 CM0+ system interrupt control 0x8830 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL525 CM0+ system interrupt control 0x8834 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL526 CM0+ system interrupt control 0x8838 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL527 CM0+ system interrupt control 0x883C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL528 CM0+ system interrupt control 0x8840 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL529 CM0+ system interrupt control 0x8844 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL53 CM0+ system interrupt control 0x80D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL530 CM0+ system interrupt control 0x8848 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL531 CM0+ system interrupt control 0x884C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL532 CM0+ system interrupt control 0x8850 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL533 CM0+ system interrupt control 0x8854 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL534 CM0+ system interrupt control 0x8858 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL535 CM0+ system interrupt control 0x885C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL536 CM0+ system interrupt control 0x8860 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL537 CM0+ system interrupt control 0x8864 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL538 CM0+ system interrupt control 0x8868 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL539 CM0+ system interrupt control 0x886C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL54 CM0+ system interrupt control 0x80D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL540 CM0+ system interrupt control 0x8870 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL541 CM0+ system interrupt control 0x8874 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL542 CM0+ system interrupt control 0x8878 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL543 CM0+ system interrupt control 0x887C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL544 CM0+ system interrupt control 0x8880 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL545 CM0+ system interrupt control 0x8884 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL546 CM0+ system interrupt control 0x8888 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL547 CM0+ system interrupt control 0x888C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL548 CM0+ system interrupt control 0x8890 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL549 CM0+ system interrupt control 0x8894 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL55 CM0+ system interrupt control 0x80DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL550 CM0+ system interrupt control 0x8898 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL551 CM0+ system interrupt control 0x889C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL552 CM0+ system interrupt control 0x88A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL553 CM0+ system interrupt control 0x88A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL554 CM0+ system interrupt control 0x88A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL555 CM0+ system interrupt control 0x88AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL556 CM0+ system interrupt control 0x88B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL557 CM0+ system interrupt control 0x88B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL558 CM0+ system interrupt control 0x88B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL559 CM0+ system interrupt control 0x88BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL56 CM0+ system interrupt control 0x80E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL560 CM0+ system interrupt control 0x88C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL561 CM0+ system interrupt control 0x88C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL562 CM0+ system interrupt control 0x88C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL563 CM0+ system interrupt control 0x88CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL564 CM0+ system interrupt control 0x88D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL565 CM0+ system interrupt control 0x88D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL566 CM0+ system interrupt control 0x88D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL567 CM0+ system interrupt control 0x88DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL568 CM0+ system interrupt control 0x88E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL569 CM0+ system interrupt control 0x88E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL57 CM0+ system interrupt control 0x80E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL570 CM0+ system interrupt control 0x88E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL571 CM0+ system interrupt control 0x88EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL572 CM0+ system interrupt control 0x88F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL573 CM0+ system interrupt control 0x88F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL574 CM0+ system interrupt control 0x88F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL575 CM0+ system interrupt control 0x88FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL576 CM0+ system interrupt control 0x8900 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL577 CM0+ system interrupt control 0x8904 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL578 CM0+ system interrupt control 0x8908 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL579 CM0+ system interrupt control 0x890C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL58 CM0+ system interrupt control 0x80E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL580 CM0+ system interrupt control 0x8910 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL581 CM0+ system interrupt control 0x8914 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL582 CM0+ system interrupt control 0x8918 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL583 CM0+ system interrupt control 0x891C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL584 CM0+ system interrupt control 0x8920 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL585 CM0+ system interrupt control 0x8924 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL586 CM0+ system interrupt control 0x8928 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL587 CM0+ system interrupt control 0x892C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL588 CM0+ system interrupt control 0x8930 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL589 CM0+ system interrupt control 0x8934 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL59 CM0+ system interrupt control 0x80EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL590 CM0+ system interrupt control 0x8938 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL591 CM0+ system interrupt control 0x893C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL592 CM0+ system interrupt control 0x8940 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL593 CM0+ system interrupt control 0x8944 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL594 CM0+ system interrupt control 0x8948 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL595 CM0+ system interrupt control 0x894C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL596 CM0+ system interrupt control 0x8950 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL597 CM0+ system interrupt control 0x8954 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL598 CM0+ system interrupt control 0x8958 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL599 CM0+ system interrupt control 0x895C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL6 CM0+ system interrupt control 0x8018 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL60 CM0+ system interrupt control 0x80F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL600 CM0+ system interrupt control 0x8960 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL601 CM0+ system interrupt control 0x8964 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL602 CM0+ system interrupt control 0x8968 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL603 CM0+ system interrupt control 0x896C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL604 CM0+ system interrupt control 0x8970 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL605 CM0+ system interrupt control 0x8974 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL606 CM0+ system interrupt control 0x8978 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL607 CM0+ system interrupt control 0x897C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL608 CM0+ system interrupt control 0x8980 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL609 CM0+ system interrupt control 0x8984 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL61 CM0+ system interrupt control 0x80F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL610 CM0+ system interrupt control 0x8988 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL611 CM0+ system interrupt control 0x898C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL612 CM0+ system interrupt control 0x8990 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL613 CM0+ system interrupt control 0x8994 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL614 CM0+ system interrupt control 0x8998 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL615 CM0+ system interrupt control 0x899C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL616 CM0+ system interrupt control 0x89A0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL617 CM0+ system interrupt control 0x89A4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL618 CM0+ system interrupt control 0x89A8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL619 CM0+ system interrupt control 0x89AC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL62 CM0+ system interrupt control 0x80F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL620 CM0+ system interrupt control 0x89B0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL621 CM0+ system interrupt control 0x89B4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL622 CM0+ system interrupt control 0x89B8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL623 CM0+ system interrupt control 0x89BC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL624 CM0+ system interrupt control 0x89C0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL625 CM0+ system interrupt control 0x89C4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL626 CM0+ system interrupt control 0x89C8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL627 CM0+ system interrupt control 0x89CC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL628 CM0+ system interrupt control 0x89D0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL629 CM0+ system interrupt control 0x89D4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL63 CM0+ system interrupt control 0x80FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL630 CM0+ system interrupt control 0x89D8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL631 CM0+ system interrupt control 0x89DC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL632 CM0+ system interrupt control 0x89E0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL633 CM0+ system interrupt control 0x89E4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL634 CM0+ system interrupt control 0x89E8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL635 CM0+ system interrupt control 0x89EC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL636 CM0+ system interrupt control 0x89F0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL637 CM0+ system interrupt control 0x89F4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL638 CM0+ system interrupt control 0x89F8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL639 CM0+ system interrupt control 0x89FC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL64 CM0+ system interrupt control 0x8100 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL640 CM0+ system interrupt control 0x8A00 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL641 CM0+ system interrupt control 0x8A04 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL642 CM0+ system interrupt control 0x8A08 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL643 CM0+ system interrupt control 0x8A0C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL644 CM0+ system interrupt control 0x8A10 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL645 CM0+ system interrupt control 0x8A14 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL646 CM0+ system interrupt control 0x8A18 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL647 CM0+ system interrupt control 0x8A1C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL648 CM0+ system interrupt control 0x8A20 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL649 CM0+ system interrupt control 0x8A24 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL65 CM0+ system interrupt control 0x8104 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL650 CM0+ system interrupt control 0x8A28 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL651 CM0+ system interrupt control 0x8A2C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL652 CM0+ system interrupt control 0x8A30 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL653 CM0+ system interrupt control 0x8A34 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL654 CM0+ system interrupt control 0x8A38 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL655 CM0+ system interrupt control 0x8A3C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL656 CM0+ system interrupt control 0x8A40 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL657 CM0+ system interrupt control 0x8A44 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL658 CM0+ system interrupt control 0x8A48 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL659 CM0+ system interrupt control 0x8A4C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL66 CM0+ system interrupt control 0x8108 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL660 CM0+ system interrupt control 0x8A50 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL661 CM0+ system interrupt control 0x8A54 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL662 CM0+ system interrupt control 0x8A58 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL663 CM0+ system interrupt control 0x8A5C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL664 CM0+ system interrupt control 0x8A60 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL665 CM0+ system interrupt control 0x8A64 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL666 CM0+ system interrupt control 0x8A68 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL667 CM0+ system interrupt control 0x8A6C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL668 CM0+ system interrupt control 0x8A70 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL669 CM0+ system interrupt control 0x8A74 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL67 CM0+ system interrupt control 0x810C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL670 CM0+ system interrupt control 0x8A78 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL671 CM0+ system interrupt control 0x8A7C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL672 CM0+ system interrupt control 0x8A80 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL673 CM0+ system interrupt control 0x8A84 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL674 CM0+ system interrupt control 0x8A88 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL675 CM0+ system interrupt control 0x8A8C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL676 CM0+ system interrupt control 0x8A90 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL677 CM0+ system interrupt control 0x8A94 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL678 CM0+ system interrupt control 0x8A98 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL679 CM0+ system interrupt control 0x8A9C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL68 CM0+ system interrupt control 0x8110 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL680 CM0+ system interrupt control 0x8AA0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL681 CM0+ system interrupt control 0x8AA4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL682 CM0+ system interrupt control 0x8AA8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL683 CM0+ system interrupt control 0x8AAC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL684 CM0+ system interrupt control 0x8AB0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL685 CM0+ system interrupt control 0x8AB4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL686 CM0+ system interrupt control 0x8AB8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL687 CM0+ system interrupt control 0x8ABC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL688 CM0+ system interrupt control 0x8AC0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL689 CM0+ system interrupt control 0x8AC4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL69 CM0+ system interrupt control 0x8114 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL690 CM0+ system interrupt control 0x8AC8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL691 CM0+ system interrupt control 0x8ACC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL692 CM0+ system interrupt control 0x8AD0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL693 CM0+ system interrupt control 0x8AD4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL694 CM0+ system interrupt control 0x8AD8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL695 CM0+ system interrupt control 0x8ADC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL696 CM0+ system interrupt control 0x8AE0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL697 CM0+ system interrupt control 0x8AE4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL698 CM0+ system interrupt control 0x8AE8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL699 CM0+ system interrupt control 0x8AEC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL7 CM0+ system interrupt control 0x801C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL70 CM0+ system interrupt control 0x8118 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL700 CM0+ system interrupt control 0x8AF0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL701 CM0+ system interrupt control 0x8AF4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL702 CM0+ system interrupt control 0x8AF8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL703 CM0+ system interrupt control 0x8AFC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL704 CM0+ system interrupt control 0x8B00 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL705 CM0+ system interrupt control 0x8B04 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL706 CM0+ system interrupt control 0x8B08 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL707 CM0+ system interrupt control 0x8B0C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL708 CM0+ system interrupt control 0x8B10 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL709 CM0+ system interrupt control 0x8B14 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL71 CM0+ system interrupt control 0x811C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL710 CM0+ system interrupt control 0x8B18 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL711 CM0+ system interrupt control 0x8B1C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL712 CM0+ system interrupt control 0x8B20 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL713 CM0+ system interrupt control 0x8B24 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL714 CM0+ system interrupt control 0x8B28 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL715 CM0+ system interrupt control 0x8B2C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL716 CM0+ system interrupt control 0x8B30 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL717 CM0+ system interrupt control 0x8B34 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL718 CM0+ system interrupt control 0x8B38 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL719 CM0+ system interrupt control 0x8B3C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL72 CM0+ system interrupt control 0x8120 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL720 CM0+ system interrupt control 0x8B40 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL721 CM0+ system interrupt control 0x8B44 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL722 CM0+ system interrupt control 0x8B48 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL723 CM0+ system interrupt control 0x8B4C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL724 CM0+ system interrupt control 0x8B50 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL725 CM0+ system interrupt control 0x8B54 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL726 CM0+ system interrupt control 0x8B58 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL727 CM0+ system interrupt control 0x8B5C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL728 CM0+ system interrupt control 0x8B60 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL729 CM0+ system interrupt control 0x8B64 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL73 CM0+ system interrupt control 0x8124 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL730 CM0+ system interrupt control 0x8B68 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL731 CM0+ system interrupt control 0x8B6C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL732 CM0+ system interrupt control 0x8B70 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL733 CM0+ system interrupt control 0x8B74 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL734 CM0+ system interrupt control 0x8B78 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL735 CM0+ system interrupt control 0x8B7C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL736 CM0+ system interrupt control 0x8B80 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL737 CM0+ system interrupt control 0x8B84 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL738 CM0+ system interrupt control 0x8B88 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL739 CM0+ system interrupt control 0x8B8C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL74 CM0+ system interrupt control 0x8128 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL740 CM0+ system interrupt control 0x8B90 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL741 CM0+ system interrupt control 0x8B94 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL742 CM0+ system interrupt control 0x8B98 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL743 CM0+ system interrupt control 0x8B9C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL744 CM0+ system interrupt control 0x8BA0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL745 CM0+ system interrupt control 0x8BA4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL746 CM0+ system interrupt control 0x8BA8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL747 CM0+ system interrupt control 0x8BAC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL748 CM0+ system interrupt control 0x8BB0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL749 CM0+ system interrupt control 0x8BB4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL75 CM0+ system interrupt control 0x812C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL750 CM0+ system interrupt control 0x8BB8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL751 CM0+ system interrupt control 0x8BBC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL752 CM0+ system interrupt control 0x8BC0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL753 CM0+ system interrupt control 0x8BC4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL754 CM0+ system interrupt control 0x8BC8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL755 CM0+ system interrupt control 0x8BCC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL756 CM0+ system interrupt control 0x8BD0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL757 CM0+ system interrupt control 0x8BD4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL758 CM0+ system interrupt control 0x8BD8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL759 CM0+ system interrupt control 0x8BDC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL76 CM0+ system interrupt control 0x8130 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL760 CM0+ system interrupt control 0x8BE0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL761 CM0+ system interrupt control 0x8BE4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL762 CM0+ system interrupt control 0x8BE8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL763 CM0+ system interrupt control 0x8BEC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL764 CM0+ system interrupt control 0x8BF0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL765 CM0+ system interrupt control 0x8BF4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL766 CM0+ system interrupt control 0x8BF8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL767 CM0+ system interrupt control 0x8BFC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL768 CM0+ system interrupt control 0x8C00 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL769 CM0+ system interrupt control 0x8C04 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL77 CM0+ system interrupt control 0x8134 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL770 CM0+ system interrupt control 0x8C08 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL771 CM0+ system interrupt control 0x8C0C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL772 CM0+ system interrupt control 0x8C10 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL773 CM0+ system interrupt control 0x8C14 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL774 CM0+ system interrupt control 0x8C18 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL775 CM0+ system interrupt control 0x8C1C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL776 CM0+ system interrupt control 0x8C20 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL777 CM0+ system interrupt control 0x8C24 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL778 CM0+ system interrupt control 0x8C28 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL779 CM0+ system interrupt control 0x8C2C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL78 CM0+ system interrupt control 0x8138 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL780 CM0+ system interrupt control 0x8C30 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL781 CM0+ system interrupt control 0x8C34 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL782 CM0+ system interrupt control 0x8C38 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL783 CM0+ system interrupt control 0x8C3C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL784 CM0+ system interrupt control 0x8C40 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL785 CM0+ system interrupt control 0x8C44 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL786 CM0+ system interrupt control 0x8C48 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL787 CM0+ system interrupt control 0x8C4C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL788 CM0+ system interrupt control 0x8C50 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL789 CM0+ system interrupt control 0x8C54 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL79 CM0+ system interrupt control 0x813C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL790 CM0+ system interrupt control 0x8C58 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL791 CM0+ system interrupt control 0x8C5C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL792 CM0+ system interrupt control 0x8C60 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL793 CM0+ system interrupt control 0x8C64 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL794 CM0+ system interrupt control 0x8C68 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL795 CM0+ system interrupt control 0x8C6C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL796 CM0+ system interrupt control 0x8C70 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL797 CM0+ system interrupt control 0x8C74 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL798 CM0+ system interrupt control 0x8C78 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL799 CM0+ system interrupt control 0x8C7C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL8 CM0+ system interrupt control 0x8020 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL80 CM0+ system interrupt control 0x8140 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL800 CM0+ system interrupt control 0x8C80 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL801 CM0+ system interrupt control 0x8C84 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL802 CM0+ system interrupt control 0x8C88 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL803 CM0+ system interrupt control 0x8C8C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL804 CM0+ system interrupt control 0x8C90 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL805 CM0+ system interrupt control 0x8C94 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL806 CM0+ system interrupt control 0x8C98 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL807 CM0+ system interrupt control 0x8C9C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL808 CM0+ system interrupt control 0x8CA0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL809 CM0+ system interrupt control 0x8CA4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL81 CM0+ system interrupt control 0x8144 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL810 CM0+ system interrupt control 0x8CA8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL811 CM0+ system interrupt control 0x8CAC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL812 CM0+ system interrupt control 0x8CB0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL813 CM0+ system interrupt control 0x8CB4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL814 CM0+ system interrupt control 0x8CB8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL815 CM0+ system interrupt control 0x8CBC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL816 CM0+ system interrupt control 0x8CC0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL817 CM0+ system interrupt control 0x8CC4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL818 CM0+ system interrupt control 0x8CC8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL819 CM0+ system interrupt control 0x8CCC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL82 CM0+ system interrupt control 0x8148 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL820 CM0+ system interrupt control 0x8CD0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL821 CM0+ system interrupt control 0x8CD4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL822 CM0+ system interrupt control 0x8CD8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL823 CM0+ system interrupt control 0x8CDC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL824 CM0+ system interrupt control 0x8CE0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL825 CM0+ system interrupt control 0x8CE4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL826 CM0+ system interrupt control 0x8CE8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL827 CM0+ system interrupt control 0x8CEC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL828 CM0+ system interrupt control 0x8CF0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL829 CM0+ system interrupt control 0x8CF4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL83 CM0+ system interrupt control 0x814C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL830 CM0+ system interrupt control 0x8CF8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL831 CM0+ system interrupt control 0x8CFC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL832 CM0+ system interrupt control 0x8D00 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL833 CM0+ system interrupt control 0x8D04 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL834 CM0+ system interrupt control 0x8D08 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL835 CM0+ system interrupt control 0x8D0C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL836 CM0+ system interrupt control 0x8D10 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL837 CM0+ system interrupt control 0x8D14 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL838 CM0+ system interrupt control 0x8D18 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL839 CM0+ system interrupt control 0x8D1C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL84 CM0+ system interrupt control 0x8150 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL840 CM0+ system interrupt control 0x8D20 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL841 CM0+ system interrupt control 0x8D24 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL842 CM0+ system interrupt control 0x8D28 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL843 CM0+ system interrupt control 0x8D2C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL844 CM0+ system interrupt control 0x8D30 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL845 CM0+ system interrupt control 0x8D34 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL846 CM0+ system interrupt control 0x8D38 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL847 CM0+ system interrupt control 0x8D3C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL848 CM0+ system interrupt control 0x8D40 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL849 CM0+ system interrupt control 0x8D44 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL85 CM0+ system interrupt control 0x8154 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL850 CM0+ system interrupt control 0x8D48 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL851 CM0+ system interrupt control 0x8D4C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL852 CM0+ system interrupt control 0x8D50 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL853 CM0+ system interrupt control 0x8D54 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL854 CM0+ system interrupt control 0x8D58 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL855 CM0+ system interrupt control 0x8D5C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL856 CM0+ system interrupt control 0x8D60 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL857 CM0+ system interrupt control 0x8D64 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL858 CM0+ system interrupt control 0x8D68 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL859 CM0+ system interrupt control 0x8D6C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL86 CM0+ system interrupt control 0x8158 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL860 CM0+ system interrupt control 0x8D70 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL861 CM0+ system interrupt control 0x8D74 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL862 CM0+ system interrupt control 0x8D78 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL863 CM0+ system interrupt control 0x8D7C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL864 CM0+ system interrupt control 0x8D80 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL865 CM0+ system interrupt control 0x8D84 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL866 CM0+ system interrupt control 0x8D88 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL867 CM0+ system interrupt control 0x8D8C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL868 CM0+ system interrupt control 0x8D90 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL869 CM0+ system interrupt control 0x8D94 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL87 CM0+ system interrupt control 0x815C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL870 CM0+ system interrupt control 0x8D98 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL871 CM0+ system interrupt control 0x8D9C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL872 CM0+ system interrupt control 0x8DA0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL873 CM0+ system interrupt control 0x8DA4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL874 CM0+ system interrupt control 0x8DA8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL875 CM0+ system interrupt control 0x8DAC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL876 CM0+ system interrupt control 0x8DB0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL877 CM0+ system interrupt control 0x8DB4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL878 CM0+ system interrupt control 0x8DB8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL879 CM0+ system interrupt control 0x8DBC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL88 CM0+ system interrupt control 0x8160 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL880 CM0+ system interrupt control 0x8DC0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL881 CM0+ system interrupt control 0x8DC4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL882 CM0+ system interrupt control 0x8DC8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL883 CM0+ system interrupt control 0x8DCC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL884 CM0+ system interrupt control 0x8DD0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL885 CM0+ system interrupt control 0x8DD4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL886 CM0+ system interrupt control 0x8DD8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL887 CM0+ system interrupt control 0x8DDC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL888 CM0+ system interrupt control 0x8DE0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL889 CM0+ system interrupt control 0x8DE4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL89 CM0+ system interrupt control 0x8164 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL890 CM0+ system interrupt control 0x8DE8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL891 CM0+ system interrupt control 0x8DEC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL892 CM0+ system interrupt control 0x8DF0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL893 CM0+ system interrupt control 0x8DF4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL894 CM0+ system interrupt control 0x8DF8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL895 CM0+ system interrupt control 0x8DFC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL896 CM0+ system interrupt control 0x8E00 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL897 CM0+ system interrupt control 0x8E04 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL898 CM0+ system interrupt control 0x8E08 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL899 CM0+ system interrupt control 0x8E0C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL9 CM0+ system interrupt control 0x8024 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL90 CM0+ system interrupt control 0x8168 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL900 CM0+ system interrupt control 0x8E10 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL901 CM0+ system interrupt control 0x8E14 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL902 CM0+ system interrupt control 0x8E18 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL903 CM0+ system interrupt control 0x8E1C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL904 CM0+ system interrupt control 0x8E20 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL905 CM0+ system interrupt control 0x8E24 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL906 CM0+ system interrupt control 0x8E28 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL907 CM0+ system interrupt control 0x8E2C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL908 CM0+ system interrupt control 0x8E30 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL909 CM0+ system interrupt control 0x8E34 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL91 CM0+ system interrupt control 0x816C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL910 CM0+ system interrupt control 0x8E38 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL911 CM0+ system interrupt control 0x8E3C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL912 CM0+ system interrupt control 0x8E40 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL913 CM0+ system interrupt control 0x8E44 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL914 CM0+ system interrupt control 0x8E48 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL915 CM0+ system interrupt control 0x8E4C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL916 CM0+ system interrupt control 0x8E50 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL917 CM0+ system interrupt control 0x8E54 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL918 CM0+ system interrupt control 0x8E58 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL919 CM0+ system interrupt control 0x8E5C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL92 CM0+ system interrupt control 0x8170 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL920 CM0+ system interrupt control 0x8E60 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL921 CM0+ system interrupt control 0x8E64 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL922 CM0+ system interrupt control 0x8E68 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL923 CM0+ system interrupt control 0x8E6C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL924 CM0+ system interrupt control 0x8E70 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL925 CM0+ system interrupt control 0x8E74 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL926 CM0+ system interrupt control 0x8E78 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL927 CM0+ system interrupt control 0x8E7C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL928 CM0+ system interrupt control 0x8E80 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL929 CM0+ system interrupt control 0x8E84 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL93 CM0+ system interrupt control 0x8174 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL930 CM0+ system interrupt control 0x8E88 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL931 CM0+ system interrupt control 0x8E8C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL932 CM0+ system interrupt control 0x8E90 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL933 CM0+ system interrupt control 0x8E94 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL934 CM0+ system interrupt control 0x8E98 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL935 CM0+ system interrupt control 0x8E9C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL936 CM0+ system interrupt control 0x8EA0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL937 CM0+ system interrupt control 0x8EA4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL938 CM0+ system interrupt control 0x8EA8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL939 CM0+ system interrupt control 0x8EAC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL94 CM0+ system interrupt control 0x8178 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL940 CM0+ system interrupt control 0x8EB0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL941 CM0+ system interrupt control 0x8EB4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL942 CM0+ system interrupt control 0x8EB8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL943 CM0+ system interrupt control 0x8EBC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL944 CM0+ system interrupt control 0x8EC0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL945 CM0+ system interrupt control 0x8EC4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL946 CM0+ system interrupt control 0x8EC8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL947 CM0+ system interrupt control 0x8ECC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL948 CM0+ system interrupt control 0x8ED0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL949 CM0+ system interrupt control 0x8ED4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL95 CM0+ system interrupt control 0x817C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL950 CM0+ system interrupt control 0x8ED8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL951 CM0+ system interrupt control 0x8EDC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL952 CM0+ system interrupt control 0x8EE0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL953 CM0+ system interrupt control 0x8EE4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL954 CM0+ system interrupt control 0x8EE8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL955 CM0+ system interrupt control 0x8EEC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL956 CM0+ system interrupt control 0x8EF0 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL957 CM0+ system interrupt control 0x8EF4 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL958 CM0+ system interrupt control 0x8EF8 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL959 CM0+ system interrupt control 0x8EFC 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL96 CM0+ system interrupt control 0x8180 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL960 CM0+ system interrupt control 0x8F00 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL961 CM0+ system interrupt control 0x8F04 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL962 CM0+ system interrupt control 0x8F08 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL963 CM0+ system interrupt control 0x8F0C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL964 CM0+ system interrupt control 0x8F10 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL965 CM0+ system interrupt control 0x8F14 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL966 CM0+ system interrupt control 0x8F18 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL967 CM0+ system interrupt control 0x8F1C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL968 CM0+ system interrupt control 0x8F20 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL969 CM0+ system interrupt control 0x8F24 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL97 CM0+ system interrupt control 0x8184 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL970 CM0+ system interrupt control 0x8F28 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL971 CM0+ system interrupt control 0x8F2C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL972 CM0+ system interrupt control 0x8F30 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL973 CM0+ system interrupt control 0x8F34 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL974 CM0+ system interrupt control 0x8F38 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL975 CM0+ system interrupt control 0x8F3C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL976 CM0+ system interrupt control 0x8F40 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL977 CM0+ system interrupt control 0x8F44 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL978 CM0+ system interrupt control 0x8F48 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL979 CM0+ system interrupt control 0x8F4C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL98 CM0+ system interrupt control 0x8188 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL980 CM0+ system interrupt control 0x8F50 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL981 CM0+ system interrupt control 0x8F54 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL982 CM0+ system interrupt control 0x8F58 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL983 CM0+ system interrupt control 0x8F5C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL984 CM0+ system interrupt control 0x8F60 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL985 CM0+ system interrupt control 0x8F64 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL986 CM0+ system interrupt control 0x8F68 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL987 CM0+ system interrupt control 0x8F6C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL988 CM0+ system interrupt control 0x8F70 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL989 CM0+ system interrupt control 0x8F74 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL99 CM0+ system interrupt control 0x818C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL990 CM0+ system interrupt control 0x8F78 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL991 CM0+ system interrupt control 0x8F7C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL992 CM0+ system interrupt control 0x8F80 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL993 CM0+ system interrupt control 0x8F84 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL994 CM0+ system interrupt control 0x8F88 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL995 CM0+ system interrupt control 0x8F8C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL996 CM0+ system interrupt control 0x8F90 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL997 CM0+ system interrupt control 0x8F94 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL998 CM0+ system interrupt control 0x8F98 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_SYSTEM_INT_CTL999 CM0+ system interrupt control 0x8F9C 32 read-write n 0x0 0x0 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. 0 3 read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. 31 32 read-write CM0_VECTOR_TABLE_BASE CM0+ vector table base 0x1120 32 read-write n 0x0 0x0 ADDR24 Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. Note: the CM0+ vector table is at an address that is a 256 B multiple. 8 32 read-write CM4_CLOCK_CTL CM4 clock control 0x8 32 read-write n 0x0 0x0 FAST_INT_DIV Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write CM4_CTL CM4 control 0xC 32 read-write n 0x0 0x0 DZC_MASK CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. 25 26 read-write IDC_MASK CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. 31 32 read-write IOC_MASK CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the ARM architecture does NOT support FPU exceptions i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. 24 25 read-write IXC_MASK CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. 28 29 read-write OFC_MASK CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. 26 27 read-write UFC_MASK CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. 27 28 read-write CM4_INT0_STATUS CM4 interrupt 0 status 0x100 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 0. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_INT1_STATUS CM4 interrupt 1 status 0x104 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_INT2_STATUS CM4 interrupt 2 status 0x108 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_INT3_STATUS CM4 interrupt 3 status 0x10C 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_INT4_STATUS CM4 interrupt 4 status 0x110 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_INT5_STATUS CM4 interrupt 5 status 0x114 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_INT6_STATUS CM4 interrupt 6 status 0x118 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_INT7_STATUS CM4 interrupt 7 status 0x11C 32 read-only n 0x0 0x0 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. 0 10 read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. 31 32 read-only CM4_NMI_CTL0 CM4 NMI control 0x240 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM4_NMI_CTL1 CM4 NMI control 0x244 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM4_NMI_CTL2 CM4 NMI control 0x248 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM4_NMI_CTL3 CM4 NMI control 0x24C 32 read-write n 0x0 0x0 SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. 0 10 read-write CM4_PWR_CTL CM4 power control 0x1200 32 read-write n 0x0 0x0 PWR_MODE Power mode. 0 2 read-write OFF Switch CM4 off Power off, clock off, isolate, reset and no retain. 0 RESET Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. 1 RETAINED Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain. 2 ENABLED Switch CM4 on. Power on, clock on, no isolate, no reset and no retain. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only CM4_PWR_DELAY_CTL CM4 power control 0x1204 32 read-write n 0x0 0x0 UP Number clock cycles delay needed after power domain power up 0 10 read-write CM4_STATUS CM4 status 0x4 32 read-only n 0x0 0x0 PWR_DONE After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req 4 5 read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. 1 2 read-only SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. 0 1 read-only CM4_SYSTEM_INT_CTL0 CM4 system interrupt control 0xA000 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1 CM4 system interrupt control 0xA004 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL10 CM4 system interrupt control 0xA028 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL100 CM4 system interrupt control 0xA190 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1000 CM4 system interrupt control 0xAFA0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1001 CM4 system interrupt control 0xAFA4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1002 CM4 system interrupt control 0xAFA8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1003 CM4 system interrupt control 0xAFAC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1004 CM4 system interrupt control 0xAFB0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1005 CM4 system interrupt control 0xAFB4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1006 CM4 system interrupt control 0xAFB8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1007 CM4 system interrupt control 0xAFBC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1008 CM4 system interrupt control 0xAFC0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1009 CM4 system interrupt control 0xAFC4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL101 CM4 system interrupt control 0xA194 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1010 CM4 system interrupt control 0xAFC8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1011 CM4 system interrupt control 0xAFCC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1012 CM4 system interrupt control 0xAFD0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1013 CM4 system interrupt control 0xAFD4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1014 CM4 system interrupt control 0xAFD8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1015 CM4 system interrupt control 0xAFDC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1016 CM4 system interrupt control 0xAFE0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1017 CM4 system interrupt control 0xAFE4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1018 CM4 system interrupt control 0xAFE8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1019 CM4 system interrupt control 0xAFEC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL102 CM4 system interrupt control 0xA198 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1020 CM4 system interrupt control 0xAFF0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1021 CM4 system interrupt control 0xAFF4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL1022 CM4 system interrupt control 0xAFF8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL103 CM4 system interrupt control 0xA19C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL104 CM4 system interrupt control 0xA1A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL105 CM4 system interrupt control 0xA1A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL106 CM4 system interrupt control 0xA1A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL107 CM4 system interrupt control 0xA1AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL108 CM4 system interrupt control 0xA1B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL109 CM4 system interrupt control 0xA1B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL11 CM4 system interrupt control 0xA02C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL110 CM4 system interrupt control 0xA1B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL111 CM4 system interrupt control 0xA1BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL112 CM4 system interrupt control 0xA1C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL113 CM4 system interrupt control 0xA1C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL114 CM4 system interrupt control 0xA1C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL115 CM4 system interrupt control 0xA1CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL116 CM4 system interrupt control 0xA1D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL117 CM4 system interrupt control 0xA1D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL118 CM4 system interrupt control 0xA1D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL119 CM4 system interrupt control 0xA1DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL12 CM4 system interrupt control 0xA030 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL120 CM4 system interrupt control 0xA1E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL121 CM4 system interrupt control 0xA1E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL122 CM4 system interrupt control 0xA1E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL123 CM4 system interrupt control 0xA1EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL124 CM4 system interrupt control 0xA1F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL125 CM4 system interrupt control 0xA1F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL126 CM4 system interrupt control 0xA1F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL127 CM4 system interrupt control 0xA1FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL128 CM4 system interrupt control 0xA200 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL129 CM4 system interrupt control 0xA204 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL13 CM4 system interrupt control 0xA034 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL130 CM4 system interrupt control 0xA208 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL131 CM4 system interrupt control 0xA20C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL132 CM4 system interrupt control 0xA210 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL133 CM4 system interrupt control 0xA214 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL134 CM4 system interrupt control 0xA218 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL135 CM4 system interrupt control 0xA21C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL136 CM4 system interrupt control 0xA220 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL137 CM4 system interrupt control 0xA224 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL138 CM4 system interrupt control 0xA228 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL139 CM4 system interrupt control 0xA22C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL14 CM4 system interrupt control 0xA038 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL140 CM4 system interrupt control 0xA230 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL141 CM4 system interrupt control 0xA234 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL142 CM4 system interrupt control 0xA238 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL143 CM4 system interrupt control 0xA23C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL144 CM4 system interrupt control 0xA240 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL145 CM4 system interrupt control 0xA244 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL146 CM4 system interrupt control 0xA248 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL147 CM4 system interrupt control 0xA24C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL148 CM4 system interrupt control 0xA250 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL149 CM4 system interrupt control 0xA254 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL15 CM4 system interrupt control 0xA03C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL150 CM4 system interrupt control 0xA258 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL151 CM4 system interrupt control 0xA25C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL152 CM4 system interrupt control 0xA260 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL153 CM4 system interrupt control 0xA264 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL154 CM4 system interrupt control 0xA268 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL155 CM4 system interrupt control 0xA26C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL156 CM4 system interrupt control 0xA270 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL157 CM4 system interrupt control 0xA274 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL158 CM4 system interrupt control 0xA278 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL159 CM4 system interrupt control 0xA27C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL16 CM4 system interrupt control 0xA040 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL160 CM4 system interrupt control 0xA280 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL161 CM4 system interrupt control 0xA284 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL162 CM4 system interrupt control 0xA288 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL163 CM4 system interrupt control 0xA28C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL164 CM4 system interrupt control 0xA290 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL165 CM4 system interrupt control 0xA294 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL166 CM4 system interrupt control 0xA298 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL167 CM4 system interrupt control 0xA29C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL168 CM4 system interrupt control 0xA2A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL169 CM4 system interrupt control 0xA2A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL17 CM4 system interrupt control 0xA044 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL170 CM4 system interrupt control 0xA2A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL171 CM4 system interrupt control 0xA2AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL172 CM4 system interrupt control 0xA2B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL173 CM4 system interrupt control 0xA2B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL174 CM4 system interrupt control 0xA2B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL175 CM4 system interrupt control 0xA2BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL176 CM4 system interrupt control 0xA2C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL177 CM4 system interrupt control 0xA2C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL178 CM4 system interrupt control 0xA2C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL179 CM4 system interrupt control 0xA2CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL18 CM4 system interrupt control 0xA048 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL180 CM4 system interrupt control 0xA2D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL181 CM4 system interrupt control 0xA2D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL182 CM4 system interrupt control 0xA2D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL183 CM4 system interrupt control 0xA2DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL184 CM4 system interrupt control 0xA2E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL185 CM4 system interrupt control 0xA2E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL186 CM4 system interrupt control 0xA2E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL187 CM4 system interrupt control 0xA2EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL188 CM4 system interrupt control 0xA2F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL189 CM4 system interrupt control 0xA2F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL19 CM4 system interrupt control 0xA04C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL190 CM4 system interrupt control 0xA2F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL191 CM4 system interrupt control 0xA2FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL192 CM4 system interrupt control 0xA300 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL193 CM4 system interrupt control 0xA304 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL194 CM4 system interrupt control 0xA308 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL195 CM4 system interrupt control 0xA30C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL196 CM4 system interrupt control 0xA310 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL197 CM4 system interrupt control 0xA314 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL198 CM4 system interrupt control 0xA318 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL199 CM4 system interrupt control 0xA31C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL2 CM4 system interrupt control 0xA008 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL20 CM4 system interrupt control 0xA050 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL200 CM4 system interrupt control 0xA320 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL201 CM4 system interrupt control 0xA324 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL202 CM4 system interrupt control 0xA328 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL203 CM4 system interrupt control 0xA32C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL204 CM4 system interrupt control 0xA330 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL205 CM4 system interrupt control 0xA334 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL206 CM4 system interrupt control 0xA338 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL207 CM4 system interrupt control 0xA33C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL208 CM4 system interrupt control 0xA340 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL209 CM4 system interrupt control 0xA344 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL21 CM4 system interrupt control 0xA054 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL210 CM4 system interrupt control 0xA348 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL211 CM4 system interrupt control 0xA34C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL212 CM4 system interrupt control 0xA350 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL213 CM4 system interrupt control 0xA354 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL214 CM4 system interrupt control 0xA358 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL215 CM4 system interrupt control 0xA35C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL216 CM4 system interrupt control 0xA360 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL217 CM4 system interrupt control 0xA364 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL218 CM4 system interrupt control 0xA368 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL219 CM4 system interrupt control 0xA36C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL22 CM4 system interrupt control 0xA058 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL220 CM4 system interrupt control 0xA370 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL221 CM4 system interrupt control 0xA374 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL222 CM4 system interrupt control 0xA378 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL223 CM4 system interrupt control 0xA37C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL224 CM4 system interrupt control 0xA380 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL225 CM4 system interrupt control 0xA384 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL226 CM4 system interrupt control 0xA388 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL227 CM4 system interrupt control 0xA38C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL228 CM4 system interrupt control 0xA390 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL229 CM4 system interrupt control 0xA394 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL23 CM4 system interrupt control 0xA05C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL230 CM4 system interrupt control 0xA398 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL231 CM4 system interrupt control 0xA39C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL232 CM4 system interrupt control 0xA3A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL233 CM4 system interrupt control 0xA3A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL234 CM4 system interrupt control 0xA3A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL235 CM4 system interrupt control 0xA3AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL236 CM4 system interrupt control 0xA3B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL237 CM4 system interrupt control 0xA3B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL238 CM4 system interrupt control 0xA3B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL239 CM4 system interrupt control 0xA3BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL24 CM4 system interrupt control 0xA060 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL240 CM4 system interrupt control 0xA3C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL241 CM4 system interrupt control 0xA3C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL242 CM4 system interrupt control 0xA3C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL243 CM4 system interrupt control 0xA3CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL244 CM4 system interrupt control 0xA3D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL245 CM4 system interrupt control 0xA3D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL246 CM4 system interrupt control 0xA3D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL247 CM4 system interrupt control 0xA3DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL248 CM4 system interrupt control 0xA3E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL249 CM4 system interrupt control 0xA3E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL25 CM4 system interrupt control 0xA064 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL250 CM4 system interrupt control 0xA3E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL251 CM4 system interrupt control 0xA3EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL252 CM4 system interrupt control 0xA3F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL253 CM4 system interrupt control 0xA3F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL254 CM4 system interrupt control 0xA3F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL255 CM4 system interrupt control 0xA3FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL256 CM4 system interrupt control 0xA400 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL257 CM4 system interrupt control 0xA404 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL258 CM4 system interrupt control 0xA408 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL259 CM4 system interrupt control 0xA40C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL26 CM4 system interrupt control 0xA068 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL260 CM4 system interrupt control 0xA410 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL261 CM4 system interrupt control 0xA414 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL262 CM4 system interrupt control 0xA418 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL263 CM4 system interrupt control 0xA41C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL264 CM4 system interrupt control 0xA420 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL265 CM4 system interrupt control 0xA424 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL266 CM4 system interrupt control 0xA428 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL267 CM4 system interrupt control 0xA42C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL268 CM4 system interrupt control 0xA430 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL269 CM4 system interrupt control 0xA434 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL27 CM4 system interrupt control 0xA06C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL270 CM4 system interrupt control 0xA438 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL271 CM4 system interrupt control 0xA43C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL272 CM4 system interrupt control 0xA440 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL273 CM4 system interrupt control 0xA444 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL274 CM4 system interrupt control 0xA448 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL275 CM4 system interrupt control 0xA44C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL276 CM4 system interrupt control 0xA450 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL277 CM4 system interrupt control 0xA454 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL278 CM4 system interrupt control 0xA458 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL279 CM4 system interrupt control 0xA45C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL28 CM4 system interrupt control 0xA070 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL280 CM4 system interrupt control 0xA460 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL281 CM4 system interrupt control 0xA464 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL282 CM4 system interrupt control 0xA468 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL283 CM4 system interrupt control 0xA46C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL284 CM4 system interrupt control 0xA470 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL285 CM4 system interrupt control 0xA474 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL286 CM4 system interrupt control 0xA478 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL287 CM4 system interrupt control 0xA47C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL288 CM4 system interrupt control 0xA480 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL289 CM4 system interrupt control 0xA484 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL29 CM4 system interrupt control 0xA074 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL290 CM4 system interrupt control 0xA488 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL291 CM4 system interrupt control 0xA48C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL292 CM4 system interrupt control 0xA490 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL293 CM4 system interrupt control 0xA494 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL294 CM4 system interrupt control 0xA498 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL295 CM4 system interrupt control 0xA49C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL296 CM4 system interrupt control 0xA4A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL297 CM4 system interrupt control 0xA4A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL298 CM4 system interrupt control 0xA4A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL299 CM4 system interrupt control 0xA4AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL3 CM4 system interrupt control 0xA00C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL30 CM4 system interrupt control 0xA078 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL300 CM4 system interrupt control 0xA4B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL301 CM4 system interrupt control 0xA4B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL302 CM4 system interrupt control 0xA4B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL303 CM4 system interrupt control 0xA4BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL304 CM4 system interrupt control 0xA4C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL305 CM4 system interrupt control 0xA4C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL306 CM4 system interrupt control 0xA4C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL307 CM4 system interrupt control 0xA4CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL308 CM4 system interrupt control 0xA4D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL309 CM4 system interrupt control 0xA4D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL31 CM4 system interrupt control 0xA07C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL310 CM4 system interrupt control 0xA4D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL311 CM4 system interrupt control 0xA4DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL312 CM4 system interrupt control 0xA4E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL313 CM4 system interrupt control 0xA4E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL314 CM4 system interrupt control 0xA4E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL315 CM4 system interrupt control 0xA4EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL316 CM4 system interrupt control 0xA4F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL317 CM4 system interrupt control 0xA4F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL318 CM4 system interrupt control 0xA4F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL319 CM4 system interrupt control 0xA4FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL32 CM4 system interrupt control 0xA080 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL320 CM4 system interrupt control 0xA500 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL321 CM4 system interrupt control 0xA504 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL322 CM4 system interrupt control 0xA508 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL323 CM4 system interrupt control 0xA50C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL324 CM4 system interrupt control 0xA510 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL325 CM4 system interrupt control 0xA514 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL326 CM4 system interrupt control 0xA518 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL327 CM4 system interrupt control 0xA51C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL328 CM4 system interrupt control 0xA520 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL329 CM4 system interrupt control 0xA524 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL33 CM4 system interrupt control 0xA084 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL330 CM4 system interrupt control 0xA528 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL331 CM4 system interrupt control 0xA52C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL332 CM4 system interrupt control 0xA530 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL333 CM4 system interrupt control 0xA534 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL334 CM4 system interrupt control 0xA538 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL335 CM4 system interrupt control 0xA53C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL336 CM4 system interrupt control 0xA540 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL337 CM4 system interrupt control 0xA544 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL338 CM4 system interrupt control 0xA548 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL339 CM4 system interrupt control 0xA54C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL34 CM4 system interrupt control 0xA088 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL340 CM4 system interrupt control 0xA550 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL341 CM4 system interrupt control 0xA554 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL342 CM4 system interrupt control 0xA558 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL343 CM4 system interrupt control 0xA55C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL344 CM4 system interrupt control 0xA560 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL345 CM4 system interrupt control 0xA564 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL346 CM4 system interrupt control 0xA568 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL347 CM4 system interrupt control 0xA56C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL348 CM4 system interrupt control 0xA570 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL349 CM4 system interrupt control 0xA574 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL35 CM4 system interrupt control 0xA08C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL350 CM4 system interrupt control 0xA578 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL351 CM4 system interrupt control 0xA57C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL352 CM4 system interrupt control 0xA580 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL353 CM4 system interrupt control 0xA584 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL354 CM4 system interrupt control 0xA588 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL355 CM4 system interrupt control 0xA58C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL356 CM4 system interrupt control 0xA590 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL357 CM4 system interrupt control 0xA594 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL358 CM4 system interrupt control 0xA598 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL359 CM4 system interrupt control 0xA59C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL36 CM4 system interrupt control 0xA090 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL360 CM4 system interrupt control 0xA5A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL361 CM4 system interrupt control 0xA5A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL362 CM4 system interrupt control 0xA5A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL363 CM4 system interrupt control 0xA5AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL364 CM4 system interrupt control 0xA5B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL365 CM4 system interrupt control 0xA5B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL366 CM4 system interrupt control 0xA5B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL367 CM4 system interrupt control 0xA5BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL368 CM4 system interrupt control 0xA5C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL369 CM4 system interrupt control 0xA5C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL37 CM4 system interrupt control 0xA094 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL370 CM4 system interrupt control 0xA5C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL371 CM4 system interrupt control 0xA5CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL372 CM4 system interrupt control 0xA5D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL373 CM4 system interrupt control 0xA5D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL374 CM4 system interrupt control 0xA5D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL375 CM4 system interrupt control 0xA5DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL376 CM4 system interrupt control 0xA5E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL377 CM4 system interrupt control 0xA5E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL378 CM4 system interrupt control 0xA5E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL379 CM4 system interrupt control 0xA5EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL38 CM4 system interrupt control 0xA098 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL380 CM4 system interrupt control 0xA5F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL381 CM4 system interrupt control 0xA5F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL382 CM4 system interrupt control 0xA5F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL383 CM4 system interrupt control 0xA5FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL384 CM4 system interrupt control 0xA600 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL385 CM4 system interrupt control 0xA604 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL386 CM4 system interrupt control 0xA608 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL387 CM4 system interrupt control 0xA60C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL388 CM4 system interrupt control 0xA610 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL389 CM4 system interrupt control 0xA614 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL39 CM4 system interrupt control 0xA09C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL390 CM4 system interrupt control 0xA618 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL391 CM4 system interrupt control 0xA61C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL392 CM4 system interrupt control 0xA620 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL393 CM4 system interrupt control 0xA624 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL394 CM4 system interrupt control 0xA628 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL395 CM4 system interrupt control 0xA62C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL396 CM4 system interrupt control 0xA630 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL397 CM4 system interrupt control 0xA634 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL398 CM4 system interrupt control 0xA638 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL399 CM4 system interrupt control 0xA63C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL4 CM4 system interrupt control 0xA010 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL40 CM4 system interrupt control 0xA0A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL400 CM4 system interrupt control 0xA640 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL401 CM4 system interrupt control 0xA644 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL402 CM4 system interrupt control 0xA648 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL403 CM4 system interrupt control 0xA64C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL404 CM4 system interrupt control 0xA650 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL405 CM4 system interrupt control 0xA654 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL406 CM4 system interrupt control 0xA658 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL407 CM4 system interrupt control 0xA65C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL408 CM4 system interrupt control 0xA660 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL409 CM4 system interrupt control 0xA664 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL41 CM4 system interrupt control 0xA0A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL410 CM4 system interrupt control 0xA668 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL411 CM4 system interrupt control 0xA66C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL412 CM4 system interrupt control 0xA670 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL413 CM4 system interrupt control 0xA674 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL414 CM4 system interrupt control 0xA678 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL415 CM4 system interrupt control 0xA67C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL416 CM4 system interrupt control 0xA680 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL417 CM4 system interrupt control 0xA684 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL418 CM4 system interrupt control 0xA688 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL419 CM4 system interrupt control 0xA68C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL42 CM4 system interrupt control 0xA0A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL420 CM4 system interrupt control 0xA690 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL421 CM4 system interrupt control 0xA694 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL422 CM4 system interrupt control 0xA698 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL423 CM4 system interrupt control 0xA69C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL424 CM4 system interrupt control 0xA6A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL425 CM4 system interrupt control 0xA6A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL426 CM4 system interrupt control 0xA6A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL427 CM4 system interrupt control 0xA6AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL428 CM4 system interrupt control 0xA6B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL429 CM4 system interrupt control 0xA6B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL43 CM4 system interrupt control 0xA0AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL430 CM4 system interrupt control 0xA6B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL431 CM4 system interrupt control 0xA6BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL432 CM4 system interrupt control 0xA6C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL433 CM4 system interrupt control 0xA6C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL434 CM4 system interrupt control 0xA6C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL435 CM4 system interrupt control 0xA6CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL436 CM4 system interrupt control 0xA6D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL437 CM4 system interrupt control 0xA6D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL438 CM4 system interrupt control 0xA6D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL439 CM4 system interrupt control 0xA6DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL44 CM4 system interrupt control 0xA0B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL440 CM4 system interrupt control 0xA6E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL441 CM4 system interrupt control 0xA6E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL442 CM4 system interrupt control 0xA6E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL443 CM4 system interrupt control 0xA6EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL444 CM4 system interrupt control 0xA6F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL445 CM4 system interrupt control 0xA6F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL446 CM4 system interrupt control 0xA6F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL447 CM4 system interrupt control 0xA6FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL448 CM4 system interrupt control 0xA700 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL449 CM4 system interrupt control 0xA704 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL45 CM4 system interrupt control 0xA0B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL450 CM4 system interrupt control 0xA708 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL451 CM4 system interrupt control 0xA70C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL452 CM4 system interrupt control 0xA710 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL453 CM4 system interrupt control 0xA714 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL454 CM4 system interrupt control 0xA718 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL455 CM4 system interrupt control 0xA71C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL456 CM4 system interrupt control 0xA720 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL457 CM4 system interrupt control 0xA724 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL458 CM4 system interrupt control 0xA728 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL459 CM4 system interrupt control 0xA72C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL46 CM4 system interrupt control 0xA0B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL460 CM4 system interrupt control 0xA730 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL461 CM4 system interrupt control 0xA734 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL462 CM4 system interrupt control 0xA738 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL463 CM4 system interrupt control 0xA73C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL464 CM4 system interrupt control 0xA740 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL465 CM4 system interrupt control 0xA744 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL466 CM4 system interrupt control 0xA748 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL467 CM4 system interrupt control 0xA74C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL468 CM4 system interrupt control 0xA750 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL469 CM4 system interrupt control 0xA754 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL47 CM4 system interrupt control 0xA0BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL470 CM4 system interrupt control 0xA758 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL471 CM4 system interrupt control 0xA75C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL472 CM4 system interrupt control 0xA760 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL473 CM4 system interrupt control 0xA764 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL474 CM4 system interrupt control 0xA768 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL475 CM4 system interrupt control 0xA76C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL476 CM4 system interrupt control 0xA770 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL477 CM4 system interrupt control 0xA774 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL478 CM4 system interrupt control 0xA778 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL479 CM4 system interrupt control 0xA77C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL48 CM4 system interrupt control 0xA0C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL480 CM4 system interrupt control 0xA780 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL481 CM4 system interrupt control 0xA784 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL482 CM4 system interrupt control 0xA788 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL483 CM4 system interrupt control 0xA78C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL484 CM4 system interrupt control 0xA790 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL485 CM4 system interrupt control 0xA794 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL486 CM4 system interrupt control 0xA798 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL487 CM4 system interrupt control 0xA79C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL488 CM4 system interrupt control 0xA7A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL489 CM4 system interrupt control 0xA7A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL49 CM4 system interrupt control 0xA0C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL490 CM4 system interrupt control 0xA7A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL491 CM4 system interrupt control 0xA7AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL492 CM4 system interrupt control 0xA7B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL493 CM4 system interrupt control 0xA7B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL494 CM4 system interrupt control 0xA7B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL495 CM4 system interrupt control 0xA7BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL496 CM4 system interrupt control 0xA7C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL497 CM4 system interrupt control 0xA7C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL498 CM4 system interrupt control 0xA7C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL499 CM4 system interrupt control 0xA7CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL5 CM4 system interrupt control 0xA014 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL50 CM4 system interrupt control 0xA0C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL500 CM4 system interrupt control 0xA7D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL501 CM4 system interrupt control 0xA7D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL502 CM4 system interrupt control 0xA7D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL503 CM4 system interrupt control 0xA7DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL504 CM4 system interrupt control 0xA7E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL505 CM4 system interrupt control 0xA7E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL506 CM4 system interrupt control 0xA7E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL507 CM4 system interrupt control 0xA7EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL508 CM4 system interrupt control 0xA7F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL509 CM4 system interrupt control 0xA7F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL51 CM4 system interrupt control 0xA0CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL510 CM4 system interrupt control 0xA7F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL511 CM4 system interrupt control 0xA7FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL512 CM4 system interrupt control 0xA800 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL513 CM4 system interrupt control 0xA804 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL514 CM4 system interrupt control 0xA808 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL515 CM4 system interrupt control 0xA80C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL516 CM4 system interrupt control 0xA810 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL517 CM4 system interrupt control 0xA814 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL518 CM4 system interrupt control 0xA818 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL519 CM4 system interrupt control 0xA81C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL52 CM4 system interrupt control 0xA0D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL520 CM4 system interrupt control 0xA820 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL521 CM4 system interrupt control 0xA824 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL522 CM4 system interrupt control 0xA828 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL523 CM4 system interrupt control 0xA82C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL524 CM4 system interrupt control 0xA830 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL525 CM4 system interrupt control 0xA834 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL526 CM4 system interrupt control 0xA838 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL527 CM4 system interrupt control 0xA83C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL528 CM4 system interrupt control 0xA840 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL529 CM4 system interrupt control 0xA844 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL53 CM4 system interrupt control 0xA0D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL530 CM4 system interrupt control 0xA848 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL531 CM4 system interrupt control 0xA84C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL532 CM4 system interrupt control 0xA850 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL533 CM4 system interrupt control 0xA854 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL534 CM4 system interrupt control 0xA858 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL535 CM4 system interrupt control 0xA85C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL536 CM4 system interrupt control 0xA860 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL537 CM4 system interrupt control 0xA864 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL538 CM4 system interrupt control 0xA868 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL539 CM4 system interrupt control 0xA86C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL54 CM4 system interrupt control 0xA0D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL540 CM4 system interrupt control 0xA870 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL541 CM4 system interrupt control 0xA874 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL542 CM4 system interrupt control 0xA878 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL543 CM4 system interrupt control 0xA87C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL544 CM4 system interrupt control 0xA880 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL545 CM4 system interrupt control 0xA884 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL546 CM4 system interrupt control 0xA888 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL547 CM4 system interrupt control 0xA88C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL548 CM4 system interrupt control 0xA890 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL549 CM4 system interrupt control 0xA894 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL55 CM4 system interrupt control 0xA0DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL550 CM4 system interrupt control 0xA898 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL551 CM4 system interrupt control 0xA89C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL552 CM4 system interrupt control 0xA8A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL553 CM4 system interrupt control 0xA8A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL554 CM4 system interrupt control 0xA8A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL555 CM4 system interrupt control 0xA8AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL556 CM4 system interrupt control 0xA8B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL557 CM4 system interrupt control 0xA8B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL558 CM4 system interrupt control 0xA8B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL559 CM4 system interrupt control 0xA8BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL56 CM4 system interrupt control 0xA0E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL560 CM4 system interrupt control 0xA8C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL561 CM4 system interrupt control 0xA8C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL562 CM4 system interrupt control 0xA8C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL563 CM4 system interrupt control 0xA8CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL564 CM4 system interrupt control 0xA8D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL565 CM4 system interrupt control 0xA8D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL566 CM4 system interrupt control 0xA8D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL567 CM4 system interrupt control 0xA8DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL568 CM4 system interrupt control 0xA8E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL569 CM4 system interrupt control 0xA8E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL57 CM4 system interrupt control 0xA0E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL570 CM4 system interrupt control 0xA8E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL571 CM4 system interrupt control 0xA8EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL572 CM4 system interrupt control 0xA8F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL573 CM4 system interrupt control 0xA8F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL574 CM4 system interrupt control 0xA8F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL575 CM4 system interrupt control 0xA8FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL576 CM4 system interrupt control 0xA900 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL577 CM4 system interrupt control 0xA904 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL578 CM4 system interrupt control 0xA908 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL579 CM4 system interrupt control 0xA90C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL58 CM4 system interrupt control 0xA0E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL580 CM4 system interrupt control 0xA910 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL581 CM4 system interrupt control 0xA914 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL582 CM4 system interrupt control 0xA918 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL583 CM4 system interrupt control 0xA91C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL584 CM4 system interrupt control 0xA920 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL585 CM4 system interrupt control 0xA924 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL586 CM4 system interrupt control 0xA928 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL587 CM4 system interrupt control 0xA92C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL588 CM4 system interrupt control 0xA930 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL589 CM4 system interrupt control 0xA934 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL59 CM4 system interrupt control 0xA0EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL590 CM4 system interrupt control 0xA938 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL591 CM4 system interrupt control 0xA93C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL592 CM4 system interrupt control 0xA940 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL593 CM4 system interrupt control 0xA944 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL594 CM4 system interrupt control 0xA948 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL595 CM4 system interrupt control 0xA94C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL596 CM4 system interrupt control 0xA950 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL597 CM4 system interrupt control 0xA954 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL598 CM4 system interrupt control 0xA958 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL599 CM4 system interrupt control 0xA95C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL6 CM4 system interrupt control 0xA018 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL60 CM4 system interrupt control 0xA0F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL600 CM4 system interrupt control 0xA960 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL601 CM4 system interrupt control 0xA964 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL602 CM4 system interrupt control 0xA968 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL603 CM4 system interrupt control 0xA96C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL604 CM4 system interrupt control 0xA970 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL605 CM4 system interrupt control 0xA974 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL606 CM4 system interrupt control 0xA978 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL607 CM4 system interrupt control 0xA97C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL608 CM4 system interrupt control 0xA980 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL609 CM4 system interrupt control 0xA984 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL61 CM4 system interrupt control 0xA0F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL610 CM4 system interrupt control 0xA988 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL611 CM4 system interrupt control 0xA98C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL612 CM4 system interrupt control 0xA990 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL613 CM4 system interrupt control 0xA994 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL614 CM4 system interrupt control 0xA998 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL615 CM4 system interrupt control 0xA99C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL616 CM4 system interrupt control 0xA9A0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL617 CM4 system interrupt control 0xA9A4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL618 CM4 system interrupt control 0xA9A8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL619 CM4 system interrupt control 0xA9AC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL62 CM4 system interrupt control 0xA0F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL620 CM4 system interrupt control 0xA9B0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL621 CM4 system interrupt control 0xA9B4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL622 CM4 system interrupt control 0xA9B8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL623 CM4 system interrupt control 0xA9BC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL624 CM4 system interrupt control 0xA9C0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL625 CM4 system interrupt control 0xA9C4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL626 CM4 system interrupt control 0xA9C8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL627 CM4 system interrupt control 0xA9CC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL628 CM4 system interrupt control 0xA9D0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL629 CM4 system interrupt control 0xA9D4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL63 CM4 system interrupt control 0xA0FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL630 CM4 system interrupt control 0xA9D8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL631 CM4 system interrupt control 0xA9DC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL632 CM4 system interrupt control 0xA9E0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL633 CM4 system interrupt control 0xA9E4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL634 CM4 system interrupt control 0xA9E8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL635 CM4 system interrupt control 0xA9EC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL636 CM4 system interrupt control 0xA9F0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL637 CM4 system interrupt control 0xA9F4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL638 CM4 system interrupt control 0xA9F8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL639 CM4 system interrupt control 0xA9FC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL64 CM4 system interrupt control 0xA100 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL640 CM4 system interrupt control 0xAA00 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL641 CM4 system interrupt control 0xAA04 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL642 CM4 system interrupt control 0xAA08 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL643 CM4 system interrupt control 0xAA0C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL644 CM4 system interrupt control 0xAA10 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL645 CM4 system interrupt control 0xAA14 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL646 CM4 system interrupt control 0xAA18 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL647 CM4 system interrupt control 0xAA1C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL648 CM4 system interrupt control 0xAA20 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL649 CM4 system interrupt control 0xAA24 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL65 CM4 system interrupt control 0xA104 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL650 CM4 system interrupt control 0xAA28 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL651 CM4 system interrupt control 0xAA2C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL652 CM4 system interrupt control 0xAA30 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL653 CM4 system interrupt control 0xAA34 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL654 CM4 system interrupt control 0xAA38 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL655 CM4 system interrupt control 0xAA3C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL656 CM4 system interrupt control 0xAA40 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL657 CM4 system interrupt control 0xAA44 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL658 CM4 system interrupt control 0xAA48 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL659 CM4 system interrupt control 0xAA4C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL66 CM4 system interrupt control 0xA108 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL660 CM4 system interrupt control 0xAA50 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL661 CM4 system interrupt control 0xAA54 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL662 CM4 system interrupt control 0xAA58 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL663 CM4 system interrupt control 0xAA5C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL664 CM4 system interrupt control 0xAA60 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL665 CM4 system interrupt control 0xAA64 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL666 CM4 system interrupt control 0xAA68 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL667 CM4 system interrupt control 0xAA6C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL668 CM4 system interrupt control 0xAA70 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL669 CM4 system interrupt control 0xAA74 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL67 CM4 system interrupt control 0xA10C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL670 CM4 system interrupt control 0xAA78 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL671 CM4 system interrupt control 0xAA7C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL672 CM4 system interrupt control 0xAA80 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL673 CM4 system interrupt control 0xAA84 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL674 CM4 system interrupt control 0xAA88 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL675 CM4 system interrupt control 0xAA8C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL676 CM4 system interrupt control 0xAA90 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL677 CM4 system interrupt control 0xAA94 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL678 CM4 system interrupt control 0xAA98 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL679 CM4 system interrupt control 0xAA9C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL68 CM4 system interrupt control 0xA110 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL680 CM4 system interrupt control 0xAAA0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL681 CM4 system interrupt control 0xAAA4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL682 CM4 system interrupt control 0xAAA8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL683 CM4 system interrupt control 0xAAAC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL684 CM4 system interrupt control 0xAAB0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL685 CM4 system interrupt control 0xAAB4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL686 CM4 system interrupt control 0xAAB8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL687 CM4 system interrupt control 0xAABC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL688 CM4 system interrupt control 0xAAC0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL689 CM4 system interrupt control 0xAAC4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL69 CM4 system interrupt control 0xA114 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL690 CM4 system interrupt control 0xAAC8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL691 CM4 system interrupt control 0xAACC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL692 CM4 system interrupt control 0xAAD0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL693 CM4 system interrupt control 0xAAD4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL694 CM4 system interrupt control 0xAAD8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL695 CM4 system interrupt control 0xAADC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL696 CM4 system interrupt control 0xAAE0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL697 CM4 system interrupt control 0xAAE4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL698 CM4 system interrupt control 0xAAE8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL699 CM4 system interrupt control 0xAAEC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL7 CM4 system interrupt control 0xA01C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL70 CM4 system interrupt control 0xA118 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL700 CM4 system interrupt control 0xAAF0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL701 CM4 system interrupt control 0xAAF4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL702 CM4 system interrupt control 0xAAF8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL703 CM4 system interrupt control 0xAAFC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL704 CM4 system interrupt control 0xAB00 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL705 CM4 system interrupt control 0xAB04 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL706 CM4 system interrupt control 0xAB08 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL707 CM4 system interrupt control 0xAB0C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL708 CM4 system interrupt control 0xAB10 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL709 CM4 system interrupt control 0xAB14 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL71 CM4 system interrupt control 0xA11C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL710 CM4 system interrupt control 0xAB18 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL711 CM4 system interrupt control 0xAB1C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL712 CM4 system interrupt control 0xAB20 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL713 CM4 system interrupt control 0xAB24 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL714 CM4 system interrupt control 0xAB28 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL715 CM4 system interrupt control 0xAB2C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL716 CM4 system interrupt control 0xAB30 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL717 CM4 system interrupt control 0xAB34 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL718 CM4 system interrupt control 0xAB38 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL719 CM4 system interrupt control 0xAB3C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL72 CM4 system interrupt control 0xA120 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL720 CM4 system interrupt control 0xAB40 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL721 CM4 system interrupt control 0xAB44 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL722 CM4 system interrupt control 0xAB48 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL723 CM4 system interrupt control 0xAB4C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL724 CM4 system interrupt control 0xAB50 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL725 CM4 system interrupt control 0xAB54 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL726 CM4 system interrupt control 0xAB58 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL727 CM4 system interrupt control 0xAB5C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL728 CM4 system interrupt control 0xAB60 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL729 CM4 system interrupt control 0xAB64 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL73 CM4 system interrupt control 0xA124 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL730 CM4 system interrupt control 0xAB68 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL731 CM4 system interrupt control 0xAB6C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL732 CM4 system interrupt control 0xAB70 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL733 CM4 system interrupt control 0xAB74 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL734 CM4 system interrupt control 0xAB78 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL735 CM4 system interrupt control 0xAB7C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL736 CM4 system interrupt control 0xAB80 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL737 CM4 system interrupt control 0xAB84 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL738 CM4 system interrupt control 0xAB88 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL739 CM4 system interrupt control 0xAB8C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL74 CM4 system interrupt control 0xA128 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL740 CM4 system interrupt control 0xAB90 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL741 CM4 system interrupt control 0xAB94 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL742 CM4 system interrupt control 0xAB98 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL743 CM4 system interrupt control 0xAB9C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL744 CM4 system interrupt control 0xABA0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL745 CM4 system interrupt control 0xABA4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL746 CM4 system interrupt control 0xABA8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL747 CM4 system interrupt control 0xABAC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL748 CM4 system interrupt control 0xABB0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL749 CM4 system interrupt control 0xABB4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL75 CM4 system interrupt control 0xA12C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL750 CM4 system interrupt control 0xABB8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL751 CM4 system interrupt control 0xABBC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL752 CM4 system interrupt control 0xABC0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL753 CM4 system interrupt control 0xABC4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL754 CM4 system interrupt control 0xABC8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL755 CM4 system interrupt control 0xABCC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL756 CM4 system interrupt control 0xABD0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL757 CM4 system interrupt control 0xABD4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL758 CM4 system interrupt control 0xABD8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL759 CM4 system interrupt control 0xABDC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL76 CM4 system interrupt control 0xA130 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL760 CM4 system interrupt control 0xABE0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL761 CM4 system interrupt control 0xABE4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL762 CM4 system interrupt control 0xABE8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL763 CM4 system interrupt control 0xABEC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL764 CM4 system interrupt control 0xABF0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL765 CM4 system interrupt control 0xABF4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL766 CM4 system interrupt control 0xABF8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL767 CM4 system interrupt control 0xABFC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL768 CM4 system interrupt control 0xAC00 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL769 CM4 system interrupt control 0xAC04 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL77 CM4 system interrupt control 0xA134 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL770 CM4 system interrupt control 0xAC08 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL771 CM4 system interrupt control 0xAC0C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL772 CM4 system interrupt control 0xAC10 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL773 CM4 system interrupt control 0xAC14 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL774 CM4 system interrupt control 0xAC18 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL775 CM4 system interrupt control 0xAC1C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL776 CM4 system interrupt control 0xAC20 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL777 CM4 system interrupt control 0xAC24 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL778 CM4 system interrupt control 0xAC28 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL779 CM4 system interrupt control 0xAC2C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL78 CM4 system interrupt control 0xA138 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL780 CM4 system interrupt control 0xAC30 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL781 CM4 system interrupt control 0xAC34 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL782 CM4 system interrupt control 0xAC38 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL783 CM4 system interrupt control 0xAC3C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL784 CM4 system interrupt control 0xAC40 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL785 CM4 system interrupt control 0xAC44 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL786 CM4 system interrupt control 0xAC48 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL787 CM4 system interrupt control 0xAC4C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL788 CM4 system interrupt control 0xAC50 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL789 CM4 system interrupt control 0xAC54 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL79 CM4 system interrupt control 0xA13C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL790 CM4 system interrupt control 0xAC58 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL791 CM4 system interrupt control 0xAC5C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL792 CM4 system interrupt control 0xAC60 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL793 CM4 system interrupt control 0xAC64 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL794 CM4 system interrupt control 0xAC68 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL795 CM4 system interrupt control 0xAC6C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL796 CM4 system interrupt control 0xAC70 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL797 CM4 system interrupt control 0xAC74 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL798 CM4 system interrupt control 0xAC78 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL799 CM4 system interrupt control 0xAC7C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL8 CM4 system interrupt control 0xA020 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL80 CM4 system interrupt control 0xA140 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL800 CM4 system interrupt control 0xAC80 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL801 CM4 system interrupt control 0xAC84 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL802 CM4 system interrupt control 0xAC88 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL803 CM4 system interrupt control 0xAC8C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL804 CM4 system interrupt control 0xAC90 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL805 CM4 system interrupt control 0xAC94 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL806 CM4 system interrupt control 0xAC98 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL807 CM4 system interrupt control 0xAC9C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL808 CM4 system interrupt control 0xACA0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL809 CM4 system interrupt control 0xACA4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL81 CM4 system interrupt control 0xA144 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL810 CM4 system interrupt control 0xACA8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL811 CM4 system interrupt control 0xACAC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL812 CM4 system interrupt control 0xACB0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL813 CM4 system interrupt control 0xACB4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL814 CM4 system interrupt control 0xACB8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL815 CM4 system interrupt control 0xACBC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL816 CM4 system interrupt control 0xACC0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL817 CM4 system interrupt control 0xACC4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL818 CM4 system interrupt control 0xACC8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL819 CM4 system interrupt control 0xACCC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL82 CM4 system interrupt control 0xA148 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL820 CM4 system interrupt control 0xACD0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL821 CM4 system interrupt control 0xACD4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL822 CM4 system interrupt control 0xACD8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL823 CM4 system interrupt control 0xACDC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL824 CM4 system interrupt control 0xACE0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL825 CM4 system interrupt control 0xACE4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL826 CM4 system interrupt control 0xACE8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL827 CM4 system interrupt control 0xACEC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL828 CM4 system interrupt control 0xACF0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL829 CM4 system interrupt control 0xACF4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL83 CM4 system interrupt control 0xA14C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL830 CM4 system interrupt control 0xACF8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL831 CM4 system interrupt control 0xACFC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL832 CM4 system interrupt control 0xAD00 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL833 CM4 system interrupt control 0xAD04 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL834 CM4 system interrupt control 0xAD08 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL835 CM4 system interrupt control 0xAD0C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL836 CM4 system interrupt control 0xAD10 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL837 CM4 system interrupt control 0xAD14 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL838 CM4 system interrupt control 0xAD18 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL839 CM4 system interrupt control 0xAD1C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL84 CM4 system interrupt control 0xA150 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL840 CM4 system interrupt control 0xAD20 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL841 CM4 system interrupt control 0xAD24 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL842 CM4 system interrupt control 0xAD28 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL843 CM4 system interrupt control 0xAD2C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL844 CM4 system interrupt control 0xAD30 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL845 CM4 system interrupt control 0xAD34 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL846 CM4 system interrupt control 0xAD38 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL847 CM4 system interrupt control 0xAD3C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL848 CM4 system interrupt control 0xAD40 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL849 CM4 system interrupt control 0xAD44 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL85 CM4 system interrupt control 0xA154 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL850 CM4 system interrupt control 0xAD48 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL851 CM4 system interrupt control 0xAD4C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL852 CM4 system interrupt control 0xAD50 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL853 CM4 system interrupt control 0xAD54 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL854 CM4 system interrupt control 0xAD58 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL855 CM4 system interrupt control 0xAD5C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL856 CM4 system interrupt control 0xAD60 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL857 CM4 system interrupt control 0xAD64 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL858 CM4 system interrupt control 0xAD68 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL859 CM4 system interrupt control 0xAD6C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL86 CM4 system interrupt control 0xA158 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL860 CM4 system interrupt control 0xAD70 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL861 CM4 system interrupt control 0xAD74 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL862 CM4 system interrupt control 0xAD78 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL863 CM4 system interrupt control 0xAD7C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL864 CM4 system interrupt control 0xAD80 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL865 CM4 system interrupt control 0xAD84 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL866 CM4 system interrupt control 0xAD88 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL867 CM4 system interrupt control 0xAD8C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL868 CM4 system interrupt control 0xAD90 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL869 CM4 system interrupt control 0xAD94 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL87 CM4 system interrupt control 0xA15C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL870 CM4 system interrupt control 0xAD98 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL871 CM4 system interrupt control 0xAD9C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL872 CM4 system interrupt control 0xADA0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL873 CM4 system interrupt control 0xADA4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL874 CM4 system interrupt control 0xADA8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL875 CM4 system interrupt control 0xADAC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL876 CM4 system interrupt control 0xADB0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL877 CM4 system interrupt control 0xADB4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL878 CM4 system interrupt control 0xADB8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL879 CM4 system interrupt control 0xADBC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL88 CM4 system interrupt control 0xA160 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL880 CM4 system interrupt control 0xADC0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL881 CM4 system interrupt control 0xADC4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL882 CM4 system interrupt control 0xADC8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL883 CM4 system interrupt control 0xADCC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL884 CM4 system interrupt control 0xADD0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL885 CM4 system interrupt control 0xADD4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL886 CM4 system interrupt control 0xADD8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL887 CM4 system interrupt control 0xADDC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL888 CM4 system interrupt control 0xADE0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL889 CM4 system interrupt control 0xADE4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL89 CM4 system interrupt control 0xA164 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL890 CM4 system interrupt control 0xADE8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL891 CM4 system interrupt control 0xADEC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL892 CM4 system interrupt control 0xADF0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL893 CM4 system interrupt control 0xADF4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL894 CM4 system interrupt control 0xADF8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL895 CM4 system interrupt control 0xADFC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL896 CM4 system interrupt control 0xAE00 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL897 CM4 system interrupt control 0xAE04 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL898 CM4 system interrupt control 0xAE08 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL899 CM4 system interrupt control 0xAE0C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL9 CM4 system interrupt control 0xA024 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL90 CM4 system interrupt control 0xA168 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL900 CM4 system interrupt control 0xAE10 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL901 CM4 system interrupt control 0xAE14 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL902 CM4 system interrupt control 0xAE18 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL903 CM4 system interrupt control 0xAE1C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL904 CM4 system interrupt control 0xAE20 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL905 CM4 system interrupt control 0xAE24 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL906 CM4 system interrupt control 0xAE28 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL907 CM4 system interrupt control 0xAE2C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL908 CM4 system interrupt control 0xAE30 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL909 CM4 system interrupt control 0xAE34 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL91 CM4 system interrupt control 0xA16C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL910 CM4 system interrupt control 0xAE38 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL911 CM4 system interrupt control 0xAE3C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL912 CM4 system interrupt control 0xAE40 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL913 CM4 system interrupt control 0xAE44 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL914 CM4 system interrupt control 0xAE48 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL915 CM4 system interrupt control 0xAE4C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL916 CM4 system interrupt control 0xAE50 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL917 CM4 system interrupt control 0xAE54 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL918 CM4 system interrupt control 0xAE58 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL919 CM4 system interrupt control 0xAE5C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL92 CM4 system interrupt control 0xA170 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL920 CM4 system interrupt control 0xAE60 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL921 CM4 system interrupt control 0xAE64 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL922 CM4 system interrupt control 0xAE68 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL923 CM4 system interrupt control 0xAE6C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL924 CM4 system interrupt control 0xAE70 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL925 CM4 system interrupt control 0xAE74 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL926 CM4 system interrupt control 0xAE78 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL927 CM4 system interrupt control 0xAE7C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL928 CM4 system interrupt control 0xAE80 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL929 CM4 system interrupt control 0xAE84 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL93 CM4 system interrupt control 0xA174 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL930 CM4 system interrupt control 0xAE88 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL931 CM4 system interrupt control 0xAE8C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL932 CM4 system interrupt control 0xAE90 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL933 CM4 system interrupt control 0xAE94 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL934 CM4 system interrupt control 0xAE98 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL935 CM4 system interrupt control 0xAE9C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL936 CM4 system interrupt control 0xAEA0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL937 CM4 system interrupt control 0xAEA4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL938 CM4 system interrupt control 0xAEA8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL939 CM4 system interrupt control 0xAEAC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL94 CM4 system interrupt control 0xA178 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL940 CM4 system interrupt control 0xAEB0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL941 CM4 system interrupt control 0xAEB4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL942 CM4 system interrupt control 0xAEB8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL943 CM4 system interrupt control 0xAEBC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL944 CM4 system interrupt control 0xAEC0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL945 CM4 system interrupt control 0xAEC4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL946 CM4 system interrupt control 0xAEC8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL947 CM4 system interrupt control 0xAECC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL948 CM4 system interrupt control 0xAED0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL949 CM4 system interrupt control 0xAED4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL95 CM4 system interrupt control 0xA17C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL950 CM4 system interrupt control 0xAED8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL951 CM4 system interrupt control 0xAEDC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL952 CM4 system interrupt control 0xAEE0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL953 CM4 system interrupt control 0xAEE4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL954 CM4 system interrupt control 0xAEE8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL955 CM4 system interrupt control 0xAEEC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL956 CM4 system interrupt control 0xAEF0 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL957 CM4 system interrupt control 0xAEF4 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL958 CM4 system interrupt control 0xAEF8 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL959 CM4 system interrupt control 0xAEFC 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL96 CM4 system interrupt control 0xA180 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL960 CM4 system interrupt control 0xAF00 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL961 CM4 system interrupt control 0xAF04 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL962 CM4 system interrupt control 0xAF08 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL963 CM4 system interrupt control 0xAF0C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL964 CM4 system interrupt control 0xAF10 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL965 CM4 system interrupt control 0xAF14 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL966 CM4 system interrupt control 0xAF18 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL967 CM4 system interrupt control 0xAF1C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL968 CM4 system interrupt control 0xAF20 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL969 CM4 system interrupt control 0xAF24 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL97 CM4 system interrupt control 0xA184 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL970 CM4 system interrupt control 0xAF28 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL971 CM4 system interrupt control 0xAF2C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL972 CM4 system interrupt control 0xAF30 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL973 CM4 system interrupt control 0xAF34 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL974 CM4 system interrupt control 0xAF38 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL975 CM4 system interrupt control 0xAF3C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL976 CM4 system interrupt control 0xAF40 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL977 CM4 system interrupt control 0xAF44 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL978 CM4 system interrupt control 0xAF48 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL979 CM4 system interrupt control 0xAF4C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL98 CM4 system interrupt control 0xA188 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL980 CM4 system interrupt control 0xAF50 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL981 CM4 system interrupt control 0xAF54 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL982 CM4 system interrupt control 0xAF58 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL983 CM4 system interrupt control 0xAF5C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL984 CM4 system interrupt control 0xAF60 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL985 CM4 system interrupt control 0xAF64 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL986 CM4 system interrupt control 0xAF68 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL987 CM4 system interrupt control 0xAF6C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL988 CM4 system interrupt control 0xAF70 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL989 CM4 system interrupt control 0xAF74 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL99 CM4 system interrupt control 0xA18C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL990 CM4 system interrupt control 0xAF78 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL991 CM4 system interrupt control 0xAF7C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL992 CM4 system interrupt control 0xAF80 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL993 CM4 system interrupt control 0xAF84 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL994 CM4 system interrupt control 0xAF88 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL995 CM4 system interrupt control 0xAF8C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL996 CM4 system interrupt control 0xAF90 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL997 CM4 system interrupt control 0xAF94 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL998 CM4 system interrupt control 0xAF98 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_SYSTEM_INT_CTL999 CM4 system interrupt control 0xAF9C 32 read-write n 0x0 0x0 CPU_INT_IDX N/A 0 3 read-write CPU_INT_VALID N/A 31 32 read-write CM4_VECTOR_TABLE_BASE CM4 vector table base 0x200 32 read-write n 0x0 0x0 ADDR22 Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. Note: the CM4 vector table is at an address that is a 1024 B multiple. 10 32 read-write DP_STATUS Debug port status 0x1410 32 read-only n 0x0 0x0 SWJ_CONNECTED Specifies if the SWJ debug port is connected i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active. 0 1 read-only SWJ_DEBUG_EN Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled. 1 2 read-only SWJ_JTAG_SEL Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected. 2 3 read-only ECC_CTL ECC control 0x13C8 32 read-write n 0x0 0x0 PARITY ECC parity to use for ECC error injection at address WORD_ADDR. 25 32 read-write WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. This field needs to be written with the offset address within the memory, divided by 4. For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010. 0 25 read-write IDENTITY Identity 0x0 32 read-only n 0x0 0x0 MS This field specifies the bus master identifier of the transfer that reads the register. 8 12 read-only NS This field specifies the security setting ('0': secure mode '1': non-secure mode) of the transfer that reads the register. 1 2 read-only P This field specifies the privileged setting ('0': user mode '1': privileged mode) of the transfer that reads the register. 0 1 read-only PC This field specifies the protection context of the transfer that reads the register. 4 8 read-only MBIST_STAT Memory BIST status 0x1704 32 read-only n 0x0 0x0 SFP_FAIL Report status of the BIST run, only valid if SFP_READY=1 1 2 read-only SFP_READY Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. 0 1 read-only PRODUCT_ID Product identifier and version (same as CoreSight RomTables) 0x1400 32 read-only n 0x0 0x0 FAMILY_ID Family ID. Common ID for a product family. 0 12 read-only MAJOR_REV Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) 16 20 read-only MINOR_REV Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) 20 24 read-only PROTECTION Protection status 0x20C4 32 read-write n 0x0 0x0 STATE Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transitions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field. 0 3 read-write RAM0_CTL0 RAM 0 control 0x1300 32 read-write n 0x0 0x0 ECC_AUTO_CORRECT HW ECC autocorrect functionality: '0': Disabled. '1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. 17 18 read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. 16 17 read-write ECC_INJ_EN Enable error injection for system SRAM 0. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. 18 19 read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. 8 10 read-write SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. 0 2 read-write RAM0_PWR_MACRO_CTL0 RAM 0 power control 0x1340 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL1 RAM 0 power control 0x1344 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL10 RAM 0 power control 0x1368 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL11 RAM 0 power control 0x136C 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL12 RAM 0 power control 0x1370 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL13 RAM 0 power control 0x1374 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL14 RAM 0 power control 0x1378 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL15 RAM 0 power control 0x137C 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL2 RAM 0 power control 0x1348 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL3 RAM 0 power control 0x134C 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL4 RAM 0 power control 0x1350 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL5 RAM 0 power control 0x1354 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL6 RAM 0 power control 0x1358 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL7 RAM 0 power control 0x135C 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL8 RAM 0 power control 0x1360 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_PWR_MACRO_CTL9 RAM 0 power control 0x1364 32 read-write n 0x0 0x0 PWR_MODE SRAM Power mode. 0 2 read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only RAM0_STATUS RAM 0 status 0x1304 32 read-only n 0x0 0x0 WB_EMPTY Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. '0': Write buffer NOT empty. '1': Write buffer empty. Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). 0 1 read-only RAM1_CTL0 RAM 1 control 0x1380 32 read-write n 0x0 0x0 ECC_AUTO_CORRECT See RAM0_CTL. 17 18 read-write ECC_EN See RAM0_CTL. 16 17 read-write ECC_INJ_EN See RAM0_CTL. 18 19 read-write FAST_WS See RAM0_CTL. 8 10 read-write SLOW_WS See RAM0_CTL. 0 2 read-write RAM1_PWR_CTL RAM 1 power control 0x1388 32 read-write n 0x0 0x0 PWR_MODE Power mode. 0 2 read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. 16 32 read-only RAM1_STATUS RAM 1 status 0x1384 32 read-only n 0x0 0x0 WB_EMPTY See RAM0_STATUS. 0 1 read-only RAM2_CTL0 RAM 2 control 0x13A0 32 read-write n 0x0 0x0 ECC_AUTO_CORRECT See RAM0_CTL. 17 18 read-write ECC_EN See RAM0_CTL. 16 17 read-write ECC_INJ_EN See RAM0_CTL. 18 19 read-write FAST_WS See RAM0_CTL. 8 10 read-write SLOW_WS See RAM0_CTL. 0 2 read-write RAM2_PWR_CTL RAM 2 power control 0x13A8 32 read-write n 0x0 0x0 PWR_MODE Power mode. 0 2 read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. 16 32 read-only RAM2_STATUS RAM 2 status 0x13A4 32 read-only n 0x0 0x0 WB_EMPTY See RAM0_STATUS. 0 1 read-only RAM_PWR_DELAY_CTL Power up delay used for all SRAM power domains 0x13C0 32 read-write n 0x0 0x0 UP Number clock cycles (clk_slow) delay needed after power domain power up 0 10 read-write ROM_CTL ROM control 0x13C4 32 read-write n 0x0 0x0 FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. ROM_CTL.FAST_WS = '0' when clk_hf <= clk_hf_max. 8 10 read-write SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. ROM_CTL.SLOW_WS = '0' when clk_hf <=100 MHz. ROM_CTL.SLOW_WS = '1' when 100MHz < clk_hf <=clk_hf_max. Note: clk_hf_max depends on the target device. Refer datasheet. 0 2 read-write SYSTICK_CTL SysTick timer control 0x1600 32 read-write n 0x0 0x0 CLOCK_SOURCE Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. 24 26 read-write NOREF Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. 31 32 read-write SKEW Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise. 30 31 read-write TENMS Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. 0 24 read-write TRIM_RAM_CTL RAM trim control 0x2104 32 read-write n 0x0 0x0 TRIM N/A 0 32 read-write TRIM_ROM_CTL ROM trim control 0x2100 32 read-write n 0x0 0x0 TRIM N/A 0 32 read-write UDB_PWR_CTL UDB power control 0x300 32 read-write n 0x0 0x0 PWR_MODE Set Power mode for UDBs 0 2 read-write OFF See CM4_PWR_CTL 0 RESET See CM4_PWR_CTL 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. 16 32 read-only UDB_PWR_DELAY_CTL UDB power control 0x304 32 read-write n 0x0 0x0 UP Number clock cycles delay needed after power domain power up 0 10 read-write FAULT Fault structures FAULT 0x0 0x0 0x10000 registers n CTL Fault control 0x0 32 read-write n 0x0 0x0 OUT_EN IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. 1 2 read-write RESET_REQ_EN Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. 2 3 read-write TR_EN Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). 0 1 read-write DATA0 Fault data 0x10 32 read-write n 0x0 0x0 DATA Captured fault source data. Note: the DATA registers can only be written when STATUS.VALID is '0'. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. 0 32 read-write DATA1 Fault data 0x14 32 read-write n 0x0 0x0 DATA Captured fault source data. Note: the DATA registers can only be written when STATUS.VALID is '0'. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. 0 32 read-write DATA2 Fault data 0x18 32 read-write n 0x0 0x0 DATA Captured fault source data. Note: the DATA registers can only be written when STATUS.VALID is '0'. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. 0 32 read-write DATA3 Fault data 0x1C 32 read-write n 0x0 0x0 DATA Captured fault source data. Note: the DATA registers can only be written when STATUS.VALID is '0'. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. 0 32 read-write INTR Interrupt 0xC0 32 read-write n 0x0 0x0 FAULT This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source data. SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). 0 1 read-write INTR_MASK Interrupt mask 0xC8 32 read-write n 0x0 0x0 FAULT Mask bit for corresponding field in the INTR register. 0 1 read-write INTR_MASKED Interrupt masked 0xCC 32 read-only n 0x0 0x0 FAULT Logical and of corresponding INTR and INTR_MASK fields. 0 1 read-only INTR_SET Interrupt set 0xC4 32 read-write n 0x0 0x0 FAULT SW writes a '1' to this field to set the corresponding field in the INTR register. 0 1 read-write MASK0 Fault mask 0 0x50 32 read-write n 0x0 0x0 SOURCE Fault source enables: Bits 31-0: Fault sources 31 to 0. 0 32 read-write MASK1 Fault mask 1 0x54 32 read-write n 0x0 0x0 SOURCE Fault source enables: Bits 31-0: Fault sources 63 to 32. 0 32 read-write MASK2 Fault mask 2 0x58 32 read-write n 0x0 0x0 SOURCE Fault source enables: Bits 31-0: Fault sources 95 to 64. 0 32 read-write PENDING0 Fault pending 0 0x40 32 read-only n 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. Bit 4: DMA controller MPU. ... Bit 15: DAP MPU. Bit 16: CM4 system bus MPU. Bit 17: CM4 code bus MPU (for non FLASH controller accesses). Bit 18: CM4 code bus MPU (for FLASH controller accesses). 0 32 read-only PENDING1 Fault pending 1 0x44 32 read-only n 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 16 - 31: See STATUS register. 0 32 read-only PENDING2 Fault pending 2 0x48 32 read-only n 0x0 0x0 SOURCE This field specifies the following sources: Bit 0 - 31: See STATUS register. 0 32 read-only STATUS Fault status 0xC 32 read-write n 0x0 0x0 IDX The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. 0 7 read-write VALID Valid indication: '0': Invalid. '1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: - STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0' the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) 31 32 read-write FLASHC Flash controller FLASHC 0x0 0x0 0x10000 registers n ACLK_CTL MPCON clock 0x3C 32 write-only n 0x0 0x0 ACLK_GEN A write to this register generates the clock pulse for HV control registers (mpcon outputs) 0 1 write-only ANA_CTL0 Analog control 0 0x18 32 read-write n 0x0 0x0 CSLDAC Trimming of common source line DAC. 8 11 read-write FLIP_AMUXBUS_AB Flips amuxbusa and amuxbusb 0: amuxbusa, amuxbusb 1: amuxbusb, amuxbusb 11 12 read-write MDAC Trimming of the output margin Voltage as a function of Vpos and Vneg. 0 8 read-write NDAC_MIN NDAC staircase min value 12 16 read-write PDAC_MIN PDAC staircase min value 16 20 read-write SCALE_PRG_PEOFF PROG and PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 30 32 read-write SCALE_PRG_PEON PROG and PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 28 30 read-write SCALE_PRG_SEQ01 PROG and PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 20 22 read-write SCALE_PRG_SEQ12 PROG and PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 22 24 read-write SCALE_PRG_SEQ23 PROG and PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 24 26 read-write SCALE_SEQ30 PROG and PRE_PROG and ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 26 28 read-write ANA_CTL1 Analog control 1 0x1C 32 read-write n 0x0 0x0 NDAC_MAX Ndac Max Value.Trimming of negative pump output Voltage. 0 4 read-write NDAC_STEP Ndac step increment 4 8 read-write NPDAC_STEP_TIME Ndac/Pdac step duration: (1uS .. 255uS) * 8 When = 0 N/PDAC_MAX control the pumps 16 24 read-write NPDAC_ZERO_TIME Ndac/Pdac LO duration: (1uS .. 255uS) * 8 When 0, N/PDAC don't return to 0 24 32 read-write PDAC_MAX Pdac Max Value.Trimming of positive pump output Voltage: 8 12 read-write PDAC_STEP Pdac step increment 12 16 read-write BOOKMARK Bookmark register - keeps the current FW HV seq 0xC 32 read-write n 0x0 0x0 BOOKMARK Used by FW. Keeps the Current HV cycle sequence 0 32 read-write CAL_CTL0 Cal control BG LO trim bits 0x50 32 read-write n 0x0 0x0 CDAC_LO_HV LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. 5 8 read-write ICREF_TC_TRIM_LO_HV LO Bandgap Current Temperature Compensation trim control 16 19 read-write IPREF_TRIMA_LO_HV Adds 100-150nA boost on IPREF_LO 19 20 read-write VBG_TC_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control 13 16 read-write VBG_TRIM_LO_HV LO Bandgap Voltage trim control. 8 13 read-write VCT_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control. 0 5 read-write CAL_CTL1 Cal control BG HI trim bits 0x54 32 read-write n 0x0 0x0 CDAC_HI_HV HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. 5 8 read-write ICREF_TC_TRIM_HI_HV HI Bandgap Current Temperature Compensation trim control. 16 19 read-write IPREF_TRIMA_HI_HV Adds 100-150nA boost on IPREF_HI 19 20 read-write VBG_TC_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. 13 16 read-write VBG_TRIM_HI_HV HI Bandgap Voltage trim control. 8 13 read-write VCT_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. 0 5 read-write CAL_CTL2 Cal control BG LO and HI trim bits 0x58 32 read-write n 0x0 0x0 ICREF_TRIM_HI_HV HI Bandgap Current trim control. 5 10 read-write ICREF_TRIM_LO_HV LO Bandgap Current trim control. 0 5 read-write IPREF_TRIM_HI_HV HI Bandgap IPTAT trim control. 15 20 read-write IPREF_TRIM_LO_HV LO Bandgap IPTAT trim control. 10 15 read-write CAL_CTL3 Cal control osc trim bits, idac, sdac, itim 0x5C 32 read-write n 0x0 0x0 BGHI_EN_HV 0: Normal (Automatic change over from HI to LO) 1: Force enable HI Bandgap When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active 16 17 read-write BGLO_EN_HV 0: Normal (Automatic change over from HI to LO) 1: Force enable LO Bandgap 15 16 read-write CL_ISO_DIS_HV 0: The internal logic controls the CL isolation 1: Forces CL bypass 17 18 read-write FDIV_TRIM_HV FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. Following are the clock frequencies seen by doubler 00: F = 1MHz 01: F = 0.5MHz 10: F = 2MHz 11: F = 4MHz 10 12 read-write IPREF_TC_HV 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA 1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA 6 7 read-write IREF_SEL_HV Current reference: 0: internal current reference 1: external current reference 8 9 read-write LP_ULP_SW_HV LP<-->ULP switch for trim signals: 0: LP 1: ULP 19 20 read-write OSC_RANGE_TRIM_HV 0: Oscillator High Frequency Range 1: Oscillator Low Frequency range 4 5 read-write OSC_TRIM_HV Flash macro pump clock trim control. 0 4 read-write REG_ACT_HV 0: VBST regulator will operate in active/standby mode based on control signal. 1: Forces the VBST regulator in active mode all the time 9 10 read-write R_GRANT_EN_HV 0: r_grant handshake disabled, r_grant always 1. 1: r_grand handshake enabled 18 19 read-write TURBO_PULSEW_HV Turbo pulse width trim (Typical) 00: 40 us 01: 20 us 10: 15 us 11: 8 us 13 15 read-write VDDHI_HV 0: vdd < 2.3V 1: vdd >= 2.3V '0' setting can used for vdd > 2.3V also, but with a current penalty. 12 13 read-write VPROT_ACT_HV Forces VPROT in active mode all the time 5 6 read-write VREF_SEL_HV Voltage reference: 0: internal bandgap reference 1: external voltage reference 7 8 read-write CAL_CTL4 Cal Control Vlim, SA, fdiv, reg_act 0x60 32 read-write n 0x0 0x0 AUTO_HVPULSE_HV 0: HV Pulse controlled by FW 1: HV Pulse controlled by Hardware 18 19 read-write FM_READY_DEL_ULP_HV 00: Default : delay 1ns 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us 13 15 read-write IDAC_ULP_HV Sets the sense current reference offset value. Refer to trim tables for details. 2 6 read-write ITIM_ULP_HV Trimming of timing current 8 13 read-write READY_RESTART_N_HV Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only. 16 17 read-write SDAC_ULP_HV Sets the sense current reference temp slope. Refer to trim tables for details. 6 8 read-write SPARE451_ULP_HV N/A 15 16 read-write UGB_EN_HV UGB enable in TM control 19 20 read-write VBST_S_DIS_HV 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. 1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector. 17 18 read-write VLIM_TRIM_ULP_HV VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV 0 2 read-write CAL_CTL5 Cal control 0x64 32 read-write n 0x0 0x0 AMUX_SEL_HV Amux Select in AMUX_UGB 00: Bypass UGB for both amuxbusa and amuxbusb 01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. 10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. 11: UGB Calibrate mode 18 20 read-write FM_READY_DEL_LP_HV 00: Delayed by 1us 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us 13 15 read-write IDAC_LP_HV Sets the sense current reference offset value. Refer to trim tables for details. 2 6 read-write ITIM_LP_HV Trimming of timing current 8 13 read-write SDAC_LP_HV Sets the sense current reference temp slope. Refer to trim tables for details. 6 8 read-write SPARE451_LP_HV N/A 15 16 read-write SPARE52_HV N/A 16 18 read-write VLIM_TRIM_LP_HV VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV 0 2 read-write CAL_CTL6 SA trim LP/ULP 0x68 32 read-write n 0x0 0x0 SA_CTL_TRIM_T1_LP_HV clk_trk delay 10 11 read-write SA_CTL_TRIM_T1_ULP_HV clk_trk delay 0 1 read-write SA_CTL_TRIM_T4_LP_HV SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim) 11 14 read-write SA_CTL_TRIM_T4_ULP_HV SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim) 1 4 read-write SA_CTL_TRIM_T5_LP_HV SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim) 14 17 read-write SA_CTL_TRIM_T5_ULP_HV SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim) 4 7 read-write SA_CTL_TRIM_T6_LP_HV SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim) 17 19 read-write SA_CTL_TRIM_T6_ULP_HV SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim) 7 9 read-write SA_CTL_TRIM_T8_LP_HV saen3 pulse width trim (Current trim) 19 20 read-write SA_CTL_TRIM_T8_ULP_HV saen3 pulse width trim (Current trim) 9 10 read-write CAL_CTL7 Cal control 0x6C 32 read-write n 0x0 0x0 DISABLE_LOAD_ONCE_HV 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. 1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register. 7 8 read-write ERSX8_CLK_SEL_HV Clock frequency into the ersx8 shift register block 00: Oscillator clock 01: Oscillator clock / 2 10: Oscillator clock / 4 11: Oscillator clock 0 2 read-write ERSX8_EN_ALL_HV 0': Staggered turn on/off of GWL 1: GWL are turned on/off at the same time (old FM legacy) 6 7 read-write FM_ACTIVE_HV 0: Normal operation 1: Forces FM SYS in active mode 2 3 read-write FM_READY_DIS_HV 0': fm ready is enabled 1: fm ready is disabled (fm_ready is always '1') 5 6 read-write NPDAC_HWCTL_DIS_HV 0': ndac, pdac staircase hardware controlled 1: ndac, pdac staircase disabled. Enables FW control. 4 5 read-write SPARE7_HV N/A 8 10 read-write SPARE7_LP_HV N/A 15 20 read-write SPARE7_ULP_HV N/A 10 15 read-write TURBO_EXT_HV 0: Normal operation 1: Uses external turbo pulse 3 4 read-write CM0_CA_CTL0 CM0+ cache control 0x400 32 read-write n 0x0 0x0 CA_EN Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled. 31 32 read-write PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled i.e. ENABLED is '1'. 30 31 read-write RAM_ECC_EN Enable ECC checking for cache accesses: 0: Disabled. 1: Enabled. 0 1 read-write RAM_ECC_INJ_EN Enable error injection for cache. When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. 1 2 read-write SET_ADDR Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. 24 27 read-write WAY Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. 16 18 read-write CM0_CA_CTL1 CM0+ cache control 0x404 32 read-write n 0x0 0x0 PWR_MODE Specifies power mode for CM0 cache. The following sequnece should be followed for turning OFF/ON the cache SRAM. Turn OFF sequence: a) Write CM0_CA_CTL0 to disable cache. b) Write CM0_CA_CTL1 to turn OFF cache SRAM. Turn ON sequence: a) Write CM0_CA_CTL1 to turn ON cache SRAM. b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. c) Write CM0_CA_CTL0 to enable cache. 0 2 read-write OFF Power OFF the CM0 cache SRAM. 0 RSVD Undefined 1 RETAINED Put CM0 cache SRAM in retained mode. 2 ENABLED Enable/Turn ON the CM0 cache SRAM. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only CM0_CA_CTL2 CM0+ cache control 0x408 32 read-write n 0x0 0x0 PWRUP_DELAY Number clock cycles delay needed after power domain power up 0 10 read-write CM0_CA_STATUS0 CM0+ cache status 0 0x440 32 read-only n 0x0 0x0 VALID32 Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. 0 32 read-only CM0_CA_STATUS1 CM0+ cache status 1 0x444 32 read-only n 0x0 0x0 TAG Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. 0 32 read-only CM0_CA_STATUS2 CM0+ cache status 2 0x448 32 read-only n 0x0 0x0 LRU Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3. 0 6 read-only CM0_STATUS CM0+ interface status 0x460 32 read-write n 0x0 0x0 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. 0 1 read-write WORK_INTERNAL_ERR See CM0_STATUS.MAIN_INTERNAL_ERROR. 1 2 read-write CM4_CA_CTL0 CM4 cache control 0x480 32 read-write n 0x0 0x0 CA_EN See CM0_CA_CTL. 31 32 read-write PREF_EN See CM0_CA_CTL. 30 31 read-write RAM_ECC_EN See CM0_CA_CTL. 0 1 read-write RAM_ECC_INJ_EN See CM0_CA_CTL. 1 2 read-write SET_ADDR See CM0_CA_CTL. 24 27 read-write WAY See CM0_CA_CTL. 16 18 read-write CM4_CA_CTL1 CM4 cache control 0x484 32 read-write n 0x0 0x0 PWR_MODE Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details. 0 2 read-write OFF See CM0_CA_CTL1 0 RSVD Undefined 1 RETAINED See CM0_CA_CTL1 2 ENABLED See CM0_CA_CTL1 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. 16 32 read-only CM4_CA_CTL2 CM4 cache control 0x488 32 read-write n 0x0 0x0 PWRUP_DELAY Number clock cycles delay needed after power domain power up 0 10 read-write CM4_CA_STATUS0 CM4 cache status 0 0x4C0 32 read-only n 0x0 0x0 VALID32 See CM0_CA_STATUS0. 0 32 read-only CM4_CA_STATUS1 CM4 cache status 1 0x4C4 32 read-only n 0x0 0x0 TAG See CM0_CA_STATUS1. 0 32 read-only CM4_CA_STATUS2 CM4 cache status 2 0x4C8 32 read-only n 0x0 0x0 LRU See CM0_CA_STATUS2. 0 6 read-only CM4_STATUS CM4 interface status 0x4E0 32 read-write n 0x0 0x0 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. 0 1 read-write WORK_INTERNAL_ERR See CM4_STATUS.MAIN_INTERNAL_ERROR. 1 2 read-write CRYPTO_BUFF_CTL Cryptography buffer control 0x500 32 read-write n 0x0 0x0 PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. For eCT work Flash, prefetch will not be done. 30 31 read-write DMAC_BUFF_CTL DMA controller buffer control 0x680 32 read-write n 0x0 0x0 PREF_EN See CRYPTO_BUFF_CTL. 30 31 read-write DW0_BUFF_CTL Datawire 0 buffer control 0x580 32 read-write n 0x0 0x0 PREF_EN See CRYPTO_BUFF_CTL. 30 31 read-write DW1_BUFF_CTL Datawire 1 buffer control 0x600 32 read-write n 0x0 0x0 PREF_EN See CRYPTO_BUFF_CTL. 30 31 read-write ECC_CTL ECC control 0x2A0 32 read-write n 0x0 0x0 PARITY ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. 24 32 read-write WORD_ADDR Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). 0 24 read-write EXT_MS0_BUFF_CTL External master 0 buffer control 0x700 32 read-write n 0x0 0x0 PREF_EN See CRYPTO_BUFF_CTL. 30 31 read-write EXT_MS1_BUFF_CTL External master 1 buffer control 0x780 32 read-write n 0x0 0x0 PREF_EN See CRYPTO_BUFF_CTL. 30 31 read-write FLASH_CMD Command 0x8 32 read-write n 0x0 0x0 BUFF_INV Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. 1 2 read-write INV Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. 0 1 read-write FLASH_CTL Control 0x0 32 read-write n 0x0 0x0 MAIN_BANK_MODE Specifies bank mode of FLASH macro main array. 0: Single bank mode. 1: Dual bank mode. 12 13 read-write MAIN_ECC_EN Enable ECC checking for FLASH main interface: 0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. 16 17 read-write MAIN_ECC_INJ_EN Enable error injection for FLASH main interface. When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. 17 18 read-write MAIN_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro main interface internal error. - FLASH macro main interface non-recoverable ECC error. - FLASH macro main interface recoverable ECC error. - FLASH macro main interface memory hole error. 18 19 read-write MAIN_MAP Specifies mapping of FLASH macro main array. 0: Mapping A. 1: Mapping B. This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). 8 9 read-write MAIN_WS FLASH macro main interface wait states: '0': 0 wait states. ... '15': 15 wait states 0 4 read-write WORK_BANK_MODE Specifies bank mode of FLASH macro work array. 0: Single bank mode. 1: Dual bank mode. 13 14 read-write WORK_ECC_EN Enable ECC checking for FLASH work interface: 0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. 20 21 read-write WORK_ECC_INJ_EN Enable error injection for FLASH work interface. When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. 21 22 read-write WORK_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro work interface internal error. - FLASH macro work interface non-recoverable ECC error. - FLASH macro work interface recoverable ECC error. - FLASH macro work interface memory hole error. 22 23 read-write WORK_MAP Specifies mapping of FLASH macro work array. 0: Mapping A. 1: Mapping B. This field is only used when WORK_BANK_MODE is '1' (dual bank mode). 9 10 read-write FLASH_PWR_CTL Flash power control 0x4 32 read-write n 0x0 0x0 ENABLE Controls 'enable' pin of the Flash memory. 0 1 read-write ENABLE_HV Controls 'enable_hv' pin of the Flash memory. 1 2 read-write FM_ADDR Flash macro address 0x8 32 read-write n 0x0 0x0 AXA Auxiliary address field: 0: regular flash memory. 1: supervisory flash memory. 24 25 read-write BA Bank address. 16 24 read-write RA Row address. 0 16 read-write FM_CTL Flash macro control 0x0 32 read-write n 0x0 0x0 DAA_MUX_SEL Direct memory cell access address. 16 23 read-write FM_MODE Requires (IF_SEL|WR_EN)=1 Flash macro mode selection 0 4 read-write FM_SEQ Requires (IF_SEL|WR_EN)=1 Flash macro sequence selection 8 10 read-write IF_SEL Interface selection. Specifies the interface that is used for flash memory read operations: 0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. 1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. Note: IF_SEL and WR_EN cannot be changed at the same time 24 25 read-write WR_EN 0: normal mode 1: Fm Write Enable Note: IF_SEL and WR_EN cannot be changed at the same time 25 26 read-write FM_MEM_DATA0 Flash macro memory sense amplifier and column decoder data 0xC00 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA1 Flash macro memory sense amplifier and column decoder data 0xC04 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA10 Flash macro memory sense amplifier and column decoder data 0xC28 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA100 Flash macro memory sense amplifier and column decoder data 0xD90 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA101 Flash macro memory sense amplifier and column decoder data 0xD94 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA102 Flash macro memory sense amplifier and column decoder data 0xD98 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA103 Flash macro memory sense amplifier and column decoder data 0xD9C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA104 Flash macro memory sense amplifier and column decoder data 0xDA0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA105 Flash macro memory sense amplifier and column decoder data 0xDA4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA106 Flash macro memory sense amplifier and column decoder data 0xDA8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA107 Flash macro memory sense amplifier and column decoder data 0xDAC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA108 Flash macro memory sense amplifier and column decoder data 0xDB0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA109 Flash macro memory sense amplifier and column decoder data 0xDB4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA11 Flash macro memory sense amplifier and column decoder data 0xC2C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA110 Flash macro memory sense amplifier and column decoder data 0xDB8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA111 Flash macro memory sense amplifier and column decoder data 0xDBC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA112 Flash macro memory sense amplifier and column decoder data 0xDC0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA113 Flash macro memory sense amplifier and column decoder data 0xDC4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA114 Flash macro memory sense amplifier and column decoder data 0xDC8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA115 Flash macro memory sense amplifier and column decoder data 0xDCC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA116 Flash macro memory sense amplifier and column decoder data 0xDD0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA117 Flash macro memory sense amplifier and column decoder data 0xDD4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA118 Flash macro memory sense amplifier and column decoder data 0xDD8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA119 Flash macro memory sense amplifier and column decoder data 0xDDC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA12 Flash macro memory sense amplifier and column decoder data 0xC30 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA120 Flash macro memory sense amplifier and column decoder data 0xDE0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA121 Flash macro memory sense amplifier and column decoder data 0xDE4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA122 Flash macro memory sense amplifier and column decoder data 0xDE8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA123 Flash macro memory sense amplifier and column decoder data 0xDEC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA124 Flash macro memory sense amplifier and column decoder data 0xDF0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA125 Flash macro memory sense amplifier and column decoder data 0xDF4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA126 Flash macro memory sense amplifier and column decoder data 0xDF8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA127 Flash macro memory sense amplifier and column decoder data 0xDFC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA128 Flash macro memory sense amplifier and column decoder data 0xE00 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA129 Flash macro memory sense amplifier and column decoder data 0xE04 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA13 Flash macro memory sense amplifier and column decoder data 0xC34 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA130 Flash macro memory sense amplifier and column decoder data 0xE08 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA131 Flash macro memory sense amplifier and column decoder data 0xE0C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA132 Flash macro memory sense amplifier and column decoder data 0xE10 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA133 Flash macro memory sense amplifier and column decoder data 0xE14 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA134 Flash macro memory sense amplifier and column decoder data 0xE18 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA135 Flash macro memory sense amplifier and column decoder data 0xE1C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA136 Flash macro memory sense amplifier and column decoder data 0xE20 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA137 Flash macro memory sense amplifier and column decoder data 0xE24 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA138 Flash macro memory sense amplifier and column decoder data 0xE28 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA139 Flash macro memory sense amplifier and column decoder data 0xE2C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA14 Flash macro memory sense amplifier and column decoder data 0xC38 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA140 Flash macro memory sense amplifier and column decoder data 0xE30 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA141 Flash macro memory sense amplifier and column decoder data 0xE34 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA142 Flash macro memory sense amplifier and column decoder data 0xE38 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA143 Flash macro memory sense amplifier and column decoder data 0xE3C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA144 Flash macro memory sense amplifier and column decoder data 0xE40 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA145 Flash macro memory sense amplifier and column decoder data 0xE44 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA146 Flash macro memory sense amplifier and column decoder data 0xE48 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA147 Flash macro memory sense amplifier and column decoder data 0xE4C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA148 Flash macro memory sense amplifier and column decoder data 0xE50 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA149 Flash macro memory sense amplifier and column decoder data 0xE54 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA15 Flash macro memory sense amplifier and column decoder data 0xC3C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA150 Flash macro memory sense amplifier and column decoder data 0xE58 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA151 Flash macro memory sense amplifier and column decoder data 0xE5C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA152 Flash macro memory sense amplifier and column decoder data 0xE60 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA153 Flash macro memory sense amplifier and column decoder data 0xE64 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA154 Flash macro memory sense amplifier and column decoder data 0xE68 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA155 Flash macro memory sense amplifier and column decoder data 0xE6C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA156 Flash macro memory sense amplifier and column decoder data 0xE70 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA157 Flash macro memory sense amplifier and column decoder data 0xE74 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA158 Flash macro memory sense amplifier and column decoder data 0xE78 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA159 Flash macro memory sense amplifier and column decoder data 0xE7C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA16 Flash macro memory sense amplifier and column decoder data 0xC40 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA160 Flash macro memory sense amplifier and column decoder data 0xE80 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA161 Flash macro memory sense amplifier and column decoder data 0xE84 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA162 Flash macro memory sense amplifier and column decoder data 0xE88 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA163 Flash macro memory sense amplifier and column decoder data 0xE8C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA164 Flash macro memory sense amplifier and column decoder data 0xE90 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA165 Flash macro memory sense amplifier and column decoder data 0xE94 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA166 Flash macro memory sense amplifier and column decoder data 0xE98 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA167 Flash macro memory sense amplifier and column decoder data 0xE9C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA168 Flash macro memory sense amplifier and column decoder data 0xEA0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA169 Flash macro memory sense amplifier and column decoder data 0xEA4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA17 Flash macro memory sense amplifier and column decoder data 0xC44 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA170 Flash macro memory sense amplifier and column decoder data 0xEA8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA171 Flash macro memory sense amplifier and column decoder data 0xEAC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA172 Flash macro memory sense amplifier and column decoder data 0xEB0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA173 Flash macro memory sense amplifier and column decoder data 0xEB4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA174 Flash macro memory sense amplifier and column decoder data 0xEB8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA175 Flash macro memory sense amplifier and column decoder data 0xEBC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA176 Flash macro memory sense amplifier and column decoder data 0xEC0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA177 Flash macro memory sense amplifier and column decoder data 0xEC4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA178 Flash macro memory sense amplifier and column decoder data 0xEC8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA179 Flash macro memory sense amplifier and column decoder data 0xECC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA18 Flash macro memory sense amplifier and column decoder data 0xC48 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA180 Flash macro memory sense amplifier and column decoder data 0xED0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA181 Flash macro memory sense amplifier and column decoder data 0xED4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA182 Flash macro memory sense amplifier and column decoder data 0xED8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA183 Flash macro memory sense amplifier and column decoder data 0xEDC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA184 Flash macro memory sense amplifier and column decoder data 0xEE0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA185 Flash macro memory sense amplifier and column decoder data 0xEE4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA186 Flash macro memory sense amplifier and column decoder data 0xEE8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA187 Flash macro memory sense amplifier and column decoder data 0xEEC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA188 Flash macro memory sense amplifier and column decoder data 0xEF0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA189 Flash macro memory sense amplifier and column decoder data 0xEF4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA19 Flash macro memory sense amplifier and column decoder data 0xC4C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA190 Flash macro memory sense amplifier and column decoder data 0xEF8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA191 Flash macro memory sense amplifier and column decoder data 0xEFC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA192 Flash macro memory sense amplifier and column decoder data 0xF00 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA193 Flash macro memory sense amplifier and column decoder data 0xF04 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA194 Flash macro memory sense amplifier and column decoder data 0xF08 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA195 Flash macro memory sense amplifier and column decoder data 0xF0C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA196 Flash macro memory sense amplifier and column decoder data 0xF10 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA197 Flash macro memory sense amplifier and column decoder data 0xF14 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA198 Flash macro memory sense amplifier and column decoder data 0xF18 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA199 Flash macro memory sense amplifier and column decoder data 0xF1C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA2 Flash macro memory sense amplifier and column decoder data 0xC08 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA20 Flash macro memory sense amplifier and column decoder data 0xC50 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA200 Flash macro memory sense amplifier and column decoder data 0xF20 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA201 Flash macro memory sense amplifier and column decoder data 0xF24 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA202 Flash macro memory sense amplifier and column decoder data 0xF28 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA203 Flash macro memory sense amplifier and column decoder data 0xF2C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA204 Flash macro memory sense amplifier and column decoder data 0xF30 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA205 Flash macro memory sense amplifier and column decoder data 0xF34 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA206 Flash macro memory sense amplifier and column decoder data 0xF38 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA207 Flash macro memory sense amplifier and column decoder data 0xF3C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA208 Flash macro memory sense amplifier and column decoder data 0xF40 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA209 Flash macro memory sense amplifier and column decoder data 0xF44 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA21 Flash macro memory sense amplifier and column decoder data 0xC54 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA210 Flash macro memory sense amplifier and column decoder data 0xF48 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA211 Flash macro memory sense amplifier and column decoder data 0xF4C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA212 Flash macro memory sense amplifier and column decoder data 0xF50 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA213 Flash macro memory sense amplifier and column decoder data 0xF54 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA214 Flash macro memory sense amplifier and column decoder data 0xF58 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA215 Flash macro memory sense amplifier and column decoder data 0xF5C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA216 Flash macro memory sense amplifier and column decoder data 0xF60 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA217 Flash macro memory sense amplifier and column decoder data 0xF64 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA218 Flash macro memory sense amplifier and column decoder data 0xF68 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA219 Flash macro memory sense amplifier and column decoder data 0xF6C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA22 Flash macro memory sense amplifier and column decoder data 0xC58 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA220 Flash macro memory sense amplifier and column decoder data 0xF70 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA221 Flash macro memory sense amplifier and column decoder data 0xF74 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA222 Flash macro memory sense amplifier and column decoder data 0xF78 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA223 Flash macro memory sense amplifier and column decoder data 0xF7C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA224 Flash macro memory sense amplifier and column decoder data 0xF80 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA225 Flash macro memory sense amplifier and column decoder data 0xF84 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA226 Flash macro memory sense amplifier and column decoder data 0xF88 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA227 Flash macro memory sense amplifier and column decoder data 0xF8C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA228 Flash macro memory sense amplifier and column decoder data 0xF90 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA229 Flash macro memory sense amplifier and column decoder data 0xF94 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA23 Flash macro memory sense amplifier and column decoder data 0xC5C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA230 Flash macro memory sense amplifier and column decoder data 0xF98 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA231 Flash macro memory sense amplifier and column decoder data 0xF9C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA232 Flash macro memory sense amplifier and column decoder data 0xFA0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA233 Flash macro memory sense amplifier and column decoder data 0xFA4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA234 Flash macro memory sense amplifier and column decoder data 0xFA8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA235 Flash macro memory sense amplifier and column decoder data 0xFAC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA236 Flash macro memory sense amplifier and column decoder data 0xFB0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA237 Flash macro memory sense amplifier and column decoder data 0xFB4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA238 Flash macro memory sense amplifier and column decoder data 0xFB8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA239 Flash macro memory sense amplifier and column decoder data 0xFBC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA24 Flash macro memory sense amplifier and column decoder data 0xC60 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA240 Flash macro memory sense amplifier and column decoder data 0xFC0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA241 Flash macro memory sense amplifier and column decoder data 0xFC4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA242 Flash macro memory sense amplifier and column decoder data 0xFC8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA243 Flash macro memory sense amplifier and column decoder data 0xFCC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA244 Flash macro memory sense amplifier and column decoder data 0xFD0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA245 Flash macro memory sense amplifier and column decoder data 0xFD4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA246 Flash macro memory sense amplifier and column decoder data 0xFD8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA247 Flash macro memory sense amplifier and column decoder data 0xFDC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA248 Flash macro memory sense amplifier and column decoder data 0xFE0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA249 Flash macro memory sense amplifier and column decoder data 0xFE4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA25 Flash macro memory sense amplifier and column decoder data 0xC64 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA250 Flash macro memory sense amplifier and column decoder data 0xFE8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA251 Flash macro memory sense amplifier and column decoder data 0xFEC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA252 Flash macro memory sense amplifier and column decoder data 0xFF0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA253 Flash macro memory sense amplifier and column decoder data 0xFF4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA254 Flash macro memory sense amplifier and column decoder data 0xFF8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA255 Flash macro memory sense amplifier and column decoder data 0xFFC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA26 Flash macro memory sense amplifier and column decoder data 0xC68 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA27 Flash macro memory sense amplifier and column decoder data 0xC6C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA28 Flash macro memory sense amplifier and column decoder data 0xC70 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA29 Flash macro memory sense amplifier and column decoder data 0xC74 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA3 Flash macro memory sense amplifier and column decoder data 0xC0C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA30 Flash macro memory sense amplifier and column decoder data 0xC78 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA31 Flash macro memory sense amplifier and column decoder data 0xC7C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA32 Flash macro memory sense amplifier and column decoder data 0xC80 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA33 Flash macro memory sense amplifier and column decoder data 0xC84 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA34 Flash macro memory sense amplifier and column decoder data 0xC88 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA35 Flash macro memory sense amplifier and column decoder data 0xC8C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA36 Flash macro memory sense amplifier and column decoder data 0xC90 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA37 Flash macro memory sense amplifier and column decoder data 0xC94 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA38 Flash macro memory sense amplifier and column decoder data 0xC98 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA39 Flash macro memory sense amplifier and column decoder data 0xC9C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA4 Flash macro memory sense amplifier and column decoder data 0xC10 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA40 Flash macro memory sense amplifier and column decoder data 0xCA0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA41 Flash macro memory sense amplifier and column decoder data 0xCA4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA42 Flash macro memory sense amplifier and column decoder data 0xCA8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA43 Flash macro memory sense amplifier and column decoder data 0xCAC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA44 Flash macro memory sense amplifier and column decoder data 0xCB0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA45 Flash macro memory sense amplifier and column decoder data 0xCB4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA46 Flash macro memory sense amplifier and column decoder data 0xCB8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA47 Flash macro memory sense amplifier and column decoder data 0xCBC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA48 Flash macro memory sense amplifier and column decoder data 0xCC0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA49 Flash macro memory sense amplifier and column decoder data 0xCC4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA5 Flash macro memory sense amplifier and column decoder data 0xC14 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA50 Flash macro memory sense amplifier and column decoder data 0xCC8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA51 Flash macro memory sense amplifier and column decoder data 0xCCC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA52 Flash macro memory sense amplifier and column decoder data 0xCD0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA53 Flash macro memory sense amplifier and column decoder data 0xCD4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA54 Flash macro memory sense amplifier and column decoder data 0xCD8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA55 Flash macro memory sense amplifier and column decoder data 0xCDC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA56 Flash macro memory sense amplifier and column decoder data 0xCE0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA57 Flash macro memory sense amplifier and column decoder data 0xCE4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA58 Flash macro memory sense amplifier and column decoder data 0xCE8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA59 Flash macro memory sense amplifier and column decoder data 0xCEC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA6 Flash macro memory sense amplifier and column decoder data 0xC18 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA60 Flash macro memory sense amplifier and column decoder data 0xCF0 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA61 Flash macro memory sense amplifier and column decoder data 0xCF4 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA62 Flash macro memory sense amplifier and column decoder data 0xCF8 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA63 Flash macro memory sense amplifier and column decoder data 0xCFC 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA64 Flash macro memory sense amplifier and column decoder data 0xD00 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA65 Flash macro memory sense amplifier and column decoder data 0xD04 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA66 Flash macro memory sense amplifier and column decoder data 0xD08 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA67 Flash macro memory sense amplifier and column decoder data 0xD0C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA68 Flash macro memory sense amplifier and column decoder data 0xD10 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA69 Flash macro memory sense amplifier and column decoder data 0xD14 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA7 Flash macro memory sense amplifier and column decoder data 0xC1C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA70 Flash macro memory sense amplifier and column decoder data 0xD18 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA71 Flash macro memory sense amplifier and column decoder data 0xD1C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA72 Flash macro memory sense amplifier and column decoder data 0xD20 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA73 Flash macro memory sense amplifier and column decoder data 0xD24 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA74 Flash macro memory sense amplifier and column decoder data 0xD28 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA75 Flash macro memory sense amplifier and column decoder data 0xD2C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA76 Flash macro memory sense amplifier and column decoder data 0xD30 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA77 Flash macro memory sense amplifier and column decoder data 0xD34 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA78 Flash macro memory sense amplifier and column decoder data 0xD38 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA79 Flash macro memory sense amplifier and column decoder data 0xD3C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA8 Flash macro memory sense amplifier and column decoder data 0xC20 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA80 Flash macro memory sense amplifier and column decoder data 0xD40 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA81 Flash macro memory sense amplifier and column decoder data 0xD44 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA82 Flash macro memory sense amplifier and column decoder data 0xD48 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA83 Flash macro memory sense amplifier and column decoder data 0xD4C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA84 Flash macro memory sense amplifier and column decoder data 0xD50 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA85 Flash macro memory sense amplifier and column decoder data 0xD54 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA86 Flash macro memory sense amplifier and column decoder data 0xD58 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA87 Flash macro memory sense amplifier and column decoder data 0xD5C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA88 Flash macro memory sense amplifier and column decoder data 0xD60 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA89 Flash macro memory sense amplifier and column decoder data 0xD64 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA9 Flash macro memory sense amplifier and column decoder data 0xC24 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA90 Flash macro memory sense amplifier and column decoder data 0xD68 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA91 Flash macro memory sense amplifier and column decoder data 0xD6C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA92 Flash macro memory sense amplifier and column decoder data 0xD70 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA93 Flash macro memory sense amplifier and column decoder data 0xD74 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA94 Flash macro memory sense amplifier and column decoder data 0xD78 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA95 Flash macro memory sense amplifier and column decoder data 0xD7C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA96 Flash macro memory sense amplifier and column decoder data 0xD80 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA97 Flash macro memory sense amplifier and column decoder data 0xD84 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA98 Flash macro memory sense amplifier and column decoder data 0xD88 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_MEM_DATA99 Flash macro memory sense amplifier and column decoder data 0xD8C 32 read-only n 0x0 0x0 DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. 0 32 read-only FM_PL_DATA0 Flash macro Page Latches data 0x800 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA1 Flash macro Page Latches data 0x804 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA10 Flash macro Page Latches data 0x828 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA100 Flash macro Page Latches data 0x990 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA101 Flash macro Page Latches data 0x994 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA102 Flash macro Page Latches data 0x998 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA103 Flash macro Page Latches data 0x99C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA104 Flash macro Page Latches data 0x9A0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA105 Flash macro Page Latches data 0x9A4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA106 Flash macro Page Latches data 0x9A8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA107 Flash macro Page Latches data 0x9AC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA108 Flash macro Page Latches data 0x9B0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA109 Flash macro Page Latches data 0x9B4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA11 Flash macro Page Latches data 0x82C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA110 Flash macro Page Latches data 0x9B8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA111 Flash macro Page Latches data 0x9BC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA112 Flash macro Page Latches data 0x9C0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA113 Flash macro Page Latches data 0x9C4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA114 Flash macro Page Latches data 0x9C8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA115 Flash macro Page Latches data 0x9CC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA116 Flash macro Page Latches data 0x9D0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA117 Flash macro Page Latches data 0x9D4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA118 Flash macro Page Latches data 0x9D8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA119 Flash macro Page Latches data 0x9DC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA12 Flash macro Page Latches data 0x830 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA120 Flash macro Page Latches data 0x9E0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA121 Flash macro Page Latches data 0x9E4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA122 Flash macro Page Latches data 0x9E8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA123 Flash macro Page Latches data 0x9EC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA124 Flash macro Page Latches data 0x9F0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA125 Flash macro Page Latches data 0x9F4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA126 Flash macro Page Latches data 0x9F8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA127 Flash macro Page Latches data 0x9FC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA128 Flash macro Page Latches data 0xA00 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA129 Flash macro Page Latches data 0xA04 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA13 Flash macro Page Latches data 0x834 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA130 Flash macro Page Latches data 0xA08 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA131 Flash macro Page Latches data 0xA0C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA132 Flash macro Page Latches data 0xA10 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA133 Flash macro Page Latches data 0xA14 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA134 Flash macro Page Latches data 0xA18 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA135 Flash macro Page Latches data 0xA1C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA136 Flash macro Page Latches data 0xA20 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA137 Flash macro Page Latches data 0xA24 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA138 Flash macro Page Latches data 0xA28 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA139 Flash macro Page Latches data 0xA2C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA14 Flash macro Page Latches data 0x838 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA140 Flash macro Page Latches data 0xA30 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA141 Flash macro Page Latches data 0xA34 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA142 Flash macro Page Latches data 0xA38 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA143 Flash macro Page Latches data 0xA3C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA144 Flash macro Page Latches data 0xA40 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA145 Flash macro Page Latches data 0xA44 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA146 Flash macro Page Latches data 0xA48 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA147 Flash macro Page Latches data 0xA4C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA148 Flash macro Page Latches data 0xA50 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA149 Flash macro Page Latches data 0xA54 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA15 Flash macro Page Latches data 0x83C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA150 Flash macro Page Latches data 0xA58 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA151 Flash macro Page Latches data 0xA5C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA152 Flash macro Page Latches data 0xA60 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA153 Flash macro Page Latches data 0xA64 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA154 Flash macro Page Latches data 0xA68 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA155 Flash macro Page Latches data 0xA6C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA156 Flash macro Page Latches data 0xA70 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA157 Flash macro Page Latches data 0xA74 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA158 Flash macro Page Latches data 0xA78 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA159 Flash macro Page Latches data 0xA7C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA16 Flash macro Page Latches data 0x840 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA160 Flash macro Page Latches data 0xA80 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA161 Flash macro Page Latches data 0xA84 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA162 Flash macro Page Latches data 0xA88 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA163 Flash macro Page Latches data 0xA8C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA164 Flash macro Page Latches data 0xA90 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA165 Flash macro Page Latches data 0xA94 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA166 Flash macro Page Latches data 0xA98 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA167 Flash macro Page Latches data 0xA9C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA168 Flash macro Page Latches data 0xAA0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA169 Flash macro Page Latches data 0xAA4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA17 Flash macro Page Latches data 0x844 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA170 Flash macro Page Latches data 0xAA8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA171 Flash macro Page Latches data 0xAAC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA172 Flash macro Page Latches data 0xAB0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA173 Flash macro Page Latches data 0xAB4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA174 Flash macro Page Latches data 0xAB8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA175 Flash macro Page Latches data 0xABC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA176 Flash macro Page Latches data 0xAC0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA177 Flash macro Page Latches data 0xAC4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA178 Flash macro Page Latches data 0xAC8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA179 Flash macro Page Latches data 0xACC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA18 Flash macro Page Latches data 0x848 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA180 Flash macro Page Latches data 0xAD0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA181 Flash macro Page Latches data 0xAD4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA182 Flash macro Page Latches data 0xAD8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA183 Flash macro Page Latches data 0xADC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA184 Flash macro Page Latches data 0xAE0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA185 Flash macro Page Latches data 0xAE4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA186 Flash macro Page Latches data 0xAE8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA187 Flash macro Page Latches data 0xAEC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA188 Flash macro Page Latches data 0xAF0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA189 Flash macro Page Latches data 0xAF4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA19 Flash macro Page Latches data 0x84C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA190 Flash macro Page Latches data 0xAF8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA191 Flash macro Page Latches data 0xAFC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA192 Flash macro Page Latches data 0xB00 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA193 Flash macro Page Latches data 0xB04 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA194 Flash macro Page Latches data 0xB08 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA195 Flash macro Page Latches data 0xB0C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA196 Flash macro Page Latches data 0xB10 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA197 Flash macro Page Latches data 0xB14 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA198 Flash macro Page Latches data 0xB18 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA199 Flash macro Page Latches data 0xB1C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA2 Flash macro Page Latches data 0x808 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA20 Flash macro Page Latches data 0x850 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA200 Flash macro Page Latches data 0xB20 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA201 Flash macro Page Latches data 0xB24 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA202 Flash macro Page Latches data 0xB28 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA203 Flash macro Page Latches data 0xB2C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA204 Flash macro Page Latches data 0xB30 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA205 Flash macro Page Latches data 0xB34 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA206 Flash macro Page Latches data 0xB38 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA207 Flash macro Page Latches data 0xB3C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA208 Flash macro Page Latches data 0xB40 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA209 Flash macro Page Latches data 0xB44 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA21 Flash macro Page Latches data 0x854 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA210 Flash macro Page Latches data 0xB48 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA211 Flash macro Page Latches data 0xB4C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA212 Flash macro Page Latches data 0xB50 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA213 Flash macro Page Latches data 0xB54 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA214 Flash macro Page Latches data 0xB58 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA215 Flash macro Page Latches data 0xB5C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA216 Flash macro Page Latches data 0xB60 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA217 Flash macro Page Latches data 0xB64 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA218 Flash macro Page Latches data 0xB68 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA219 Flash macro Page Latches data 0xB6C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA22 Flash macro Page Latches data 0x858 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA220 Flash macro Page Latches data 0xB70 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA221 Flash macro Page Latches data 0xB74 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA222 Flash macro Page Latches data 0xB78 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA223 Flash macro Page Latches data 0xB7C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA224 Flash macro Page Latches data 0xB80 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA225 Flash macro Page Latches data 0xB84 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA226 Flash macro Page Latches data 0xB88 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA227 Flash macro Page Latches data 0xB8C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA228 Flash macro Page Latches data 0xB90 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA229 Flash macro Page Latches data 0xB94 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA23 Flash macro Page Latches data 0x85C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA230 Flash macro Page Latches data 0xB98 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA231 Flash macro Page Latches data 0xB9C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA232 Flash macro Page Latches data 0xBA0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA233 Flash macro Page Latches data 0xBA4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA234 Flash macro Page Latches data 0xBA8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA235 Flash macro Page Latches data 0xBAC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA236 Flash macro Page Latches data 0xBB0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA237 Flash macro Page Latches data 0xBB4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA238 Flash macro Page Latches data 0xBB8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA239 Flash macro Page Latches data 0xBBC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA24 Flash macro Page Latches data 0x860 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA240 Flash macro Page Latches data 0xBC0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA241 Flash macro Page Latches data 0xBC4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA242 Flash macro Page Latches data 0xBC8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA243 Flash macro Page Latches data 0xBCC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA244 Flash macro Page Latches data 0xBD0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA245 Flash macro Page Latches data 0xBD4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA246 Flash macro Page Latches data 0xBD8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA247 Flash macro Page Latches data 0xBDC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA248 Flash macro Page Latches data 0xBE0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA249 Flash macro Page Latches data 0xBE4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA25 Flash macro Page Latches data 0x864 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA250 Flash macro Page Latches data 0xBE8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA251 Flash macro Page Latches data 0xBEC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA252 Flash macro Page Latches data 0xBF0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA253 Flash macro Page Latches data 0xBF4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA254 Flash macro Page Latches data 0xBF8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA255 Flash macro Page Latches data 0xBFC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA26 Flash macro Page Latches data 0x868 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA27 Flash macro Page Latches data 0x86C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA28 Flash macro Page Latches data 0x870 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA29 Flash macro Page Latches data 0x874 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA3 Flash macro Page Latches data 0x80C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA30 Flash macro Page Latches data 0x878 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA31 Flash macro Page Latches data 0x87C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA32 Flash macro Page Latches data 0x880 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA33 Flash macro Page Latches data 0x884 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA34 Flash macro Page Latches data 0x888 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA35 Flash macro Page Latches data 0x88C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA36 Flash macro Page Latches data 0x890 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA37 Flash macro Page Latches data 0x894 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA38 Flash macro Page Latches data 0x898 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA39 Flash macro Page Latches data 0x89C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA4 Flash macro Page Latches data 0x810 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA40 Flash macro Page Latches data 0x8A0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA41 Flash macro Page Latches data 0x8A4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA42 Flash macro Page Latches data 0x8A8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA43 Flash macro Page Latches data 0x8AC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA44 Flash macro Page Latches data 0x8B0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA45 Flash macro Page Latches data 0x8B4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA46 Flash macro Page Latches data 0x8B8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA47 Flash macro Page Latches data 0x8BC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA48 Flash macro Page Latches data 0x8C0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA49 Flash macro Page Latches data 0x8C4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA5 Flash macro Page Latches data 0x814 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA50 Flash macro Page Latches data 0x8C8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA51 Flash macro Page Latches data 0x8CC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA52 Flash macro Page Latches data 0x8D0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA53 Flash macro Page Latches data 0x8D4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA54 Flash macro Page Latches data 0x8D8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA55 Flash macro Page Latches data 0x8DC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA56 Flash macro Page Latches data 0x8E0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA57 Flash macro Page Latches data 0x8E4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA58 Flash macro Page Latches data 0x8E8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA59 Flash macro Page Latches data 0x8EC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA6 Flash macro Page Latches data 0x818 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA60 Flash macro Page Latches data 0x8F0 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA61 Flash macro Page Latches data 0x8F4 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA62 Flash macro Page Latches data 0x8F8 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA63 Flash macro Page Latches data 0x8FC 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA64 Flash macro Page Latches data 0x900 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA65 Flash macro Page Latches data 0x904 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA66 Flash macro Page Latches data 0x908 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA67 Flash macro Page Latches data 0x90C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA68 Flash macro Page Latches data 0x910 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA69 Flash macro Page Latches data 0x914 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA7 Flash macro Page Latches data 0x81C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA70 Flash macro Page Latches data 0x918 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA71 Flash macro Page Latches data 0x91C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA72 Flash macro Page Latches data 0x920 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA73 Flash macro Page Latches data 0x924 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA74 Flash macro Page Latches data 0x928 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA75 Flash macro Page Latches data 0x92C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA76 Flash macro Page Latches data 0x930 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA77 Flash macro Page Latches data 0x934 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA78 Flash macro Page Latches data 0x938 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA79 Flash macro Page Latches data 0x93C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA8 Flash macro Page Latches data 0x820 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA80 Flash macro Page Latches data 0x940 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA81 Flash macro Page Latches data 0x944 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA82 Flash macro Page Latches data 0x948 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA83 Flash macro Page Latches data 0x94C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA84 Flash macro Page Latches data 0x950 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA85 Flash macro Page Latches data 0x954 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA86 Flash macro Page Latches data 0x958 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA87 Flash macro Page Latches data 0x95C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA88 Flash macro Page Latches data 0x960 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA89 Flash macro Page Latches data 0x964 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA9 Flash macro Page Latches data 0x824 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA90 Flash macro Page Latches data 0x968 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA91 Flash macro Page Latches data 0x96C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA92 Flash macro Page Latches data 0x970 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA93 Flash macro Page Latches data 0x974 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA94 Flash macro Page Latches data 0x978 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA95 Flash macro Page Latches data 0x97C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA96 Flash macro Page Latches data 0x980 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA97 Flash macro Page Latches data 0x984 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA98 Flash macro Page Latches data 0x988 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_DATA99 Flash macro Page Latches data 0x98C 32 read-write n 0x0 0x0 DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. 0 32 read-write FM_PL_WRDATA_ALL Flash macro write page latches all 0x7FC 32 read-write n 0x0 0x0 DATA32 Write all high Voltage page latches with the same 32-bit data in a single write cycle Read always returns 0. 0 32 read-write FM_SRAM_ECC_CTL0 eCT Flash SRAM ECC control 0 0x2B0 32 read-write n 0x0 0x0 ECC_INJ_DATA 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. 0 32 read-write FM_SRAM_ECC_CTL1 eCT Flash SRAM ECC control 1 0x2B4 32 read-write n 0x0 0x0 ECC_INJ_PARITY 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. 0 7 read-write FM_SRAM_ECC_CTL2 eCT Flash SRAM ECC control 2 0x2B8 32 read-only n 0x0 0x0 CORRECTED_DATA 32-bit corrected data output of the ECC syndrome logic. 0 32 read-only FM_SRAM_ECC_CTL3 eCT Flash SRAM ECC control 3 0x2BC 32 read-write n 0x0 0x0 ECC_ENABLE ECC generation/check enable for eCT Flash SRAM memory. 0 1 read-write ECC_INJ_EN eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: 1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. 2. Set the ECC_INJ_EN bit to '1'. 3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. 4. Check the corrected data in FM_SRAM_ECC_CTL2. 5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if corrupted data was written in step 1). 6. If not finished, start over at 1 with different data. 4 5 read-write ECC_TEST_FAIL Status of ECC test. 1 : ECC test failed because eCT Flash macro is busy and using the SRAM. 0: ECC was performed. 8 9 read-only GEOMETRY Regular flash geometry 0x10 32 read-only n 0x0 0x0 BANK_COUNT Number of banks (minus 1): 0: 1 bank 1: 2 banks ... '255': 256 banks 16 24 read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2): 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 15: 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. 28 32 read-only ROW_COUNT Number of rows (minus 1): 0: 1 row 1: 2 rows 2: 3 rows ... '65535': 65536 rows 0 16 read-only WORD_SIZE_LOG2 Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 3: 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. 24 28 read-only GEOMETRY_SUPERVISORY Supervisory flash geometry 0x14 32 read-only n 0x0 0x0 BANK_COUNT Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. 16 24 read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. 28 32 read-only ROW_COUNT Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT 0 16 read-only WORD_SIZE_LOG2 Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. 24 28 read-only INTR Interrupt 0x40 32 read-write n 0x0 0x0 TIMER_EXPIRED Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. 0 1 read-write INTR_MASK Interrupt mask 0x48 32 read-write n 0x0 0x0 TIMER_EXPIRED Mask for corresponding field in INTR register. 0 1 read-write INTR_MASKED Interrupt masked 0x4C 32 read-only n 0x0 0x0 TIMER_EXPIRED Logical and of corresponding request and mask fields. 0 1 read-only INTR_SET Interrupt set 0x44 32 read-write n 0x0 0x0 TIMER_EXPIRED Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). 0 1 read-write PW_SEQ12 HV Pulse Delay for seq 1 and 2 pre 0xA0 32 read-write n 0x0 0x0 PW_SEQ1 Seq1 delay 0 16 read-write PW_SEQ2_PRE Seq2 pre delay 16 32 read-write PW_SEQ23 HV Pulse Delay for seq2 post and seq3 0xA4 32 read-write n 0x0 0x0 PW_SEQ2_POST Seq2 post delay 0 16 read-write PW_SEQ3 Seq3 delay 16 32 read-write RED_CTL01 Redundancy Control normal sectors 0,1 0x80 32 read-write n 0x0 0x0 RED_ADDR_0 Bad Row Pair Address for Sector 0 0 8 read-write RED_ADDR_1 Bad Row Pair Address for Sector 1 16 24 read-write RED_EN_0 1: Redundancy Enable for Sector 0 8 9 read-write RED_EN_1 1: Redundancy Enable for Sector 1 24 25 read-write RED_CTL23 Redundancy Control normal sectors 2,3 0x84 32 read-write n 0x0 0x0 RED_ADDR_2 Bad Row Pair Address for Sector 2 0 8 read-write RED_ADDR_3 Bad Row Pair Address for Sector 3 16 24 read-write RED_EN_2 1: Redundancy Enable for Sector 2 8 9 read-write RED_EN_3 1: Redundancy Enable for Sector 3 24 25 read-write RED_CTL45 Redundancy Control normal sectors 4,5 0x88 32 read-write n 0x0 0x0 RED_ADDR_4 Bad Row Pair Address for Sector 4 0 8 read-write RED_ADDR_5 Bad Row Pair Address for Sector 5 16 24 read-write RED_EN_4 1: Redundancy Enable for Sector 4 8 9 read-write RED_EN_5 1: Redundancy Enable for Sector 5 24 25 read-write RED_CTL67 Redundancy Control normal sectors 6,7 0x8C 32 read-write n 0x0 0x0 RED_ADDR_6 Bad Row Pair Address for Sector 6 0 8 read-write RED_ADDR_7 Bad Row Pair Address for Sector 7 16 24 read-write RED_EN_6 1: Redundancy Enable for Sector 6 8 9 read-write RED_EN_7 1: Redundancy Enable for Sector 7 24 25 read-write RED_CTL_SM01 Redundancy Control special sectors 0,1 0x90 32 read-write n 0x0 0x0 RED_ADDR_SM0 Bad Row Pair Address for Special Sector 0 0 8 read-write RED_ADDR_SM1 Bad Row Pair Address for Special Sector 1 16 24 read-write RED_EN_SM0 Redundancy Enable for Special Sector 0 8 9 read-write RED_EN_SM1 Redundancy Enable for Special Sector 1 24 25 read-write RGRANT_DELAY_ERS R-grant delay for erase 0xAC 32 read-write n 0x0 0x0 RGRANT_DELAY_ERS_SEQ01 ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 0 8 read-write RGRANT_DELAY_ERS_SEQ12 ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 8 16 read-write RGRANT_DELAY_ERS_SEQ23 ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 16 24 read-write RGRANT_DELAY_PRG R-grant delay for program 0x98 32 read-write n 0x0 0x0 HV_PARAMS_LOADED 0: HV Pulse common params not loaded 1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3 31 32 read-write RGRANT_DELAY_CLK Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay The value of this field is the integer result of 'clk_t frequency / 8'. Example: for clk_t=100 this field is INT(100/8) =12. This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table 24 28 read-write RGRANT_DELAY_PRG_SEQ12 PROG and PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 0 8 read-write RGRANT_DELAY_PRG_SEQ23 PROG and PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 8 16 read-write RGRANT_DELAY_SEQ30 PROG and PRE_PROG and ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 16 24 read-write RGRANT_SCALE_ERS R-grant delay scale for erase 0xA8 32 read-write n 0x0 0x0 RGRANT_DELAY_ERS_PEOFF ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 24 32 read-write RGRANT_DELAY_ERS_PEON ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 16 24 read-write SCALE_ERS_PEOFF ERASE: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 8 10 read-write SCALE_ERS_PEON ERASE: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 6 8 read-write SCALE_ERS_SEQ01 ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 0 2 read-write SCALE_ERS_SEQ12 ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 2 4 read-write SCALE_ERS_SEQ23 ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS 4 6 read-write STATUS Status 0x4 32 read-only n 0x0 0x0 CBUS_RA_MATCH Test_only, internal node: mpcon ra match 21 22 read-only CBUS_RED_ROW_EN Test_only, internal node: mpcon red_row_en 22 23 read-only FM_BUSY 0': FM not busy 1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations. 8 9 read-only FM_READY 0: FM not ready 1: FM ready 9 10 read-only HVOP_BULK_ALL Test_only, internal node: mpcon bk_all 20 21 read-only HVOP_SECTOR Test_only, internal node: mpcon bk_sec 19 20 read-only HVOP_SUB_SECTOR_N Test_only, internal node: mpcon bk_subb 18 19 read-only HV_REGS_ISOLATED Indicates the isolation status at HV trim and redundancy registers inputs 0: Not isolated, writing permitted 1: isolated writing disabled 1 2 read-only IF_SEL_MON FM_CTL.IF_SEL bit after being synchronized in clk_r domain 5 6 read-only ILLEGAL_HVOP Indicates a bulk, sector erase, program has been requested when axa=1 0: no error 1: illegal HV operation error 2 3 read-only MAX_DOUT_WIDTH Internal memory core max data out size (number of data out bits per column): 0: x128 bits 1: x256 bits 13 14 read-only NEG_PUMP_VHI NEG pump VHI 11 12 read-only POS_PUMP_VLO POS pump VLO 10 11 read-only PUMP_NDAC Test_only, internal node: regif ndac outputs to pos pump 28 32 read-only PUMP_PDAC Test_only, internal node: regif pdac outputs to pos pump 24 28 read-only RESET_MM Test_only, internal node: mpcon reset_mm 15 16 read-only ROW_EVEN Test_only, internal node: mpcon row_even 17 18 read-only ROW_ODD Test_only, internal node: mpcon row_odd 16 17 read-only RQ_ERROR Test_only, internal node: rq_error sync-de in clk_c domain 23 24 read-only RWW FM Type (Read While Write or Not Read While Write): 0: Non RWW FM Type 1: RWW FM Type 12 13 read-only R_GRANT_DELAY_STATUS 0: R_GRANT_DELAY timer is not running 1: R_GRANT_DELAY timer is running 7 8 read-only SECTOR0_SR 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. 1: Sector 0 contains special rows 14 15 read-only TIMER_ENABLED This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires 0: timer not running 1: Timer is enabled and not expired yet 0 1 read-only TIMER_STATUS The actual timer state sync-ed in clk_c domain: 0: timer is not running: 1: timer is running 6 7 read-only TURBO_N After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an 'FM READY' flag. 0: turbo mode 1: normal mode 3 4 read-only WR_EN_MON FM_CTL.WR_EN bit after being synchronized in clk_r domain 4 5 read-only TIMER_CLK_CTL Timer prescaler (clk_t to timer clock frequency divider) 0x34 32 read-write n 0x0 0x0 RGRANT_DELAY_PRG_PEOFF PROG and PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 16 24 read-write RGRANT_DELAY_PRG_PEON PROG and PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 8 16 read-write RGRANT_DELAY_PRG_SEQ01 PROG and PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled 24 32 read-write TIMER_CLOCK_FREQ Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. Equal to the frequency in MHz of the timer clock 'clk_t'. Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' Max clk_t frequency = 100MHz. This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table 0 8 read-write TIMER_CTL Timer control 0x38 32 read-write n 0x0 0x0 ACLK_EN ACLK enable (generates a single cycle pulse for the FM): 0: disabled 1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. 30 31 read-write AUTO_SEQUENCE 1': Starts1 the HV automatic sequencing Cleared by HW 24 25 read-write PERIOD Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. 0 15 read-write PRE_PROG 1 during pre-program operation 25 26 read-write PRE_PROG_CSL 0: CSL lines driven by CSL_DAC 1: CSL lines driven by VNEG_G 26 27 read-write PUMP_EN Pump enable: 0: disabled 1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired. 29 30 read-write SCALE Timer tick scale: 0: 1 microsecond. 1: 100 microseconds. 15 16 read-write TIMER_EN Timer enable: 0: disabled 1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. 31 32 read-write WAIT_CTL Wait State control 0x28 32 read-write n 0x0 0x0 DRMM 0: Normal 1: Test mode to enable Margin mode for 2 rows at a time 27 28 read-write FM_RWW_MODE 00: Full CBUS MODE 01: RWW 10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration 24 26 read-write LV_SPARE_1 Spare register 26 27 read-write MBA 0: Normal 1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program). 28 29 read-write PL_SOFT_SET_EN Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API 29 30 read-write WAIT_FM_HV_RD Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit 8 12 read-write WAIT_FM_HV_WR Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. 16 19 read-write WAIT_FM_MEM_RD Number of C interface wait cycles (on 'clk_c') for a read from the memory 0 4 read-write IPC IPC IPC 0x0 0x0 0x10000 registers n ACQUIRE IPC acquire 0x0 32 read-only n 0x0 0x0 MS This field specifies the bus master identifier that successfully acquired the lock. 8 12 read-only NS Secure/non-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock. 1 2 read-only P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock. 0 1 read-only PC This field specifies the protection context that successfully acquired the lock. 4 8 read-only SUCCESS Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). 31 32 read-only DATA0 IPC data 0 0xC 32 read-write n 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. 0 32 read-write DATA1 IPC data 1 0x10 32 read-write n 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. 0 32 read-write INTR Interrupt 0x0 32 read-write n 0x0 0x0 NOTIFY These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. 16 32 read-write RELEASE These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. 0 16 read-write INTR_MASK Interrupt mask 0x8 32 read-write n 0x0 0x0 NOTIFY Mask bit for corresponding field in the INTR register. 16 32 read-write RELEASE Mask bit for corresponding field in the INTR register. 0 16 read-write INTR_MASKED Interrupt masked 0xC 32 read-only n 0x0 0x0 NOTIFY Logical and of corresponding INTR and INTR_MASK fields. 16 32 read-only RELEASE Logical and of corresponding request and mask bits. 0 16 read-only INTR_SET Interrupt set 0x4 32 read-write n 0x0 0x0 NOTIFY SW writes a '1' to this field to set the corresponding field in the INTR register. 16 32 read-write RELEASE SW writes a '1' to this field to set the corresponding field in the INTR register. 0 16 read-write LOCK_STATUS IPC lock status 0x1C 32 read-only n 0x0 0x0 ACQUIRED Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. 31 32 read-only MS This field specifies the bus master identifier that successfully acquired the lock. 8 12 read-only NS This field specifies the secure/non-secure access control: '0': secure. '1': non-secure. 1 2 read-only P This field specifies the user/privileged access control: '0': user mode. '1': privileged mode. 0 1 read-only PC This field specifies the protection context that successfully acquired the lock. 4 8 read-only NOTIFY IPC notification 0x8 32 write-only n 0x0 0x0 INTR_NOTIFY This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. 0 16 write-only RELEASE IPC release 0x4 32 write-only n 0x0 0x0 INTR_RELEASE Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. 0 16 write-only PERI Peripheral interconnect PERI 0x0 0x0 0x10000 registers n CLOCK_CTL Clock control 0x0 32 read-write n 0x0 0x0 INT8_DIV Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write CLOCK_CTL0 Clock control 0xC00 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL1 Clock control 0xC04 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL10 Clock control 0xC28 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL100 Clock control 0xD90 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL101 Clock control 0xD94 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL102 Clock control 0xD98 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL103 Clock control 0xD9C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL104 Clock control 0xDA0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL105 Clock control 0xDA4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL106 Clock control 0xDA8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL107 Clock control 0xDAC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL108 Clock control 0xDB0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL109 Clock control 0xDB4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL11 Clock control 0xC2C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL110 Clock control 0xDB8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL111 Clock control 0xDBC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL112 Clock control 0xDC0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL113 Clock control 0xDC4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL114 Clock control 0xDC8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL115 Clock control 0xDCC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL116 Clock control 0xDD0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL117 Clock control 0xDD4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL118 Clock control 0xDD8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL119 Clock control 0xDDC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL12 Clock control 0xC30 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL120 Clock control 0xDE0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL121 Clock control 0xDE4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL122 Clock control 0xDE8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL123 Clock control 0xDEC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL124 Clock control 0xDF0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL125 Clock control 0xDF4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL126 Clock control 0xDF8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL127 Clock control 0xDFC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL128 Clock control 0xE00 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL129 Clock control 0xE04 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL13 Clock control 0xC34 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL130 Clock control 0xE08 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL131 Clock control 0xE0C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL132 Clock control 0xE10 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL133 Clock control 0xE14 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL134 Clock control 0xE18 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL135 Clock control 0xE1C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL136 Clock control 0xE20 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL137 Clock control 0xE24 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL138 Clock control 0xE28 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL139 Clock control 0xE2C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL14 Clock control 0xC38 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL140 Clock control 0xE30 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL141 Clock control 0xE34 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL142 Clock control 0xE38 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL143 Clock control 0xE3C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL144 Clock control 0xE40 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL145 Clock control 0xE44 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL146 Clock control 0xE48 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL147 Clock control 0xE4C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL148 Clock control 0xE50 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL149 Clock control 0xE54 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL15 Clock control 0xC3C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL150 Clock control 0xE58 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL151 Clock control 0xE5C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL152 Clock control 0xE60 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL153 Clock control 0xE64 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL154 Clock control 0xE68 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL155 Clock control 0xE6C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL156 Clock control 0xE70 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL157 Clock control 0xE74 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL158 Clock control 0xE78 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL159 Clock control 0xE7C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL16 Clock control 0xC40 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL160 Clock control 0xE80 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL161 Clock control 0xE84 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL162 Clock control 0xE88 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL163 Clock control 0xE8C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL164 Clock control 0xE90 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL165 Clock control 0xE94 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL166 Clock control 0xE98 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL167 Clock control 0xE9C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL168 Clock control 0xEA0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL169 Clock control 0xEA4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL17 Clock control 0xC44 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL170 Clock control 0xEA8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL171 Clock control 0xEAC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL172 Clock control 0xEB0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL173 Clock control 0xEB4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL174 Clock control 0xEB8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL175 Clock control 0xEBC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL176 Clock control 0xEC0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL177 Clock control 0xEC4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL178 Clock control 0xEC8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL179 Clock control 0xECC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL18 Clock control 0xC48 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL180 Clock control 0xED0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL181 Clock control 0xED4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL182 Clock control 0xED8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL183 Clock control 0xEDC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL184 Clock control 0xEE0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL185 Clock control 0xEE4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL186 Clock control 0xEE8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL187 Clock control 0xEEC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL188 Clock control 0xEF0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL189 Clock control 0xEF4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL19 Clock control 0xC4C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL190 Clock control 0xEF8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL191 Clock control 0xEFC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL192 Clock control 0xF00 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL193 Clock control 0xF04 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL194 Clock control 0xF08 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL195 Clock control 0xF0C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL196 Clock control 0xF10 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL197 Clock control 0xF14 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL198 Clock control 0xF18 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL199 Clock control 0xF1C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL2 Clock control 0xC08 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL20 Clock control 0xC50 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL200 Clock control 0xF20 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL201 Clock control 0xF24 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL202 Clock control 0xF28 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL203 Clock control 0xF2C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL204 Clock control 0xF30 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL205 Clock control 0xF34 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL206 Clock control 0xF38 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL207 Clock control 0xF3C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL208 Clock control 0xF40 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL209 Clock control 0xF44 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL21 Clock control 0xC54 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL210 Clock control 0xF48 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL211 Clock control 0xF4C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL212 Clock control 0xF50 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL213 Clock control 0xF54 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL214 Clock control 0xF58 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL215 Clock control 0xF5C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL216 Clock control 0xF60 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL217 Clock control 0xF64 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL218 Clock control 0xF68 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL219 Clock control 0xF6C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL22 Clock control 0xC58 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL220 Clock control 0xF70 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL221 Clock control 0xF74 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL222 Clock control 0xF78 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL223 Clock control 0xF7C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL224 Clock control 0xF80 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL225 Clock control 0xF84 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL226 Clock control 0xF88 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL227 Clock control 0xF8C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL228 Clock control 0xF90 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL229 Clock control 0xF94 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL23 Clock control 0xC5C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL230 Clock control 0xF98 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL231 Clock control 0xF9C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL232 Clock control 0xFA0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL233 Clock control 0xFA4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL234 Clock control 0xFA8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL235 Clock control 0xFAC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL236 Clock control 0xFB0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL237 Clock control 0xFB4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL238 Clock control 0xFB8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL239 Clock control 0xFBC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL24 Clock control 0xC60 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL240 Clock control 0xFC0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL241 Clock control 0xFC4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL242 Clock control 0xFC8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL243 Clock control 0xFCC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL244 Clock control 0xFD0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL245 Clock control 0xFD4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL246 Clock control 0xFD8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL247 Clock control 0xFDC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL248 Clock control 0xFE0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL249 Clock control 0xFE4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL25 Clock control 0xC64 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL250 Clock control 0xFE8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL251 Clock control 0xFEC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL252 Clock control 0xFF0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL253 Clock control 0xFF4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL254 Clock control 0xFF8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL255 Clock control 0xFFC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL26 Clock control 0xC68 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL27 Clock control 0xC6C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL28 Clock control 0xC70 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL29 Clock control 0xC74 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL3 Clock control 0xC0C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL30 Clock control 0xC78 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL31 Clock control 0xC7C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL32 Clock control 0xC80 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL33 Clock control 0xC84 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL34 Clock control 0xC88 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL35 Clock control 0xC8C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL36 Clock control 0xC90 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL37 Clock control 0xC94 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL38 Clock control 0xC98 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL39 Clock control 0xC9C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL4 Clock control 0xC10 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL40 Clock control 0xCA0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL41 Clock control 0xCA4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL42 Clock control 0xCA8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL43 Clock control 0xCAC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL44 Clock control 0xCB0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL45 Clock control 0xCB4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL46 Clock control 0xCB8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL47 Clock control 0xCBC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL48 Clock control 0xCC0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL49 Clock control 0xCC4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL5 Clock control 0xC14 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL50 Clock control 0xCC8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL51 Clock control 0xCCC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL52 Clock control 0xCD0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL53 Clock control 0xCD4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL54 Clock control 0xCD8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL55 Clock control 0xCDC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL56 Clock control 0xCE0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL57 Clock control 0xCE4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL58 Clock control 0xCE8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL59 Clock control 0xCEC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL6 Clock control 0xC18 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL60 Clock control 0xCF0 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL61 Clock control 0xCF4 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL62 Clock control 0xCF8 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL63 Clock control 0xCFC 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL64 Clock control 0xD00 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL65 Clock control 0xD04 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL66 Clock control 0xD08 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL67 Clock control 0xD0C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL68 Clock control 0xD10 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL69 Clock control 0xD14 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL7 Clock control 0xC1C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL70 Clock control 0xD18 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL71 Clock control 0xD1C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL72 Clock control 0xD20 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL73 Clock control 0xD24 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL74 Clock control 0xD28 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL75 Clock control 0xD2C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL76 Clock control 0xD30 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL77 Clock control 0xD34 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL78 Clock control 0xD38 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL79 Clock control 0xD3C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL8 Clock control 0xC20 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL80 Clock control 0xD40 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL81 Clock control 0xD44 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL82 Clock control 0xD48 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL83 Clock control 0xD4C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL84 Clock control 0xD50 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL85 Clock control 0xD54 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL86 Clock control 0xD58 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL87 Clock control 0xD5C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL88 Clock control 0xD60 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL89 Clock control 0xD64 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL9 Clock control 0xC24 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL90 Clock control 0xD68 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL91 Clock control 0xD6C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL92 Clock control 0xD70 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL93 Clock control 0xD74 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL94 Clock control 0xD78 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL95 Clock control 0xD7C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL96 Clock control 0xD80 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL97 Clock control 0xD84 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL98 Clock control 0xD88 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write CLOCK_CTL99 Clock control 0xD8C 32 read-write n 0x0 0x0 DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. 0 8 read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write DIV_16_5_CTL0 Divider control (for 16.5 divider) 0x1800 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL1 Divider control (for 16.5 divider) 0x1804 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL10 Divider control (for 16.5 divider) 0x1828 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL100 Divider control (for 16.5 divider) 0x1990 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL101 Divider control (for 16.5 divider) 0x1994 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL102 Divider control (for 16.5 divider) 0x1998 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL103 Divider control (for 16.5 divider) 0x199C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL104 Divider control (for 16.5 divider) 0x19A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL105 Divider control (for 16.5 divider) 0x19A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL106 Divider control (for 16.5 divider) 0x19A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL107 Divider control (for 16.5 divider) 0x19AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL108 Divider control (for 16.5 divider) 0x19B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL109 Divider control (for 16.5 divider) 0x19B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL11 Divider control (for 16.5 divider) 0x182C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL110 Divider control (for 16.5 divider) 0x19B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL111 Divider control (for 16.5 divider) 0x19BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL112 Divider control (for 16.5 divider) 0x19C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL113 Divider control (for 16.5 divider) 0x19C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL114 Divider control (for 16.5 divider) 0x19C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL115 Divider control (for 16.5 divider) 0x19CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL116 Divider control (for 16.5 divider) 0x19D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL117 Divider control (for 16.5 divider) 0x19D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL118 Divider control (for 16.5 divider) 0x19D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL119 Divider control (for 16.5 divider) 0x19DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL12 Divider control (for 16.5 divider) 0x1830 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL120 Divider control (for 16.5 divider) 0x19E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL121 Divider control (for 16.5 divider) 0x19E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL122 Divider control (for 16.5 divider) 0x19E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL123 Divider control (for 16.5 divider) 0x19EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL124 Divider control (for 16.5 divider) 0x19F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL125 Divider control (for 16.5 divider) 0x19F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL126 Divider control (for 16.5 divider) 0x19F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL127 Divider control (for 16.5 divider) 0x19FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL128 Divider control (for 16.5 divider) 0x1A00 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL129 Divider control (for 16.5 divider) 0x1A04 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL13 Divider control (for 16.5 divider) 0x1834 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL130 Divider control (for 16.5 divider) 0x1A08 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL131 Divider control (for 16.5 divider) 0x1A0C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL132 Divider control (for 16.5 divider) 0x1A10 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL133 Divider control (for 16.5 divider) 0x1A14 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL134 Divider control (for 16.5 divider) 0x1A18 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL135 Divider control (for 16.5 divider) 0x1A1C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL136 Divider control (for 16.5 divider) 0x1A20 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL137 Divider control (for 16.5 divider) 0x1A24 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL138 Divider control (for 16.5 divider) 0x1A28 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL139 Divider control (for 16.5 divider) 0x1A2C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL14 Divider control (for 16.5 divider) 0x1838 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL140 Divider control (for 16.5 divider) 0x1A30 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL141 Divider control (for 16.5 divider) 0x1A34 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL142 Divider control (for 16.5 divider) 0x1A38 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL143 Divider control (for 16.5 divider) 0x1A3C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL144 Divider control (for 16.5 divider) 0x1A40 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL145 Divider control (for 16.5 divider) 0x1A44 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL146 Divider control (for 16.5 divider) 0x1A48 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL147 Divider control (for 16.5 divider) 0x1A4C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL148 Divider control (for 16.5 divider) 0x1A50 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL149 Divider control (for 16.5 divider) 0x1A54 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL15 Divider control (for 16.5 divider) 0x183C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL150 Divider control (for 16.5 divider) 0x1A58 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL151 Divider control (for 16.5 divider) 0x1A5C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL152 Divider control (for 16.5 divider) 0x1A60 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL153 Divider control (for 16.5 divider) 0x1A64 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL154 Divider control (for 16.5 divider) 0x1A68 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL155 Divider control (for 16.5 divider) 0x1A6C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL156 Divider control (for 16.5 divider) 0x1A70 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL157 Divider control (for 16.5 divider) 0x1A74 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL158 Divider control (for 16.5 divider) 0x1A78 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL159 Divider control (for 16.5 divider) 0x1A7C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL16 Divider control (for 16.5 divider) 0x1840 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL160 Divider control (for 16.5 divider) 0x1A80 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL161 Divider control (for 16.5 divider) 0x1A84 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL162 Divider control (for 16.5 divider) 0x1A88 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL163 Divider control (for 16.5 divider) 0x1A8C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL164 Divider control (for 16.5 divider) 0x1A90 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL165 Divider control (for 16.5 divider) 0x1A94 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL166 Divider control (for 16.5 divider) 0x1A98 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL167 Divider control (for 16.5 divider) 0x1A9C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL168 Divider control (for 16.5 divider) 0x1AA0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL169 Divider control (for 16.5 divider) 0x1AA4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL17 Divider control (for 16.5 divider) 0x1844 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL170 Divider control (for 16.5 divider) 0x1AA8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL171 Divider control (for 16.5 divider) 0x1AAC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL172 Divider control (for 16.5 divider) 0x1AB0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL173 Divider control (for 16.5 divider) 0x1AB4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL174 Divider control (for 16.5 divider) 0x1AB8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL175 Divider control (for 16.5 divider) 0x1ABC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL176 Divider control (for 16.5 divider) 0x1AC0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL177 Divider control (for 16.5 divider) 0x1AC4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL178 Divider control (for 16.5 divider) 0x1AC8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL179 Divider control (for 16.5 divider) 0x1ACC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL18 Divider control (for 16.5 divider) 0x1848 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL180 Divider control (for 16.5 divider) 0x1AD0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL181 Divider control (for 16.5 divider) 0x1AD4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL182 Divider control (for 16.5 divider) 0x1AD8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL183 Divider control (for 16.5 divider) 0x1ADC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL184 Divider control (for 16.5 divider) 0x1AE0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL185 Divider control (for 16.5 divider) 0x1AE4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL186 Divider control (for 16.5 divider) 0x1AE8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL187 Divider control (for 16.5 divider) 0x1AEC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL188 Divider control (for 16.5 divider) 0x1AF0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL189 Divider control (for 16.5 divider) 0x1AF4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL19 Divider control (for 16.5 divider) 0x184C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL190 Divider control (for 16.5 divider) 0x1AF8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL191 Divider control (for 16.5 divider) 0x1AFC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL192 Divider control (for 16.5 divider) 0x1B00 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL193 Divider control (for 16.5 divider) 0x1B04 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL194 Divider control (for 16.5 divider) 0x1B08 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL195 Divider control (for 16.5 divider) 0x1B0C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL196 Divider control (for 16.5 divider) 0x1B10 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL197 Divider control (for 16.5 divider) 0x1B14 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL198 Divider control (for 16.5 divider) 0x1B18 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL199 Divider control (for 16.5 divider) 0x1B1C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL2 Divider control (for 16.5 divider) 0x1808 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL20 Divider control (for 16.5 divider) 0x1850 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL200 Divider control (for 16.5 divider) 0x1B20 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL201 Divider control (for 16.5 divider) 0x1B24 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL202 Divider control (for 16.5 divider) 0x1B28 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL203 Divider control (for 16.5 divider) 0x1B2C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL204 Divider control (for 16.5 divider) 0x1B30 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL205 Divider control (for 16.5 divider) 0x1B34 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL206 Divider control (for 16.5 divider) 0x1B38 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL207 Divider control (for 16.5 divider) 0x1B3C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL208 Divider control (for 16.5 divider) 0x1B40 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL209 Divider control (for 16.5 divider) 0x1B44 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL21 Divider control (for 16.5 divider) 0x1854 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL210 Divider control (for 16.5 divider) 0x1B48 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL211 Divider control (for 16.5 divider) 0x1B4C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL212 Divider control (for 16.5 divider) 0x1B50 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL213 Divider control (for 16.5 divider) 0x1B54 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL214 Divider control (for 16.5 divider) 0x1B58 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL215 Divider control (for 16.5 divider) 0x1B5C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL216 Divider control (for 16.5 divider) 0x1B60 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL217 Divider control (for 16.5 divider) 0x1B64 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL218 Divider control (for 16.5 divider) 0x1B68 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL219 Divider control (for 16.5 divider) 0x1B6C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL22 Divider control (for 16.5 divider) 0x1858 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL220 Divider control (for 16.5 divider) 0x1B70 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL221 Divider control (for 16.5 divider) 0x1B74 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL222 Divider control (for 16.5 divider) 0x1B78 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL223 Divider control (for 16.5 divider) 0x1B7C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL224 Divider control (for 16.5 divider) 0x1B80 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL225 Divider control (for 16.5 divider) 0x1B84 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL226 Divider control (for 16.5 divider) 0x1B88 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL227 Divider control (for 16.5 divider) 0x1B8C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL228 Divider control (for 16.5 divider) 0x1B90 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL229 Divider control (for 16.5 divider) 0x1B94 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL23 Divider control (for 16.5 divider) 0x185C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL230 Divider control (for 16.5 divider) 0x1B98 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL231 Divider control (for 16.5 divider) 0x1B9C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL232 Divider control (for 16.5 divider) 0x1BA0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL233 Divider control (for 16.5 divider) 0x1BA4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL234 Divider control (for 16.5 divider) 0x1BA8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL235 Divider control (for 16.5 divider) 0x1BAC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL236 Divider control (for 16.5 divider) 0x1BB0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL237 Divider control (for 16.5 divider) 0x1BB4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL238 Divider control (for 16.5 divider) 0x1BB8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL239 Divider control (for 16.5 divider) 0x1BBC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL24 Divider control (for 16.5 divider) 0x1860 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL240 Divider control (for 16.5 divider) 0x1BC0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL241 Divider control (for 16.5 divider) 0x1BC4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL242 Divider control (for 16.5 divider) 0x1BC8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL243 Divider control (for 16.5 divider) 0x1BCC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL244 Divider control (for 16.5 divider) 0x1BD0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL245 Divider control (for 16.5 divider) 0x1BD4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL246 Divider control (for 16.5 divider) 0x1BD8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL247 Divider control (for 16.5 divider) 0x1BDC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL248 Divider control (for 16.5 divider) 0x1BE0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL249 Divider control (for 16.5 divider) 0x1BE4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL25 Divider control (for 16.5 divider) 0x1864 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL250 Divider control (for 16.5 divider) 0x1BE8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL251 Divider control (for 16.5 divider) 0x1BEC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL252 Divider control (for 16.5 divider) 0x1BF0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL253 Divider control (for 16.5 divider) 0x1BF4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL254 Divider control (for 16.5 divider) 0x1BF8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL255 Divider control (for 16.5 divider) 0x1BFC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL26 Divider control (for 16.5 divider) 0x1868 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL27 Divider control (for 16.5 divider) 0x186C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL28 Divider control (for 16.5 divider) 0x1870 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL29 Divider control (for 16.5 divider) 0x1874 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL3 Divider control (for 16.5 divider) 0x180C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL30 Divider control (for 16.5 divider) 0x1878 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL31 Divider control (for 16.5 divider) 0x187C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL32 Divider control (for 16.5 divider) 0x1880 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL33 Divider control (for 16.5 divider) 0x1884 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL34 Divider control (for 16.5 divider) 0x1888 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL35 Divider control (for 16.5 divider) 0x188C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL36 Divider control (for 16.5 divider) 0x1890 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL37 Divider control (for 16.5 divider) 0x1894 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL38 Divider control (for 16.5 divider) 0x1898 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL39 Divider control (for 16.5 divider) 0x189C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL4 Divider control (for 16.5 divider) 0x1810 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL40 Divider control (for 16.5 divider) 0x18A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL41 Divider control (for 16.5 divider) 0x18A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL42 Divider control (for 16.5 divider) 0x18A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL43 Divider control (for 16.5 divider) 0x18AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL44 Divider control (for 16.5 divider) 0x18B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL45 Divider control (for 16.5 divider) 0x18B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL46 Divider control (for 16.5 divider) 0x18B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL47 Divider control (for 16.5 divider) 0x18BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL48 Divider control (for 16.5 divider) 0x18C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL49 Divider control (for 16.5 divider) 0x18C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL5 Divider control (for 16.5 divider) 0x1814 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL50 Divider control (for 16.5 divider) 0x18C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL51 Divider control (for 16.5 divider) 0x18CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL52 Divider control (for 16.5 divider) 0x18D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL53 Divider control (for 16.5 divider) 0x18D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL54 Divider control (for 16.5 divider) 0x18D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL55 Divider control (for 16.5 divider) 0x18DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL56 Divider control (for 16.5 divider) 0x18E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL57 Divider control (for 16.5 divider) 0x18E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL58 Divider control (for 16.5 divider) 0x18E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL59 Divider control (for 16.5 divider) 0x18EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL6 Divider control (for 16.5 divider) 0x1818 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL60 Divider control (for 16.5 divider) 0x18F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL61 Divider control (for 16.5 divider) 0x18F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL62 Divider control (for 16.5 divider) 0x18F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL63 Divider control (for 16.5 divider) 0x18FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL64 Divider control (for 16.5 divider) 0x1900 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL65 Divider control (for 16.5 divider) 0x1904 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL66 Divider control (for 16.5 divider) 0x1908 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL67 Divider control (for 16.5 divider) 0x190C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL68 Divider control (for 16.5 divider) 0x1910 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL69 Divider control (for 16.5 divider) 0x1914 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL7 Divider control (for 16.5 divider) 0x181C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL70 Divider control (for 16.5 divider) 0x1918 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL71 Divider control (for 16.5 divider) 0x191C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL72 Divider control (for 16.5 divider) 0x1920 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL73 Divider control (for 16.5 divider) 0x1924 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL74 Divider control (for 16.5 divider) 0x1928 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL75 Divider control (for 16.5 divider) 0x192C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL76 Divider control (for 16.5 divider) 0x1930 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL77 Divider control (for 16.5 divider) 0x1934 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL78 Divider control (for 16.5 divider) 0x1938 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL79 Divider control (for 16.5 divider) 0x193C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL8 Divider control (for 16.5 divider) 0x1820 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL80 Divider control (for 16.5 divider) 0x1940 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL81 Divider control (for 16.5 divider) 0x1944 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL82 Divider control (for 16.5 divider) 0x1948 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL83 Divider control (for 16.5 divider) 0x194C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL84 Divider control (for 16.5 divider) 0x1950 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL85 Divider control (for 16.5 divider) 0x1954 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL86 Divider control (for 16.5 divider) 0x1958 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL87 Divider control (for 16.5 divider) 0x195C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL88 Divider control (for 16.5 divider) 0x1960 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL89 Divider control (for 16.5 divider) 0x1964 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL9 Divider control (for 16.5 divider) 0x1824 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL90 Divider control (for 16.5 divider) 0x1968 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL91 Divider control (for 16.5 divider) 0x196C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL92 Divider control (for 16.5 divider) 0x1970 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL93 Divider control (for 16.5 divider) 0x1974 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL94 Divider control (for 16.5 divider) 0x1978 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL95 Divider control (for 16.5 divider) 0x197C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL96 Divider control (for 16.5 divider) 0x1980 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL97 Divider control (for 16.5 divider) 0x1984 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL98 Divider control (for 16.5 divider) 0x1988 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL99 Divider control (for 16.5 divider) 0x198C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL0 Divider control (for 16.0 divider) 0x1400 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL1 Divider control (for 16.0 divider) 0x1404 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL10 Divider control (for 16.0 divider) 0x1428 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL100 Divider control (for 16.0 divider) 0x1590 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL101 Divider control (for 16.0 divider) 0x1594 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL102 Divider control (for 16.0 divider) 0x1598 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL103 Divider control (for 16.0 divider) 0x159C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL104 Divider control (for 16.0 divider) 0x15A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL105 Divider control (for 16.0 divider) 0x15A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL106 Divider control (for 16.0 divider) 0x15A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL107 Divider control (for 16.0 divider) 0x15AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL108 Divider control (for 16.0 divider) 0x15B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL109 Divider control (for 16.0 divider) 0x15B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL11 Divider control (for 16.0 divider) 0x142C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL110 Divider control (for 16.0 divider) 0x15B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL111 Divider control (for 16.0 divider) 0x15BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL112 Divider control (for 16.0 divider) 0x15C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL113 Divider control (for 16.0 divider) 0x15C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL114 Divider control (for 16.0 divider) 0x15C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL115 Divider control (for 16.0 divider) 0x15CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL116 Divider control (for 16.0 divider) 0x15D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL117 Divider control (for 16.0 divider) 0x15D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL118 Divider control (for 16.0 divider) 0x15D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL119 Divider control (for 16.0 divider) 0x15DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL12 Divider control (for 16.0 divider) 0x1430 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL120 Divider control (for 16.0 divider) 0x15E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL121 Divider control (for 16.0 divider) 0x15E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL122 Divider control (for 16.0 divider) 0x15E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL123 Divider control (for 16.0 divider) 0x15EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL124 Divider control (for 16.0 divider) 0x15F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL125 Divider control (for 16.0 divider) 0x15F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL126 Divider control (for 16.0 divider) 0x15F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL127 Divider control (for 16.0 divider) 0x15FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL128 Divider control (for 16.0 divider) 0x1600 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL129 Divider control (for 16.0 divider) 0x1604 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL13 Divider control (for 16.0 divider) 0x1434 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL130 Divider control (for 16.0 divider) 0x1608 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL131 Divider control (for 16.0 divider) 0x160C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL132 Divider control (for 16.0 divider) 0x1610 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL133 Divider control (for 16.0 divider) 0x1614 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL134 Divider control (for 16.0 divider) 0x1618 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL135 Divider control (for 16.0 divider) 0x161C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL136 Divider control (for 16.0 divider) 0x1620 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL137 Divider control (for 16.0 divider) 0x1624 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL138 Divider control (for 16.0 divider) 0x1628 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL139 Divider control (for 16.0 divider) 0x162C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL14 Divider control (for 16.0 divider) 0x1438 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL140 Divider control (for 16.0 divider) 0x1630 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL141 Divider control (for 16.0 divider) 0x1634 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL142 Divider control (for 16.0 divider) 0x1638 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL143 Divider control (for 16.0 divider) 0x163C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL144 Divider control (for 16.0 divider) 0x1640 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL145 Divider control (for 16.0 divider) 0x1644 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL146 Divider control (for 16.0 divider) 0x1648 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL147 Divider control (for 16.0 divider) 0x164C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL148 Divider control (for 16.0 divider) 0x1650 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL149 Divider control (for 16.0 divider) 0x1654 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL15 Divider control (for 16.0 divider) 0x143C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL150 Divider control (for 16.0 divider) 0x1658 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL151 Divider control (for 16.0 divider) 0x165C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL152 Divider control (for 16.0 divider) 0x1660 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL153 Divider control (for 16.0 divider) 0x1664 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL154 Divider control (for 16.0 divider) 0x1668 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL155 Divider control (for 16.0 divider) 0x166C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL156 Divider control (for 16.0 divider) 0x1670 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL157 Divider control (for 16.0 divider) 0x1674 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL158 Divider control (for 16.0 divider) 0x1678 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL159 Divider control (for 16.0 divider) 0x167C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL16 Divider control (for 16.0 divider) 0x1440 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL160 Divider control (for 16.0 divider) 0x1680 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL161 Divider control (for 16.0 divider) 0x1684 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL162 Divider control (for 16.0 divider) 0x1688 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL163 Divider control (for 16.0 divider) 0x168C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL164 Divider control (for 16.0 divider) 0x1690 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL165 Divider control (for 16.0 divider) 0x1694 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL166 Divider control (for 16.0 divider) 0x1698 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL167 Divider control (for 16.0 divider) 0x169C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL168 Divider control (for 16.0 divider) 0x16A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL169 Divider control (for 16.0 divider) 0x16A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL17 Divider control (for 16.0 divider) 0x1444 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL170 Divider control (for 16.0 divider) 0x16A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL171 Divider control (for 16.0 divider) 0x16AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL172 Divider control (for 16.0 divider) 0x16B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL173 Divider control (for 16.0 divider) 0x16B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL174 Divider control (for 16.0 divider) 0x16B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL175 Divider control (for 16.0 divider) 0x16BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL176 Divider control (for 16.0 divider) 0x16C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL177 Divider control (for 16.0 divider) 0x16C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL178 Divider control (for 16.0 divider) 0x16C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL179 Divider control (for 16.0 divider) 0x16CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL18 Divider control (for 16.0 divider) 0x1448 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL180 Divider control (for 16.0 divider) 0x16D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL181 Divider control (for 16.0 divider) 0x16D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL182 Divider control (for 16.0 divider) 0x16D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL183 Divider control (for 16.0 divider) 0x16DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL184 Divider control (for 16.0 divider) 0x16E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL185 Divider control (for 16.0 divider) 0x16E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL186 Divider control (for 16.0 divider) 0x16E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL187 Divider control (for 16.0 divider) 0x16EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL188 Divider control (for 16.0 divider) 0x16F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL189 Divider control (for 16.0 divider) 0x16F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL19 Divider control (for 16.0 divider) 0x144C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL190 Divider control (for 16.0 divider) 0x16F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL191 Divider control (for 16.0 divider) 0x16FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL192 Divider control (for 16.0 divider) 0x1700 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL193 Divider control (for 16.0 divider) 0x1704 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL194 Divider control (for 16.0 divider) 0x1708 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL195 Divider control (for 16.0 divider) 0x170C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL196 Divider control (for 16.0 divider) 0x1710 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL197 Divider control (for 16.0 divider) 0x1714 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL198 Divider control (for 16.0 divider) 0x1718 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL199 Divider control (for 16.0 divider) 0x171C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL2 Divider control (for 16.0 divider) 0x1408 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL20 Divider control (for 16.0 divider) 0x1450 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL200 Divider control (for 16.0 divider) 0x1720 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL201 Divider control (for 16.0 divider) 0x1724 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL202 Divider control (for 16.0 divider) 0x1728 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL203 Divider control (for 16.0 divider) 0x172C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL204 Divider control (for 16.0 divider) 0x1730 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL205 Divider control (for 16.0 divider) 0x1734 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL206 Divider control (for 16.0 divider) 0x1738 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL207 Divider control (for 16.0 divider) 0x173C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL208 Divider control (for 16.0 divider) 0x1740 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL209 Divider control (for 16.0 divider) 0x1744 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL21 Divider control (for 16.0 divider) 0x1454 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL210 Divider control (for 16.0 divider) 0x1748 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL211 Divider control (for 16.0 divider) 0x174C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL212 Divider control (for 16.0 divider) 0x1750 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL213 Divider control (for 16.0 divider) 0x1754 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL214 Divider control (for 16.0 divider) 0x1758 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL215 Divider control (for 16.0 divider) 0x175C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL216 Divider control (for 16.0 divider) 0x1760 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL217 Divider control (for 16.0 divider) 0x1764 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL218 Divider control (for 16.0 divider) 0x1768 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL219 Divider control (for 16.0 divider) 0x176C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL22 Divider control (for 16.0 divider) 0x1458 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL220 Divider control (for 16.0 divider) 0x1770 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL221 Divider control (for 16.0 divider) 0x1774 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL222 Divider control (for 16.0 divider) 0x1778 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL223 Divider control (for 16.0 divider) 0x177C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL224 Divider control (for 16.0 divider) 0x1780 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL225 Divider control (for 16.0 divider) 0x1784 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL226 Divider control (for 16.0 divider) 0x1788 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL227 Divider control (for 16.0 divider) 0x178C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL228 Divider control (for 16.0 divider) 0x1790 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL229 Divider control (for 16.0 divider) 0x1794 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL23 Divider control (for 16.0 divider) 0x145C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL230 Divider control (for 16.0 divider) 0x1798 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL231 Divider control (for 16.0 divider) 0x179C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL232 Divider control (for 16.0 divider) 0x17A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL233 Divider control (for 16.0 divider) 0x17A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL234 Divider control (for 16.0 divider) 0x17A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL235 Divider control (for 16.0 divider) 0x17AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL236 Divider control (for 16.0 divider) 0x17B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL237 Divider control (for 16.0 divider) 0x17B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL238 Divider control (for 16.0 divider) 0x17B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL239 Divider control (for 16.0 divider) 0x17BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL24 Divider control (for 16.0 divider) 0x1460 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL240 Divider control (for 16.0 divider) 0x17C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL241 Divider control (for 16.0 divider) 0x17C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL242 Divider control (for 16.0 divider) 0x17C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL243 Divider control (for 16.0 divider) 0x17CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL244 Divider control (for 16.0 divider) 0x17D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL245 Divider control (for 16.0 divider) 0x17D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL246 Divider control (for 16.0 divider) 0x17D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL247 Divider control (for 16.0 divider) 0x17DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL248 Divider control (for 16.0 divider) 0x17E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL249 Divider control (for 16.0 divider) 0x17E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL25 Divider control (for 16.0 divider) 0x1464 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL250 Divider control (for 16.0 divider) 0x17E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL251 Divider control (for 16.0 divider) 0x17EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL252 Divider control (for 16.0 divider) 0x17F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL253 Divider control (for 16.0 divider) 0x17F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL254 Divider control (for 16.0 divider) 0x17F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL255 Divider control (for 16.0 divider) 0x17FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL26 Divider control (for 16.0 divider) 0x1468 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL27 Divider control (for 16.0 divider) 0x146C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL28 Divider control (for 16.0 divider) 0x1470 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL29 Divider control (for 16.0 divider) 0x1474 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL3 Divider control (for 16.0 divider) 0x140C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL30 Divider control (for 16.0 divider) 0x1478 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL31 Divider control (for 16.0 divider) 0x147C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL32 Divider control (for 16.0 divider) 0x1480 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL33 Divider control (for 16.0 divider) 0x1484 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL34 Divider control (for 16.0 divider) 0x1488 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL35 Divider control (for 16.0 divider) 0x148C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL36 Divider control (for 16.0 divider) 0x1490 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL37 Divider control (for 16.0 divider) 0x1494 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL38 Divider control (for 16.0 divider) 0x1498 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL39 Divider control (for 16.0 divider) 0x149C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL4 Divider control (for 16.0 divider) 0x1410 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL40 Divider control (for 16.0 divider) 0x14A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL41 Divider control (for 16.0 divider) 0x14A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL42 Divider control (for 16.0 divider) 0x14A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL43 Divider control (for 16.0 divider) 0x14AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL44 Divider control (for 16.0 divider) 0x14B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL45 Divider control (for 16.0 divider) 0x14B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL46 Divider control (for 16.0 divider) 0x14B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL47 Divider control (for 16.0 divider) 0x14BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL48 Divider control (for 16.0 divider) 0x14C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL49 Divider control (for 16.0 divider) 0x14C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL5 Divider control (for 16.0 divider) 0x1414 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL50 Divider control (for 16.0 divider) 0x14C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL51 Divider control (for 16.0 divider) 0x14CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL52 Divider control (for 16.0 divider) 0x14D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL53 Divider control (for 16.0 divider) 0x14D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL54 Divider control (for 16.0 divider) 0x14D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL55 Divider control (for 16.0 divider) 0x14DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL56 Divider control (for 16.0 divider) 0x14E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL57 Divider control (for 16.0 divider) 0x14E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL58 Divider control (for 16.0 divider) 0x14E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL59 Divider control (for 16.0 divider) 0x14EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL6 Divider control (for 16.0 divider) 0x1418 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL60 Divider control (for 16.0 divider) 0x14F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL61 Divider control (for 16.0 divider) 0x14F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL62 Divider control (for 16.0 divider) 0x14F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL63 Divider control (for 16.0 divider) 0x14FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL64 Divider control (for 16.0 divider) 0x1500 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL65 Divider control (for 16.0 divider) 0x1504 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL66 Divider control (for 16.0 divider) 0x1508 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL67 Divider control (for 16.0 divider) 0x150C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL68 Divider control (for 16.0 divider) 0x1510 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL69 Divider control (for 16.0 divider) 0x1514 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL7 Divider control (for 16.0 divider) 0x141C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL70 Divider control (for 16.0 divider) 0x1518 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL71 Divider control (for 16.0 divider) 0x151C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL72 Divider control (for 16.0 divider) 0x1520 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL73 Divider control (for 16.0 divider) 0x1524 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL74 Divider control (for 16.0 divider) 0x1528 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL75 Divider control (for 16.0 divider) 0x152C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL76 Divider control (for 16.0 divider) 0x1530 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL77 Divider control (for 16.0 divider) 0x1534 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL78 Divider control (for 16.0 divider) 0x1538 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL79 Divider control (for 16.0 divider) 0x153C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL8 Divider control (for 16.0 divider) 0x1420 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL80 Divider control (for 16.0 divider) 0x1540 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL81 Divider control (for 16.0 divider) 0x1544 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL82 Divider control (for 16.0 divider) 0x1548 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL83 Divider control (for 16.0 divider) 0x154C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL84 Divider control (for 16.0 divider) 0x1550 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL85 Divider control (for 16.0 divider) 0x1554 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL86 Divider control (for 16.0 divider) 0x1558 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL87 Divider control (for 16.0 divider) 0x155C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL88 Divider control (for 16.0 divider) 0x1560 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL89 Divider control (for 16.0 divider) 0x1564 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL9 Divider control (for 16.0 divider) 0x1424 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL90 Divider control (for 16.0 divider) 0x1568 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL91 Divider control (for 16.0 divider) 0x156C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL92 Divider control (for 16.0 divider) 0x1570 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL93 Divider control (for 16.0 divider) 0x1574 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL94 Divider control (for 16.0 divider) 0x1578 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL95 Divider control (for 16.0 divider) 0x157C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL96 Divider control (for 16.0 divider) 0x1580 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL97 Divider control (for 16.0 divider) 0x1584 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL98 Divider control (for 16.0 divider) 0x1588 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL99 Divider control (for 16.0 divider) 0x158C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_24_5_CTL0 Divider control (for 24.5 divider) 0x1C00 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL1 Divider control (for 24.5 divider) 0x1C04 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL10 Divider control (for 24.5 divider) 0x1C28 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL100 Divider control (for 24.5 divider) 0x1D90 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL101 Divider control (for 24.5 divider) 0x1D94 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL102 Divider control (for 24.5 divider) 0x1D98 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL103 Divider control (for 24.5 divider) 0x1D9C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL104 Divider control (for 24.5 divider) 0x1DA0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL105 Divider control (for 24.5 divider) 0x1DA4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL106 Divider control (for 24.5 divider) 0x1DA8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL107 Divider control (for 24.5 divider) 0x1DAC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL108 Divider control (for 24.5 divider) 0x1DB0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL109 Divider control (for 24.5 divider) 0x1DB4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL11 Divider control (for 24.5 divider) 0x1C2C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL110 Divider control (for 24.5 divider) 0x1DB8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL111 Divider control (for 24.5 divider) 0x1DBC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL112 Divider control (for 24.5 divider) 0x1DC0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL113 Divider control (for 24.5 divider) 0x1DC4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL114 Divider control (for 24.5 divider) 0x1DC8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL115 Divider control (for 24.5 divider) 0x1DCC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL116 Divider control (for 24.5 divider) 0x1DD0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL117 Divider control (for 24.5 divider) 0x1DD4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL118 Divider control (for 24.5 divider) 0x1DD8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL119 Divider control (for 24.5 divider) 0x1DDC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL12 Divider control (for 24.5 divider) 0x1C30 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL120 Divider control (for 24.5 divider) 0x1DE0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL121 Divider control (for 24.5 divider) 0x1DE4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL122 Divider control (for 24.5 divider) 0x1DE8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL123 Divider control (for 24.5 divider) 0x1DEC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL124 Divider control (for 24.5 divider) 0x1DF0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL125 Divider control (for 24.5 divider) 0x1DF4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL126 Divider control (for 24.5 divider) 0x1DF8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL127 Divider control (for 24.5 divider) 0x1DFC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL128 Divider control (for 24.5 divider) 0x1E00 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL129 Divider control (for 24.5 divider) 0x1E04 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL13 Divider control (for 24.5 divider) 0x1C34 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL130 Divider control (for 24.5 divider) 0x1E08 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL131 Divider control (for 24.5 divider) 0x1E0C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL132 Divider control (for 24.5 divider) 0x1E10 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL133 Divider control (for 24.5 divider) 0x1E14 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL134 Divider control (for 24.5 divider) 0x1E18 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL135 Divider control (for 24.5 divider) 0x1E1C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL136 Divider control (for 24.5 divider) 0x1E20 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL137 Divider control (for 24.5 divider) 0x1E24 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL138 Divider control (for 24.5 divider) 0x1E28 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL139 Divider control (for 24.5 divider) 0x1E2C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL14 Divider control (for 24.5 divider) 0x1C38 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL140 Divider control (for 24.5 divider) 0x1E30 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL141 Divider control (for 24.5 divider) 0x1E34 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL142 Divider control (for 24.5 divider) 0x1E38 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL143 Divider control (for 24.5 divider) 0x1E3C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL144 Divider control (for 24.5 divider) 0x1E40 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL145 Divider control (for 24.5 divider) 0x1E44 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL146 Divider control (for 24.5 divider) 0x1E48 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL147 Divider control (for 24.5 divider) 0x1E4C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL148 Divider control (for 24.5 divider) 0x1E50 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL149 Divider control (for 24.5 divider) 0x1E54 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL15 Divider control (for 24.5 divider) 0x1C3C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL150 Divider control (for 24.5 divider) 0x1E58 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL151 Divider control (for 24.5 divider) 0x1E5C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL152 Divider control (for 24.5 divider) 0x1E60 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL153 Divider control (for 24.5 divider) 0x1E64 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL154 Divider control (for 24.5 divider) 0x1E68 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL155 Divider control (for 24.5 divider) 0x1E6C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL156 Divider control (for 24.5 divider) 0x1E70 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL157 Divider control (for 24.5 divider) 0x1E74 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL158 Divider control (for 24.5 divider) 0x1E78 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL159 Divider control (for 24.5 divider) 0x1E7C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL16 Divider control (for 24.5 divider) 0x1C40 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL160 Divider control (for 24.5 divider) 0x1E80 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL161 Divider control (for 24.5 divider) 0x1E84 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL162 Divider control (for 24.5 divider) 0x1E88 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL163 Divider control (for 24.5 divider) 0x1E8C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL164 Divider control (for 24.5 divider) 0x1E90 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL165 Divider control (for 24.5 divider) 0x1E94 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL166 Divider control (for 24.5 divider) 0x1E98 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL167 Divider control (for 24.5 divider) 0x1E9C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL168 Divider control (for 24.5 divider) 0x1EA0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL169 Divider control (for 24.5 divider) 0x1EA4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL17 Divider control (for 24.5 divider) 0x1C44 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL170 Divider control (for 24.5 divider) 0x1EA8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL171 Divider control (for 24.5 divider) 0x1EAC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL172 Divider control (for 24.5 divider) 0x1EB0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL173 Divider control (for 24.5 divider) 0x1EB4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL174 Divider control (for 24.5 divider) 0x1EB8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL175 Divider control (for 24.5 divider) 0x1EBC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL176 Divider control (for 24.5 divider) 0x1EC0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL177 Divider control (for 24.5 divider) 0x1EC4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL178 Divider control (for 24.5 divider) 0x1EC8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL179 Divider control (for 24.5 divider) 0x1ECC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL18 Divider control (for 24.5 divider) 0x1C48 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL180 Divider control (for 24.5 divider) 0x1ED0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL181 Divider control (for 24.5 divider) 0x1ED4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL182 Divider control (for 24.5 divider) 0x1ED8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL183 Divider control (for 24.5 divider) 0x1EDC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL184 Divider control (for 24.5 divider) 0x1EE0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL185 Divider control (for 24.5 divider) 0x1EE4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL186 Divider control (for 24.5 divider) 0x1EE8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL187 Divider control (for 24.5 divider) 0x1EEC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL188 Divider control (for 24.5 divider) 0x1EF0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL189 Divider control (for 24.5 divider) 0x1EF4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL19 Divider control (for 24.5 divider) 0x1C4C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL190 Divider control (for 24.5 divider) 0x1EF8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL191 Divider control (for 24.5 divider) 0x1EFC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL192 Divider control (for 24.5 divider) 0x1F00 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL193 Divider control (for 24.5 divider) 0x1F04 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL194 Divider control (for 24.5 divider) 0x1F08 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL195 Divider control (for 24.5 divider) 0x1F0C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL196 Divider control (for 24.5 divider) 0x1F10 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL197 Divider control (for 24.5 divider) 0x1F14 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL198 Divider control (for 24.5 divider) 0x1F18 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL199 Divider control (for 24.5 divider) 0x1F1C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL2 Divider control (for 24.5 divider) 0x1C08 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL20 Divider control (for 24.5 divider) 0x1C50 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL200 Divider control (for 24.5 divider) 0x1F20 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL201 Divider control (for 24.5 divider) 0x1F24 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL202 Divider control (for 24.5 divider) 0x1F28 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL203 Divider control (for 24.5 divider) 0x1F2C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL204 Divider control (for 24.5 divider) 0x1F30 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL205 Divider control (for 24.5 divider) 0x1F34 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL206 Divider control (for 24.5 divider) 0x1F38 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL207 Divider control (for 24.5 divider) 0x1F3C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL208 Divider control (for 24.5 divider) 0x1F40 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL209 Divider control (for 24.5 divider) 0x1F44 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL21 Divider control (for 24.5 divider) 0x1C54 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL210 Divider control (for 24.5 divider) 0x1F48 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL211 Divider control (for 24.5 divider) 0x1F4C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL212 Divider control (for 24.5 divider) 0x1F50 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL213 Divider control (for 24.5 divider) 0x1F54 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL214 Divider control (for 24.5 divider) 0x1F58 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL215 Divider control (for 24.5 divider) 0x1F5C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL216 Divider control (for 24.5 divider) 0x1F60 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL217 Divider control (for 24.5 divider) 0x1F64 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL218 Divider control (for 24.5 divider) 0x1F68 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL219 Divider control (for 24.5 divider) 0x1F6C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL22 Divider control (for 24.5 divider) 0x1C58 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL220 Divider control (for 24.5 divider) 0x1F70 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL221 Divider control (for 24.5 divider) 0x1F74 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL222 Divider control (for 24.5 divider) 0x1F78 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL223 Divider control (for 24.5 divider) 0x1F7C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL224 Divider control (for 24.5 divider) 0x1F80 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL225 Divider control (for 24.5 divider) 0x1F84 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL226 Divider control (for 24.5 divider) 0x1F88 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL227 Divider control (for 24.5 divider) 0x1F8C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL228 Divider control (for 24.5 divider) 0x1F90 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL229 Divider control (for 24.5 divider) 0x1F94 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL23 Divider control (for 24.5 divider) 0x1C5C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL230 Divider control (for 24.5 divider) 0x1F98 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL231 Divider control (for 24.5 divider) 0x1F9C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL232 Divider control (for 24.5 divider) 0x1FA0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL233 Divider control (for 24.5 divider) 0x1FA4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL234 Divider control (for 24.5 divider) 0x1FA8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL235 Divider control (for 24.5 divider) 0x1FAC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL236 Divider control (for 24.5 divider) 0x1FB0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL237 Divider control (for 24.5 divider) 0x1FB4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL238 Divider control (for 24.5 divider) 0x1FB8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL239 Divider control (for 24.5 divider) 0x1FBC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL24 Divider control (for 24.5 divider) 0x1C60 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL240 Divider control (for 24.5 divider) 0x1FC0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL241 Divider control (for 24.5 divider) 0x1FC4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL242 Divider control (for 24.5 divider) 0x1FC8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL243 Divider control (for 24.5 divider) 0x1FCC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL244 Divider control (for 24.5 divider) 0x1FD0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL245 Divider control (for 24.5 divider) 0x1FD4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL246 Divider control (for 24.5 divider) 0x1FD8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL247 Divider control (for 24.5 divider) 0x1FDC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL248 Divider control (for 24.5 divider) 0x1FE0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL249 Divider control (for 24.5 divider) 0x1FE4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL25 Divider control (for 24.5 divider) 0x1C64 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL250 Divider control (for 24.5 divider) 0x1FE8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL251 Divider control (for 24.5 divider) 0x1FEC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL252 Divider control (for 24.5 divider) 0x1FF0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL253 Divider control (for 24.5 divider) 0x1FF4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL254 Divider control (for 24.5 divider) 0x1FF8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL26 Divider control (for 24.5 divider) 0x1C68 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL27 Divider control (for 24.5 divider) 0x1C6C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL28 Divider control (for 24.5 divider) 0x1C70 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL29 Divider control (for 24.5 divider) 0x1C74 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL3 Divider control (for 24.5 divider) 0x1C0C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL30 Divider control (for 24.5 divider) 0x1C78 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL31 Divider control (for 24.5 divider) 0x1C7C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL32 Divider control (for 24.5 divider) 0x1C80 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL33 Divider control (for 24.5 divider) 0x1C84 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL34 Divider control (for 24.5 divider) 0x1C88 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL35 Divider control (for 24.5 divider) 0x1C8C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL36 Divider control (for 24.5 divider) 0x1C90 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL37 Divider control (for 24.5 divider) 0x1C94 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL38 Divider control (for 24.5 divider) 0x1C98 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL39 Divider control (for 24.5 divider) 0x1C9C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL4 Divider control (for 24.5 divider) 0x1C10 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL40 Divider control (for 24.5 divider) 0x1CA0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL41 Divider control (for 24.5 divider) 0x1CA4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL42 Divider control (for 24.5 divider) 0x1CA8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL43 Divider control (for 24.5 divider) 0x1CAC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL44 Divider control (for 24.5 divider) 0x1CB0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL45 Divider control (for 24.5 divider) 0x1CB4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL46 Divider control (for 24.5 divider) 0x1CB8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL47 Divider control (for 24.5 divider) 0x1CBC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL48 Divider control (for 24.5 divider) 0x1CC0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL49 Divider control (for 24.5 divider) 0x1CC4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL5 Divider control (for 24.5 divider) 0x1C14 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL50 Divider control (for 24.5 divider) 0x1CC8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL51 Divider control (for 24.5 divider) 0x1CCC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL52 Divider control (for 24.5 divider) 0x1CD0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL53 Divider control (for 24.5 divider) 0x1CD4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL54 Divider control (for 24.5 divider) 0x1CD8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL55 Divider control (for 24.5 divider) 0x1CDC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL56 Divider control (for 24.5 divider) 0x1CE0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL57 Divider control (for 24.5 divider) 0x1CE4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL58 Divider control (for 24.5 divider) 0x1CE8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL59 Divider control (for 24.5 divider) 0x1CEC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL6 Divider control (for 24.5 divider) 0x1C18 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL60 Divider control (for 24.5 divider) 0x1CF0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL61 Divider control (for 24.5 divider) 0x1CF4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL62 Divider control (for 24.5 divider) 0x1CF8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL63 Divider control (for 24.5 divider) 0x1CFC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL64 Divider control (for 24.5 divider) 0x1D00 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL65 Divider control (for 24.5 divider) 0x1D04 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL66 Divider control (for 24.5 divider) 0x1D08 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL67 Divider control (for 24.5 divider) 0x1D0C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL68 Divider control (for 24.5 divider) 0x1D10 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL69 Divider control (for 24.5 divider) 0x1D14 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL7 Divider control (for 24.5 divider) 0x1C1C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL70 Divider control (for 24.5 divider) 0x1D18 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL71 Divider control (for 24.5 divider) 0x1D1C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL72 Divider control (for 24.5 divider) 0x1D20 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL73 Divider control (for 24.5 divider) 0x1D24 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL74 Divider control (for 24.5 divider) 0x1D28 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL75 Divider control (for 24.5 divider) 0x1D2C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL76 Divider control (for 24.5 divider) 0x1D30 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL77 Divider control (for 24.5 divider) 0x1D34 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL78 Divider control (for 24.5 divider) 0x1D38 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL79 Divider control (for 24.5 divider) 0x1D3C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL8 Divider control (for 24.5 divider) 0x1C20 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL80 Divider control (for 24.5 divider) 0x1D40 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL81 Divider control (for 24.5 divider) 0x1D44 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL82 Divider control (for 24.5 divider) 0x1D48 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL83 Divider control (for 24.5 divider) 0x1D4C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL84 Divider control (for 24.5 divider) 0x1D50 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL85 Divider control (for 24.5 divider) 0x1D54 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL86 Divider control (for 24.5 divider) 0x1D58 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL87 Divider control (for 24.5 divider) 0x1D5C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL88 Divider control (for 24.5 divider) 0x1D60 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL89 Divider control (for 24.5 divider) 0x1D64 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL9 Divider control (for 24.5 divider) 0x1C24 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL90 Divider control (for 24.5 divider) 0x1D68 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL91 Divider control (for 24.5 divider) 0x1D6C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL92 Divider control (for 24.5 divider) 0x1D70 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL93 Divider control (for 24.5 divider) 0x1D74 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL94 Divider control (for 24.5 divider) 0x1D78 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL95 Divider control (for 24.5 divider) 0x1D7C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL96 Divider control (for 24.5 divider) 0x1D80 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL97 Divider control (for 24.5 divider) 0x1D84 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL98 Divider control (for 24.5 divider) 0x1D88 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL99 Divider control (for 24.5 divider) 0x1D8C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_8_CTL0 Divider control (for 8.0 divider) 0x1000 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL1 Divider control (for 8.0 divider) 0x1004 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL10 Divider control (for 8.0 divider) 0x1028 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL100 Divider control (for 8.0 divider) 0x1190 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL101 Divider control (for 8.0 divider) 0x1194 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL102 Divider control (for 8.0 divider) 0x1198 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL103 Divider control (for 8.0 divider) 0x119C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL104 Divider control (for 8.0 divider) 0x11A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL105 Divider control (for 8.0 divider) 0x11A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL106 Divider control (for 8.0 divider) 0x11A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL107 Divider control (for 8.0 divider) 0x11AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL108 Divider control (for 8.0 divider) 0x11B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL109 Divider control (for 8.0 divider) 0x11B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL11 Divider control (for 8.0 divider) 0x102C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL110 Divider control (for 8.0 divider) 0x11B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL111 Divider control (for 8.0 divider) 0x11BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL112 Divider control (for 8.0 divider) 0x11C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL113 Divider control (for 8.0 divider) 0x11C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL114 Divider control (for 8.0 divider) 0x11C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL115 Divider control (for 8.0 divider) 0x11CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL116 Divider control (for 8.0 divider) 0x11D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL117 Divider control (for 8.0 divider) 0x11D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL118 Divider control (for 8.0 divider) 0x11D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL119 Divider control (for 8.0 divider) 0x11DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL12 Divider control (for 8.0 divider) 0x1030 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL120 Divider control (for 8.0 divider) 0x11E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL121 Divider control (for 8.0 divider) 0x11E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL122 Divider control (for 8.0 divider) 0x11E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL123 Divider control (for 8.0 divider) 0x11EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL124 Divider control (for 8.0 divider) 0x11F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL125 Divider control (for 8.0 divider) 0x11F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL126 Divider control (for 8.0 divider) 0x11F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL127 Divider control (for 8.0 divider) 0x11FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL128 Divider control (for 8.0 divider) 0x1200 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL129 Divider control (for 8.0 divider) 0x1204 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL13 Divider control (for 8.0 divider) 0x1034 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL130 Divider control (for 8.0 divider) 0x1208 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL131 Divider control (for 8.0 divider) 0x120C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL132 Divider control (for 8.0 divider) 0x1210 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL133 Divider control (for 8.0 divider) 0x1214 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL134 Divider control (for 8.0 divider) 0x1218 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL135 Divider control (for 8.0 divider) 0x121C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL136 Divider control (for 8.0 divider) 0x1220 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL137 Divider control (for 8.0 divider) 0x1224 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL138 Divider control (for 8.0 divider) 0x1228 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL139 Divider control (for 8.0 divider) 0x122C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL14 Divider control (for 8.0 divider) 0x1038 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL140 Divider control (for 8.0 divider) 0x1230 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL141 Divider control (for 8.0 divider) 0x1234 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL142 Divider control (for 8.0 divider) 0x1238 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL143 Divider control (for 8.0 divider) 0x123C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL144 Divider control (for 8.0 divider) 0x1240 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL145 Divider control (for 8.0 divider) 0x1244 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL146 Divider control (for 8.0 divider) 0x1248 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL147 Divider control (for 8.0 divider) 0x124C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL148 Divider control (for 8.0 divider) 0x1250 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL149 Divider control (for 8.0 divider) 0x1254 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL15 Divider control (for 8.0 divider) 0x103C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL150 Divider control (for 8.0 divider) 0x1258 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL151 Divider control (for 8.0 divider) 0x125C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL152 Divider control (for 8.0 divider) 0x1260 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL153 Divider control (for 8.0 divider) 0x1264 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL154 Divider control (for 8.0 divider) 0x1268 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL155 Divider control (for 8.0 divider) 0x126C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL156 Divider control (for 8.0 divider) 0x1270 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL157 Divider control (for 8.0 divider) 0x1274 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL158 Divider control (for 8.0 divider) 0x1278 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL159 Divider control (for 8.0 divider) 0x127C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL16 Divider control (for 8.0 divider) 0x1040 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL160 Divider control (for 8.0 divider) 0x1280 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL161 Divider control (for 8.0 divider) 0x1284 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL162 Divider control (for 8.0 divider) 0x1288 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL163 Divider control (for 8.0 divider) 0x128C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL164 Divider control (for 8.0 divider) 0x1290 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL165 Divider control (for 8.0 divider) 0x1294 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL166 Divider control (for 8.0 divider) 0x1298 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL167 Divider control (for 8.0 divider) 0x129C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL168 Divider control (for 8.0 divider) 0x12A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL169 Divider control (for 8.0 divider) 0x12A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL17 Divider control (for 8.0 divider) 0x1044 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL170 Divider control (for 8.0 divider) 0x12A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL171 Divider control (for 8.0 divider) 0x12AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL172 Divider control (for 8.0 divider) 0x12B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL173 Divider control (for 8.0 divider) 0x12B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL174 Divider control (for 8.0 divider) 0x12B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL175 Divider control (for 8.0 divider) 0x12BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL176 Divider control (for 8.0 divider) 0x12C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL177 Divider control (for 8.0 divider) 0x12C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL178 Divider control (for 8.0 divider) 0x12C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL179 Divider control (for 8.0 divider) 0x12CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL18 Divider control (for 8.0 divider) 0x1048 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL180 Divider control (for 8.0 divider) 0x12D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL181 Divider control (for 8.0 divider) 0x12D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL182 Divider control (for 8.0 divider) 0x12D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL183 Divider control (for 8.0 divider) 0x12DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL184 Divider control (for 8.0 divider) 0x12E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL185 Divider control (for 8.0 divider) 0x12E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL186 Divider control (for 8.0 divider) 0x12E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL187 Divider control (for 8.0 divider) 0x12EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL188 Divider control (for 8.0 divider) 0x12F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL189 Divider control (for 8.0 divider) 0x12F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL19 Divider control (for 8.0 divider) 0x104C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL190 Divider control (for 8.0 divider) 0x12F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL191 Divider control (for 8.0 divider) 0x12FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL192 Divider control (for 8.0 divider) 0x1300 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL193 Divider control (for 8.0 divider) 0x1304 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL194 Divider control (for 8.0 divider) 0x1308 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL195 Divider control (for 8.0 divider) 0x130C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL196 Divider control (for 8.0 divider) 0x1310 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL197 Divider control (for 8.0 divider) 0x1314 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL198 Divider control (for 8.0 divider) 0x1318 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL199 Divider control (for 8.0 divider) 0x131C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL2 Divider control (for 8.0 divider) 0x1008 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL20 Divider control (for 8.0 divider) 0x1050 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL200 Divider control (for 8.0 divider) 0x1320 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL201 Divider control (for 8.0 divider) 0x1324 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL202 Divider control (for 8.0 divider) 0x1328 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL203 Divider control (for 8.0 divider) 0x132C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL204 Divider control (for 8.0 divider) 0x1330 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL205 Divider control (for 8.0 divider) 0x1334 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL206 Divider control (for 8.0 divider) 0x1338 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL207 Divider control (for 8.0 divider) 0x133C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL208 Divider control (for 8.0 divider) 0x1340 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL209 Divider control (for 8.0 divider) 0x1344 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL21 Divider control (for 8.0 divider) 0x1054 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL210 Divider control (for 8.0 divider) 0x1348 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL211 Divider control (for 8.0 divider) 0x134C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL212 Divider control (for 8.0 divider) 0x1350 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL213 Divider control (for 8.0 divider) 0x1354 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL214 Divider control (for 8.0 divider) 0x1358 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL215 Divider control (for 8.0 divider) 0x135C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL216 Divider control (for 8.0 divider) 0x1360 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL217 Divider control (for 8.0 divider) 0x1364 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL218 Divider control (for 8.0 divider) 0x1368 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL219 Divider control (for 8.0 divider) 0x136C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL22 Divider control (for 8.0 divider) 0x1058 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL220 Divider control (for 8.0 divider) 0x1370 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL221 Divider control (for 8.0 divider) 0x1374 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL222 Divider control (for 8.0 divider) 0x1378 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL223 Divider control (for 8.0 divider) 0x137C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL224 Divider control (for 8.0 divider) 0x1380 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL225 Divider control (for 8.0 divider) 0x1384 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL226 Divider control (for 8.0 divider) 0x1388 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL227 Divider control (for 8.0 divider) 0x138C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL228 Divider control (for 8.0 divider) 0x1390 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL229 Divider control (for 8.0 divider) 0x1394 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL23 Divider control (for 8.0 divider) 0x105C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL230 Divider control (for 8.0 divider) 0x1398 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL231 Divider control (for 8.0 divider) 0x139C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL232 Divider control (for 8.0 divider) 0x13A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL233 Divider control (for 8.0 divider) 0x13A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL234 Divider control (for 8.0 divider) 0x13A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL235 Divider control (for 8.0 divider) 0x13AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL236 Divider control (for 8.0 divider) 0x13B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL237 Divider control (for 8.0 divider) 0x13B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL238 Divider control (for 8.0 divider) 0x13B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL239 Divider control (for 8.0 divider) 0x13BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL24 Divider control (for 8.0 divider) 0x1060 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL240 Divider control (for 8.0 divider) 0x13C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL241 Divider control (for 8.0 divider) 0x13C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL242 Divider control (for 8.0 divider) 0x13C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL243 Divider control (for 8.0 divider) 0x13CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL244 Divider control (for 8.0 divider) 0x13D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL245 Divider control (for 8.0 divider) 0x13D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL246 Divider control (for 8.0 divider) 0x13D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL247 Divider control (for 8.0 divider) 0x13DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL248 Divider control (for 8.0 divider) 0x13E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL249 Divider control (for 8.0 divider) 0x13E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL25 Divider control (for 8.0 divider) 0x1064 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL250 Divider control (for 8.0 divider) 0x13E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL251 Divider control (for 8.0 divider) 0x13EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL252 Divider control (for 8.0 divider) 0x13F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL253 Divider control (for 8.0 divider) 0x13F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL254 Divider control (for 8.0 divider) 0x13F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL255 Divider control (for 8.0 divider) 0x13FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL26 Divider control (for 8.0 divider) 0x1068 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL27 Divider control (for 8.0 divider) 0x106C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL28 Divider control (for 8.0 divider) 0x1070 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL29 Divider control (for 8.0 divider) 0x1074 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL3 Divider control (for 8.0 divider) 0x100C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL30 Divider control (for 8.0 divider) 0x1078 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL31 Divider control (for 8.0 divider) 0x107C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL32 Divider control (for 8.0 divider) 0x1080 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL33 Divider control (for 8.0 divider) 0x1084 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL34 Divider control (for 8.0 divider) 0x1088 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL35 Divider control (for 8.0 divider) 0x108C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL36 Divider control (for 8.0 divider) 0x1090 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL37 Divider control (for 8.0 divider) 0x1094 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL38 Divider control (for 8.0 divider) 0x1098 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL39 Divider control (for 8.0 divider) 0x109C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL4 Divider control (for 8.0 divider) 0x1010 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL40 Divider control (for 8.0 divider) 0x10A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL41 Divider control (for 8.0 divider) 0x10A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL42 Divider control (for 8.0 divider) 0x10A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL43 Divider control (for 8.0 divider) 0x10AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL44 Divider control (for 8.0 divider) 0x10B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL45 Divider control (for 8.0 divider) 0x10B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL46 Divider control (for 8.0 divider) 0x10B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL47 Divider control (for 8.0 divider) 0x10BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL48 Divider control (for 8.0 divider) 0x10C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL49 Divider control (for 8.0 divider) 0x10C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL5 Divider control (for 8.0 divider) 0x1014 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL50 Divider control (for 8.0 divider) 0x10C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL51 Divider control (for 8.0 divider) 0x10CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL52 Divider control (for 8.0 divider) 0x10D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL53 Divider control (for 8.0 divider) 0x10D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL54 Divider control (for 8.0 divider) 0x10D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL55 Divider control (for 8.0 divider) 0x10DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL56 Divider control (for 8.0 divider) 0x10E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL57 Divider control (for 8.0 divider) 0x10E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL58 Divider control (for 8.0 divider) 0x10E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL59 Divider control (for 8.0 divider) 0x10EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL6 Divider control (for 8.0 divider) 0x1018 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL60 Divider control (for 8.0 divider) 0x10F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL61 Divider control (for 8.0 divider) 0x10F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL62 Divider control (for 8.0 divider) 0x10F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL63 Divider control (for 8.0 divider) 0x10FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL64 Divider control (for 8.0 divider) 0x1100 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL65 Divider control (for 8.0 divider) 0x1104 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL66 Divider control (for 8.0 divider) 0x1108 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL67 Divider control (for 8.0 divider) 0x110C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL68 Divider control (for 8.0 divider) 0x1110 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL69 Divider control (for 8.0 divider) 0x1114 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL7 Divider control (for 8.0 divider) 0x101C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL70 Divider control (for 8.0 divider) 0x1118 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL71 Divider control (for 8.0 divider) 0x111C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL72 Divider control (for 8.0 divider) 0x1120 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL73 Divider control (for 8.0 divider) 0x1124 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL74 Divider control (for 8.0 divider) 0x1128 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL75 Divider control (for 8.0 divider) 0x112C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL76 Divider control (for 8.0 divider) 0x1130 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL77 Divider control (for 8.0 divider) 0x1134 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL78 Divider control (for 8.0 divider) 0x1138 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL79 Divider control (for 8.0 divider) 0x113C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL8 Divider control (for 8.0 divider) 0x1020 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL80 Divider control (for 8.0 divider) 0x1140 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL81 Divider control (for 8.0 divider) 0x1144 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL82 Divider control (for 8.0 divider) 0x1148 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL83 Divider control (for 8.0 divider) 0x114C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL84 Divider control (for 8.0 divider) 0x1150 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL85 Divider control (for 8.0 divider) 0x1154 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL86 Divider control (for 8.0 divider) 0x1158 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL87 Divider control (for 8.0 divider) 0x115C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL88 Divider control (for 8.0 divider) 0x1160 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL89 Divider control (for 8.0 divider) 0x1164 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL9 Divider control (for 8.0 divider) 0x1024 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL90 Divider control (for 8.0 divider) 0x1168 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL91 Divider control (for 8.0 divider) 0x116C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL92 Divider control (for 8.0 divider) 0x1170 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL93 Divider control (for 8.0 divider) 0x1174 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL94 Divider control (for 8.0 divider) 0x1178 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL95 Divider control (for 8.0 divider) 0x117C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL96 Divider control (for 8.0 divider) 0x1180 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL97 Divider control (for 8.0 divider) 0x1184 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL98 Divider control (for 8.0 divider) 0x1188 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL99 Divider control (for 8.0 divider) 0x118C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_CMD Divider command 0x400 32 read-write n 0x0 0x0 DISABLE Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. 30 31 read-write DIV_SEL (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. 0 8 read-write ENABLE Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. 31 32 read-write PA_DIV_SEL (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. 16 24 read-write PA_TYPE_SEL Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 24 26 read-write TYPE_SEL Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 8 10 read-write ECC_CTL ECC control 0x2000 32 read-write n 0x0 0x0 ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. 16 17 read-write ECC_INJ_EN Enable error injection for PERI protection structure SRAM. When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. 18 19 read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. 24 32 read-write WORD_ADDR Specifies the word address where the parity is injected. - On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. 0 11 read-write SL_CTL Slave control 0x10 32 read-write n 0x0 0x0 DISABLED_0 Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. 16 17 read-write DISABLED_1 N/A 17 18 read-write DISABLED_10 N/A 26 27 read-write DISABLED_11 N/A 27 28 read-write DISABLED_12 N/A 28 29 read-write DISABLED_13 N/A 29 30 read-write DISABLED_14 N/A 30 31 read-write DISABLED_15 N/A 31 32 read-write DISABLED_2 N/A 18 19 read-write DISABLED_3 N/A 19 20 read-write DISABLED_4 N/A 20 21 read-write DISABLED_5 N/A 21 22 read-write DISABLED_6 N/A 22 23 read-write DISABLED_7 N/A 23 24 read-write DISABLED_8 N/A 24 25 read-write DISABLED_9 N/A 25 26 read-write ENABLED_0 Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. 0 1 read-write ENABLED_1 Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. 1 2 read-write ENABLED_10 N/A 10 11 read-write ENABLED_11 N/A 11 12 read-write ENABLED_12 N/A 12 13 read-write ENABLED_13 N/A 13 14 read-write ENABLED_14 N/A 14 15 read-write ENABLED_15 N/A 15 16 read-write ENABLED_2 N/A 2 3 read-write ENABLED_3 N/A 3 4 read-write ENABLED_4 N/A 4 5 read-write ENABLED_5 N/A 5 6 read-write ENABLED_6 N/A 6 7 read-write ENABLED_7 N/A 7 8 read-write ENABLED_8 N/A 8 9 read-write ENABLED_9 N/A 9 10 read-write TIMEOUT_CTL Timeout control 0x200 32 read-write n 0x0 0x0 TIMEOUT This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. 0 16 read-write TR_CMD Trigger command 0x220 32 read-write n 0x0 0x0 ACTIVATE SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. Note: when ACTIVATE is '1', SW should not modify the other register fields. 31 32 read-write GROUP_SEL Specifies the trigger group: '0'-'15': trigger multiplexer groups. '16'-'31': trigger 1-to-1 groups. 8 13 read-write OUT_SEL Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. Note: this field is not used for trigger 1-to-1 groups. 30 31 read-write TR_EDGE Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. '1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. 29 30 read-write TR_SEL Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. 0 8 read-write TR_CTL0 Trigger control register 0x0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL1 Trigger control register 0x4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL10 Trigger control register 0x28 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL100 Trigger control register 0x190 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL101 Trigger control register 0x194 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL102 Trigger control register 0x198 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL103 Trigger control register 0x19C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL104 Trigger control register 0x1A0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL105 Trigger control register 0x1A4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL106 Trigger control register 0x1A8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL107 Trigger control register 0x1AC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL108 Trigger control register 0x1B0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL109 Trigger control register 0x1B4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL11 Trigger control register 0x2C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL110 Trigger control register 0x1B8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL111 Trigger control register 0x1BC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL112 Trigger control register 0x1C0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL113 Trigger control register 0x1C4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL114 Trigger control register 0x1C8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL115 Trigger control register 0x1CC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL116 Trigger control register 0x1D0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL117 Trigger control register 0x1D4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL118 Trigger control register 0x1D8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL119 Trigger control register 0x1DC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL12 Trigger control register 0x30 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL120 Trigger control register 0x1E0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL121 Trigger control register 0x1E4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL122 Trigger control register 0x1E8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL123 Trigger control register 0x1EC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL124 Trigger control register 0x1F0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL125 Trigger control register 0x1F4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL126 Trigger control register 0x1F8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL127 Trigger control register 0x1FC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL128 Trigger control register 0x200 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL129 Trigger control register 0x204 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL13 Trigger control register 0x34 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL130 Trigger control register 0x208 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL131 Trigger control register 0x20C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL132 Trigger control register 0x210 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL133 Trigger control register 0x214 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL134 Trigger control register 0x218 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL135 Trigger control register 0x21C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL136 Trigger control register 0x220 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL137 Trigger control register 0x224 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL138 Trigger control register 0x228 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL139 Trigger control register 0x22C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL14 Trigger control register 0x38 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL140 Trigger control register 0x230 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL141 Trigger control register 0x234 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL142 Trigger control register 0x238 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL143 Trigger control register 0x23C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL144 Trigger control register 0x240 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL145 Trigger control register 0x244 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL146 Trigger control register 0x248 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL147 Trigger control register 0x24C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL148 Trigger control register 0x250 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL149 Trigger control register 0x254 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL15 Trigger control register 0x3C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL150 Trigger control register 0x258 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL151 Trigger control register 0x25C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL152 Trigger control register 0x260 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL153 Trigger control register 0x264 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL154 Trigger control register 0x268 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL155 Trigger control register 0x26C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL156 Trigger control register 0x270 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL157 Trigger control register 0x274 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL158 Trigger control register 0x278 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL159 Trigger control register 0x27C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL16 Trigger control register 0x40 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL160 Trigger control register 0x280 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL161 Trigger control register 0x284 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL162 Trigger control register 0x288 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL163 Trigger control register 0x28C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL164 Trigger control register 0x290 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL165 Trigger control register 0x294 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL166 Trigger control register 0x298 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL167 Trigger control register 0x29C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL168 Trigger control register 0x2A0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL169 Trigger control register 0x2A4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL17 Trigger control register 0x44 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL170 Trigger control register 0x2A8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL171 Trigger control register 0x2AC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL172 Trigger control register 0x2B0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL173 Trigger control register 0x2B4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL174 Trigger control register 0x2B8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL175 Trigger control register 0x2BC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL176 Trigger control register 0x2C0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL177 Trigger control register 0x2C4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL178 Trigger control register 0x2C8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL179 Trigger control register 0x2CC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL18 Trigger control register 0x48 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL180 Trigger control register 0x2D0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL181 Trigger control register 0x2D4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL182 Trigger control register 0x2D8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL183 Trigger control register 0x2DC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL184 Trigger control register 0x2E0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL185 Trigger control register 0x2E4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL186 Trigger control register 0x2E8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL187 Trigger control register 0x2EC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL188 Trigger control register 0x2F0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL189 Trigger control register 0x2F4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL19 Trigger control register 0x4C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL190 Trigger control register 0x2F8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL191 Trigger control register 0x2FC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL192 Trigger control register 0x300 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL193 Trigger control register 0x304 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL194 Trigger control register 0x308 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL195 Trigger control register 0x30C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL196 Trigger control register 0x310 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL197 Trigger control register 0x314 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL198 Trigger control register 0x318 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL199 Trigger control register 0x31C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL2 Trigger control register 0x8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL20 Trigger control register 0x50 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL200 Trigger control register 0x320 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL201 Trigger control register 0x324 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL202 Trigger control register 0x328 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL203 Trigger control register 0x32C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL204 Trigger control register 0x330 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL205 Trigger control register 0x334 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL206 Trigger control register 0x338 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL207 Trigger control register 0x33C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL208 Trigger control register 0x340 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL209 Trigger control register 0x344 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL21 Trigger control register 0x54 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL210 Trigger control register 0x348 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL211 Trigger control register 0x34C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL212 Trigger control register 0x350 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL213 Trigger control register 0x354 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL214 Trigger control register 0x358 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL215 Trigger control register 0x35C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL216 Trigger control register 0x360 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL217 Trigger control register 0x364 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL218 Trigger control register 0x368 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL219 Trigger control register 0x36C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL22 Trigger control register 0x58 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL220 Trigger control register 0x370 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL221 Trigger control register 0x374 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL222 Trigger control register 0x378 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL223 Trigger control register 0x37C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL224 Trigger control register 0x380 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL225 Trigger control register 0x384 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL226 Trigger control register 0x388 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL227 Trigger control register 0x38C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL228 Trigger control register 0x390 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL229 Trigger control register 0x394 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL23 Trigger control register 0x5C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL230 Trigger control register 0x398 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL231 Trigger control register 0x39C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL232 Trigger control register 0x3A0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL233 Trigger control register 0x3A4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL234 Trigger control register 0x3A8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL235 Trigger control register 0x3AC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL236 Trigger control register 0x3B0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL237 Trigger control register 0x3B4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL238 Trigger control register 0x3B8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL239 Trigger control register 0x3BC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL24 Trigger control register 0x60 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL240 Trigger control register 0x3C0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL241 Trigger control register 0x3C4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL242 Trigger control register 0x3C8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL243 Trigger control register 0x3CC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL244 Trigger control register 0x3D0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL245 Trigger control register 0x3D4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL246 Trigger control register 0x3D8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL247 Trigger control register 0x3DC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL248 Trigger control register 0x3E0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL249 Trigger control register 0x3E4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL25 Trigger control register 0x64 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL250 Trigger control register 0x3E8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL251 Trigger control register 0x3EC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL252 Trigger control register 0x3F0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL253 Trigger control register 0x3F4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL254 Trigger control register 0x3F8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL255 Trigger control register 0x3FC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL26 Trigger control register 0x68 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL27 Trigger control register 0x6C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL28 Trigger control register 0x70 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL29 Trigger control register 0x74 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL3 Trigger control register 0xC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL30 Trigger control register 0x78 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL31 Trigger control register 0x7C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL32 Trigger control register 0x80 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL33 Trigger control register 0x84 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL34 Trigger control register 0x88 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL35 Trigger control register 0x8C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL36 Trigger control register 0x90 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL37 Trigger control register 0x94 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL38 Trigger control register 0x98 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL39 Trigger control register 0x9C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL4 Trigger control register 0x10 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL40 Trigger control register 0xA0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL41 Trigger control register 0xA4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL42 Trigger control register 0xA8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL43 Trigger control register 0xAC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL44 Trigger control register 0xB0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL45 Trigger control register 0xB4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL46 Trigger control register 0xB8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL47 Trigger control register 0xBC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL48 Trigger control register 0xC0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL49 Trigger control register 0xC4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL5 Trigger control register 0x14 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL50 Trigger control register 0xC8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL51 Trigger control register 0xCC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL52 Trigger control register 0xD0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL53 Trigger control register 0xD4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL54 Trigger control register 0xD8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL55 Trigger control register 0xDC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL56 Trigger control register 0xE0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL57 Trigger control register 0xE4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL58 Trigger control register 0xE8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL59 Trigger control register 0xEC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL6 Trigger control register 0x18 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL60 Trigger control register 0xF0 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL61 Trigger control register 0xF4 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL62 Trigger control register 0xF8 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL63 Trigger control register 0xFC 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL64 Trigger control register 0x100 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL65 Trigger control register 0x104 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL66 Trigger control register 0x108 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL67 Trigger control register 0x10C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL68 Trigger control register 0x110 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL69 Trigger control register 0x114 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL7 Trigger control register 0x1C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL70 Trigger control register 0x118 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL71 Trigger control register 0x11C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL72 Trigger control register 0x120 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL73 Trigger control register 0x124 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL74 Trigger control register 0x128 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL75 Trigger control register 0x12C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL76 Trigger control register 0x130 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL77 Trigger control register 0x134 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL78 Trigger control register 0x138 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL79 Trigger control register 0x13C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL8 Trigger control register 0x20 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL80 Trigger control register 0x140 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL81 Trigger control register 0x144 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL82 Trigger control register 0x148 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL83 Trigger control register 0x14C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL84 Trigger control register 0x150 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL85 Trigger control register 0x154 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL86 Trigger control register 0x158 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL87 Trigger control register 0x15C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL88 Trigger control register 0x160 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL89 Trigger control register 0x164 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL9 Trigger control register 0x24 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL90 Trigger control register 0x168 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL91 Trigger control register 0x16C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL92 Trigger control register 0x170 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL93 Trigger control register 0x174 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL94 Trigger control register 0x178 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL95 Trigger control register 0x17C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL96 Trigger control register 0x180 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL97 Trigger control register 0x184 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL98 Trigger control register 0x188 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write TR_CTL99 Trigger control register 0x18C 32 read-write n 0x0 0x0 DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. 12 13 read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. 9 10 read-write TR_INV Specifies if the output trigger is inverted. 8 9 read-write TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. 0 1 read-write PERI_MS Peripheral interconnect, master interface PERI_MS 0x0 0x0 0x10000 registers n MS_ADDR Master region, base address 0x20 32 read-only n 0x0 0x0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. 6 32 read-only MS_ATT0 Master attributes 0 0x30 32 read-write n 0x0 0x0 PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). 4 5 read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). 2 3 read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). 3 4 read-only PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). 0 1 read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). 1 2 read-only PC1_NS Protection context 1, non-secure. 12 13 read-write PC1_PR Protection context 1, privileged read enable. 10 11 read-only PC1_PW Protection context 1, privileged write enable. 11 12 read-write PC1_UR Protection context 1, user read enable. 8 9 read-only PC1_UW Protection context 1, user write enable. 9 10 read-write PC2_NS Protection context 2, non-secure. 20 21 read-write PC2_PR Protection context 2, privileged read enable. 18 19 read-only PC2_PW Protection context 2, privileged write enable. 19 20 read-write PC2_UR Protection context 2, user read enable. 16 17 read-only PC2_UW Protection context 2, user write enable. 17 18 read-write PC3_NS Protection context 3, non-secure. 28 29 read-write PC3_PR Protection context 3, privileged read enable. 26 27 read-only PC3_PW Protection context 3, privileged write enable. 27 28 read-write PC3_UR Protection context 3, user read enable. 24 25 read-only PC3_UW Protection context 3, user write enable. 25 26 read-write MS_ATT1 Master attributes 1 0x34 32 read-write n 0x0 0x0 PC4_NS Protection context 4, non-secure. 4 5 read-write PC4_PR Protection context 4, privileged read enable. 2 3 read-only PC4_PW Protection context 4, privileged write enable. 3 4 read-write PC4_UR Protection context 4, user read enable. 0 1 read-only PC4_UW Protection context 4, user write enable. 1 2 read-write PC5_NS Protection context 5, non-secure. 12 13 read-write PC5_PR Protection context 5, privileged read enable. 10 11 read-only PC5_PW Protection context 5, privileged write enable. 11 12 read-write PC5_UR Protection context 5, user read enable. 8 9 read-only PC5_UW Protection context 5, user write enable. 9 10 read-write PC6_NS Protection context 6, non-secure. 20 21 read-write PC6_PR Protection context 6, privileged read enable. 18 19 read-only PC6_PW Protection context 6, privileged write enable. 19 20 read-write PC6_UR Protection context 6, user read enable. 16 17 read-only PC6_UW Protection context 6, user write enable. 17 18 read-write PC7_NS Protection context 7, non-secure. 28 29 read-write PC7_PR Protection context 7, privileged read enable. 26 27 read-only PC7_PW Protection context 7, privileged write enable. 27 28 read-write PC7_UR Protection context 7, user read enable. 24 25 read-only PC7_UW Protection context 7, user write enable. 25 26 read-write MS_ATT2 Master attributes 2 0x38 32 read-write n 0x0 0x0 PC10_NS Protection context 10, non-secure. 20 21 read-write PC10_PR Protection context 10, privileged read enable. 18 19 read-only PC10_PW Protection context 10, privileged write enable. 19 20 read-write PC10_UR Protection context 10, user read enable. 16 17 read-only PC10_UW Protection context 10, user write enable. 17 18 read-write PC11_NS Protection context 11, non-secure. 28 29 read-write PC11_PR Protection context 11, privileged read enable. 26 27 read-only PC11_PW Protection context 11, privileged write enable. 27 28 read-write PC11_UR Protection context 11, user read enable. 24 25 read-only PC11_UW Protection context 11, user write enable. 25 26 read-write PC8_NS Protection context 8, non-secure. 4 5 read-write PC8_PR Protection context 8, privileged read enable. 2 3 read-only PC8_PW Protection context 8, privileged write enable. 3 4 read-write PC8_UR Protection context 8, user read enable. 0 1 read-only PC8_UW Protection context 8, user write enable. 1 2 read-write PC9_NS Protection context 9, non-secure. 12 13 read-write PC9_PR Protection context 9, privileged read enable. 10 11 read-only PC9_PW Protection context 9, privileged write enable. 11 12 read-write PC9_UR Protection context 9, user read enable. 8 9 read-only PC9_UW Protection context 9, user write enable. 9 10 read-write MS_ATT3 Master attributes 3 0x3C 32 read-write n 0x0 0x0 PC12_NS Protection context 12, non-secure. 4 5 read-write PC12_PR Protection context 12, privileged read enable. 2 3 read-only PC12_PW Protection context 12, privileged write enable. 3 4 read-write PC12_UR Protection context 12, user read enable. 0 1 read-only PC12_UW Protection context 12, user write enable. 1 2 read-write PC13_NS Protection context 13, non-secure. 12 13 read-write PC13_PR Protection context 13, privileged read enable. 10 11 read-only PC13_PW Protection context 13, privileged write enable. 11 12 read-write PC13_UR Protection context 13, user read enable. 8 9 read-only PC13_UW Protection context 13, user write enable. 9 10 read-write PC14_NS Protection context 14, non-secure. 20 21 read-write PC14_PR Protection context 14, privileged read enable. 18 19 read-only PC14_PW Protection context 14, privileged write enable. 19 20 read-write PC14_UR Protection context 14, user read enable. 16 17 read-only PC14_UW Protection context 14, user write enable. 17 18 read-write PC15_NS Protection context 15, non-secure. 28 29 read-write PC15_PR Protection context 15, privileged read enable. 26 27 read-only PC15_PW Protection context 15, privileged write enable. 27 28 read-write PC15_UR Protection context 15, user read enable. 24 25 read-only PC15_UW Protection context 15, user write enable. 25 26 read-write MS_SIZE Master region, size 0x24 32 read-only n 0x0 0x0 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. 24 29 read-only VALID Master region enable: '1': Enabled. 31 32 read-only SL_ADDR Slave region, base address 0x0 32 read-write n 0x0 0x0 ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. 2 32 read-write SL_ATT0 Slave attributes 0 0x10 32 read-write n 0x0 0x0 PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). 4 5 read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). 2 3 read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). 3 4 read-only PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). 0 1 read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). 1 2 read-only PC1_NS Protection context 1, non-secure. 12 13 read-write PC1_PR Protection context 1, privileged read enable. 10 11 read-write PC1_PW Protection context 1, privileged write enable. 11 12 read-write PC1_UR Protection context 1, user read enable. 8 9 read-write PC1_UW Protection context 1, user write enable. 9 10 read-write PC2_NS Protection context 2, non-secure. 20 21 read-write PC2_PR Protection context 2, privileged read enable. 18 19 read-write PC2_PW Protection context 2, privileged write enable. 19 20 read-write PC2_UR Protection context 2, user read enable. 16 17 read-write PC2_UW Protection context 2, user write enable. 17 18 read-write PC3_NS Protection context 3, non-secure. 28 29 read-write PC3_PR Protection context 3, privileged read enable. 26 27 read-write PC3_PW Protection context 3, privileged write enable. 27 28 read-write PC3_UR Protection context 3, user read enable. 24 25 read-write PC3_UW Protection context 3, user write enable. 25 26 read-write SL_ATT1 Slave attributes 1 0x14 32 read-write n 0x0 0x0 PC4_NS Protection context 4, non-secure. 4 5 read-write PC4_PR Protection context 4, privileged read enable. 2 3 read-write PC4_PW Protection context 4, privileged write enable. 3 4 read-write PC4_UR Protection context 4, user read enable. 0 1 read-write PC4_UW Protection context 4, user write enable. 1 2 read-write PC5_NS Protection context 5, non-secure. 12 13 read-write PC5_PR Protection context 5, privileged read enable. 10 11 read-write PC5_PW Protection context 5, privileged write enable. 11 12 read-write PC5_UR Protection context 5, user read enable. 8 9 read-write PC5_UW Protection context 5, user write enable. 9 10 read-write PC6_NS Protection context 6, non-secure. 20 21 read-write PC6_PR Protection context 6, privileged read enable. 18 19 read-write PC6_PW Protection context 6, privileged write enable. 19 20 read-write PC6_UR Protection context 6, user read enable. 16 17 read-write PC6_UW Protection context 6, user write enable. 17 18 read-write PC7_NS Protection context 7, non-secure. 28 29 read-write PC7_PR Protection context 7, privileged read enable. 26 27 read-write PC7_PW Protection context 7, privileged write enable. 27 28 read-write PC7_UR Protection context 7, user read enable. 24 25 read-write PC7_UW Protection context 7, user write enable. 25 26 read-write SL_ATT2 Slave attributes 2 0x18 32 read-write n 0x0 0x0 PC10_NS Protection context 10, non-secure. 20 21 read-write PC10_PR Protection context 10, privileged read enable. 18 19 read-write PC10_PW Protection context 10, privileged write enable. 19 20 read-write PC10_UR Protection context 10, user read enable. 16 17 read-write PC10_UW Protection context 10, user write enable. 17 18 read-write PC11_NS Protection context 11, non-secure. 28 29 read-write PC11_PR Protection context 11, privileged read enable. 26 27 read-write PC11_PW Protection context 11, privileged write enable. 27 28 read-write PC11_UR Protection context 11, user read enable. 24 25 read-write PC11_UW Protection context 11, user write enable. 25 26 read-write PC8_NS Protection context 8, non-secure. 4 5 read-write PC8_PR Protection context 8, privileged read enable. 2 3 read-write PC8_PW Protection context 8, privileged write enable. 3 4 read-write PC8_UR Protection context 8, user read enable. 0 1 read-write PC8_UW Protection context 8, user write enable. 1 2 read-write PC9_NS Protection context 9, non-secure. 12 13 read-write PC9_PR Protection context 9, privileged read enable. 10 11 read-write PC9_PW Protection context 9, privileged write enable. 11 12 read-write PC9_UR Protection context 9, user read enable. 8 9 read-write PC9_UW Protection context 9, user write enable. 9 10 read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write n 0x0 0x0 PC12_NS Protection context 12, non-secure. 4 5 read-write PC12_PR Protection context 12, privileged read enable. 2 3 read-write PC12_PW Protection context 12, privileged write enable. 3 4 read-write PC12_UR Protection context 12, user read enable. 0 1 read-write PC12_UW Protection context 12, user write enable. 1 2 read-write PC13_NS Protection context 13, non-secure. 12 13 read-write PC13_PR Protection context 13, privileged read enable. 10 11 read-write PC13_PW Protection context 13, privileged write enable. 11 12 read-write PC13_UR Protection context 13, user read enable. 8 9 read-write PC13_UW Protection context 13, user write enable. 9 10 read-write PC14_NS Protection context 14, non-secure. 20 21 read-write PC14_PR Protection context 14, privileged read enable. 18 19 read-write PC14_PW Protection context 14, privileged write enable. 19 20 read-write PC14_UR Protection context 14, user read enable. 16 17 read-write PC14_UW Protection context 14, user write enable. 17 18 read-write PC15_NS Protection context 15, non-secure. 28 29 read-write PC15_PR Protection context 15, privileged read enable. 26 27 read-write PC15_PW Protection context 15, privileged write enable. 27 28 read-write PC15_UR Protection context 15, user read enable. 24 25 read-write PC15_UW Protection context 15, user write enable. 25 26 read-write SL_SIZE Slave region, size 0x4 32 read-write n 0x0 0x0 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region 24 29 read-write VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. 31 32 read-write PROT Protection PROT 0x0 0x0 0x10000 registers n ADDR MPU region address 0x0 32 read-write n 0x0 0x0 ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. 8 32 read-write SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. 0 8 read-write ADDR0 SMPU region address 0 (slave structure) 0x0 32 read-write n 0x0 0x0 ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. 8 32 read-write SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. 0 8 read-write ADDR1 SMPU region address 1 (master structure) 0x20 32 read-only n 0x0 0x0 ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only. 8 32 read-only SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. 0 8 read-only ATT MPU region attrributes 0x4 32 read-write n 0x0 0x0 ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. 31 32 read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). 6 7 read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). 3 4 read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). 4 5 read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). 5 6 read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region 24 29 read-write UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). 0 1 read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). 1 2 read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). 2 3 read-write ATT0 SMPU region attributes 0 (slave structure) 0x4 32 read-write n 0x0 0x0 ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. 31 32 read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). 6 7 read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. 8 9 read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled i.e. not allowed. If '1', protection context i+1 access is enabled i.e. allowed. 9 24 read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. 30 31 read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). 3 4 read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). 4 5 read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). 5 6 read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region 24 29 read-write UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). 0 1 read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). 1 2 read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). 2 3 read-write ATT1 SMPU region attributes 1 (master structure) 0x24 32 read-write n 0x0 0x0 ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. 31 32 read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). 6 7 read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. 8 9 read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled i.e. not allowed. If '1', protection context i+1 access is enabled i.e. allowed. 9 24 read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. 30 31 read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1' i.e. privileged read accesses are ALWAYS allowed. 3 4 read-only PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). 4 5 read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0' i.e. privileged execute accesses are NEVER allowed. 5 6 read-only REGION_SIZE This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only. 24 29 read-only UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1' i.e. user read accesses are ALWAYS allowed. 0 1 read-only UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). 1 2 read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0' i.e. user execute accesses are NEVER allowed. 2 3 read-only MS0_CTL Master 0 protection context control 0x0 32 read-write n 0x0 0x0 NS Security setting ('0': secure mode '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters. 1 2 read-write P Privileged setting ('0': user mode '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities. 0 1 read-write PC_MASK_0 Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. 16 17 read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). 17 32 read-write PRIO Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. 8 10 read-write MS10_CTL Master 10 protection context control 0x28 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS11_CTL Master 11 protection context control 0x2C 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS12_CTL Master 12 protection context control 0x30 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS13_CTL Master 13 protection context control 0x34 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS14_CTL Master 14 protection context control 0x38 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS15_CTL Master 15 protection context control 0x3C 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS1_CTL Master 1 protection context control 0x4 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS2_CTL Master 2 protection context control 0x8 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS3_CTL Master 3 protection context control 0xC 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS4_CTL Master 4 protection context control 0x10 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS5_CTL Master 5 protection context control 0x14 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS6_CTL Master 6 protection context control 0x18 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS7_CTL Master 7 protection context control 0x1C 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS8_CTL Master 8 protection context control 0x20 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS9_CTL Master 9 protection context control 0x24 32 read-write n 0x0 0x0 NS See MS0_CTL.NS. 1 2 read-write P See MS0_CTL.P. 0 1 read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. 16 17 read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. 17 32 read-write PRIO See MS0_CTL.PRIO 8 10 read-write MS_CTL Master control 0x0 32 read-write n 0x0 0x0 PC Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: * On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: IF (the new PC is the same as MS_CTL.PC) PC is not affected PC_SAVED is not affected. ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) An AHB-Lite bus error is generated for the exception handler fetch PC is not affected PC_SAVED is not affected. ELSE PC = 'new PC' PC_SAVED = PC (push operation). * On entry of any other exception/interrupt handler: PC = PC_SAVED PC_SAVED is not affected (pop operation). Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. 0 4 read-write PC_SAVED Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. Note: this field is ONLY used by the CM0+. 16 20 read-write MS_CTL_READ_MIR0 Master control read mirror 0x4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR1 Master control read mirror 0x8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR10 Master control read mirror 0x2C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR100 Master control read mirror 0x194 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR101 Master control read mirror 0x198 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR102 Master control read mirror 0x19C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR103 Master control read mirror 0x1A0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR104 Master control read mirror 0x1A4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR105 Master control read mirror 0x1A8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR106 Master control read mirror 0x1AC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR107 Master control read mirror 0x1B0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR108 Master control read mirror 0x1B4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR109 Master control read mirror 0x1B8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR11 Master control read mirror 0x30 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR110 Master control read mirror 0x1BC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR111 Master control read mirror 0x1C0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR112 Master control read mirror 0x1C4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR113 Master control read mirror 0x1C8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR114 Master control read mirror 0x1CC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR115 Master control read mirror 0x1D0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR116 Master control read mirror 0x1D4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR117 Master control read mirror 0x1D8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR118 Master control read mirror 0x1DC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR119 Master control read mirror 0x1E0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR12 Master control read mirror 0x34 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR120 Master control read mirror 0x1E4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR121 Master control read mirror 0x1E8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR122 Master control read mirror 0x1EC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR123 Master control read mirror 0x1F0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR124 Master control read mirror 0x1F4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR125 Master control read mirror 0x1F8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR126 Master control read mirror 0x1FC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR13 Master control read mirror 0x38 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR14 Master control read mirror 0x3C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR15 Master control read mirror 0x40 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR16 Master control read mirror 0x44 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR17 Master control read mirror 0x48 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR18 Master control read mirror 0x4C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR19 Master control read mirror 0x50 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR2 Master control read mirror 0xC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR20 Master control read mirror 0x54 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR21 Master control read mirror 0x58 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR22 Master control read mirror 0x5C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR23 Master control read mirror 0x60 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR24 Master control read mirror 0x64 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR25 Master control read mirror 0x68 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR26 Master control read mirror 0x6C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR27 Master control read mirror 0x70 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR28 Master control read mirror 0x74 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR29 Master control read mirror 0x78 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR3 Master control read mirror 0x10 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR30 Master control read mirror 0x7C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR31 Master control read mirror 0x80 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR32 Master control read mirror 0x84 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR33 Master control read mirror 0x88 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR34 Master control read mirror 0x8C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR35 Master control read mirror 0x90 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR36 Master control read mirror 0x94 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR37 Master control read mirror 0x98 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR38 Master control read mirror 0x9C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR39 Master control read mirror 0xA0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR4 Master control read mirror 0x14 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR40 Master control read mirror 0xA4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR41 Master control read mirror 0xA8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR42 Master control read mirror 0xAC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR43 Master control read mirror 0xB0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR44 Master control read mirror 0xB4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR45 Master control read mirror 0xB8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR46 Master control read mirror 0xBC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR47 Master control read mirror 0xC0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR48 Master control read mirror 0xC4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR49 Master control read mirror 0xC8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR5 Master control read mirror 0x18 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR50 Master control read mirror 0xCC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR51 Master control read mirror 0xD0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR52 Master control read mirror 0xD4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR53 Master control read mirror 0xD8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR54 Master control read mirror 0xDC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR55 Master control read mirror 0xE0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR56 Master control read mirror 0xE4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR57 Master control read mirror 0xE8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR58 Master control read mirror 0xEC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR59 Master control read mirror 0xF0 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR6 Master control read mirror 0x1C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR60 Master control read mirror 0xF4 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR61 Master control read mirror 0xF8 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR62 Master control read mirror 0xFC 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR63 Master control read mirror 0x100 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR64 Master control read mirror 0x104 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR65 Master control read mirror 0x108 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR66 Master control read mirror 0x10C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR67 Master control read mirror 0x110 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR68 Master control read mirror 0x114 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR69 Master control read mirror 0x118 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR7 Master control read mirror 0x20 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR70 Master control read mirror 0x11C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR71 Master control read mirror 0x120 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR72 Master control read mirror 0x124 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR73 Master control read mirror 0x128 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR74 Master control read mirror 0x12C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR75 Master control read mirror 0x130 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR76 Master control read mirror 0x134 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR77 Master control read mirror 0x138 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR78 Master control read mirror 0x13C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR79 Master control read mirror 0x140 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR8 Master control read mirror 0x24 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR80 Master control read mirror 0x144 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR81 Master control read mirror 0x148 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR82 Master control read mirror 0x14C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR83 Master control read mirror 0x150 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR84 Master control read mirror 0x154 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR85 Master control read mirror 0x158 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR86 Master control read mirror 0x15C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR87 Master control read mirror 0x160 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR88 Master control read mirror 0x164 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR89 Master control read mirror 0x168 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR9 Master control read mirror 0x28 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR90 Master control read mirror 0x16C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR91 Master control read mirror 0x170 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR92 Master control read mirror 0x174 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR93 Master control read mirror 0x178 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR94 Master control read mirror 0x17C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR95 Master control read mirror 0x180 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR96 Master control read mirror 0x184 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR97 Master control read mirror 0x188 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR98 Master control read mirror 0x18C 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only MS_CTL_READ_MIR99 Master control read mirror 0x190 32 read-only n 0x0 0x0 PC Read-only mirror of MS_CTL.PC 0 4 read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED 16 20 read-only SRSS SRSS Core Registers SRSS 0x0 0x0 0x10000 registers n CLK_CAL_CNT1 Clock Calibration Counter 1 0x51C 32 read-write n 0x0 0x0 CAL_COUNTER1 Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. 0 24 read-write CAL_COUNTER_DONE Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up 31 32 read-only CLK_CAL_CNT2 Clock Calibration Counter 2 0x520 32 read-only n 0x0 0x0 CAL_COUNTER2 Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) 0 24 read-only CLK_DSI_SELECT0 Clock DSI Select Register 0x300 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT1 Clock DSI Select Register 0x304 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT10 Clock DSI Select Register 0x328 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT11 Clock DSI Select Register 0x32C 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT12 Clock DSI Select Register 0x330 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT13 Clock DSI Select Register 0x334 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT14 Clock DSI Select Register 0x338 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT15 Clock DSI Select Register 0x33C 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT2 Clock DSI Select Register 0x308 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT3 Clock DSI Select Register 0x30C 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT4 Clock DSI Select Register 0x310 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT5 Clock DSI Select Register 0x314 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT6 Clock DSI Select Register 0x318 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT7 Clock DSI Select Register 0x31C 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT8 Clock DSI Select Register 0x320 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_DSI_SELECT9 Clock DSI Select Register 0x324 32 read-write n 0x0 0x0 DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. 0 5 read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 CLK_ECO_CONFIG ECO Configuration Register 0x52C 32 read-write n 0x0 0x0 AGC_EN Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. 1 2 read-write ECO_EN Master enable for ECO oscillator. 31 32 read-write CLK_ECO_STATUS ECO Status Register 0x530 32 read-only n 0x0 0x0 ECO_OK Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. 0 1 read-only ECO_READY Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. 1 2 read-only CLK_FLL_CONFIG FLL Configuration Register 0x580 32 read-write n 0x0 0x0 FLL_ENABLE Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. 0: Block is powered off 1: Block is powered on 31 32 read-write FLL_MULT Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) 0 18 read-write FLL_OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2 24 25 read-write CLK_FLL_CONFIG2 FLL Configuration Register 2 0x584 32 read-write n 0x0 0x0 FLL_REF_DIV Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191 0 13 read-write LOCK_TOL Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 511: tolerate error of 512 count values 16 25 read-write CLK_FLL_CONFIG3 FLL Configuration Register 3 0x588 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. 28 30 read-write AUTO N/A 0 AUTO1 N/A 1 FLL_REF Select FLL reference input (bypass mode). Ignores lock indicator 2 FLL_OUT Select FLL output. Ignores lock indicator. 3 FLL_LF_IGAIN FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal 0 4 read-write FLL_LF_PGAIN FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal 4 8 read-write SETTLING_COUNT Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles 8 21 read-write CLK_FLL_CONFIG4 FLL Configuration Register 4 0x58C 32 read-write n 0x0 0x0 CCO_ENABLE Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on 31 32 read-write CCO_FREQ CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. 16 25 read-write CCO_HW_UPDATE_DIS Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. 30 31 read-write CCO_LIMIT Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) 0 8 read-write CCO_RANGE Frequency range of CCO 8 11 read-write RANGE0 Target frequency is in range [48, 64) MHz 0 RANGE1 Target frequency is in range [64, 85) MHz 1 RANGE2 Target frequency is in range [85, 113) MHz 2 RANGE3 Target frequency is in range [113, 150) MHz 3 RANGE4 Target frequency is in range [150, 200] MHz 4 CLK_FLL_STATUS FLL Status Register 0x590 32 read-write n 0x0 0x0 CCO_READY This indicates that the CCO is internally settled and ready to use. 2 3 read-only LOCKED FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. 0 1 read-only UNLOCK_OCCURRED N/A 1 2 read-write CLK_ILO_CONFIG ILO Configuration 0x50C 32 read-write n 0x0 0x0 ENABLE Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. 31 32 read-write ILO_BACKUP If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0: ILO turns off at XRES/BOD event or HIBERNATE entry. 1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. 0 1 read-write CLK_IMO_CONFIG IMO Configuration 0x510 32 read-write n 0x0 0x0 ENABLE Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0. 31 32 read-write CLK_OUTPUT_FAST Fast Clock Output Select Register 0x514 32 read-write n 0x0 0x0 FAST_SEL0 Select signal for fast clock output #0 0 4 read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL0 Selects the clock path chosen by PATH_SEL0 field 5 HFCLK_SEL0 Selects the output of the HFCLK_SEL0 mux 6 SLOW_SEL0 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 7 FAST_SEL1 Select signal for fast clock output #1 16 20 read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL1 Selects the clock path chosen by PATH_SEL1 field 5 HFCLK_SEL1 Selects the output of the HFCLK_SEL1 mux 6 SLOW_SEL1 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 7 HFCLK_SEL0 Selects a HFCLK tree for use in fast clock output #0 8 12 read-write HFCLK_SEL1 Selects a HFCLK tree for use in fast clock output #1 logic 24 28 read-write PATH_SEL0 Selects a clock path to use in fast clock output #0 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) 4 8 read-write PATH_SEL1 Selects a clock path to use in fast clock output #1 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) 20 24 read-write CLK_OUTPUT_SLOW Slow Clock Output Select Register 0x518 32 read-write n 0x0 0x0 SLOW_SEL0 Select signal for slow clock output #0 0 4 read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 SLOW_SEL1 Select signal for slow clock output #1 4 8 read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 CLK_PATH_SELECT0 Clock Path Select Register 0x340 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT1 Clock Path Select Register 0x344 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT10 Clock Path Select Register 0x368 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT11 Clock Path Select Register 0x36C 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT12 Clock Path Select Register 0x370 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT13 Clock Path Select Register 0x374 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT14 Clock Path Select Register 0x378 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT15 Clock Path Select Register 0x37C 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT2 Clock Path Select Register 0x348 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT3 Clock Path Select Register 0x34C 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT4 Clock Path Select Register 0x350 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT5 Clock Path Select Register 0x354 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT6 Clock Path Select Register 0x358 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT7 Clock Path Select Register 0x35C 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT8 Clock Path Select Register 0x360 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PATH_SELECT9 Clock Path Select Register 0x364 32 read-write n 0x0 0x0 PATH_MUX Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 3 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 CLK_PILO_CONFIG Precision ILO Configuration Register 0x53C 32 read-write n 0x0 0x0 PILO_CLK_EN Enable the PILO clock output. See PILO_EN field for required sequencing. 29 30 read-write PILO_EN Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. 31 32 read-write PILO_FFREQ Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. 0 10 read-write PILO_RESET_N Reset the PILO. See PILO_EN field for required sequencing. 30 31 read-write CLK_PLL_CONFIG0 PLL Configuration Register 0x600 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG1 PLL Configuration Register 0x604 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG10 PLL Configuration Register 0x628 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG11 PLL Configuration Register 0x62C 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG12 PLL Configuration Register 0x630 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG13 PLL Configuration Register 0x634 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG14 PLL Configuration Register 0x638 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG2 PLL Configuration Register 0x608 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG3 PLL Configuration Register 0x60C 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG4 PLL Configuration Register 0x610 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG5 PLL Configuration Register 0x614 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG6 PLL Configuration Register 0x618 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG7 PLL Configuration Register 0x61C 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG8 PLL Configuration Register 0x620 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_CONFIG9 PLL Configuration Register 0x624 32 read-write n 0x0 0x0 BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. 28 30 read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled 31 32 read-write FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) 0 7 read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) 16 21 read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) 27 28 read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) 8 13 read-write CLK_PLL_STATUS0 PLL Status Register 0x640 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS1 PLL Status Register 0x644 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS10 PLL Status Register 0x668 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS11 PLL Status Register 0x66C 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS12 PLL Status Register 0x670 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS13 PLL Status Register 0x674 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS14 PLL Status Register 0x678 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS2 PLL Status Register 0x648 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS3 PLL Status Register 0x64C 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS4 PLL Status Register 0x650 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS5 PLL Status Register 0x654 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS6 PLL Status Register 0x658 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS7 PLL Status Register 0x65C 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS8 PLL Status Register 0x660 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_PLL_STATUS9 PLL Status Register 0x664 32 read-write n 0x0 0x0 LOCKED PLL Lock Indicator 0 1 read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. 1 2 read-write CLK_ROOT_SELECT0 Clock Root Select Register 0x380 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT1 Clock Root Select Register 0x384 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT10 Clock Root Select Register 0x3A8 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT11 Clock Root Select Register 0x3AC 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT12 Clock Root Select Register 0x3B0 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT13 Clock Root Select Register 0x3B4 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT14 Clock Root Select Register 0x3B8 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT15 Clock Root Select Register 0x3BC 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT2 Clock Root Select Register 0x388 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT3 Clock Root Select Register 0x38C 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT4 Clock Root Select Register 0x390 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT5 Clock Root Select Register 0x394 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT6 Clock Root Select Register 0x398 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT7 Clock Root Select Register 0x39C 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT8 Clock Root Select Register 0x3A0 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_ROOT_SELECT9 Clock Root Select Register 0x3A4 32 read-write n 0x0 0x0 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. 31 32 read-write ROOT_DIV Selects predivider value for this clock root and DSI input. 4 6 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ROOT_MUX Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 4 read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 CLK_SELECT Clock selection register 0x500 32 read-write n 0x0 0x0 LFCLK_SEL Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0 2 read-write ILO ILO - Internal Low-speed Oscillator 0 WCO WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). 1 ALTLF ALTLF - Alternate Low-Frequency Clock. Capability is product-specific 2 PILO PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. 3 PUMP_DIV Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. 12 15 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 DIV_BY_16 Divide selected clock source by 16 4 PUMP_ENABLE Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: 1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. 2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. 15 16 read-write PUMP_SEL Selects clock PATH, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. 8 12 read-write CLK_TIMER_CTL Timer Clock Control Register 0x504 32 read-write n 0x0 0x0 ENABLE Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled 31 32 read-write TIMER_DIV Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. 16 24 read-write TIMER_HF0_DIV Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. 8 10 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. 0 DIV_BY_2 Divide HFCLK0 by 2. 1 DIV_BY_4 Divide HFCLK0 by 4. 2 DIV_BY_8 Divide HFCLK0 by 8. 3 TIMER_SEL Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. 0 1 read-write IMO IMO - Internal Main Oscillator 0 HF0_DIV Select the output of the predivider configured by TIMER_HF0_DIV. 1 CLK_TRIM_CCO_CTL CCO Trim Register 0x7F08 32 read-write n 0x0 0x0 CCO_RCSTRIM CCO reference current source trim. 0 6 read-write CCO_STABLE_CNT Terminal count for the stabilization counter from CCO_ENABLE until stable. 24 30 read-write ENABLE_CNT Enables the automatic stabilization counter. 31 32 read-write CLK_TRIM_CCO_CTL2 CCO Trim Register 2 0x7F0C 32 read-write n 0x0 0x0 CCO_FCTRIM1 CCO frequency 1st range calibration 0 5 read-write CCO_FCTRIM2 CCO frequency 2nd range calibration 5 10 read-write CCO_FCTRIM3 CCO frequency 3rd range calibration 10 15 read-write CCO_FCTRIM4 CCO frequency 4th range calibration 15 20 read-write CCO_FCTRIM5 CCO frequency 5th range calibration 20 25 read-write CLK_TRIM_ECO_CTL ECO Trim Register 0xFF20 32 read-write n 0x0 0x0 ATRIM Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0 - 150mV 0x1 - 175mV 0x2 - 200mV 0x3 - 225mV 0x4 - 250mV 0x5 - 275mV 0x6 - 300mV 0x7 - 325mV 0x8 - 350mV 0x9 - 375mV 0xA - 400mV 0xB - 425mV 0xC - 450mV 0xD - 475mV 0xE - 500mV 0xF - 525mV 4 8 read-write FTRIM Filter Trim - 3rd harmonic oscillation 8 10 read-write GTRIM Gain Trim - Startup time 12 14 read-write ITRIM Current Trim 16 22 read-write RTRIM Feedback resistor Trim 10 12 read-write WDTRIM Watch Dog Trim - Delta voltage below steady state level 0x0 - 50mV 0x1 - 75mV 0x2 - 100mV 0x3 - 125mV 0x4 - 150mV 0x5 - 175mV 0x6 - 200mV 0x7 - 225mV 0 3 read-write CLK_TRIM_ILO_CTL ILO Trim Register 0xFF18 32 read-write n 0x0 0x0 ILO_FTRIM ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. 0 6 read-write CLK_TRIM_PILO_CTL PILO Trim Register 0xFF24 32 read-write n 0x0 0x0 PILO_CFREQ Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. 0 6 read-write PILO_COMP_TRIM Trim for comparator bias current. 16 18 read-write PILO_ISLOPE_TRIM Trim for beta-multiplier current slope 26 28 read-write PILO_NBIAS_TRIM Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier 18 20 read-write PILO_OSC_TRIM Trim for current in oscillator block. 12 15 read-write PILO_RES_TRIM Trim for beta-multiplier branch current 20 25 read-write PILO_VTDIFF_TRIM Trim for VT-DIFF output (internal power supply) 28 31 read-write CLK_TRIM_PILO_CTL2 PILO Trim Register 2 0xFF28 32 read-write n 0x0 0x0 PILO_IREFBM_TRIM Trim for beta-multiplier current reference 8 13 read-write PILO_IREF_TRIM Trim for current reference 16 24 read-write PILO_VREF_TRIM Trim for voltage reference 0 8 read-write CLK_TRIM_PILO_CTL3 PILO Trim Register 3 0xFF2C 32 read-write n 0x0 0x0 PILO_ENGOPT Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. 0 16 read-write INTR SRSS Interrupt Register 0x700 32 read-write n 0x0 0x0 CLK_CAL Clock calibration counter is done. This field is reset during DEEPSLEEP mode. 5 6 read-write HVLVD1 Interrupt for low voltage detector HVLVD1 1 2 read-write WDT_MATCH WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. 0 1 read-write INTR_CFG SRSS Interrupt Configuration Register 0x710 32 read-write n 0x0 0x0 HVLVD1_EDGE_SEL Sets which edge(s) will trigger an IRQ for HVLVD1 0 2 read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 INTR_MASK SRSS Interrupt Mask Register 0x708 32 read-write n 0x0 0x0 CLK_CAL Mask for clock calibration done 5 6 read-write HVLVD1 Mask for low voltage detector HVLVD1 1 2 read-write WDT_MATCH Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. 0 1 read-write INTR_MASKED SRSS Interrupt Masked Register 0x70C 32 read-only n 0x0 0x0 CLK_CAL Logical and of corresponding request and mask bits. 5 6 read-only HVLVD1 Logical and of corresponding request and mask bits. 1 2 read-only WDT_MATCH Logical and of corresponding request and mask bits. 0 1 read-only INTR_SET SRSS Interrupt Set Register 0x704 32 read-write n 0x0 0x0 CLK_CAL Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. 5 6 read-write HVLVD1 Set interrupt for low voltage detector HVLVD1 1 2 read-write WDT_MATCH Set interrupt for low voltage detector WDT_MATCH 0 1 read-write MCWDT_CNTHIGH Multi-Counter Watchdog Sub-counter 2 0x8 32 read-write n 0x0 0x0 WDT_CTR2 Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled 0 32 read-write MCWDT_CNTLOW Multi-Counter Watchdog Sub-counters 0/1 0x4 32 read-write n 0x0 0x0 WDT_CTR0 Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. 0 16 read-write WDT_CTR1 Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled 16 32 read-write MCWDT_CONFIG Multi-Counter Watchdog Counter Configuration 0x10 32 read-write n 0x0 0x0 WDT_BITS2 Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) ... 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) 24 29 read-write WDT_CASCADE0_1 Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters 3 4 read-write WDT_CASCADE1_2 Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. 11 12 read-write WDT_CLEAR0 Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. 2 3 read-write WDT_CLEAR1 Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. 10 11 read-write WDT_MODE0 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). 0 2 read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_MODE1 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). 8 10 read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_MODE2 Watchdog Counter 2 Mode. 16 17 read-write NOTHING Free running counter with no interrupt requests 0 INT Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). 1 MCWDT_CTL Multi-Counter Watchdog Counter Control 0x14 32 read-write n 0x0 0x0 WDT_ENABLE0 Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) 0 1 read-write WDT_ENABLE1 Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) 8 9 read-write WDT_ENABLE2 Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) 16 17 read-write WDT_ENABLED0 Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. 1 2 read-only WDT_ENABLED1 Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. 9 10 read-only WDT_ENABLED2 Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. 17 18 read-only WDT_RESET0 Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. 3 4 read-write WDT_RESET1 Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. 11 12 read-write WDT_RESET2 Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. 19 20 read-write MCWDT_INTR Multi-Counter Watchdog Counter Interrupt Register 0x18 32 read-write n 0x0 0x0 MCWDT_INT0 MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. 0 1 read-write MCWDT_INT1 MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. 1 2 read-write MCWDT_INT2 MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. 2 3 read-write MCWDT_INTR_MASK Multi-Counter Watchdog Counter Interrupt Mask Register 0x20 32 read-write n 0x0 0x0 MCWDT_INT0 Mask for sub-counter 0 0 1 read-write MCWDT_INT1 Mask for sub-counter 1 1 2 read-write MCWDT_INT2 Mask for sub-counter 2 2 3 read-write MCWDT_INTR_MASKED Multi-Counter Watchdog Counter Interrupt Masked Register 0x24 32 read-only n 0x0 0x0 MCWDT_INT0 Logical and of corresponding request and mask bits. 0 1 read-only MCWDT_INT1 Logical and of corresponding request and mask bits. 1 2 read-only MCWDT_INT2 Logical and of corresponding request and mask bits. 2 3 read-only MCWDT_INTR_SET Multi-Counter Watchdog Counter Interrupt Set Register 0x1C 32 read-write n 0x0 0x0 MCWDT_INT0 Set interrupt for MCWDT_INT0 0 1 read-write MCWDT_INT1 Set interrupt for MCWDT_INT1 1 2 read-write MCWDT_INT2 Set interrupt for MCWDT_INT2 2 3 read-write MCWDT_LOCK Multi-Counter Watchdog Counter Lock Register 0x28 32 read-write n 0x0 0x0 MCWDT_LOCK Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. 30 32 read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 MCWDT_MATCH Multi-Counter Watchdog Counter Match Register 0xC 32 read-write n 0x0 0x0 WDT_MATCH0 Match value for sub-counter 0 of this MCWDT 0 16 read-write WDT_MATCH1 Match value for sub-counter 1 of this MCWDT 16 32 read-write PWR_BUCK_CTL Buck Control Register 0x14 32 read-write n 0x0 0x0 BUCK_EN Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. 30 31 read-write BUCK_OUT1_EN Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. TRM must follow the SAS. 31 32 read-write BUCK_OUT1_SEL Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V 0 3 read-write PWR_BUCK_CTL2 Buck Control Register 2 0x18 32 read-write n 0x0 0x0 BUCK_OUT2_EN Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. 31 32 read-write BUCK_OUT2_HW_SEL Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. 30 31 read-write BUCK_OUT2_SEL Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V 0 3 read-write PWR_CTL Power Mode Control 0x0 32 read-write n 0x0 0x0 ACT_REF_DIS Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled 30 31 read-write ACT_REF_OK Indicates that the normal mode of the Active Reference is ready. 31 32 read-only BGREF_LPMODE Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0. 26 27 read-write DEBUG_SESSION Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) 4 5 read-only NO_SESSION No debug session active 0 SESSION_ACTIVE Debug session is active. Power modes behave differently to keep the debug session active. 1 DPSLP_REG_DIS Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off. 20 21 read-write IREF_LPMODE Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. 18 19 read-write LINREG_DIS Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off. 23 24 read-write LINREG_LPMODE Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. 24 25 read-write LPM_READY Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. 5 6 read-only NWELL_REG_DIS Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off. 22 23 read-write PLL_LS_BYPASS Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. 27 28 read-write PORBOD_LPMODE Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. 25 26 read-write POWER_MODE Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. 0 2 read-only RESET System is resetting. 0 ACTIVE At least one CPU is running. 1 SLEEP No CPUs are running. Peripherals may be running. 2 DEEPSLEEP Main high-frequency clock is off low speed clocks are available. Communication interface clocks may be present. 3 RET_REG_DIS Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off. 21 22 read-write VREFBUF_DIS Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. 29 30 read-write VREFBUF_LPMODE Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/HIBERNATE. 1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. 28 29 read-write VREFBUF_OK Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. 19 20 read-only PWR_HIBERNATE HIBERNATE Mode Register 0x4 32 read-write n 0x0 0x0 FREEZE Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. 17 18 read-write HIBERNATE Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. 31 32 read-write HIBERNATE_DISABLE Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. 30 31 read-write MASK_HIBALARM When set, HIBERNATE will wakeup for a RTC interrupt 18 19 read-write MASK_HIBPIN When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. 24 28 read-write MASK_HIBWDT When set, HIBERNATE will wakeup if WDT matches 19 20 read-write POLARITY_HIBPIN Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE 20 24 read-write TOKEN Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. 0 8 read-write UNLOCK This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. 8 16 read-write PWR_HIB_DATA0 HIBERNATE Data Register 0x80 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA1 HIBERNATE Data Register 0x84 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA10 HIBERNATE Data Register 0xA8 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA11 HIBERNATE Data Register 0xAC 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA12 HIBERNATE Data Register 0xB0 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA13 HIBERNATE Data Register 0xB4 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA14 HIBERNATE Data Register 0xB8 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA15 HIBERNATE Data Register 0xBC 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA2 HIBERNATE Data Register 0x88 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA3 HIBERNATE Data Register 0x8C 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA4 HIBERNATE Data Register 0x90 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA5 HIBERNATE Data Register 0x94 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA6 HIBERNATE Data Register 0x98 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA7 HIBERNATE Data Register 0x9C 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA8 HIBERNATE Data Register 0xA0 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_HIB_DATA9 HIBERNATE Data Register 0xA4 32 read-write n 0x0 0x0 HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. 0 32 read-write PWR_LVD_CTL Low Voltage Detector (LVD) Configuration Register 0x8 32 read-write n 0x0 0x0 HVLVD1_EN Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. 7 8 read-write HVLVD1_SRCSEL Source selection for HVLVD1 4 7 read-write VDDD Select VDDD 0 AMUXBUSA Select AMUXBUSA (VDDD branch) 1 RSVD N/A 2 VDDIO N/A 3 AMUXBUSB Select AMUXBUSB (VDDD branch) 4 HVLVD1_TRIPSEL Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom) 0 4 read-write PWR_LVD_STATUS Low Voltage Detector (LVD) Status Register 0x1C 32 read-only n 0x0 0x0 HVLVD1_OK HVLVD1 output. 0: below voltage threshold 1: above voltage threshold 0 1 read-only PWR_TRIM_BODOVP_CTL BOD/OVP Trim Register 0x7F04 32 read-write n 0x0 0x0 HVPORBOD_ITRIM HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 7 10 read-write HVPORBOD_OFSTRIM HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 4 7 read-write HVPORBOD_TRIPSEL HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 3 read-write LVPORBOD_ITRIM LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 17 20 read-write LVPORBOD_OFSTRIM LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 14 17 read-write LVPORBOD_TRIPSEL LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. 10 13 read-write PWR_TRIM_LVD_CTL LVD Trim Register 0xFF10 32 read-write n 0x0 0x0 HVLVD1_ITRIM HVLVD1 current trim 4 7 read-write HVLVD1_OFSTRIM HVLVD1 offset trim 0 3 read-write PWR_TRIM_PWRSYS_CTL Power System Trim Register 0xFF1C 32 read-write n 0x0 0x0 ACT_REG_BOOST Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default) 100mA chip: 2'b00 (default) 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default) 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default) 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default) 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default) This register is only reset by XRES/POR/BOD/HIBERNATE. 30 32 read-write ACT_REG_TRIM Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. Two voltages are supported: 0.9V and 1.1V. The codes for these are stored in SFLASH_LDO_0P9V_TRIM and SFLASH_LDO_1P1V_TRIM, respectively. 0 5 read-write PWR_TRIM_REF_CTL Reference Trim Register 0x7F00 32 read-write n 0x0 0x0 ACT_REF_ABSTRIM Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range 8 13 read-write ACT_REF_IBOOST Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: normal operation others: risk mitigation 14 15 read-write ACT_REF_ITRIM Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range 4 8 read-write ACT_REF_TCTRIM Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range 0 4 read-write DPSLP_REF_ABSTRIM DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 20 25 read-write DPSLP_REF_ITRIM DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 28 32 read-write DPSLP_REF_TCTRIM DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range 16 20 read-write PWR_TRIM_WAKE_CTL Wakeup Trim Register 0x7F30 32 read-write n 0x0 0x0 WAKE_DELAY Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. 0 8 read-write RES_CAUSE Reset Cause Observation Register 0x800 32 read-write n 0x0 0x0 RESET_ACT_FAULT Fault logging system requested a reset from its Active logic. 1 2 read-write RESET_CSV_WCO_LOSS Clock supervision logic requested a reset due to loss of a watch-crystal clock. 3 4 read-write RESET_DPSLP_FAULT Fault logging system requested a reset from its DeepSleep logic. 2 3 read-write RESET_MCWDT0 Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. 5 6 read-write RESET_MCWDT1 Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. 6 7 read-write RESET_MCWDT2 Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. 7 8 read-write RESET_MCWDT3 Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. 8 9 read-write RESET_SOFT A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. 4 5 read-write RESET_WDT A basic WatchDog Timer (WDT) reset has occurred since last power cycle. 0 1 read-write RES_CAUSE2 Reset Cause Observation Register 2 0x804 32 read-write n 0x0 0x0 RESET_CSV_HF_FREQ Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK. Unimplemented clock bits return zero. 16 32 read-write RESET_CSV_HF_LOSS Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK. Unimplemented clock bits return zero. 0 16 read-write WDT_CNT Watchdog Counter Count Register 0x184 32 read-write n 0x0 0x0 COUNTER Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. 0 16 read-write WDT_CTL Watchdog Counter Control Register 0x180 32 read-write n 0x0 0x0 WDT_EN Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. 0 1 read-write WDT_LOCK Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. 30 32 read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 WDT_MATCH Watchdog Counter Match Register 0x188 32 read-write n 0x0 0x0 IGNORE_BITS The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. 16 20 read-write MATCH Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). 0 16 read-write