Maxim max32625 2024.09.17 The MAX32625/6 device family is designed for wearable and portable medical and fitness applications. The devices contain an ARM Cortex-M4 processor with FPU, execute up to 96MHz and include a 10-bit ADC and a versatile set of on-chip peripherals. CM4 r1p0 little 3 false 8 32 ADC 10-bit Analog to Digital Converter ADC 0x4001F000 0x0 0x1000 registers n ADC ADC IRQ 48 AFE_CTRL AFE Control Register 0x20 read-write n 0x0 0xFFFFFFFF tmon_extbias_en Enable external temperature measurement bias generator 9 10 read-write tmon_intbias_en Enable internal temperature measurement bias generator 8 9 read-write CTRL ADC Control 0x0 read-write n 0x0 0xFFFFFFFF adc_chgpump_pu ADC Charge Pump Power Up 4 5 read-write adc_chsel ADC Channel Select 12 16 read-write adc_clk_en ADC Clock Enable 11 12 read-write adc_dataalign ADC Data Alignment Select 17 18 read-write adc_pu ADC Power Up 1 2 read-write adc_refbuf_pu ADC Reference Buffer Power Up 3 4 read-write adc_refscl ADC Reference Scale 8 9 read-write adc_refsel ADC Reference (VRef) Select (INTERNAL ONLY) 10 11 read-write adc_scale ADC Scale 9 10 read-write adc_xref Enable Use of ADC External Reference 16 17 read-write afe_pwr_up_dly Delay from ADC Powerup Until ADC Ready Asserted 24 32 read-write buf_bypass Bypass Input Buffer 7 8 read-write buf_chop_dis ADC Input Buffer Chop Disable (INTERNAL ONLY) 5 6 read-write buf_pu ADC Input Buffer Power Up 2 3 read-write buf_pump_dis Disable Use of Charge Pump Output by Input Buffer (INTERNAL) 6 7 read-write cpu_adc_start Start ADC Conversion 0 1 read-write DATA ADC Output Data 0x8 read-write n 0x0 0xFFFFFFFF adc_data ADC Converted Sample Data Output 0 16 read-only INTR ADC Interrupt Control Register 0xC read-write n 0x0 0xFFFFFFFF adc_done_ie ADC Done Interrupt Enable 0 1 read-write adc_done_if ADC Done Interrupt Flag 16 17 read-write oneToClear adc_hi_limit_ie ADC Hi Limit Monitor Interrupt Enable 2 3 read-write adc_hi_limit_if ADC Hi Limit Monitor Interrupt Flag 18 19 read-write oneToClear adc_int_pending ADC Interrupt Pending Status 22 23 read-only adc_lo_limit_ie ADC Lo Limit Monitor Interrupt Enable 3 4 read-write adc_lo_limit_if ADC Lo Limit Monitor Interrupt Flag 19 20 read-write oneToClear adc_overflow_ie ADC Overflow Interrupt Enable 4 5 read-write adc_overflow_if ADC Overflow Interrupt Flag 20 21 read-write oneToClear adc_ref_ready_ie ADC Reference Ready Interrupt Enable 1 2 read-write adc_ref_ready_if ADC Reference Ready Interrupt Flag 17 18 read-write oneToClear ro_cal_done_ie RO Cal Done Interrupt Enable 5 6 read-write ro_cal_done_if RO Cal Done Interrupt Flag 21 22 read-write oneToClear LIMIT0 ADC Limit 0x10 read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write LIMIT1 ADC Limit 1 0x14 read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write LIMIT2 ADC Limit 2 0x18 read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write LIMIT3 ADC Limit 3 0x1C read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write RO_CAL0 RO Trim Calibration Register 0 0x24 read-write n 0x0 0xFFFFFFFF dummy Dummy Write Field 5 8 read-write ro_cal_atomic RO Calibration Run Atomic 4 5 read-write ro_cal_en RO Calibration Enable 0 1 read-write ro_cal_load RO Calibration Load Initial Value 2 3 read-write ro_cal_run RO Calibration Run 1 2 read-write ro_trm RO Trim Calibration Result 23 32 read-write trm_mu RO Trim Adaptation Gain 8 20 read-write RO_CAL1 RO Trim Calibration Register 1 0x28 read-write n 0x0 0xFFFFFFFF trm_init RO Trim Initial Value 0 9 read-write trm_max RO Trim Minimum Adaptive Limit 20 29 read-write trm_min RO Trim Maximum Adaptive Limit 10 19 read-write RO_CAL2 RO Trim Calibration Register 2 0x2C read-write n 0x0 0xFFFFFFFF auto_cal_done_cnt Auto Cal Time Delay for Atomic Calibration (in milliseconds) 0 8 read-write STATUS ADC Status 0x4 read-write n 0x0 0xFFFFFFFF adc_active ADC Conversion In Progress 0 1 read-only adc_overflow ADC Overflow 3 4 read-only afe_pwr_up_active AFE Power Up Delay Active 2 3 read-only ro_cal_atomic_active RO Frequency Calibration Active (If Atomic) 1 2 read-only AES AES Cryptographic Engine AES 0x40007400 0x0 0x400 registers n AES AES IRQ 9 CTRL AES Control and Status 0x0 read-write n 0x0 0xFFFFFFFF crypt_mode AES Encrypt/Decrypt Mode 1 2 read-write ENCRYPT_MODE Perform AES encryption operation. 0 DECRYPT_MODE Perform AES decryption operation. 1 exp_key_mode AES Expanded Key Mode 2 3 read-write CALC_NEW_EXP_KEY Calculate new expanded key for this operation. 0 USE_LAST_EXP_KEY Use expanded key calculated by the last operation. 1 inten AES Interrupt Enable 5 6 read-write intfl AES Interrupt Flag 6 7 read-write oneToClear key_size AES Key Size Select 3 5 read-write KEY_SIZE_128 Use 128-bit AES key size. 0 KEY_SIZE_192 Use 192-bit AES key size. 1 KEY_SIZE_256 Use 256-bit AES key size. 2 start AES Start/Busy 0 1 read-write ERASE_ALL A write to this location triggers an erase of all AES memory locations. 0x8 write-only n 0x0 0xFFFFFFFF CLKMAN System Clock Manager System Clock Manager 0x40000400 0x0 0x400 registers n CLKMAN Clock Management IRQ 0 CLK_CONFIG System Clock Configuration 0x0 read-write n 0x0 0xFFFFFFFF crypto_enable Cryptographic (TPU) Relaxation Oscillator Enable 0 1 read-write crypto_stability_count Crypto Oscillator Stability Select 4 8 read-write CLK_CTRL System Clock Controls 0x4 read-write n 0x0 0xFFFFFFFF adc_clock_enable ADC Clock Enable 24 25 read-write cpu_dynamic_clock Enable CPU Dynamic Clock Gating 13 14 read-write crypto_clock_enable Crypto Clock Enable 8 9 read-write rtos_mode Enable RTOS Mode for SysTick Timers 12 13 read-write system_source_select System Clock Source Select 0 2 read-write usb_clock_enable USB Clock Enable 4 5 read-write usb_clock_select USB Clock Select 5 6 read-write wdt0_clock_enable Watchdog 0 Clock Enable 16 17 read-write wdt0_clock_select Watchdog 0 Clock Source Select 17 19 read-write wdt1_clock_enable Watchdog 1 Clock Enable 20 21 read-write wdt1_clock_select Watchdog 1 Clock Source Select 21 23 read-write CLK_GATE_CTRL0 Dynamic Clock Gating Control Register 0 0x140 read-write n 0x0 0xFFFFFFFF ahb32_clk_gater Clock Gating Control for AHB32 2 4 read-write apb_bridge_clk_gater Clock Gating Control for AHB-to-APB Bridge 10 12 read-write cm4_clk_gater Clock Gating Control for CM4 CPU 0 2 read-write crc_clk_gater Clock Gating Control for CRC 26 28 read-write flash_clk_gater Clock Gating Control for Flash Memory 6 8 read-write icache_clk_gater Clock Gating Control for Instruction Cache 4 6 read-write pad_clk_gater Clock Gating Control for Pad Mode Filter 18 20 read-write pmu_clk_gater Clock Gating Control for PMU 22 24 read-write ptp_clk_gater Clock Gating Control for PTP Logic 14 16 read-write spix_clk_gater Clock Gating Control for SPI XIP 20 22 read-write sram_clk_gater Clock Gating Control for SRAM 8 10 read-write ssb_mux_clk_gater Clock Gating Control for SSB Mux 16 18 read-write sysman_clk_gater Clock Gating Control for CLKMAN, PWRMAN, and IOMAN 12 14 read-write tpu_clk_gater Clock Gating Control for TPU 28 30 read-write usb_clk_gater Clock Gating Control for USB 24 26 read-write watchdog0_clk_gater Clock Gating Control for Watchdog Timer 0 30 32 read-write CLK_GATE_CTRL1 Dynamic Clock Gating Control Register 1 0x144 read-write n 0x0 0xFFFFFFFF gpio_clk_gater Clock Gating Control for GPIO Ports 2 4 read-write i2cm0_clk_gater Clock Gating Control for I2C Master 0 26 28 read-write i2cm1_clk_gater Clock Gating Control for I2C Master 1 28 30 read-write i2cm2_clk_gater Clock Gating Control for I2C Master 2 30 32 read-write pulsetrain_clk_gater Clock Gating Control for Pulse Train Generators 16 18 read-write timer0_clk_gater Clock Gating Control for Timer/Counter Module 0 4 6 read-write timer1_clk_gater Clock Gating Control for Timer/Counter Module 1 6 8 read-write timer2_clk_gater Clock Gating Control for Timer/Counter Module 2 8 10 read-write timer3_clk_gater Clock Gating Control for Timer/Counter Module 3 10 12 read-write timer4_clk_gater Clock Gating Control for Timer/Counter Module 4 12 14 read-write timer5_clk_gater Clock Gating Control for Timer/Counter Module 5 14 16 read-write uart0_clk_gater Clock Gating Control for UART 0 18 20 read-write uart1_clk_gater Clock Gating Control for UART 1 20 22 read-write uart2_clk_gater Clock Gating Control for UART 2 22 24 read-write uart3_clk_gater Clock Gating Control for UART 3 24 26 read-write watchdog1_clk_gater Clock Gating Control for Watchdog Timer 1 0 2 read-write CLK_GATE_CTRL2 Dynamic Clock Gating Control Register 2 0x148 read-write n 0x0 0xFFFFFFFF adc_clk_gater Clock Gating Control for ADC 12 14 read-write i2cs_clk_gater Clock Gating Control for I2C Slave 0 2 read-write owm_clk_gater Clock Gating Control for 1-Wire Master (OWM) 10 12 read-write spi0_clk_gater Clock Gating Control for SPI Master 0 2 4 read-write spi1_clk_gater Clock Gating Control for SPI Master 1 4 6 read-write spi2_clk_gater Clock Gating Control for SPI Master 2 6 8 read-write spis_clk_gater Clock Gating Control for SPI Slave 14 16 read-write spi_bridge_clk_gater Clock Gating Control for SPI Bridge 8 10 read-write CM4_START_CLK_EN0 CM4 Start Clock on Interrupt Enable 0 0x18 read-write n 0x0 0xFFFFFFFF ints Interrupt Sources 0-31 0 32 read-write CM4_START_CLK_EN1 CM4 Start Clock on Interrupt Enable 1 0x1C read-write n 0x0 0xFFFFFFFF ints Interrupt Sources 32-63 0 32 read-write CM4_START_CLK_EN2 CM4 Start Clock on Interrupt Enable 2 0x20 read-write n 0x0 0xFFFFFFFF ints Interrupt Sources 95-64 0 32 read-write CRYPT_CLK_CTRL_0_AES Control Settings for Crypto Clock 0 - AES 0x100 read-write n 0x0 0xFFFFFFFF aes_clk_scale Control Settings for Crypto Clock 0 - AES 0 4 read-write CRYPT_CLK_CTRL_1_MAA Control Settings for Crypto Clock 1 - MAA 0x104 read-write n 0x0 0xFFFFFFFF maa_clk_scale Control Settings for Crypto Clock 1 - MAA 0 4 read-write CRYPT_CLK_CTRL_2_PRNG Control Settings for Crypto Clock 2 - PRNG 0x108 read-write n 0x0 0xFFFFFFFF prng_clk_scale Control Settings for Crypto Clock 2 - PRNG 0 4 read-write I2C_TIMER_CTRL I2C Timer Control 0x14 read-write n 0x0 0xFFFFFFFF i2c_1ms_timer_en I2C 1ms Timer Enable 0 1 read-write INTEN Interrupt Enable/Disable Controls 0xC read-write n 0x0 0xFFFFFFFF crypto_stable Crypto Oscillator Stable Interrupt Enable 0 1 read-write sys_ro_stable System Oscillator Stable Interrupt Enable 1 2 read-write INTFL Interrupt Flags 0x8 read-write n 0x0 0xFFFFFFFF crypto_stable Crypto Oscillator Stable Interrupt Flag 0 1 read-write oneToClear sys_ro_stable System Oscillator Stable Interrupt Flag 1 2 read-write oneToClear SYS_CLK_CTRL_0_CM4 Control Settings for CLK0 - Cortex M4 Clock 0x40 read-write n 0x0 0xFFFFFFFF cm4_clk_scale Control Settings for CLK0 - Cortex M4 Clock 0 4 read-write SYS_CLK_CTRL_10_I2CS Control Settings for CLK10 - Source Clock for I2C Slave 0x68 read-write n 0x0 0xFFFFFFFF i2cs_clk_scale Control Settings for CLK10 - Source Clock for I2C Slave 0 4 read-write SYS_CLK_CTRL_11_SPI0 Control Settings for CLK11 - SPI Master 0 0x6C read-write n 0x0 0xFFFFFFFF spi0_clk_scale Control Settings for CLK11 - SPI Master 0 0 4 read-write SYS_CLK_CTRL_12_SPI1 Control Settings for CLK12 - SPI Master 1 0x70 read-write n 0x0 0xFFFFFFFF spi1_clk_scale Control Settings for CLK12 - SPI Master 1 0 4 read-write SYS_CLK_CTRL_13_SPI2 Control Settings for CLK13 - SPI Master 2 0x74 read-write n 0x0 0xFFFFFFFF spi2_clk_scale Control Settings for CLK13 - SPI Master 2 0 4 read-write SYS_CLK_CTRL_14_SPIB Control Settings for CLK14 - SPI Bridge Clock 0x78 read-write n 0x0 0xFFFFFFFF spib_clk_scale Control Settings for CLK14 - SPI Bridge Clock 0 4 read-write SYS_CLK_CTRL_15_OWM Control Settings for CLK15 - 1-Wire Master Clock 0x7C read-write n 0x0 0xFFFFFFFF owm_clk_scale Control Settings for CLK15 - 1-Wire Master Clock 0 4 read-write SYS_CLK_CTRL_16_SPIS Control Settings for CLK16 - SPI Slave Clock 0x80 read-write n 0x0 0xFFFFFFFF spis_clk_scale Control Settings for CLK16 - SPI Slave Clock 0 4 read-write SYS_CLK_CTRL_1_SYNC Control Settings for CLK1 - Synchronizer Clock 0x44 read-write n 0x0 0xFFFFFFFF sync_clk_scale Control Settings for CLK1 - Synchronizer Clock 0 4 read-write SYS_CLK_CTRL_2_SPIX Control Settings for CLK2 - SPI XIP Clock 0x48 read-write n 0x0 0xFFFFFFFF spix_clk_scale Control Settings for CLK2 - SPI XIP Clock 0 4 read-write SYS_CLK_CTRL_3_PRNG Control Settings for CLK3 - PRNG Clock 0x4C read-write n 0x0 0xFFFFFFFF prng_clk_scale Control Settings for CLK3 - PRNG Clock 0 4 read-write SYS_CLK_CTRL_4_WDT0 Control Settings for CLK4 - Watchdog Timer 0 0x50 read-write n 0x0 0xFFFFFFFF watchdog0_clk_scale Control Settings for CLK4 - Watchdog Timer 0 0 4 read-write SYS_CLK_CTRL_5_WDT1 Control Settings for CLK5 - Watchdog Timer 1 0x54 read-write n 0x0 0xFFFFFFFF watchdog1_clk_scale Control Settings for CLK5 - Watchdog Timer 1 0 4 read-write SYS_CLK_CTRL_6_GPIO Control Settings for CLK6 - Clock for GPIO Ports 0x58 read-write n 0x0 0xFFFFFFFF gpio_clk_scale Control Settings for CLK6 - Clock for GPIO Ports 0 4 read-write SYS_CLK_CTRL_7_PT Control Settings for CLK7 - Source Clock for All Pulse Trains 0x5C read-write n 0x0 0xFFFFFFFF pulse_train_clk_scale Control Settings for CLK7 - Source Clock for All Pulse Trains 0 4 read-write SYS_CLK_CTRL_8_UART Control Settings for CLK8 - Source Clock for All UARTs 0x60 read-write n 0x0 0xFFFFFFFF uart_clk_scale Control Settings for CLK8 - Source Clock for All UARTs 0 4 read-write SYS_CLK_CTRL_9_I2CM Control Settings for CLK9 - Source Clock for All I2C Masters 0x64 read-write n 0x0 0xFFFFFFFF i2cm_clk_scale Control Settings for CLK9 - Source Clock for All I2C Masters 0 4 read-write TRIM_CALC Trim Calculation Controls 0x10 read-write n 0x0 0xFFFFFFFF trim_calc_completed Trim Calculation Completed 2 3 read-only trim_calc_results Trim Calculation Results 16 26 read-only trim_calc_start Start Trim Calculation 1 2 read-write trim_clk_sel Trim Clock Select 0 1 read-write trim_enable Trim Logic Enable 3 4 read-write CRC CRC-16/CRC-32 Engine CRC 0x40006000 0x0 0x1000 registers n RESEED CRC-16/CRC-32 Reseed Controls 0x0 read-write n 0x0 0xFFFFFFFF ccitt_mode CRC16-CCITT Mode 8 9 read-write crc16 Reseed CRC16 Generator 0 1 read-write oneToClear crc32 Reseed CRC32 Generator 1 2 read-write oneToClear rev_endian16 Reverse Endianness for CRC16 4 5 read-write rev_endian32 Reverse Endianness for CRC32 5 6 read-write SEED16 Reseed Value for CRC-16 Calculations 0x4 read-write n 0x0 0xFFFFFFFF SEED32 Reseed Value for CRC-32 Calculations 0x8 read-write n 0x0 0xFFFFFFFF FLC Flash Controller FLC 0x40002000 0x0 0x1000 registers n FLC Flash Controller IRQ 2 BL_CTRL Bootloader Control Register 0x170 read-write n 0x0 0xFFFFFFFF BYPASS Status Flags for DSB Operations 0x9C read-write n 0x0 0xFFFFFFFF destruct_bypass_complete Destructive Security Bypass Erase Complete 2 3 read-only destruct_bypass_erase Destructive Security Bypass In Progress 0 1 read-only superwipe_complete Superwipe Erase Complete 3 4 read-only superwipe_erase Superwipe Erase In Progress 1 2 read-only CTRL Flash Control Register 0x8 read-write n 0x0 0xFFFFFFFF auto_incre_mode Address Auto-Increment Mode 27 28 read-write erase_code Flash Erase Code 8 16 read-write flsh_unlock Flash Write/Erase Enable 28 32 read-write info_block_unlock Flash Info Block Locked 16 17 read-only info_block_valid Info Block Valid Status 25 26 read-only mass_erase Start Flash Mass Erase Operation 1 2 read-write page_erase Start Flash Page Erase Operation 2 3 read-write pending Flash Controller Status 24 25 read-only write Start Flash Write Operation 0 1 read-write write_enable Flash Writes Enabled 17 18 read-only CTRL2 Flash Control Register 2 0x140 read-write n 0x0 0xFFFFFFFF bypass_ahb_fail AHB Fail Bypass 8 16 read-write flash_lve Flash LVE Enable 0 8 read-write DISABLE_WE0 Disable Flash Page Write/Erase Register 0 0x300 read-write n 0x0 0xFFFFFFFF DISABLE_WE1 Disable Flash Page Write/Erase Register 1 0x304 read-write n 0x0 0xFFFFFFFF DISABLE_WE2 Disable Flash Page Write/Erase Register 2 0x308 read-write n 0x0 0xFFFFFFFF DISABLE_WE3 Disable Flash Page Write/Erase Register 3 0x30C read-write n 0x0 0xFFFFFFFF DISABLE_WE4 Disable Flash Page Write/Erase Register 4 0x310 read-write n 0x0 0xFFFFFFFF DISABLE_WE5 Disable Flash Page Write/Erase Register 5 0x314 read-write n 0x0 0xFFFFFFFF DISABLE_WE6 Disable Flash Page Write/Erase Register 6 0x318 read-write n 0x0 0xFFFFFFFF DISABLE_WE7 Disable Flash Page Write/Erase Register 7 0x31C read-write n 0x0 0xFFFFFFFF DISABLE_XR0 Disable Flash Page Exec/Read Register 0 0x200 read-write n 0x0 0xFFFFFFFF DISABLE_XR1 Disable Flash Page Exec/Read Register 1 0x204 read-write n 0x0 0xFFFFFFFF DISABLE_XR2 Disable Flash Page Exec/Read Register 2 0x208 read-write n 0x0 0xFFFFFFFF DISABLE_XR3 Disable Flash Page Exec/Read Register 3 0x20C read-write n 0x0 0xFFFFFFFF DISABLE_XR4 Disable Flash Page Exec/Read Register 4 0x210 read-write n 0x0 0xFFFFFFFF DISABLE_XR5 Disable Flash Page Exec/Read Register 5 0x214 read-write n 0x0 0xFFFFFFFF DISABLE_XR6 Disable Flash Page Exec/Read Register 6 0x218 read-write n 0x0 0xFFFFFFFF DISABLE_XR7 Disable Flash Page Exec/Read Register 7 0x21C read-write n 0x0 0xFFFFFFFF FADDR Flash Operation Address 0x0 read-write n 0x0 0xFFFFFFFF faddr Flash Operation Address 0 22 read-write FCKDIV Flash Clock Pulse Divisor 0x4 read-write n 0x0 0xFFFFFFFF auto_fckdiv_result Auto FCKDIV Calculation Result 16 32 read-only fckdiv Flash Clock Pulse Divisor 0 7 read-write FDATA Flash Operation Data Register 0x30 read-write n 0x0 0xFFFFFFFF INTEN1 Interrupt Enable/Disable Register 1 0x148 read-write n 0x0 0xFFFFFFFF flash_read_locked Flash Read from Locked Area Interrupt Enable/Disable 2 3 read-write oneToClear flc_prog_complete Program (Write or Erase) Op Completed Int Enable/Disable 5 6 read-write flc_state_done FLC State Machine Reached DONE Interrupt Enable/Disable 4 5 read-write invalid_flash_addr Invalid Flash Address Interrupt Enable/Disable 1 2 read-write oneToClear sram_addr_wrapped SRAM Address Wrapped Interrupt Enable/Disable 0 1 read-write oneToClear trim_update_done Trim Update Complete Interrupt Enable/Disable 3 4 read-write oneToClear INTFL1 Interrupt Flags Register 1 0x144 read-write n 0x0 0xFFFFFFFF flash_read_locked Flash Read from Locked Area Interrupt Flag 2 3 read-write oneToClear flc_prog_complete Program (Write or Erase) Operation Completed Interrupt Flag 5 6 read-write oneToClear flc_state_done FLC State Machine Reached DONE Interrupt Flag 4 5 read-write oneToClear invalid_flash_addr Invalid Flash Address Interrupt Flag 1 2 read-write oneToClear sram_addr_wrapped SRAM Address Wrapped Interrupt Flag 0 1 read-write oneToClear trim_update_done Trim Update Complete Interrupt Flag 3 4 read-write oneToClear INTR Flash Controller Interrupt Flags and Enable/Disable 0 0x24 read-write n 0x0 0xFFFFFFFF failed_ie Flash Operation Failed Interrupt Enable 9 10 read-write failed_if Flash Operation Failed 1 2 read-write fail_flags Flash Operation Failure Details 16 32 read-only finished_ie Flash Write/Erase Operation Finished Interrupt Enable 8 9 read-write finished_if Flash Write/Erase Operation Finished 0 1 read-write PDM33 PDM33 Register 0x178 read-write n 0x0 0xFFFFFFFF PERFORM Flash Performance Settings 0x50 read-write n 0x0 0xFFFFFFFF auto_clkdiv Auto CLKDIV 29 30 read-write auto_tacc Auto TACC 28 29 read-write delay_se_en Delay SE Enable (Deprecated) 0 1 read-write en_back2back_rds Enable Back To Back Reads 16 17 read-write en_back2back_wrs Enable Back To Back Writes 20 21 read-write en_merge_grab_gnt Enable Merge Grab GNT 24 25 read-write en_prevent_fail Prevent Fail Flag Set on FLC Busy 12 13 read-write fast_read_mode_en Fast Read Mode Enable (Deprecated) 8 9 read-write SECURITY Flash Controller Security Settings 0x88 read-write n 0x0 0xFFFFFFFF debug_disable Debug Lockout 0 8 read-write disable_ahb_wr Disable AHB Flash Write Operations 16 20 read-write flc_settings_lock FLC Settings Lock 24 28 read-write mass_erase_lock Mass Erase Lockout 8 12 read-write security_lock Security Lock 28 32 read-write SLM Sleep Mode Register 0x17C read-write n 0x0 0xFFFFFFFF STATUS Security Status Flags 0x80 read-write n 0x0 0xFFFFFFFF auto_lock Debug Locked - Auto Lock 3 4 read-only info_block_valid Info Block Valid 30 31 read-only jtag_lock_static Debug Locked - Firmware Lockout 1 2 read-only jtag_lock_window Debug Locked - Hardware Window 0 1 read-only trim_update_done Trim Update Done 29 30 read-only TACC Flash Read Cycle Config 0x54 read-write n 0x0 0xFFFFFFFF TPROG Flash Write Cycle Config 0x58 read-write n 0x0 0xFFFFFFFF TWK_CYCL_CNT Cycle Count Tweak Register 0x174 read-write n 0x0 0xFFFFFFFF USER_OPTION Used to set DSB Access code and Auto-Lock in info block 0x100 read-write n 0x0 0xFFFFFFFF GPIO General Purpose I/O Ports (GPIO) IO 0x4000A000 0x0 0x1000 registers n GPIO0 GPIO Port 0 IRQ 15 GPIO1 GPIO Port 1 IRQ 16 GPIO2 GPIO Port 2 IRQ 17 GPIO3 GPIO Port 3 IRQ 18 GPIO4 GPIO Port 4 IRQ 19 GPIO5 GPIO Port 5 IRQ 20 GPIO6 GPIO Port 6 IRQ 21 GPIO7 GPIO Port 7 IRQ 50 GPIO8 GPIO Port 8 IRQ 51 FREE_P0 Port P0 Free for GPIO Operation Flags 0x40 read-write n 0x0 0xFFFFFFFF pin0 P0.0 GPIO Mode Acknowledge 0 1 read-only pin1 P0.1 GPIO Mode Acknowledge 1 2 read-only pin2 P0.2 GPIO Mode Acknowledge 2 3 read-only pin3 P0.3 GPIO Mode Acknowledge 3 4 read-only pin4 P0.4 GPIO Mode Acknowledge 4 5 read-only pin5 P0.5 GPIO Mode Acknowledge 5 6 read-only pin6 P0.6 GPIO Mode Acknowledge 6 7 read-only pin7 P0.7 GPIO Mode Acknowledge 7 8 read-only FREE_P1 Port P1 Free for GPIO Operation Flags 0x44 read-write n 0x0 0xFFFFFFFF pin0 P1.0 GPIO Mode Acknowledge 0 1 read-only pin1 P1.1 GPIO Mode Acknowledge 1 2 read-only pin2 P1.2 GPIO Mode Acknowledge 2 3 read-only pin3 P1.3 GPIO Mode Acknowledge 3 4 read-only pin4 P1.4 GPIO Mode Acknowledge 4 5 read-only pin5 P1.5 GPIO Mode Acknowledge 5 6 read-only pin6 P1.6 GPIO Mode Acknowledge 6 7 read-only pin7 P1.7 GPIO Mode Acknowledge 7 8 read-only FREE_P2 Port P2 Free for GPIO Operation Flags 0x48 read-write n 0x0 0xFFFFFFFF pin0 P2.0 GPIO Mode Acknowledge 0 1 read-only pin1 P2.1 GPIO Mode Acknowledge 1 2 read-only pin2 P2.2 GPIO Mode Acknowledge 2 3 read-only pin3 P2.3 GPIO Mode Acknowledge 3 4 read-only pin4 P2.4 GPIO Mode Acknowledge 4 5 read-only pin5 P2.5 GPIO Mode Acknowledge 5 6 read-only pin6 P2.6 GPIO Mode Acknowledge 6 7 read-only pin7 P2.7 GPIO Mode Acknowledge 7 8 read-only FREE_P3 Port P3 Free for GPIO Operation Flags 0x4C read-write n 0x0 0xFFFFFFFF pin0 P3.0 GPIO Mode Acknowledge 0 1 read-only pin1 P3.1 GPIO Mode Acknowledge 1 2 read-only pin2 P3.2 GPIO Mode Acknowledge 2 3 read-only pin3 P3.3 GPIO Mode Acknowledge 3 4 read-only pin4 P3.4 GPIO Mode Acknowledge 4 5 read-only pin5 P3.5 GPIO Mode Acknowledge 5 6 read-only pin6 P3.6 GPIO Mode Acknowledge 6 7 read-only pin7 P3.7 GPIO Mode Acknowledge 7 8 read-only FREE_P4 Port P4 Free for GPIO Operation Flags 0x50 read-write n 0x0 0xFFFFFFFF pin0 P4.0 GPIO Mode Acknowledge 0 1 read-only pin1 P4.1 GPIO Mode Acknowledge 1 2 read-only pin2 P4.2 GPIO Mode Acknowledge 2 3 read-only pin3 P4.3 GPIO Mode Acknowledge 3 4 read-only pin4 P4.4 GPIO Mode Acknowledge 4 5 read-only pin5 P4.5 GPIO Mode Acknowledge 5 6 read-only pin6 P4.6 GPIO Mode Acknowledge 6 7 read-only pin7 P4.7 GPIO Mode Acknowledge 7 8 read-only FREE_P5 Port P5 Free for GPIO Operation Flags 0x54 read-write n 0x0 0xFFFFFFFF pin0 P5.0 GPIO Mode Acknowledge 0 1 read-only pin1 P5.1 GPIO Mode Acknowledge 1 2 read-only pin2 P5.2 GPIO Mode Acknowledge 2 3 read-only pin3 P5.3 GPIO Mode Acknowledge 3 4 read-only pin4 P5.4 GPIO Mode Acknowledge 4 5 read-only pin5 P5.5 GPIO Mode Acknowledge 5 6 read-only pin6 P5.6 GPIO Mode Acknowledge 6 7 read-only pin7 P5.7 GPIO Mode Acknowledge 7 8 read-only FREE_P6 Port P6 Free for GPIO Operation Flags 0x58 read-write n 0x0 0xFFFFFFFF pin0 P6.0 GPIO Mode Acknowledge 0 1 read-only pin1 P6.1 GPIO Mode Acknowledge 1 2 read-only pin2 P6.2 GPIO Mode Acknowledge 2 3 read-only pin3 P6.3 GPIO Mode Acknowledge 3 4 read-only pin4 P6.4 GPIO Mode Acknowledge 4 5 read-only pin5 P6.5 GPIO Mode Acknowledge 5 6 read-only pin6 P6.6 GPIO Mode Acknowledge 6 7 read-only pin7 P6.7 GPIO Mode Acknowledge 7 8 read-only FREE_P7 Port P7 Free for GPIO Operation Flags 0x5C read-write n 0x0 0xFFFFFFFF pin0 P7.0 GPIO Mode Acknowledge 0 1 read-only pin1 P7.1 GPIO Mode Acknowledge 1 2 read-only pin2 P7.2 GPIO Mode Acknowledge 2 3 read-only pin3 P7.3 GPIO Mode Acknowledge 3 4 read-only pin4 P7.4 GPIO Mode Acknowledge 4 5 read-only pin5 P7.5 GPIO Mode Acknowledge 5 6 read-only pin6 P7.6 GPIO Mode Acknowledge 6 7 read-only pin7 P7.7 GPIO Mode Acknowledge 7 8 read-only FREE_P8 Port P8 Free for GPIO Operation Flags 0x60 read-write n 0x0 0xFFFFFFFF pin0 P8.0 GPIO Mode Acknowledge 0 1 read-only pin1 P8.1 GPIO Mode Acknowledge 1 2 read-only pin2 P8.2 GPIO Mode Acknowledge 2 3 read-only pin3 P8.3 GPIO Mode Acknowledge 3 4 read-only pin4 P8.4 GPIO Mode Acknowledge 4 5 read-only pin5 P8.5 GPIO Mode Acknowledge 5 6 read-only pin6 P8.6 GPIO Mode Acknowledge 6 7 read-only pin7 P8.7 GPIO Mode Acknowledge 7 8 read-only FUNC_SEL_P0 Port P0 GPIO Function Select 0x100 read-write n 0x0 0xFFFFFFFF pin0 P0.0 Output Function Select 0 4 read-write pin1 P0.1 Output Function Select 4 8 read-write pin2 P0.2 Output Function Select 8 12 read-write pin3 P0.3 Output Function Select 12 16 read-write pin4 P0.4 Output Function Select 16 20 read-write pin5 P0.5 Output Function Select 20 24 read-write pin6 P0.6 Output Function Select 24 28 read-write pin7 P0.7 Output Function Select 28 32 read-write FUNC_SEL_P1 Port P1 GPIO Function Select 0x104 read-write n 0x0 0xFFFFFFFF pin0 P1.0 Output Function Select 0 4 read-write pin1 P1.1 Output Function Select 4 8 read-write pin2 P1.2 Output Function Select 8 12 read-write pin3 P1.3 Output Function Select 12 16 read-write pin4 P1.4 Output Function Select 16 20 read-write pin5 P1.5 Output Function Select 20 24 read-write pin6 P1.6 Output Function Select 24 28 read-write pin7 P1.7 Output Function Select 28 32 read-write FUNC_SEL_P2 Port P2 GPIO Function Select 0x108 read-write n 0x0 0xFFFFFFFF pin0 P2.0 Output Function Select 0 4 read-write pin1 P2.1 Output Function Select 4 8 read-write pin2 P2.2 Output Function Select 8 12 read-write pin3 P2.3 Output Function Select 12 16 read-write pin4 P2.4 Output Function Select 16 20 read-write pin5 P2.5 Output Function Select 20 24 read-write pin6 P2.6 Output Function Select 24 28 read-write pin7 P2.7 Output Function Select 28 32 read-write FUNC_SEL_P3 Port P3 GPIO Function Select 0x10C read-write n 0x0 0xFFFFFFFF pin0 P3.0 Output Function Select 0 4 read-write pin1 P3.1 Output Function Select 4 8 read-write pin2 P3.2 Output Function Select 8 12 read-write pin3 P3.3 Output Function Select 12 16 read-write pin4 P3.4 Output Function Select 16 20 read-write pin5 P3.5 Output Function Select 20 24 read-write pin6 P3.6 Output Function Select 24 28 read-write pin7 P3.7 Output Function Select 28 32 read-write FUNC_SEL_P4 Port P4 GPIO Function Select 0x110 read-write n 0x0 0xFFFFFFFF pin0 P4.0 Output Function Select 0 4 read-write pin1 P4.1 Output Function Select 4 8 read-write pin2 P4.2 Output Function Select 8 12 read-write pin3 P4.3 Output Function Select 12 16 read-write pin4 P4.4 Output Function Select 16 20 read-write pin5 P4.5 Output Function Select 20 24 read-write pin6 P4.6 Output Function Select 24 28 read-write pin7 P4.7 Output Function Select 28 32 read-write FUNC_SEL_P5 Port P5 GPIO Function Select 0x114 read-write n 0x0 0xFFFFFFFF pin0 P5.0 Output Function Select 0 4 read-write pin1 P5.1 Output Function Select 4 8 read-write pin2 P5.2 Output Function Select 8 12 read-write pin3 P5.3 Output Function Select 12 16 read-write pin4 P5.4 Output Function Select 16 20 read-write pin5 P5.5 Output Function Select 20 24 read-write pin6 P5.6 Output Function Select 24 28 read-write pin7 P5.7 Output Function Select 28 32 read-write FUNC_SEL_P6 Port P6 GPIO Function Select 0x118 read-write n 0x0 0xFFFFFFFF pin0 P6.0 Output Function Select 0 4 read-write pin1 P6.1 Output Function Select 4 8 read-write pin2 P6.2 Output Function Select 8 12 read-write pin3 P6.3 Output Function Select 12 16 read-write pin4 P6.4 Output Function Select 16 20 read-write pin5 P6.5 Output Function Select 20 24 read-write pin6 P6.6 Output Function Select 24 28 read-write pin7 P6.7 Output Function Select 28 32 read-write FUNC_SEL_P7 Port P7 GPIO Function Select 0x11C read-write n 0x0 0xFFFFFFFF pin0 P7.0 Output Function Select 0 4 read-write pin1 P7.1 Output Function Select 4 8 read-write pin2 P7.2 Output Function Select 8 12 read-write pin3 P7.3 Output Function Select 12 16 read-write pin4 P7.4 Output Function Select 16 20 read-write pin5 P7.5 Output Function Select 20 24 read-write pin6 P7.6 Output Function Select 24 28 read-write pin7 P7.7 Output Function Select 28 32 read-write FUNC_SEL_P8 Port P8 GPIO Function Select 0x120 read-write n 0x0 0xFFFFFFFF pin0 P8.0 Output Function Select 0 4 read-write pin1 P8.1 Output Function Select 4 8 read-write INTEN_P0 Port P0 Interrupt Enables 0x240 read-write n 0x0 0xFFFFFFFF pin0 P0.0 External Interrupt Enable 0 1 read-write pin1 P0.1 External Interrupt Enable 1 2 read-write pin2 P0.2 External Interrupt Enable 2 3 read-write pin3 P0.3 External Interrupt Enable 3 4 read-write pin4 P0.4 External Interrupt Enable 4 5 read-write pin5 P0.5 External Interrupt Enable 5 6 read-write pin6 P0.6 External Interrupt Enable 6 7 read-write pin7 P0.7 External Interrupt Enable 7 8 read-write INTEN_P1 Port P1 Interrupt Enables 0x244 read-write n 0x0 0xFFFFFFFF pin0 P1.0 External Interrupt Enable 0 1 read-write pin1 P1.1 External Interrupt Enable 1 2 read-write pin2 P1.2 External Interrupt Enable 2 3 read-write pin3 P1.3 External Interrupt Enable 3 4 read-write pin4 P1.4 External Interrupt Enable 4 5 read-write pin5 P1.5 External Interrupt Enable 5 6 read-write pin6 P1.6 External Interrupt Enable 6 7 read-write pin7 P1.7 External Interrupt Enable 7 8 read-write INTEN_P2 Port P2 Interrupt Enables 0x248 read-write n 0x0 0xFFFFFFFF pin0 P2.0 External Interrupt Enable 0 1 read-write pin1 P2.1 External Interrupt Enable 1 2 read-write pin2 P2.2 External Interrupt Enable 2 3 read-write pin3 P2.3 External Interrupt Enable 3 4 read-write pin4 P2.4 External Interrupt Enable 4 5 read-write pin5 P2.5 External Interrupt Enable 5 6 read-write pin6 P2.6 External Interrupt Enable 6 7 read-write pin7 P2.7 External Interrupt Enable 7 8 read-write INTEN_P3 Port P3 Interrupt Enables 0x24C read-write n 0x0 0xFFFFFFFF pin0 P3.0 External Interrupt Enable 0 1 read-write pin1 P3.1 External Interrupt Enable 1 2 read-write pin2 P3.2 External Interrupt Enable 2 3 read-write pin3 P3.3 External Interrupt Enable 3 4 read-write pin4 P3.4 External Interrupt Enable 4 5 read-write pin5 P3.5 External Interrupt Enable 5 6 read-write pin6 P3.6 External Interrupt Enable 6 7 read-write pin7 P3.7 External Interrupt Enable 7 8 read-write INTEN_P4 Port P4 Interrupt Enables 0x250 read-write n 0x0 0xFFFFFFFF pin0 P4.0 External Interrupt Enable 0 1 read-write pin1 P4.1 External Interrupt Enable 1 2 read-write pin2 P4.2 External Interrupt Enable 2 3 read-write pin3 P4.3 External Interrupt Enable 3 4 read-write pin4 P4.4 External Interrupt Enable 4 5 read-write pin5 P4.5 External Interrupt Enable 5 6 read-write pin6 P4.6 External Interrupt Enable 6 7 read-write pin7 P4.7 External Interrupt Enable 7 8 read-write INTEN_P5 Port P5 Interrupt Enables 0x254 read-write n 0x0 0xFFFFFFFF pin0 P5.0 External Interrupt Enable 0 1 read-write pin1 P5.1 External Interrupt Enable 1 2 read-write pin2 P5.2 External Interrupt Enable 2 3 read-write pin3 P5.3 External Interrupt Enable 3 4 read-write pin4 P5.4 External Interrupt Enable 4 5 read-write pin5 P5.5 External Interrupt Enable 5 6 read-write pin6 P5.6 External Interrupt Enable 6 7 read-write pin7 P5.7 External Interrupt Enable 7 8 read-write INTEN_P6 Port P6 Interrupt Enables 0x258 read-write n 0x0 0xFFFFFFFF pin0 P6.0 External Interrupt Enable 0 1 read-write pin1 P6.1 External Interrupt Enable 1 2 read-write pin2 P6.2 External Interrupt Enable 2 3 read-write pin3 P6.3 External Interrupt Enable 3 4 read-write pin4 P6.4 External Interrupt Enable 4 5 read-write pin5 P6.5 External Interrupt Enable 5 6 read-write pin6 P6.6 External Interrupt Enable 6 7 read-write pin7 P6.7 External Interrupt Enable 7 8 read-write INTEN_P7 Port P7 Interrupt Enables 0x25C read-write n 0x0 0xFFFFFFFF pin0 P7.0 External Interrupt Enable 0 1 read-write pin1 P7.1 External Interrupt Enable 1 2 read-write pin2 P7.2 External Interrupt Enable 2 3 read-write pin3 P7.3 External Interrupt Enable 3 4 read-write pin4 P7.4 External Interrupt Enable 4 5 read-write pin5 P7.5 External Interrupt Enable 5 6 read-write pin6 P7.6 External Interrupt Enable 6 7 read-write pin7 P7.7 External Interrupt Enable 7 8 read-write INTEN_P8 Port P8 Interrupt Enables 0x260 read-write n 0x0 0xFFFFFFFF pin0 P8.0 External Interrupt Enable 0 1 read-write pin1 P8.1 External Interrupt Enable 1 2 read-write pin2 P8.2 External Interrupt Enable 2 3 read-write pin3 P8.3 External Interrupt Enable 3 4 read-write pin4 P8.4 External Interrupt Enable 4 5 read-write pin5 P8.5 External Interrupt Enable 5 6 read-write pin6 P8.6 External Interrupt Enable 6 7 read-write pin7 P8.7 External Interrupt Enable 7 8 read-write INTFL_P0 Port P0 Interrupt Flags 0x200 read-write n 0x0 0xFFFFFFFF pin0 P0.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P0.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P0.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P0.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P0.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P0.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P0.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P0.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P1 Port P1 Interrupt Flags 0x204 read-write n 0x0 0xFFFFFFFF pin0 P1.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P1.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P1.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P1.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P1.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P1.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P1.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P1.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P2 Port P2 Interrupt Flags 0x208 read-write n 0x0 0xFFFFFFFF pin0 P2.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P2.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P2.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P2.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P2.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P2.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P2.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P2.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P3 Port P3 Interrupt Flags 0x20C read-write n 0x0 0xFFFFFFFF pin0 P3.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P3.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P3.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P3.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P3.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P3.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P3.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P3.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P4 Port P4 Interrupt Flags 0x210 read-write n 0x0 0xFFFFFFFF pin0 P4.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P4.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P4.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P4.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P4.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P4.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P4.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P4.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P5 Port P5 Interrupt Flags 0x214 read-write n 0x0 0xFFFFFFFF pin0 P5.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P5.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P5.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P5.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P5.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P5.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P5.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P5.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P6 Port P6 Interrupt Flags 0x218 read-write n 0x0 0xFFFFFFFF pin0 P6.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P6.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P6.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P6.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P6.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P6.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P6.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P6.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P7 Port P7 Interrupt Flags 0x21C read-write n 0x0 0xFFFFFFFF pin0 P7.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P7.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P7.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P7.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P7.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P7.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P7.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P7.7 External Interrupt Flags 7 8 read-write oneToClear INTFL_P8 Port P8 Interrupt Flags 0x220 read-write n 0x0 0xFFFFFFFF pin0 P8.0 External Interrupt Flags 0 1 read-write oneToClear pin1 P8.1 External Interrupt Flags 1 2 read-write oneToClear pin2 P8.2 External Interrupt Flags 2 3 read-write oneToClear pin3 P8.3 External Interrupt Flags 3 4 read-write oneToClear pin4 P8.4 External Interrupt Flags 4 5 read-write oneToClear pin5 P8.5 External Interrupt Flags 5 6 read-write oneToClear pin6 P8.6 External Interrupt Flags 6 7 read-write oneToClear pin7 P8.7 External Interrupt Flags 7 8 read-write oneToClear INT_MODE_P0 Port P0 Interrupt Detection Mode 0x1C0 read-write n 0x0 0xFFFFFFFF pin0 P0.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P0.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P0.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P0.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P0.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P0.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P0.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P0.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P1 Port P1 Interrupt Detection Mode 0x1C4 read-write n 0x0 0xFFFFFFFF pin0 P1.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P1.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P1.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P1.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P1.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P1.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P1.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P1.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P2 Port P2 Interrupt Detection Mode 0x1C8 read-write n 0x0 0xFFFFFFFF pin0 P2.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P2.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P2.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P2.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P2.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P2.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P2.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P2.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P3 Port P3 Interrupt Detection Mode 0x1CC read-write n 0x0 0xFFFFFFFF pin0 P3.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P3.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P3.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P3.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P3.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P3.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P3.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P3.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P4 Port P4 Interrupt Detection Mode 0x1D0 read-write n 0x0 0xFFFFFFFF pin0 P4.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P4.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P4.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P4.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P4.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P4.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P4.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P4.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P5 Port P5 Interrupt Detection Mode 0x1D4 read-write n 0x0 0xFFFFFFFF pin0 P5.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P5.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P5.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P5.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P5.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P5.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P5.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P5.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P6 Port P6 Interrupt Detection Mode 0x1D8 read-write n 0x0 0xFFFFFFFF pin0 P6.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P6.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P6.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P6.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P6.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P6.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P6.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P6.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P7 Port P7 Interrupt Detection Mode 0x1DC read-write n 0x0 0xFFFFFFFF pin0 P7.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P7.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P7.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P7.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P7.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P7.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P7.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P7.7 GPIO Interrupt Detection Mode 28 31 read-write INT_MODE_P8 Port P8 Interrupt Detection Mode 0x1E0 read-write n 0x0 0xFFFFFFFF pin0 P8.0 GPIO Interrupt Detection Mode 0 3 read-write pin1 P8.1 GPIO Interrupt Detection Mode 4 7 read-write pin2 P8.2 GPIO Interrupt Detection Mode 8 11 read-write pin3 P8.3 GPIO Interrupt Detection Mode 12 15 read-write pin4 P8.4 GPIO Interrupt Detection Mode 16 19 read-write pin5 P8.5 GPIO Interrupt Detection Mode 20 23 read-write pin6 P8.6 GPIO Interrupt Detection Mode 24 27 read-write pin7 P8.7 GPIO Interrupt Detection Mode 28 31 read-write IN_MODE_P0 Port P0 GPIO Input Monitoring Mode 0x140 read-write n 0x0 0xFFFFFFFF pin0 P0.0 Input Monitoring Mode 0 2 read-write pin1 P0.1 Input Monitoring Mode 4 6 read-write pin2 P0.2 Input Monitoring Mode 8 10 read-write pin3 P0.3 Input Monitoring Mode 12 14 read-write pin4 P0.4 Input Monitoring Mode 16 18 read-write pin5 P0.5 Input Monitoring Mode 20 22 read-write pin6 P0.6 Input Monitoring Mode 24 26 read-write pin7 P0.7 Input Monitoring Mode 28 30 read-write IN_MODE_P1 Port P1 GPIO Input Monitoring Mode 0x144 read-write n 0x0 0xFFFFFFFF pin0 P1.0 Input Monitoring Mode 0 2 read-write pin1 P1.1 Input Monitoring Mode 4 6 read-write pin2 P1.2 Input Monitoring Mode 8 10 read-write pin3 P1.3 Input Monitoring Mode 12 14 read-write pin4 P1.4 Input Monitoring Mode 16 18 read-write pin5 P1.5 Input Monitoring Mode 20 22 read-write pin6 P1.6 Input Monitoring Mode 24 26 read-write pin7 P1.7 Input Monitoring Mode 28 30 read-write IN_MODE_P2 Port P2 GPIO Input Monitoring Mode 0x148 read-write n 0x0 0xFFFFFFFF pin0 P2.0 Input Monitoring Mode 0 2 read-write pin1 P2.1 Input Monitoring Mode 4 6 read-write pin2 P2.2 Input Monitoring Mode 8 10 read-write pin3 P2.3 Input Monitoring Mode 12 14 read-write pin4 P2.4 Input Monitoring Mode 16 18 read-write pin5 P2.5 Input Monitoring Mode 20 22 read-write pin6 P2.6 Input Monitoring Mode 24 26 read-write pin7 P2.7 Input Monitoring Mode 28 30 read-write IN_MODE_P3 Port P3 GPIO Input Monitoring Mode 0x14C read-write n 0x0 0xFFFFFFFF pin0 P3.0 Input Monitoring Mode 0 2 read-write pin1 P3.1 Input Monitoring Mode 4 6 read-write pin2 P3.2 Input Monitoring Mode 8 10 read-write pin3 P3.3 Input Monitoring Mode 12 14 read-write pin4 P3.4 Input Monitoring Mode 16 18 read-write pin5 P3.5 Input Monitoring Mode 20 22 read-write pin6 P3.6 Input Monitoring Mode 24 26 read-write pin7 P3.7 Input Monitoring Mode 28 30 read-write IN_MODE_P4 Port P4 GPIO Input Monitoring Mode 0x150 read-write n 0x0 0xFFFFFFFF pin0 P4.0 Input Monitoring Mode 0 2 read-write pin1 P4.1 Input Monitoring Mode 4 6 read-write pin2 P4.2 Input Monitoring Mode 8 10 read-write pin3 P4.3 Input Monitoring Mode 12 14 read-write pin4 P4.4 Input Monitoring Mode 16 18 read-write pin5 P4.5 Input Monitoring Mode 20 22 read-write pin6 P4.6 Input Monitoring Mode 24 26 read-write pin7 P4.7 Input Monitoring Mode 28 30 read-write IN_MODE_P5 Port P5 GPIO Input Monitoring Mode 0x154 read-write n 0x0 0xFFFFFFFF pin0 P5.0 Input Monitoring Mode 0 2 read-write pin1 P5.1 Input Monitoring Mode 4 6 read-write pin2 P5.2 Input Monitoring Mode 8 10 read-write pin3 P5.3 Input Monitoring Mode 12 14 read-write pin4 P5.4 Input Monitoring Mode 16 18 read-write pin5 P5.5 Input Monitoring Mode 20 22 read-write pin6 P5.6 Input Monitoring Mode 24 26 read-write pin7 P5.7 Input Monitoring Mode 28 30 read-write IN_MODE_P6 Port P6 GPIO Input Monitoring Mode 0x158 read-write n 0x0 0xFFFFFFFF pin0 P6.0 Input Monitoring Mode 0 2 read-write pin1 P6.1 Input Monitoring Mode 4 6 read-write pin2 P6.2 Input Monitoring Mode 8 10 read-write pin3 P6.3 Input Monitoring Mode 12 14 read-write pin4 P6.4 Input Monitoring Mode 16 18 read-write pin5 P6.5 Input Monitoring Mode 20 22 read-write pin6 P6.6 Input Monitoring Mode 24 26 read-write pin7 P6.7 Input Monitoring Mode 28 30 read-write IN_MODE_P7 Port P7 GPIO Input Monitoring Mode 0x15C read-write n 0x0 0xFFFFFFFF pin0 P7.0 Input Monitoring Mode 0 2 read-write pin1 P7.1 Input Monitoring Mode 4 6 read-write pin2 P7.2 Input Monitoring Mode 8 10 read-write pin3 P7.3 Input Monitoring Mode 12 14 read-write pin4 P7.4 Input Monitoring Mode 16 18 read-write pin5 P7.5 Input Monitoring Mode 20 22 read-write pin6 P7.6 Input Monitoring Mode 24 26 read-write pin7 P7.7 Input Monitoring Mode 28 30 read-write IN_MODE_P8 Port P8 GPIO Input Monitoring Mode 0x160 read-write n 0x0 0xFFFFFFFF pin0 P8.0 Input Monitoring Mode 0 2 read-write pin1 P8.1 Input Monitoring Mode 4 6 read-write pin2 P8.2 Input Monitoring Mode 8 10 read-write pin3 P8.3 Input Monitoring Mode 12 14 read-write pin4 P8.4 Input Monitoring Mode 16 18 read-write pin5 P8.5 Input Monitoring Mode 20 22 read-write pin6 P8.6 Input Monitoring Mode 24 26 read-write pin7 P8.7 Input Monitoring Mode 28 30 read-write IN_VAL_P0 Port P0 GPIO Input Value 0x180 read-write n 0x0 0xFFFFFFFF pin0 P0.0 Input Value 0 1 read-only pin1 P0.1 Input Value 1 2 read-only pin2 P0.2 Input Value 2 3 read-only pin3 P0.3 Input Value 3 4 read-only pin4 P0.4 Input Value 4 5 read-only pin5 P0.5 Input Value 5 6 read-only pin6 P0.6 Input Value 6 7 read-only pin7 P0.7 Input Value 7 8 read-only IN_VAL_P1 Port P1 GPIO Input Value 0x184 read-write n 0x0 0xFFFFFFFF pin0 P1.0 Input Value 0 1 read-only pin1 P1.1 Input Value 1 2 read-only pin2 P1.2 Input Value 2 3 read-only pin3 P1.3 Input Value 3 4 read-only pin4 P1.4 Input Value 4 5 read-only pin5 P1.5 Input Value 5 6 read-only pin6 P1.6 Input Value 6 7 read-only pin7 P1.7 Input Value 7 8 read-only IN_VAL_P2 Port P2 GPIO Input Value 0x188 read-write n 0x0 0xFFFFFFFF pin0 P2.0 Input Value 0 1 read-only pin1 P2.1 Input Value 1 2 read-only pin2 P2.2 Input Value 2 3 read-only pin3 P2.3 Input Value 3 4 read-only pin4 P2.4 Input Value 4 5 read-only pin5 P2.5 Input Value 5 6 read-only pin6 P2.6 Input Value 6 7 read-only pin7 P2.7 Input Value 7 8 read-only IN_VAL_P3 Port P3 GPIO Input Value 0x18C read-write n 0x0 0xFFFFFFFF pin0 P3.0 Input Value 0 1 read-only pin1 P3.1 Input Value 1 2 read-only pin2 P3.2 Input Value 2 3 read-only pin3 P3.3 Input Value 3 4 read-only pin4 P3.4 Input Value 4 5 read-only pin5 P3.5 Input Value 5 6 read-only pin6 P3.6 Input Value 6 7 read-only pin7 P3.7 Input Value 7 8 read-only IN_VAL_P4 Port P4 GPIO Input Value 0x190 read-write n 0x0 0xFFFFFFFF pin0 P4.0 Input Value 0 1 read-only pin1 P4.1 Input Value 1 2 read-only pin2 P4.2 Input Value 2 3 read-only pin3 P4.3 Input Value 3 4 read-only pin4 P4.4 Input Value 4 5 read-only pin5 P4.5 Input Value 5 6 read-only pin6 P4.6 Input Value 6 7 read-only pin7 P4.7 Input Value 7 8 read-only IN_VAL_P5 Port P5 GPIO Input Value 0x194 read-write n 0x0 0xFFFFFFFF pin0 P5.0 Input Value 0 1 read-only pin1 P5.1 Input Value 1 2 read-only pin2 P5.2 Input Value 2 3 read-only pin3 P5.3 Input Value 3 4 read-only pin4 P5.4 Input Value 4 5 read-only pin5 P5.5 Input Value 5 6 read-only pin6 P5.6 Input Value 6 7 read-only pin7 P5.7 Input Value 7 8 read-only IN_VAL_P6 Port P6 GPIO Input Value 0x198 read-write n 0x0 0xFFFFFFFF pin0 P6.0 Input Value 0 1 read-only pin1 P6.1 Input Value 1 2 read-only pin2 P6.2 Input Value 2 3 read-only pin3 P6.3 Input Value 3 4 read-only pin4 P6.4 Input Value 4 5 read-only pin5 P6.5 Input Value 5 6 read-only pin6 P6.6 Input Value 6 7 read-only pin7 P6.7 Input Value 7 8 read-only IN_VAL_P7 Port P7 GPIO Input Value 0x19C read-write n 0x0 0xFFFFFFFF pin0 P7.0 Input Value 0 1 read-only pin1 P7.1 Input Value 1 2 read-only pin2 P7.2 Input Value 2 3 read-only pin3 P7.3 Input Value 3 4 read-only pin4 P7.4 Input Value 4 5 read-only pin5 P7.5 Input Value 5 6 read-only pin6 P7.6 Input Value 6 7 read-only pin7 P7.7 Input Value 7 8 read-only IN_VAL_P8 Port P8 GPIO Input Value 0x1A0 read-write n 0x0 0xFFFFFFFF pin0 P8.0 Input Value 0 1 read-only pin1 P8.1 Input Value 1 2 read-only pin2 P8.2 Input Value 2 3 read-only pin3 P8.3 Input Value 3 4 read-only pin4 P8.4 Input Value 4 5 read-only pin5 P8.5 Input Value 5 6 read-only pin6 P8.6 Input Value 6 7 read-only pin7 P8.7 Input Value 7 8 read-only OUT_MODE_P0 Port P0 GPIO Output Drive Mode 0x80 read-write n 0x0 0xFFFFFFFF pin0 P0.0 Output Drive Mode 0 4 read-write pin1 P0.1 Output Drive Mode 4 8 read-write pin2 P0.2 Output Drive Mode 8 12 read-write pin3 P0.3 Output Drive Mode 12 16 read-write pin4 P0.4 Output Drive Mode 16 20 read-write pin5 P0.5 Output Drive Mode 20 24 read-write pin6 P0.6 Output Drive Mode 24 28 read-write pin7 P0.7 Output Drive Mode 28 32 read-write OUT_MODE_P1 Port P1 GPIO Output Drive Mode 0x84 read-write n 0x0 0xFFFFFFFF pin0 P1.0 Output Drive Mode 0 4 read-write pin1 P1.1 Output Drive Mode 4 8 read-write pin2 P1.2 Output Drive Mode 8 12 read-write pin3 P1.3 Output Drive Mode 12 16 read-write pin4 P1.4 Output Drive Mode 16 20 read-write pin5 P1.5 Output Drive Mode 20 24 read-write pin6 P1.6 Output Drive Mode 24 28 read-write pin7 P1.7 Output Drive Mode 28 32 read-write OUT_MODE_P2 Port P2 GPIO Output Drive Mode 0x88 read-write n 0x0 0xFFFFFFFF pin0 P2.0 Output Drive Mode 0 4 read-write pin1 P2.1 Output Drive Mode 4 8 read-write pin2 P2.2 Output Drive Mode 8 12 read-write pin3 P2.3 Output Drive Mode 12 16 read-write pin4 P2.4 Output Drive Mode 16 20 read-write pin5 P2.5 Output Drive Mode 20 24 read-write pin6 P2.6 Output Drive Mode 24 28 read-write pin7 P2.7 Output Drive Mode 28 32 read-write OUT_MODE_P3 Port P3 GPIO Output Drive Mode 0x8C read-write n 0x0 0xFFFFFFFF pin0 P3.0 Output Drive Mode 0 4 read-write pin1 P3.1 Output Drive Mode 4 8 read-write pin2 P3.2 Output Drive Mode 8 12 read-write pin3 P3.3 Output Drive Mode 12 16 read-write pin4 P3.4 Output Drive Mode 16 20 read-write pin5 P3.5 Output Drive Mode 20 24 read-write pin6 P3.6 Output Drive Mode 24 28 read-write pin7 P3.7 Output Drive Mode 28 32 read-write OUT_MODE_P4 Port P4 GPIO Output Drive Mode 0x90 read-write n 0x0 0xFFFFFFFF pin0 P4.0 Output Drive Mode 0 4 read-write pin1 P4.1 Output Drive Mode 4 8 read-write pin2 P4.2 Output Drive Mode 8 12 read-write pin3 P4.3 Output Drive Mode 12 16 read-write pin4 P4.4 Output Drive Mode 16 20 read-write pin5 P4.5 Output Drive Mode 20 24 read-write pin6 P4.6 Output Drive Mode 24 28 read-write pin7 P4.7 Output Drive Mode 28 32 read-write OUT_MODE_P5 Port P5 GPIO Output Drive Mode 0x94 read-write n 0x0 0xFFFFFFFF pin0 P5.0 Output Drive Mode 0 4 read-write pin1 P5.1 Output Drive Mode 4 8 read-write pin2 P5.2 Output Drive Mode 8 12 read-write pin3 P5.3 Output Drive Mode 12 16 read-write pin4 P5.4 Output Drive Mode 16 20 read-write pin5 P5.5 Output Drive Mode 20 24 read-write pin6 P5.6 Output Drive Mode 24 28 read-write pin7 P5.7 Output Drive Mode 28 32 read-write OUT_MODE_P6 Port P6 GPIO Output Drive Mode 0x98 read-write n 0x0 0xFFFFFFFF pin0 P6.0 Output Drive Mode 0 4 read-write pin1 P6.1 Output Drive Mode 4 8 read-write pin2 P6.2 Output Drive Mode 8 12 read-write pin3 P6.3 Output Drive Mode 12 16 read-write pin4 P6.4 Output Drive Mode 16 20 read-write pin5 P6.5 Output Drive Mode 20 24 read-write pin6 P6.6 Output Drive Mode 24 28 read-write pin7 P6.7 Output Drive Mode 28 32 read-write OUT_MODE_P7 Port P7 GPIO Output Drive Mode 0x9C read-write n 0x0 0xFFFFFFFF pin0 P7.0 Output Drive Mode 0 4 read-write pin1 P7.1 Output Drive Mode 4 8 read-write pin2 P7.2 Output Drive Mode 8 12 read-write pin3 P7.3 Output Drive Mode 12 16 read-write pin4 P7.4 Output Drive Mode 16 20 read-write pin5 P7.5 Output Drive Mode 20 24 read-write pin6 P7.6 Output Drive Mode 24 28 read-write pin7 P7.7 Output Drive Mode 28 32 read-write OUT_MODE_P8 Port P8 GPIO Output Drive Mode 0xA0 read-write n 0x0 0xFFFFFFFF pin0 P8.0 Output Drive Mode 0 4 read-write pin1 P8.1 Output Drive Mode 4 8 read-write pin2 P8.2 Output Drive Mode 8 12 read-write pin3 P8.3 Output Drive Mode 12 16 read-write pin4 P8.4 Output Drive Mode 16 20 read-write pin5 P8.5 Output Drive Mode 20 24 read-write pin6 P8.6 Output Drive Mode 24 28 read-write pin7 P8.7 Output Drive Mode 28 32 read-write OUT_VAL_P0 Port P0 GPIO Output Value 0xC0 read-write n 0x0 0xFFFFFFFF pin0 P0.0 GPIO Output Drive Value 0 1 read-write pin1 P0.1 GPIO Output Drive Value 1 2 read-write pin2 P0.2 GPIO Output Drive Value 2 3 read-write pin3 P0.3 GPIO Output Drive Value 3 4 read-write pin4 P0.4 GPIO Output Drive Value 4 5 read-write pin5 P0.5 GPIO Output Drive Value 5 6 read-write pin6 P0.6 GPIO Output Drive Value 6 7 read-write pin7 P0.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P1 Port P1 GPIO Output Value 0xC4 read-write n 0x0 0xFFFFFFFF pin0 P1.0 GPIO Output Drive Value 0 1 read-write pin1 P1.1 GPIO Output Drive Value 1 2 read-write pin2 P1.2 GPIO Output Drive Value 2 3 read-write pin3 P1.3 GPIO Output Drive Value 3 4 read-write pin4 P1.4 GPIO Output Drive Value 4 5 read-write pin5 P1.5 GPIO Output Drive Value 5 6 read-write pin6 P1.6 GPIO Output Drive Value 6 7 read-write pin7 P1.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P2 Port P2 GPIO Output Value 0xC8 read-write n 0x0 0xFFFFFFFF pin0 P2.0 GPIO Output Drive Value 0 1 read-write pin1 P2.1 GPIO Output Drive Value 1 2 read-write pin2 P2.2 GPIO Output Drive Value 2 3 read-write pin3 P2.3 GPIO Output Drive Value 3 4 read-write pin4 P2.4 GPIO Output Drive Value 4 5 read-write pin5 P2.5 GPIO Output Drive Value 5 6 read-write pin6 P2.6 GPIO Output Drive Value 6 7 read-write pin7 P2.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P3 Port P3 GPIO Output Value 0xCC read-write n 0x0 0xFFFFFFFF pin0 P3.0 GPIO Output Drive Value 0 1 read-write pin1 P3.1 GPIO Output Drive Value 1 2 read-write pin2 P3.2 GPIO Output Drive Value 2 3 read-write pin3 P3.3 GPIO Output Drive Value 3 4 read-write pin4 P3.4 GPIO Output Drive Value 4 5 read-write pin5 P3.5 GPIO Output Drive Value 5 6 read-write pin6 P3.6 GPIO Output Drive Value 6 7 read-write pin7 P3.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P4 Port P4 GPIO Output Value 0xD0 read-write n 0x0 0xFFFFFFFF pin0 P4.0 GPIO Output Drive Value 0 1 read-write pin1 P4.1 GPIO Output Drive Value 1 2 read-write pin2 P4.2 GPIO Output Drive Value 2 3 read-write pin3 P4.3 GPIO Output Drive Value 3 4 read-write pin4 P4.4 GPIO Output Drive Value 4 5 read-write pin5 P4.5 GPIO Output Drive Value 5 6 read-write pin6 P4.6 GPIO Output Drive Value 6 7 read-write pin7 P4.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P5 Port P5 GPIO Output Value 0xD4 read-write n 0x0 0xFFFFFFFF pin0 P5.0 GPIO Output Drive Value 0 1 read-write pin1 P5.1 GPIO Output Drive Value 1 2 read-write pin2 P5.2 GPIO Output Drive Value 2 3 read-write pin3 P5.3 GPIO Output Drive Value 3 4 read-write pin4 P5.4 GPIO Output Drive Value 4 5 read-write pin5 P5.5 GPIO Output Drive Value 5 6 read-write pin6 P5.6 GPIO Output Drive Value 6 7 read-write pin7 P5.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P6 Port P6 GPIO Output Value 0xD8 read-write n 0x0 0xFFFFFFFF pin0 P6.0 GPIO Output Drive Value 0 1 read-write pin1 P6.1 GPIO Output Drive Value 1 2 read-write pin2 P6.2 GPIO Output Drive Value 2 3 read-write pin3 P6.3 GPIO Output Drive Value 3 4 read-write pin4 P6.4 GPIO Output Drive Value 4 5 read-write pin5 P6.5 GPIO Output Drive Value 5 6 read-write pin6 P6.6 GPIO Output Drive Value 6 7 read-write pin7 P6.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P7 Port P7 GPIO Output Value 0xDC read-write n 0x0 0xFFFFFFFF pin0 P7.0 GPIO Output Drive Value 0 1 read-write pin1 P7.1 GPIO Output Drive Value 1 2 read-write pin2 P7.2 GPIO Output Drive Value 2 3 read-write pin3 P7.3 GPIO Output Drive Value 3 4 read-write pin4 P7.4 GPIO Output Drive Value 4 5 read-write pin5 P7.5 GPIO Output Drive Value 5 6 read-write pin6 P7.6 GPIO Output Drive Value 6 7 read-write pin7 P7.7 GPIO Output Drive Value 7 8 read-write OUT_VAL_P8 Port P8 GPIO Output Value 0xE0 read-write n 0x0 0xFFFFFFFF pin0 P8.0 GPIO Output Drive Value 0 1 read-write pin1 P8.1 GPIO Output Drive Value 1 2 read-write pin2 P8.2 GPIO Output Drive Value 2 3 read-write pin3 P8.3 GPIO Output Drive Value 3 4 read-write pin4 P8.4 GPIO Output Drive Value 4 5 read-write pin5 P8.5 GPIO Output Drive Value 5 6 read-write pin6 P8.6 GPIO Output Drive Value 6 7 read-write pin7 P8.7 GPIO Output Drive Value 7 8 read-write RST_MODE_P0 Port P0 Default (Power-On Reset) Output Drive Mode 0x0 read-write n 0x0 0xFFFFFFFF pin0 P0.0 Default Output Drive Mode 0 3 read-write pin1 P0.1 Default Output Drive Mode 4 7 read-write pin2 P0.2 Default Output Drive Mode 8 11 read-write pin3 P0.3 Default Output Drive Mode 12 15 read-write pin4 P0.4 Default Output Drive Mode 16 19 read-write pin5 P0.5 Default Output Drive Mode 20 23 read-write pin6 P0.6 Default Output Drive Mode 24 27 read-write pin7 P0.7 Default Output Drive Mode 28 31 read-write RST_MODE_P1 Port P1 Default (Power-On Reset) Output Drive Mode 0x4 read-write n 0x0 0xFFFFFFFF pin0 P1.0 Default Output Drive Mode 0 3 read-write pin1 P1.1 Default Output Drive Mode 4 7 read-write pin2 P1.2 Default Output Drive Mode 8 11 read-write pin3 P1.3 Default Output Drive Mode 12 15 read-write pin4 P1.4 Default Output Drive Mode 16 19 read-write pin5 P1.5 Default Output Drive Mode 20 23 read-write pin6 P1.6 Default Output Drive Mode 24 27 read-write pin7 P1.7 Default Output Drive Mode 28 31 read-write RST_MODE_P2 Port P2 Default (Power-On Reset) Output Drive Mode 0x8 read-write n 0x0 0xFFFFFFFF pin0 P2.0 Default Output Drive Mode 0 3 read-write pin1 P2.1 Default Output Drive Mode 4 7 read-write pin2 P2.2 Default Output Drive Mode 8 11 read-write pin3 P2.3 Default Output Drive Mode 12 15 read-write pin4 P2.4 Default Output Drive Mode 16 19 read-write pin5 P2.5 Default Output Drive Mode 20 23 read-write pin6 P2.6 Default Output Drive Mode 24 27 read-write pin7 P2.7 Default Output Drive Mode 28 31 read-write RST_MODE_P3 Port P3 Default (Power-On Reset) Output Drive Mode 0xC read-write n 0x0 0xFFFFFFFF pin0 P3.0 Default Output Drive Mode 0 3 read-write pin1 P3.1 Default Output Drive Mode 4 7 read-write pin2 P3.2 Default Output Drive Mode 8 11 read-write pin3 P3.3 Default Output Drive Mode 12 15 read-write pin4 P3.4 Default Output Drive Mode 16 19 read-write pin5 P3.5 Default Output Drive Mode 20 23 read-write pin6 P3.6 Default Output Drive Mode 24 27 read-write pin7 P3.7 Default Output Drive Mode 28 31 read-write RST_MODE_P4 Port P4 Default (Power-On Reset) Output Drive Mode 0x10 read-write n 0x0 0xFFFFFFFF pin0 P4.0 Default Output Drive Mode 0 3 read-write pin1 P4.1 Default Output Drive Mode 4 7 read-write pin2 P4.2 Default Output Drive Mode 8 11 read-write pin3 P4.3 Default Output Drive Mode 12 15 read-write pin4 P4.4 Default Output Drive Mode 16 19 read-write pin5 P4.5 Default Output Drive Mode 20 23 read-write pin6 P4.6 Default Output Drive Mode 24 27 read-write pin7 P4.7 Default Output Drive Mode 28 31 read-write RST_MODE_P5 Port P5 Default (Power-On Reset) Output Drive Mode 0x14 read-write n 0x0 0xFFFFFFFF pin0 P5.0 Default Output Drive Mode 0 3 read-write pin1 P5.1 Default Output Drive Mode 4 7 read-write pin2 P5.2 Default Output Drive Mode 8 11 read-write pin3 P5.3 Default Output Drive Mode 12 15 read-write pin4 P5.4 Default Output Drive Mode 16 19 read-write pin5 P5.5 Default Output Drive Mode 20 23 read-write pin6 P5.6 Default Output Drive Mode 24 27 read-write pin7 P5.7 Default Output Drive Mode 28 31 read-write RST_MODE_P6 Port P6 Default (Power-On Reset) Output Drive Mode 0x18 read-write n 0x0 0xFFFFFFFF pin0 P6.0 Default Output Drive Mode 0 3 read-write pin1 P6.1 Default Output Drive Mode 4 7 read-write pin2 P6.2 Default Output Drive Mode 8 11 read-write pin3 P6.3 Default Output Drive Mode 12 15 read-write pin4 P6.4 Default Output Drive Mode 16 19 read-write pin5 P6.5 Default Output Drive Mode 20 23 read-write pin6 P6.6 Default Output Drive Mode 24 27 read-write pin7 P6.7 Default Output Drive Mode 28 31 read-write RST_MODE_P7 Port P7 Default (Power-On Reset) Output Drive Mode 0x1C read-write n 0x0 0xFFFFFFFF pin0 P7.0 Default Output Drive Mode 0 3 read-write pin1 P7.1 Default Output Drive Mode 4 7 read-write pin2 P7.2 Default Output Drive Mode 8 11 read-write pin3 P7.3 Default Output Drive Mode 12 15 read-write pin4 P7.4 Default Output Drive Mode 16 19 read-write pin5 P7.5 Default Output Drive Mode 20 23 read-write pin6 P7.6 Default Output Drive Mode 24 27 read-write pin7 P7.7 Default Output Drive Mode 28 31 read-write RST_MODE_P8 Port P8 Default (Power-On Reset) Output Drive Mode 0x20 read-write n 0x0 0xFFFFFFFF pin0 P8.0 Default Output Drive Mode 0 3 read-write pin1 P8.1 Default Output Drive Mode 4 7 read-write pin2 P8.2 Default Output Drive Mode 8 11 read-write pin3 P8.3 Default Output Drive Mode 12 15 read-write pin4 P8.4 Default Output Drive Mode 16 19 read-write pin5 P8.5 Default Output Drive Mode 20 23 read-write pin6 P8.6 Default Output Drive Mode 24 27 read-write pin7 P8.7 Default Output Drive Mode 28 31 read-write I2CM0 I2C Master 0 Interface I2C Master 0x40016000 0x0 0x1000 registers n I2CM0 I2C Master 0 IRQ 39 BB Bit-Bang Control Register 0x28 read-write n 0x0 0xFFFFFFFF bb_scl_in_val Bit Bang SCL Input Value 2 3 read-only bb_scl_out Bit Bang SCL Output 0 1 read-write bb_sda_in_val Bit Bang SCL Input Value 3 4 read-only bb_sda_out Bit Bang SDA Output 1 2 read-write rx_fifo_cnt Results FIFO Data Received Count 16 21 read-only CTRL I2C Master Control Register 0x10 read-write n 0x0 0xFFFFFFFF mstr_reset_en Master Reset 7 8 read-write rx_fifo_en Master Results FIFO Enable 3 4 read-write tx_fifo_en Master Transaction FIFO Enable 2 3 read-write FS_CLK_DIV Full Speed SCL Clock Settings 0x0 read-write n 0x0 0xFFFFFFFF fs_filter_clk_div Full Speed Filter Clock Divisor 0 8 read-write fs_scl_hi_cnt Full Speed SCL High Count 20 32 read-write fs_scl_lo_cnt Full Speed SCL Low Count 8 20 read-write INTEN Interrupt Enable/Disable Controls 0x1C read-write n 0x0 0xFFFFFFFF rx_fifo_2q_full Results FIFO 2Q Full Int Enable 7 8 read-write rx_fifo_3q_full Results FIFO 3Q Full Int Enable 8 9 read-write rx_fifo_full Results FIFO Full Int Enable 9 10 read-write rx_fifo_not_empty Results FIFO Not Empty Int Enable 6 7 read-write tx_done Transaction Done Int Enable 0 1 read-write tx_fifo_3q_empty Transaction FIFO 3Q Empty Int Enable 5 6 read-write tx_fifo_empty Transaction FIFO Empty Int Enable 4 5 read-write tx_lost_arbitr Transaction Lost Arbitration IntEnable 2 3 read-write tx_nacked Transaction NACKed Int Enable 1 2 read-write tx_timeout Transaction Timed Out Int Enable 3 4 read-write INTFL Interrupt Flags 0x18 read-write n 0x0 0xFFFFFFFF rx_fifo_2q_full Results FIFO 2Q Full Int Status 7 8 read-write oneToClear rx_fifo_3q_full Results FIFO 3Q Full Int Status 8 9 read-write oneToClear rx_fifo_full Results FIFO Full Int Status 9 10 read-write oneToClear rx_fifo_not_empty Results FIFO Not Empty Int Status 6 7 read-write oneToClear tx_done Transaction Done Int Status 0 1 read-write oneToClear tx_fifo_3q_empty Transaction FIFO 3Q Empty Int Status 5 6 read-write oneToClear tx_fifo_empty Transaction FIFO Empty Int Status 4 5 read-write oneToClear tx_lost_arbitr Transaction Lost Arbitration Int Status 2 3 read-write oneToClear tx_nacked Transaction NACKed Int Status 1 2 read-write oneToClear tx_timeout Transaction Timed Out Int Status 3 4 read-write oneToClear TIMEOUT Timeout and Auto-Stop Settings 0xC read-write n 0x0 0xFFFFFFFF auto_stop_en Auto-Stop Enable 24 25 read-write tx_timeout Transaction Timeout Limit 16 24 read-write TRANS I2C Master Transaction Start and Status Flags 0x14 read-write n 0x0 0xFFFFFFFF tx_done Transaction Done 2 3 read-only tx_in_progress Transaction In Progress 1 2 read-only tx_lost_arbitr Transaction Lost Arbitration 4 5 read-only tx_nacked Transaction Nacked 3 4 read-only tx_start Start Transaction 0 1 read-write tx_timeout Transaction Timed Out 5 6 read-only I2CM1 I2C Master 0 Interface I2C Master 0x40017000 0x0 0x1000 registers n I2CM1 I2C Master 1 IRQ 40 BB Bit-Bang Control Register 0x28 read-write n 0x0 0xFFFFFFFF bb_scl_in_val Bit Bang SCL Input Value 2 3 read-only bb_scl_out Bit Bang SCL Output 0 1 read-write bb_sda_in_val Bit Bang SCL Input Value 3 4 read-only bb_sda_out Bit Bang SDA Output 1 2 read-write rx_fifo_cnt Results FIFO Data Received Count 16 21 read-only CTRL I2C Master Control Register 0x10 read-write n 0x0 0xFFFFFFFF mstr_reset_en Master Reset 7 8 read-write rx_fifo_en Master Results FIFO Enable 3 4 read-write tx_fifo_en Master Transaction FIFO Enable 2 3 read-write FS_CLK_DIV Full Speed SCL Clock Settings 0x0 read-write n 0x0 0xFFFFFFFF fs_filter_clk_div Full Speed Filter Clock Divisor 0 8 read-write fs_scl_hi_cnt Full Speed SCL High Count 20 32 read-write fs_scl_lo_cnt Full Speed SCL Low Count 8 20 read-write INTEN Interrupt Enable/Disable Controls 0x1C read-write n 0x0 0xFFFFFFFF rx_fifo_2q_full Results FIFO 2Q Full Int Enable 7 8 read-write rx_fifo_3q_full Results FIFO 3Q Full Int Enable 8 9 read-write rx_fifo_full Results FIFO Full Int Enable 9 10 read-write rx_fifo_not_empty Results FIFO Not Empty Int Enable 6 7 read-write tx_done Transaction Done Int Enable 0 1 read-write tx_fifo_3q_empty Transaction FIFO 3Q Empty Int Enable 5 6 read-write tx_fifo_empty Transaction FIFO Empty Int Enable 4 5 read-write tx_lost_arbitr Transaction Lost Arbitration IntEnable 2 3 read-write tx_nacked Transaction NACKed Int Enable 1 2 read-write tx_timeout Transaction Timed Out Int Enable 3 4 read-write INTFL Interrupt Flags 0x18 read-write n 0x0 0xFFFFFFFF rx_fifo_2q_full Results FIFO 2Q Full Int Status 7 8 read-write oneToClear rx_fifo_3q_full Results FIFO 3Q Full Int Status 8 9 read-write oneToClear rx_fifo_full Results FIFO Full Int Status 9 10 read-write oneToClear rx_fifo_not_empty Results FIFO Not Empty Int Status 6 7 read-write oneToClear tx_done Transaction Done Int Status 0 1 read-write oneToClear tx_fifo_3q_empty Transaction FIFO 3Q Empty Int Status 5 6 read-write oneToClear tx_fifo_empty Transaction FIFO Empty Int Status 4 5 read-write oneToClear tx_lost_arbitr Transaction Lost Arbitration Int Status 2 3 read-write oneToClear tx_nacked Transaction NACKed Int Status 1 2 read-write oneToClear tx_timeout Transaction Timed Out Int Status 3 4 read-write oneToClear TIMEOUT Timeout and Auto-Stop Settings 0xC read-write n 0x0 0xFFFFFFFF auto_stop_en Auto-Stop Enable 24 25 read-write tx_timeout Transaction Timeout Limit 16 24 read-write TRANS I2C Master Transaction Start and Status Flags 0x14 read-write n 0x0 0xFFFFFFFF tx_done Transaction Done 2 3 read-only tx_in_progress Transaction In Progress 1 2 read-only tx_lost_arbitr Transaction Lost Arbitration 4 5 read-only tx_nacked Transaction Nacked 3 4 read-only tx_start Start Transaction 0 1 read-write tx_timeout Transaction Timed Out 5 6 read-only I2CM2 I2C Master 0 Interface I2C Master 0x40018000 0x0 0x1000 registers n I2CM2 I2C Master 2 IRQ 41 BB Bit-Bang Control Register 0x28 read-write n 0x0 0xFFFFFFFF bb_scl_in_val Bit Bang SCL Input Value 2 3 read-only bb_scl_out Bit Bang SCL Output 0 1 read-write bb_sda_in_val Bit Bang SCL Input Value 3 4 read-only bb_sda_out Bit Bang SDA Output 1 2 read-write rx_fifo_cnt Results FIFO Data Received Count 16 21 read-only CTRL I2C Master Control Register 0x10 read-write n 0x0 0xFFFFFFFF mstr_reset_en Master Reset 7 8 read-write rx_fifo_en Master Results FIFO Enable 3 4 read-write tx_fifo_en Master Transaction FIFO Enable 2 3 read-write FS_CLK_DIV Full Speed SCL Clock Settings 0x0 read-write n 0x0 0xFFFFFFFF fs_filter_clk_div Full Speed Filter Clock Divisor 0 8 read-write fs_scl_hi_cnt Full Speed SCL High Count 20 32 read-write fs_scl_lo_cnt Full Speed SCL Low Count 8 20 read-write INTEN Interrupt Enable/Disable Controls 0x1C read-write n 0x0 0xFFFFFFFF rx_fifo_2q_full Results FIFO 2Q Full Int Enable 7 8 read-write rx_fifo_3q_full Results FIFO 3Q Full Int Enable 8 9 read-write rx_fifo_full Results FIFO Full Int Enable 9 10 read-write rx_fifo_not_empty Results FIFO Not Empty Int Enable 6 7 read-write tx_done Transaction Done Int Enable 0 1 read-write tx_fifo_3q_empty Transaction FIFO 3Q Empty Int Enable 5 6 read-write tx_fifo_empty Transaction FIFO Empty Int Enable 4 5 read-write tx_lost_arbitr Transaction Lost Arbitration IntEnable 2 3 read-write tx_nacked Transaction NACKed Int Enable 1 2 read-write tx_timeout Transaction Timed Out Int Enable 3 4 read-write INTFL Interrupt Flags 0x18 read-write n 0x0 0xFFFFFFFF rx_fifo_2q_full Results FIFO 2Q Full Int Status 7 8 read-write oneToClear rx_fifo_3q_full Results FIFO 3Q Full Int Status 8 9 read-write oneToClear rx_fifo_full Results FIFO Full Int Status 9 10 read-write oneToClear rx_fifo_not_empty Results FIFO Not Empty Int Status 6 7 read-write oneToClear tx_done Transaction Done Int Status 0 1 read-write oneToClear tx_fifo_3q_empty Transaction FIFO 3Q Empty Int Status 5 6 read-write oneToClear tx_fifo_empty Transaction FIFO Empty Int Status 4 5 read-write oneToClear tx_lost_arbitr Transaction Lost Arbitration Int Status 2 3 read-write oneToClear tx_nacked Transaction NACKed Int Status 1 2 read-write oneToClear tx_timeout Transaction Timed Out Int Status 3 4 read-write oneToClear TIMEOUT Timeout and Auto-Stop Settings 0xC read-write n 0x0 0xFFFFFFFF auto_stop_en Auto-Stop Enable 24 25 read-write tx_timeout Transaction Timeout Limit 16 24 read-write TRANS I2C Master Transaction Start and Status Flags 0x14 read-write n 0x0 0xFFFFFFFF tx_done Transaction Done 2 3 read-only tx_in_progress Transaction In Progress 1 2 read-only tx_lost_arbitr Transaction Lost Arbitration 4 5 read-only tx_nacked Transaction Nacked 3 4 read-only tx_start Start Transaction 0 1 read-write tx_timeout Transaction Timed Out 5 6 read-only I2CS I2C Slave Interface I2C Slave 0x40019000 0x0 0x1000 registers n I2CS I2C Slave IRQ 42 CLK_DIV I2C Slave Clock Divisor Control 0x0 read-write n 0x0 0xFFFFFFFF fs_filter_clock_div FS Filter Clock Divisor 0 8 read-write DATA_BYTE I2CS Data Byte 0x10 read-write n 0x0 0xFFFFFFFF data_field Data Field 0 8 read-write data_updated_fl Byte Updated Flag 9 10 read-only read_only_fl Read Only Flag 8 9 read-write DEV_ID I2C Slave Device ID Register 0x4 read-write n 0x0 0xFFFFFFFF slave_dev_id Slave Device ID 0 10 read-write slave_reset Slave Reset 14 15 read-write ten_bit_id_mode 10-bit ID Mode 12 13 read-write INTEN I2CS Interrupt Enable/Disable Controls 0xC read-write n 0x0 0xFFFFFFFF byte0 Updated Byte 0 0 1 read-write byte1 Updated Byte 1 1 2 read-write byte10 Updated Byte 10 10 11 read-write byte11 Updated Byte 11 11 12 read-write byte12 Updated Byte 12 12 13 read-write byte13 Updated Byte 13 13 14 read-write byte14 Updated Byte 14 14 15 read-write byte15 Updated Byte 15 15 16 read-write byte16 Updated Byte 16 16 17 read-write byte17 Updated Byte 17 17 18 read-write byte18 Updated Byte 18 18 19 read-write byte19 Updated Byte 19 19 20 read-write byte2 Updated Byte 2 2 3 read-write byte20 Updated Byte 20 20 21 read-write byte21 Updated Byte 21 21 22 read-write byte22 Updated Byte 22 22 23 read-write byte23 Updated Byte 23 23 24 read-write byte24 Updated Byte 24 24 25 read-write byte25 Updated Byte 25 25 26 read-write byte26 Updated Byte 26 26 27 read-write byte27 Updated Byte 27 27 28 read-write byte28 Updated Byte 28 28 29 read-write byte29 Updated Byte 29 29 30 read-write byte3 Updated Byte 3 3 4 read-write byte30 Updated Byte 30 30 31 read-write byte31 Updated Byte 31 31 32 read-write byte4 Updated Byte 4 4 5 read-write byte5 Updated Byte 5 5 6 read-write byte6 Updated Byte 6 6 7 read-write byte7 Updated Byte 7 7 8 read-write byte8 Updated Byte 8 8 9 read-write byte9 Updated Byte 9 9 10 read-write INTFL I2CS Interrupt Flags 0x8 read-write n 0x0 0xFFFFFFFF byte0 Updated Byte 0 0 1 read-write oneToClear byte1 Updated Byte 1 1 2 read-write oneToClear byte10 Updated Byte 10 10 11 read-write oneToClear byte11 Updated Byte 11 11 12 read-write oneToClear byte12 Updated Byte 12 12 13 read-write oneToClear byte13 Updated Byte 13 13 14 read-write oneToClear byte14 Updated Byte 14 14 15 read-write oneToClear byte15 Updated Byte 15 15 16 read-write oneToClear byte16 Updated Byte 16 16 17 read-write oneToClear byte17 Updated Byte 17 17 18 read-write oneToClear byte18 Updated Byte 18 18 19 read-write oneToClear byte19 Updated Byte 19 19 20 read-write oneToClear byte2 Updated Byte 2 2 3 read-write oneToClear byte20 Updated Byte 20 20 21 read-write oneToClear byte21 Updated Byte 21 21 22 read-write oneToClear byte22 Updated Byte 22 22 23 read-write oneToClear byte23 Updated Byte 23 23 24 read-write oneToClear byte24 Updated Byte 24 24 25 read-write oneToClear byte25 Updated Byte 25 25 26 read-write oneToClear byte26 Updated Byte 26 26 27 read-write oneToClear byte27 Updated Byte 27 27 28 read-write oneToClear byte28 Updated Byte 28 28 29 read-write oneToClear byte29 Updated Byte 29 29 30 read-write oneToClear byte3 Updated Byte 3 3 4 read-write oneToClear byte30 Updated Byte 30 30 31 read-write oneToClear byte31 Updated Byte 31 31 32 read-write oneToClear byte4 Updated Byte 4 4 5 read-write oneToClear byte5 Updated Byte 5 5 6 read-write oneToClear byte6 Updated Byte 6 6 7 read-write oneToClear byte7 Updated Byte 7 7 8 read-write oneToClear byte8 Updated Byte 8 8 9 read-write oneToClear byte9 Updated Byte 9 9 10 read-write oneToClear ICC Instruction Cache Controller ICC 0x40003000 0x0 0x1000 registers n CTRL_STAT Control and Status 0x100 read-write n 0x0 0xFFFFFFFF enable Cache Enable 0 1 read-write ready Cache Ready Status 16 17 read-only ID Device ID Register 0x0 read-write n 0x0 0xFFFFFFFF cache_id Cache ID 10 16 read-only part_num Part Number ID 6 10 read-only rtl_version RTL Release Version 0 6 read-only INVDT_ALL Invalidate (Clear) Cache Control 0x700 read-write n 0x0 0xFFFFFFFF MEM_CFG Memory Configuration Register 0x4 read-write n 0x0 0xFFFFFFFF cache_size Instruction Cache Size 0 16 read-only main_memory_size Internal Flash Memory Size 16 32 read-only IOMAN System I/O Manager IO 0x40000C00 0x0 0x400 registers n ALI_ACK0 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) 0x18 read-write n 0x0 0xFFFFFFFF ali_ack_p0 Analog In Mode Acknowledge: P0[7:0] 0 8 read-only ali_ack_p1 Analog In Mode Acknowledge: P1[7:0] 8 16 read-only ali_ack_p2 Analog In Mode Acknowledge: P2[7:0] 16 24 read-only ali_ack_p3 Analog In Mode Acknowledge: P3[7:0] 24 32 read-only ALI_ACK1 Analog Input Acknowledge Register 1 (P4/P5/P6) 0x1C read-write n 0x0 0xFFFFFFFF ali_ack_p4 Analog In Mode Acknowledge: P4[7:0] 0 8 read-only ali_ack_p5 Analog In Mode Acknowledge: P5[7:0] 8 16 read-only ali_ack_p6 Analog In Mode Acknowledge: P6[0] 16 17 read-only ALI_CONNECT0 Analog I/O Connection Control Register 0 0x20 read-write n 0x0 0xFFFFFFFF ALI_CONNECT1 Analog I/O Connection Control Register 1 0x24 read-write n 0x0 0xFFFFFFFF ALI_REQ0 Analog Input Request Register 0 (P0/P1/P2/P3) 0x10 read-write n 0x0 0xFFFFFFFF ali_req_p0 Analog Input Mode Request: P0[7:0] 0 8 read-write ali_req_p1 Analog Input Mode Request: P1[7:0] 8 16 read-write ali_req_p2 Analog Input Mode Request: P2[7:0] 16 24 read-write ali_req_p3 Analog Input Mode Request: P3[7:0] 24 32 read-write ALI_REQ1 Analog Input Request Register 1 (P4/P5/P6) 0x14 read-write n 0x0 0xFFFFFFFF ali_req_p4 Analog Input Mode Request: P4[7:0] 0 8 read-write ali_req_p5 Analog Input Mode Request: P5[7:0] 8 16 read-write ali_req_p6 Analog Input Mode Request: P6[0] 16 17 read-write I2CM0_ACK I2C Master 0 I/O Acknowledge 0x54 read-write n 0x0 0xFFFFFFFF mapping_ack I2C Master 0 I/O Acknowledge 4 5 read-only I2CM0_REQ I2C Master 0 I/O Request 0x50 read-write n 0x0 0xFFFFFFFF mapping_req I2C Master 0 I/O Request 4 5 read-write I2CM1_ACK I2C Master 1 I/O Acknowledge 0x5C read-write n 0x0 0xFFFFFFFF mapping_ack I2C Master 1 I/O Acknowledge 4 5 read-only I2CM1_REQ I2C Master 1 I/O Request 0x58 read-write n 0x0 0xFFFFFFFF mapping_req I2C Master 1 I/O Request 4 5 read-write I2CM2_ACK I2C Master 2 I/O Acknowledge 0x64 read-write n 0x0 0xFFFFFFFF mapping_ack I2C Master 2 I/O Acknowledge 4 5 read-only I2CM2_REQ I2C Master 2 I/O Request 0x60 read-write n 0x0 0xFFFFFFFF mapping_req I2C Master 2 I/O Request 4 5 read-write I2CS_ACK I2C Slave I/O Acknowledge 0x6C read-write n 0x0 0xFFFFFFFF io_sel I2C Slave I/O Mapping Acknowledge 0 2 read-only mapping_ack I2C Slave I/O Acknowledge 4 5 read-only I2CS_REQ I2C Slave I/O Request 0x68 read-write n 0x0 0xFFFFFFFF io_sel I2C Slave I/O Mapping Select 0 2 read-write mapping_req I2C Slave I/O Request 4 5 read-write OWM_ACK 1-Wire Master I/O Mode Acknowledge 0x94 read-write n 0x0 0xFFFFFFFF epu_io_ack External Pullup Control Line I/O Acknowledge 5 6 read-write mapping_ack 1-Wire Line I/O Acknowledge 4 5 read-write OWM_REQ 1-Wire Master I/O Mode Request 0x90 read-write n 0x0 0xFFFFFFFF epu_io_req External Pullup Control Line I/O Request 5 6 read-write mapping_req 1-Wire Line I/O Request 4 5 read-write SPI0_ACK SPI Master 0 I/O Mode Acknowledge 0x74 read-write n 0x0 0xFFFFFFFF core_io_ack SPI Master 0 Core I/O Acknowledge 4 5 read-only fast_mode SPI Master 0 Fast Mode Acknowledge 24 25 read-only quad_io_ack SPI Master 0 Quad I/O Acknowledge 20 21 read-only ss0_io_ack SPI Master 0 SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPI Master 0 SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPI Master 0 SS[2] I/O Acknowledge 10 11 read-only ss3_io_ack SPI Master 0 SS[3] I/O Acknowledge 11 12 read-only ss4_io_ack SPI Master 0 SS[4] I/O Acknowledge 12 13 read-only SPI0_REQ SPI Master 0 I/O Mode Request 0x70 read-write n 0x0 0xFFFFFFFF core_io_req SPI Master 0 Core I/O Request 4 5 read-write fast_mode SPI Master 0 Fast Mode Request 24 25 read-write quad_io_req SPI Master 0 Quad I/O Request 20 21 read-write ss0_io_req SPI Master 0 SS[0] I/O Request 8 9 read-write ss1_io_req SPI Master 0 SS[1] I/O Request 9 10 read-write ss2_io_req SPI Master 0 SS[2] I/O Request 10 11 read-write ss3_io_req SPI Master 0 SS[3] I/O Request 11 12 read-write ss4_io_req SPI Master 0 SS[4] I/O Request 12 13 read-write SPI1_ACK SPI Master 1 I/O Mode Acknowledge 0x7C read-write n 0x0 0xFFFFFFFF core_io_ack SPI Master 1 Core I/O Acknowledge 4 5 read-only fast_mode SPI Master 1 Fast Mode Acknowledge 24 25 read-only quad_io_ack SPI Master 1 Quad I/O Acknowledge 20 21 read-only ss0_io_ack SPI Master 1 SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPI Master 1 SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPI Master 1 SS[2] I/O Acknowledge 10 11 read-only SPI1_REQ SPI Master 1 I/O Mode Request 0x78 read-write n 0x0 0xFFFFFFFF core_io_req SPI Master 1 Core I/O Request 4 5 read-write fast_mode SPI Master 1 Fast Mode Request 24 25 read-write quad_io_req SPI Master 1 Quad I/O Request 20 21 read-write ss0_io_req SPI Master 1 SS[0] I/O Request 8 9 read-write ss1_io_req SPI Master 1 SS[1] I/O Request 9 10 read-write ss2_io_req SPI Master 1 SS[2] I/O Request 10 11 read-write SPI2_ACK SPI Master 2 I/O Mode Acknowledge 0x84 read-write n 0x0 0xFFFFFFFF core_io_ack SPI Master 2 Core I/O Acknowledge 4 5 read-only fast_mode SPI Master 2 Fast Mode Acknowledge 24 25 read-only mapping_ack SPI Master 2 I/O Mapping Acknowledge 0 1 read-only quad_io_ack SPI Master 2 Quad I/O Acknowledge 20 21 read-only sr0_io_req SPI Master 2 SR[0] I/O Acknowledge 16 17 read-only sr1_io_req SPI Master 2 SR[1] I/O Acknowledge 17 18 read-only ss0_io_ack SPI Master 2 SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPI Master 2 SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPI Master 2 SS[2] I/O Acknowledge 10 11 read-only SPI2_REQ SPI Master 2 I/O Mode Request 0x80 read-write n 0x0 0xFFFFFFFF core_io_req SPI Master 2 Core I/O Request 4 5 read-write fast_mode SPI Master 2 Fast Mode Request 24 25 read-write mapping_req SPI Master 2 I/O Mapping Select 0 1 read-write quad_io_req SPI Master 2 Quad I/O Request 20 21 read-write sr0_io_req SPI Master 2 SR[0] I/O Request 16 17 read-write sr1_io_req SPI Master 2 SR[1] I/O Request 17 18 read-write ss0_io_req SPI Master 2 SS[0] I/O Request 8 9 read-write ss1_io_req SPI Master 2 SS[1] I/O Request 9 10 read-write ss2_io_req SPI Master 2 SS[2] I/O Request 10 11 read-write SPIB_ACK SPI Bridge I/O Mode Acknowledge 0x8C read-write n 0x0 0xFFFFFFFF core_io_ack SPI Bridge Core I/O Acknowledge 4 5 read-only fast_mode SPI Bridge Fast Mode Acknowledge 12 13 read-only quad_io_ack SPI Bridge Quad I/O Acknowledge 8 9 read-only SPIB_REQ SPI Bridge I/O Mode Request 0x88 read-write n 0x0 0xFFFFFFFF core_io_req SPI Bridge Core I/O Request 4 5 read-only fast_mode SPI Bridge Fast Mode Request 12 13 read-only quad_io_req SPI Bridge Quad I/O Request 8 9 read-only SPIX_ACK SPIX I/O Mode Acknowledge 0x2C read-write n 0x0 0xFFFFFFFF core_io_ack SPIX Core I/O Acknowledge 4 5 read-only fast_mode SPIX Fast Mode Acknowledge 16 17 read-only quad_io_ack SPIX Quad I/O Acknowledge 12 13 read-only ss0_io_ack SPIX SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPIX SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPIX SS[2] I/O Acknowledge 10 11 read-only SPIX_REQ SPIX I/O Mode Request 0x28 read-write n 0x0 0xFFFFFFFF core_io_req SPIX Core I/O Request 4 5 read-write fast_mode SPIX Fast Mode Request 16 17 read-write quad_io_req SPIX Quad I/O Request 12 13 read-write ss0_io_req SPIX SS[0] I/O Request 8 9 read-write ss1_io_req SPIX SS[1] I/O Request 9 10 read-write ss2_io_req SPIX SS[2] I/O Request 10 11 read-write UART0_ACK UART0 I/O Mode Acknowledge 0x34 read-write n 0x0 0xFFFFFFFF cts_io_req UART0 CTS I/O Acknowledge 5 6 read-only cts_map UART0 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART0 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART0 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART0 RTS I/O Acknowledge 6 7 read-only rts_map UART0 RTS I/O Mapping Acknowledge 2 3 read-only UART0_REQ UART0 I/O Mode Request 0x30 read-write n 0x0 0xFFFFFFFF cts_io_req UART0 CTS I/O Request 5 6 read-write cts_map UART0 CTS I/O Mapping Select 1 2 read-write io_map UART0 TX/RX I/O Mapping Select 0 1 read-write io_req UART0 TX/RX I/O Request 4 5 read-write rts_io_req UART0 RTS I/O Request 6 7 read-write rts_map UART0 RTS I/O Mapping Select 2 3 read-write UART1_ACK UART1 I/O Mode Acknowledge 0x3C read-write n 0x0 0xFFFFFFFF cts_io_req UART1 CTS I/O Acknowledge 5 6 read-only cts_map UART1 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART1 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART1 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART1 RTS I/O Acknowledge 6 7 read-only rts_map UART1 RTS I/O Mapping Acknowledge 2 3 read-only UART1_REQ UART1 I/O Mode Request 0x38 read-write n 0x0 0xFFFFFFFF cts_io_req UART1 CTS I/O Request 5 6 read-write cts_map UART1 CTS I/O Mapping Select 1 2 read-write io_map UART1 TX/RX I/O Mapping Select 0 1 read-write io_req UART1 TX/RX I/O Request 4 5 read-write rts_io_req UART1 RTS I/O Request 6 7 read-write rts_map UART1 RTS I/O Mapping Select 2 3 read-write UART2_ACK UART2 I/O Mode Acknowledge 0x44 read-write n 0x0 0xFFFFFFFF cts_io_req UART2 CTS I/O Acknowledge 5 6 read-only cts_map UART2 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART2 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART2 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART2 RTS I/O Acknowledge 6 7 read-only rts_map UART2 RTS I/O Mapping Acknowledge 2 3 read-only UART2_REQ UART2 I/O Mode Request 0x40 read-write n 0x0 0xFFFFFFFF cts_io_req UART2 CTS I/O Request 5 6 read-write cts_map UART2 CTS I/O Mapping Select 1 2 read-write io_map UART2 TX/RX I/O Mapping Select 0 1 read-write io_req UART2 TX/RX I/O Request 4 5 read-write rts_io_req UART2 RTS I/O Request 6 7 read-write rts_map UART2 RTS I/O Mapping Select 2 3 read-write UART3_ACK UART3 I/O Mode Acknowledge 0x4C read-write n 0x0 0xFFFFFFFF cts_io_req UART3 CTS I/O Acknowledge 5 6 read-only cts_map UART3 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART3 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART3 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART3 RTS I/O Acknowledge 6 7 read-only rts_map UART3 RTS I/O Mapping Acknowledge 2 3 read-only UART3_REQ UART3 I/O Mode Request 0x48 read-write n 0x0 0xFFFFFFFF cts_io_req UART3 CTS I/O Request 5 6 read-write cts_map UART3 CTS I/O Mapping Select 1 2 read-write io_map UART3 TX/RX I/O Mapping Select 0 1 read-write io_req UART3 TX/RX I/O Request 4 5 read-write rts_io_req UART3 RTS I/O Request 6 7 read-write rts_map UART3 RTS I/O Mapping Select 2 3 read-write WUD_ACK0 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) 0x8 read-write n 0x0 0xFFFFFFFF wud_ack_p0 WUD Mode Acknowledge: P0[7:0] 0 8 read-only wud_ack_p1 WUD Mode Acknowledge: P1[7:0] 8 16 read-only wud_ack_p2 WUD Mode Acknowledge: P2[7:0] 16 24 read-only wud_ack_p3 WUD Mode Acknowledge: P3[7:0] 24 32 read-only WUD_ACK1 Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6) 0xC read-write n 0x0 0xFFFFFFFF wud_ack_p4 WUD Mode Acknowledge: P4[7:0] 0 8 read-only wud_ack_p5 WUD Mode Acknowledge: P5[7:0] 8 16 read-only wud_ack_p6 WUD Mode Acknowledge: P6[7:0] 16 17 read-only WUD_REQ0 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) 0x0 read-write n 0x0 0xFFFFFFFF wud_req_p0 Wakeup Detect Request Mode: P0[7:0] 0 8 read-write wud_req_p1 Wakeup Detect Request Mode: P1[7:0] 8 16 read-write wud_req_p2 Wakeup Detect Request Mode: P2[7:0] 16 24 read-write wud_req_p3 Wakeup Detect Request Mode: P3[7:0] 24 32 read-write WUD_REQ1 Wakeup Detect Mode Request Register 1 (P4/P5/P6) 0x4 read-write n 0x0 0xFFFFFFFF wud_req_p4 Wakeup Detect Request Mode: P4[7:0] 0 8 read-write wud_req_p5 Wakeup Detect Request Mode: P5[7:0] 8 16 read-write wud_req_p6 Wakeup Detect Request Mode: P6[0] 16 17 read-write MAA MAA Cryptographic Engine MAA 0x40007800 0x0 0x400 registers n MAA Modular Arithematic Accelerator IRQ 10 CTRL MAA Control, Configuration and Status 0x0 read-write n 0x0 0xFFFFFFFF if_done Interrupt Flag - Calculation Done 5 6 read-write if_error Interrupt Flag - Error 7 8 read-write inten MAA Interrupt Enable 6 7 read-write ocalc Optimized Calculation Control 4 5 read-write ofs_a Operand A Memory Offset Select 8 10 read-write ofs_b Operand B Memory Offset Select 10 12 read-write ofs_exp Exponent Memory Offset Select 12 14 read-write ofs_mod Modulus Memory Select 14 16 read-write opsel Select Operation Type 1 4 read-write EXP Exponentiation. 0 SQR Square operation. 1 MUL Multiply. 2 SQRMUL Square operation followed by multiply. 3 ADD Addition. 4 SUB Subtraction. 5 seg_a Operand A Memory Segment Select 16 20 read-write seg_b Operand B Memory Segment Select 20 24 read-write seg_res Result Memory Segment Select 24 28 read-write seg_tmp Temporary Memory Segment Select 28 32 read-write start Start MAA Calculation 0 1 read-write MAWS MAA Word (Operand) Size, Big/Little Endian Mode Select 0x4 read-write n 0x0 0xFFFFFFFF byteswap Big Endian Byte Mode 15 16 read-write modlen MAA Word Size 0 10 read-write OWM 1-Wire Master Interface 1-Wire Master 0x4001E000 0x0 0x1000 registers n OWM 1-Wire Master IRQ 47 CFG 1-Wire Master Configuration 0x0 read-write n 0x0 0xFFFFFFFF bit_bang_en Bit Bang Enable 2 3 read-write ext_pullup_enable Enable External Pullup 4 5 read-write ext_pullup_mode Provide an extra output to control an external pullup. 3 4 read-write force_pres_det Force Line During Presence Detect 1 2 read-write int_pullup_enable Enable internal pullup. 7 8 read-write long_line_mode Long Line Mode 0 1 read-write overdrive Enables overdrive speed for 1-Wire operations. 6 7 read-write single_bit_mode Enable Single Bit TX/RX Mode 5 6 read-write CLK_DIV_1US 1-Wire Master Clock Divisor 0x4 read-write n 0x0 0xFFFFFFFF divisor Clock Divisor for 1MHz 0 8 read-write CTRL_STAT 1-Wire Master Control/Status 0x8 read-write n 0x0 0xFFFFFFFF bit_bang_oe Bit Bang Output Enable 2 3 read-write ow_input OW Input State 3 4 read-only presence_detect Presence Pulse Detected 7 8 read-write sra_mode SRA Mode 1 2 read-write start_ow_reset Start OW Reset 0 1 read-write DATA 1-Wire Master Data Buffer 0xC read-write n 0x0 0xFFFFFFFF tx_rx Tx/Rx Buffer 0 8 read-write INTEN 1-Wire Master Interrupt Enables 0x14 read-write n 0x0 0xFFFFFFFF line_low OW Line Low Detected Interrupt Enable 4 5 read-write line_short OW Line Short Detected Interrupt Enable 3 4 read-write ow_reset_done OW Reset Sequence Completed 0 1 read-write rx_data_ready Rx Data Ready Interrupt Enable 2 3 read-write tx_data_empty Tx Data Empty Interrupt Enable 1 2 read-write INTFL 1-Wire Master Interrupt Flags 0x10 read-write n 0x0 0xFFFFFFFF line_low OW Line Low Detected Interrupt Flag 4 5 read-write oneToClear line_short OW Line Short Detected Interrupt Flag 3 4 read-write oneToClear ow_reset_done OW Reset Sequence Completed 0 1 read-write oneToClear rx_data_ready Rx Data Ready Interrupt Flag 2 3 read-write oneToClear tx_data_empty Tx Data Empty Interrupt Flag 1 2 read-write oneToClear PMU0 Peripheral Management Unit PMU 0x40005000 0x0 0x20 registers n PMU Peripheral Manament IRQ 7 CFG Channel Configuration 0x4 read-write n 0x0 0xFFFFFFFF burst_size DMA Maximum Burst Size 24 29 read-write bus_error AHB Bus Error Interrupt Flag 4 5 read-write oneToClear enable PMU Channel Enable 0 1 read-write interrupt Descriptor Interrupt Flag 16 17 read-write oneToClear int_en PMU Channel Interrupt Enable 17 18 read-write ll_stopped Linked List Engine Status 2 3 read-write manual Manual Mode Enable 3 4 read-write ps_sel Time Out Interval Prescale Select 14 16 read-write to_sel Time Out Interval Select 11 14 read-write to_stat AHB Bus Timeout Interrupt Flag 6 7 read-write oneToClear DSC1 Current Descriptor DWORD 1 0x10 read-write n 0x0 0xFFFFFFFF DSC2 Current Descriptor DWORD 2 0x14 read-write n 0x0 0xFFFFFFFF DSC3 Current Descriptor DWORD 3 0x18 read-write n 0x0 0xFFFFFFFF DSC4 Current Descriptor DWORD 4 0x1C read-write n 0x0 0xFFFFFFFF DSCADR Starting Descriptor Address 0x0 read-write n 0x0 0xFFFFFFFF LOOP Channel Loop Counters 0x8 read-write n 0x0 0xFFFFFFFF counter_0 CH1 Loop Counter 1 0 16 read-write counter_1 CH1 Loop Counter 0 16 32 read-write OP Current Descriptor DWORD 0 (OP) 0xC read-write n 0x0 0xFFFFFFFF PMU1 Peripheral Management Unit PMU 0x40005020 0x0 0x20 registers n CFG Channel Configuration 0x4 read-write n 0x0 0xFFFFFFFF burst_size DMA Maximum Burst Size 24 29 read-write bus_error AHB Bus Error Interrupt Flag 4 5 read-write oneToClear enable PMU Channel Enable 0 1 read-write interrupt Descriptor Interrupt Flag 16 17 read-write oneToClear int_en PMU Channel Interrupt Enable 17 18 read-write ll_stopped Linked List Engine Status 2 3 read-write manual Manual Mode Enable 3 4 read-write ps_sel Time Out Interval Prescale Select 14 16 read-write to_sel Time Out Interval Select 11 14 read-write to_stat AHB Bus Timeout Interrupt Flag 6 7 read-write oneToClear DSC1 Current Descriptor DWORD 1 0x10 read-write n 0x0 0xFFFFFFFF DSC2 Current Descriptor DWORD 2 0x14 read-write n 0x0 0xFFFFFFFF DSC3 Current Descriptor DWORD 3 0x18 read-write n 0x0 0xFFFFFFFF DSC4 Current Descriptor DWORD 4 0x1C read-write n 0x0 0xFFFFFFFF DSCADR Starting Descriptor Address 0x0 read-write n 0x0 0xFFFFFFFF LOOP Channel Loop Counters 0x8 read-write n 0x0 0xFFFFFFFF counter_0 CH1 Loop Counter 1 0 16 read-write counter_1 CH1 Loop Counter 0 16 32 read-write OP Current Descriptor DWORD 0 (OP) 0xC read-write n 0x0 0xFFFFFFFF PMU2 Peripheral Management Unit PMU 0x40005040 0x0 0x20 registers n CFG Channel Configuration 0x4 read-write n 0x0 0xFFFFFFFF burst_size DMA Maximum Burst Size 24 29 read-write bus_error AHB Bus Error Interrupt Flag 4 5 read-write oneToClear enable PMU Channel Enable 0 1 read-write interrupt Descriptor Interrupt Flag 16 17 read-write oneToClear int_en PMU Channel Interrupt Enable 17 18 read-write ll_stopped Linked List Engine Status 2 3 read-write manual Manual Mode Enable 3 4 read-write ps_sel Time Out Interval Prescale Select 14 16 read-write to_sel Time Out Interval Select 11 14 read-write to_stat AHB Bus Timeout Interrupt Flag 6 7 read-write oneToClear DSC1 Current Descriptor DWORD 1 0x10 read-write n 0x0 0xFFFFFFFF DSC2 Current Descriptor DWORD 2 0x14 read-write n 0x0 0xFFFFFFFF DSC3 Current Descriptor DWORD 3 0x18 read-write n 0x0 0xFFFFFFFF DSC4 Current Descriptor DWORD 4 0x1C read-write n 0x0 0xFFFFFFFF DSCADR Starting Descriptor Address 0x0 read-write n 0x0 0xFFFFFFFF LOOP Channel Loop Counters 0x8 read-write n 0x0 0xFFFFFFFF counter_0 CH1 Loop Counter 1 0 16 read-write counter_1 CH1 Loop Counter 0 16 32 read-write OP Current Descriptor DWORD 0 (OP) 0xC read-write n 0x0 0xFFFFFFFF PMU3 Peripheral Management Unit PMU 0x40005060 0x0 0x20 registers n CFG Channel Configuration 0x4 read-write n 0x0 0xFFFFFFFF burst_size DMA Maximum Burst Size 24 29 read-write bus_error AHB Bus Error Interrupt Flag 4 5 read-write oneToClear enable PMU Channel Enable 0 1 read-write interrupt Descriptor Interrupt Flag 16 17 read-write oneToClear int_en PMU Channel Interrupt Enable 17 18 read-write ll_stopped Linked List Engine Status 2 3 read-write manual Manual Mode Enable 3 4 read-write ps_sel Time Out Interval Prescale Select 14 16 read-write to_sel Time Out Interval Select 11 14 read-write to_stat AHB Bus Timeout Interrupt Flag 6 7 read-write oneToClear DSC1 Current Descriptor DWORD 1 0x10 read-write n 0x0 0xFFFFFFFF DSC2 Current Descriptor DWORD 2 0x14 read-write n 0x0 0xFFFFFFFF DSC3 Current Descriptor DWORD 3 0x18 read-write n 0x0 0xFFFFFFFF DSC4 Current Descriptor DWORD 4 0x1C read-write n 0x0 0xFFFFFFFF DSCADR Starting Descriptor Address 0x0 read-write n 0x0 0xFFFFFFFF LOOP Channel Loop Counters 0x8 read-write n 0x0 0xFFFFFFFF counter_0 CH1 Loop Counter 1 0 16 read-write counter_1 CH1 Loop Counter 0 16 32 read-write OP Current Descriptor DWORD 0 (OP) 0xC read-write n 0x0 0xFFFFFFFF PMU4 Peripheral Management Unit PMU 0x40005080 0x0 0x20 registers n CFG Channel Configuration 0x4 read-write n 0x0 0xFFFFFFFF burst_size DMA Maximum Burst Size 24 29 read-write bus_error AHB Bus Error Interrupt Flag 4 5 read-write oneToClear enable PMU Channel Enable 0 1 read-write interrupt Descriptor Interrupt Flag 16 17 read-write oneToClear int_en PMU Channel Interrupt Enable 17 18 read-write ll_stopped Linked List Engine Status 2 3 read-write manual Manual Mode Enable 3 4 read-write ps_sel Time Out Interval Prescale Select 14 16 read-write to_sel Time Out Interval Select 11 14 read-write to_stat AHB Bus Timeout Interrupt Flag 6 7 read-write oneToClear DSC1 Current Descriptor DWORD 1 0x10 read-write n 0x0 0xFFFFFFFF DSC2 Current Descriptor DWORD 2 0x14 read-write n 0x0 0xFFFFFFFF DSC3 Current Descriptor DWORD 3 0x18 read-write n 0x0 0xFFFFFFFF DSC4 Current Descriptor DWORD 4 0x1C read-write n 0x0 0xFFFFFFFF DSCADR Starting Descriptor Address 0x0 read-write n 0x0 0xFFFFFFFF LOOP Channel Loop Counters 0x8 read-write n 0x0 0xFFFFFFFF counter_0 CH1 Loop Counter 1 0 16 read-write counter_1 CH1 Loop Counter 0 16 32 read-write OP Current Descriptor DWORD 0 (OP) 0xC read-write n 0x0 0xFFFFFFFF PMU5 Peripheral Management Unit PMU 0x400050A0 0x0 0x20 registers n CFG Channel Configuration 0x4 read-write n 0x0 0xFFFFFFFF burst_size DMA Maximum Burst Size 24 29 read-write bus_error AHB Bus Error Interrupt Flag 4 5 read-write oneToClear enable PMU Channel Enable 0 1 read-write interrupt Descriptor Interrupt Flag 16 17 read-write oneToClear int_en PMU Channel Interrupt Enable 17 18 read-write ll_stopped Linked List Engine Status 2 3 read-write manual Manual Mode Enable 3 4 read-write ps_sel Time Out Interval Prescale Select 14 16 read-write to_sel Time Out Interval Select 11 14 read-write to_stat AHB Bus Timeout Interrupt Flag 6 7 read-write oneToClear DSC1 Current Descriptor DWORD 1 0x10 read-write n 0x0 0xFFFFFFFF DSC2 Current Descriptor DWORD 2 0x14 read-write n 0x0 0xFFFFFFFF DSC3 Current Descriptor DWORD 3 0x18 read-write n 0x0 0xFFFFFFFF DSC4 Current Descriptor DWORD 4 0x1C read-write n 0x0 0xFFFFFFFF DSCADR Starting Descriptor Address 0x0 read-write n 0x0 0xFFFFFFFF LOOP Channel Loop Counters 0x8 read-write n 0x0 0xFFFFFFFF counter_0 CH1 Loop Counter 1 0 16 read-write counter_1 CH1 Loop Counter 0 16 32 read-write OP Current Descriptor DWORD 0 (OP) 0xC read-write n 0x0 0xFFFFFFFF PT0 Pulse Train Generation Pulse Train 0x40011010 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT1 Pulse Train Generation Pulse Train 0x4001101C 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT10 Pulse Train Generation Pulse Train 0x40011088 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT11 Pulse Train Generation Pulse Train 0x40011094 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT12 Pulse Train Generation Pulse Train 0x400110A0 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT13 Pulse Train Generation Pulse Train 0x400110AC 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT14 Pulse Train Generation Pulse Train 0x400110B8 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT15 Pulse Train Generation Pulse Train 0x400110C4 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT2 Pulse Train Generation Pulse Train 0x40011028 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT3 Pulse Train Generation Pulse Train 0x40011034 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT4 Pulse Train Generation Pulse Train 0x40011040 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT5 Pulse Train Generation Pulse Train 0x4001104C 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT6 Pulse Train Generation Pulse Train 0x40011058 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT7 Pulse Train Generation Pulse Train 0x40011064 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT8 Pulse Train Generation Pulse Train 0x40011070 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PT9 Pulse Train Generation Pulse Train 0x4001107C 0x0 0xC registers n LOOP Pulse Train Loop Count 0x8 read-write n 0x0 0xFFFFFFFF RATE_LENGTH Pulse Train Configuration 0x0 read-write n 0x0 0xFFFFFFFF mode Pulse Train Output Mode/Train Length 27 32 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 2_BIT Pulse train, 2 bit pattern. 2 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 3_BIT Pulse train, 3 bit pattern. 3 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 rate_control Pulse Train Enable/Rate Control 0 27 read-write TRAIN Pulse Train Output Pattern 0x4 read-write n 0x0 0xFFFFFFFF PTG Pulse Train Generation Pulse Train 0x40011000 0x0 0x10 registers n PT Pulse Train IRQ 38 ENABLE Global Enable/Disable Controls for All Pulse Trains 0x0 read-write n 0x0 0xFFFFFFFF pt0 Enable/Disable control for PT0 0 1 read-write pt1 Enable/Disable control for PT1 1 2 read-write pt10 Enable/Disable control for PT10 10 11 read-write pt11 Enable/Disable control for PT11 11 12 read-write pt12 Enable/Disable control for PT12 12 13 read-write pt13 Enable/Disable control for PT13 13 14 read-write pt14 Enable/Disable control for PT14 14 15 read-write pt15 Enable/Disable control for PT15 15 16 read-write pt2 Enable/Disable control for PT2 2 3 read-write pt3 Enable/Disable control for PT3 3 4 read-write pt4 Enable/Disable control for PT4 4 5 read-write pt5 Enable/Disable control for PT5 5 6 read-write pt6 Enable/Disable control for PT6 6 7 read-write pt7 Enable/Disable control for PT7 7 8 read-write pt8 Enable/Disable control for PT8 8 9 read-write pt9 Enable/Disable control for PT9 9 10 read-write INTEN Pulse Train Interrupt Enable/Disable 0xC read-write n 0x0 0xFFFFFFFF pt0 Pulse Train 0 Stopped Interrupt Enable/Disable 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Enable/Disable 1 2 read-write pt10 Pulse Train 10 Stopped Interrupt Enable/Disable 10 11 read-write pt11 Pulse Train 11 Stopped Interrupt Enable/Disable 11 12 read-write pt12 Pulse Train 12 Stopped Interrupt Enable/Disable 12 13 read-write pt13 Pulse Train 13 Stopped Interrupt Enable/Disable 13 14 read-write pt14 Pulse Train 14 Stopped Interrupt Enable/Disable 14 15 read-write pt15 Pulse Train 15 Stopped Interrupt Enable/Disable 15 16 read-write pt2 Pulse Train 2 Stopped Interrupt Enable/Disable 2 3 read-write pt3 Pulse Train 3 Stopped Interrupt Enable/Disable 3 4 read-write pt4 Pulse Train 4 Stopped Interrupt Enable/Disable 4 5 read-write pt5 Pulse Train 5 Stopped Interrupt Enable/Disable 5 6 read-write pt6 Pulse Train 6 Stopped Interrupt Enable/Disable 6 7 read-write pt7 Pulse Train 7 Stopped Interrupt Enable/Disable 7 8 read-write pt8 Pulse Train 8 Stopped Interrupt Enable/Disable 8 9 read-write pt9 Pulse Train 9 Stopped Interrupt Enable/Disable 9 10 read-write INTFL Pulse Train Interrupt Flags 0x8 read-write n 0x0 0xFFFFFFFF pt0 Pulse Train 0 Stopped Interrupt Flag 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Flag 1 2 read-write pt10 Pulse Train 10 Stopped Interrupt Flag 10 11 read-write pt11 Pulse Train 11 Stopped Interrupt Flag 11 12 read-write pt12 Pulse Train 12 Stopped Interrupt Flag 12 13 read-write pt13 Pulse Train 13 Stopped Interrupt Flag 13 14 read-write pt14 Pulse Train 14 Stopped Interrupt Flag 14 15 read-write pt15 Pulse Train 15 Stopped Interrupt Flag 15 16 read-write pt2 Pulse Train 2 Stopped Interrupt Flag 2 3 read-write pt3 Pulse Train 3 Stopped Interrupt Flag 3 4 read-write pt4 Pulse Train 4 Stopped Interrupt Flag 4 5 read-write pt5 Pulse Train 5 Stopped Interrupt Flag 5 6 read-write pt6 Pulse Train 6 Stopped Interrupt Flag 6 7 read-write pt7 Pulse Train 7 Stopped Interrupt Flag 7 8 read-write pt8 Pulse Train 8 Stopped Interrupt Flag 8 9 read-write pt9 Pulse Train 9 Stopped Interrupt Flag 9 10 read-write RESYNC Global Resync (All Pulse Trains) Control 0x4 read-write n 0x0 0xFFFFFFFF pt0 Resync control for PT0 0 1 read-write pt1 Resync control for PT1 1 2 read-write pt10 Resync control for PT10 10 11 read-write pt11 Resync control for PT11 11 12 read-write pt12 Resync control for PT12 12 13 read-write pt13 Resync control for PT13 13 14 read-write pt14 Resync control for PT14 14 15 read-write pt15 Resync control for PT15 15 16 read-write pt2 Resync control for PT2 2 3 read-write pt3 Resync control for PT3 3 4 read-write pt4 Resync control for PT4 4 5 read-write pt5 Resync control for PT5 5 6 read-write pt6 Resync control for PT6 6 7 read-write pt7 Resync control for PT7 7 8 read-write pt8 Resync control for PT8 8 9 read-write pt9 Resync control for PT9 9 10 read-write PWRMAN System Power Manager Power Manager 0x40000800 0x0 0x200 registers n PowerManager Power Manager IRQ 1 BASE_PART_NUM Base Part Number 0x3C read-write n 0x0 0xFFFFFFFF base_part_number Base Part Number 0 16 read-only DIE_TYPE Die Type ID Register 0x38 read-write n 0x0 0xFFFFFFFF INTEN Interrupt Enable/Disable Controls 0x8 read-write n 0x0 0xFFFFFFFF rtc_warning RTC Warning Monitor Int Enable 2 3 read-write v1_2_warning 1.2V Warning Monitor Int Enable 0 1 read-write v1_8_warning 1.8V Warning Monitor Int Enable 1 2 read-write vdda_warning VDDA Warning Monitor Int Enable 3 4 read-write vddb_warning VDDB Warning Monitor Int Enable 4 5 read-write vddioh_reset VDDIOH Supply Reset Int Flag 6 7 read-write oneToClear vddio_reset VDDIO Supply Reset Int Flag 5 6 read-write oneToClear INTFL Interrupt Flags 0x4 read-write n 0x0 0xFFFFFFFF rtc_warning RTC Warning Monitor Int Flag 2 3 read-write oneToClear v1_2_warning 1.2V Warning Monitor Int Flag 0 1 read-write oneToClear v1_8_warning 1.8V Warning Monitor Int Flag 1 2 read-write oneToClear vdda_warning VDDA Warning Monitor Int Flag 3 4 read-write oneToClear vddb_warning VDDB Warning Monitor Int Flag 4 5 read-write oneToClear vddioh_reset VDDIOH Supply Reset Int Flag 6 7 read-write oneToClear vddio_reset VDDIO Supply Reset Int Flag 5 6 read-write oneToClear MARGIN_CTRL SRAM Margin Adjustment 0x34 read-write n 0x0 0xFFFFFFFF extra_margin Extra Margin Adjustment 0 3 read-write extra_write_margin Extra Write Margin Adjustment 3 5 read-write write_assist_en Write Assist Enable 5 6 read-write write_assist_margin Write Assist Margin Adjustment 6 8 read-write MASK_ID0 Mask ID Register 0 0x40 read-write n 0x0 0xFFFFFFFF mask_id Mask ID[27:0] 4 32 read-only revision_id Revision ID 0 4 read-only MASK_ID1 Mask ID Register 1 0x44 read-write n 0x0 0xFFFFFFFF mask_id Mask ID[58:28] 0 31 read-only mask_id_enable Enable Mask ID 31 32 read-write PERIPHERAL_RESET Peripheral Reset Control Register 0x48 read-write n 0x0 0xFFFFFFFF adc Reset ADC 28 29 read-write crc Reset CRC 4 5 read-write gpio Reset GPIO 7 8 read-write i2cm0 Reset I2C Master 0 19 20 read-write i2cm1 Reset I2C Master 1 20 21 read-write i2cm2 Reset I2C Master 2 21 22 read-write i2cs Reset I2C Slave 22 23 read-write owm Reset 1-Wire Master 27 28 read-write pmu Reset PMU 2 3 read-write pulse_train Reset All Pulse Trains 14 15 read-write spib Reset SPI Bridge 26 27 read-write spim0 Reset SPI Master 0 23 24 read-write spim1 Reset SPI Master 1 24 25 read-write spim2 Reset SPI Master 2 25 26 read-write spix Reset SPI XIP 1 2 read-write ssb Reset SSB 0 1 read-write timer0 Reset Timer/Counter Module 0 8 9 read-write timer1 Reset Timer/Counter Module 1 9 10 read-write timer2 Reset Timer/Counter Module 2 10 11 read-write timer3 Reset Timer/Counter Module 3 11 12 read-write timer4 Reset Timer/Counter Module 4 12 13 read-write timer5 Reset Timer/Counter Module 5 13 14 read-write tpu Reset TPU 5 6 read-write uart0 Reset UART 0 15 16 read-write uart1 Reset UART 1 16 17 read-write uart2 Reset UART 2 17 18 read-write uart3 Reset UART 3 18 19 read-write usb Reset USB 3 4 read-write watchdog0 Reset Watchdog Timer 0 6 7 read-write PWR_RST_CTRL Power Reset Control and Status 0x0 read-write n 0x0 0xFFFFFFFF afe_powered AFE Powered 2 3 read-write arm_lockup Reset Caused By - ARM Core Lockup 17 18 read-only arm_lockup_reset ARM Lockup Reset 9 10 read-write firmware_reset Firmware Initiated Reset 8 9 read-write fw_command_arm Reset Caused By - Firmware Commanded Reset 18 19 read-only fw_command_sysman Reset Caused By - Firmware Initiated Reset from SysMan 20 21 read-only io_active I/O Active 3 4 read-write low_power_mode Power Manager Dynamic Clock Gating Enable 31 32 read-write por Reset Caused By - Power On Reset (POR) 22 23 read-only pullups_enabled Static Pullups Enabled 5 6 read-write srstn_assertion Reset Caused By - External System Reset (SRSTn) 21 22 read-only tamper_detect Reset Caused By - Tamper Detect 16 17 read-only usb_powered USB Powered 4 5 read-write watchdog_timeout Reset Caused By - Watchdog Timeout 19 20 read-only SVM_EVENTS SVM Event Status Flags (read-only) 0xC read-write n 0x0 0xFFFFFFFF rtc_warning RTC Warning Monitor Event Input 2 3 read-only v1_2_warning 1.2V Warning Monitor Event Input 0 1 read-only v1_8_warning 1.8V Warning Monitor Event Input 1 2 read-only vdda_warning VDDA Warning Monitor Event Input 3 4 read-only vddb_warning VDDB Warning Monitor Event Input 4 5 read-only vddioh_warning VDDIOH Warning Monitor Event Input 6 7 read-only vddio_warning VDDIO Warning Monitor Event Input 5 6 read-only WUD_CTRL Wake-Up Detect Control 0x10 read-write n 0x0 0xFFFFFFFF clear_all Clear All WUD Pad States 12 13 read-write ctrl_enable Enable WUD Control Modification 16 17 read-write pad_mode Wake-Up Pad Signal Mode 8 10 read-write pad_select Wake-Up Pad Select 0 6 read-write WUD_PULSE0 WUD Pulse To Mode Bit 0 0x14 read-write n 0x0 0xFFFFFFFF WUD_PULSE1 WUD Pulse To Mode Bit 1 0x18 read-write n 0x0 0xFFFFFFFF WUD_SEEN0 Wake-up Detect Status for P0/P1/P2/P3 0x1C read-write n 0x0 0xFFFFFFFF gpio0 Wake-Up Detect Status for P0.0 0 1 read-only gpio1 Wake-Up Detect Status for P0.1 1 2 read-only gpio10 Wake-Up Detect Status for P1.2 10 11 read-only gpio11 Wake-Up Detect Status for P1.3 11 12 read-only gpio12 Wake-Up Detect Status for P1.4 12 13 read-only gpio13 Wake-Up Detect Status for P1.5 13 14 read-only gpio14 Wake-Up Detect Status for P1.6 14 15 read-only gpio15 Wake-Up Detect Status for P1.7 15 16 read-only gpio16 Wake-Up Detect Status for P2.0 16 17 read-only gpio17 Wake-Up Detect Status for P2.1 17 18 read-only gpio18 Wake-Up Detect Status for P2.2 18 19 read-only gpio19 Wake-Up Detect Status for P2.3 19 20 read-only gpio2 Wake-Up Detect Status for P0.2 2 3 read-only gpio20 Wake-Up Detect Status for P2.4 20 21 read-only gpio21 Wake-Up Detect Status for P2.5 21 22 read-only gpio22 Wake-Up Detect Status for P2.6 22 23 read-only gpio23 Wake-Up Detect Status for P2.7 23 24 read-only gpio24 Wake-Up Detect Status for P3.0 24 25 read-only gpio25 Wake-Up Detect Status for P3.1 25 26 read-only gpio26 Wake-Up Detect Status for P3.2 26 27 read-only gpio27 Wake-Up Detect Status for P3.3 27 28 read-only gpio28 Wake-Up Detect Status for P3.4 28 29 read-only gpio29 Wake-Up Detect Status for P3.5 29 30 read-only gpio3 Wake-Up Detect Status for P0.3 3 4 read-only gpio30 Wake-Up Detect Status for P3.6 30 31 read-only gpio31 Wake-Up Detect Status for P3.7 31 32 read-only gpio4 Wake-Up Detect Status for P0.4 4 5 read-only gpio5 Wake-Up Detect Status for P0.5 5 6 read-only gpio6 Wake-Up Detect Status for P0.6 6 7 read-only gpio7 Wake-Up Detect Status for P0.7 7 8 read-only gpio8 Wake-Up Detect Status for P1.0 8 9 read-only gpio9 Wake-Up Detect Status for P1.1 9 10 read-only WUD_SEEN1 Wake-up Detect Status for P4/P5/P6/P7 0x20 read-write n 0x0 0xFFFFFFFF gpio32 Wake-Up Detect Status for P4.0 0 1 read-only gpio33 Wake-Up Detect Status for P4.1 1 2 read-only gpio34 Wake-Up Detect Status for P4.2 2 3 read-only gpio35 Wake-Up Detect Status for P4.3 3 4 read-only gpio36 Wake-Up Detect Status for P4.4 4 5 read-only gpio37 Wake-Up Detect Status for P4.5 5 6 read-only gpio38 Wake-Up Detect Status for P4.6 6 7 read-only gpio39 Wake-Up Detect Status for P4.7 7 8 read-only gpio40 Wake-Up Detect Status for P5.0 8 9 read-only gpio41 Wake-Up Detect Status for P5.1 9 10 read-only gpio42 Wake-Up Detect Status for P5.2 10 11 read-only gpio43 Wake-Up Detect Status for P5.3 11 12 read-only gpio44 Wake-Up Detect Status for P5.4 12 13 read-only gpio45 Wake-Up Detect Status for P5.5 13 14 read-only gpio46 Wake-Up Detect Status for P5.6 14 15 read-only gpio47 Wake-Up Detect Status for P5.7 15 16 read-only gpio48 Wake-Up Detect Status for P6.0 16 17 read-only PWRSEQ Power Sequencer Power Manager 0x40000A30 0x0 0x40 registers n FLAGS Power Sequencer Flags 0x20 read-write n 0x0 0xFFFFFFFF pwr_boot_fail Boot Fail event detected flag 3 4 read-write oneToClear pwr_first_boot Initial Boot event detected flag 0 1 read-only pwr_flash_discharge Flash Discharged During Powerfail event detected flag 4 5 read-write oneToClear pwr_iowakeup GPIO Wakeup event detected flag 5 6 read-write oneToClear pwr_isoz_vddioh_fail VDDIOH Isolation POR Tripped 22 23 read-write oneToClear pwr_isoz_vddio_fail VDDIO Isolation POR Tripped 21 22 read-write oneToClear pwr_nanoring_wakeup_flag Wakeup Triggered by Nanoring Wakeup 23 24 read-write oneToClear pwr_por18z_fail_latch POR18 and POR18_bg have been tripped 11 12 read-write oneToClear pwr_power_fail Power Fail event detected flag 2 3 read-write oneToClear pwr_sys_reboot Firmware Reset event detected flag 1 2 read-only pwr_tvdd12_bad Retention Regulator POR Tripped event detected flag 18 19 read-write oneToClear pwr_tvdd12_rst_bad TVDD12 Comparator Tripped event detected flag 10 11 read-write oneToClear pwr_usb_plug_wakeup USB Power Connect Wakeup event detected flag 16 17 read-write oneToClear pwr_usb_remove_wakeup USB Power Remove Wakeup event detected flag 17 18 read-write oneToClear pwr_vdd12_rst_bad VDD12_SW Comparator Tripped event detected flag 6 7 read-write oneToClear pwr_vdd18_rst_bad VDD18_SW Comparator Tripped event detected flag 7 8 read-write oneToClear pwr_vddb_rst_bad VDDB Comparator Tripped event detected flag 9 10 read-write oneToClear pwr_vddioh_rst_bad VDDIOH Comparator Tripped 20 21 read-write oneToClear pwr_vddio_rst_bad VDDIO Comparator Tripped 19 20 read-write oneToClear pwr_vrtc_rst_bad VRTC Comparator Tripped event detected flag 8 9 read-write oneToClear pwr_watchdog_rstn_flag Power Sequencer Reset Triggered by Watchdog Flag 24 25 read-write oneToClear rtc_cmpr0 RTC Comparator 0 Match event detected flag 12 13 read-only rtc_cmpr1 RTC Comparator 1 Match event detected flag 13 14 read-only rtc_prescale_cmp RTC Prescale Comparator Match event detected flag 14 15 read-only rtc_rollover RTC Rollover event detected flag 15 16 read-only MSK_FLAGS Power Sequencer Flags Mask Register 0x24 read-write n 0x0 0xFFFFFFFF pwr_boot_fail Mask for previous boot fail detect 3 4 read-write pwr_flash_discharge Mask for flash discharge event 4 5 read-write pwr_iowakeup Mask for GPIO wakeup event detect 5 6 read-write pwr_isoz_vddioh_fail Mask for VDDIOH Isolation POR Tripped 22 23 read-write oneToClear pwr_isoz_vddio_fail Mask for VDDIO Isolation POR Tripped 21 22 read-write oneToClear pwr_nanoring_wakeup_flag Mask for Wakeup Triggered by Nanoring Wakeup 23 24 read-write oneToClear pwr_por18z_fail_latch Mask for POR18 powerfail event 11 12 read-write pwr_power_fail Mask for previous power fail detect 2 3 read-write pwr_sys_reboot Mask for system reboot detect 1 2 read-write pwr_tvdd12_bad Mask for TVDD12 power fail event 18 19 read-write pwr_tvdd12_rst_bad Mask for TVDD12 rst event 10 11 read-write pwr_usb_plug_wakeup Mask for USB plug connect event 16 17 read-write pwr_usb_remove_wakeup Mask for USB plug disconnect event 17 18 read-write pwr_vdd12_rst_bad Mask for VDD12 rst event 6 7 read-write pwr_vdd18_rst_bad Mask for VDD18 rst event 7 8 read-write pwr_vddb_rst_bad Mask for VDDB rst event 9 10 read-write pwr_vddioh_rst_bad Mask for VDDIOH Comparator Tripped 20 21 read-write oneToClear pwr_vddio_rst_bad Mask for VDDIO Comparator Tripped 19 20 read-write oneToClear pwr_vrtc_rst_bad Mask for VRTC rst event 8 9 read-write pwr_watchdog_rstn_flag Mask for Power Sequencer Reset Triggered by Watchdog Flag 24 25 read-write oneToClear rtc_cmpr0 Mask for RTC compare 0 event 12 13 read-write rtc_cmpr1 Mask for RTC compare 1 event 13 14 read-write rtc_prescale_cmp Mask for RTC prescale compare event 14 15 read-write rtc_rollover Mask for RTC rollover event 15 16 read-write PWR_MISC Power Misc Controls 0x38 read-write n 0x0 0xFFFFFFFF invert_4_mask_bits Invert Sense of Power Mask Flags for RTC 0 1 read-write REG0 Power Sequencer Control Register 0 0x0 read-write n 0x0 0xFFFFFFFF pwr_first_boot Wake on First Boot 1 2 read-write pwr_flashen_run Enable Flash Operation during Run Mode 3 4 read-write pwr_flashen_slp Enable Flash Operation during Sleep Mode 4 5 read-write pwr_lp1 Shutdown Power Mode Select 0 1 read-write pwr_nren_run Enable Nano Oscillator in Run Mode 9 10 read-write pwr_nren_slp Enable Nano Oscillator in Sleep Mode 10 11 read-write pwr_osc_select Select Primary System Oscillator 96MHz or 4MHz 31 32 read-write pwr_rcen_run Enable 4MHz RC oscillator operation during Run Mode for LP2 and LP3 29 30 read-write pwr_rcen_slp Enable 4MHz RC oscillator operation during Sleep Mode for LP1 30 31 read-write pwr_retregen_run Enable Retention Regulator Operation during Run Mode 5 6 read-write pwr_retregen_slp Enable Retention Regulator Operation during Sleep Mode 6 7 read-write pwr_roen_run Enable 96MHz System Relaxation Oscillator in Run Mode 7 8 read-write pwr_roen_slp Enable 96MHz System Relaxation Oscillator in Sleep Mode 8 9 read-write pwr_rtcen_run Enable Real Time Clock Operation during Run Mode 11 12 read-write pwr_rtcen_slp Enable Real Time Clock Operation during Sleep Mode 12 13 read-write pwr_svm12en_run Enable VDD12_SW SVM operation during Run Mode 13 14 read-write pwr_svm18en_run Enable VDD18_SW SVM operation during Run Mode 15 16 read-write pwr_svmrtcen_run Enable VRTC SVM operation during Run Mode 17 18 read-write pwr_svmtvdd12en_run Enable TVDD12 SVM operation during Run Mode 21 22 read-write pwr_svm_vddb_run Enable VDDB SVM operation during Run Mode 19 20 read-write pwr_sys_reboot Firmware System Reboot Request 2 3 write-only pwr_tvdd12_swen_run Enable TVDD12 switching during Run Mode 27 28 read-write pwr_tvdd12_swen_slp Enable TVDD12 switching during Sleep Mode 28 29 read-write pwr_vdd12_swen_run Enable VDD12 switching during Run Mode 23 24 read-write pwr_vdd12_swen_slp Enable VDD12 switching during Sleep Mode 24 25 read-write pwr_vdd18_swen_run Enable VDD18 switching during Run Mode 25 26 read-write pwr_vdd18_swen_slp Enable VDD18 switching during Sleep Mode 26 27 read-write REG1 Power Sequencer Control Register 1 0x4 read-write n 0x0 0xFFFFFFFF pwr_auto_mbus_gate Automatically Set/Clear GPIO MBus Gate 6 7 read-write pwr_clr_io_cfg_latch Clear all GPIO Configuration Latches 1 2 read-write pwr_clr_io_event_latch Clear all GPIO Event Seen Latches 0 1 read-write pwr_discharge_en Enable Flash Discharge During Powerfail Event 3 4 read-write pwr_lp0_core_resume_en Enable Core Resume to Toggle during LP0 18 19 read-write pwr_lp1_core_rstn_en Enable Core RSTN to Toggle during LP1 19 20 read-write pwr_mbus_gate Freeze GPIO MBus State 2 3 read-write pwr_retreg_src_v12 Enable VDDIO SVM Run for LP2 and LP3 12 13 read-write pwr_retreg_src_v18 Enables VDD18 Rail as Retention Power Supply 14 15 read-write pwr_retreg_src_vrtc Enables VRTC Rail as Retention Power Su 13 14 read-write pwr_sram_nwell_sw SRAM n-Well Switch 5 6 read-write pwr_svm_vddioh_en_run Enable VDDIOH SVM Run for LP2 and LP3 10 11 read-write pwr_svm_vddio_en_run Enable VDDIO SVM Run for LP2 and LP3 8 9 read-write pwr_tvdd12_well TVDD12 Well Switch 4 5 read-write pwr_vddioh_en_iso_por Enable VDDIOH Isolation POR 17 18 read-write pwr_vddio_en_iso_por Enable VDDIO Isolation POR 16 17 read-write REG2 Power Sequencer Control Register 2 0x8 read-write n 0x0 0xFFFFFFFF pwr_tvdd12_hyst TVDD12 Comparator Hysteresis Setting 8 10 read-write pwr_vdd12_hyst VDD12_SW Comparator Hysteresis Setting 0 2 read-write pwr_vdd18_hyst VDD18_SW Comparator Hysteresis Setting 2 4 read-write pwr_vddb_hyst VDDB Comparator Hysteresis Setting 6 8 read-write pwr_vddioh_hyst VDDIO Comparator Hysteresis Setting 12 14 read-write pwr_vddio_hyst VDDIO Comparator Hysteresis Setting 10 12 read-write pwr_vrtc_hyst VRTC Comparator Hysteresis Setting 4 6 read-write REG3 Power Sequencer Control Register 3 0xC read-write n 0x0 0xFFFFFFFF pwr_failsel Timeout before rebooting during PowerFail/BootFail events. 10 13 read-write pwr_fltrrosel Window of time power must be valid before entering Run mode. 3 6 read-write pwr_rc_div Frequency Divider for 4MHz RC Oscillator 20 22 read-write pwr_rosel Relaxation Oscillator Stable Timeout 0 3 read-write pwr_ro_clk_mux Relaxation Clock Mux 8 10 read-write pwr_ro_div Frequency Divider for 96MHz Relaxation Oscillator 16 19 read-write pwr_svm_clk_mux SVM Clock Mux 6 8 read-write REG4 Power Sequencer Control Register 4 (Internal Test Only) 0x10 read-write n 0x0 0xFFFFFFFF pwr_ext_clk_in_en Internal Use Only 6 7 read-write pwr_nr_clk_gate_en Internal Use Only 5 6 read-write pwr_pseq_32k_en Internal Use Only 7 8 read-write pwr_ro_tstclk_en Internal Use Only 4 5 read-write pwr_tm_fast_timers Internal Use Only 1 2 read-write pwr_tm_ps_2_gpio Internal Use Only 0 1 read-write pwr_usb_dis_comp Internal Use Only 3 4 read-write REG5 Power Sequencer Control Register 5 (Trim 0) 0x14 read-write n 0x0 0xFFFFFFFF pwr_rtc_trim Real Time Clock trim setting 21 25 read-write pwr_trim_bias Power Manager Bias Current trim setting 9 15 read-write pwr_trim_retreg Retention Regulator trim setting 15 21 read-write pwr_trim_svm_bg Power Manager Bandgap trim setting 0 9 read-write REG6 Power Sequencer Control Register 6 (Trim 1) 0x18 read-write n 0x0 0xFFFFFFFF pwr_trim_crypto_osc Crypto Oscillator trim setting 20 29 read-write pwr_trim_osc_vref Relaxation Oscillator trim setting 11 20 read-write pwr_trim_usb_bias USB Bias Current trim setting 0 3 read-write pwr_trim_usb_dm_res USB Data Minus Slew Rate trim setting 7 11 read-write pwr_trim_usb_pm_res USB Data Plus Slew Rate trim setting 3 7 read-write REG7 Power Sequencer Control Register 7 0x1C read-write n 0x0 0xFFFFFFFF pwr_flash_pd_lookahead Flash Powerdown Lookahead Flag 0 1 read-only RETN_CTRL0 Retention Control Register 0 0x30 read-write n 0x0 0xFFFFFFFF rc_poll_flash Enable Automatic Flash Polling for Wakeup 3 4 read-write rc_rel_ccg_early Early Core Clock Gate Release 1 2 read-write rc_use_flc_twk Enable Flash Controller TWake Timer 2 3 read-write retn_ctrl_en Retention Controller Enable 0 1 read-write RETN_CTRL1 Retention Control Register 1 0x34 read-write n 0x0 0xFFFFFFFF rtc_twk Retention Controller TWake Cycle Count 0 4 read-write RTC_CTRL2 RTC Misc Controls 0x3C read-write n 0x0 0xFFFFFFFF ssb_performance None 3 4 read-write timer_async_rd None 0 1 read-write timer_async_wr None 1 2 read-write timer_auto_update None 2 3 read-write WR_PROTECT Critical Setting Write Protect Register 0x2C read-write n 0x0 0xFFFFFFFF bypass Write Protect Bypass 30 31 read-write bypass_seq Write Protect Bypass Sequence Write 0 8 read-write info Write Protect from Info Block 29 30 read-write rtc Write Protect from RTC 28 29 read-write rtc_seq Write Protect RTC Sequence Write 8 16 read-write wp Critical Setting Write Protect 31 32 read-write RTCCFG RTC Configuration Register Real-Time Clock 0x40000A70 0x0 0x80 registers n CLK_CTRL RTC Clock Control Settings 0x4 read-write n 0x0 0xFFFFFFFF nano_en Enable nanoring oscillator output 2 3 read-write NANO_CNTR Nano Oscillator Counter Read Register 0x0 read-write n 0x0 0xFFFFFFFF nanoring_counter Nano Oscillator Counter 0 16 read-only OSC_CTRL RTC Oscillator Control 0xC read-write n 0x0 0xFFFFFFFF osc_bypass Bypass RTC oscillator 0 1 read-write osc_disable_o Reset RTC Oscillator 3 4 read-only osc_disable_r if osc_disable_sel = 1, this will hold the RTC in reset. 1 2 read-write osc_disable_sel Select RTC Oscillator Disable Control Source 2 3 read-write PwrSeq_Control PowerSequencer controls the reset state of the RTC 0 RTC_Domain_Control RTC reset controlled by osc_disable_r bit 1 RTCTMR Real Time Clock Real-Time Clock 0x40000A00 0x0 0x30 registers n RTC_COMP0 RTC Compare 0 IRQ 3 RTC_COMP1 RTC Compare 1 IRQ 4 RTC_PRESCALE_COMP RTC Prescale Compare IRQ 5 RTC_OVERFLOW RTC Overflow IRQ 6 COMP0 RTC Time of Day Alarm 0 Compare Register 0x8 read-write n 0x0 0xFFFFFFFF COMP1 RTC Time of Day Alarm 1 Compare Register 0xC read-write n 0x0 0xFFFFFFFF CTRL RTC Timer Control 0x0 read-write n 0x0 0xFFFFFFFF aggressive_rst Use Aggressive Reset Mode 4 5 read-write clear RTC Timer Clear Bit 1 2 write-only clr_active RTC clear is pending 21 22 read-only cmpr0_clr_active cmpr0 clear transaction is pending 26 27 read-only cmpr1_clr_active cmpr1 clear transaction is pending 25 26 read-only enable RTC Timer Enable 0 1 read-write en_active Enable RTC in Active Modes 16 17 read-only osc_frce_sm_en_active osc_force_mode transaction is pending 18 19 read-only osc_frce_st_active osc_force_state transaction is pending 19 20 read-only osc_goto_low_active osc_goto_low_r transaction is pending 17 18 read-only pending RTC Transaction Pending 2 3 read-only prescale_cmpr0_active prescale cmpr0 is pending 23 24 read-only prescale_update_active prescale update transaction is pending 24 25 read-only rollover_clr_active rollover clr is pending 22 23 read-only set_active timer_set_active 20 21 read-only use_async_flags Use Async RTC Flags 3 4 read-write FLAGS CPU Interrupt and RTC Domain Flags 0x10 read-write n 0x0 0xFFFFFFFF async_clr_flags Asynchronous RTC Flag Clear 31 32 write-only comp0 RTC Compare 0 Interrupt Status 0 1 read-write oneToClear comp0_flag_a RTC Compare 0 4kHz Flag 8 9 read-only comp1 RTC Compare 1 Interrupt Status 1 2 read-write oneToClear comp1_flag_a RTC Compare 1 4kHz Flag 9 10 read-only overflow RTC Overflow Interrupt Status 3 4 read-write oneToClear overflow_flag_a RTC Overflow 4kHz Flag 11 12 read-only prescale_comp RTC Prescale Compare Int Status 2 3 read-write oneToClear prescl_flag_a RTC Prescale Compare 4kHz Flag 10 11 read-only trim RTC Trim Interrupt Status 4 5 read-write oneToClear trim_flag_a RTC Trim Event 4kHz Flag 12 13 read-only INTEN Interrupt Enable Controls 0x18 read-write n 0x0 0xFFFFFFFF comp0 RTC Time of Day Alarm (Compare 0) Interrupt Enable 0 1 read-write comp1 RTC Time of Day Alarm (Compare 1) Interrupt Enable 1 2 read-write overflow RTC Overflow Interrupt Enable 3 4 read-write prescale_comp RTC Prescale Compare Int Enable 2 3 read-write trim RTC Trim Adjust Event Interrupt Enable 4 5 read-write PRESCALE RTC Timer Prescale Setting 0x1C read-write n 0x0 0xFFFFFFFF width_selection RTC Timer Prescale Setting 0 4 read-write PRESCALE_MASK RTC Timer Prescale Compare Mask 0x24 read-write n 0x0 0xFFFFFFFF comp_mask RTC Timer Prescale Compare Mask 0 4 read-write SNZ_VALUE RTC Timer Alarm Snooze Value 0x14 read-write n 0x0 0xFFFFFFFF TIMER RTC Timer Count Value 0x4 read-write n 0x0 0xFFFFFFFF TRIM_CTRL RTC Timer Trim Controls 0x28 read-write n 0x0 0xFFFFFFFF trim_enable_r Enable RTL Trim of RTC Timer 0 1 read-write trim_faster_ovr_r Force RTC Trim to Faster 1 2 read-write trim_slower_r RTC Trim Direction Status 2 3 read-only TRIM_VALUE RTC Timer Trim Adjustment Interval 0x2C read-write n 0x0 0xFFFFFFFF trim_control Trim Direction 18 19 read-write trim_value Trim PPM Value 0 18 read-write SPIM0 SPI Master Interface SPI Master 0x4001A000 0x0 0x1000 registers n SPIM0 SPI Master 0 IRQ 43 FIFO_CTRL SPI Master FIFO Control Register 0xC read-write n 0x0 0xFFFFFFFF rx_fifo_af_lvl Results FIFO AF Level 16 21 read-write rx_fifo_used Results FIFO Used 24 30 read-only tx_fifo_ae_lvl Transaction FIFO AE Level 0 4 read-write tx_fifo_used Transaction FIFO Used 8 13 read-only GEN_CTRL SPI Master General Control Register 0x8 read-write n 0x0 0xFFFFFFFF bb_sck_in_out Bit Bang SCK Input/Output 6 7 read-write bb_sdio_dr_en Bit Bang SDIO Drive Enable 16 20 read-write bb_sdio_in Bit Bang SDIO Input 8 12 read-only bb_sdio_out Bit Bang SDIO Output 12 16 read-write bb_sr_in Bit Bang SR Input 5 6 read-only bb_ss_in_out Bit Bang SS Input/Output 4 5 read-write bit_bang_mode Bit Bang Mode Enable 3 4 read-write rx_fifo_en Results FIFO Enable 2 3 read-write spi_mstr_en Enable/Disable SPI Master 0 1 read-write tx_fifo_en Transaction FIFO Enable 1 2 read-write INTEN SPI Master Interrupt Enable/Disable Settings 0x18 read-write n 0x0 0xFFFFFFFF rx_done Results Done Int Enable 3 4 read-write rx_fifo_af RXFIFO Almost Full Int Enable 5 6 read-write rx_stalled Results Stalled Int Enable 1 2 read-write tx_fifo_ae TXFIFO Almost Empty Int Enable 4 5 read-write tx_ready Transaction Ready Int Enable 2 3 read-write tx_stalled Transaction Stalled Int Enable 0 1 read-write INTFL SPI Master Interrupt Flags 0x14 read-write n 0x0 0xFFFFFFFF rx_done Results Done Int Status 3 4 read-write oneToClear rx_fifo_af RXFIFO Almost Full Int Status 5 6 read-write oneToClear rx_stalled Results Stalled Int Status 1 2 read-write oneToClear tx_fifo_ae TXFIFO Almost Empty Int Status 4 5 read-write oneToClear tx_ready Transaction Ready Int Status 2 3 read-write oneToClear tx_stalled Transaction Stalled Int Status 0 1 read-write oneToClear MSTR_CFG SPI Master Configuration Register 0x0 read-write n 0x0 0xFFFFFFFF act_delay SS Active Timing 16 18 read-write alt_sck_hi_clk Alt SCK High Clocks 20 24 read-write alt_sck_lo_clk Alt SCK Low Clocks 24 28 read-write inact_delay SS Inactive Timing 18 20 read-write page_size Page Size 6 8 read-write sck_hi_clk SCK High Clocks 8 12 read-write sck_lo_clk SCK Low Clocks 12 16 read-write slave_sel SPI Slave Select 0 3 read-write spi_mode SPI Mode 4 6 read-write three_wire_mode 3-Wire Mode 3 4 read-write SPCL_CTRL SPI Master Special Mode Controls 0x10 read-write n 0x0 0xFFFFFFFF miso_fc_en SDIO(1) to SR(0) Mode 1 2 read-write ss_sample_mode SS Sample Mode 0 1 read-write ss_sa_sdio_dr_en SDIO Active Drive Mode 8 12 read-write ss_sa_sdio_out SDIO Active Output Value 4 8 read-write SS_SR_POLARITY Polarity Control for SS and SR Signals 0x4 read-write n 0x0 0xFFFFFFFF fc_polarity SR Signal Polarity [FC Polarity] 8 16 read-write ss_polarity SS Signal Polarity 0 8 read-write SPIM1 SPI Master Interface SPI Master 0x4001B000 0x0 0x1000 registers n SPIM1 SPI Master 1 IRQ 44 FIFO_CTRL SPI Master FIFO Control Register 0xC read-write n 0x0 0xFFFFFFFF rx_fifo_af_lvl Results FIFO AF Level 16 21 read-write rx_fifo_used Results FIFO Used 24 30 read-only tx_fifo_ae_lvl Transaction FIFO AE Level 0 4 read-write tx_fifo_used Transaction FIFO Used 8 13 read-only GEN_CTRL SPI Master General Control Register 0x8 read-write n 0x0 0xFFFFFFFF bb_sck_in_out Bit Bang SCK Input/Output 6 7 read-write bb_sdio_dr_en Bit Bang SDIO Drive Enable 16 20 read-write bb_sdio_in Bit Bang SDIO Input 8 12 read-only bb_sdio_out Bit Bang SDIO Output 12 16 read-write bb_sr_in Bit Bang SR Input 5 6 read-only bb_ss_in_out Bit Bang SS Input/Output 4 5 read-write bit_bang_mode Bit Bang Mode Enable 3 4 read-write rx_fifo_en Results FIFO Enable 2 3 read-write spi_mstr_en Enable/Disable SPI Master 0 1 read-write tx_fifo_en Transaction FIFO Enable 1 2 read-write INTEN SPI Master Interrupt Enable/Disable Settings 0x18 read-write n 0x0 0xFFFFFFFF rx_done Results Done Int Enable 3 4 read-write rx_fifo_af RXFIFO Almost Full Int Enable 5 6 read-write rx_stalled Results Stalled Int Enable 1 2 read-write tx_fifo_ae TXFIFO Almost Empty Int Enable 4 5 read-write tx_ready Transaction Ready Int Enable 2 3 read-write tx_stalled Transaction Stalled Int Enable 0 1 read-write INTFL SPI Master Interrupt Flags 0x14 read-write n 0x0 0xFFFFFFFF rx_done Results Done Int Status 3 4 read-write oneToClear rx_fifo_af RXFIFO Almost Full Int Status 5 6 read-write oneToClear rx_stalled Results Stalled Int Status 1 2 read-write oneToClear tx_fifo_ae TXFIFO Almost Empty Int Status 4 5 read-write oneToClear tx_ready Transaction Ready Int Status 2 3 read-write oneToClear tx_stalled Transaction Stalled Int Status 0 1 read-write oneToClear MSTR_CFG SPI Master Configuration Register 0x0 read-write n 0x0 0xFFFFFFFF act_delay SS Active Timing 16 18 read-write alt_sck_hi_clk Alt SCK High Clocks 20 24 read-write alt_sck_lo_clk Alt SCK Low Clocks 24 28 read-write inact_delay SS Inactive Timing 18 20 read-write page_size Page Size 6 8 read-write sck_hi_clk SCK High Clocks 8 12 read-write sck_lo_clk SCK Low Clocks 12 16 read-write slave_sel SPI Slave Select 0 3 read-write spi_mode SPI Mode 4 6 read-write three_wire_mode 3-Wire Mode 3 4 read-write SPCL_CTRL SPI Master Special Mode Controls 0x10 read-write n 0x0 0xFFFFFFFF miso_fc_en SDIO(1) to SR(0) Mode 1 2 read-write ss_sample_mode SS Sample Mode 0 1 read-write ss_sa_sdio_dr_en SDIO Active Drive Mode 8 12 read-write ss_sa_sdio_out SDIO Active Output Value 4 8 read-write SS_SR_POLARITY Polarity Control for SS and SR Signals 0x4 read-write n 0x0 0xFFFFFFFF fc_polarity SR Signal Polarity [FC Polarity] 8 16 read-write ss_polarity SS Signal Polarity 0 8 read-write SPIM2 SPI Master Interface SPI Master 0x4001C000 0x0 0x1000 registers n SPIM2 SPI Master 2 IRQ 45 FIFO_CTRL SPI Master FIFO Control Register 0xC read-write n 0x0 0xFFFFFFFF rx_fifo_af_lvl Results FIFO AF Level 16 21 read-write rx_fifo_used Results FIFO Used 24 30 read-only tx_fifo_ae_lvl Transaction FIFO AE Level 0 4 read-write tx_fifo_used Transaction FIFO Used 8 13 read-only GEN_CTRL SPI Master General Control Register 0x8 read-write n 0x0 0xFFFFFFFF bb_sck_in_out Bit Bang SCK Input/Output 6 7 read-write bb_sdio_dr_en Bit Bang SDIO Drive Enable 16 20 read-write bb_sdio_in Bit Bang SDIO Input 8 12 read-only bb_sdio_out Bit Bang SDIO Output 12 16 read-write bb_sr_in Bit Bang SR Input 5 6 read-only bb_ss_in_out Bit Bang SS Input/Output 4 5 read-write bit_bang_mode Bit Bang Mode Enable 3 4 read-write rx_fifo_en Results FIFO Enable 2 3 read-write spi_mstr_en Enable/Disable SPI Master 0 1 read-write tx_fifo_en Transaction FIFO Enable 1 2 read-write INTEN SPI Master Interrupt Enable/Disable Settings 0x18 read-write n 0x0 0xFFFFFFFF rx_done Results Done Int Enable 3 4 read-write rx_fifo_af RXFIFO Almost Full Int Enable 5 6 read-write rx_stalled Results Stalled Int Enable 1 2 read-write tx_fifo_ae TXFIFO Almost Empty Int Enable 4 5 read-write tx_ready Transaction Ready Int Enable 2 3 read-write tx_stalled Transaction Stalled Int Enable 0 1 read-write INTFL SPI Master Interrupt Flags 0x14 read-write n 0x0 0xFFFFFFFF rx_done Results Done Int Status 3 4 read-write oneToClear rx_fifo_af RXFIFO Almost Full Int Status 5 6 read-write oneToClear rx_stalled Results Stalled Int Status 1 2 read-write oneToClear tx_fifo_ae TXFIFO Almost Empty Int Status 4 5 read-write oneToClear tx_ready Transaction Ready Int Status 2 3 read-write oneToClear tx_stalled Transaction Stalled Int Status 0 1 read-write oneToClear MSTR_CFG SPI Master Configuration Register 0x0 read-write n 0x0 0xFFFFFFFF act_delay SS Active Timing 16 18 read-write alt_sck_hi_clk Alt SCK High Clocks 20 24 read-write alt_sck_lo_clk Alt SCK Low Clocks 24 28 read-write inact_delay SS Inactive Timing 18 20 read-write page_size Page Size 6 8 read-write sck_hi_clk SCK High Clocks 8 12 read-write sck_lo_clk SCK Low Clocks 12 16 read-write slave_sel SPI Slave Select 0 3 read-write spi_mode SPI Mode 4 6 read-write three_wire_mode 3-Wire Mode 3 4 read-write SPCL_CTRL SPI Master Special Mode Controls 0x10 read-write n 0x0 0xFFFFFFFF miso_fc_en SDIO(1) to SR(0) Mode 1 2 read-write ss_sample_mode SS Sample Mode 0 1 read-write ss_sa_sdio_dr_en SDIO Active Drive Mode 8 12 read-write ss_sa_sdio_out SDIO Active Output Value 4 8 read-write SS_SR_POLARITY Polarity Control for SS and SR Signals 0x4 read-write n 0x0 0xFFFFFFFF fc_polarity SR Signal Polarity [FC Polarity] 8 16 read-write ss_polarity SS Signal Polarity 0 8 read-write SPIS SPI Slave Interface SPI Slave 0x40020000 0x0 0x1000 registers n SPIS SPI Slave IRQ 49 FIFO_CTRL SPI Master FIFO Control Register 0x4 read-write n 0x0 0xFFFFFFFF rx_fifo_af_lvl Receive FIFO Almost Full Flag Level 8 13 read-only tx_fifo_ae_lvl Transaction FIFO Almost Empty Flag Level 0 5 read-write FIFO_STAT SPI Slave FIFO Status Information 0x8 read-write n 0x0 0xFFFFFFFF rx_fifo_used Number of Bytes in Receive FIFO 8 14 read-only tx_fifo_used Number of Bytes in Transmit FIFO 0 6 read-only GEN_CTRL SPI Slave General Control Register 0x0 read-write n 0x0 0xFFFFFFFF data_width Width of SPI Slave Data Transfers 4 6 read-write Enable read-write x1 1-bit Wide 0 x2 2-bit Wide/Dual 1 x4 4-bit Wide/Quad 2 invalid Reserved for future use. Do not use. 3 disable_parking Disable automatic resetting of SPI Slave on exit from LP Modes 31 32 read-write rx_fifo_en SPI RX FIFO Enable 2 3 read-write Enable read-write Disabled Disable SPI Slave RX FIFO 0 Enabled Enable SPI Slave RX FIFO 1 spi_mode Defines Clock Polarity (bit 17) and Clock Phase (bit 16), collectively referred to as SPI Mode. 16 18 read-write spi_slave_en SPI Slave Enable 0 1 read-write Enable read-write Disabled Disable SPI Slave 0 Enabled Enable SPI Slave 1 tx_clk_invert Invert TX Clock 20 21 read-write Enable read-write no_effect No Effect 0 Invert Inverts the TX transmit clock such that outgoing data is updated on the opposite clock edge from that specified by spi_mode. Effectively, this inverts the value of the Clock Polarity bit from the value specified in spi_mode. 1 tx_fifo_en TX FIFO Enable 1 2 read-write Enable read-write Disabled Disable SPI Slave TX FIFO 0 Enabled Enable SPI Slave TX FIFO 1 INTEN SPI Slave Interrupt Enable/Disable Settings 0x10 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Int Enable 1 2 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 rx_lost_data RX FIFO Overflow Int Enable 3 4 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 ss_asserted Slave Select Asserted Int Enable 5 6 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 ss_deasserted Slave Select Deasserted Int Enable 6 7 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 tx_fifo_ae TX FIFO Almost Empty Int Enable 0 1 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 tx_no_data No Data in TX FIFO Int Enable 2 3 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 tx_underflow TX Underflow Int Enable 4 5 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 INTFL SPI Slave Interrupt Flags 0xC read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full 1 2 read-write oneToClear rx_lost_data RX FIFO Overflow 3 4 read-write oneToClear ss_asserted Slave Select Asserted 5 6 read-write oneToClear ss_deasserted Slave Select Deasserted 6 7 read-write oneToClear tx_fifo_ae TX FIFO Almost Empty 0 1 read-write oneToClear tx_no_data TX FIFO Empty 2 3 read-write oneToClear SPIX SPI XIP Interface SPI XIP 0x40004000 0x0 0x1000 registers n FETCH_CTRL SPIX Fetch Control 0x4 read-write n 0x0 0xFFFFFFFF addr_width Address Width 10 12 read-write SINGLE Single I/O used for Tx/Rx. 0 DUAL_IO Dual I/O lines used for Tx/Rx. 1 QUAD_IO Quad I/O lines used for Tx/Rx. 2 cmd_value Command Value 0 8 read-write cmd_width Command Width 8 10 read-write SINGLE Single I/O used for Tx/Rx. 0 DUAL_IO Dual I/O lines used for Tx/Rx. 1 QUAD_IO Quad I/O lines used for Tx/Rx. 2 data_width Data Width 12 14 read-write SINGLE Single I/O used for Tx/Rx. 0 DUAL_IO Dual I/O lines used for Tx/Rx. 1 QUAD_IO Quad I/O lines used for Tx/Rx. 2 MASTER_CFG SPIX Master Configuration 0x0 read-write n 0x0 0xFFFFFFFF act_delay SS Active Timing 16 18 read-write OFF No SS Active timing delay enabled. 0 FOR_2_MOD_CLK SS Active timing delay of 2 SPIX module clock cycles. 1 FOR_4_MOD_CLK SS Active timing delay of 4 SPIX module clock cycles. 2 FOR_8_MOD_CLK SS Active timing delay of 8 SPIX module clock cycles. 3 alt_sck_hi_clk Alt SCK High Clocks 20 24 read-write alt_sck_lo_clk Alt SCK Low Clocks 24 28 read-write alt_timing_en Alternate Timing Mode Enable 3 4 read-write DISABLED Alternate timing is disabled. 0 ENABLED_AS_NEEDED Alternate timing will be enabled automatically when needed. 1 inact_delay SS Inactive Timing 18 20 read-write OFF No SS Active timing delay enabled. 0 FOR_2_MOD_CLK SS Active timing delay of 2 SPIX module clock cycles. 1 FOR_4_MOD_CLK SS Active timing delay of 4 SPIX module clock cycles. 2 FOR_8_MOD_CLK SS Active timing delay of 8 SPIX module clock cycles. 3 sck_hi_clk SCK High Clocks 8 12 read-write sck_lo_clk SCK Low Clocks 12 16 read-write slave_sel SPIX Slave Select 4 7 read-write spi_mode SPIX Mode 0 2 read-write SCK_HI_SAMPLE_RISING SCK is active high, data is sampled on clock rising edge. 0 SCK_LO_SAMPLE_FALLING SCK is active low, data is sampled on clock rising edge. 3 ss_act_lo SPIX Slave Select Polarity 2 3 read-write ACTIVE_HIGH Enabled slave select (SS) is active high. 0 ACTIVE_LOW Enabled slave select (SS) is active low. 1 MODE_CTRL SPIX Mode Control 0x8 read-write n 0x0 0xFFFFFFFF mode_clocks Mode Clocks 0 4 read-write no_cmd_mode No Command Mode 8 9 read-write MODE_DATA SPIX Mode Data 0xC read-write n 0x0 0xFFFFFFFF mode_data_bits Mode Data 0 16 read-write mode_data_oe Mode Output Enable 16 32 read-write TMR0 16/32 bit Timer/Counters Timers 0x4000B000 0x0 0x1000 registers n TMR0 Timer 0 IRQ 22 TMR16_0 16-bit Timer 0 IRQ 23 COUNT16_0 [16 bit] Current Count Value, 16-bit Timer 0 0x10 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT16_1 [16 bit] Current Count Value, 16-bit Timer 1 0x18 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT32 [32 bit] Current Count Value 0x4 read-write n 0x0 0xFFFFFFFF CTRL Timer Control Register 0x0 read-write n 0x0 0xFFFFFFFF enable0 Enable 32-bit timer / 16-bit timer 0 12 13 read-write enable1 Enable 16-bit timer 1 13 14 read-write mode Operating Modes for 32-bit/16-bit Timers 0 3 read-write polarity Timer I/O Polarity 8 9 read-write prescale Timer Clock Prescale Setting 4 8 read-write tmr2x16 Dual 16-bit Timer Mode 3 4 read-write INTEN Timer Module Interrupt Enable/Disable Settings 0x24 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Enable for 32-bit Timer / 16-bit Timer 0 0 1 read-write timer1 Interrupt Enable for 16-bit Timer 1 1 2 read-write INTFL Timer Module Interrupt Flags 0x20 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Flag for 32-bit Timer / 16-bit Timer 0 0 1 read-write oneToClear timer1 Interrupt Flag for 16-bit Timer 1 1 2 read-write oneToClear PWM_CAP32 [32 bit] PWM Compare Setting or Capture/Measure Value 0xC read-write n 0x0 0xFFFFFFFF TERM_CNT16_0 [16 bit] Terminal Count Setting, 16-bit Timer 0 0x14 read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT16_1 [16 bit] Terminal Count Setting, 16-bit Timer 1 0x1C read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT32 [32 bit] Terminal Count Setting 0x8 read-write n 0x0 0xFFFFFFFF TMR1 16/32 bit Timer/Counters Timers 0x4000C000 0x0 0x1000 registers n TMR1 Timer 1 IRQ 24 TMR16_1 16-bit Timer 1 IRQ 25 COUNT16_0 [16 bit] Current Count Value, 16-bit Timer 0 0x10 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT16_1 [16 bit] Current Count Value, 16-bit Timer 1 0x18 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT32 [32 bit] Current Count Value 0x4 read-write n 0x0 0xFFFFFFFF CTRL Timer Control Register 0x0 read-write n 0x0 0xFFFFFFFF enable0 Enable 32-bit timer / 16-bit timer 0 12 13 read-write enable1 Enable 16-bit timer 1 13 14 read-write mode Operating Modes for 32-bit/16-bit Timers 0 3 read-write polarity Timer I/O Polarity 8 9 read-write prescale Timer Clock Prescale Setting 4 8 read-write tmr2x16 Dual 16-bit Timer Mode 3 4 read-write INTEN Timer Module Interrupt Enable/Disable Settings 0x24 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Enable for 32-bit Timer / 16-bit Timer 0 0 1 read-write timer1 Interrupt Enable for 16-bit Timer 1 1 2 read-write INTFL Timer Module Interrupt Flags 0x20 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Flag for 32-bit Timer / 16-bit Timer 0 0 1 read-write oneToClear timer1 Interrupt Flag for 16-bit Timer 1 1 2 read-write oneToClear PWM_CAP32 [32 bit] PWM Compare Setting or Capture/Measure Value 0xC read-write n 0x0 0xFFFFFFFF TERM_CNT16_0 [16 bit] Terminal Count Setting, 16-bit Timer 0 0x14 read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT16_1 [16 bit] Terminal Count Setting, 16-bit Timer 1 0x1C read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT32 [32 bit] Terminal Count Setting 0x8 read-write n 0x0 0xFFFFFFFF TMR2 16/32 bit Timer/Counters Timers 0x4000D000 0x0 0x1000 registers n TMR2 Timer 2 IRQ 26 TMR16_2 16-bit Timer 2 IRQ 27 COUNT16_0 [16 bit] Current Count Value, 16-bit Timer 0 0x10 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT16_1 [16 bit] Current Count Value, 16-bit Timer 1 0x18 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT32 [32 bit] Current Count Value 0x4 read-write n 0x0 0xFFFFFFFF CTRL Timer Control Register 0x0 read-write n 0x0 0xFFFFFFFF enable0 Enable 32-bit timer / 16-bit timer 0 12 13 read-write enable1 Enable 16-bit timer 1 13 14 read-write mode Operating Modes for 32-bit/16-bit Timers 0 3 read-write polarity Timer I/O Polarity 8 9 read-write prescale Timer Clock Prescale Setting 4 8 read-write tmr2x16 Dual 16-bit Timer Mode 3 4 read-write INTEN Timer Module Interrupt Enable/Disable Settings 0x24 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Enable for 32-bit Timer / 16-bit Timer 0 0 1 read-write timer1 Interrupt Enable for 16-bit Timer 1 1 2 read-write INTFL Timer Module Interrupt Flags 0x20 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Flag for 32-bit Timer / 16-bit Timer 0 0 1 read-write oneToClear timer1 Interrupt Flag for 16-bit Timer 1 1 2 read-write oneToClear PWM_CAP32 [32 bit] PWM Compare Setting or Capture/Measure Value 0xC read-write n 0x0 0xFFFFFFFF TERM_CNT16_0 [16 bit] Terminal Count Setting, 16-bit Timer 0 0x14 read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT16_1 [16 bit] Terminal Count Setting, 16-bit Timer 1 0x1C read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT32 [32 bit] Terminal Count Setting 0x8 read-write n 0x0 0xFFFFFFFF TMR3 16/32 bit Timer/Counters Timers 0x4000E000 0x0 0x1000 registers n TMR3 Timer 3 IRQ 28 TMR16_3 16-bit Timer 3 IRQ 29 COUNT16_0 [16 bit] Current Count Value, 16-bit Timer 0 0x10 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT16_1 [16 bit] Current Count Value, 16-bit Timer 1 0x18 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT32 [32 bit] Current Count Value 0x4 read-write n 0x0 0xFFFFFFFF CTRL Timer Control Register 0x0 read-write n 0x0 0xFFFFFFFF enable0 Enable 32-bit timer / 16-bit timer 0 12 13 read-write enable1 Enable 16-bit timer 1 13 14 read-write mode Operating Modes for 32-bit/16-bit Timers 0 3 read-write polarity Timer I/O Polarity 8 9 read-write prescale Timer Clock Prescale Setting 4 8 read-write tmr2x16 Dual 16-bit Timer Mode 3 4 read-write INTEN Timer Module Interrupt Enable/Disable Settings 0x24 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Enable for 32-bit Timer / 16-bit Timer 0 0 1 read-write timer1 Interrupt Enable for 16-bit Timer 1 1 2 read-write INTFL Timer Module Interrupt Flags 0x20 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Flag for 32-bit Timer / 16-bit Timer 0 0 1 read-write oneToClear timer1 Interrupt Flag for 16-bit Timer 1 1 2 read-write oneToClear PWM_CAP32 [32 bit] PWM Compare Setting or Capture/Measure Value 0xC read-write n 0x0 0xFFFFFFFF TERM_CNT16_0 [16 bit] Terminal Count Setting, 16-bit Timer 0 0x14 read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT16_1 [16 bit] Terminal Count Setting, 16-bit Timer 1 0x1C read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT32 [32 bit] Terminal Count Setting 0x8 read-write n 0x0 0xFFFFFFFF TMR4 16/32 bit Timer/Counters Timers 0x4000F000 0x0 0x1000 registers n TMR4 Timer 4 IRQ 30 TMR16_4 16-bit Timer 4 IRQ 31 COUNT16_0 [16 bit] Current Count Value, 16-bit Timer 0 0x10 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT16_1 [16 bit] Current Count Value, 16-bit Timer 1 0x18 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT32 [32 bit] Current Count Value 0x4 read-write n 0x0 0xFFFFFFFF CTRL Timer Control Register 0x0 read-write n 0x0 0xFFFFFFFF enable0 Enable 32-bit timer / 16-bit timer 0 12 13 read-write enable1 Enable 16-bit timer 1 13 14 read-write mode Operating Modes for 32-bit/16-bit Timers 0 3 read-write polarity Timer I/O Polarity 8 9 read-write prescale Timer Clock Prescale Setting 4 8 read-write tmr2x16 Dual 16-bit Timer Mode 3 4 read-write INTEN Timer Module Interrupt Enable/Disable Settings 0x24 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Enable for 32-bit Timer / 16-bit Timer 0 0 1 read-write timer1 Interrupt Enable for 16-bit Timer 1 1 2 read-write INTFL Timer Module Interrupt Flags 0x20 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Flag for 32-bit Timer / 16-bit Timer 0 0 1 read-write oneToClear timer1 Interrupt Flag for 16-bit Timer 1 1 2 read-write oneToClear PWM_CAP32 [32 bit] PWM Compare Setting or Capture/Measure Value 0xC read-write n 0x0 0xFFFFFFFF TERM_CNT16_0 [16 bit] Terminal Count Setting, 16-bit Timer 0 0x14 read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT16_1 [16 bit] Terminal Count Setting, 16-bit Timer 1 0x1C read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT32 [32 bit] Terminal Count Setting 0x8 read-write n 0x0 0xFFFFFFFF TMR5 16/32 bit Timer/Counters Timers 0x40010000 0x0 0x1000 registers n TMR5 Timer 5 IRQ 32 TMR16_5 16-bit Timer 5 IRQ 33 COUNT16_0 [16 bit] Current Count Value, 16-bit Timer 0 0x10 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT16_1 [16 bit] Current Count Value, 16-bit Timer 1 0x18 read-write n 0x0 0xFFFFFFFF value Count Value 0 16 read-write COUNT32 [32 bit] Current Count Value 0x4 read-write n 0x0 0xFFFFFFFF CTRL Timer Control Register 0x0 read-write n 0x0 0xFFFFFFFF enable0 Enable 32-bit timer / 16-bit timer 0 12 13 read-write enable1 Enable 16-bit timer 1 13 14 read-write mode Operating Modes for 32-bit/16-bit Timers 0 3 read-write polarity Timer I/O Polarity 8 9 read-write prescale Timer Clock Prescale Setting 4 8 read-write tmr2x16 Dual 16-bit Timer Mode 3 4 read-write INTEN Timer Module Interrupt Enable/Disable Settings 0x24 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Enable for 32-bit Timer / 16-bit Timer 0 0 1 read-write timer1 Interrupt Enable for 16-bit Timer 1 1 2 read-write INTFL Timer Module Interrupt Flags 0x20 read-write n 0x0 0xFFFFFFFF timer0 Interrupt Flag for 32-bit Timer / 16-bit Timer 0 0 1 read-write oneToClear timer1 Interrupt Flag for 16-bit Timer 1 1 2 read-write oneToClear PWM_CAP32 [32 bit] PWM Compare Setting or Capture/Measure Value 0xC read-write n 0x0 0xFFFFFFFF TERM_CNT16_0 [16 bit] Terminal Count Setting, 16-bit Timer 0 0x14 read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT16_1 [16 bit] Terminal Count Setting, 16-bit Timer 1 0x1C read-write n 0x0 0xFFFFFFFF term_count Terminal Count Setting 0 16 read-write TERM_CNT32 [32 bit] Terminal Count Setting 0x8 read-write n 0x0 0xFFFFFFFF TPU Trust Protection Unit (TPU) TPU 0x40007000 0x0 0x400 registers n PRNG_RND_NUM PRNG Random Number Output 0x4 read-write n 0x0 0xFFFFFFFF PRNG_USER_ENTROPY PRNG User Entropy Value 0x0 read-write n 0x0 0xFFFFFFFF TPU_TSR Trust Protection Unit (TPU) TPU_TSR 0x40007C00 0x0 0x400 registers n SKS0 TPU Secure Key Storage Register 0 (Cleared on Tamper Detect) 0x10 read-write n 0x0 0xFFFFFFFF SKS1 TPU Secure Key Storage Register 1 (Cleared on Tamper Detect) 0x14 read-write n 0x0 0xFFFFFFFF SKS2 TPU Secure Key Storage Register 2 (Cleared on Tamper Detect) 0x18 read-write n 0x0 0xFFFFFFFF SKS3 TPU Secure Key Storage Register 3 (Cleared on Tamper Detect) 0x1C read-write n 0x0 0xFFFFFFFF UART0 UART / Serial Port Interface UARTs 0x40012000 0x0 0x1000 registers n UART0 UART 0 IRQ 34 BAUD UART Baud Control Register 0x4 read-write n 0x0 0xFFFFFFFF baud_divisor Baud Divisor 0 8 read-write CTRL UART Control Register 0x0 read-write n 0x0 0xFFFFFFFF cts_en CTS Enable 16 17 read-write cts_polarity CTS Polarity 17 18 read-write data_size Data Size 4 6 read-write extra_stop Extra Stop Enable 8 9 read-write parity Parity Mode 12 14 read-write rts_en RTS Enable 18 19 read-write rts_level RX FIFO LTE Level for RTS Assert 20 26 read-write rts_polarity RTS Polarity 19 20 read-write rx_fifo_en RX FIFO Enable 1 2 read-write tx_fifo_en TX FIFO Enable 2 3 read-write uart_en UART Enable 0 1 read-write INTEN UART Interrupt Enable/Disable Controls 0x18 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Enable/Disable 5 6 read-write rx_fifo_not_empty RX FIFO Not Empty Interrupt Enable/Disable 3 4 read-write rx_fifo_overflow RX FIFO Overflow Interrupt Enable/Disable 6 7 read-write rx_framing_err RX Framing Error Interrupt Enable/Disable 7 8 read-write rx_parity_err RX Parity Error Interrupt Enable/Disable 8 9 read-write rx_stalled RX Stalled Interrupt Enable/Disable 4 5 read-write tx_done TX Done Interrupt Enable/Disable 0 1 read-write tx_fifo_ae TX FIFO Almost Empty Interrupt Enable/Disable 2 3 read-write tx_unstalled TX Unstalled Interrupt Enable/Disable 1 2 read-write INTFL UART Interrupt Flags 0x14 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Flag 5 6 read-write oneToClear rx_fifo_not_empty RX FIFO Not Empty Interrupt Flag 3 4 read-write oneToClear rx_fifo_overflow RX FIFO Overflow Interrupt Flag 6 7 read-write oneToClear rx_framing_err RX Framing Error Interrupt Flag 7 8 read-write oneToClear rx_parity_err RX Parity Error Interrupt Flag 8 9 read-write oneToClear rx_stalled RX Stalled Interrupt Flag 4 5 read-write oneToClear tx_done TX Done Interrupt Flag 0 1 read-write oneToClear tx_fifo_ae TX FIFO Almost Empty Interrupt Flag 2 3 read-write oneToClear tx_unstalled TX Unstalled Interrupt Flag 1 2 read-write oneToClear MD_CTRL UART Multidrop Control Register 0x10 read-write n 0x0 0xFFFFFFFF md_mstr Multidrop Master 16 17 read-write slave_addr Slave Address 0 8 read-write slave_addr_msk Slave Address Mask 8 16 read-write tx_addr_mark RX Address Mark 17 18 read-write RX_FIFO_CTRL UART RX Fifo Control Register 0xC read-write n 0x0 0xFFFFFFFF fifo_af_lvl RX FIFO AF Level 16 22 read-write fifo_entry RX FIFO Entries 0 5 read-only TX_FIFO_CTRL UART TX Fifo Control Register 0x8 read-write n 0x0 0xFFFFFFFF fifo_ae_lvl TX FIFO AE Level 16 22 read-write fifo_entry TX FIFO Entries 0 5 read-only UART1 UART / Serial Port Interface UARTs 0x40013000 0x0 0x1000 registers n UART1 UART 1 IRQ 35 BAUD UART Baud Control Register 0x4 read-write n 0x0 0xFFFFFFFF baud_divisor Baud Divisor 0 8 read-write CTRL UART Control Register 0x0 read-write n 0x0 0xFFFFFFFF cts_en CTS Enable 16 17 read-write cts_polarity CTS Polarity 17 18 read-write data_size Data Size 4 6 read-write extra_stop Extra Stop Enable 8 9 read-write parity Parity Mode 12 14 read-write rts_en RTS Enable 18 19 read-write rts_level RX FIFO LTE Level for RTS Assert 20 26 read-write rts_polarity RTS Polarity 19 20 read-write rx_fifo_en RX FIFO Enable 1 2 read-write tx_fifo_en TX FIFO Enable 2 3 read-write uart_en UART Enable 0 1 read-write INTEN UART Interrupt Enable/Disable Controls 0x18 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Enable/Disable 5 6 read-write rx_fifo_not_empty RX FIFO Not Empty Interrupt Enable/Disable 3 4 read-write rx_fifo_overflow RX FIFO Overflow Interrupt Enable/Disable 6 7 read-write rx_framing_err RX Framing Error Interrupt Enable/Disable 7 8 read-write rx_parity_err RX Parity Error Interrupt Enable/Disable 8 9 read-write rx_stalled RX Stalled Interrupt Enable/Disable 4 5 read-write tx_done TX Done Interrupt Enable/Disable 0 1 read-write tx_fifo_ae TX FIFO Almost Empty Interrupt Enable/Disable 2 3 read-write tx_unstalled TX Unstalled Interrupt Enable/Disable 1 2 read-write INTFL UART Interrupt Flags 0x14 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Flag 5 6 read-write oneToClear rx_fifo_not_empty RX FIFO Not Empty Interrupt Flag 3 4 read-write oneToClear rx_fifo_overflow RX FIFO Overflow Interrupt Flag 6 7 read-write oneToClear rx_framing_err RX Framing Error Interrupt Flag 7 8 read-write oneToClear rx_parity_err RX Parity Error Interrupt Flag 8 9 read-write oneToClear rx_stalled RX Stalled Interrupt Flag 4 5 read-write oneToClear tx_done TX Done Interrupt Flag 0 1 read-write oneToClear tx_fifo_ae TX FIFO Almost Empty Interrupt Flag 2 3 read-write oneToClear tx_unstalled TX Unstalled Interrupt Flag 1 2 read-write oneToClear MD_CTRL UART Multidrop Control Register 0x10 read-write n 0x0 0xFFFFFFFF md_mstr Multidrop Master 16 17 read-write slave_addr Slave Address 0 8 read-write slave_addr_msk Slave Address Mask 8 16 read-write tx_addr_mark RX Address Mark 17 18 read-write RX_FIFO_CTRL UART RX Fifo Control Register 0xC read-write n 0x0 0xFFFFFFFF fifo_af_lvl RX FIFO AF Level 16 22 read-write fifo_entry RX FIFO Entries 0 5 read-only TX_FIFO_CTRL UART TX Fifo Control Register 0x8 read-write n 0x0 0xFFFFFFFF fifo_ae_lvl TX FIFO AE Level 16 22 read-write fifo_entry TX FIFO Entries 0 5 read-only UART2 UART / Serial Port Interface UARTs 0x40014000 0x0 0x1000 registers n UART2 UART 2 IRQ 36 BAUD UART Baud Control Register 0x4 read-write n 0x0 0xFFFFFFFF baud_divisor Baud Divisor 0 8 read-write CTRL UART Control Register 0x0 read-write n 0x0 0xFFFFFFFF cts_en CTS Enable 16 17 read-write cts_polarity CTS Polarity 17 18 read-write data_size Data Size 4 6 read-write extra_stop Extra Stop Enable 8 9 read-write parity Parity Mode 12 14 read-write rts_en RTS Enable 18 19 read-write rts_level RX FIFO LTE Level for RTS Assert 20 26 read-write rts_polarity RTS Polarity 19 20 read-write rx_fifo_en RX FIFO Enable 1 2 read-write tx_fifo_en TX FIFO Enable 2 3 read-write uart_en UART Enable 0 1 read-write INTEN UART Interrupt Enable/Disable Controls 0x18 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Enable/Disable 5 6 read-write rx_fifo_not_empty RX FIFO Not Empty Interrupt Enable/Disable 3 4 read-write rx_fifo_overflow RX FIFO Overflow Interrupt Enable/Disable 6 7 read-write rx_framing_err RX Framing Error Interrupt Enable/Disable 7 8 read-write rx_parity_err RX Parity Error Interrupt Enable/Disable 8 9 read-write rx_stalled RX Stalled Interrupt Enable/Disable 4 5 read-write tx_done TX Done Interrupt Enable/Disable 0 1 read-write tx_fifo_ae TX FIFO Almost Empty Interrupt Enable/Disable 2 3 read-write tx_unstalled TX Unstalled Interrupt Enable/Disable 1 2 read-write INTFL UART Interrupt Flags 0x14 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Flag 5 6 read-write oneToClear rx_fifo_not_empty RX FIFO Not Empty Interrupt Flag 3 4 read-write oneToClear rx_fifo_overflow RX FIFO Overflow Interrupt Flag 6 7 read-write oneToClear rx_framing_err RX Framing Error Interrupt Flag 7 8 read-write oneToClear rx_parity_err RX Parity Error Interrupt Flag 8 9 read-write oneToClear rx_stalled RX Stalled Interrupt Flag 4 5 read-write oneToClear tx_done TX Done Interrupt Flag 0 1 read-write oneToClear tx_fifo_ae TX FIFO Almost Empty Interrupt Flag 2 3 read-write oneToClear tx_unstalled TX Unstalled Interrupt Flag 1 2 read-write oneToClear MD_CTRL UART Multidrop Control Register 0x10 read-write n 0x0 0xFFFFFFFF md_mstr Multidrop Master 16 17 read-write slave_addr Slave Address 0 8 read-write slave_addr_msk Slave Address Mask 8 16 read-write tx_addr_mark RX Address Mark 17 18 read-write RX_FIFO_CTRL UART RX Fifo Control Register 0xC read-write n 0x0 0xFFFFFFFF fifo_af_lvl RX FIFO AF Level 16 22 read-write fifo_entry RX FIFO Entries 0 5 read-only TX_FIFO_CTRL UART TX Fifo Control Register 0x8 read-write n 0x0 0xFFFFFFFF fifo_ae_lvl TX FIFO AE Level 16 22 read-write fifo_entry TX FIFO Entries 0 5 read-only UART3 UART / Serial Port Interface UARTs 0x40015000 0x0 0x1000 registers n UART3 UART 3 IRQ 37 BAUD UART Baud Control Register 0x4 read-write n 0x0 0xFFFFFFFF baud_divisor Baud Divisor 0 8 read-write CTRL UART Control Register 0x0 read-write n 0x0 0xFFFFFFFF cts_en CTS Enable 16 17 read-write cts_polarity CTS Polarity 17 18 read-write data_size Data Size 4 6 read-write extra_stop Extra Stop Enable 8 9 read-write parity Parity Mode 12 14 read-write rts_en RTS Enable 18 19 read-write rts_level RX FIFO LTE Level for RTS Assert 20 26 read-write rts_polarity RTS Polarity 19 20 read-write rx_fifo_en RX FIFO Enable 1 2 read-write tx_fifo_en TX FIFO Enable 2 3 read-write uart_en UART Enable 0 1 read-write INTEN UART Interrupt Enable/Disable Controls 0x18 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Enable/Disable 5 6 read-write rx_fifo_not_empty RX FIFO Not Empty Interrupt Enable/Disable 3 4 read-write rx_fifo_overflow RX FIFO Overflow Interrupt Enable/Disable 6 7 read-write rx_framing_err RX Framing Error Interrupt Enable/Disable 7 8 read-write rx_parity_err RX Parity Error Interrupt Enable/Disable 8 9 read-write rx_stalled RX Stalled Interrupt Enable/Disable 4 5 read-write tx_done TX Done Interrupt Enable/Disable 0 1 read-write tx_fifo_ae TX FIFO Almost Empty Interrupt Enable/Disable 2 3 read-write tx_unstalled TX Unstalled Interrupt Enable/Disable 1 2 read-write INTFL UART Interrupt Flags 0x14 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Interrupt Flag 5 6 read-write oneToClear rx_fifo_not_empty RX FIFO Not Empty Interrupt Flag 3 4 read-write oneToClear rx_fifo_overflow RX FIFO Overflow Interrupt Flag 6 7 read-write oneToClear rx_framing_err RX Framing Error Interrupt Flag 7 8 read-write oneToClear rx_parity_err RX Parity Error Interrupt Flag 8 9 read-write oneToClear rx_stalled RX Stalled Interrupt Flag 4 5 read-write oneToClear tx_done TX Done Interrupt Flag 0 1 read-write oneToClear tx_fifo_ae TX FIFO Almost Empty Interrupt Flag 2 3 read-write oneToClear tx_unstalled TX Unstalled Interrupt Flag 1 2 read-write oneToClear MD_CTRL UART Multidrop Control Register 0x10 read-write n 0x0 0xFFFFFFFF md_mstr Multidrop Master 16 17 read-write slave_addr Slave Address 0 8 read-write slave_addr_msk Slave Address Mask 8 16 read-write tx_addr_mark RX Address Mark 17 18 read-write RX_FIFO_CTRL UART RX Fifo Control Register 0xC read-write n 0x0 0xFFFFFFFF fifo_af_lvl RX FIFO AF Level 16 22 read-write fifo_entry RX FIFO Entries 0 5 read-only TX_FIFO_CTRL UART TX Fifo Control Register 0x8 read-write n 0x0 0xFFFFFFFF fifo_ae_lvl TX FIFO AE Level 16 22 read-write fifo_entry TX FIFO Entries 0 5 read-only USB USB Device Controller USB 0x40100000 0x0 0x1000 registers n USB USB IRQ 8 BUF_OVR_INT USB Buffer Overflow Interrupt 0x240 read-write n 0x0 0xFFFFFFFF buf_ovr0 Endpoint 0 Buffer Overflow Interrupt Flag 0 1 read-write oneToClear buf_ovr1 Endpoint 1 Buffer Overflow Interrupt Flag 1 2 read-write oneToClear buf_ovr2 Endpoint 2 Buffer Overflow Interrupt Flag 2 3 read-write oneToClear buf_ovr3 Endpoint 3 Buffer Overflow Interrupt Flag 3 4 read-write oneToClear buf_ovr4 Endpoint 4 Buffer Overflow Interrupt Flag 4 5 read-write oneToClear buf_ovr5 Endpoint 5 Buffer Overflow Interrupt Flag 5 6 read-write oneToClear buf_ovr6 Endpoint 6 Buffer Overflow Interrupt Flag 6 7 read-write oneToClear buf_ovr7 Endpoint 7 Buffer Overflow Interrupt Flag 7 8 read-write oneToClear CN USB Control Register 0x0 read-write n 0x0 0xFFFFFFFF usb_en USB Device Interface Enable 0 1 read-write CUR_BUF USB Current Endpoint Buffer Register 0x224 read-write n 0x0 0xFFFFFFFF in_buf IN Transfer Current Buffers 16 24 read-only out_buf OUT Transfer Current Buffers 0 8 read-only DEV_ADDR USB Device Address Register 0x200 read-write n 0x0 0xFFFFFFFF dev_addr USB Device Address 0 7 read-only DEV_CN USB Device Control Register 0x204 read-write n 0x0 0xFFFFFFFF connect Connect to USB 3 4 read-write fifo_mode FIFO Mode 9 10 read-write sigrwu USB Signal Remote Wakeup 2 3 read-write ulpm USB Low Power Mode 4 5 read-write urst USB Device Controller Reset 5 6 read-write vbgate VBUS Gate 6 7 read-write DEV_INTEN USB Device Interrupt Enable 0x20C read-write n 0x0 0xFFFFFFFF bact USB Bus Activity Interrupt Flag 2 3 read-write brst USB Bus Reset In Progress Interrupt Flag 3 4 read-write brst_dn USB Bus Reset Completed Interrupt Flag 7 8 read-write buf_ovr Buffer Overflow Interrupt Flag 13 14 read-write dma_err DMA Error Interrupt Flag 12 13 read-write dpact DPLUS Activity Interrupt Flag 0 1 read-write ep_in Endpoint IN Interrupt Flag 9 10 read-write ep_nak Endpoint NAK Interrupt Flag 11 12 read-write ep_out Endpoint OUT Interrupt Flag 10 11 read-write no_vbus No VBUS Interrupt Flag 5 6 read-write rwu_dn Remote Wakeup Done Interrupt Flag 1 2 read-write setup Setup Packet Interrupt Flag 8 9 read-write susp USB Suspend Interrupt Flag 4 5 read-write vbus VBUS Detect Interrupt Flag 6 7 read-write DEV_INTFL USB Device Interrupt 0x208 read-write n 0x0 0xFFFFFFFF