Maxim
max32650
2024.04.28
MAX32650 32-bit ARM Cortex-M4 microcontroller with 1MB of system RAM and 3MB of flash memory.
CM4
r2p1
little
true
true
3
false
8
32
ADC
10-bit Analog to Digital Converter
ADC
0x0
0x0
0x1000
registers
n
ADC
ADC IRQ
20
CTRL
ADC Control
0x0
read-write
n
0x0
0x0
adc_xref
Enable Use of ADC External Reference
16
17
read-write
chgpump_pwr
ADC Charge Pump Power Up
4
5
read-write
ch_sel
ADC Channel Select
12
16
read-write
clk_en
ADC Clock Enable
11
12
read-write
data_align
ADC Data Alignment Select
17
18
read-write
pwr
ADC Power Up
1
2
read-write
refbuf_pwr
ADC Reference Buffer Power Up
3
4
read-write
ref_scale
ADC Reference Scale
8
9
read-write
ref_sel
ADC Reference (VRef) Select (INTERNAL ONLY)
10
11
read-write
scale
ADC Scale
9
10
read-write
start
Start ADC Conversion
0
1
read-write
DATA
ADC Output Data
0x8
read-write
n
0x0
0x0
adc_data
ADC Converted Sample Data Output
0
16
read-only
INTR
ADC Interrupt Control Register
0xC
read-write
n
0x0
0x0
done_ie
ADC Done Interrupt Enable
0
1
read-write
done_if
ADC Done Interrupt Flag
16
17
read-write
oneToClear
hi_limit_ie
ADC Hi Limit Monitor Interrupt Enable
2
3
read-write
hi_limit_if
ADC Hi Limit Monitor Interrupt Flag
18
19
read-write
oneToClear
lo_limit_ie
ADC Lo Limit Monitor Interrupt Enable
3
4
read-write
lo_limit_if
ADC Lo Limit Monitor Interrupt Flag
19
20
read-write
oneToClear
overflow_ie
ADC Overflow Interrupt Enable
4
5
read-write
overflow_if
ADC Overflow Interrupt Flag
20
21
read-write
oneToClear
pending
ADC Interrupt Pending Status
22
23
read-only
ref_ready_ie
ADC Reference Ready Interrupt Enable
1
2
read-write
ref_ready_if
ADC Reference Ready Interrupt Flag
17
18
read-write
oneToClear
LIMIT0
ADC Limit
0x10
-1
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
LIMIT1
ADC Limit
0x14
-1
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
LIMIT2
ADC Limit
0x18
-1
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
LIMIT3
ADC Limit
0x1C
-1
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
LIMIT[0]
ADC Limit
0x20
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
LIMIT[1]
ADC Limit
0x34
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
LIMIT[2]
ADC Limit
0x4C
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
LIMIT[3]
ADC Limit
0x68
read-write
n
0x0
0x0
ch_hi_limit
High Limit Threshold
12
22
read-write
ch_hi_limit_en
High Limit Monitoring Enable
29
30
read-write
ch_lo_limit
Low Limit Threshold
0
10
read-write
ch_lo_limit_en
Low Limit Monitoring Enable
28
29
read-write
ch_sel
ADC Channel Select
24
28
read-write
STATUS
ADC Status
0x4
read-write
n
0x0
0x0
active
ADC Conversion In Progress
0
1
read-only
afe_pwr_up_active
AFE Power Up Delay Active
2
3
read-only
overflow
ADC Overflow
3
4
read-only
AES_KEY
AES Keys.
AES_KEY
0x0
0x0
0x400
registers
n
aes_key0
AES Key 0
0x0
32
read-only
n
0x0
0x0
aes_key1
AES Key 1
0x80
read-only
n
0x0
0x0
aes_key2
AES Key 2
0x100
read-only
n
0x0
0x0
aes_key3
AES Key 3
0x180
read-only
n
0x0
0x0
BBFC
Battery-Backed Function Control.
BBFC
0x0
0x0
0x400
registers
n
BBFCR0
Function Control Register 0.
0x0
read-write
n
0x0
0x0
CKNPDRV
Hyperbus CKN Pad Driver Control.
4
4
CKPDRV
Hyperbus CK Pad Driver Control.
0
4
RDSDLLEN
Hyperbus RDS DLL Power Up Control.
8
1
dis
Disabled.
0
en
Enabled.
1
BBSIR
Battery-Backed Registers.
BBSIR
0x0
0x0
0x400
registers
n
BB_SIR2
System Init. Configuration Register 2.
0x8
read-only
n
0x0
0x0
BB_SIR3
System Init. Configuration Register 3.
0xC
read-only
n
0x0
0x0
CLCD
Color LCD Controller
CLCD
0x0
0x0
0xFFF
registers
n
CLK
LCD Clock Register
0x0
read-only
n
0x0
0x0
ACB
ACB
8
8
CLKDIV
Clock divsor
0
8
DPOL
D Polarity
16
1
ACTIVEHI
Active Hi
0
ACTIVELO
Active Low
1
EDGE
Edge Selection
19
1
POSEDGE
Positve edge
0
NEGEDGE
Negative Edge
1
HPOL
H Polarity
18
1
ACTIVELO
Active Low
0
ACTIVEHI
Active Hi
1
PASCLK
Clock Active on Data
20
1
ALWAYSACTIVE
Always Active
0
ACTIVEONDATA
ACTIVE ON DATA
1
VPOL
V Polarity
17
1
CTRL
LCD Control Register
0x10
read-only
n
0x0
0x0
BPP
BPP
8
3
BPP1
BPP 1
0
BPP2
BPP 2
1
BPP4
BPP 4
2
BPP8
BPP 8
3
BPP16
BPP 16
4
BPP24
BPP 24
5
BURST
BURST
19
2
WORDS4
WORDS4
0
WORDS8
WORDS8
1
C24
C24
15
1
DISPTYPE
Display Type
4
4
STNCOLOR8BIT
STN Color 8 bit
4
CLCD
CLCD
8
EMODE
EMODE
12
2
LLBP
LLBP
0
BBBP
BBBP
1
LBBP
LBBP
2
RFU
RFU
3
LCDEN
LCD Enable
0
1
DISABLE
Disable
0
ENABLE
Enable
1
LPOL
LPOL
21
1
ACTIVEHI
ACTIVE HIGH
0
ACTIVELO
ACTIVE LOW
1
MODE565
MODE565
11
1
MODE555
MODE 555
0
MODE565
MODE 565
1
PEN
PEN
22
1
VISEL
VI Select
1
2
ONVERTSYNC
On Vertical Sync
0
ONVERTBACKPORCH
On Vertical Back Porch
1
ONACTIVEVIDEO
On Active Video
2
ONVERTFRONTPORCH
On Vertical Front Porch
3
FR
FR
0x18
read-only
n
0x0
0x0
HTIM
LCD Horizontal Timing Register.
0xC
read-only
n
0x0
0x0
HBACKPORCH
Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP=(HBACKPORCH+1)
24
8
HFRONTPORCH
Horizontal Front Porch size in lines from 1 to 256
8
8
HSIZE
Horizontal Front Porch Size in Pixels = (HSIZE + 1)*16
16
8
HSYNCWIDTH
Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks
0
8
HV_PHASE
HV Phase
0x30
read-only
n
0x0
0x0
INT_EN
LCD Interrupt Enable Register.
0x20
read-only
n
0x0
0x0
ADRRDY
Address Ready Interupt Enable
1
1
BERR
BERR Interupt Enable
3
1
UFLO
Under FLow Interupt Enable
0
1
VCI
VCI Interupt Enable
2
1
PALETTE0
Palette
0x400
-1
read-only
n
0x0
0x0
PALETTE1
Palette
0x404
-1
read-only
n
0x0
0x0
PALETTE10
Palette
0x428
-1
read-only
n
0x0
0x0
PALETTE100
Palette
0x590
-1
read-only
n
0x0
0x0
PALETTE101
Palette
0x594
-1
read-only
n
0x0
0x0
PALETTE102
Palette
0x598
-1
read-only
n
0x0
0x0
PALETTE103
Palette
0x59C
-1
read-only
n
0x0
0x0
PALETTE104
Palette
0x5A0
-1
read-only
n
0x0
0x0
PALETTE105
Palette
0x5A4
-1
read-only
n
0x0
0x0
PALETTE106
Palette
0x5A8
-1
read-only
n
0x0
0x0
PALETTE107
Palette
0x5AC
-1
read-only
n
0x0
0x0
PALETTE108
Palette
0x5B0
-1
read-only
n
0x0
0x0
PALETTE109
Palette
0x5B4
-1
read-only
n
0x0
0x0
PALETTE11
Palette
0x42C
-1
read-only
n
0x0
0x0
PALETTE110
Palette
0x5B8
-1
read-only
n
0x0
0x0
PALETTE111
Palette
0x5BC
-1
read-only
n
0x0
0x0
PALETTE112
Palette
0x5C0
-1
read-only
n
0x0
0x0
PALETTE113
Palette
0x5C4
-1
read-only
n
0x0
0x0
PALETTE114
Palette
0x5C8
-1
read-only
n
0x0
0x0
PALETTE115
Palette
0x5CC
-1
read-only
n
0x0
0x0
PALETTE116
Palette
0x5D0
-1
read-only
n
0x0
0x0
PALETTE117
Palette
0x5D4
-1
read-only
n
0x0
0x0
PALETTE118
Palette
0x5D8
-1
read-only
n
0x0
0x0
PALETTE119
Palette
0x5DC
-1
read-only
n
0x0
0x0
PALETTE12
Palette
0x430
-1
read-only
n
0x0
0x0
PALETTE120
Palette
0x5E0
-1
read-only
n
0x0
0x0
PALETTE121
Palette
0x5E4
-1
read-only
n
0x0
0x0
PALETTE122
Palette
0x5E8
-1
read-only
n
0x0
0x0
PALETTE123
Palette
0x5EC
-1
read-only
n
0x0
0x0
PALETTE124
Palette
0x5F0
-1
read-only
n
0x0
0x0
PALETTE125
Palette
0x5F4
-1
read-only
n
0x0
0x0
PALETTE126
Palette
0x5F8
-1
read-only
n
0x0
0x0
PALETTE127
Palette
0x5FC
-1
read-only
n
0x0
0x0
PALETTE128
Palette
0x600
-1
read-only
n
0x0
0x0
PALETTE129
Palette
0x604
-1
read-only
n
0x0
0x0
PALETTE13
Palette
0x434
-1
read-only
n
0x0
0x0
PALETTE130
Palette
0x608
-1
read-only
n
0x0
0x0
PALETTE131
Palette
0x60C
-1
read-only
n
0x0
0x0
PALETTE132
Palette
0x610
-1
read-only
n
0x0
0x0
PALETTE133
Palette
0x614
-1
read-only
n
0x0
0x0
PALETTE134
Palette
0x618
-1
read-only
n
0x0
0x0
PALETTE135
Palette
0x61C
-1
read-only
n
0x0
0x0
PALETTE136
Palette
0x620
-1
read-only
n
0x0
0x0
PALETTE137
Palette
0x624
-1
read-only
n
0x0
0x0
PALETTE138
Palette
0x628
-1
read-only
n
0x0
0x0
PALETTE139
Palette
0x62C
-1
read-only
n
0x0
0x0
PALETTE14
Palette
0x438
-1
read-only
n
0x0
0x0
PALETTE140
Palette
0x630
-1
read-only
n
0x0
0x0
PALETTE141
Palette
0x634
-1
read-only
n
0x0
0x0
PALETTE142
Palette
0x638
-1
read-only
n
0x0
0x0
PALETTE143
Palette
0x63C
-1
read-only
n
0x0
0x0
PALETTE144
Palette
0x640
-1
read-only
n
0x0
0x0
PALETTE145
Palette
0x644
-1
read-only
n
0x0
0x0
PALETTE146
Palette
0x648
-1
read-only
n
0x0
0x0
PALETTE147
Palette
0x64C
-1
read-only
n
0x0
0x0
PALETTE148
Palette
0x650
-1
read-only
n
0x0
0x0
PALETTE149
Palette
0x654
-1
read-only
n
0x0
0x0
PALETTE15
Palette
0x43C
-1
read-only
n
0x0
0x0
PALETTE150
Palette
0x658
-1
read-only
n
0x0
0x0
PALETTE151
Palette
0x65C
-1
read-only
n
0x0
0x0
PALETTE152
Palette
0x660
-1
read-only
n
0x0
0x0
PALETTE153
Palette
0x664
-1
read-only
n
0x0
0x0
PALETTE154
Palette
0x668
-1
read-only
n
0x0
0x0
PALETTE155
Palette
0x66C
-1
read-only
n
0x0
0x0
PALETTE156
Palette
0x670
-1
read-only
n
0x0
0x0
PALETTE157
Palette
0x674
-1
read-only
n
0x0
0x0
PALETTE158
Palette
0x678
-1
read-only
n
0x0
0x0
PALETTE159
Palette
0x67C
-1
read-only
n
0x0
0x0
PALETTE16
Palette
0x440
-1
read-only
n
0x0
0x0
PALETTE160
Palette
0x680
-1
read-only
n
0x0
0x0
PALETTE161
Palette
0x684
-1
read-only
n
0x0
0x0
PALETTE162
Palette
0x688
-1
read-only
n
0x0
0x0
PALETTE163
Palette
0x68C
-1
read-only
n
0x0
0x0
PALETTE164
Palette
0x690
-1
read-only
n
0x0
0x0
PALETTE165
Palette
0x694
-1
read-only
n
0x0
0x0
PALETTE166
Palette
0x698
-1
read-only
n
0x0
0x0
PALETTE167
Palette
0x69C
-1
read-only
n
0x0
0x0
PALETTE168
Palette
0x6A0
-1
read-only
n
0x0
0x0
PALETTE169
Palette
0x6A4
-1
read-only
n
0x0
0x0
PALETTE17
Palette
0x444
-1
read-only
n
0x0
0x0
PALETTE170
Palette
0x6A8
-1
read-only
n
0x0
0x0
PALETTE171
Palette
0x6AC
-1
read-only
n
0x0
0x0
PALETTE172
Palette
0x6B0
-1
read-only
n
0x0
0x0
PALETTE173
Palette
0x6B4
-1
read-only
n
0x0
0x0
PALETTE174
Palette
0x6B8
-1
read-only
n
0x0
0x0
PALETTE175
Palette
0x6BC
-1
read-only
n
0x0
0x0
PALETTE176
Palette
0x6C0
-1
read-only
n
0x0
0x0
PALETTE177
Palette
0x6C4
-1
read-only
n
0x0
0x0
PALETTE178
Palette
0x6C8
-1
read-only
n
0x0
0x0
PALETTE179
Palette
0x6CC
-1
read-only
n
0x0
0x0
PALETTE18
Palette
0x448
-1
read-only
n
0x0
0x0
PALETTE180
Palette
0x6D0
-1
read-only
n
0x0
0x0
PALETTE181
Palette
0x6D4
-1
read-only
n
0x0
0x0
PALETTE182
Palette
0x6D8
-1
read-only
n
0x0
0x0
PALETTE183
Palette
0x6DC
-1
read-only
n
0x0
0x0
PALETTE184
Palette
0x6E0
-1
read-only
n
0x0
0x0
PALETTE185
Palette
0x6E4
-1
read-only
n
0x0
0x0
PALETTE186
Palette
0x6E8
-1
read-only
n
0x0
0x0
PALETTE187
Palette
0x6EC
-1
read-only
n
0x0
0x0
PALETTE188
Palette
0x6F0
-1
read-only
n
0x0
0x0
PALETTE189
Palette
0x6F4
-1
read-only
n
0x0
0x0
PALETTE19
Palette
0x44C
-1
read-only
n
0x0
0x0
PALETTE190
Palette
0x6F8
-1
read-only
n
0x0
0x0
PALETTE191
Palette
0x6FC
-1
read-only
n
0x0
0x0
PALETTE192
Palette
0x700
-1
read-only
n
0x0
0x0
PALETTE193
Palette
0x704
-1
read-only
n
0x0
0x0
PALETTE194
Palette
0x708
-1
read-only
n
0x0
0x0
PALETTE195
Palette
0x70C
-1
read-only
n
0x0
0x0
PALETTE196
Palette
0x710
-1
read-only
n
0x0
0x0
PALETTE197
Palette
0x714
-1
read-only
n
0x0
0x0
PALETTE198
Palette
0x718
-1
read-only
n
0x0
0x0
PALETTE199
Palette
0x71C
-1
read-only
n
0x0
0x0
PALETTE2
Palette
0x408
-1
read-only
n
0x0
0x0
PALETTE20
Palette
0x450
-1
read-only
n
0x0
0x0
PALETTE200
Palette
0x720
-1
read-only
n
0x0
0x0
PALETTE201
Palette
0x724
-1
read-only
n
0x0
0x0
PALETTE202
Palette
0x728
-1
read-only
n
0x0
0x0
PALETTE203
Palette
0x72C
-1
read-only
n
0x0
0x0
PALETTE204
Palette
0x730
-1
read-only
n
0x0
0x0
PALETTE205
Palette
0x734
-1
read-only
n
0x0
0x0
PALETTE206
Palette
0x738
-1
read-only
n
0x0
0x0
PALETTE207
Palette
0x73C
-1
read-only
n
0x0
0x0
PALETTE208
Palette
0x740
-1
read-only
n
0x0
0x0
PALETTE209
Palette
0x744
-1
read-only
n
0x0
0x0
PALETTE21
Palette
0x454
-1
read-only
n
0x0
0x0
PALETTE210
Palette
0x748
-1
read-only
n
0x0
0x0
PALETTE211
Palette
0x74C
-1
read-only
n
0x0
0x0
PALETTE212
Palette
0x750
-1
read-only
n
0x0
0x0
PALETTE213
Palette
0x754
-1
read-only
n
0x0
0x0
PALETTE214
Palette
0x758
-1
read-only
n
0x0
0x0
PALETTE215
Palette
0x75C
-1
read-only
n
0x0
0x0
PALETTE216
Palette
0x760
-1
read-only
n
0x0
0x0
PALETTE217
Palette
0x764
-1
read-only
n
0x0
0x0
PALETTE218
Palette
0x768
-1
read-only
n
0x0
0x0
PALETTE219
Palette
0x76C
-1
read-only
n
0x0
0x0
PALETTE22
Palette
0x458
-1
read-only
n
0x0
0x0
PALETTE220
Palette
0x770
-1
read-only
n
0x0
0x0
PALETTE221
Palette
0x774
-1
read-only
n
0x0
0x0
PALETTE222
Palette
0x778
-1
read-only
n
0x0
0x0
PALETTE223
Palette
0x77C
-1
read-only
n
0x0
0x0
PALETTE224
Palette
0x780
-1
read-only
n
0x0
0x0
PALETTE225
Palette
0x784
-1
read-only
n
0x0
0x0
PALETTE226
Palette
0x788
-1
read-only
n
0x0
0x0
PALETTE227
Palette
0x78C
-1
read-only
n
0x0
0x0
PALETTE228
Palette
0x790
-1
read-only
n
0x0
0x0
PALETTE229
Palette
0x794
-1
read-only
n
0x0
0x0
PALETTE23
Palette
0x45C
-1
read-only
n
0x0
0x0
PALETTE230
Palette
0x798
-1
read-only
n
0x0
0x0
PALETTE231
Palette
0x79C
-1
read-only
n
0x0
0x0
PALETTE232
Palette
0x7A0
-1
read-only
n
0x0
0x0
PALETTE233
Palette
0x7A4
-1
read-only
n
0x0
0x0
PALETTE234
Palette
0x7A8
-1
read-only
n
0x0
0x0
PALETTE235
Palette
0x7AC
-1
read-only
n
0x0
0x0
PALETTE236
Palette
0x7B0
-1
read-only
n
0x0
0x0
PALETTE237
Palette
0x7B4
-1
read-only
n
0x0
0x0
PALETTE238
Palette
0x7B8
-1
read-only
n
0x0
0x0
PALETTE239
Palette
0x7BC
-1
read-only
n
0x0
0x0
PALETTE24
Palette
0x460
-1
read-only
n
0x0
0x0
PALETTE240
Palette
0x7C0
-1
read-only
n
0x0
0x0
PALETTE241
Palette
0x7C4
-1
read-only
n
0x0
0x0
PALETTE242
Palette
0x7C8
-1
read-only
n
0x0
0x0
PALETTE243
Palette
0x7CC
-1
read-only
n
0x0
0x0
PALETTE244
Palette
0x7D0
-1
read-only
n
0x0
0x0
PALETTE245
Palette
0x7D4
-1
read-only
n
0x0
0x0
PALETTE246
Palette
0x7D8
-1
read-only
n
0x0
0x0
PALETTE247
Palette
0x7DC
-1
read-only
n
0x0
0x0
PALETTE248
Palette
0x7E0
-1
read-only
n
0x0
0x0
PALETTE249
Palette
0x7E4
-1
read-only
n
0x0
0x0
PALETTE25
Palette
0x464
-1
read-only
n
0x0
0x0
PALETTE250
Palette
0x7E8
-1
read-only
n
0x0
0x0
PALETTE251
Palette
0x7EC
-1
read-only
n
0x0
0x0
PALETTE252
Palette
0x7F0
-1
read-only
n
0x0
0x0
PALETTE253
Palette
0x7F4
-1
read-only
n
0x0
0x0
PALETTE254
Palette
0x7F8
-1
read-only
n
0x0
0x0
PALETTE255
Palette
0x7FC
-1
read-only
n
0x0
0x0
PALETTE26
Palette
0x468
-1
read-only
n
0x0
0x0
PALETTE27
Palette
0x46C
-1
read-only
n
0x0
0x0
PALETTE28
Palette
0x470
-1
read-only
n
0x0
0x0
PALETTE29
Palette
0x474
-1
read-only
n
0x0
0x0
PALETTE3
Palette
0x40C
-1
read-only
n
0x0
0x0
PALETTE30
Palette
0x478
-1
read-only
n
0x0
0x0
PALETTE31
Palette
0x47C
-1
read-only
n
0x0
0x0
PALETTE32
Palette
0x480
-1
read-only
n
0x0
0x0
PALETTE33
Palette
0x484
-1
read-only
n
0x0
0x0
PALETTE34
Palette
0x488
-1
read-only
n
0x0
0x0
PALETTE35
Palette
0x48C
-1
read-only
n
0x0
0x0
PALETTE36
Palette
0x490
-1
read-only
n
0x0
0x0
PALETTE37
Palette
0x494
-1
read-only
n
0x0
0x0
PALETTE38
Palette
0x498
-1
read-only
n
0x0
0x0
PALETTE39
Palette
0x49C
-1
read-only
n
0x0
0x0
PALETTE4
Palette
0x410
-1
read-only
n
0x0
0x0
PALETTE40
Palette
0x4A0
-1
read-only
n
0x0
0x0
PALETTE41
Palette
0x4A4
-1
read-only
n
0x0
0x0
PALETTE42
Palette
0x4A8
-1
read-only
n
0x0
0x0
PALETTE43
Palette
0x4AC
-1
read-only
n
0x0
0x0
PALETTE44
Palette
0x4B0
-1
read-only
n
0x0
0x0
PALETTE45
Palette
0x4B4
-1
read-only
n
0x0
0x0
PALETTE46
Palette
0x4B8
-1
read-only
n
0x0
0x0
PALETTE47
Palette
0x4BC
-1
read-only
n
0x0
0x0
PALETTE48
Palette
0x4C0
-1
read-only
n
0x0
0x0
PALETTE49
Palette
0x4C4
-1
read-only
n
0x0
0x0
PALETTE5
Palette
0x414
-1
read-only
n
0x0
0x0
PALETTE50
Palette
0x4C8
-1
read-only
n
0x0
0x0
PALETTE51
Palette
0x4CC
-1
read-only
n
0x0
0x0
PALETTE52
Palette
0x4D0
-1
read-only
n
0x0
0x0
PALETTE53
Palette
0x4D4
-1
read-only
n
0x0
0x0
PALETTE54
Palette
0x4D8
-1
read-only
n
0x0
0x0
PALETTE55
Palette
0x4DC
-1
read-only
n
0x0
0x0
PALETTE56
Palette
0x4E0
-1
read-only
n
0x0
0x0
PALETTE57
Palette
0x4E4
-1
read-only
n
0x0
0x0
PALETTE58
Palette
0x4E8
-1
read-only
n
0x0
0x0
PALETTE59
Palette
0x4EC
-1
read-only
n
0x0
0x0
PALETTE6
Palette
0x418
-1
read-only
n
0x0
0x0
PALETTE60
Palette
0x4F0
-1
read-only
n
0x0
0x0
PALETTE61
Palette
0x4F4
-1
read-only
n
0x0
0x0
PALETTE62
Palette
0x4F8
-1
read-only
n
0x0
0x0
PALETTE63
Palette
0x4FC
-1
read-only
n
0x0
0x0
PALETTE64
Palette
0x500
-1
read-only
n
0x0
0x0
PALETTE65
Palette
0x504
-1
read-only
n
0x0
0x0
PALETTE66
Palette
0x508
-1
read-only
n
0x0
0x0
PALETTE67
Palette
0x50C
-1
read-only
n
0x0
0x0
PALETTE68
Palette
0x510
-1
read-only
n
0x0
0x0
PALETTE69
Palette
0x514
-1
read-only
n
0x0
0x0
PALETTE7
Palette
0x41C
-1
read-only
n
0x0
0x0
PALETTE70
Palette
0x518
-1
read-only
n
0x0
0x0
PALETTE71
Palette
0x51C
-1
read-only
n
0x0
0x0
PALETTE72
Palette
0x520
-1
read-only
n
0x0
0x0
PALETTE73
Palette
0x524
-1
read-only
n
0x0
0x0
PALETTE74
Palette
0x528
-1
read-only
n
0x0
0x0
PALETTE75
Palette
0x52C
-1
read-only
n
0x0
0x0
PALETTE76
Palette
0x530
-1
read-only
n
0x0
0x0
PALETTE77
Palette
0x534
-1
read-only
n
0x0
0x0
PALETTE78
Palette
0x538
-1
read-only
n
0x0
0x0
PALETTE79
Palette
0x53C
-1
read-only
n
0x0
0x0
PALETTE8
Palette
0x420
-1
read-only
n
0x0
0x0
PALETTE80
Palette
0x540
-1
read-only
n
0x0
0x0
PALETTE81
Palette
0x544
-1
read-only
n
0x0
0x0
PALETTE82
Palette
0x548
-1
read-only
n
0x0
0x0
PALETTE83
Palette
0x54C
-1
read-only
n
0x0
0x0
PALETTE84
Palette
0x550
-1
read-only
n
0x0
0x0
PALETTE85
Palette
0x554
-1
read-only
n
0x0
0x0
PALETTE86
Palette
0x558
-1
read-only
n
0x0
0x0
PALETTE87
Palette
0x55C
-1
read-only
n
0x0
0x0
PALETTE88
Palette
0x560
-1
read-only
n
0x0
0x0
PALETTE89
Palette
0x564
-1
read-only
n
0x0
0x0
PALETTE9
Palette
0x424
-1
read-only
n
0x0
0x0
PALETTE90
Palette
0x568
-1
read-only
n
0x0
0x0
PALETTE91
Palette
0x56C
-1
read-only
n
0x0
0x0
PALETTE92
Palette
0x570
-1
read-only
n
0x0
0x0
PALETTE93
Palette
0x574
-1
read-only
n
0x0
0x0
PALETTE94
Palette
0x578
-1
read-only
n
0x0
0x0
PALETTE95
Palette
0x57C
-1
read-only
n
0x0
0x0
PALETTE96
Palette
0x580
-1
read-only
n
0x0
0x0
PALETTE97
Palette
0x584
-1
read-only
n
0x0
0x0
PALETTE98
Palette
0x588
-1
read-only
n
0x0
0x0
PALETTE99
Palette
0x58C
-1
read-only
n
0x0
0x0
PALETTE[0]
Palette
0x800
read-only
n
0x0
0x0
PALETTE[100]
Palette
0x1E6E8
read-only
n
0x0
0x0
PALETTE[101]
Palette
0x1EC7C
read-only
n
0x0
0x0
PALETTE[102]
Palette
0x1F214
read-only
n
0x0
0x0
PALETTE[103]
Palette
0x1F7B0
read-only
n
0x0
0x0
PALETTE[104]
Palette
0x1FD50
read-only
n
0x0
0x0
PALETTE[105]
Palette
0x202F4
read-only
n
0x0
0x0
PALETTE[106]
Palette
0x2089C
read-only
n
0x0
0x0
PALETTE[107]
Palette
0x20E48
read-only
n
0x0
0x0
PALETTE[108]
Palette
0x213F8
read-only
n
0x0
0x0
PALETTE[109]
Palette
0x219AC
read-only
n
0x0
0x0
PALETTE[10]
Palette
0x30DC
read-only
n
0x0
0x0
PALETTE[110]
Palette
0x21F64
read-only
n
0x0
0x0
PALETTE[111]
Palette
0x22520
read-only
n
0x0
0x0
PALETTE[112]
Palette
0x22AE0
read-only
n
0x0
0x0
PALETTE[113]
Palette
0x230A4
read-only
n
0x0
0x0
PALETTE[114]
Palette
0x2366C
read-only
n
0x0
0x0
PALETTE[115]
Palette
0x23C38
read-only
n
0x0
0x0
PALETTE[116]
Palette
0x24208
read-only
n
0x0
0x0
PALETTE[117]
Palette
0x247DC
read-only
n
0x0
0x0
PALETTE[118]
Palette
0x24DB4
read-only
n
0x0
0x0
PALETTE[119]
Palette
0x25390
read-only
n
0x0
0x0
PALETTE[11]
Palette
0x3508
read-only
n
0x0
0x0
PALETTE[120]
Palette
0x25970
read-only
n
0x0
0x0
PALETTE[121]
Palette
0x25F54
read-only
n
0x0
0x0
PALETTE[122]
Palette
0x2653C
read-only
n
0x0
0x0
PALETTE[123]
Palette
0x26B28
read-only
n
0x0
0x0
PALETTE[124]
Palette
0x27118
read-only
n
0x0
0x0
PALETTE[125]
Palette
0x2770C
read-only
n
0x0
0x0
PALETTE[126]
Palette
0x27D04
read-only
n
0x0
0x0
PALETTE[127]
Palette
0x28300
read-only
n
0x0
0x0
PALETTE[128]
Palette
0x28900
read-only
n
0x0
0x0
PALETTE[129]
Palette
0x28F04
read-only
n
0x0
0x0
PALETTE[12]
Palette
0x3938
read-only
n
0x0
0x0
PALETTE[130]
Palette
0x2950C
read-only
n
0x0
0x0
PALETTE[131]
Palette
0x29B18
read-only
n
0x0
0x0
PALETTE[132]
Palette
0x2A128
read-only
n
0x0
0x0
PALETTE[133]
Palette
0x2A73C
read-only
n
0x0
0x0
PALETTE[134]
Palette
0x2AD54
read-only
n
0x0
0x0
PALETTE[135]
Palette
0x2B370
read-only
n
0x0
0x0
PALETTE[136]
Palette
0x2B990
read-only
n
0x0
0x0
PALETTE[137]
Palette
0x2BFB4
read-only
n
0x0
0x0
PALETTE[138]
Palette
0x2C5DC
read-only
n
0x0
0x0
PALETTE[139]
Palette
0x2CC08
read-only
n
0x0
0x0
PALETTE[13]
Palette
0x3D6C
read-only
n
0x0
0x0
PALETTE[140]
Palette
0x2D238
read-only
n
0x0
0x0
PALETTE[141]
Palette
0x2D86C
read-only
n
0x0
0x0
PALETTE[142]
Palette
0x2DEA4
read-only
n
0x0
0x0
PALETTE[143]
Palette
0x2E4E0
read-only
n
0x0
0x0
PALETTE[144]
Palette
0x2EB20
read-only
n
0x0
0x0
PALETTE[145]
Palette
0x2F164
read-only
n
0x0
0x0
PALETTE[146]
Palette
0x2F7AC
read-only
n
0x0
0x0
PALETTE[147]
Palette
0x2FDF8
read-only
n
0x0
0x0
PALETTE[148]
Palette
0x30448
read-only
n
0x0
0x0
PALETTE[149]
Palette
0x30A9C
read-only
n
0x0
0x0
PALETTE[14]
Palette
0x41A4
read-only
n
0x0
0x0
PALETTE[150]
Palette
0x310F4
read-only
n
0x0
0x0
PALETTE[151]
Palette
0x31750
read-only
n
0x0
0x0
PALETTE[152]
Palette
0x31DB0
read-only
n
0x0
0x0
PALETTE[153]
Palette
0x32414
read-only
n
0x0
0x0
PALETTE[154]
Palette
0x32A7C
read-only
n
0x0
0x0
PALETTE[155]
Palette
0x330E8
read-only
n
0x0
0x0
PALETTE[156]
Palette
0x33758
read-only
n
0x0
0x0
PALETTE[157]
Palette
0x33DCC
read-only
n
0x0
0x0
PALETTE[158]
Palette
0x34444
read-only
n
0x0
0x0
PALETTE[159]
Palette
0x34AC0
read-only
n
0x0
0x0
PALETTE[15]
Palette
0x45E0
read-only
n
0x0
0x0
PALETTE[160]
Palette
0x35140
read-only
n
0x0
0x0
PALETTE[161]
Palette
0x357C4
read-only
n
0x0
0x0
PALETTE[162]
Palette
0x35E4C
read-only
n
0x0
0x0
PALETTE[163]
Palette
0x364D8
read-only
n
0x0
0x0
PALETTE[164]
Palette
0x36B68
read-only
n
0x0
0x0
PALETTE[165]
Palette
0x371FC
read-only
n
0x0
0x0
PALETTE[166]
Palette
0x37894
read-only
n
0x0
0x0
PALETTE[167]
Palette
0x37F30
read-only
n
0x0
0x0
PALETTE[168]
Palette
0x385D0
read-only
n
0x0
0x0
PALETTE[169]
Palette
0x38C74
read-only
n
0x0
0x0
PALETTE[16]
Palette
0x4A20
read-only
n
0x0
0x0
PALETTE[170]
Palette
0x3931C
read-only
n
0x0
0x0
PALETTE[171]
Palette
0x399C8
read-only
n
0x0
0x0
PALETTE[172]
Palette
0x3A078
read-only
n
0x0
0x0
PALETTE[173]
Palette
0x3A72C
read-only
n
0x0
0x0
PALETTE[174]
Palette
0x3ADE4
read-only
n
0x0
0x0
PALETTE[175]
Palette
0x3B4A0
read-only
n
0x0
0x0
PALETTE[176]
Palette
0x3BB60
read-only
n
0x0
0x0
PALETTE[177]
Palette
0x3C224
read-only
n
0x0
0x0
PALETTE[178]
Palette
0x3C8EC
read-only
n
0x0
0x0
PALETTE[179]
Palette
0x3CFB8
read-only
n
0x0
0x0
PALETTE[17]
Palette
0x4E64
read-only
n
0x0
0x0
PALETTE[180]
Palette
0x3D688
read-only
n
0x0
0x0
PALETTE[181]
Palette
0x3DD5C
read-only
n
0x0
0x0
PALETTE[182]
Palette
0x3E434
read-only
n
0x0
0x0
PALETTE[183]
Palette
0x3EB10
read-only
n
0x0
0x0
PALETTE[184]
Palette
0x3F1F0
read-only
n
0x0
0x0
PALETTE[185]
Palette
0x3F8D4
read-only
n
0x0
0x0
PALETTE[186]
Palette
0x3FFBC
read-only
n
0x0
0x0
PALETTE[187]
Palette
0x406A8
read-only
n
0x0
0x0
PALETTE[188]
Palette
0x40D98
read-only
n
0x0
0x0
PALETTE[189]
Palette
0x4148C
read-only
n
0x0
0x0
PALETTE[18]
Palette
0x52AC
read-only
n
0x0
0x0
PALETTE[190]
Palette
0x41B84
read-only
n
0x0
0x0
PALETTE[191]
Palette
0x42280
read-only
n
0x0
0x0
PALETTE[192]
Palette
0x42980
read-only
n
0x0
0x0
PALETTE[193]
Palette
0x43084
read-only
n
0x0
0x0
PALETTE[194]
Palette
0x4378C
read-only
n
0x0
0x0
PALETTE[195]
Palette
0x43E98
read-only
n
0x0
0x0
PALETTE[196]
Palette
0x445A8
read-only
n
0x0
0x0
PALETTE[197]
Palette
0x44CBC
read-only
n
0x0
0x0
PALETTE[198]
Palette
0x453D4
read-only
n
0x0
0x0
PALETTE[199]
Palette
0x45AF0
read-only
n
0x0
0x0
PALETTE[19]
Palette
0x56F8
read-only
n
0x0
0x0
PALETTE[1]
Palette
0xC04
read-only
n
0x0
0x0
PALETTE[200]
Palette
0x46210
read-only
n
0x0
0x0
PALETTE[201]
Palette
0x46934
read-only
n
0x0
0x0
PALETTE[202]
Palette
0x4705C
read-only
n
0x0
0x0
PALETTE[203]
Palette
0x47788
read-only
n
0x0
0x0
PALETTE[204]
Palette
0x47EB8
read-only
n
0x0
0x0
PALETTE[205]
Palette
0x485EC
read-only
n
0x0
0x0
PALETTE[206]
Palette
0x48D24
read-only
n
0x0
0x0
PALETTE[207]
Palette
0x49460
read-only
n
0x0
0x0
PALETTE[208]
Palette
0x49BA0
read-only
n
0x0
0x0
PALETTE[209]
Palette
0x4A2E4
read-only
n
0x0
0x0
PALETTE[20]
Palette
0x5B48
read-only
n
0x0
0x0
PALETTE[210]
Palette
0x4AA2C
read-only
n
0x0
0x0
PALETTE[211]
Palette
0x4B178
read-only
n
0x0
0x0
PALETTE[212]
Palette
0x4B8C8
read-only
n
0x0
0x0
PALETTE[213]
Palette
0x4C01C
read-only
n
0x0
0x0
PALETTE[214]
Palette
0x4C774
read-only
n
0x0
0x0
PALETTE[215]
Palette
0x4CED0
read-only
n
0x0
0x0
PALETTE[216]
Palette
0x4D630
read-only
n
0x0
0x0
PALETTE[217]
Palette
0x4DD94
read-only
n
0x0
0x0
PALETTE[218]
Palette
0x4E4FC
read-only
n
0x0
0x0
PALETTE[219]
Palette
0x4EC68
read-only
n
0x0
0x0
PALETTE[21]
Palette
0x5F9C
read-only
n
0x0
0x0
PALETTE[220]
Palette
0x4F3D8
read-only
n
0x0
0x0
PALETTE[221]
Palette
0x4FB4C
read-only
n
0x0
0x0
PALETTE[222]
Palette
0x502C4
read-only
n
0x0
0x0
PALETTE[223]
Palette
0x50A40
read-only
n
0x0
0x0
PALETTE[224]
Palette
0x511C0
read-only
n
0x0
0x0
PALETTE[225]
Palette
0x51944
read-only
n
0x0
0x0
PALETTE[226]
Palette
0x520CC
read-only
n
0x0
0x0
PALETTE[227]
Palette
0x52858
read-only
n
0x0
0x0
PALETTE[228]
Palette
0x52FE8
read-only
n
0x0
0x0
PALETTE[229]
Palette
0x5377C
read-only
n
0x0
0x0
PALETTE[22]
Palette
0x63F4
read-only
n
0x0
0x0
PALETTE[230]
Palette
0x53F14
read-only
n
0x0
0x0
PALETTE[231]
Palette
0x546B0
read-only
n
0x0
0x0
PALETTE[232]
Palette
0x54E50
read-only
n
0x0
0x0
PALETTE[233]
Palette
0x555F4
read-only
n
0x0
0x0
PALETTE[234]
Palette
0x55D9C
read-only
n
0x0
0x0
PALETTE[235]
Palette
0x56548
read-only
n
0x0
0x0
PALETTE[236]
Palette
0x56CF8
read-only
n
0x0
0x0
PALETTE[237]
Palette
0x574AC
read-only
n
0x0
0x0
PALETTE[238]
Palette
0x57C64
read-only
n
0x0
0x0
PALETTE[239]
Palette
0x58420
read-only
n
0x0
0x0
PALETTE[23]
Palette
0x6850
read-only
n
0x0
0x0
PALETTE[240]
Palette
0x58BE0
read-only
n
0x0
0x0
PALETTE[241]
Palette
0x593A4
read-only
n
0x0
0x0
PALETTE[242]
Palette
0x59B6C
read-only
n
0x0
0x0
PALETTE[243]
Palette
0x5A338
read-only
n
0x0
0x0
PALETTE[244]
Palette
0x5AB08
read-only
n
0x0
0x0
PALETTE[245]
Palette
0x5B2DC
read-only
n
0x0
0x0
PALETTE[246]
Palette
0x5BAB4
read-only
n
0x0
0x0
PALETTE[247]
Palette
0x5C290
read-only
n
0x0
0x0
PALETTE[248]
Palette
0x5CA70
read-only
n
0x0
0x0
PALETTE[249]
Palette
0x5D254
read-only
n
0x0
0x0
PALETTE[24]
Palette
0x6CB0
read-only
n
0x0
0x0
PALETTE[250]
Palette
0x5DA3C
read-only
n
0x0
0x0
PALETTE[251]
Palette
0x5E228
read-only
n
0x0
0x0
PALETTE[252]
Palette
0x5EA18
read-only
n
0x0
0x0
PALETTE[253]
Palette
0x5F20C
read-only
n
0x0
0x0
PALETTE[254]
Palette
0x5FA04
read-only
n
0x0
0x0
PALETTE[255]
Palette
0x60200
read-only
n
0x0
0x0
PALETTE[25]
Palette
0x7114
read-only
n
0x0
0x0
PALETTE[26]
Palette
0x757C
read-only
n
0x0
0x0
PALETTE[27]
Palette
0x79E8
read-only
n
0x0
0x0
PALETTE[28]
Palette
0x7E58
read-only
n
0x0
0x0
PALETTE[29]
Palette
0x82CC
read-only
n
0x0
0x0
PALETTE[2]
Palette
0x100C
read-only
n
0x0
0x0
PALETTE[30]
Palette
0x8744
read-only
n
0x0
0x0
PALETTE[31]
Palette
0x8BC0
read-only
n
0x0
0x0
PALETTE[32]
Palette
0x9040
read-only
n
0x0
0x0
PALETTE[33]
Palette
0x94C4
read-only
n
0x0
0x0
PALETTE[34]
Palette
0x994C
read-only
n
0x0
0x0
PALETTE[35]
Palette
0x9DD8
read-only
n
0x0
0x0
PALETTE[36]
Palette
0xA268
read-only
n
0x0
0x0
PALETTE[37]
Palette
0xA6FC
read-only
n
0x0
0x0
PALETTE[38]
Palette
0xAB94
read-only
n
0x0
0x0
PALETTE[39]
Palette
0xB030
read-only
n
0x0
0x0
PALETTE[3]
Palette
0x1418
read-only
n
0x0
0x0
PALETTE[40]
Palette
0xB4D0
read-only
n
0x0
0x0
PALETTE[41]
Palette
0xB974
read-only
n
0x0
0x0
PALETTE[42]
Palette
0xBE1C
read-only
n
0x0
0x0
PALETTE[43]
Palette
0xC2C8
read-only
n
0x0
0x0
PALETTE[44]
Palette
0xC778
read-only
n
0x0
0x0
PALETTE[45]
Palette
0xCC2C
read-only
n
0x0
0x0
PALETTE[46]
Palette
0xD0E4
read-only
n
0x0
0x0
PALETTE[47]
Palette
0xD5A0
read-only
n
0x0
0x0
PALETTE[48]
Palette
0xDA60
read-only
n
0x0
0x0
PALETTE[49]
Palette
0xDF24
read-only
n
0x0
0x0
PALETTE[4]
Palette
0x1828
read-only
n
0x0
0x0
PALETTE[50]
Palette
0xE3EC
read-only
n
0x0
0x0
PALETTE[51]
Palette
0xE8B8
read-only
n
0x0
0x0
PALETTE[52]
Palette
0xED88
read-only
n
0x0
0x0
PALETTE[53]
Palette
0xF25C
read-only
n
0x0
0x0
PALETTE[54]
Palette
0xF734
read-only
n
0x0
0x0
PALETTE[55]
Palette
0xFC10
read-only
n
0x0
0x0
PALETTE[56]
Palette
0x100F0
read-only
n
0x0
0x0
PALETTE[57]
Palette
0x105D4
read-only
n
0x0
0x0
PALETTE[58]
Palette
0x10ABC
read-only
n
0x0
0x0
PALETTE[59]
Palette
0x10FA8
read-only
n
0x0
0x0
PALETTE[5]
Palette
0x1C3C
read-only
n
0x0
0x0
PALETTE[60]
Palette
0x11498
read-only
n
0x0
0x0
PALETTE[61]
Palette
0x1198C
read-only
n
0x0
0x0
PALETTE[62]
Palette
0x11E84
read-only
n
0x0
0x0
PALETTE[63]
Palette
0x12380
read-only
n
0x0
0x0
PALETTE[64]
Palette
0x12880
read-only
n
0x0
0x0
PALETTE[65]
Palette
0x12D84
read-only
n
0x0
0x0
PALETTE[66]
Palette
0x1328C
read-only
n
0x0
0x0
PALETTE[67]
Palette
0x13798
read-only
n
0x0
0x0
PALETTE[68]
Palette
0x13CA8
read-only
n
0x0
0x0
PALETTE[69]
Palette
0x141BC
read-only
n
0x0
0x0
PALETTE[6]
Palette
0x2054
read-only
n
0x0
0x0
PALETTE[70]
Palette
0x146D4
read-only
n
0x0
0x0
PALETTE[71]
Palette
0x14BF0
read-only
n
0x0
0x0
PALETTE[72]
Palette
0x15110
read-only
n
0x0
0x0
PALETTE[73]
Palette
0x15634
read-only
n
0x0
0x0
PALETTE[74]
Palette
0x15B5C
read-only
n
0x0
0x0
PALETTE[75]
Palette
0x16088
read-only
n
0x0
0x0
PALETTE[76]
Palette
0x165B8
read-only
n
0x0
0x0
PALETTE[77]
Palette
0x16AEC
read-only
n
0x0
0x0
PALETTE[78]
Palette
0x17024
read-only
n
0x0
0x0
PALETTE[79]
Palette
0x17560
read-only
n
0x0
0x0
PALETTE[7]
Palette
0x2470
read-only
n
0x0
0x0
PALETTE[80]
Palette
0x17AA0
read-only
n
0x0
0x0
PALETTE[81]
Palette
0x17FE4
read-only
n
0x0
0x0
PALETTE[82]
Palette
0x1852C
read-only
n
0x0
0x0
PALETTE[83]
Palette
0x18A78
read-only
n
0x0
0x0
PALETTE[84]
Palette
0x18FC8
read-only
n
0x0
0x0
PALETTE[85]
Palette
0x1951C
read-only
n
0x0
0x0
PALETTE[86]
Palette
0x19A74
read-only
n
0x0
0x0
PALETTE[87]
Palette
0x19FD0
read-only
n
0x0
0x0
PALETTE[88]
Palette
0x1A530
read-only
n
0x0
0x0
PALETTE[89]
Palette
0x1AA94
read-only
n
0x0
0x0
PALETTE[8]
Palette
0x2890
read-only
n
0x0
0x0
PALETTE[90]
Palette
0x1AFFC
read-only
n
0x0
0x0
PALETTE[91]
Palette
0x1B568
read-only
n
0x0
0x0
PALETTE[92]
Palette
0x1BAD8
read-only
n
0x0
0x0
PALETTE[93]
Palette
0x1C04C
read-only
n
0x0
0x0
PALETTE[94]
Palette
0x1C5C4
read-only
n
0x0
0x0
PALETTE[95]
Palette
0x1CB40
read-only
n
0x0
0x0
PALETTE[96]
Palette
0x1D0C0
read-only
n
0x0
0x0
PALETTE[97]
Palette
0x1D644
read-only
n
0x0
0x0
PALETTE[98]
Palette
0x1DBCC
read-only
n
0x0
0x0
PALETTE[99]
Palette
0x1E158
read-only
n
0x0
0x0
PALETTE[9]
Palette
0x2CB4
read-only
n
0x0
0x0
STAT
LCD Status Register.
0x24
read-only
n
0x0
0x0
oneToClear
ADRRDY
Address Ready Interupt Status
1
1
write
Inactive
No interrupt pending
0
Clear
Clears the interrupt flag
1
Pending
Interrupt pending
1
BERR
BERR Interupt Status
3
1
write
Inactive
No interrupt pending
0
Clear
Clears the interrupt flag
1
Pending
Interrupt pending
1
LCDIDLE
LCD IDLE Staus
8
1
BUSY
BUSY
0
READY
READY
1
UFLO
Under FLow Interupt Status
0
1
write
Inactive
No interrupt pending
0
Clear
Clears the interrupt flag
1
Pending
Interrupt pending
1
VCI
VCI Interupt Status
2
1
write
Inactive
No interrupt pending
0
Clear
Clears the interrupt flag
1
Pending
Interrupt pending
1
VTIM_0
LCD Vertical Timing 0 Register
0x4
read-only
n
0x0
0x0
VBACKPORCH
V BACK PORCH
16
8
VLINES
V Lines
0
8
VTIM_1
LCD Vertical Timing 1 Register
0x8
read-only
n
0x0
0x0
VFRONTPORCH
V Front PORCH
16
8
VSYNCWIDTH
V Sync Width
0
8
CRYPTO
The Cryptographic Accelerator used to assist the computationally intensive operations of several common algorithms.
CRYPTO
0x0
0x0
0x1000
registers
n
Crypto_Engine
Crypto Engine interrupt.
27
CIPHER_CTRL
Cipher Control Register.
0x4
read-write
n
0x0
0x0
CIPHER
Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.
4
3
dis
Disabled.
0
aes128
AES 128.
1
aes192
AES 192.
2
aes256
AES 256.
3
des
DES.
4
tdes
Triple DES.
5
ENC
Encrypt. Select encryption or decryption of input data.
0
1
encrypt
Encrypt.
0
decrypt
Decrypt.
1
KEY
Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.
1
1
complete
No operation/complete.
0
start
Start operation.
1
MODE
Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.
8
3
ECB
ECB Mode.
0
CBC
CBC Mode.
1
CFB
CFB (AES only).
2
OFB
OFB (AES only).
3
CTR
CTR (AES only).
4
SRC
Source of Random key.
2
2
cipherKey
User cipher key (0x4000_1060).
0
regFile
Key from battery-backed register file (0x4000_5000 to 0x4000_501F).
2
qspiKey_regFile
Key from battery-backed register file (0x4000_5020 to 0x4000_502F).
3
CIPHER_INIT0
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0x50
-1
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_INIT1
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0x54
-1
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_INIT2
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0x58
-1
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_INIT3
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0x5C
-1
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_INIT[0]
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0xA0
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_INIT[1]
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0xF4
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_INIT[2]
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0x14C
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_INIT[3]
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0x1A8
read-write
n
0x0
0x0
IVEC
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
0
32
CIPHER_KEY0
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x60
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY1
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x64
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY2
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x68
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY3
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x6C
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY4
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x70
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY5
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x74
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY6
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x78
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY7
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x7C
-1
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[0]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0xC0
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[1]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x124
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[2]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x18C
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[3]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x1F8
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[4]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x268
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[5]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x2DC
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[6]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x354
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CIPHER_KEY[7]
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
0x3D0
write-only
n
0x0
0x0
KEY
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
0
32
CRC_CTRL
CRC Control Register.
0xC
read-write
n
0x0
0x0
CRC
Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled.
0
1
dis
Disable.
0
en
Enable.
1
ENT
Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source.
3
1
HAM
Hamming Code Enable. Enable hamming code calculation.
4
1
HRST
Hamming Reset. Reset Hamming code ECC generator for next block.
5
1
write-only
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
MSB
MSB select. This bit selects the order of calculating CRC on data.
1
1
lsbFirst
LSB First.
0
msbFirst
MSB First.
1
PRNG
Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle.
2
1
CRC_POLY
CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.
0x40
read-write
n
0x0
0x0
POLY
CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.
0
32
CRC_PRNG
Pseudo Random Value. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled.
0x48
read-only
n
0x0
0x0
PRNG
Pseudo Random Value. Output of the Galois Field Shift Register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled.
0
32
CRC_VAL
CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit.
0x44
read-write
n
0x0
0x0
VAL
CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.
0
32
CTRL
Crypto Control Register.
0x0
read-write
n
0x0
0x0
BSI
Byte Swap Input. Note. No byte swap will occur if there is not a full word.
5
1
BSO
Byte Swap Output. Note. No byte swap will occur if there is not a full word.
4
1
CPH_DONE
Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.
27
1
DMADNEMSK
DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.
15
1
not_used
DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.
0
used
DMA_DONE used in setting CRYPTO_CTRL.DONE bit.
1
DMA_DONE
DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.
24
1
notDone
Not Done.
0
done
Done.
1
DONE
Done. One or more cryptographic calculations complete (logical OR of done flags).
31
1
read-only
ERR
AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.
29
1
read-only
noError
No Error.
0
error
Error.
1
FLAG_MODE
Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.
14
1
unres_wr
Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags.
0
res_wr
Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect.
1
GLS_DONE
Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.
25
1
HSH_DONE
Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.
26
1
INTR
Interrupt Enable. Generates an interrupt when done or error set.
1
1
dis
Disable
0
en
Enable
1
MAA_DONE
MAA Done. MAA operation is complete. This bit must be cleared before starting a new MAA operation. This bit is read only while the MAA is in progress. This bit is negate of MAA_CTRL.STC.
28
1
RDSRC
Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.
10
2
dmaDisabled
DMA Disable.
0
dmaOrApb
DMA Or APB.
1
rng
RNG.
2
RDY
Ready. Crypto block ready for more data.
30
1
read-only
busy
Busy.
0
ready
Ready.
1
RST
Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.
0
1
reset_read
read
reset_done
Reset complete.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SRC
Source Select. This bit selects the hash function and CRC generator input source.
2
1
inputFIFO
Input FIFO
0
outputFIFO
Output FIFO
1
WAIT_EN
Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.
6
1
WAIT_POL
Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.
7
1
activeLo
Active Low.
0
activeHi
Active High.
1
WRSRC
Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.
8
2
none
None.
0
cipherOutput
Cipher Output.
1
readFIFO
Read FIFO.
2
RFU
Reserved. Do not use.
3
DIN0
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0x20
-1
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DIN1
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0x24
-1
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DIN2
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0x28
-1
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DIN3
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0x2C
-1
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DIN[0]
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0x40
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DIN[1]
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0x64
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DIN[2]
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0x8C
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DIN[3]
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
0xB8
write-only
n
0x0
0x0
DATA
Crypto Data Input. Input can be written to this register instead of using DMA.
0
32
DMA_CNT
Crypto DMA Byte Count.
0x18
read-write
n
0x0
0x0
ADDR
DMA Byte Address.
0
32
DMA_DEST
Crypto DMA Destination Address.
0x14
read-write
n
0x0
0x0
ADDR
DMA Destination Address.
0
32
DMA_SRC
Crypto DMA Source Address.
0x10
read-write
n
0x0
0x0
ADDR
DMA Source Address.
0
32
DOUT0
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0x30
-1
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
DOUT1
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0x34
-1
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
DOUT2
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0x38
-1
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
DOUT3
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0x3C
-1
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
DOUT[0]
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0x60
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
DOUT[1]
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0x94
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
DOUT[2]
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0xCC
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
DOUT[3]
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
0x108
read-only
n
0x0
0x0
DATA
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
0
32
HAM_ECC
Hamming ECC Register.
0x4C
read-write
n
0x0
0x0
ECC
Hamming ECC Value. These bits are the even parity of their corresponding bit groups.
0
16
PAR
Parity. This is the parity of the entire array.
16
1
even
Even.
0
odd
Odd.
1
HASH_CTRL
HASH Control Register.
0x8
read-write
n
0x0
0x0
HASH
Hash function selection.
2
3
dis
Disabled.
0
sha1
SHA-1.
1
sha224
SHA 224.
2
sha256
SHA 256.
3
sha384
SHA 384.
4
sha512
SHA 512.
5
INIT
Initialize. Initializes hash registers with standard constants.
0
1
nop
No operation/complete.
0
start
Start operation.
1
LAST
Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.
5
1
noEffect
No Effect.
0
lastMsgData
Last Message Data.
1
XOR
XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.
1
1
dis
Disable.
0
en
Enable.
1
HASH_DIGEST0
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x80
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST1
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x84
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST10
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xA8
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST11
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xAC
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST12
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xB0
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST13
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xB4
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST14
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xB8
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST15
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xBC
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST2
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x88
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST3
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x8C
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST4
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x90
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST5
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x94
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST6
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x98
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST7
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x9C
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST8
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xA0
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST9
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xA4
-1
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[0]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x100
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[10]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x6DC
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[11]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x788
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[12]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x838
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[13]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x8EC
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[14]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x9A4
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[15]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0xA60
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[1]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x184
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[2]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x20C
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[3]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x298
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[4]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x328
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[5]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x3BC
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[6]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x454
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[7]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x4F0
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[8]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x590
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_DIGEST[9]
This register holds the calculated hash value. This register is affected by the endian swap bits.
0x634
read-write
n
0x0
0x0
HASH
This register holds the calculated hash value. This register is affected by the endian swap bits.
0
32
HASH_MSG_SZ0
Message Size. This register holds the lowest 32-bit of message size in bytes.
0xC0
-1
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
HASH_MSG_SZ1
Message Size. This register holds the lowest 32-bit of message size in bytes.
0xC4
-1
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
HASH_MSG_SZ2
Message Size. This register holds the lowest 32-bit of message size in bytes.
0xC8
-1
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
HASH_MSG_SZ3
Message Size. This register holds the lowest 32-bit of message size in bytes.
0xCC
-1
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
HASH_MSG_SZ[0]
Message Size. This register holds the lowest 32-bit of message size in bytes.
0x180
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
HASH_MSG_SZ[1]
Message Size. This register holds the lowest 32-bit of message size in bytes.
0x244
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
HASH_MSG_SZ[2]
Message Size. This register holds the lowest 32-bit of message size in bytes.
0x30C
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
HASH_MSG_SZ[3]
Message Size. This register holds the lowest 32-bit of message size in bytes.
0x3D8
read-write
n
0x0
0x0
MSGSZ
Message Size. This register holds the lowest 32-bit of message size in bytes.
0
32
MAA_CTRL
MAA Control Register.
0x1C
read-write
n
0x0
0x0
AMA
Multiplier / Operand A Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'a'.
16
4
AMS
Multiplier A Memory Select. These bits select the starting position of the parameter 'a' within the logical segment specified by AMA.
8
2
BMA
Multiplicand / Operand B Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'b'.
20
4
BMS
Multiplicand B Memory Select. These bits select the starting position of the parameter 'b' within the logical segment specified by BMA.
10
2
CLC
Calculation Configuration. These bits select desired calculation.
1
3
exp
Exponentiation.
0
sq
Square operation.
1
mul
Multiplication.
2
sqMul
Square followed by a multiplication.
3
add
Addition.
4
sub
Subtraction.
5
EMS
Exponent Memory Select. These bits select the starting position of the parameter 'e' within the logical segment specified by EMA.
12
2
MAAER
MAA Error. The MAAER bit defaults to 0 and can only be set by hardware. Once set, it must be cleared by software otherwise no new operation can be initiated. Software writes 1 to this bit has no effect and MAAER will maintain its original state.
7
1
noError
No Error.
0
error
Error.
1
MMS
Modulus Memory Select. These bits select the starting position of the parameter 'm' within the logical segment 5.
14
2
OCALC
Optimized Calculation Control. For optimized calculation, unnecessary multiply operations after normalizing the exponent are skipped.
4
1
dis
Disable.
0
en
Enable.
1
RMA
Result Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'r'.
24
4
STC
Start Calculation. This bit functions as both the control and the status of the MAA. If the size value in the MAWS register is invalid, the STC bit will be cleared by hardware immediately. Otherwise, the STC bit is automatically cleared following the completion of each calculation or detecting an error. Clearing the STC bit resets the controller to its default state.
0
1
nop
No operation/complete.
0
start
Start operation.
1
TMA
Temporary Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 't'.
28
4
MAA_MAWS
MAA Word Size. This register defines the number of bits for a modular operation. This register must be set to a valid value prior to the MAA operation start. Valid values are from 1 to 2048. Invalid values are ignored and will not initiate a MAA operation.
0xD0
read-write
n
0x0
0x0
MAWS
MAA Word Size.
0
12
DMA
DMA Controller Fully programmable, chaining capable DMA channels.
DMA
0x0
0x0
0x1000
registers
n
DMA0
DMA Channel 0 IRQ
28
DMA1
DMA Channel 1 IRQ
29
DMA2
DMA Channel 2 IRQ
30
DMA3
DMA Channel 3 IRQ
31
DMA4
DMA Channel 4 IRQ
68
DMA5
DMA Channel 5 IRQ
69
DMA6
DMA Channel 6 IRQ
70
DMA7
DMA Channel 7 IRQ
71
DMA8
DMA Channel 8 IRQ
72
DMA9
DMA Channel 9 IRQ
73
DMA10
DMA Channel 10 IRQ
74
DMA11
DMA Channel 11 IRQ
75
DMA12
DMA Channel 12 IRQ
76
DMA13
DMA Channel 13 IRQ
77
DMA14
DMA Channel 14 IRQ
78
DMA15
DMA Channel 15 IRQ
79
CFG
DMA Channel Configuration Register.
0x100
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[0]-CFG
DMA Channel Configuration Register.
0x200
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x210
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x21C
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x20C
read-write
n
0x0
0x0
ADDR
0
32
CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x218
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x208
read-write
n
0x0
0x0
ADDR
0
32
CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x214
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[0]-ST
DMA Channel Status Register.
0x204
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0xCDC
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0xCEC
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0xCF8
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0xCE8
read-write
n
0x0
0x0
ADDR
0
32
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0xCF4
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0xCE4
read-write
n
0x0
0x0
ADDR
0
32
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0xCF0
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0xCE0
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0xE08
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0xE18
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0xE24
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0xE14
read-write
n
0x0
0x0
ADDR
0
32
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0xE20
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0xE10
read-write
n
0x0
0x0
ADDR
0
32
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0xE1C
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0xE0C
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0xF38
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0xF48
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0xF54
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0xF44
read-write
n
0x0
0x0
ADDR
0
32
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0xF50
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0xF40
read-write
n
0x0
0x0
ADDR
0
32
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0xF4C
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0xF3C
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x106C
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x107C
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x1088
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x1078
read-write
n
0x0
0x0
ADDR
0
32
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x1084
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x1074
read-write
n
0x0
0x0
ADDR
0
32
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x1080
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x1070
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x11A4
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x11B4
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x11C0
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x11B0
read-write
n
0x0
0x0
ADDR
0
32
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x11BC
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x11AC
read-write
n
0x0
0x0
ADDR
0
32
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x11B8
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x11A8
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x12E0
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x12F0
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x12FC
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x12EC
read-write
n
0x0
0x0
ADDR
0
32
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x12F8
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x12E8
read-write
n
0x0
0x0
ADDR
0
32
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x12F4
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[15]-CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x12E4
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x304
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x314
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x320
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x310
read-write
n
0x0
0x0
ADDR
0
32
CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x31C
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x30C
read-write
n
0x0
0x0
ADDR
0
32
CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x318
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[1]-CH[0]-ST
DMA Channel Status Register.
0x308
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x40C
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x41C
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x428
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x418
read-write
n
0x0
0x0
ADDR
0
32
CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x424
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x414
read-write
n
0x0
0x0
ADDR
0
32
CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x420
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x410
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x518
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x528
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x534
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x524
read-write
n
0x0
0x0
ADDR
0
32
CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x530
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x520
read-write
n
0x0
0x0
ADDR
0
32
CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x52C
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x51C
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x628
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x638
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x644
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x634
read-write
n
0x0
0x0
ADDR
0
32
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x640
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x630
read-write
n
0x0
0x0
ADDR
0
32
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x63C
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x62C
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x73C
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x74C
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x758
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x748
read-write
n
0x0
0x0
ADDR
0
32
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x754
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x744
read-write
n
0x0
0x0
ADDR
0
32
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x750
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x740
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x854
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x864
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x870
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x860
read-write
n
0x0
0x0
ADDR
0
32
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x86C
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x85C
read-write
n
0x0
0x0
ADDR
0
32
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x868
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x858
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0x970
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x980
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0x98C
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x97C
read-write
n
0x0
0x0
ADDR
0
32
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x988
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x978
read-write
n
0x0
0x0
ADDR
0
32
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x984
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0x974
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0xA90
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0xAA0
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0xAAC
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0xA9C
read-write
n
0x0
0x0
ADDR
0
32
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0xAA8
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0xA98
read-write
n
0x0
0x0
ADDR
0
32
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0xAA4
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0xA94
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
DMA Channel Configuration Register.
0xBB4
read-write
n
0x0
0x0
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
SPI2RX
SPI2 RX
0x03
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
ADC
Analog-to-Digital Converter Channel
0x09
UART2RX
UART2 RX
0x0E
SPI3RX
SPI3 RX
0x0F
SPI_MSS0RX
SPI MSS0 RX
0x10
USBRXEP1
USB Endpoint 1 RX
0x11
USBRXEP2
USB Endpoint 2 RX
0x12
USBRXEP3
USB Endpoint 3 RX
0x13
USBRXEP4
USB Endpoint 4 RX
0x14
USBRXEP5
USB Endpoint 5 RX
0x15
USBRXEP6
USB Endpoint 6 RX
0x16
USBRXEP7
USB Endpoint 7 RX
0x17
USBRXEP8
USB Endpoint 8 RX
0x18
USBRXEP9
USB Endpoint 9 RX
0x19
USBRXEP10
USB Endpoint 10 RX
0x1A
USBRXEP11
USB Endpoint 11 RX
0x1B
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
SPI2TX
SPI2 TX
0x23
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
UART2TX
UART2 TX
0x2E
SPI3TX
SPI3 TX
0x2F
SPI_MSS0TX
SPI MSS0 TX
0x30
USBTXEP1
USB Endpoint 1 TX
0x31
USBTXEP2
USB Endpoint 2 TX
0x32
USBTXEP3
USB Endpoint 3 TX
0x33
USBTXEP4
USB Endpoint 4 TX
0x34
USBTXEP5
USB Endpoint 5 TX
0x35
USBTXEP6
USB Endpoint 6 TX
0x36
USBTXEP7
USB Endpoint 7 TX
0x37
USBTXEP8
USB Endpoint 8 TX
0x38
USBTXEP9
USB Endpoint 9 TX
0x39
USBTXEP10
USB Endpoint 10 TX
0x3A
USBTXEP11
USB Endpoint 11 TX
0x3B
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0xBC4
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Channel Count Reload Register.
0xBD0
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0xBC0
read-write
n
0x0
0x0
ADDR
0
32
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0xBCC
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0xBBC
read-write
n
0x0
0x0
ADDR
0
32
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0xBC8
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
DMA Channel Status Register.
0xBB8
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
Clear
Clears the interrupt flag
1
CN
DMA Control Register.
0x0
read-write
n
0x0
0x0
CH0_IEN
Channel 0 Interrupt Enable.
0
1
dis
Disable.
0
en
Enable.
1
CH10_IEN
Channel 10 Interrupt Enable.
10
1
CH11_IEN
Channel 11 Interrupt Enable.
11
1
CH12_IEN
Channel 12 Interrupt Enable.
12
1
CH13_IEN
Channel 13 Interrupt Enable.
13
1
CH14_IEN
Channel 14 Interrupt Enable.
14
1
CH15_IEN
Channel 15 Interrupt Enable.
15
1
CH1_IEN
Channel 1 Interrupt Enable.
1
1
CH2_IEN
Channel 2 Interrupt Enable.
2
1
CH3_IEN
Channel 3 Interrupt Enable.
3
1
CH4_IEN
Channel 4 Interrupt Enable.
4
1
CH5_IEN
Channel 5 Interrupt Enable.
5
1
CH6_IEN
Channel 6 Interrupt Enable.
6
1
CH7_IEN
Channel 7 Interrupt Enable.
7
1
CH8_IEN
Channel 8 Interrupt Enable.
8
1
CH9_IEN
Channel 9 Interrupt Enable.
9
1
CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x110
read-write
n
0x0
0x0
CNT
DMA Counter.
0
24
CNT_RLD
DMA Channel Count Reload Register.
0x11C
read-write
n
0x0
0x0
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x10C
read-write
n
0x0
0x0
ADDR
0
32
DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x118
read-write
n
0x0
0x0
DST_RLD
Destination Address Reload Value.
0
31
INTR
DMA Interrupt Register.
0x4
read-only
n
0x0
0x0
CH0_IPEND
Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.
0
1
ch_ipend_enum
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
CH10_IPEND
10
1
CH11_IPEND
11
1
CH12_IPEND
12
1
CH13_IPEND
13
1
CH14_IPEND
14
1
CH15_IPEND
15
1
CH1_IPEND
1
1
CH2_IPEND
2
1
CH3_IPEND
3
1
CH4_IPEND
4
1
CH5_IPEND
5
1
CH6_IPEND
6
1
CH7_IPEND
7
1
CH8_IPEND
8
1
CH9_IPEND
9
1
SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x108
read-write
n
0x0
0x0
ADDR
0
32
SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x114
read-write
n
0x0
0x0
SRC_RLD
Source Address Reload Value.
0
31
ST
DMA Channel Status Register.
0x104
read-write
n
0x0
0x0
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
write
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
Clear
Clears the interrupt flag
1
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_wr
write
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
Clear
Clears the interrupt flag
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
RLD_ST
Reload Status.
3
1
oneToClear
write
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
write
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
Clear
Clears the interrupt flag
1
EMCC
External Memory Cache Controller Registers.
EMCC
0x0
0x0
0x1000
registers
n
CACHE_CTRL
Cache Control and Status Register.
0x100
read-write
n
0x0
0x0
CACHE_EN
Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.
0
1
dis
Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
0
en
Cache Enabled.
1
CACHE_RDY
Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.
16
1
notReady
Not Ready.
0
ready
Ready.
1
CWFST_DIS
Critical word first and streaming disable. This bit only writeable while the cache is disabled.
2
1
en
Critical word first and streaming enabled.
0
dis
Critical word first and streaming disabled.
1
WRITE_ALLOC_EN
Write Allocate Enable. This bit only writable while the cache is disabled.
1
1
dis
Write-no-allocate.
0
en
Write-allocate enabled.
1
CACHE_ID
Cache ID Register.
0x0
read-only
n
0x0
0x0
CCHID
Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.
10
6
PARTNUM
Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.
6
4
RELNUM
Release Number. Identifies the RTL release version.
0
6
INVALIDATE
Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.
0x700
read-write
n
0x0
0x0
IA
Invalidate all cache contents.
0
32
MEMCFG
Memory Configuration Register.
0x4
read-only
n
0x0
0x0
CCHSZ
Cache Size. Indicates total size in Kbytes of cache.
0
16
MEMSZ
Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.
16
16
FLC
Flash Memory Control.
FLC
0x0
0x0
0x1000
registers
n
Flash_Controller
Flash Controller interrupt.
23
ACNTL
Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3 pflc-acntl = 0xa1e34f20 pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.
0x40
-1
write-only
n
0x0
0x0
ACNTL
Access control.
0
32
ADDR
Flash Write Address.
0x0
-1
read-write
n
0x0
0x0
ADDR
Address for next operation.
0
32
CLKDIV
Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
0x4
-1
read-write
n
0x0
0x0
CLKDIV
Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.
0
8
CN
Flash Control Register.
0x8
-1
read-write
n
0x0
0x0
BRST
Burst Mode Enable.
27
1
disable
Disable
0
enable
Enable
1
ERASE_CODE
Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.
8
8
nop
No operation.
0
erasePage
Enable Page Erase.
0x55
eraseAll
Enable Mass Erase. The debug port must be enabled.
0xAA
LVE
Low Voltage Read Enable
25
1
read-only
lve_read
read
dis
Disabled
0
en
Enabled
1
ME
Mass Erase. This bit is automatically cleared after the operation.
1
1
PEND
Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.
24
1
read-only
idle
Idle.
0
busy
Busy.
1
PGE
Page Erase. This bit is automatically cleared after the operation.
2
1
UNLOCK
Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.
28
4
unlocked
Flash Unlocked
2
locked
Flash Locked
3
WDTH
Data Width. This bits selects write data width.
4
1
size128
128-bit.
0
size32
32-bit.
1
WR
Write. This bit is automatically cleared after the operation.
0
1
complete
No operation/complete.
0
start
Start operation.
1
DATA0
Flash Write Data.
0x30
-1
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
DATA1
Flash Write Data.
0x34
-1
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
DATA2
Flash Write Data.
0x38
-1
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
DATA3
Flash Write Data.
0x3C
-1
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
FLSH_ACNTL
Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.
0x40
write-only
n
0x0
0x0
ACNTL
Access control.
0
32
FLSH_ADDR
Flash Write Address.
0x0
read-write
n
0x0
0x0
ADDR
Address for next operation.
0
32
FLSH_CLKDIV
Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
0x4
read-write
n
0x0
0x0
CLKDIV
Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.
0
8
FLSH_CN
Flash Control Register.
0x8
read-write
n
0x0
0x0
BRST
Burst Mode Enable.
27
1
disable
Disable
0
enable
Enable
1
ERASE_CODE
Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.
8
8
nop
No operation.
0
erasePage
Enable Page Erase.
0x55
eraseAll
Enable Mass Erase. The debug port must be enabled.
0xAA
LVE
Low Voltage Read Enable
25
1
read-only
lve_read
read
dis
Disabled
0
en
Enabled
1
ME
Mass Erase. This bit is automatically cleared after the operation.
1
1
PEND
Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.
24
1
read-only
idle
Idle.
0
busy
Busy.
1
PGE
Page Erase. This bit is automatically cleared after the operation.
2
1
UNLOCK
Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.
28
4
unlocked
Flash Unlocked
2
WDTH
Data Width. This bits selects write data width.
4
1
size128
128-bit.
0
size32
32-bit.
1
WR
Write. This bit is automatically cleared after the operation.
0
1
complete
No operation/complete.
0
start
Start operation.
1
FLSH_DATA[0]
Flash Write Data.
0x60
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
FLSH_DATA[1]
Flash Write Data.
0x94
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
FLSH_DATA[2]
Flash Write Data.
0xCC
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
FLSH_DATA[3]
Flash Write Data.
0x108
read-write
n
0x0
0x0
DATA
Data next operation.
0
32
FLSH_INTR
Flash Interrupt Register.
0x24
read-write
n
0x0
0x0
AF
Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.
1
1
noError
No Failure.
0
error
Failure occurs.
1
AFIE
9
1
DONE
Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.
0
1
inactive
No interrupt is pending
0
pending
An interrupt is pending
1
DONEIE
Flash Done Interrupt Enable.
8
1
disable
Disable.
0
enable
Enable.
1
INTR
Flash Interrupt Register.
0x24
-1
read-write
n
0x0
0x0
AF
Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.
1
1
noError
No Failure.
0
error
Failure occurs.
1
AFIE
9
1
DONE
Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.
0
1
inactive
No interrupt is pending
0
pending
An interrupt is pending
1
DONEIE
Flash Done Interrupt Enable.
8
1
disable
Disable.
0
enable
Enable.
1
GCR
Global Control Registers.
GCR
0x0
0x0
0x400
registers
n
CLKCN
Clock Control.
0x8
read-write
n
0x0
0x0
CCD
Cryptographic clock divider
15
1
read-only
non_div
The cryptographic accelerator clock is running in non-divided mode.
0
div
The cryptographic accelerator clock is running in divided mode.
1
CKRDY
Clock Ready. This read only bit reflects whether the currently selected system clock source is running.
13
1
read-only
busy
Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.
0
ready
System clock running from CLKSEL clock source.
1
CLKSEL
Clock Source Select. This 3 bit field selects the source for the system clock.
9
3
cryptoOsc
Crypto oscillator is used for the system clock.
0
hfxIn
HFXIN is used for the system clock.
2
nanoRing
The nano-ring output is used for the system clock.
3
HIRC96
The internal 96 MHz oscillator is used for the system clock.
4
HIRC8
The internal 8 MHz oscillator is used for the system clock.
5
HIRC8M_EN
8MHz High Frequency Internal Reference Clock Enable.
20
1
dis
Is Disabled.
0
en
Is Enabled.
1
HIRC8M_RDY
8MHz HIRC Ready.
28
1
not
Not Ready
0
ready
HIRC8M Ready
1
HIRC96M_EN
96MHz High Frequency Internal Reference Clock Enable.
19
1
dis
Is Disabled.
0
en
Is Enabled.
1
HIRC96M_RDY
96MHz HIRC Ready.
27
1
not
Not Ready
0
ready
HIRC96M Ready
1
HIRC_EN
60MHz High Frequency Internal Reference Clock Enable.
18
1
dis
Is Disabled.
0
en
Is Enabled.
1
HIRC_RDY
60MHz HIRC Ready.
26
1
not
Not Ready
0
ready
HIRC Ready
1
LIRC8K_RDY
8kHz Low Frequency Reference Clock Ready.
29
1
not
Not Ready
0
ready
Clock Ready
1
PSC
Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.
6
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
X32K_EN
32kHz Crystal Oscillator Enable.
17
1
dis
Is Disabled.
0
en
Is Enabled.
1
X32K_RDY
32kHz Crystal Oscillator Ready
25
1
read-only
not
Not Ready
0
Ready
X32K Ready
1
EVTEN
Event Enable Register.
0x4C
read-write
n
0x0
0x0
DMAEVENT
Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.
0
1
RXEVENT
Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode.
1
1
TXEVENT
Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].
2
1
MEMCKCN
Memory Clock Control Register.
0x28
read-write
n
0x0
0x0
CRYPTOLS
CRYPTO RAM Light Sleep Mode.
27
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
FWS
Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
0
3
ICACHELS
ICache RAM Light Sleep Mode.
24
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
ICACHEXIPLS
ICACHE-XIP RAM Light Sleep Mode.
25
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
ROMLS
ROM Light Sleep Mode.
29
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SCACHELS
SysCache RAM Light Sleep Mode.
26
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SYSRAM0LS
System RAM 0 Light Sleep Mode.
16
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SYSRAM1LS
System RAM 1 Light Sleep Mode.
17
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SYSRAM2LS
System RAM 2 Light Sleep Mode.
18
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SYSRAM3LS
System RAM 3 Light Sleep Mode.
19
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SYSRAM4LS
System RAM 4 Light Sleep Mode.
20
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SYSRAM5LS
System RAM 5 Light Sleep Mode.
21
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
SYSRAM6LS
System RAM 6 Light Sleep Mode.
22
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
USBLS
USB FIFO Light Sleep Mode.
28
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
MEMZCN
Memory Zeroize Control.
0x2C
read-write
n
0x0
0x0
CRYPTOZ
Crypto (MAA) Memory.
12
1
nop
No operation/complete.
0
start
Start operation.
1
ICACHEXIPZ
Instruction Cache XIP Data and Tag Ram zeroizatoin.
9
1
nop
No operation/complete.
0
start
Start operation.
1
ICACHEZ
Instruction Cache.
8
1
nop
No operation/complete.
0
start
Start operation.
1
SCACHEDATAZ
System Cache Data Ram Zeroization.
10
1
nop
No operation/complete.
0
start
Start operation.
1
SCACHETAGZ
System Cache Tag Zeroization.
11
1
nop
No operation/complete.
0
start
Start operation.
1
SRAM0Z
System RAM Block 0.
0
1
nop
No operation/complete.
0
start
Start operation.
1
SRAM1Z
System RAM Block 1.
1
1
nop
No operation/complete.
0
start
Start operation.
1
SRAM2Z
System RAM Block 2.
2
1
nop
No operation/complete.
0
start
Start operation.
1
SRAM3Z
System RAM Block 3.
3
1
nop
No operation/complete.
0
start
Start operation.
1
SRAM4Z
System RAM Block 4.
4
1
nop
No operation/complete.
0
start
Start operation.
1
SRAM5Z
System RAM Block 5.
5
1
nop
No operation/complete.
0
start
Start operation.
1
SRAM6Z
System RAM Block 6.
6
1
nop
No operation/complete.
0
start
Start operation.
1
USBFIFOZ
USB FIFO Zeroizatoin.
13
1
nop
No operation/complete.
0
start
Start operation.
1
MPRI0
Master Priority Control Register 0.
0x38
read-write
n
0x0
0x0
MPRI1
Mater Priority Control Register 1.
0x3C
read-write
n
0x0
0x0
PCKDIV
Peripheral Clock Divider.
0x18
read-write
n
0x0
0x0
ADCFRQ
ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ).
10
4
AONCD
Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.
14
2
div_4
PCLK divide by 4.
0
div_8
PCLK divide by 8.
1
div_16
PCLK divide by 16.
2
div_32
PCLK divide by 32.
3
PCF
These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware.
0
3
96MHz
None
2
48MHz
None
3
24MHz
None
4
12MHz
None
5
6MHz
None
6
3MHz
None
7
PCFWEN
PCF Write Enable. This bit allows the PCF Register bits to be updated by Software.
3
1
blocked
Writes to PCF are blocked.
0
allowed
Writes to PCF are allowed
1
SDHCFRQ
SDHC Clock Frequency. This bits defines the clock frequency of SDHC.
7
1
48MHz
None
0
24MHz
None
1
PERCKCN0
Peripheral Clock Disable.
0x24
read-write
n
0x0
0x0
ADCD
ADC Disable.
23
1
GPIODisable
en
enable it.
0
dis
disable it.
1
CLCDD
CLCD Disable.
4
1
GPIODisable
en
enable it.
0
dis
disable it.
1
CRYPTOD
Crypto Disable.
14
1
GPIODisable
en
enable it.
0
dis
disable it.
1
DMAD
DMA Disable.
5
1
GPIODisable
en
enable it.
0
dis
disable it.
1
GPIO0D
GPIO0 Disable.
0
1
GPIODisable
en
enable it.
0
dis
disable it.
1
GPIO1D
GPIO1 Disable.
1
1
GPIODisable
en
enable it.
0
dis
disable it.
1
GPIO2D
GPIO2 Disable.
2
1
GPIODisable
en
enable it.
0
dis
disable it.
1
I2C0D
I2C 0 Disable.
13
1
GPIODisable
en
enable it.
0
dis
disable it.
1
I2C1D
I2C 1 Disable.
28
1
GPIODisable
en
enable it.
0
dis
disable it.
1
PTD
PT Clock Disable.
29
1
GPIODisable
en
enable it.
0
dis
disable it.
1
RSV_0X19
Reserved for Future Use
25
1
SPI0D
SPI 0 Disable.
6
1
GPIODisable
en
enable it.
0
dis
disable it.
1
SPI1D
SPI 1 Disable.
7
1
GPIODisable
en
enable it.
0
dis
disable it.
1
SPI2D
SPI 2 Disable.
8
1
GPIODisable
en
enable it.
0
dis
disable it.
1
SPIMD
SPI XiP Master Controller Disable.
31
1
GPIODisable
en
enable it.
0
dis
disable it.
1
SPIXIPD
SPI XiP Disable.
30
1
GPIODisable
en
enable it.
0
dis
disable it.
1
T0D
Timer 0 Disable.
15
1
GPIODisable
en
enable it.
0
dis
disable it.
1
T1D
Timer 1 Disable.
16
1
GPIODisable
en
enable it.
0
dis
disable it.
1
T2D
Timer 2 Disable.
17
1
GPIODisable
en
enable it.
0
dis
disable it.
1
T3D
Timer 3 Disable.
18
1
GPIODisable
en
enable it.
0
dis
disable it.
1
T4D
Timer 4 Disable.
19
1
GPIODisable
en
enable it.
0
dis
disable it.
1
T5D
Timer 5 Disable.
20
1
GPIODisable
en
enable it.
0
dis
disable it.
1
UART0D
UART 0 Disable.
9
1
GPIODisable
en
enable it.
0
dis
disable it.
1
UART1D
UART 1 Disable.
10
1
GPIODisable
en
enable it.
0
dis
disable it.
1
USBD
USB Disable.
3
1
GPIODisable
en
enable it.
0
dis
disable it.
1
PERCKCN1
Peripheral Clock Disable.
0x48
read-write
n
0x0
0x0
FLCD
Secure Flash Controller Disable.
3
1
en
Enable.
0
dis
Disable.
1
GPIO3D
GPIO3 Clock Disable.
6
1
en
Enable.
0
dis
Disable.
1
HBCD
Hyper Bus Controller Clock Disable.
4
1
en
Enable.
0
dis
Disable.
1
I2SD
I2S(SPI_MSS) Clock Disable
15
1
en
Enable.
0
dis
Disable.
1
ICACHED
ICache Clock Disable.
11
1
en
Enable.
0
dis
Disable.
1
ICACHEXIPD
ICache XIP Clock Disable.
12
1
en
Enable.
0
dis
Disable.
1
OWIRED
One-Wire Clock Disable.
13
1
en
Enable.
0
dis
Disable.
1
RSV_0X05
Reserved for Future Use
5
1
SCACHED
System Cache Clock Disable.
7
1
en
Enable.
0
dis
Disable.
1
SDHCD
SDHC/SDIO Clock Disable.
10
1
en
Enable.
0
dis
Disable.
1
SDMAD
SDMA Clock Disable.
8
1
en
Enable.
0
dis
Disable.
1
SMPHRD
Semaphore Clock Disable.
9
1
en
Enable.
0
dis
Disable.
1
SPI3D
SPI3 Clock Disable.
14
1
en
Enable.
0
dis
Disable.
1
SPIMM0
SPI Medical Master 0 Clock Disable.
16
1
en
Enable.
0
dis
Disable.
1
SPIMM1
SPI Medical Master 1 Clock Disable.
17
1
en
Enable.
0
dis
Disable.
1
SPIMM2
SPI Medical Master 2 Clock Disable.
18
1
en
Enable.
0
dis
Disable.
1
SPIMS0
SPI Medical Slave 0 Clock Disable.
19
1
en
Enable.
0
dis
Disable.
1
SPIXIPDD
SPI-XIP Data Clock Disable
20
1
en
Enable.
0
dis
Disable.
1
TRNGD
TRNG Disable.
2
1
en
Enable.
0
dis
Disable.
1
UART2D
BTLE Disable.
1
1
en
Enable.
0
dis
Disable.
1
PLL0CN
PLL 0 Control.
0x10
read-write
n
0x0
0x0
RFU
Reserved for Future Use
0
32
PLL1CN
PLL 1 Control.
0x14
read-write
n
0x0
0x0
RFU
Reserved for Future Use
0
32
PM
Power Management.
0xC
read-write
n
0x0
0x0
GPIOWKEN
GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.
4
1
dis
Wake Up Disable.
0
en
Wake Up Enable.
1
HIRC8MPD
8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode.
17
1
active
Mode is Active.
0
deepsleep
Powered down in DEEPSLEEP.
1
HIRC96MPD
96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode.
16
1
active
Mode is Active.
0
deepsleep
Powered down in DEEPSLEEP.
1
HIRCPD
HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode.
15
1
active
Mode is Active.
0
deepsleep
Powered down in DEEPSLEEP.
1
MODE
Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.
0
3
active
Active Mode.
0
shutdown
Shutdown Mode.
3
backup
Backup Mode.
4
RTCWKEN
RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.
5
1
dis
Wake Up Disable.
0
en
Wake Up Enable.
1
USBWKEN
USB Wake Up Enable. This bit enables USB activity as wakeup source.
6
1
dis
Wake Up Disable.
0
en
Wake Up Enable.
1
REVISION
Revision Register.
0x50
read-only
n
0x0
0x0
REVISION
Manufacturer Chip Revision.
0
16
RSTR0
Reset.
0x4
read-write
n
0x0
0x0
ADC
Analog to Digital Reset.
26
1
adc_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
CLCD
CLCD Reset. Setting this bit to 1 resets the CLCD clock.
22
1
clcd_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
CRYPTO
Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.
18
1
crypto_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
DMA
DMA Reset.
0
1
dma_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
GPIO0
GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.
2
1
gpio0_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
GPIO1
GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.
3
1
gpio1_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
GPIO2
GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states.
4
1
gpio2_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
HBC
Hyper Bus Controller Reset. Setting this bit to 1 resets the HBC clock.
21
1
hbc_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
I2C0
I2C0 Reset.
16
1
i2c0_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
PRST
Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.
30
1
prst_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
RSV_0x19
Reserved for Future Use
25
1
RTC
Real Time Clock Reset.
17
1
rtc_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
SPI0
SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.
13
1
spi0_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
SPI1
SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.
14
1
xpi1_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
SPI2
SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.
15
1
spi2_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
SRST
Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.
29
1
srst_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
SYSTEM
System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.
31
1
system_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
TIMER0
Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.
5
1
timer0_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
TIMER1
Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.
6
1
timer1_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
TIMER2
Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.
7
1
timer2_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
TIMER3
Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.
8
1
timer3_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
TIMER4
Timer3 Reset. Setting this bit to 1 resets Timer 4 blocks.
9
1
timer4_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
TIMER5
Timer3 Reset. Setting this bit to 1 resets Timer 5 blocks.
10
1
timer5_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
TRNG
TRNG Reset.
24
1
trng_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
UART0
UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.
11
1
uart0_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
UART1
UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.
12
1
uart1_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
UART2
UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.
28
1
uart2_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
USB
USB Reset. Setting this bit resets both USB blocks.
23
1
usb_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
WDT
Watchdog Timer Reset.
1
1
wdt_read
read
Reset_Done
Reset Complete
0
RFU
Reserved. Do not use.
0
Busy
Reset Busy
1
reset
Starts reset operation.
1
RSTR1
Reset 1.
0x44
read-write
n
0x0
0x0
GPIO3
GPIO3 Reset.
5
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
I2C1
I2C1 Reset.
0
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
I2S
I2S Reset.
10
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
OWIRE
OWIRE Reset.
7
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
PT
PT Reset.
1
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
RSV_0X02
Reserved for Future Use
2
1
SDHC
SDHC/SDIO Reset.
6
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SMPHR
SMPHR Reset.
16
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SPI3
SPI3 Reset.
9
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SPIMM0
SPIMM0 Reset.
11
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SPIMM1
SPIMM1 Reset.
12
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SPIMM2
SPIMM2 Reset.
13
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SPIMS0
SPIMS0 Reset.
14
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SPIXIP
SPI XiP Master Reset.
3
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SPIXMEM
SPIXMEM Reset.
15
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
WDT1
WDT1 Reset.
8
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
XSPIM
GSPI XiP Master Controller Reset.
4
1
reset_read
read
reset_done
Reset complete.
0
RFU
Reserved. Do not use.
0
busy
Reset in progress.
1
reset
Starts reset operation.
1
SCCK
Smart Card Clock Control.
0x34
read-write
n
0x0
0x0
SCON
System Control.
0x0
read-write
n
0x0
0x0
BSTAPEN
Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.
0
1
dis
Boundary Scan TAP port disabled.
0
en
Boundary Scan TAP port enabled.
1
CCACHE_FLUSH
Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4.
6
1
normal
Normal Code Cache Operation
0
flush
Code Caches and CPU instruction buffer are flushed
1
CCHK
Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.
13
1
complete
No operation/complete.
0
start
Start operation.
1
CHKRES
ROM Checksum Result. This bit is only valid when CHKRD=1.
15
1
pass
ROM Checksum Correct.
0
fail
ROM Checksum Fail.
1
DCACHE_DIS
Data Cache Disable. The system cache(s) will be completely disabled when this bit is set.
9
1
en
Is enabled.
0
dis
Is Disabled.
1
DCACHE_FLUSH
Data Cache Flush. The system cache(s) will be flushed when this bit is set.
7
1
normal
Normal System Cache Operation
0
flush
System Cache is flushed
1
FLASH_PAGE_FLIP
Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.
4
1
normal
Physical layout matches logical layout.
0
swapped
Bottom half mapped to logical top half and vice versa.
1
OVR
Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range.
16
2
0_9V
0.9V +/- 10 Percent
0
1_0V
1.0V +/- 10 Percent
1
1_1V
1.1V +/- 10 Percent
2
SBUSARB
System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.
1
2
fix
Fixed Burst abritration.
0
round
Round-robin scheme.
1
SYSSIE
System Status Interrupt Enable Register.
0x54
read-write
n
0x0
0x0
CIEIE
Code Integrity Error Interrupt Enable.
1
1
dis
disabled.
0
en
enabled.
1
ICEULIE
ARM ICE Unlock Interrupt Enable.
0
1
dis
disabled.
0
en
enabled.
1
SCMFIE
System Cache Memory Fault Interrupt Enable.
5
1
dis
disabled.
0
en
enabled.
1
SYSST
System Status Register.
0x40
read-write
n
0x0
0x0
CODEINTERR
Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface.
1
1
norm
Normal Operating Condition.
0
code
Code Integrity Error.
1
ICECLOCK
ARM ICE Lock Status.
0
1
unlocked
ICE is unlocked.
0
locked
ICE is locked.
1
SCMEMF
System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.
5
1
norm
Normal Operating Condition.
0
memory
Memory Fault.
1
GPIO0
Individual I/O for each GPIO
GPIO
0x0
0x0
0x1000
registers
n
GPIO0
GPIO0 interrupt.
24
DS
GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB0
-1
read-only
n
0x0
0x0
DS
Mask of all of the pins on the port.
0
32
ld
GPIO port pin is in low-drive mode.
0
hd
GPIO port pin is in high-drive mode.
1
DS1
GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN
GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.
0x0
-1
read-only
n
0x0
0x0
GPIO_EN
Mask of all of the pins on the port.
0
32
alternate
Alternate function enabled.
0
GPIO
GPIO function is enabled.
1
EN1
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x68
-1
read-only
n
0x0
0x0
GPIO_EN1
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN1_CLR
GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.
0x70
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN1_SET
GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.
0x6C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x74
-1
read-only
n
0x0
0x0
GPIO_EN2
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN2_CLR
GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.
0x7C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2_SET
GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.
0x78
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_CLR
GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.
0x8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_SET
GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.
0x4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
IN
GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.
0x24
read-only
n
0x0
0x0
GPIO_IN
Mask of all of the pins on the port.
0
32
INT_CLR
GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.
0x48
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
INT_DUAL_EDGE
GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.
0x5C
-1
read-only
n
0x0
0x0
GPIO_INT_DUAL_EDGE
Mask of all of the pins on the port.
0
32
no
No Effect.
0
en
Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.
1
INT_EN
GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.
0x34
-1
read-only
n
0x0
0x0
GPIO_INT_EN
Mask of all of the pins on the port.
0
32
dis
Interrupts are disabled for this GPIO pin.
0
en
Interrupts are enabled for this GPIO pin.
1
INT_EN_CLR
GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.
0x3C
-1
read-only
n
0x0
0x0
GPIO_INT_EN_CLR
Mask of all of the pins on the port.
0
32
no
No Effect.
0
clear
Clear GPIO_INT_EN bit in this position to '0'
1
INT_EN_SET
GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.
0x38
-1
read-only
n
0x0
0x0
GPIO_INT_EN_SET
Mask of all of the pins on the port.
0
32
no
No effect.
0
set
Set GPIO_INT_EN bit in this position to '1'
1
INT_MOD
GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.
0x28
-1
read-only
n
0x0
0x0
GPIO_INT_MOD
Mask of all of the pins on the port.
0
32
level
Interrupts for this pin are level triggered.
0
edge
Interrupts for this pin are edge triggered.
1
INT_POL
GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.
0x2C
-1
read-only
n
0x0
0x0
GPIO_INT_POL
Mask of all of the pins on the port.
0
32
falling
Interrupts are latched on a falling edge or low level condition for this pin.
0
rising
Interrupts are latched on a rising edge or high condition for this pin.
1
INT_STAT
GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.
0x40
read-only
n
0x0
0x0
GPIO_INT_STAT
Mask of all of the pins on the port.
0
32
no
No Interrupt is pending on this GPIO pin.
0
pending
An Interrupt is pending on this GPIO pin.
1
IS
Input Hysteresis Enable Register
0xA8
-1
read-only
n
0x0
0x0
OUT
GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
0x18
-1
read-only
n
0x0
0x0
GPIO_OUT
Mask of all of the pins on the port.
0
32
low
Drive Logic 0 (low) on GPIO output.
0
high
Drive logic 1 (high) on GPIO output.
1
OUT_CLR
GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.
0x20
write-only
n
0x0
0x0
GPIO_OUT_CLR
Mask of all of the pins on the port.
0
32
OUT_EN
GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.
0xC
-1
read-only
n
0x0
0x0
GPIO_OUT_EN
Mask of all of the pins on the port.
0
32
dis
GPIO Output Disable
0
en
GPIO Output Enable
1
OUT_EN_CLR
GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.
0x14
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_EN_SET
GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.
0x10
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_SET
GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.
0x1C
write-only
n
0x0
0x0
GPIO_OUT_SET
Mask of all of the pins on the port.
0
32
no
No Effect.
0
set
Set GPIO_OUT bit in this position to '1'
1
PAD_CFG1
GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x60
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG1
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PAD_CFG2
GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x64
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG2
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PS
GPIO Pull Select Mode.
0xB8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
SR
Slew Rate Select Register.
0xAC
-1
read-only
n
0x0
0x0
VSSEL
GPIO Voltage Select.
0xC0
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN
GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.
0x4C
-1
read-only
n
0x0
0x0
GPIO_WAKE_EN
Mask of all of the pins on the port.
0
32
dis
PMU wakeup for this GPIO is disabled.
0
en
PMU wakeup for this GPIO is enabled.
1
WAKE_EN_CLR
GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.
0x54
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN_SET
GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.
0x50
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
GPIO1
Individual I/O for each GPIO 1
GPIO
0x0
0x0
0x1000
registers
n
GPIO1
GPIO1 IRQ
25
DS
GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB0
-1
read-only
n
0x0
0x0
DS
Mask of all of the pins on the port.
0
32
ld
GPIO port pin is in low-drive mode.
0
hd
GPIO port pin is in high-drive mode.
1
DS1
GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN
GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.
0x0
-1
read-only
n
0x0
0x0
GPIO_EN
Mask of all of the pins on the port.
0
32
alternate
Alternate function enabled.
0
GPIO
GPIO function is enabled.
1
EN1
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x68
-1
read-only
n
0x0
0x0
GPIO_EN1
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN1_CLR
GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.
0x70
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN1_SET
GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.
0x6C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x74
-1
read-only
n
0x0
0x0
GPIO_EN2
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN2_CLR
GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.
0x7C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2_SET
GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.
0x78
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_CLR
GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.
0x8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_SET
GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.
0x4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
IN
GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.
0x24
read-only
n
0x0
0x0
GPIO_IN
Mask of all of the pins on the port.
0
32
INT_CLR
GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.
0x48
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
INT_DUAL_EDGE
GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.
0x5C
-1
read-only
n
0x0
0x0
GPIO_INT_DUAL_EDGE
Mask of all of the pins on the port.
0
32
no
No Effect.
0
en
Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.
1
INT_EN
GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.
0x34
-1
read-only
n
0x0
0x0
GPIO_INT_EN
Mask of all of the pins on the port.
0
32
dis
Interrupts are disabled for this GPIO pin.
0
en
Interrupts are enabled for this GPIO pin.
1
INT_EN_CLR
GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.
0x3C
-1
read-only
n
0x0
0x0
GPIO_INT_EN_CLR
Mask of all of the pins on the port.
0
32
no
No Effect.
0
clear
Clear GPIO_INT_EN bit in this position to '0'
1
INT_EN_SET
GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.
0x38
-1
read-only
n
0x0
0x0
GPIO_INT_EN_SET
Mask of all of the pins on the port.
0
32
no
No effect.
0
set
Set GPIO_INT_EN bit in this position to '1'
1
INT_MOD
GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.
0x28
-1
read-only
n
0x0
0x0
GPIO_INT_MOD
Mask of all of the pins on the port.
0
32
level
Interrupts for this pin are level triggered.
0
edge
Interrupts for this pin are edge triggered.
1
INT_POL
GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.
0x2C
-1
read-only
n
0x0
0x0
GPIO_INT_POL
Mask of all of the pins on the port.
0
32
falling
Interrupts are latched on a falling edge or low level condition for this pin.
0
rising
Interrupts are latched on a rising edge or high condition for this pin.
1
INT_STAT
GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.
0x40
read-only
n
0x0
0x0
GPIO_INT_STAT
Mask of all of the pins on the port.
0
32
no
No Interrupt is pending on this GPIO pin.
0
pending
An Interrupt is pending on this GPIO pin.
1
IS
Input Hysteresis Enable Register
0xA8
-1
read-only
n
0x0
0x0
OUT
GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
0x18
-1
read-only
n
0x0
0x0
GPIO_OUT
Mask of all of the pins on the port.
0
32
low
Drive Logic 0 (low) on GPIO output.
0
high
Drive logic 1 (high) on GPIO output.
1
OUT_CLR
GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.
0x20
write-only
n
0x0
0x0
GPIO_OUT_CLR
Mask of all of the pins on the port.
0
32
OUT_EN
GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.
0xC
-1
read-only
n
0x0
0x0
GPIO_OUT_EN
Mask of all of the pins on the port.
0
32
dis
GPIO Output Disable
0
en
GPIO Output Enable
1
OUT_EN_CLR
GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.
0x14
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_EN_SET
GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.
0x10
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_SET
GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.
0x1C
write-only
n
0x0
0x0
GPIO_OUT_SET
Mask of all of the pins on the port.
0
32
no
No Effect.
0
set
Set GPIO_OUT bit in this position to '1'
1
PAD_CFG1
GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x60
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG1
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PAD_CFG2
GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x64
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG2
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PS
GPIO Pull Select Mode.
0xB8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
SR
Slew Rate Select Register.
0xAC
-1
read-only
n
0x0
0x0
VSSEL
GPIO Voltage Select.
0xC0
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN
GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.
0x4C
-1
read-only
n
0x0
0x0
GPIO_WAKE_EN
Mask of all of the pins on the port.
0
32
dis
PMU wakeup for this GPIO is disabled.
0
en
PMU wakeup for this GPIO is enabled.
1
WAKE_EN_CLR
GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.
0x54
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN_SET
GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.
0x50
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
GPIO2
Individual I/O for each GPIO 2
GPIO
0x0
0x0
0x1000
registers
n
GPIO2
GPIO2 IRQ
26
DS
GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB0
-1
read-only
n
0x0
0x0
DS
Mask of all of the pins on the port.
0
32
ld
GPIO port pin is in low-drive mode.
0
hd
GPIO port pin is in high-drive mode.
1
DS1
GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN
GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.
0x0
-1
read-only
n
0x0
0x0
GPIO_EN
Mask of all of the pins on the port.
0
32
alternate
Alternate function enabled.
0
GPIO
GPIO function is enabled.
1
EN1
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x68
-1
read-only
n
0x0
0x0
GPIO_EN1
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN1_CLR
GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.
0x70
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN1_SET
GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.
0x6C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x74
-1
read-only
n
0x0
0x0
GPIO_EN2
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN2_CLR
GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.
0x7C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2_SET
GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.
0x78
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_CLR
GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.
0x8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_SET
GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.
0x4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
IN
GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.
0x24
read-only
n
0x0
0x0
GPIO_IN
Mask of all of the pins on the port.
0
32
INT_CLR
GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.
0x48
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
INT_DUAL_EDGE
GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.
0x5C
-1
read-only
n
0x0
0x0
GPIO_INT_DUAL_EDGE
Mask of all of the pins on the port.
0
32
no
No Effect.
0
en
Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.
1
INT_EN
GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.
0x34
-1
read-only
n
0x0
0x0
GPIO_INT_EN
Mask of all of the pins on the port.
0
32
dis
Interrupts are disabled for this GPIO pin.
0
en
Interrupts are enabled for this GPIO pin.
1
INT_EN_CLR
GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.
0x3C
-1
read-only
n
0x0
0x0
GPIO_INT_EN_CLR
Mask of all of the pins on the port.
0
32
no
No Effect.
0
clear
Clear GPIO_INT_EN bit in this position to '0'
1
INT_EN_SET
GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.
0x38
-1
read-only
n
0x0
0x0
GPIO_INT_EN_SET
Mask of all of the pins on the port.
0
32
no
No effect.
0
set
Set GPIO_INT_EN bit in this position to '1'
1
INT_MOD
GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.
0x28
-1
read-only
n
0x0
0x0
GPIO_INT_MOD
Mask of all of the pins on the port.
0
32
level
Interrupts for this pin are level triggered.
0
edge
Interrupts for this pin are edge triggered.
1
INT_POL
GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.
0x2C
-1
read-only
n
0x0
0x0
GPIO_INT_POL
Mask of all of the pins on the port.
0
32
falling
Interrupts are latched on a falling edge or low level condition for this pin.
0
rising
Interrupts are latched on a rising edge or high condition for this pin.
1
INT_STAT
GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.
0x40
read-only
n
0x0
0x0
GPIO_INT_STAT
Mask of all of the pins on the port.
0
32
no
No Interrupt is pending on this GPIO pin.
0
pending
An Interrupt is pending on this GPIO pin.
1
IS
Input Hysteresis Enable Register
0xA8
-1
read-only
n
0x0
0x0
OUT
GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
0x18
-1
read-only
n
0x0
0x0
GPIO_OUT
Mask of all of the pins on the port.
0
32
low
Drive Logic 0 (low) on GPIO output.
0
high
Drive logic 1 (high) on GPIO output.
1
OUT_CLR
GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.
0x20
write-only
n
0x0
0x0
GPIO_OUT_CLR
Mask of all of the pins on the port.
0
32
OUT_EN
GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.
0xC
-1
read-only
n
0x0
0x0
GPIO_OUT_EN
Mask of all of the pins on the port.
0
32
dis
GPIO Output Disable
0
en
GPIO Output Enable
1
OUT_EN_CLR
GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.
0x14
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_EN_SET
GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.
0x10
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_SET
GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.
0x1C
write-only
n
0x0
0x0
GPIO_OUT_SET
Mask of all of the pins on the port.
0
32
no
No Effect.
0
set
Set GPIO_OUT bit in this position to '1'
1
PAD_CFG1
GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x60
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG1
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PAD_CFG2
GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x64
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG2
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PS
GPIO Pull Select Mode.
0xB8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
SR
Slew Rate Select Register.
0xAC
-1
read-only
n
0x0
0x0
VSSEL
GPIO Voltage Select.
0xC0
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN
GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.
0x4C
-1
read-only
n
0x0
0x0
GPIO_WAKE_EN
Mask of all of the pins on the port.
0
32
dis
PMU wakeup for this GPIO is disabled.
0
en
PMU wakeup for this GPIO is enabled.
1
WAKE_EN_CLR
GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.
0x54
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN_SET
GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.
0x50
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
GPIO3
Individual I/O for each GPIO 3
GPIO
0x0
0x0
0x1000
registers
n
GPIO3
GPIO3 IRQ
58
DS
GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB0
-1
read-only
n
0x0
0x0
DS
Mask of all of the pins on the port.
0
32
ld
GPIO port pin is in low-drive mode.
0
hd
GPIO port pin is in high-drive mode.
1
DS1
GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN
GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.
0x0
-1
read-only
n
0x0
0x0
GPIO_EN
Mask of all of the pins on the port.
0
32
alternate
Alternate function enabled.
0
GPIO
GPIO function is enabled.
1
EN1
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x68
-1
read-only
n
0x0
0x0
GPIO_EN1
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN1_CLR
GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.
0x70
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN1_SET
GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.
0x6C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x74
-1
read-only
n
0x0
0x0
GPIO_EN2
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN2_CLR
GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.
0x7C
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN2_SET
GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.
0x78
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_CLR
GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.
0x8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
EN_SET
GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.
0x4
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
IN
GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.
0x24
read-only
n
0x0
0x0
GPIO_IN
Mask of all of the pins on the port.
0
32
INT_CLR
GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.
0x48
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
INT_DUAL_EDGE
GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.
0x5C
-1
read-only
n
0x0
0x0
GPIO_INT_DUAL_EDGE
Mask of all of the pins on the port.
0
32
no
No Effect.
0
en
Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.
1
INT_EN
GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.
0x34
-1
read-only
n
0x0
0x0
GPIO_INT_EN
Mask of all of the pins on the port.
0
32
dis
Interrupts are disabled for this GPIO pin.
0
en
Interrupts are enabled for this GPIO pin.
1
INT_EN_CLR
GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.
0x3C
-1
read-only
n
0x0
0x0
GPIO_INT_EN_CLR
Mask of all of the pins on the port.
0
32
no
No Effect.
0
clear
Clear GPIO_INT_EN bit in this position to '0'
1
INT_EN_SET
GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.
0x38
-1
read-only
n
0x0
0x0
GPIO_INT_EN_SET
Mask of all of the pins on the port.
0
32
no
No effect.
0
set
Set GPIO_INT_EN bit in this position to '1'
1
INT_MOD
GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.
0x28
-1
read-only
n
0x0
0x0
GPIO_INT_MOD
Mask of all of the pins on the port.
0
32
level
Interrupts for this pin are level triggered.
0
edge
Interrupts for this pin are edge triggered.
1
INT_POL
GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.
0x2C
-1
read-only
n
0x0
0x0
GPIO_INT_POL
Mask of all of the pins on the port.
0
32
falling
Interrupts are latched on a falling edge or low level condition for this pin.
0
rising
Interrupts are latched on a rising edge or high condition for this pin.
1
INT_STAT
GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.
0x40
read-only
n
0x0
0x0
GPIO_INT_STAT
Mask of all of the pins on the port.
0
32
no
No Interrupt is pending on this GPIO pin.
0
pending
An Interrupt is pending on this GPIO pin.
1
IS
Input Hysteresis Enable Register
0xA8
-1
read-only
n
0x0
0x0
OUT
GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
0x18
-1
read-only
n
0x0
0x0
GPIO_OUT
Mask of all of the pins on the port.
0
32
low
Drive Logic 0 (low) on GPIO output.
0
high
Drive logic 1 (high) on GPIO output.
1
OUT_CLR
GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.
0x20
write-only
n
0x0
0x0
GPIO_OUT_CLR
Mask of all of the pins on the port.
0
32
OUT_EN
GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.
0xC
-1
read-only
n
0x0
0x0
GPIO_OUT_EN
Mask of all of the pins on the port.
0
32
dis
GPIO Output Disable
0
en
GPIO Output Enable
1
OUT_EN_CLR
GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.
0x14
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_EN_SET
GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.
0x10
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
OUT_SET
GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.
0x1C
write-only
n
0x0
0x0
GPIO_OUT_SET
Mask of all of the pins on the port.
0
32
no
No Effect.
0
set
Set GPIO_OUT bit in this position to '1'
1
PAD_CFG1
GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x60
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG1
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PAD_CFG2
GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x64
-1
read-only
n
0x0
0x0
GPIO_PAD_CFG2
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PS
GPIO Pull Select Mode.
0xB8
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
SR
Slew Rate Select Register.
0xAC
-1
read-only
n
0x0
0x0
VSSEL
GPIO Voltage Select.
0xC0
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN
GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.
0x4C
-1
read-only
n
0x0
0x0
GPIO_WAKE_EN
Mask of all of the pins on the port.
0
32
dis
PMU wakeup for this GPIO is disabled.
0
en
PMU wakeup for this GPIO is enabled.
1
WAKE_EN_CLR
GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.
0x54
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN_SET
GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.
0x50
-1
read-only
n
0x0
0x0
ALL
Mask of all of the pins on the port.
0
32
HPB
HyperBus.
HPB
0x0
0x0
0x1000
registers
n
HPB
HPB Interrupt.
61
INTEN
Interrupt Enable Control Register.
0x4
read-write
n
0x0
0x0
ERRINTE
Error Interrupt Enable.
1
2
read-write
INTFL
Interrupt Status Register.
0x8
read-only
n
0x0
0x0
ERRINTE
Error Interrupt Status.
1
2
read-only
MBR0
Memory Base Address Registers.
0x10
-1
read-write
n
0x0
0x0
ADDR
Base address for memory space 0.
24
32
read-write
MBR1
Memory Base Address Registers.
0x14
-1
read-write
n
0x0
0x0
ADDR
Base address for memory space 0.
24
32
read-write
MBR[0]
Memory Base Address Registers.
0x20
read-write
n
0x0
0x0
ADDR
Base address for memory space 0.
24
32
read-write
MBR[1]
Memory Base Address Registers.
0x34
read-write
n
0x0
0x0
ADDR
Base address for memory space 0.
24
32
read-write
MCR0
Memory Configuration Registers.
0x20
-1
read-write
n
0x0
0x0
CRT
Configuration Register Target.
5
6
read-write
DEVTYPE
Device Type.
3
5
read-write
HYPER_FLASH
Hyper flash device.
0
XCCELA_PSRAM
Hyper PSRAM device.
1
HYPER_RAM
Hyper RAM device.
2
FRL
Fixed Read latency enable.
6
7
read-write
HSE
Halt Sleep Exit.
7
8
read-write
MAXEN
Maximum length Enable.
31
32
read-write
MAXLEN
Maximum Length.
18
27
read-write
MCR1
Memory Configuration Registers.
0x24
-1
read-write
n
0x0
0x0
CRT
Configuration Register Target.
5
6
read-write
DEVTYPE
Device Type.
3
5
read-write
HYPER_FLASH
Hyper flash device.
0
XCCELA_PSRAM
Hyper PSRAM device.
1
HYPER_RAM
Hyper RAM device.
2
FRL
Fixed Read latency enable.
6
7
read-write
HSE
Halt Sleep Exit.
7
8
read-write
MAXEN
Maximum length Enable.
31
32
read-write
MAXLEN
Maximum Length.
18
27
read-write
MCR[0]
Memory Configuration Registers.
0x40
read-write
n
0x0
0x0
CRT
Configuration Register Target.
5
6
read-write
DEVTYPE
Device Type.
3
5
read-write
HYPER_FLASH
Hyper flash device.
0
XCCELA_PSRAM
Hyper PSRAM device.
1
HYPER_RAM
Hyper RAM device.
2
FRL
Fixed Read latency enable.
6
7
read-write
HSE
Halt Sleep Exit.
7
8
read-write
MAXEN
Maximum length Enable.
31
32
read-write
MAXLEN
Maximum Length.
18
27
read-write
MCR[1]
Memory Configuration Registers.
0x64
read-write
n
0x0
0x0
CRT
Configuration Register Target.
5
6
read-write
DEVTYPE
Device Type.
3
5
read-write
HYPER_FLASH
Hyper flash device.
0
XCCELA_PSRAM
Hyper PSRAM device.
1
HYPER_RAM
Hyper RAM device.
2
FRL
Fixed Read latency enable.
6
7
read-write
HSE
Halt Sleep Exit.
7
8
read-write
MAXEN
Maximum length Enable.
31
32
read-write
MAXLEN
Maximum Length.
18
27
read-write
MTR0
Memory Timing Registers.
0x30
-1
read-write
n
0x0
0x0
LTCY
Latency Cycle for HyperRAM mode.
0
4
read-write
5CLOCK
5 clock latency.
0
3CLOCK
3 clock latency.
0xE
4CLOCK
4 clock latency.
0xF
6CLOCK
6 clock latency.
1
RCSH
Read Chip Select Hold After CK falling Edge.
12
16
read-write
RCSHI
Read Chip Select High Between Operations.
28
32
read-write
RCSS
Read Chip Select Setup To Next CK Rising Edge.
20
24
read-write
WCSH
Write Chip Select Hold After CK falling Edge.
8
12
read-write
WCSHI
Write Chip Select High Between Operations.
24
28
read-write
WCSS
Write Chip Select Setup To Next CK Rising Edge.
16
20
read-write
MTR1
Memory Timing Registers.
0x34
-1
read-write
n
0x0
0x0
LTCY
Latency Cycle for HyperRAM mode.
0
4
read-write
5CLOCK
5 clock latency.
0
3CLOCK
3 clock latency.
0xE
4CLOCK
4 clock latency.
0xF
6CLOCK
6 clock latency.
1
RCSH
Read Chip Select Hold After CK falling Edge.
12
16
read-write
RCSHI
Read Chip Select High Between Operations.
28
32
read-write
RCSS
Read Chip Select Setup To Next CK Rising Edge.
20
24
read-write
WCSH
Write Chip Select Hold After CK falling Edge.
8
12
read-write
WCSHI
Write Chip Select High Between Operations.
24
28
read-write
WCSS
Write Chip Select Setup To Next CK Rising Edge.
16
20
read-write
MTR[0]
Memory Timing Registers.
0x60
read-write
n
0x0
0x0
LTCY
Latency Cycle for HyperRAM mode.
0
4
read-write
5CLOCK
5 clock latency.
0
3CLOCK
3 clock latency.
0xE
4CLOCK
4 clock latency.
0xF
6CLOCK
6 clock latency.
1
RCSH
Read Chip Select Hold After CK falling Edge.
12
16
read-write
RCSHI
Read Chip Select High Between Operations.
28
32
read-write
RCSS
Read Chip Select Setup To Next CK Rising Edge.
20
24
read-write
WCSH
Write Chip Select Hold After CK falling Edge.
8
12
read-write
WCSHI
Write Chip Select High Between Operations.
24
28
read-write
WCSS
Write Chip Select Setup To Next CK Rising Edge.
16
20
read-write
MTR[1]
Memory Timing Registers.
0x94
read-write
n
0x0
0x0
LTCY
Latency Cycle for HyperRAM mode.
0
4
read-write
5CLOCK
5 clock latency.
0
3CLOCK
3 clock latency.
0xE
4CLOCK
4 clock latency.
0xF
6CLOCK
6 clock latency.
1
RCSH
Read Chip Select Hold After CK falling Edge.
12
16
read-write
RCSHI
Read Chip Select High Between Operations.
28
32
read-write
RCSS
Read Chip Select Setup To Next CK Rising Edge.
20
24
read-write
WCSH
Write Chip Select Hold After CK falling Edge.
8
12
read-write
WCSHI
Write Chip Select High Between Operations.
24
28
read-write
WCSS
Write Chip Select Setup To Next CK Rising Edge.
16
20
read-write
STATUS
Controller Status Register.
0x0
read-only
n
0x0
0x0
RACT
Read Transaction Active.
0
1
read-only
RDECERR
Decode Error in Read Transaction.
8
9
read-only
RDSSTALL
RDS Stall Error in Read Transaction.
11
12
read-only
RRSTOERR
RSTO Error in Read Transaction.
10
11
read-only
WACT
Write Transaction Active.
16
17
read-only
WDECERR
Decode Error in Write Transaction.
24
25
read-only
WRSTOERR
RSTO Error in Write Transaction.
26
27
read-only
I2C0
Inter-Integrated Circuit.
I2C
0x0
0x0
0x1000
registers
n
I2C0
I2C0 IRQ
13
CLK_HI
Clock high Register.
0x38
-1
read-only
n
0x0
0x0
CKH
Clock High. In master mode, these bits define the SCL high period.
0
9
CLK_LO
Clock Low Register.
0x34
-1
read-only
n
0x0
0x0
CLK_LO
Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.
0
9
CTRL
Control Register0.
0x0
-1
read-only
n
0x0
0x0
GEN_CALL_ADDR
General Call Address Enable.
2
3
read-write
dis
Ignore Gneral Call Address.
0
en
Acknowledge general call address.
1
HS_MODE
Hs-mode Enable.
15
1
dis
Hs-mode disabled.
0
en
Hs-mode enabled.
1
I2C_EN
I2C Enable.
0
1
read-write
dis
Disable I2C.
0
en
enable I2C.
1
MST
Master Mode Enable.
1
2
read-write
slave_mode
Slave Mode.
0
master_mode
Master Mode.
1
READ
Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.
11
12
read-only
write
Write.
0
read
Read.
1
RX_MODE
Interactive Receive Mode.
3
4
read-write
dis
Disable Interactive Receive Mode.
0
en
Enable Interactive Receive Mode.
1
RX_MODE_ACK
Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.
4
5
read-write
ack
return ACK (pulling SDA LOW).
0
nack
return NACK (leaving SDA HIGH).
1
SCL
SCL status. This bit reflects the logic gate of SCL signal.
8
9
read-only
SCL_CLK_STRECH_DIS
This bit will disable slave clock stretching when set.
12
13
read-write
en
Slave clock stretching enabled.
0
dis
Slave clock stretching disabled.
1
SCL_OUT
SCL Output. This bits control SCL output when SWOE =1.
6
7
read-write
drive_scl_low
Drive SCL low.
0
release_scl
Release SCL.
1
SCL_PP_MODE
SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.
13
14
read-write
dis
Standard open-drain operation: drive low for 0, Hi-Z for 1
0
en
Non-standard push-pull operation: drive low for 0, drive high for 1
1
SDA
SDA status. THis bit reflects the logic gate of SDA signal.
9
10
read-only
SDA_OUT
SDA Output. This bits control SDA output when SWOE = 1.
7
8
read-write
drive_sda_low
Drive SDA low.
0
release_sda
Release SDA.
1
SW_OUT_EN
Software Output Enable.
10
11
read-write
outputs_disable
I2C Outputs SCLO and SDAO disabled.
0
outputs_enable
I2C Outputs SCLO and SDAO enabled.
1
DMA
DMA Register.
0x48
-1
read-only
n
0x0
0x0
RX_EN
RX channel enable.
1
2
dis
Disable.
0
en
Enable.
1
TX_EN
TX channel enable.
0
1
dis
Disable.
0
en
Enable.
1
FIFO
Data Register.
0x2C
-1
read-only
n
0x0
0x0
DATA
Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.
0
8
FIFO_LEN
FIFO Configuration Register.
0x18
-1
read-only
n
0x0
0x0
RX_LEN
Receive FIFO Length.
0
8
read-only
TX_LEN
Transmit FIFO Length.
8
16
read-only
HS_CLK
HS-Mode Clock Control Register
0x3C
-1
read-only
n
0x0
0x0
HS_CLK_HI
Slave Address.
8
16
HS_CLK_LO
Slave Address.
0
8
INT_EN0
Interrupt Enable Register.
0xC
read-write
n
0x0
0x0
ADDR_ACK
Received Address ACK from Slave Interrupt.
7
8
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
ADDR_ER
Master Mode Address NACK Received Interrupt.
10
11
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
ADDR_MATCH
Slave mode incoming address match interrupt.
3
4
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when ADDR_MATCH = 1.
1
ARB_ER
Master Mode Arbitration Lost Interrupt.
8
9
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
DATA_ER
Master Mode Data NACK Received Interrupt.
11
12
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
DONE
Transfer Done Interrupt Enable.
0
1
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when DONE = 1.
1
DO_NOT_RESP_ER
Slave Mode Do Not Respond Interrupt.
12
13
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
GEN_CTRL_ADDR
Slave mode general call address match received input enable.
2
3
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when GEN_CTRL_ADDR = 1.
1
RX_MODE
Description not available.
1
2
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when RX_MODE = 1.
1
RX_THRESH
RX FIFO Above Treshold Level Interrupt Enable.
4
5
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
START_ER
Out of Sequence START condition detected interrupt.
13
14
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
STOP
Stop Interrupt Enable
6
7
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when STOP = 1.
1
STOP_ER
Out of Sequence STOP condition detected interrupt.
14
15
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
TO_ER
Timeout Error Interrupt Enable.
9
10
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
TX_LOCK_OUT
TX FIFO Locked Out Interrupt.
15
16
dis
Interrupt disabled.
0
en
Interrupt enabled when TXLOIE = 1.
1
TX_THRESH
TX FIFO Below Treshold Level Interrupt Enable.
5
6
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
INT_EN1
Interrupt Staus Register 1.
0x14
read-write
n
0x0
0x0
RX_OVERFLOW
Receiver Overflow Interrupt Enable.
0
1
dis
No Interrupt is Pending.
0
en
An interrupt is pending.
1
TX_UNDERFLOW
Transmit Underflow Interrupt Enable.
1
2
dis
No Interrupt is Pending.
0
en
An interrupt is pending.
1
INT_FL0
Interrupt Status Register.
0x8
-1
read-only
n
0x0
0x0
ADDR_ACK
Address Acknowledge Interrupt.
7
8
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ADDR_MATCH
Slave Address Match Interrupt.
3
4
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ADDR_NACK_ER
Address NACK Error Interrupt.
10
11
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ARB_ER
Arbritation error Interrupt.
8
9
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DATA_ER
Data NACK Error Interrupt.
11
12
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DONE
Transfer Done Interrupt.
0
1
INT_FL0_Done
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DO_NOT_RESP_ER
Do Not Respond Error Interrupt.
12
13
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
GEN_CALL_ADDR
Slave General Call Address Match Interrupt.
2
3
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
RX_MODE
Interactive Receive Interrupt.
1
2
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
RX_THRESH
Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.
4
5
inactive
No interrupt is pending.
0
pending
An interrupt is pending. RX_FIFO equal or more bytes than the threshold.
1
START_ER
Start Error Interrupt.
13
14
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
STOP
STOP Interrupt.
6
7
inactive
No interrupt is pending.
0
pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
1
STOP_ER
Stop Error Interrupt.
14
15
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TO_ER
timeout Error Interrupt.
9
10
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TX_LOCK_OUT
Transmit Lock Out Interrupt.
15
16
TX_THRESH
Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.
5
6
inactive
No interrupt is pending.
0
pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
1
INT_FL1
Interrupt Status Register 1.
0x10
-1
read-only
n
0x0
0x0
RX_OVERFLOW
Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.
0
1
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TX_UNDERFLOW
Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).
1
2
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
MASTER_CTRL
Master Control Register.
0x30
-1
read-only
n
0x0
0x0
MASTER_CODE
Master Code. These bits set the Master Code used in Hs-mode operation.
8
11
RESTART
Setting this bit to 1 will generate a repeated START.
1
2
SCL_SPEED_UP
Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.
11
12
en
Master monitors SCL state.
0
dis
SCL state monitoring disabled.
1
SL_EX_ADDR
Slave Extend Address Select.
7
8
7_bits_address
7-bit address.
0
10_bits_address
10-bit address.
1
START
Setting this bit to 1 will start a master transfer.
0
1
STOP
Setting this bit to 1 will generate a STOP condition.
2
3
RX_CTRL0
Receive Control Register 0.
0x1C
-1
read-only
n
0x0
0x0
DNR
Do Not Respond.
0
1
respond
Always respond to address match.
0
not_respond_rx_fifo_empty
Do not respond to address match when RX_FIFO is not empty.
1
RX_FLUSH
Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.
7
8
not_flushed
FIFO not flushed.
0
flush
Flush RX_FIFO.
1
RX_THRESH
Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.
8
12
RX_CTRL1
Receive Control Register 1.
0x20
-1
read-only
n
0x0
0x0
RX_CNT
Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.
0
8
RX_FIFO
Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.
8
12
read-only
SLAVE_ADDR
Slave Address Register.
0x44
-1
read-only
n
0x0
0x0
EX_ADDR
Extended Address Select.
15
16
7_bits_address
7-bit address.
0
10_bits_address
10-bit address.
1
SLAVE_ADDR
Slave Address.
0
10
SLAVE_ADDR_DIS
Slave Address DIS.
10
11
SLAVE_ADDR_IDX
Slave Address Index.
11
15
STATUS
Status Register.
0x4
-1
read-only
n
0x0
0x0
BUS
Bus Status.
0
1
read-only
idle
I2C Bus Idle.
0
busy
I2C Bus Busy.
1
CLK_MODE
Clock Mode.
5
6
read-only
not_actively_driving_scl_clock
Device not actively driving SCL clock cycles.
0
actively_driving_scl_clock
Device operating as master and actively driving SCL clock cycles.
1
RX_EMPTY
RX empty.
1
2
read-only
not_empty
Not Empty.
0
empty
Empty.
1
RX_FULL
RX Full.
2
3
read-only
not_full
Not Full.
0
full
Full.
1
STATUS
Controller Status.
8
12
idle
Controller Idle.
0
mtx_addr
master Transmit address.
1
rx_ack
Receive data ACK (master or slave).
10
rx
Receive data (master or slave).
11
tx_ack
Transmit data ACK (master or slave).
12
nack
NACK stage (master or slave).
13
by_st
Bystander state (ongoing transaction but not participant- another master addressing another slave).
15
mrx_addr_ack
Master Receive address ACK.
2
mtx_ex_addr
Master Transmit extended address.
3
mrx_ex_addr
Master Receive extended address ACK.
4
srx_addr
Slave Receive address.
5
stx_addr_ack
Slave Transmit address ACK.
6
srx_ex_addr
Slave Receive extended address.
7
stx_ex_addr_ack
Slave Transmit extended address ACK.
8
tx
Transmit data (master or slave).
9
TX_EMPTY
TX Empty.
3
4
not_empty
Not Empty.
0
empty
Empty.
1
TX_FULL
TX Full.
4
5
not_empty
Not Empty.
0
empty
Empty.
1
TIMEOUT
Timeout Register
0x40
-1
read-only
n
0x0
0x0
TO
Timeout
0
16
TX_CTRL0
Transmit Control Register 0.
0x24
-1
read-only
n
0x0
0x0
TX_FLUSH
Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.
7
8
not_flushed
FIFO not flushed.
0
flush
Flush TX_FIFO.
1
TX_PRELOAD
Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.
0
1
TX_READY_MODE
Transmit FIFO Ready Manual Mode.
1
2
en
HW control of I2CTXRDY enabled.
0
dis
HW control of I2CTXRDY disabled.
1
TX_THRESH
Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.
8
12
TX_CTRL1
Transmit Control Register 1.
0x28
-1
read-only
n
0x0
0x0
TX_FIFO
Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.
8
12
read-only
TX_LAST
Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).
1
2
hold_scl_low
Hold SCL low on TX_FIFO empty.
0
end_transaction
End transaction on TX_FIFO empty.
1
TX_READY
Transmit FIFO Preload Ready.
0
1
I2C1
Inter-Integrated Circuit. 1
I2C
0x0
0x0
0x1000
registers
n
I2C1
I2C1 IRQ
36
CLK_HI
Clock high Register.
0x38
-1
read-only
n
0x0
0x0
CKH
Clock High. In master mode, these bits define the SCL high period.
0
9
CLK_LO
Clock Low Register.
0x34
-1
read-only
n
0x0
0x0
CLK_LO
Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.
0
9
CTRL
Control Register0.
0x0
-1
read-only
n
0x0
0x0
GEN_CALL_ADDR
General Call Address Enable.
2
3
read-write
dis
Ignore Gneral Call Address.
0
en
Acknowledge general call address.
1
HS_MODE
Hs-mode Enable.
15
1
dis
Hs-mode disabled.
0
en
Hs-mode enabled.
1
I2C_EN
I2C Enable.
0
1
read-write
dis
Disable I2C.
0
en
enable I2C.
1
MST
Master Mode Enable.
1
2
read-write
slave_mode
Slave Mode.
0
master_mode
Master Mode.
1
READ
Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.
11
12
read-only
write
Write.
0
read
Read.
1
RX_MODE
Interactive Receive Mode.
3
4
read-write
dis
Disable Interactive Receive Mode.
0
en
Enable Interactive Receive Mode.
1
RX_MODE_ACK
Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.
4
5
read-write
ack
return ACK (pulling SDA LOW).
0
nack
return NACK (leaving SDA HIGH).
1
SCL
SCL status. This bit reflects the logic gate of SCL signal.
8
9
read-only
SCL_CLK_STRECH_DIS
This bit will disable slave clock stretching when set.
12
13
read-write
en
Slave clock stretching enabled.
0
dis
Slave clock stretching disabled.
1
SCL_OUT
SCL Output. This bits control SCL output when SWOE =1.
6
7
read-write
drive_scl_low
Drive SCL low.
0
release_scl
Release SCL.
1
SCL_PP_MODE
SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.
13
14
read-write
dis
Standard open-drain operation: drive low for 0, Hi-Z for 1
0
en
Non-standard push-pull operation: drive low for 0, drive high for 1
1
SDA
SDA status. THis bit reflects the logic gate of SDA signal.
9
10
read-only
SDA_OUT
SDA Output. This bits control SDA output when SWOE = 1.
7
8
read-write
drive_sda_low
Drive SDA low.
0
release_sda
Release SDA.
1
SW_OUT_EN
Software Output Enable.
10
11
read-write
outputs_disable
I2C Outputs SCLO and SDAO disabled.
0
outputs_enable
I2C Outputs SCLO and SDAO enabled.
1
DMA
DMA Register.
0x48
-1
read-only
n
0x0
0x0
RX_EN
RX channel enable.
1
2
dis
Disable.
0
en
Enable.
1
TX_EN
TX channel enable.
0
1
dis
Disable.
0
en
Enable.
1
FIFO
Data Register.
0x2C
-1
read-only
n
0x0
0x0
DATA
Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.
0
8
FIFO_LEN
FIFO Configuration Register.
0x18
-1
read-only
n
0x0
0x0
RX_LEN
Receive FIFO Length.
0
8
read-only
TX_LEN
Transmit FIFO Length.
8
16
read-only
HS_CLK
HS-Mode Clock Control Register
0x3C
-1
read-only
n
0x0
0x0
HS_CLK_HI
Slave Address.
8
16
HS_CLK_LO
Slave Address.
0
8
INT_EN0
Interrupt Enable Register.
0xC
read-write
n
0x0
0x0
ADDR_ACK
Received Address ACK from Slave Interrupt.
7
8
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
ADDR_ER
Master Mode Address NACK Received Interrupt.
10
11
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
ADDR_MATCH
Slave mode incoming address match interrupt.
3
4
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when ADDR_MATCH = 1.
1
ARB_ER
Master Mode Arbitration Lost Interrupt.
8
9
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
DATA_ER
Master Mode Data NACK Received Interrupt.
11
12
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
DONE
Transfer Done Interrupt Enable.
0
1
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when DONE = 1.
1
DO_NOT_RESP_ER
Slave Mode Do Not Respond Interrupt.
12
13
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
GEN_CTRL_ADDR
Slave mode general call address match received input enable.
2
3
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when GEN_CTRL_ADDR = 1.
1
RX_MODE
Description not available.
1
2
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when RX_MODE = 1.
1
RX_THRESH
RX FIFO Above Treshold Level Interrupt Enable.
4
5
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
START_ER
Out of Sequence START condition detected interrupt.
13
14
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
STOP
Stop Interrupt Enable
6
7
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when STOP = 1.
1
STOP_ER
Out of Sequence STOP condition detected interrupt.
14
15
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
TO_ER
Timeout Error Interrupt Enable.
9
10
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
TX_LOCK_OUT
TX FIFO Locked Out Interrupt.
15
16
dis
Interrupt disabled.
0
en
Interrupt enabled when TXLOIE = 1.
1
TX_THRESH
TX FIFO Below Treshold Level Interrupt Enable.
5
6
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
INT_EN1
Interrupt Staus Register 1.
0x14
read-write
n
0x0
0x0
RX_OVERFLOW
Receiver Overflow Interrupt Enable.
0
1
dis
No Interrupt is Pending.
0
en
An interrupt is pending.
1
TX_UNDERFLOW
Transmit Underflow Interrupt Enable.
1
2
dis
No Interrupt is Pending.
0
en
An interrupt is pending.
1
INT_FL0
Interrupt Status Register.
0x8
-1
read-only
n
0x0
0x0
ADDR_ACK
Address Acknowledge Interrupt.
7
8
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ADDR_MATCH
Slave Address Match Interrupt.
3
4
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ADDR_NACK_ER
Address NACK Error Interrupt.
10
11
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ARB_ER
Arbritation error Interrupt.
8
9
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DATA_ER
Data NACK Error Interrupt.
11
12
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DONE
Transfer Done Interrupt.
0
1
INT_FL0_Done
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DO_NOT_RESP_ER
Do Not Respond Error Interrupt.
12
13
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
GEN_CALL_ADDR
Slave General Call Address Match Interrupt.
2
3
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
RX_MODE
Interactive Receive Interrupt.
1
2
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
RX_THRESH
Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.
4
5
inactive
No interrupt is pending.
0
pending
An interrupt is pending. RX_FIFO equal or more bytes than the threshold.
1
START_ER
Start Error Interrupt.
13
14
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
STOP
STOP Interrupt.
6
7
inactive
No interrupt is pending.
0
pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
1
STOP_ER
Stop Error Interrupt.
14
15
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TO_ER
timeout Error Interrupt.
9
10
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TX_LOCK_OUT
Transmit Lock Out Interrupt.
15
16
TX_THRESH
Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.
5
6
inactive
No interrupt is pending.
0
pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
1
INT_FL1
Interrupt Status Register 1.
0x10
-1
read-only
n
0x0
0x0
RX_OVERFLOW
Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.
0
1
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TX_UNDERFLOW
Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).
1
2
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
MASTER_CTRL
Master Control Register.
0x30
-1
read-only
n
0x0
0x0
MASTER_CODE
Master Code. These bits set the Master Code used in Hs-mode operation.
8
11
RESTART
Setting this bit to 1 will generate a repeated START.
1
2
SCL_SPEED_UP
Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.
11
12
en
Master monitors SCL state.
0
dis
SCL state monitoring disabled.
1
SL_EX_ADDR
Slave Extend Address Select.
7
8
7_bits_address
7-bit address.
0
10_bits_address
10-bit address.
1
START
Setting this bit to 1 will start a master transfer.
0
1
STOP
Setting this bit to 1 will generate a STOP condition.
2
3
RX_CTRL0
Receive Control Register 0.
0x1C
-1
read-only
n
0x0
0x0
DNR
Do Not Respond.
0
1
respond
Always respond to address match.
0
not_respond_rx_fifo_empty
Do not respond to address match when RX_FIFO is not empty.
1
RX_FLUSH
Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.
7
8
not_flushed
FIFO not flushed.
0
flush
Flush RX_FIFO.
1
RX_THRESH
Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.
8
12
RX_CTRL1
Receive Control Register 1.
0x20
-1
read-only
n
0x0
0x0
RX_CNT
Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.
0
8
RX_FIFO
Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.
8
12
read-only
SLAVE_ADDR
Slave Address Register.
0x44
-1
read-only
n
0x0
0x0
EX_ADDR
Extended Address Select.
15
16
7_bits_address
7-bit address.
0
10_bits_address
10-bit address.
1
SLAVE_ADDR
Slave Address.
0
10
SLAVE_ADDR_DIS
Slave Address DIS.
10
11
SLAVE_ADDR_IDX
Slave Address Index.
11
15
STATUS
Status Register.
0x4
-1
read-only
n
0x0
0x0
BUS
Bus Status.
0
1
read-only
idle
I2C Bus Idle.
0
busy
I2C Bus Busy.
1
CLK_MODE
Clock Mode.
5
6
read-only
not_actively_driving_scl_clock
Device not actively driving SCL clock cycles.
0
actively_driving_scl_clock
Device operating as master and actively driving SCL clock cycles.
1
RX_EMPTY
RX empty.
1
2
read-only
not_empty
Not Empty.
0
empty
Empty.
1
RX_FULL
RX Full.
2
3
read-only
not_full
Not Full.
0
full
Full.
1
STATUS
Controller Status.
8
12
idle
Controller Idle.
0
mtx_addr
master Transmit address.
1
rx_ack
Receive data ACK (master or slave).
10
rx
Receive data (master or slave).
11
tx_ack
Transmit data ACK (master or slave).
12
nack
NACK stage (master or slave).
13
by_st
Bystander state (ongoing transaction but not participant- another master addressing another slave).
15
mrx_addr_ack
Master Receive address ACK.
2
mtx_ex_addr
Master Transmit extended address.
3
mrx_ex_addr
Master Receive extended address ACK.
4
srx_addr
Slave Receive address.
5
stx_addr_ack
Slave Transmit address ACK.
6
srx_ex_addr
Slave Receive extended address.
7
stx_ex_addr_ack
Slave Transmit extended address ACK.
8
tx
Transmit data (master or slave).
9
TX_EMPTY
TX Empty.
3
4
not_empty
Not Empty.
0
empty
Empty.
1
TX_FULL
TX Full.
4
5
not_empty
Not Empty.
0
empty
Empty.
1
TIMEOUT
Timeout Register
0x40
-1
read-only
n
0x0
0x0
TO
Timeout
0
16
TX_CTRL0
Transmit Control Register 0.
0x24
-1
read-only
n
0x0
0x0
TX_FLUSH
Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.
7
8
not_flushed
FIFO not flushed.
0
flush
Flush TX_FIFO.
1
TX_PRELOAD
Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.
0
1
TX_READY_MODE
Transmit FIFO Ready Manual Mode.
1
2
en
HW control of I2CTXRDY enabled.
0
dis
HW control of I2CTXRDY disabled.
1
TX_THRESH
Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.
8
12
TX_CTRL1
Transmit Control Register 1.
0x28
-1
read-only
n
0x0
0x0
TX_FIFO
Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.
8
12
read-only
TX_LAST
Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).
1
2
hold_scl_low
Hold SCL low on TX_FIFO empty.
0
end_transaction
End transaction on TX_FIFO empty.
1
TX_READY
Transmit FIFO Preload Ready.
0
1
ICC0
Instruction Cache Controller Registers
ICC0
0x0
0x0
0x1000
registers
n
CACHE_CTRL
Cache Control and Status Register.
0x100
-1
read-only
n
0x0
0x0
CACHE_EN
Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.
0
1
dis
Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
0
en
Cache Enabled.
1
CACHE_RDY
Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.
16
1
read-only
notReady
Not Ready.
0
ready
Ready.
1
CACHE_ID
Cache ID Register.
0x0
read-only
n
0x0
0x0
CCHID
Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.
10
6
PARTNUM
Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.
6
4
RELNUM
Release Number. Identifies the RTL release version.
0
6
INVALIDATE
Invalidate All Registers.
0x700
read-write
n
0x0
0x0
MEMCFG
Memory Configuration Register.
0x4
read-only
n
0x0
0x0
CCHSZ
Cache Size. Indicates total size in Kbytes of cache.
0
16
MEMSZ
Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.
16
16
ICC1
Instruction Cache Controller Registers 1
ICC0
0x0
0x0
0x1000
registers
n
CACHE_CTRL
Cache Control and Status Register.
0x100
-1
read-only
n
0x0
0x0
CACHE_EN
Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.
0
1
dis
Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
0
en
Cache Enabled.
1
CACHE_RDY
Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.
16
1
read-only
notReady
Not Ready.
0
ready
Ready.
1
CACHE_ID
Cache ID Register.
0x0
read-only
n
0x0
0x0
CCHID
Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.
10
6
PARTNUM
Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.
6
4
RELNUM
Release Number. Identifies the RTL release version.
0
6
INVALIDATE
Invalidate All Registers.
0x700
read-write
n
0x0
0x0
MEMCFG
Memory Configuration Register.
0x4
read-only
n
0x0
0x0
CCHSZ
Cache Size. Indicates total size in Kbytes of cache.
0
16
MEMSZ
Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.
16
16
NBBFC
Non Battery-Backed Function Control.
NBBFC
0x0
0x0
0x400
registers
n
REG0
Register 0.
0x0
read-write
n
0x0
0x0
I2C0DGEN0
I2C0 SDA Pad Deglitcher enable.
20
1
dis
Deglitcher disabled.
0
en
Deglitcher enabled.
1
I2C0DGEN1
I2C0 SCL Pad Deglitcher enable.
21
1
dis
Deglitcher disabled.
0
en
Deglitcher enabled.
1
I2C1DGEN0
I2C1 SDA Pad Deglitcher enable.
22
1
dis
Deglitcher disabled.
0
en
Deglitcher enabled.
1
I2C1DGEN1
I2C1 SCL Pad Deglitcher enable.
23
1
dis
Deglitcher disabled.
0
en
Deglitcher enabled.
1
USBRCKSEL
USB External Core Clock Select.
16
1
sys
Generated clock from system clock.
0
dig
Digital clock from a GPIO.
1
REG1
Register 1.
0x4
read-write
n
0x0
0x0
ACEN
Auto-calibration Enable.
0
1
dis
Disabled.
0
en
Enabled.
1
ACRUN
Autocalibration Run.
1
1
not
Not Running.
0
run
Running.
1
ATOMIC
Atomic mode.
4
1
not
Not Running.
0
run
Running.
1
GAININV
Invert Gain.
3
1
not
Not Running.
0
run
Running.
1
LDTRM
Load Trim.
2
1
MU
MU value.
8
12
REG2
Register 2.
0x8
read-write
n
0x0
0x0
INITTRM
Initial Trim Setting.
0
9
MAXTRM
Maximum Trim Setting.
20
9
MINTRM
Minimum Trim Setting.
10
9
REG3
Register 3.
0xC
read-write
n
0x0
0x0
DONECNT
Auto-callibration Done Counter Setting.
0
8
OTP
One Time Programmable Memory controller.
OTP
0x0
0x0
0x1000
registers
n
ACNTL
Access Control Register.
0x40
read-write
n
0x0
0x0
ADATA
System Info Block Access Data.
0
32
CKDIV
Clock Divider Register.
0x4
read-write
n
0x0
0x0
CKDIV
The input clock(APB) is divided by this value.
0
2
div_by_2
Divide by 2.
0
div_by_4
Divide by 4.
1
div_by_8
Divide by 8.
2
div_by_16
Divide by 16.
3
OCNTL
OTP Control Register.
0x0
read-write
n
0x0
0x0
PA
This value is the address of the OTP 32-bit value.
0
7
PROG_OP
Setting this bit to a 1 initiates a write of the OTP location specified in the PA field.
9
1
no_operation
No Operation.
0
initiate_write_op
Initiate Write Operation.
1
RD_OP
Setting this bit to a 1 initiates a read of the OTP location specified in the PA field.
8
1
no_operation
No Operation.
0
initiate_read_op
Initiate Read Operation.
1
ODATA
Write Data Register.
0x30
write-only
n
0x0
0x0
OTPDATA
OTP write data.
0
32
OTPRDATA
Read Data Register.
0x8
read-write
n
0x0
0x0
RDATA
OTP Data Output from read operation.
0
32
read-only
STAT
OTP Status Register.
0xC
read-only
n
0x0
0x0
BUSY
This flag indicates whether the OTP controller is currently performing a read or write operation.
0
1
read-only
not_busy
OTP controller ready for new operation.
0
busy
OTP controller busy either programming or reading.
1
FAIL
Description not available.
1
1
nfail
No failure.
0
fail
Failure occurs.
1
OWM
1-Wire Master Interface.
OWM
0x0
0x0
0x1000
registers
n
OneWire
1-Wire IRQ
67
CFG
1-Wire Master Configuration.
0x0
read-write
n
0x0
0x0
bit_bang_en
Bit Bang Enable.
2
3
read-write
ext_pullup_enable
Enable External Pullup.
4
5
read-write
ext_pullup_mode
Provide an extra output control to control an external pullup.
3
4
read-write
force_pres_det
Force Line During Presence Detect.
1
2
read-write
int_pullup_enable
Enable intenral pullup.
7
8
read-write
long_line_mode
Long Line Mode.
0
1
read-write
overdrive
Enables overdrive speed for 1-Wire operations.
6
7
read-write
single_bit_mode
Enable Single Bit TX/RX Mode.
5
6
read-write
CLK_DIV_1US
1-Wire Master Clock Divisor.
0x4
read-write
n
0x0
0x0
divisor
Clock Divisor for 1Mhz.
0
8
read-write
CTRL_STAT
1-Wire Master Control/Status.
0x8
read-write
n
0x0
0x0
bit_bang_oe
Bit Bang Output Enable.
2
3
read-write
ow_input
OW Input State.
3
4
read-only
presence_detect
Presence Pulse Detected.
7
8
read-only
sra_mode
SRA Mode.
1
2
read-write
start_ow_reset
Start OW Reset.
0
1
read-write
DATA
1-Wire Master Data Buffer.
0xC
read-write
n
0x0
0x0
tx_rx
TX/RX Buffer.
0
8
read-write
INTEN
1-Wire Master Interrupt Enables.
0x14
read-write
n
0x0
0x0
line_low
OW Line Low Detected Interrupt Enable.
4
5
read-write
oneToClear
line_short
OW Line Short Detected Interrupt Enable.
3
4
read-write
oneToClear
ow_reset_done
OW Reset Sequence Completed.
0
1
read-write
oneToClear
rx_data_ready
Rx Data Ready Interrupt Enable.
2
3
read-write
oneToClear
tx_data_empty
Tx Data Empty Interrupt Enable.
1
2
read-write
oneToClear
INTFL
1-Wire Master Interrupt Flags.
0x10
read-write
n
0x0
0x0
line_low
OW Line Low Detected Interrupt Flag.
4
5
read-write
line_short
OW Line Short Detected Interrupt Flag.
3
4
read-write
ow_reset_done
OW Reset Sequence Completed.
0
1
read-write
rx_data_ready
RX Data Ready Interrupt Flag
2
3
read-write
tx_data_empty
TX Data Empty Interrupt Flag.
1
2
read-write
PT
Pulse Train
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT1
Pulse Train 1
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT10
Pulse Train 10
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT11
Pulse Train 11
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT12
Pulse Train 12
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT13
Pulse Train 13
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT14
Pulse Train 14
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT15
Pulse Train 15
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT2
Pulse Train 2
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT3
Pulse Train 3
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT4
Pulse Train 4
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT5
Pulse Train 5
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT6
Pulse Train 6
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT7
Pulse Train 7
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT8
Pulse Train 8
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PT9
Pulse Train 9
Pulse Train
0x0
0x0
0x10
registers
n
LOOP
Pulse Train Loop Count
0x8
read-write
n
0x0
0x0
count
Number of loops for this pulse train to repeat.
0
16
read-write
delay
Delay between loops of the Pulse Train in PT Peripheral Clock cycles
16
12
read-write
RATE_LENGTH
Pulse Train Configuration
0x0
read-write
n
0x0
0x0
mode
Pulse Train Output Mode/Train Length
27
5
read-write
32_BIT
Pulse train, 32 bit pattern.
0
SQUARE_WAVE
Square wave mode.
1
10_BIT
Pulse train, 10 bit pattern.
10
11_BIT
Pulse train, 11 bit pattern.
11
12_BIT
Pulse train, 12 bit pattern.
12
13_BIT
Pulse train, 13 bit pattern.
13
14_BIT
Pulse train, 14 bit pattern.
14
15_BIT
Pulse train, 15 bit pattern.
15
16_BIT
Pulse train, 16 bit pattern.
16
17_BIT
Pulse train, 17 bit pattern.
17
18_BIT
Pulse train, 18 bit pattern.
18
19_BIT
Pulse train, 19 bit pattern.
19
2_BIT
Pulse train, 2 bit pattern.
2
20_BIT
Pulse train, 20 bit pattern.
20
21_BIT
Pulse train, 21 bit pattern.
21
22_BIT
Pulse train, 22 bit pattern.
22
23_BIT
Pulse train, 23 bit pattern.
23
24_BIT
Pulse train, 24 bit pattern.
24
25_BIT
Pulse train, 25 bit pattern.
25
26_BIT
Pulse train, 26 bit pattern.
26
27_BIT
Pulse train, 27 bit pattern.
27
28_BIT
Pulse train, 28 bit pattern.
28
29_BIT
Pulse train, 29 bit pattern.
29
3_BIT
Pulse train, 3 bit pattern.
3
30_BIT
Pulse train, 30 bit pattern.
30
31_BIT
Pulse train, 31 bit pattern.
31
4_BIT
Pulse train, 4 bit pattern.
4
5_BIT
Pulse train, 5 bit pattern.
5
6_BIT
Pulse train, 6 bit pattern.
6
7_BIT
Pulse train, 7 bit pattern.
7
8_BIT
Pulse train, 8 bit pattern.
8
9_BIT
Pulse train, 9 bit pattern.
9
rate_control
Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
0
27
read-write
RESTART
Pulse Train Auto-Restart Configuration.
0xC
read-write
n
0x0
0x0
on_pt_x_loop_exit
Enable Auto-Restart on PT X Loop Exit
7
1
read-write
on_pt_y_loop_exit
Enable Auto-Restart on PT Y Loop Exit
15
1
read-write
pt_x_select
Auto-Restart PT X Select
0
5
read-write
pt_y_select
Auto-Restart PT Y Select
8
5
read-write
TRAIN
Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
0x4
read-write
n
0x0
0x0
PTG
Pulse Train Generation
Pulse Train
0x0
0x0
0x18
registers
n
0x0
0x18
registers
n
PT
Pulse Train IRQ
59
ENABLE
Global Enable/Disable Controls for All Pulse Trains
0x0
read-write
n
0x0
0x0
pt0
Enable/Disable control for PT0
0
1
read-write
pt1
Enable/Disable control for PT1
1
1
read-write
pt10
Enable/Disable control for PT10
10
1
read-write
pt11
Enable/Disable control for PT11
11
1
read-write
pt12
Enable/Disable control for PT12
12
1
read-write
pt13
Enable/Disable control for PT13
13
1
read-write
pt14
Enable/Disable control for PT14
14
1
read-write
pt15
Enable/Disable control for PT15
15
1
read-write
pt2
Enable/Disable control for PT2
2
1
read-write
pt3
Enable/Disable control for PT3
3
1
read-write
pt4
Enable/Disable control for PT4
4
1
read-write
pt5
Enable/Disable control for PT5
5
1
read-write
pt6
Enable/Disable control for PT6
6
1
read-write
pt7
Enable/Disable control for PT7
7
1
read-write
pt8
Enable/Disable control for PT8
8
1
read-write
pt9
Enable/Disable control for PT9
9
1
read-write
INTEN
Pulse Train Interrupt Enable/Disable
0xC
read-write
n
0x0
0x0
pt0
Pulse Train 0 Stopped Interrupt Enable/Disable
0
1
read-write
pt1
Pulse Train 1 Stopped Interrupt Enable/Disable
1
1
read-write
pt10
Pulse Train 10 Stopped Interrupt Enable/Disable
10
1
read-write
pt11
Pulse Train 11 Stopped Interrupt Enable/Disable
11
1
read-write
pt12
Pulse Train 12 Stopped Interrupt Enable/Disable
12
1
read-write
pt13
Pulse Train 13 Stopped Interrupt Enable/Disable
13
1
read-write
pt14
Pulse Train 14 Stopped Interrupt Enable/Disable
14
1
read-write
pt15
Pulse Train 15 Stopped Interrupt Enable/Disable
15
1
read-write
pt2
Pulse Train 2 Stopped Interrupt Enable/Disable
2
1
read-write
pt3
Pulse Train 3 Stopped Interrupt Enable/Disable
3
1
read-write
pt4
Pulse Train 4 Stopped Interrupt Enable/Disable
4
1
read-write
pt5
Pulse Train 5 Stopped Interrupt Enable/Disable
5
1
read-write
pt6
Pulse Train 6 Stopped Interrupt Enable/Disable
6
1
read-write
pt7
Pulse Train 7 Stopped Interrupt Enable/Disable
7
1
read-write
pt8
Pulse Train 8 Stopped Interrupt Enable/Disable
8
1
read-write
pt9
Pulse Train 9 Stopped Interrupt Enable/Disable
9
1
read-write
INTFL
Pulse Train Interrupt Flags
0x8
read-write
n
0x0
0x0
pt0
Pulse Train 0 Stopped Interrupt Flag
0
1
read-write
pt1
Pulse Train 1 Stopped Interrupt Flag
1
1
read-write
pt10
Pulse Train 10 Stopped Interrupt Flag
10
1
read-write
pt11
Pulse Train 11 Stopped Interrupt Flag
11
1
read-write
pt12
Pulse Train 12 Stopped Interrupt Flag
12
1
read-write
pt13
Pulse Train 13 Stopped Interrupt Flag
13
1
read-write
pt14
Pulse Train 14 Stopped Interrupt Flag
14
1
read-write
pt15
Pulse Train 15 Stopped Interrupt Flag
15
1
read-write
pt2
Pulse Train 2 Stopped Interrupt Flag
2
1
read-write
pt3
Pulse Train 3 Stopped Interrupt Flag
3
1
read-write
pt4
Pulse Train 4 Stopped Interrupt Flag
4
1
read-write
pt5
Pulse Train 5 Stopped Interrupt Flag
5
1
read-write
pt6
Pulse Train 6 Stopped Interrupt Flag
6
1
read-write
pt7
Pulse Train 7 Stopped Interrupt Flag
7
1
read-write
pt8
Pulse Train 8 Stopped Interrupt Flag
8
1
read-write
pt9
Pulse Train 9 Stopped Interrupt Flag
9
1
read-write
RESYNC
Global Resync (All Pulse Trains) Control
0x4
read-write
n
0x0
0x0
pt0
Resync control for PT0
0
1
read-write
pt1
Resync control for PT1
1
1
read-write
pt10
Resync control for PT10
10
1
read-write
pt11
Resync control for PT11
11
1
read-write
pt12
Resync control for PT12
12
1
read-write
pt13
Resync control for PT13
13
1
read-write
pt14
Resync control for PT14
14
1
read-write
pt15
Resync control for PT15
15
1
read-write
pt2
Resync control for PT2
2
1
read-write
pt3
Resync control for PT3
3
1
read-write
pt4
Resync control for PT4
4
1
read-write
pt5
Resync control for PT5
5
1
read-write
pt6
Resync control for PT6
6
1
read-write
pt7
Resync control for PT7
7
1
read-write
pt8
Resync control for PT8
8
1
read-write
pt9
Resync control for PT9
9
1
read-write
SAFE_DIS
Pulse Train Global Safe Disable.
0x14
write-only
n
0x0
0x0
PT0
0
1
write-only
PT1
1
1
write-only
PT10
10
1
write-only
PT11
11
1
write-only
PT12
12
1
write-only
PT13
13
1
write-only
PT14
14
1
write-only
PT15
15
1
write-only
PT2
2
1
write-only
PT3
3
1
write-only
PT4
4
1
write-only
PT5
5
1
write-only
PT6
6
1
write-only
PT7
7
1
write-only
PT8
8
1
write-only
PT9
9
1
write-only
SAFE_EN
Pulse Train Global Safe Enable.
0x10
write-only
n
0x0
0x0
PT0
0
1
write-only
PT1
1
1
write-only
PT10
10
1
write-only
PT11
11
1
write-only
PT12
12
1
write-only
PT13
13
1
write-only
PT14
14
1
write-only
PT15
15
1
write-only
PT2
2
1
write-only
PT3
3
1
write-only
PT4
4
1
write-only
PT5
5
1
write-only
PT6
6
1
write-only
PT7
7
1
write-only
PT8
8
1
write-only
PT9
9
1
write-only
PWRSEQ
Power Sequencer / Low Power Control Register.
PWRSEQ
0x0
0x0
0x800
registers
n
BB_GP0
Battery Backed General Purpose Register 0
0x48
read-write
n
0x0
0x0
BB_GP1
Battery Backed General Purpose Register 1
0x4C
read-write
n
0x0
0x0
LPCN
Low Power Control Register.
0x0
read-write
n
0x0
0x0
BCKGRND
Background Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep.
9
1
dis
Disabled.
0
en
Enabled.
1
BGOFF
Bandgap OFF. This controls the System Bandgap in DeepSleep mode.
11
1
on
Bandgap is always ON.
0
off
Bandgap is OFF in DeepSleep mode(default).
1
BLKDET
Block Auto-Detect
6
1
enabled
enable
0
Disable
disable
1
FVDDEN
Flash VDD Enabled
7
1
FWKM
Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical).
10
1
dis
Disabled.
0
en
Enabled.
1
OVR
Operating Voltage Range
4
2
0_9V
0.9V 24MHz
0
1_0V
1.0V 48MHz
1
1_1V
1.1V 96MHz
2
PORVDDCMD
VDDC(VCore) Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.
12
1
dis
Disabled.
0
en
Enabled.
1
PORVDDIOHMD
VDDIOH Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIOH supply in all operating mods.
26
1
dis
Disabled.
0
en
Enabled.
1
PORVDDIOMD
VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.
25
1
dis
Disabled.
0
en
Enabled.
1
RAMRET
System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.
0
2
dis
Disable Ram Retention.
0
en1
Enable System RAM 0 retention.
1
en2
Enable System RAM 0 and 1 retention.
2
en3
Enable System RAM 0 and 1 retention, if RREGEN=0, Enable all System RAM retention.
3
RREGEN
Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode.
8
1
dis
Disabled.
0
en
Enabled.
1
VDDAMD
VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
22
1
en
Enable if Bandgap is ON(default)
0
dis
Disabled.
1
VDDBMD
VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods.
27
1
dis
Disabled.
0
en
Enabled.
1
VDDCMD
VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.
20
1
en
Enable if Bandgap is ON(default)
0
dis
Disabled.
1
VDDIOHMD
VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
24
1
en
Enable if Bandgap is ON(default)
0
dis
Disabled.
1
VDDIOMD
VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
23
1
en
Enable if Bandgap is ON(default)
0
dis
Disabled.
1
VRTCMD
VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes.
21
1
en
Enable if Bandgap is ON(default)
0
dis
Disabled.
1
LPMCREQ
Low Power Multi-Core Request
0x54
read-write
n
0x0
0x0
LPMCSTAT
Low Power Multi-Core Status
0x50
read-write
n
0x0
0x0
LPMEMSD
Low Power Memory Shutdown Control.
0x40
read-write
n
0x0
0x0
CRYPTOSD
Crypto MAA RAM Shut Down.
10
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
IC1SD
ICache 1 Shut Down.
14
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
ICACHESD
Instruction Cache RAM Shut Down.
7
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
ICACHEXIPSD
XiP Instruction Cache RAM Shut Down.
8
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
ROM1SD
ROM1 Shut Down.
13
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
ROMSD
ROM Shut Down.
12
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SCACHESD
System Cache RAM Shut Down.
9
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM0SD
System RAM block 0 Shut Down.
0
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM1SD
System RAM block 1 Shut Down.
1
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM2SD
System RAM block 2 Shut Down.
2
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM3SD
System RAM block 3 Shut Down.
3
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM4SD
System RAM block 4 Shut Down.
4
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM5SD
System RAM block 5 Shut Down.
5
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM6SD
System RAM block 6 Shut Down.
6
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
USBFIFOSD
USB FIFO Shut Down.
11
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
LPPWEN
Low Power Peripheral Wakeup Enable Register.
0x34
read-write
n
0x0
0x0
SDMAWKEN
Smart DMA Wakeup Enable. This bit allows wakeup from the Smart DMA IRQ.
3
1
USBLSWKEN
USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set.
0
2
USBVBUSWKEN
USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.
2
1
LPPWST
Low Power Peripheral Wakeup Status Register.
0x30
read-write
n
0x0
0x0
BBMODEST
Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.
16
1
SDMAWKST
Smart DMA Detect Wakeup Flag (write one to clear). This bit will be set when the SDMA IRQ transition from low to high or on high to low.
3
1
USBLSWKST
USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN.
0
2
USBVBUSWKST
USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off.
2
1
LPWKEN0
Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.
0x8
read-write
n
0x0
0x0
WAKEEN
Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.
0
31
LPWKEN1
Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.
0x10
read-write
n
0x0
0x0
LPWKEN2
Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.
0x18
read-write
n
0x0
0x0
LPWKEN3
Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.
0x20
read-write
n
0x0
0x0
LPWKST0
Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.
0x4
read-write
n
0x0
0x0
WAKEST
Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.
0
1
LPWKST1
Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.
0xC
read-write
n
0x0
0x0
LPWKST2
Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.
0x14
read-write
n
0x0
0x0
LPWKST3
Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.
0x1C
read-write
n
0x0
0x0
RTC
Real Time Clock and Alarm.
RTC
0x0
0x0
0x400
registers
n
RTC
RTC interrupt.
3
CTRL
RTC Control Register.
0x10
read-write
n
0x0
0x0
ADE
Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
1
1
dis
Disable.
0
en
Enable.
1
ALDF
Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
6
1
read-only
inactive
Not active
0
Pending
Active
1
ALSF
Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
7
1
read-only
inactive
Not active
0
Pending
Active
1
ASE
Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
2
1
dis
Disable.
0
en
Enable.
1
BUSY
RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.
3
1
read-only
idle
Idle.
0
busy
Busy.
1
FT
Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.
9
2
freq1Hz
1 Hz (Compensated).
0
freq512Hz
512 Hz (Compensated).
1
freq4KHz
4 KHz.
2
clkDiv8
RTC Input Clock / 8.
3
RDY
RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.
4
1
busy
Register has not updated.
0
ready
Ready.
1
RDYE
RTC Ready Interrupt Enable.
5
1
dis
Disable.
0
en
Enable.
1
RTCE
Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
SQE
Square Wave Output Enable.
8
1
inactive
Not active
0
Pending
Active
1
WE
Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.
15
1
inactive
Not active
0
Pending
Active
1
X32KMD
32KHz Oscillator Mode.
11
2
noiseImmuneMode
Always operate in Noise Immune Mode. Oscillator warm-up required.
0
quietMode
Always operate in Quiet Mode. No oscillator warm-up required.
1
quietInStopWithWarmup
Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.
2
quietInStopNoWarmup
Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit.
3
OSCCTRL
RTC Oscillator Control Register.
0x18
read-write
n
0x0
0x0
32KOUT
RTC 32kHz Square Wave Output
5
1
BYPASS
RTC Crystal Bypass
4
1
FLITER_EN
RTC Oscillator Filter Enable
0
1
HYST_EN
RTC Oscillator Hysteresis Buffer Enable
2
1
IBIAS_EN
RTC Oscillator Bias Current Enable
3
1
IBIAS_SEL
RTC Oscillator 4X Bias Current Select
1
1
2X
Selects 2X bias current for RTC oscillator
0
4X
Selects 4X bias current for RTC oscillator
1
RAS
Time-of-day Alarm.
0x8
read-write
n
0x0
0x0
RAS
Time-of-day Alarm.
0
20
RSSA
RTC sub-second alarm. This register contains the reload value for the sub-second alarm.
0xC
read-write
n
0x0
0x0
RSSA
This register contains the reload value for the sub-second alarm.
0
32
SEC
RTC Second Counter. This register contains the 32-bit second counter.
0x0
read-write
n
0x0
0x0
SSEC
RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.
0x4
read-write
n
0x0
0x0
RTSS
RTC Sub-second Counter.
0
8
TRIM
RTC Trim Register.
0x14
read-write
n
0x0
0x0
TRIM
RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.
0
8
VBATTMR
VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.
8
24
SDHC
SDHC/SDIO Controller
SDHC
0x0
0x0
0x1000
registers
n
SDHC
SDHC IRQ
66
ADMA_ADDR_0
ADMA System Address 0-31.
0x58
32
read-write
n
0x0
0x0
ADDR
ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).
0
32
ADMA_ADDR_1
ADMA System Address 32-63.
0x5C
32
read-write
n
0x0
0x0
ADDR
ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).
0
32
ADMA_ER
ADMA Error Status.
0x54
8
read-write
n
0x0
0x0
LEN_MISMATCH
ADMA Length Mismatch Error.
2
1
STATE
ADMA Error State.
0
2
ARG_1
Argument 1.
0x8
32
read-write
n
0x0
0x0
CMD
Command Argument 1.
0
32
AUTO_CMD_ER
Auto CMD Error Status.
0x3C
16
read-write
n
0x0
0x0
CRC
Auto CMD CRC Error.
2
1
END_BIT
Auto CMD End Bit Error.
3
1
INDEX
Auto CMD Index Error.
4
1
NOT_EXCUTED
Auto CMD12 Not Executed.
0
1
NOT_ISSUED
Command Not Issued By Auto CMD12 Error.
7
1
TO
Auto CMD Timeout Error.
1
1
BLK_CNT
Block Count.
0x6
16
read-write
n
0x0
0x0
COUNT
Blocks Count For Current Transfer.
0
16
BLK_GAP
Block Gap Control.
0x2A
8
read-write
n
0x0
0x0
CONT
Continue Request.
1
1
INTR
Interrupt At Block Gap.
3
1
READ_WAIT
Read Wait Control.
2
1
STOP
Stop At Block Gap Request.
0
1
BLK_SIZE
Block Size.
0x4
16
read-write
n
0x0
0x0
HOST_BUFF
Host SDMA Buffer Boundary.
12
3
TRANS
Transfer Block Size.
0
12
BUFFER
Buffer Data Port.
0x20
32
read-write
n
0x0
0x0
DATA
Buffer Data.
0
32
CFG_0
Capabilities 0-31.
0x40
32
read-only
n
0x0
0x0
ADMA2
ADMA2 Support.
19
1
read-only
ASYNC_INT
Asynchronous Interrupt Support.
29
1
read-only
BIT_64_SYS_BUS
64-bit System Bus Support.
28
1
read-only
BIT_8
8-bit Support for Embedded Device.
18
1
read-only
CLK_FREQ
Base Clock Frequency For SD Clock.
8
8
read-only
HS
High Speed Support.
21
1
read-only
MAX_BLK_LEN
Max Block Length.
16
2
read-only
SDMA
SDMA Support.
22
1
read-only
SLOT_TYPE
Slot Type.
30
2
read-only
SUSPEND
Suspend/Resume Support.
23
1
read-only
TO_CLK_FREQ
Timeout Clock Frequency.
0
6
read-only
TO_CLK_UNIT
Timeout Clock Unit.
7
1
read-only
V1_8
Voltage Support 1.8V.
26
1
read-only
V3_0
Voltage Support 3.0V.
25
1
read-only
V3_3
Voltage Support 3.3V.
24
1
read-only
CFG_1
Capabilities 32-63.
0x44
32
read-only
n
0x0
0x0
CLK_MULTI
Clock Multiplier.
16
8
read-only
DDR50
DDR50 Support.
2
1
read-only
DRIVER_A
Driver Type A Support.
4
1
read-only
DRIVER_C
Driver Type C Support.
5
1
read-only
DRIVER_D
Driver Type D Support.
6
1
read-only
RETUNING
Re-Tuning Modes.
14
2
read-only
SDR104
SDR104 Support.
1
read-only
SDR50
SDR50 Support.
0
1
read-only
TIMER_CNT_TUNING
Timer Count for Re-Tuning.
8
4
read-only
TUNING_SDR50
Use Tuning for SDR50.
13
1
read-only
CLK_CN
Clock Control.
0x2C
16
read-write
n
0x0
0x0
CLK_GEN_SEL
Clock Generator Select.
5
1
read-only
INTERNAL_CLK_EN
Internal Clock Enable.
0
1
INTERNAL_CLK_STABLE
Internal Clock Stable.
1
1
read-only
SDCLK_FREQ_SEL
SDCLK Frequency Select.
8
8
SD_CLK_EN
SD Clock Enable.
2
1
UPPER_SDCLK_FREQ_SEL
Upper Bits of SDCLK Frequency Select.
6
2
CMD
Command.
0xE
16
read-write
n
0x0
0x0
CRC_CHK_EN
Command CRC Check Enable.
3
1
DATA_PRES_SEL
Data Present Select.
5
1
IDX
Command Index.
8
6
IDX_CHK_EN
Command Index Check Enable.
4
1
RESP_TYPE
Response Type Select.
0
2
TYPE
Command Type.
6
2
ER_INT_EN
Error Interrupt Status Enable.
0x36
16
read-write
n
0x0
0x0
ADMA
ADMA Error Status Enable.
9
1
AUTO_CMD
Auto CMD Error Status Enable.
8
1
CMD_CRC
Command CRC Error Status Enable.
1
1
CMD_END_BIT
Command End Bit Error Status Enable.
2
1
CMD_IDX
Command Index Error Status Enable.
3
1
CMD_TO
Command Timeout Error Status Enable.
0
1
DATA_CRC
Data CRC Error Status Enable.
5
1
DATA_END_BIT
Data End Bit Error Status Enable.
6
1
DATA_TO
Data Timeout Error Status Enable.
4
1
TUNING
Tuning Error Status Enable.
10
1
VENDOR
Vendor Specific Error Status Enable.
12
1
ER_INT_SIGNAL
Error Interrupt Signal Enable.
0x3A
16
read-write
n
0x0
0x0
ADMA
ADMA Error Signal Enable.
9
1
AUTO_CMD
Auto CMD Error Signal Enable.
8
1
CMD_CRC
Command CRC Error Signal Enable.
1
1
CMD_END_BIT
Command End Bit Error Signal Enable.
2
1
CMD_IDX
Command Index Error Signal Enable.
3
1
CMD_TO
Command Timeout Error Signal Enable.
0
1
CURR_LIM
Current Limit Error Signal Enable.
7
1
DATA_CRC
Data CRC Error Signal Enable.
5
1
DATA_END_BIT
Data End Bit Error Signal Enable.
6
1
DATA_TO
Data Timeout Error Signal Enable.
4
1
TAR_RESP
Target Response Error Signal Enable.
12
1
TUNING
Tuning Error Signal Enable.
10
1
ER_INT_STAT
Error Interrupt Status.
0x32
16
read-write
n
0x0
0x0
ADMA
ADMA Error.
9
1
AUTO_CMD_12
Auto CMD Error.
8
1
CMD_CRC
Command CRC Error.
1
1
CMD_END_BIT
Command End Bit Error.
2
1
CMD_IDX
Command Index Error.
3
1
CMD_TO
Command Timeout Error.
0
1
CURRENT_LIMIT
Current Limit Error.
7
1
DATA_CRC
Data CRC Error.
5
1
DATA_END_BIT
Data End Bit Error.
6
1
DATA_TO
Data Timeout Error.
4
1
DMA
DMA Error.
12
1
FORCE_CMD
Force Event for Auto CMD Error Status.
0x50
16
write-only
n
0x0
0x0
CRC
Force Event for Auto CMD CRC Error.
2
1
write-only
END_BIT
Force Event for Auto CMD End Bit Error.
3
1
write-only
INDEX
Force Event for Auto CMD Index Error.
4
1
write-only
NOT_EXCU
Force Event for Auto CMD12 Not Executed.
0
1
write-only
NOT_ISSUED
Force Event for Command Not Issued By Auto CMD12 Error.
7
1
write-only
TO
Force Event for Auto CMD Timeout Error.
1
1
write-only
FORCE_EVENT_INT_STAT
Force Event for Error Interrupt Status.
0x52
16
read-write
n
0x0
0x0
ADMA
Force Event for ADMA Error.
9
1
AUTO_CMD
Force Event for Auto CMD Error.
8
1
read-only
CMD_CRC
Force Event for Command CRC Error.
1
1
read-only
CMD_END_BIT
Force Event for Command End Bit Error.
2
1
read-only
CMD_INDEX
Force Event for Command Index Error.
3
1
read-only
CMD_TO
Force Event for Command Timeout Error.
0
1
read-only
CURR_LIMIT
Force Event for Current Limit Error.
7
1
read-only
DATA_CRC
Force Event for Data CRC Error.
5
1
read-only
DATA_END_BIT
Force Event for Data End Bit Error.
6
1
read-only
DATA_TO
Force Event for Data Timeout Error.
4
1
read-only
VENDOR
Force Event for Vendor Specific Error Status.
12
3
write-only
HOST_CN_1
Host Control 1.
0x28
8
read-write
n
0x0
0x0
CARD_DETECT_SIGNAL
Card Detect Signal Selection.
7
1
CARD_DETECT_TEST
Card Detect Test Level.
6
1
DATA_TRANSFER_WIDTH
Data Transfer Width.
1
1
DMA_SELECT
DMA Select.
3
2
EXT_DATA_TRANSFER_WIDTH
Extended Data Transfer Width.
5
1
HS_EN
High Speed Enable.
2
1
LED_CN
LED Control.
0
1
HOST_CN_2
Host Control 2.
0x3E
16
read-write
n
0x0
0x0
ASYNCH_INT
Asynchronous Interrupt Enable.
14
1
DRIVER_STRENGTH
Driver Strength Select.
4
2
EXCUTE
Execute Tuning.
6
1
PRESET_VAL_EN
Preset Value Enable.
15
1
SAMPLING_CLK
Sampling Clock Select.
7
1
SIGNAL_V1_8
1.8V Signaling Enable.
3
1
UHS
UHS Mode Select.
0
2
HOST_CN_VER
Host Controller Version.
0xFE
16
read-write
n
0x0
0x0
SPEC_VER
Specification Version Number.
0
8
VEND_VER
Vendor Version Number.
8
8
INT_EN
Normal Interrupt Status Enable.
0x34
16
read-write
n
0x0
0x0
BLK_GAP
Block Gap Event Status Enable.
2
1
BUFFER_RD
Buffer Read Ready Status Enable.
5
1
BUFFER_WR
Buffer Write Ready Status Enable.
4
1
CARD_INSERT
Card Insertion Status Enable.
6
1
CARD_INT
Card Interrupt Status Enable.
8
1
CARD_REMOVAL
Card Removal Status Enable.
7
1
CMD_COMP
Command Complete Status Enable.
0
1
DMA
DMA Interrupt Status Enable.
3
1
RETUNING
Re-Tuning Event Status Enable.
12
1
TRANS_COMP
Transfer Complete Status Enable.
1
1
INT_SIGNAL
Normal Interrupt Signal Enable.
0x38
16
read-write
n
0x0
0x0
BLK_GAP
Block Gap Event Signal Enable.
2
1
BUFFER_RD
Buffer Read Ready Signal Enable.
5
1
BUFFER_WR
Buffer Write Ready Signal Enable.
4
1
CARD_INSERT
Card Insertion Signal Enable.
6
1
CARD_INT
Card Interrupt Signal Enable.
8
1
CARD_REMOVAL
Card Removal Signal Enable.
7
1
CMD_COMP
Command Complete Signal Enable.
0
1
DMA
DMA Interrupt Signal Enable.
3
1
RETUNING
Re-Tuning Event Signal Enable.
12
1
TRANS_COMP
Transfer Complete Signal Enable.
1
1
INT_STAT
Normal Interrupt Status.
0x30
16
read-write
n
0x0
0x0
BLK_GAP_EVENT
Block Gap Event.
2
1
BUFF_RD_READY
Buffer Read Ready.
5
1
BUFF_WR_READY
Buffer Write Ready.
4
1
CARD_INSERTION
Card Insertion.
6
1
CARD_INTR
Card Interrupt.
8
1
CARD_REMOVAL
Card Removal.
7
1
CMD_COMP
Command Complete.
0
1
DMA
DMA Interrupt.
3
1
ERR_INTR
Error Interrupt.
15
1
RETUNING
Re-Tuning Event.
12
1
TRANS_COMP
Transfer Complete.
1
1
MAX_CURR_CFG
Maximum Current Capabilities.
0x48
32
read-only
n
0x0
0x0
V1_8
Maximum Current for 1.8V.
16
8
read-only
V3_0
Maximum Current for 3.0V.
8
8
read-only
V3_3
Maximum Current for 3.3V.
0
8
read-only
PRESENT
Present State.
0x24
32
read-only
n
0x0
0x0
BUFFER_READ
Buffer Read Enable.
11
1
read-only
BUFFER_WRITE
Buffer Write Enable.
10
1
read-only
CARD_DETECT
Card Detect Pin Level.
18
1
read-only
CARD_INSERTED
Card Inserted.
16
1
read-only
CARD_STATE
Card State Stable.
17
1
read-only
CMD
Command Inhibit (CMD).
0
1
read-only
CMD_SIGNAL_LEVEL
CMD Line Signal Level.
24
1
DAT
Command Inhibit (DAT).
1
1
read-only
DAT_LINE_ACTIVE
DAT Line Active.
2
1
read-only
DAT_SIGNAL_LEVEL
DAT[3:0] Line Signal Level.
20
4
READ_TRANSFER
Read Transfer Active.
9
1
read-only
RETUNING
Re-Tuning Request.
3
1
read-only
WP
Write Protect Switch Pin Level.
19
1
read-only
WRITE_TRANSFER
Write Transfer Active.
8
1
read-only
PRESET_0
Preset Value for Initialization.
0x60
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PRESET_1
Preset Value for Default Speed.
0x62
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PRESET_2
Preset Value for High Speed.
0x64
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PRESET_3
Preset Value for SDR12.
0x66
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PRESET_4
Preset Value for SDR25.
0x68
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PRESET_5
Preset Value for SDR50.
0x6A
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PRESET_6
Preset Value for SDR104.
0x6C
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PRESET_7
Preset Value for DDR50.
0x6E
16
read-only
n
0x0
0x0
CLK_GEN
Clock Generator Select Value.
10
1
read-only
DRIVER_STRENGTH
Driver Strength Select Value.
14
2
read-only
SDCLK_FREQ
SDCLK Frequency Select Value.
0
10
read-only
PWR
Power Control.
0x29
8
read-write
n
0x0
0x0
BUS_POWER
SD Bus Power.
0
1
BUS_VOLT_SEL
SD Bus Voltage Select.
1
3
RESP0
Response 0 Register 0-15.
0x10
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
RESP1
Response 0 Register 0-15.
0x14
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
RESP2
Response 0 Register 0-15.
0x18
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
RESP3
Response 0 Register 0-15.
0x1C
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
RESP[0]
Response 0 Register 0-15.
0x20
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
RESP[1]
Response 0 Register 0-15.
0x34
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
RESP[2]
Response 0 Register 0-15.
0x4C
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
RESP[3]
Response 0 Register 0-15.
0x68
32
read-write
n
0x0
0x0
CMD_RESP
Command Response.
0
32
SDMA
SDMA System Address / Argument 2.
0x0
32
read-write
n
0x0
0x0
ADDR
SDMA System Address / Argument 2 of Auto CMD23.
0
32
SHARED_BUS
Shared Bus Control.
0xE0
32
read-write
n
0x0
0x0
SLOT_INT
Slot Interrupt Status.
0xFC
16
read-only
n
0x0
0x0
INT_SIGNALS
Interrupt Signal For Each Slot.
0
1
read-only
SW_RESET
Software Reset.
0x2F
8
read-write
n
0x0
0x0
RESET_ALL
Software Reset For All.
0
1
RESET_CMD
Software Reset For CMD Line.
1
1
RESET_DAT
Software Reset For DAT Line.
2
1
TO
Timeout Control.
0x2E
8
read-write
n
0x0
0x0
DATA_COUNT_VALUE
Data Timeout Counter Value.
0
3
TRANS
Transfer Mode.
0xC
16
read-write
n
0x0
0x0
AUTO_CMD_EN
Auto CMD Enable.
2
2
CMD
disable
None
0
cmd12
None
1
cmd23
None
2
BLK_CNT_EN
Block Count Enable.
1
1
count
disable
None
0
enable
None
1
DMA_EN
DMA Enable.
0
1
enable
non_dma_transfer
None
0
dma_transfer
None
1
MULTI
Multi / Single Block Select.
5
1
multi
disable
None
0
enable
None
1
READ_WRITE
Data Transfer Direction Select.
4
1
read
write
None
0
read
None
1
WAKEUP
Wakeup Control.
0x2B
8
read-write
n
0x0
0x0
CARD_INS
Wakeup Event Enable On SD Card Insertion.
1
1
CARD_INT
Wakeup Event Enable On Card Interrupt.
0
1
CARD_REM
Wakeup Event Enable On SD Card Removal.
2
1
SDMA
Smart DMA
SDMA
0x0
0x0
0x1000
registers
n
SmartDMA
Smart DMA interrupt.
60
A0
Q30E Accumulator 0.
0x20
read-only
n
0x0
0x0
A1
Q30E Accumulator 1.
0x24
read-only
n
0x0
0x0
A2
Q30E Accumulator 2.
0x28
read-only
n
0x0
0x0
A3
Q30E Accumulator 3.
0x2C
read-only
n
0x0
0x0
BP
Q30E Frame Pointer Base.
0x10
read-only
n
0x0
0x0
CTRL
Control Register.
0x94
read-write
n
0x0
0x0
EN
Enable SDMA.
0
1
dis
Disable SDMA.
0
en
Enable SDMA.
1
DP0
Q30E Data Pointer 0.
0x8
read-only
n
0x0
0x0
DP1
Q30E Data Pointer 1.
0xC
read-only
n
0x0
0x0
INT_IN_CTRL
Interrupt Input From CPU Control Register.
0xA0
read-write
n
0x0
0x0
INTSET
Set Interrupt Flag.
0
1
dis
Set interrupt Flag to 0.
0
set
Set Interrupt Flag to 1.
1
INT_IN_FLAG
Interrupt Input From CPU Flag.
0xA4
read-write
n
0x0
0x0
INTFLAG
Interrupt Flag.
0
1
no_eff
No Effect.
0
clear
INT_IN_FLAG =0
1
INT_IN_IE
Interrupt Input From CPU Enable.
0xA8
read-write
n
0x0
0x0
INT_IN_EN
Interrupt Enable.
0
1
INT_MUX_CTRL0
Interrupt Mux Control 0.
0x80
read-write
n
0x0
0x0
INTSEL16
Interrupt Selection For 16th Interrupt.
0
8
INTSEL17
Interrupt Selection For 17th Interrupt.
8
8
INTSEL18
Interrupt Selection For 18th Interrupt.
16
8
INTSEL19
Interrupt Selection For 19th Interrupt.
24
8
INT_MUX_CTRL1
Interrupt Mux Control 1.
0x84
read-write
n
0x0
0x0
INTSEL20
Interrupt Selection For 20th Interrupt.
0
8
INTSEL21
Interrupt Selection For 21st Interrupt.
8
8
INTSEL22
Interrupt Selection For 22nd Interrupt.
16
8
INTSEL23
Interrupt Selection For 23rd Interrupt.
24
8
INT_MUX_CTRL2
Interrupt Mux Control 2.
0x88
read-write
n
0x0
0x0
INTSEL24
Interrupt Selection For 24th Interrupt.
0
8
INTSEL25
Interrupt Selection For 25th Interrupt.
8
8
INTSEL26
Interrupt Selection For 26th Interrupt.
16
8
INTSEL27
Interrupt Selection For 27th Interrupt.
24
8
INT_MUX_CTRL3
Interrupt Mux Control 3.
0x8C
read-write
n
0x0
0x0
INTSEL28
Interrupt Selection For 28th Interrupt.
0
8
INTSEL29
Interrupt Selection For 29th Interrupt.
8
8
INTSEL30
Interrupt Selection For 30th Interrupt.
16
8
INTSEL31
Interrupt Selection For 31st Interrupt.
24
8
IP
Q30E Instruction Pointer.
0x0
read-only
n
0x0
0x0
IP_ADDR
Configurable starting IP address for Q30E.
0x90
read-write
n
0x0
0x0
START_IP_ADDR
Starting IP address for Q30E
0
32
IRQ_FLAG
Interrupt Output To CPU Flag.
0xB0
read-write
n
0x0
0x0
IRQ_FLAG
Interrupt Flag.
0
1
IRQ_IE
Interrupt Output To CPU Control Register.
0xB4
read-write
n
0x0
0x0
IRQ_EN
Interrupt Enable.
0
1
LC0
Q30E Loop Counter 0.
0x18
read-only
n
0x0
0x0
LC1
Q30E Loop Counter 1.
0x1C
read-only
n
0x0
0x0
OFFS
Q30E Frame Pointer Offset.
0x14
read-only
n
0x0
0x0
SP
Q30E Stack Pointer.
0x4
read-only
n
0x0
0x0
WDCN
Q30E Watchdog Control.
0x30
read-only
n
0x0
0x0
SEMA
The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.
SEMA
0x0
0x0
0x1000
registers
n
SEMAPHORES0
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x0
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES1
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x4
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES2
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x8
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES3
Read to test and set, returns prior value. Write 0 to clear semaphore.
0xC
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES4
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x10
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES5
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x14
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES6
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x18
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES7
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x1C
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[0]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x0
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[1]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x4
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[2]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0xC
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[3]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x18
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[4]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x28
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[5]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x3C
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[6]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x54
32
read-write
n
0x0
0x0
sema
0
1
SEMAPHORES[7]
Read to test and set, returns prior value. Write 0 to clear semaphore.
0x70
32
read-write
n
0x0
0x0
sema
0
1
status
Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken.
0x100
32
read-write
n
0x0
0x0
STATUS
0
8
SIR
System Initialization Registers.
SIR
0x0
0x0
0x400
registers
n
ERRADDR
Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).
0x4
read-only
n
0x0
0x0
ERRADDR
0
32
FSTAT
funcstat register.
0x100
read-only
n
0x0
0x0
ADC
10-bit Sigma Delta ADC.
2
1
no
None
0
yes
None
1
FPU
FPU Function.
0
1
no
None
0
yes
None
1
HBC
HBC function.
5
1
no
None
0
yes
None
1
PBM
PBM function.
4
1
no
None
0
yes
None
1
SCACHE
System Cache function.
8
1
no
None
0
yes
None
1
SDHC
SDHC function.
6
1
no
None
0
yes
None
1
SMPHR
SMPHR function.
7
1
no
None
0
yes
None
1
USB
USB Device.
1
1
no
None
0
yes
None
1
XIP
XiP function.
3
1
no
None
0
yes
None
1
SFSTAT
secfuncstat register.
0x104
read-only
n
0x0
0x0
AES
AES function.
3
1
no
None
0
yes
None
1
MAA
MAA function.
5
1
no
None
0
yes
None
1
SHA
SHA function.
4
1
no
None
0
yes
None
1
TRNG
TRNG function.
2
1
no
None
0
yes
None
1
SISTAT
System Initialization Status Register.
0x0
read-only
n
0x0
0x0
CRCERR
CRC Error Status. This bit is set by the system initialization block following power-up.
1
1
read-only
read
noError
No CRC errors occurred during the read of the OTP memory block.
0
error
A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.
1
MAGIC
Magic Word Validation. This bit is set by the system initialization block following power-up.
0
1
read-only
read
magicNotSet
Magic word was not set (OTP has not been initialized properly).
0
magicSet
Magic word was set (OTP contains valid settings).
1
SMON
The Security Monitor block used to monitor system threat conditions.
SMON
0x0
0x0
0x1000
registers
n
DLRTC
DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred.
0x10
read-only
n
0x0
0x0
DLRTC
DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured.
0
32
EXTSCN
External Sensor Control Register.
0x0
read-only
n
0x0
0x0
BUSY
Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.
30
1
read-only
idle
Idle.
0
busy
Update in Progress.
1
DIVCLK
Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.
24
3
div1
Divide by 1 (8000 Hz).
0
div2
Divide by 2 (4000 Hz).
1
div4
Divide by 4 (2000 Hz).
2
div8
Divide by 8 (1000 Hz).
3
div16
Divide by 16 (500 Hz).
4
div32
Divide by 32 (250 Hz).
5
div64
Divide by 64 (125 Hz).
6
EXTCNT
External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.
16
5
EXTFRQ
External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.
21
3
freq2000Hz
Div 4 (2000Hz).
0
freq1000Hz
Div 8 (1000Hz).
1
freq500Hz
Div 16 (500Hz).
2
freq250Hz
Div 32 (250Hz).
3
freq125Hz
Div 64 (125Hz).
4
freq63Hz
Div 128 (63Hz).
5
freq31Hz
Div 256 (31Hz).
6
RFU
Reserved. Do not use.
7
EXTS_EN0
External Sensor Enable for input/output pair 0.
0
1
dis
Disable.
0
en
Enable.
1
EXTS_EN1
External Sensor Enable for input/output pair 1.
1
1
dis
Disable.
0
en
Enable.
1
EXTS_EN2
External Sensor Enable for input/output pair 2.
2
1
dis
Disable.
0
en
Enable.
1
EXTS_EN3
External Sensor Enable for input/output pair 3.
3
1
dis
Disable.
0
en
Enable.
1
EXTS_EN4
External Sensor Enable for input/output pair 4.
4
1
dis
Disable.
0
en
Enable.
1
EXTS_EN5
External Sensor Enable for input/output pair 5.
5
1
dis
Disable.
0
en
Enable.
1
LOCK
Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.
31
1
unlocked
Unlocked.
0
locked
Locked.
1
INTSCN
Internal Sensor Control Register.
0x4
read-only
n
0x0
0x0
LOCK
Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.
31
1
unlocked
Unlocked.
0
locked
Locked.
1
LOTEMP_SEL
Low Temperature Detection Select.
16
1
neg50C
-50 degrees C.
0
neg30C
-30 degrees C.
1
SHIELD_EN
Die Shield Enable.
0
1
dis
Disable.
0
en
Enable.
1
TEMP_EN
Temperature Sensor Enable.
1
1
dis
Disable.
0
en
Enable.
1
VBAT_EN
Battery Monitor Enable.
2
1
dis
Disable.
0
en
Enable.
1
VCOREHIEN
VCORE Overvoltage Detect Enable.
19
1
dis
Disable.
0
en
Enable.
1
VCORELOEN
VCORE Undervoltage Detect Enable.
18
1
dis
Disable.
0
en
Enable.
1
VDDHIEN
VDD Overvoltage Detect Enable.
21
1
dis
Disable.
0
en
Enable.
1
VDDLOEN
VDD Undervoltage Detect Enable.
20
1
dis
Disable.
0
en
Enable.
1
VGLEN
Voltage Glitch Detection Enable.
22
1
dis
Disable.
0
en
Enable.
1
SECALM
Security Alarm Register.
0x8
read-only
n
0x0
0x0
BATHI
Battery Overvoltage Detect.
6
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
BATLO
Battery Undervoltage Detect.
5
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
DRS
Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.
0
1
complete
No operation/complete.
0
start
Start operation.
1
EXTF
External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.
7
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT0
External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
16
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT1
External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
17
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT2
External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
18
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT3
External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
19
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT4
External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
20
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT5
External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
21
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSWARN0
External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
24
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSWARN1
External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
25
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSWARN2
External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
26
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSWARN3
External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
27
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSWARN4
External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
28
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSWARN5
External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
29
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
HITEMP
High Temperature Detect.
4
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
KEYWIPE
Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.
1
1
complete
No operation/complete.
0
start
Start operation.
1
LOTEMP
Low Temperature Detect.
3
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
SHIELDF
Die Shield Flag.
2
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
VCOREHI
VCORE Overvoltage Detect Flag.
10
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
VCORELO
VCORE Undervoltage Detect Flag.
9
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
VDDHI
VDD Overvoltage Flag.
11
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
VDDLO
VDD Undervoltage Detect Flag.
8
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
VGL
Voltage Glitch Detection Flag.
12
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
SECDIAG
Security Diagnostic Register.
0xC
read-only
n
0x0
0x0
AESKT
AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.
8
1
incomplete
Key has not been transferred.
0
complete
Key has been transferred.
1
BATHI
Battery Overvoltage Detect.
6
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
BATLO
Battery Undervoltage Detect.
5
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
BORF
Battery-On-Reset Flag. This bit is set once the back up battery is conneted.
0
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
DYNF
Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.
7
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT0
External Sensor 0 Detect.
16
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT1
External Sensor 1 Detect.
17
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT2
External Sensor 2 Detect.
18
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT3
External Sensor 3 Detect.
19
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT4
External Sensor 4 Detect.
20
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
EXTSTAT5
External Sensor 5 Detect.
21
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
HITEMP
High Temperature Detect.
4
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
LOTEMP
Low Temperature Detect.
3
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
SHIELDF
Die Shield Flag.
2
1
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
SECST
Security Monitor Status Register.
0x34
read-only
n
0x0
0x0
EXTSRS
External Sensor Control Register Status.
0
1
allowed
Access authorized.
0
notAllowed
Access not authorized.
1
INTSRS
Internal Sensor Control Register Status.
1
1
allowed
Access authorized.
0
notAllowed
Access not authorized.
1
SECALRS
Security Alarm Register Status.
2
1
allowed
Access authorized.
0
notAllowed
Access not authorized.
1
SPI17Y
SPI peripheral.
SPI17Y
0x0
0x0
0x1000
registers
n
SPI0
SPI0 IRQ
16
CLK_CFG
Register for controlling SPI clock rate.
0x14
read-write
n
0x0
0x0
HI
High duty cycle control. In timer mode, reload[15:8].
8
8
Dis
Duty cycle control of serial clock generation is disabled.
0
LO
Low duty cycle control. In timer mode, reload[7:0].
0
8
Dis
Duty cycle control of serial clock generation is disabled.
0
SCALE
System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
16
4
CTRL0
Register for controlling SPI peripheral.
0x4
read-write
n
0x0
0x0
EN
SPI Enable.
0
1
dis
SPI is disabled.
0
en
SPI is enabled.
1
MASTER
Master Mode Enable.
1
1
dis
SPI is Slave mode.
0
en
SPI is Master mode.
1
SS
Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
16
4
SS0
SS0 is selected.
0x1
SS1
SS1 is selected.
0x2
SS2
SS2 is selected.
0x4
SS3
SS3 is selected.
0x8
SS_CTRL
Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.
8
1
DEASSERT
SPI De-asserts Slave Select at the end of a transaction.
0
ASSERT
SPI leaves Slave Select asserted at the end of a transaction.
1
SS_IO
Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
4
1
output
Slave select 0 is output.
0
input
Slave Select 0 is input, only valid if MMEN=1.
1
START
Start Transmit.
5
1
start
Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
1
CTRL1
Register for controlling SPI peripheral.
0x8
read-write
n
0x0
0x0
RX_NUM_CHAR
Nubmer of Characters to receive.
16
16
TX_NUM_CHAR
Nubmer of Characters to transmit.
0
16
CTRL2
Register for controlling SPI peripheral.
0xC
read-write
n
0x0
0x0
CPHA
Clock Phase.
0
1
Rising_Edge
Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2
0
Falling_Edge
Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
1
CPOL
Clock Polarity.
1
1
Normal
Normal Clock. Use when in SPI Mode 0 and Mode 1
0
Inverted
Inverted Clock. Use when in SPI Mode 2 and Mode 3
1
DATA_WIDTH
SPI Data width.
12
2
Mono
1 data pin.
0
Dual
2 data pins.
1
Quad
4 data pins.
2
NUMBITS
Number of Bits per character.
8
4
0
16 bits per character.
0
SCLK_INV
Reserved - Must Always Be Cleared to 0.
4
1
SRPOL
Slave Ready Polarity, each Slave Ready can have unique polarity.
24
8
SR0_high
SR0 active high.
0x1
SR4_high
SR4 active high.
0x10
SR1_high
SR1 active high.
0x2
SR5_high
SR5 active high.
0x20
SR2_high
SR2 active high.
0x4
SR6_high
SR6 active high.
0x40
SR3_high
SR3 active high.
0x8
SR7_high
SR7 active high.
0x80
SS_POL
Slave Select Polarity, each Slave Select can have unique polarity.
16
8
SS0_high
SS0 active high.
0x1
SS1_high
SS1 active high.
0x2
SS2_high
SS2 active high.
0x4
SS3_high
SS3 active high.
0x8
THREE_WIRE
Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.
15
1
dis
Use four wire mode (Mono only).
0
en
Use three wire mode.
1
DATA160
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA161
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[0]
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[1]
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA32
Register for reading and writing the FIFO.
0x0
32
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
32
DATA80
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA81
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA82
Register for reading and writing the FIFO.
DATA32
0x2
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA83
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[0]
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[1]
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[2]
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[3]
Register for reading and writing the FIFO.
DATA32
0x6
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DMA
Register for controlling DMA.
0x1C
read-write
n
0x0
0x0
RX_DMA_EN
RX DMA Enable.
31
1
dis
RX DMA requests are disabled, any pending DMA requests are cleared.
0
en
RX DMA requests are enabled.
1
RX_FIFO_CLEAR
Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
23
1
CLEAR
Clear the Receive FIFO, clears any pending RX FIFO status.
1
RX_FIFO_CNT
Count of entries in RX FIFO.
24
6
read-only
RX_FIFO_EN
Receive FIFO enabled for SPI transactions.
22
1
DIS
Receive FIFO is not enabled.
0
en
Receive FIFO is enabled.
1
RX_FIFO_LEVEL
Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
16
5
TX_DMA_EN
TX DMA Enable.
15
1
DIS
TX DMA requests are disabled, andy pending DMA requests are cleared.
0
en
TX DMA requests are enabled.
1
TX_FIFO_CLEAR
Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. .
7
1
CLEAR
Clear the Transmit FIFO, clears any pending TX FIFO status.
1
TX_FIFO_CNT
Count of entries in TX FIFO.
8
6
read-only
TX_FIFO_EN
Transmit FIFO enabled for SPI transactions.
6
1
dis
Transmit FIFO is not enabled.
0
en
Transmit FIFO is enabled.
1
TX_FIFO_LEVEL
Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
0
5
INT_EN
Register for enabling interrupts.
0x24
read-write
n
0x0
0x0
ABORT
Slave Abort Detected interrupt enable.
9
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
FAULT
Multi-Master Mode Fault interrupt enable.
8
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
M_DONE
Master Done interrupt enable.
11
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_FULL
RX FIFO FULL interrupt enable.
3
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_OVR
Receive FIFO Overrun interrupt enable.
14
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_THRESH
RX FIFO Threshold Crossed interrupt enable.
2
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_UND
Receive FIFO Underrun interrupt enable.
15
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSA
Slave Select Asserted interrupt enable.
4
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSD
Slave Select Deasserted interrupt enable.
5
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_EMPTY
TX FIFO Empty interrupt enable.
1
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_OVR
Transmit FIFO Overrun interrupt enable.
12
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_THRESH
TX FIFO Threshold interrupt enable.
0
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_UND
Transmit FIFO Underrun interrupt enable.
13
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
INT_FL
Register for reading and clearing interrupt flags. All bits are write 1 to clear.
0x20
read-write
n
0x0
0x0
ABORT
Slave Abort Detected.
9
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
FAULT
Multi-Master Mode Fault.
8
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
M_DONE
Master Done, set when SPI Master has completed any transactions.
11
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_FULL
RX FIFO FULL.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_OVR
Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
14
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_UND
Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
15
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSA
Slave Select Asserted.
4
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSD
Slave Select Deasserted.
5
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_OVR
Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
12
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_UND
Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
13
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SS_TIME
Register for controlling SPI peripheral/Slave Select Timing.
0x10
read-write
n
0x0
0x0
INACT
Slave Select Inactive delay.
16
8
256
256 system clocks between transactions.
0
POST
Slave Select Post delay 2.
8
8
256
256 system clocks between last serial clock edge and SS inactive.
0
PRE
Slave Select Pre delay 1.
0
8
256
256 system clocks between SS active and first serial clock edge.
0
STAT
SPI Status register.
0x30
read-only
n
0x0
0x0
BUSY
SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.
0
1
not
SPI not active.
0
active
SPI active.
1
WAKE_EN
Register for wake up enable.
0x2C
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full Enable.
3
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed Enable.
2
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_EMPTY
Wake on TX FIFO Empty Enable.
1
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed Enable.
0
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
WAKE_FL
Register for wake up flags. All bits in this register are write 1 to clear.
0x28
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
Wake on TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SPI17Y1
SPI peripheral. 1
SPI17Y
0x0
0x0
0x1000
registers
n
SPI17Y1
SPI17Y1 IRQ
17
CLK_CFG
Register for controlling SPI clock rate.
0x14
read-write
n
0x0
0x0
HI
High duty cycle control. In timer mode, reload[15:8].
8
8
Dis
Duty cycle control of serial clock generation is disabled.
0
LO
Low duty cycle control. In timer mode, reload[7:0].
0
8
Dis
Duty cycle control of serial clock generation is disabled.
0
SCALE
System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
16
4
CTRL0
Register for controlling SPI peripheral.
0x4
read-write
n
0x0
0x0
EN
SPI Enable.
0
1
dis
SPI is disabled.
0
en
SPI is enabled.
1
MASTER
Master Mode Enable.
1
1
dis
SPI is Slave mode.
0
en
SPI is Master mode.
1
SS
Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
16
4
SS0
SS0 is selected.
0x1
SS1
SS1 is selected.
0x2
SS2
SS2 is selected.
0x4
SS3
SS3 is selected.
0x8
SS_CTRL
Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.
8
1
DEASSERT
SPI De-asserts Slave Select at the end of a transaction.
0
ASSERT
SPI leaves Slave Select asserted at the end of a transaction.
1
SS_IO
Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
4
1
output
Slave select 0 is output.
0
input
Slave Select 0 is input, only valid if MMEN=1.
1
START
Start Transmit.
5
1
start
Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
1
CTRL1
Register for controlling SPI peripheral.
0x8
read-write
n
0x0
0x0
RX_NUM_CHAR
Nubmer of Characters to receive.
16
16
TX_NUM_CHAR
Nubmer of Characters to transmit.
0
16
CTRL2
Register for controlling SPI peripheral.
0xC
read-write
n
0x0
0x0
CPHA
Clock Phase.
0
1
Rising_Edge
Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2
0
Falling_Edge
Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
1
CPOL
Clock Polarity.
1
1
Normal
Normal Clock. Use when in SPI Mode 0 and Mode 1
0
Inverted
Inverted Clock. Use when in SPI Mode 2 and Mode 3
1
DATA_WIDTH
SPI Data width.
12
2
Mono
1 data pin.
0
Dual
2 data pins.
1
Quad
4 data pins.
2
NUMBITS
Number of Bits per character.
8
4
0
16 bits per character.
0
SCLK_INV
Reserved - Must Always Be Cleared to 0.
4
1
SRPOL
Slave Ready Polarity, each Slave Ready can have unique polarity.
24
8
SR0_high
SR0 active high.
0x1
SR4_high
SR4 active high.
0x10
SR1_high
SR1 active high.
0x2
SR5_high
SR5 active high.
0x20
SR2_high
SR2 active high.
0x4
SR6_high
SR6 active high.
0x40
SR3_high
SR3 active high.
0x8
SR7_high
SR7 active high.
0x80
SS_POL
Slave Select Polarity, each Slave Select can have unique polarity.
16
8
SS0_high
SS0 active high.
0x1
SS1_high
SS1 active high.
0x2
SS2_high
SS2 active high.
0x4
SS3_high
SS3 active high.
0x8
THREE_WIRE
Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.
15
1
dis
Use four wire mode (Mono only).
0
en
Use three wire mode.
1
DATA160
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA161
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[0]
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[1]
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA32
Register for reading and writing the FIFO.
0x0
32
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
32
DATA80
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA81
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA82
Register for reading and writing the FIFO.
DATA32
0x2
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA83
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[0]
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[1]
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[2]
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[3]
Register for reading and writing the FIFO.
DATA32
0x6
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DMA
Register for controlling DMA.
0x1C
read-write
n
0x0
0x0
RX_DMA_EN
RX DMA Enable.
31
1
dis
RX DMA requests are disabled, any pending DMA requests are cleared.
0
en
RX DMA requests are enabled.
1
RX_FIFO_CLEAR
Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
23
1
CLEAR
Clear the Receive FIFO, clears any pending RX FIFO status.
1
RX_FIFO_CNT
Count of entries in RX FIFO.
24
6
read-only
RX_FIFO_EN
Receive FIFO enabled for SPI transactions.
22
1
DIS
Receive FIFO is not enabled.
0
en
Receive FIFO is enabled.
1
RX_FIFO_LEVEL
Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
16
5
TX_DMA_EN
TX DMA Enable.
15
1
DIS
TX DMA requests are disabled, andy pending DMA requests are cleared.
0
en
TX DMA requests are enabled.
1
TX_FIFO_CLEAR
Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. .
7
1
CLEAR
Clear the Transmit FIFO, clears any pending TX FIFO status.
1
TX_FIFO_CNT
Count of entries in TX FIFO.
8
6
read-only
TX_FIFO_EN
Transmit FIFO enabled for SPI transactions.
6
1
dis
Transmit FIFO is not enabled.
0
en
Transmit FIFO is enabled.
1
TX_FIFO_LEVEL
Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
0
5
INT_EN
Register for enabling interrupts.
0x24
read-write
n
0x0
0x0
ABORT
Slave Abort Detected interrupt enable.
9
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
FAULT
Multi-Master Mode Fault interrupt enable.
8
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
M_DONE
Master Done interrupt enable.
11
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_FULL
RX FIFO FULL interrupt enable.
3
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_OVR
Receive FIFO Overrun interrupt enable.
14
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_THRESH
RX FIFO Threshold Crossed interrupt enable.
2
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_UND
Receive FIFO Underrun interrupt enable.
15
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSA
Slave Select Asserted interrupt enable.
4
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSD
Slave Select Deasserted interrupt enable.
5
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_EMPTY
TX FIFO Empty interrupt enable.
1
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_OVR
Transmit FIFO Overrun interrupt enable.
12
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_THRESH
TX FIFO Threshold interrupt enable.
0
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_UND
Transmit FIFO Underrun interrupt enable.
13
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
INT_FL
Register for reading and clearing interrupt flags. All bits are write 1 to clear.
0x20
read-write
n
0x0
0x0
ABORT
Slave Abort Detected.
9
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
FAULT
Multi-Master Mode Fault.
8
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
M_DONE
Master Done, set when SPI Master has completed any transactions.
11
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_FULL
RX FIFO FULL.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_OVR
Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
14
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_UND
Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
15
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSA
Slave Select Asserted.
4
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSD
Slave Select Deasserted.
5
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_OVR
Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
12
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_UND
Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
13
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SS_TIME
Register for controlling SPI peripheral/Slave Select Timing.
0x10
read-write
n
0x0
0x0
INACT
Slave Select Inactive delay.
16
8
256
256 system clocks between transactions.
0
POST
Slave Select Post delay 2.
8
8
256
256 system clocks between last serial clock edge and SS inactive.
0
PRE
Slave Select Pre delay 1.
0
8
256
256 system clocks between SS active and first serial clock edge.
0
STAT
SPI Status register.
0x30
read-only
n
0x0
0x0
BUSY
SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.
0
1
not
SPI not active.
0
active
SPI active.
1
WAKE_EN
Register for wake up enable.
0x2C
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full Enable.
3
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed Enable.
2
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_EMPTY
Wake on TX FIFO Empty Enable.
1
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed Enable.
0
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
WAKE_FL
Register for wake up flags. All bits in this register are write 1 to clear.
0x28
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
Wake on TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SPI17Y2
SPI peripheral. 2
SPI17Y
0x0
0x0
0x1000
registers
n
SPI17Y2
SPI17Y2 IRQ
18
CLK_CFG
Register for controlling SPI clock rate.
0x14
read-write
n
0x0
0x0
HI
High duty cycle control. In timer mode, reload[15:8].
8
8
Dis
Duty cycle control of serial clock generation is disabled.
0
LO
Low duty cycle control. In timer mode, reload[7:0].
0
8
Dis
Duty cycle control of serial clock generation is disabled.
0
SCALE
System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
16
4
CTRL0
Register for controlling SPI peripheral.
0x4
read-write
n
0x0
0x0
EN
SPI Enable.
0
1
dis
SPI is disabled.
0
en
SPI is enabled.
1
MASTER
Master Mode Enable.
1
1
dis
SPI is Slave mode.
0
en
SPI is Master mode.
1
SS
Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
16
4
SS0
SS0 is selected.
0x1
SS1
SS1 is selected.
0x2
SS2
SS2 is selected.
0x4
SS3
SS3 is selected.
0x8
SS_CTRL
Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.
8
1
DEASSERT
SPI De-asserts Slave Select at the end of a transaction.
0
ASSERT
SPI leaves Slave Select asserted at the end of a transaction.
1
SS_IO
Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
4
1
output
Slave select 0 is output.
0
input
Slave Select 0 is input, only valid if MMEN=1.
1
START
Start Transmit.
5
1
start
Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
1
CTRL1
Register for controlling SPI peripheral.
0x8
read-write
n
0x0
0x0
RX_NUM_CHAR
Nubmer of Characters to receive.
16
16
TX_NUM_CHAR
Nubmer of Characters to transmit.
0
16
CTRL2
Register for controlling SPI peripheral.
0xC
read-write
n
0x0
0x0
CPHA
Clock Phase.
0
1
Rising_Edge
Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2
0
Falling_Edge
Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
1
CPOL
Clock Polarity.
1
1
Normal
Normal Clock. Use when in SPI Mode 0 and Mode 1
0
Inverted
Inverted Clock. Use when in SPI Mode 2 and Mode 3
1
DATA_WIDTH
SPI Data width.
12
2
Mono
1 data pin.
0
Dual
2 data pins.
1
Quad
4 data pins.
2
NUMBITS
Number of Bits per character.
8
4
0
16 bits per character.
0
SCLK_INV
Reserved - Must Always Be Cleared to 0.
4
1
SRPOL
Slave Ready Polarity, each Slave Ready can have unique polarity.
24
8
SR0_high
SR0 active high.
0x1
SR4_high
SR4 active high.
0x10
SR1_high
SR1 active high.
0x2
SR5_high
SR5 active high.
0x20
SR2_high
SR2 active high.
0x4
SR6_high
SR6 active high.
0x40
SR3_high
SR3 active high.
0x8
SR7_high
SR7 active high.
0x80
SS_POL
Slave Select Polarity, each Slave Select can have unique polarity.
16
8
SS0_high
SS0 active high.
0x1
SS1_high
SS1 active high.
0x2
SS2_high
SS2 active high.
0x4
SS3_high
SS3 active high.
0x8
THREE_WIRE
Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.
15
1
dis
Use four wire mode (Mono only).
0
en
Use three wire mode.
1
DATA160
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA161
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[0]
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[1]
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA32
Register for reading and writing the FIFO.
0x0
32
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
32
DATA80
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA81
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA82
Register for reading and writing the FIFO.
DATA32
0x2
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA83
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[0]
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[1]
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[2]
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[3]
Register for reading and writing the FIFO.
DATA32
0x6
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DMA
Register for controlling DMA.
0x1C
read-write
n
0x0
0x0
RX_DMA_EN
RX DMA Enable.
31
1
dis
RX DMA requests are disabled, any pending DMA requests are cleared.
0
en
RX DMA requests are enabled.
1
RX_FIFO_CLEAR
Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
23
1
CLEAR
Clear the Receive FIFO, clears any pending RX FIFO status.
1
RX_FIFO_CNT
Count of entries in RX FIFO.
24
6
read-only
RX_FIFO_EN
Receive FIFO enabled for SPI transactions.
22
1
DIS
Receive FIFO is not enabled.
0
en
Receive FIFO is enabled.
1
RX_FIFO_LEVEL
Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
16
5
TX_DMA_EN
TX DMA Enable.
15
1
DIS
TX DMA requests are disabled, andy pending DMA requests are cleared.
0
en
TX DMA requests are enabled.
1
TX_FIFO_CLEAR
Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. .
7
1
CLEAR
Clear the Transmit FIFO, clears any pending TX FIFO status.
1
TX_FIFO_CNT
Count of entries in TX FIFO.
8
6
read-only
TX_FIFO_EN
Transmit FIFO enabled for SPI transactions.
6
1
dis
Transmit FIFO is not enabled.
0
en
Transmit FIFO is enabled.
1
TX_FIFO_LEVEL
Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
0
5
INT_EN
Register for enabling interrupts.
0x24
read-write
n
0x0
0x0
ABORT
Slave Abort Detected interrupt enable.
9
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
FAULT
Multi-Master Mode Fault interrupt enable.
8
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
M_DONE
Master Done interrupt enable.
11
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_FULL
RX FIFO FULL interrupt enable.
3
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_OVR
Receive FIFO Overrun interrupt enable.
14
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_THRESH
RX FIFO Threshold Crossed interrupt enable.
2
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_UND
Receive FIFO Underrun interrupt enable.
15
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSA
Slave Select Asserted interrupt enable.
4
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSD
Slave Select Deasserted interrupt enable.
5
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_EMPTY
TX FIFO Empty interrupt enable.
1
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_OVR
Transmit FIFO Overrun interrupt enable.
12
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_THRESH
TX FIFO Threshold interrupt enable.
0
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_UND
Transmit FIFO Underrun interrupt enable.
13
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
INT_FL
Register for reading and clearing interrupt flags. All bits are write 1 to clear.
0x20
read-write
n
0x0
0x0
ABORT
Slave Abort Detected.
9
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
FAULT
Multi-Master Mode Fault.
8
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
M_DONE
Master Done, set when SPI Master has completed any transactions.
11
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_FULL
RX FIFO FULL.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_OVR
Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
14
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_UND
Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
15
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSA
Slave Select Asserted.
4
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSD
Slave Select Deasserted.
5
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_OVR
Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
12
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_UND
Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
13
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SS_TIME
Register for controlling SPI peripheral/Slave Select Timing.
0x10
read-write
n
0x0
0x0
INACT
Slave Select Inactive delay.
16
8
256
256 system clocks between transactions.
0
POST
Slave Select Post delay 2.
8
8
256
256 system clocks between last serial clock edge and SS inactive.
0
PRE
Slave Select Pre delay 1.
0
8
256
256 system clocks between SS active and first serial clock edge.
0
STAT
SPI Status register.
0x30
read-only
n
0x0
0x0
BUSY
SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.
0
1
not
SPI not active.
0
active
SPI active.
1
WAKE_EN
Register for wake up enable.
0x2C
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full Enable.
3
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed Enable.
2
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_EMPTY
Wake on TX FIFO Empty Enable.
1
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed Enable.
0
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
WAKE_FL
Register for wake up flags. All bits in this register are write 1 to clear.
0x28
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
Wake on TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SPID
SPID peripheral.
SPID
0x0
0x0
0x1000
registers
n
BRG_CTRL
Register for controlling SPI clock rate.
0x14
read-write
n
0x0
0x0
HI
High duty cycle control. In timer mode, reload[15:8].
8
8
Dis
Duty cycle control of serial clock generation is disabled.
0
LOW
Low duty cycle control. In timer mode, reload[7:0].
0
8
Dis
Duty cycle control of serial clock generation is disabled.
0
SCALE
System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
16
4
ctrl1
Register for controlling SPI peripheral.
0x4
read-write
n
0x0
0x0
FL_EN
Flow Control Mode Enable.
3
1
dis
Flow Control mode is disabled.
0
en
Flow Control Mode is enabled.
1
MMEN
Master Mode Enable.
1
1
dis
SPI is Slave mode.
0
en
SPI is Master mode.
1
SPIEN
SPI Enable.
0
1
dis
SPI is disabled.
0
en
SPI is enabled.
1
SS
Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
16
8
SS0
SS0 is selected.
0x1
SS4
SS4 is selected.
0x10
SS1
SS1 is selected.
0x2
SS5
SS5 is selected.
0x20
SS2
SS2 is selected.
0x4
SS6
SS6 is selected.
0x40
SS3
SS3 is selected.
0x8
SS7
SS7 is selected.
0x80
SSIO
Slave Select 0, IO direction, to support Multi-Master mode, Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
4
1
output
Slave select 0 is output.
0
input
Slave Select 0 is input, only valid if MMEN=1.
1
SS_CTRL
Slave Select Control.
8
1
deassert
SPI de-asserts Slave Select at the end of a transaction.
0
assert
SPI leaves Slave Select asserted at the end of a transaction.
1
TIMER
Timer Enable.
2
1
dis
Timer is disabled.
0
en
Timer is enabled, only valid if SPIEN=0.
1
TX_START
Start Transmit.
5
1
start
Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction completes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
1
ctrl2
Register for controlling SPI peripheral.
0x8
read-write
n
0x0
0x0
RX_NUM_CHAR
Nubmer of Characters to receive.
16
16
TX_NUM_CHAR
Nubmer of Characters to transmit.
0
16
ctrl3
Register for controlling SPI peripheral.
0xC
read-write
n
0x0
0x0
CPHA
Clock Phase.
0
1
CPOL
Clock Polarity.
1
1
DATA_WIDTH
SPI Data width.
12
2
Mono
1 data pin.
0
Dual
2 data pins.
1
Quad
4 data pins.
2
NUMBITS
Number of Bits per character.
8
4
0
16 bits per character.
0
SCLK_FB_INV
Invert SCLK Feedback in Master Mode.
4
1
NON_INV
SCLK is not inverted to Line Receiver.
0
INV
SCLK is inverted to Line Receiver.
1
SRPOL
Slave Ready Polarity, each Slave Ready can have unique polarity.
24
8
SR0_high
SR0 active high.
0x1
SR4_high
SR4 active high.
0x10
SR1_high
SR1 active high.
0x2
SR5_high
SR5 active high.
0x20
SR2_high
SR2 active high.
0x4
SR6_high
SR6 active high.
0x40
SR3_high
SR3 active high.
0x8
SR7_high
SR7 active high.
0x80
SSPOL
Slave Select Polarity, each Slave Select can have unique polarity.
16
8
SS0_high
SS0 active high.
0x1
SS4_high
SS4 active high.
0x10
SS1_high
SS1 active high.
0x2
SS5_high
SS5 active high.
0x20
SS2_high
SS2 active high.
0x4
SS6_high
SS6 active high.
0x40
SS3_high
SS3 active high.
0x8
SS7_high
SS7 active high.
0x80
THREE_WIRE
Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.
15
1
dis
Use four wire mode (Mono only).
0
en
Use three wire mode.
1
ctrl4
Register for controlling SPI peripheral.
0x10
read-write
n
0x0
0x0
SSACT1
Slave Select Action delay 1.
0
8
256
256 system clocks between SS active and first serial clock edge.
0
SSACT2
Slave Select Action delay 2.
8
8
256
256 system clocks between last serial clock edge and SS inactive.
0
SSINACT
Slave Select Inactive delay.
16
8
256
256 system clocks between transactions.
0
DATA160
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA161
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[0]
Register for reading and writing the FIFO.
DATA32
0x0
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA16[1]
Register for reading and writing the FIFO.
DATA32
0x2
16
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
16
DATA32
Register for reading and writing the FIFO.
0x0
32
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
32
DATA80
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA81
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA82
Register for reading and writing the FIFO.
DATA32
0x2
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA83
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[0]
Register for reading and writing the FIFO.
DATA32
0x0
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[1]
Register for reading and writing the FIFO.
DATA32
0x1
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[2]
Register for reading and writing the FIFO.
DATA32
0x3
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DATA8[3]
Register for reading and writing the FIFO.
DATA32
0x6
8
read-write
n
0x0
0x0
DATA
Read to pull from RX FIFO, write to put into TX FIFO.
0
8
DMA
Register for controlling DMA.
0x1C
read-write
n
0x0
0x0
RX_DMA_EN
RX DMA Enable.
31
1
dis
RX DMA requests are disabled, any pending DMA requests are cleared.
0
en
RX DMA requests are enabled.
1
RX_FIFO_CLEAR
Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
23
1
CLEAR
Clear the Receive FIFIO, clears any pending RX FIFO status.
1
RX_FIFO_CNT
Count of entries in RX FIFO.
24
6
RX_FIFO_EN
Receive FIFO enabled for SPI transactions.
22
1
DIS
Receive FIFO is not enabled.
0
en
Receive FIFO is enabled.
1
RX_FIFO_LEVEL
Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
16
6
TX_DMA_EN
TX DMA Enable.
15
1
DIS
TX DMA requests are disabled, andy pending DMA requests are cleared.
0
en
TX DMA requests are enabled.
1
TX_FIFO_CLEAR
Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
7
1
CLEAR
Clear the Transmit FIFO, clears any pending TX FIFO status.
1
TX_FIFO_CNT
Count of entries in TX FIFO.
8
5
TX_FIFO_EN
Transmit FIFO enabled for SPI transactions.
6
1
dis
Transmit FIFO is not enabled.
0
en
Transmit FIFO is enabled.
1
TX_FIFO_LEVEL
Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
0
6
I2S_CTRL
Register for controlling I2C mode.
0x18
read-write
n
0x0
0x0
I2S_EN
Low duty cycle control. In timer mode, reload[7:0].
0
1
dis
I2C mode is disabled.
0
en
I2C mode is enabled.
1
I2S_LJ
I2S Left Justify.
4
1
dis
Normal I 2 S audio protocol, audio data lags left/right channel signal by one SCLK period.
0
en
Audio data is synchronized with SSEL (left/right channel signal).
1
I2S_MONO
I2S Monotone.
3
1
dis
Stereophonic audio format.
0
en
Monophonic audio format. Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
1
I2S_MUTE
I2S Mute.
1
1
dis
Normal Transmit.
0
en
Transmit data is replaced with 0.
1
I2S_PAUSE
I2S Pause.
2
1
dis
Normal Transmit/Receive.
0
en
Halt Transmit and Receive FIFO and DMA accesses, Transmit 0s.
1
IRQ
Register for reading and clearing interrupt flags. All bits are write 1 to clear.
0x20
read-write
n
0x0
0x0
ABORT
Slave Abort Detected.
9
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
FAULT
Multi-Master Mode Fault.
8
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
M_DONE
Master Done, set when SPI Master has completed any transactions.
11
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_FULL
RX FIFO FULL.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_OVR
Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
14
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_UND
Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
15
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR0A
Slave Ready 0 Asserted.
16
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR1A
Slave Ready 1 Asserted.
17
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR2A
Slave Ready 2 Asserted.
18
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR3A
Slave Ready 3 Asserted.
19
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR4A
Slave Ready 4 Asserted.
20
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR5A
Slave Ready 5 Asserted.
21
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR6A
Slave Ready 6 Asserted.
22
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SR7A
Slave Ready 7 Asserted.
23
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSA
Slave Select Asserted.
4
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSD
Slave Select Deasserted.
5
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TIMEOUT
Timeout.
10
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_OVR
Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
12
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_UND
Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
13
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
IRQE
Register for enabling interrupts.
0x24
read-write
n
0x0
0x0
ABORT
Slave Abort Detected interrupt enable.
9
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
FAULT
Multi-Master Mode Fault interrupt enable.
8
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
M_DONE
Master Done interrupt enable.
11
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_FULL
RX FIFO FULL interrupt enable.
3
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_OVR
Receive FIFO Overrun interrupt enable.
14
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_THRESH
RX FIFO Threshold Crossed interrupt enable.
2
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_UND
Receive FIFO Underrun interrupt enable.
15
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR0A
Slave Ready 0 Asserted interrupt enable.
16
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR1A
Slave Ready 1 Asserted interrupt enable.
17
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR2A
Slave Ready 2 Asserted interrupt enable.
18
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR3A
Slave Ready 3 Asserted interrupt enable.
19
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR4A
Slave Ready 4 Asserted interrupt enable.
20
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR5A
Slave Ready 5 Asserted interrupt enable.
21
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR6A
Slave Ready 6 Asserted interrupt enable.
22
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SR7A
Slave Ready 7 Asserted interrupt enable.
23
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSA
Slave Select Asserted interrupt enable.
4
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSD
Slave Select Deasserted interrupt enable.
5
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TIMEOUT
Timeout interrupt enable.
10
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_EMPTY
TX FIFO Empty interrupt enable.
1
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_OVR
Transmit FIFO Overrun interrupt enable.
12
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_THRESH
TX FIFO Threshold interrupt enable.
0
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_UND
Transmit FIFO Underrun interrupt enable.
13
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
STAT
SPI Status register.
0x30
read-only
n
0x0
0x0
BUSY
SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.
0
1
not
SPI not active.
0
active
SPI active.
1
WAKE
Register for wake up flags. All bits in this register are write 1 to clear.
0x28
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
Wake on TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
WAKEE
Register for wake up enable.
0x2C
read-write
n
0x0
0x0
RX_FULL
Wake on RX FIFO Full Enable.
3
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
RX_THRESH
Wake on RX FIFO Threshold Crossed Enable.
2
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_EMPTY
Wake on TX FIFO Empty Enable.
1
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_THRESH
Wake on TX FIFO Threshold Crossed Enable.
0
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
XMEM_CTRL
Register to control external memory.
0x34
read-write
n
0x0
0x0
DUMMY_CLK
Dummy clocks.
16
8
RD_CMD
Read command.
0
8
WR_CMD
Write command.
8
8
XMEM_EN
XMEM enable.
31
1
SPIMSS
Serial Peripheral Interface.
SPIMSS
0x0
0x0
0x1000
registers
n
BRG
Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).
0x14
-1
read-only
n
0x0
0x0
BRG
Baud Rate Reload Value.
0
16
CTRL
SPI Control Register.
0x4
-1
read-only
n
0x0
0x0
BIRQ
Baud Rate Generator Timer Interrupt Request.
5
1
dis_en_enum
disable
0
enable
1
CLKPOL
Clock Polarity.
3
1
spi_pol_enum
idleLo
SCLK idles Low (0) after character transmission/reception.
0
idleHi
SCLK idles High (1) after character transmission/reception.
1
IRQE
Interrupt Request Enable.
7
1
dis_en_enum
disable
0
enable
1
MMEN
SPI Master Mode Enable.
1
1
slv_mst_enum
slave
0
master
1
PHASE
Phase Select.
4
1
spi_phase_enum
activeEdge
Transmit on active edge of SCLK.
0
inactiveEdge
Transmit on inactive edge of SCLK.
1
SPIEN
SPI Enable.
0
1
dis_en_enum
disable
0
enable
1
STR
Start SPI Interrupt.
6
1
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
WOR
Wired OR (open drain) Enable.
2
1
dis_en_enum
disable
0
enable
1
DATA16
SPI 16-bit Data Access
0x0
16
read-write
n
0x0
0x0
DATA
SPI data.
0
16
DATA80
SPI Data 8-bit access
DATA16
0x0
8
read-write
n
0x0
0x0
DATA
SPI data.
0
8
DATA81
SPI Data 8-bit access
DATA16
0x1
8
read-write
n
0x0
0x0
DATA
SPI data.
0
8
DMA
SPI DMA Register.
0x18
-1
read-only
n
0x0
0x0
RX_DMA_EN
Receive DMA Enable.
31
1
dis_en_enum
disable
0
enable
1
RX_FIFO_CLEAR
Receive FIFO Clear.
20
1
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
RX_FIFO_CNT
Receive FIFO Count.
24
4
read-only
RX_FIFO_LEVEL
Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.
16
3
fifo_level_enum
entry1
0
entries2
1
entries3
2
entries4
3
entries5
4
entries6
5
entries7
6
entries8
7
TX_DMA_EN
Transmit DMA Enable.
15
1
dis_en_enum
disable
0
enable
1
TX_FIFO_CLEAR
Transmit FIFO Clear.
4
1
write-only
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
TX_FIFO_CNT
Transmit FIFO Count.
8
4
read-only
TX_FIFO_LEVEL
Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.
0
3
fifo_level_enum
entry1
0
entries2
1
entries3
2
entries4
3
entries5
4
entries6
5
entries7
6
entries8
7
I2S_CTRL
I2S Control Register.
0x1C
-1
read-only
n
0x0
0x0
I2S_EN
I2S Mode Enable.
0
1
dis_en_enum
disable
0
enable
1
I2S_LJ
I2S Left Justify.
4
1
normal
Normal I2S audio protocol.
0
replaced
Audio data is synchronized with SSEL.
1
I2S_MONO
I2S Monophonic Audio Mode.
3
1
stereophonic
Stereophonic audio.
0
monophonic
Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
1
I2S_MUTE
I2S Mute transmit.
1
1
normal
Normal Transmit.
0
replaced
Transmit data is replaced with 0.
1
I2S_PAUSE
I2S Pause transmit/receive.
2
1
normal
Normal Transmit.
0
halt
Halt transmit and receive FIFO and DMA access, transmit 0's.
1
MOD
SPI Mode Register.
0xC
-1
read-only
n
0x0
0x0
NUMBITS
2
4
spi_bits_enum
bits16
0
bits1
1
bits10
10
bits11
11
bits12
12
bits13
13
bits14
14
bits15
15
bits2
2
bits3
3
bits4
4
bits5
5
bits6
6
bits7
7
bits8
8
bits9
9
SSIO
Slave Select I/O.
1
1
input_output_enum
input
0
output
1
SSL1
Slave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.
8
1
hi_lo_enum
hi
High.
0
lo
Low.
1
SSL2
Slave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.
9
1
hi_lo_enum
hi
High.
0
lo
Low.
1
SSL3
Slave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.
10
1
hi_lo_enum
hi
High.
0
lo
Low.
1
SSV
Slave Select Value.
0
1
lo_hi_enum
lo
The SSEL pin will be driven low.
0
hi
The SSEL pin will be driven high.
1
TX_LJ
Transmit Left Justify.
7
1
dis_en_enum
disable
0
enable
1
SPIMSS0_BRG
Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).
0x14
read-only
n
0x0
0x0
BRG
Baud Rate Reload Value.
0
16
SPIMSS0_CTRL
SPI Control Register.
0x4
read-only
n
0x0
0x0
BIRQ
Baud Rate Generator Timer Interrupt Request.
5
1
dis_en_enum
disable
None
0
enable
None
1
CLKPOL
Clock Polarity.
3
1
spi_pol_enum
idleLo
SCLK idles Low (0) after character transmission/reception.
0
idleHi
SCLK idles High (1) after character transmission/reception.
1
IRQE
Interrupt Request Enable.
7
1
dis_en_enum
disable
None
0
enable
None
1
MMEN
SPI Master Mode Enable.
1
1
slv_mst_enum
slave
None
0
master
None
1
PHASE
Phase Select.
4
1
spi_phase_enum
activeEdge
Transmit on active edge of SCLK.
0
inactiveEdge
Transmit on inactive edge of SCLK.
1
SPIEN
SPI Enable.
0
1
dis_en_enum
disable
None
0
enable
None
1
STR
Start SPI Interrupt.
6
1
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
WOR
Wired OR (open drain) Enable.
2
1
dis_en_enum
disable
None
0
enable
None
1
SPIMSS0_DATA16
SPI 16-bit Data Access
0x0
16
read-write
n
0x0
0x0
DATA
SPI data.
0
16
SPIMSS0_DATA8[0]
SPI Data 8-bit access
DATA16
0x0
8
read-write
n
0x0
0x0
DATA
SPI data.
0
8
SPIMSS0_DATA8[1]
SPI Data 8-bit access
DATA16
0x1
8
read-write
n
0x0
0x0
DATA
SPI data.
0
8
SPIMSS0_DMA
SPI DMA Register.
0x18
read-only
n
0x0
0x0
RX_DMA_EN
Receive DMA Enable.
31
1
dis_en_enum
disable
None
0
enable
None
1
RX_FIFO_CLEAR
Receive FIFO Clear.
20
1
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
RX_FIFO_CNT
Receive FIFO Count.
24
4
read-only
RX_FIFO_LEVEL
Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.
16
3
fifo_level_enum
entry1
None
0
entries2
None
1
entries3
None
2
entries4
None
3
entries5
None
4
entries6
None
5
entries7
None
6
entries8
None
7
TX_DMA_EN
Transmit DMA Enable.
15
1
dis_en_enum
disable
None
0
enable
None
1
TX_FIFO_CLEAR
Transmit FIFO Clear.
4
1
write-only
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
TX_FIFO_CNT
Transmit FIFO Count.
8
4
read-only
TX_FIFO_LEVEL
Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.
0
3
fifo_level_enum
entry1
None
0
entries2
None
1
entries3
None
2
entries4
None
3
entries5
None
4
entries6
None
5
entries7
None
6
entries8
None
7
SPIMSS0_I2S_CTRL
I2S Control Register.
0x1C
read-only
n
0x0
0x0
I2S_EN
I2S Mode Enable.
0
1
dis_en_enum
disable
None
0
enable
None
1
I2S_LJ
I2S Left Justify.
4
1
normal
Normal I2S audio protocol.
0
replaced
Audio data is synchronized with SSEL.
1
I2S_MONO
I2S Monophonic Audio Mode.
3
1
stereophonic
Stereophonic audio.
0
monophonic
Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
1
I2S_MUTE
I2S Mute transmit.
1
1
normal
Normal Transmit.
0
replaced
Transmit data is replaced with 0.
1
I2S_PAUSE
I2S Pause transmit/receive.
2
1
normal
Normal Transmit.
0
halt
Halt transmit and receive FIFO and DMA access, transmit 0's.
1
SPIMSS0_MOD
SPI Mode Register.
0xC
read-only
n
0x0
0x0
NUMBITS
2
4
spi_bits_enum
bits16
None
0
bits1
None
1
bits10
None
10
bits11
None
11
bits12
None
12
bits13
None
13
bits14
None
14
bits15
None
15
bits2
None
2
bits3
None
3
bits4
None
4
bits5
None
5
bits6
None
6
bits7
None
7
bits8
None
8
bits9
None
9
SSIO
Slave Select I/O.
1
1
input_output_enum
input
None
0
output
None
1
SSL1
Slave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.
8
1
hi_lo_enum
hi
High.
0
lo
Low.
1
SSL2
Slave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.
9
1
hi_lo_enum
hi
High.
0
lo
Low.
1
SSL3
Slave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.
10
1
hi_lo_enum
hi
High.
0
lo
Low.
1
SSV
Slave Select Value.
0
1
lo_hi_enum
lo
The SSEL pin will be driven low.
0
hi
The SSEL pin will be driven high.
1
TX_LJ
Transmit Left Justify.
7
1
dis_en_enum
disable
None
0
enable
None
1
SPIMSS0_STATUS
SPI Status Register.
0x8
read-only
n
0x0
0x0
ABT
Slave Mode Transaction Abort.
4
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
COL
Collision.
5
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
IRQ
SPI Interrupt Request.
7
1
oneToClear
flag_enum
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
ROVR
Receive Overrun.
3
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
SLAS
Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.
0
1
read-only
sel_enum
selected
None
0
notSelected
None
1
TOVR
Transmit Overrun.
6
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
TUND
Transmit Underrun.
2
1
oneToClear
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
TXST
Transmit Status.
1
1
read-only
busy_enum
idle
None
0
busy
None
1
STATUS
SPI Status Register.
0x8
-1
read-only
n
0x0
0x0
ABT
Slave Mode Transaction Abort.
4
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
COL
Collision.
5
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
IRQ
SPI Interrupt Request.
7
1
oneToClear
flag_enum
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
ROVR
Receive Overrun.
3
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
SLAS
Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.
0
1
read-only
sel_enum
selected
0
notSelected
1
TOVR
Transmit Overrun.
6
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
TUND
Transmit Underrun.
2
1
oneToClear
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
TXST
Transmit Status.
1
1
read-only
busy_enum
idle
0
busy
1
SPIXC_FIFO
SPI XiP Master Controller FIFO.
SPIXC_FIFO
0x0
0x0
0x1000
registers
n
RX_16
SPI RX FIFO 16-Bit Access
RX_8
0x4
16
read-only
n
0x0
0x0
uint16_t
RX_32
SPI RX FIFO 32-Bit Access
RX_8
0x4
32
read-only
n
0x0
0x0
uint32_t
RX_8
SPI RX FIFO 8-Bit Access
0x4
8
read-only
n
0x0
0x0
uint8_t
TX_16
SPI TX FIFO 16-Bit Write
TX_8
0x0
16
read-only
n
0x0
0x0
uint16_t
TX_32
SPI TX FIFO 32-Bit Write
TX_8
0x0
32
read-only
n
0x0
0x0
uint32_t
TX_8
SPI TX FIFO 8-Bit Write
0x0
8
read-only
n
0x0
0x0
uint8_t
SPIXF
SPIXF Master
SPIXF
0x0
0x0
0x1000
registers
n
CFG
SPIX Configuration Register.
0x0
read-only
n
0x0
0x0
HI_CLK
Number of system clocks that SCLK will be high when SCLK pulses are generated.
12
4
LO_CLK
Number of system clocks that SCLK will be low when SCLK pulses are generated.
8
4
MODE
Defines SPI Mode, Only valid values are 0 and 3.
0
2
SCLK_HI_SAMPLE_RISING
Description not available.
0
SCLK_LO_SAMPLE_FAILLING
Description not available.
3
SSACT
Slave Select Active Timing.
16
2
off
0 system clocks.
0
for_2_mod_clk
2 System clocks.
1
for_4_mod_clk
4 System clocks.
2
for_8_mod_clk
8 System clocks.
3
SSEL
Slave Select. Only valid value is zero.
4
3
SSIACT
Slave Select Inactive Timing.
18
2
for_1_mod_clk
1 system clocks.
0
for_3_mod_clk
3 System clocks.
1
for_5_mod_clk
5 System clocks.
2
for_9_mod_clk
9 System clocks.
3
SSPOL
Slave Select Polarity.
2
1
ACTIVE_HIGH
Slave Select is Active High.
0
ACTIVE_LOW
Slave Select is Active Low.
1
FETCH_CTRL
SPIX Fetch Control Register.
0x4
read-only
n
0x0
0x0
ADDR_WIDTH
Address Width. Number of data I/O used to send address, and mode/dummy clocks.
10
2
Single
Single SDIO.
0
Dual_IO
Dual SDIO.
1
Quad_IO
Quad SDIO.
2
Invalid
Invalid.
3
CMDVAL
Command Value sent to target to initiate fetching from SPI flash.
0
8
CMD_WIDTH
Command Width. Number of data I/O used to send commands.
8
2
Single
Single SDIO.
0
Dual_IO
Dual SDIO.
1
Quad_IO
Quad SDIO.
2
Invalid
Invalid.
3
DATA_WIDTH
Data Width. Number of data I/O used to receive data.
12
2
Single
Single SDIO.
0
Dual_IO
Dual SDIO.
1
Quad_IO
Quad SDIO.
2
Invalid
Invalid.
3
FOUR_BYTE_ADDR
Four Byte Address Mode. Enables 4-byte Flash Address Mode.
16
1
3
3 Byte Address Mode.
0
4
4 Byte Address Mode.
1
IO_CTRL
SPIX IO Control Register.
0x1C
read-only
n
0x0
0x0
PU_PD_CTRL
IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins.
3
2
tri_state
Tristate.
0
Pull_Up
Pull-Up.
1
Pull_down
Pull-Down.
2
SCLK_DS
SCLK drive Strength. This bit controls the drive strength on the SCLK pin.
0
1
Low
Low drive strength.
0
High
High drive strength.
1
SDIO_DS
SDIO Drive Strength. This bit controls the drive strength of all SDIO pins.
2
1
Low
Low drive strength.
0
High
High drive strength.
1
SS_DS
Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin.
1
1
Low
Low drive strength.
0
High
High drive strength.
1
MEMSECCN
SPIX Memory Security Control Register.
0x20
read-only
n
0x0
0x0
DECEN
Decryption Enable.
0
1
dis
Disable decryption of SPIX data.
0
en
Enable decryption of SPIX data.
1
MODE_CTRL
SPIX Mode Control Register.
0x8
read-only
n
0x0
0x0
MDCLK
Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.
0
4
NO_CMD
No Command Mode.
8
1
always
Send read command every time SPI transaction is initiated.
0
once
Send read command only once. NO read command in subsequent SPI transactions.
1
MODE_DATA
SPIX Mode Data Register.
0xC
read-only
n
0x0
0x0
DATA
Mode Data. Specifies the data to send with the Dummy/Mode clocks.
0
16
OUT_EN
Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA.
16
16
SCLK_FB_CTRL
SPIX Feedback Control Register.
0x10
read-only
n
0x0
0x0
FB_EN
Enable SCLK feedback mode.
0
1
dis
Disable SCLK feedback mode.
0
en
Enable SCLK feedback mode.
1
IGNORE_CLKS
Number of clocks to ignore after SS asertion prior to reading data.
4
6
IGNORE_CLKS_NO_CMD
Number of clocks to ignore after SS asertion prior to reading data when a read command is not explicitly sent.
12
6
INVERT_EN
Invert SCLK in feedback mode.
1
1
dis
Disable Invert SCLK feedback mode.
0
en
Enable Invert SCLK feedback mode.
1
SPIXFC
SPI XiP Flash Configuration Controller
SPIXFC
0x0
0x0
0x1000
registers
n
SPIXFC
SPIXFC IRQ
38
CFG
Configuration Register.
0x0
read-only
n
0x0
0x0
HI_CLK
SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high.
8
4
16_SCLK
16 system clocks.
0
LO_CLK
SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low.
12
4
16_SCLK
16 system clocks.
0
MODE
Defines SPI Mode, Only valid values are 0 and 3.
4
2
SPIX_Mode_0
SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0.
0
SPIX_Mode_3
SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1.
3
PAGE_SIZE
Page Size.
6
2
4_bytes
4 bytes.
0
8_bytes
8 bytes.
1
16_bytes
16 bytes.
2
32_bytes
32 bytes.
3
SSEL
Slaves Select.
0
3
Slave_0
Slave 0 is selected.
0
Slave_1
Slave 1 is selected.
1
SS_ACT
Slaves Select Activate Timing.
16
2
0_CLKS
0 sytem clocks.
0
2_CLKS
2 sytem clocks.
1
4_CLKS
4 sytem clocks.
2
8_CLKS
8 sytem clocks.
3
SS_INACT
Slaves Select Inactive Timing.
18
2
4_CLKS
4 sytem clocks.
0
6_CLKS
6 sytem clocks.
1
8_CLKS
8 sytem clocks.
2
12_CLKS
12 sytem clocks.
3
FIFO_CTRL
SPIX Controller FIFO Control and Status Register.
0xC
read-only
n
0x0
0x0
RX_FIFO_AF_LVL
Results FIFO Almost Full Level.
16
5
RX_FIFO_CNT
Result FIFO Used.
24
6
TX_FIFO_AE_LVL
Transaction FIFO Almost Empty Level.
0
4
TX_FIFO_CNT
Transaction FIFO Used.
8
5
GEN_CTRL
SPIX Controller General Controller Register.
0x8
read-only
n
0x0
0x0
BBMODE
Bit-Bang Mode.
3
1
dis
Disable Bit-Bang Mode.
0
en
Enable Bit-Bang Mode.
1
BB_DATA
No description available.
12
4
SDIO0
SDIO[0]
0
SDIO1
SDIO[1]
1
SDIO2
SDIO[2]
2
SDIO3
SDIO[3]
3
BB_DATA_OUT_EN
Bit Bang SDIO Output Enable.
16
4
SDIO0
SDIO[0]
0
SDIO1
SDIO[1]
1
SDIO2
SDIO[2]
2
SDIO3
SDIO[3]
3
ENABLE
SPI Master enable.
0
1
dis
Disable SPI Master, putting a reset state.
0
en
Enable SPI Master for processing transactions.
1
RX_FIFO_EN
Result FIFO Enable.
2
1
DIS_RXFIFO
Disable Result FIFO.
0
EN_RXFIFO
Enable Result FIFO.
1
SCLK_DR
SSCLK Drive and State.
6
1
SCLK_0
SCLK is 0.
0
SCLK_1
SCLK is 1.
1
SCLK_FB
Enable SCLK Feedback Mode.
24
1
Dis
None
0
En
None
1
SDIO_DATA_IN
SDIO Input Data Value.
8
4
SDIO0
SDIO[0]
0
SDIO1
SDIO[1]
1
SDIO2
SDIO[2]
2
SDIO3
SDIO[3]
3
SSDR
This bits reflects the state of the currently selected slave select.
4
1
output0
Selected Slave select output = 0.
0
output1
Selected Slave select output = 1.
1
TX_FIFO_EN
Transaction FIFO Enable.
1
1
dis_txfifo
Disable Transaction FIFO.
0
en_txfifo
Enable Transaction FIFO.
1
INTEN
SPIX Controller Interrupt Enable Register.
0x18
read-only
n
0x0
0x0
RX_DONE
Results Done Interrupt Enable.
3
1
EN
Disable Results Done Interrupt.
0
DIS
Enable Results Done Interrupt.
1
RX_FIFO_AF
Results FIFO Almost Full Interrupt Enable.
5
1
EN
Disable Results FIFO Almost Full Interrupt.
0
DIS
Enable Results FIFO Almost Full Interrupt.
1
RX_STALLED
Results Stalled Interrupt Enable.
1
1
EN
Disable Results Stalled Interrupt.
0
DIS
Enable Results Stalled Interrupt.
1
TX_FIFO_AE
Transaction FIFO Almost Empty Interrupt Enable.
4
1
EN
Disable Transaction FIFO Almost Empty Interrupt.
0
DIS
Enable Transaction FIFO Almost Empty Interrupt.
1
TX_READY
Transaction Ready Interrupt Enable.
2
1
EN
Disable FIFO Transaction Ready Interrupt.
0
DIS
Enable FIFO Transaction Ready Interrupt.
1
TX_STALLED
Transaction Stalled Interrupt Enable.
0
1
EN
Disable Transaction Stalled Interrupt.
0
DIS
Enable Transaction Stalled Interrupt.
1
INTFL
SPIX Controller Interrupt Status Register.
0x14
read-only
n
0x0
0x0
RX_DONE
Results Done Interrupt Status.
3
1
CLR
Results FIFO ready.
0
SET
Results FIFO Not ready.
1
RX_FIFO_AF
Results FIFO Almost Full Flag.
5
1
CLR
Results FIFO level below the Almost Full level.
0
SET
Results FIFO level at Almost Full level.
1
RX_STALLED
Results Stalled Interrupt Flag.
1
1
CLR
Normal FIFO Operation.
0
SET
Stalled FIFO.
1
TX_FIFO_AE
Transaction FIFO Almost Empty Flag.
4
1
CLR
Transaction FIFO not Almost Empty.
0
SET
Transaction FIFO Almost Empty.
1
TX_READY
Transaction Ready Interrupt Status.
2
1
CLR
FIFO Transaction not ready.
0
SET
FIFO Transaction ready.
1
TX_STALLED
Transaction Stalled Interrupt Flag.
0
1
CLR
Normal FIFO Transaction.
0
SET
Stalled FIFO Transaction.
1
SPCTRL
SPIX Controller Special Control Register.
0x10
read-only
n
0x0
0x0
SCLKINH3
SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams.
16
1
EN
Allow trailing SCLK low pulse prior to Slave Select de-assertion.
0
DIS
Inhibit trailing SCLK low pulse prior to Slave Select de-assertion.
1
SS_POL
SPIX Controller Slave Select Polarity Register.
0x4
read-only
n
0x0
0x0
SS_POLARITY
Slave Select Polarity.
0
1
lo
Active Low.
0
hi
Active High.
1
TMR0
32-bit reloadable timer that can be used for timing and event counting.
Timers
0x0
0x0
0x1000
registers
n
TMR0
TMR0 IRQ
5
CMP
Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
0x4
read-only
n
0x0
0x0
CN
Timer Control Register.
0x10
read-only
n
0x0
0x0
NOLHPOL
Timer PWM output 0A polarity bit.
10
1
dis
Disable.
0
en
Enable.
1
NOLLPOL
Timer PWM output 0A' polarity bit.
11
1
dis
Disable.
0
en
Enable.
1
PRES
Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
3
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
PRES3
MSB of prescaler value.
8
1
PWMCKBD
Timer PWM output 0A Mode Disable.
12
1
en
Enable.
0
dis
Disable.
1
PWMSYNC
Timer PWM Synchronization Mode Enable.
9
1
dis
Disable.
0
en
Enable.
1
TEN
Timer Enable.
7
1
dis
Disable.
0
en
Enable.
1
TMODE
Timer Mode.
0
3
oneShot
One Shot Mode.
0
continuous
Continuous Mode.
1
counter
Counter Mode.
2
pwm
PWM Mode.
3
capture
Capture Mode.
4
compare
Compare Mode.
5
gated
Gated Mode.
6
captureCompare
Capture/Compare Mode.
7
TPOL
Timer input/output polarity bit.
6
1
activeHi
Active High.
0
activeLo
Active Low.
1
CNT
Count. This register stores the current timer count.
0x0
read-only
n
0x0
0x0
INTR
Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
0xC
read-only
n
0x0
0x0
oneToClear
IRQ_CLR
Clear Interrupt.
0
1
NOLCMP
Timer Non-Overlapping Compare Register.
0x14
read-only
n
0x0
0x0
NOLHCMP
Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
8
8
NOLLCMP
Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
0
8
PWM
PWM. This register stores the value that is compared to the current timer count.
0x8
read-only
n
0x0
0x0
TMR1
32-bit reloadable timer that can be used for timing and event counting. 1
Timers
0x0
0x0
0x1000
registers
n
TMR1
TMR1 IRQ
6
CMP
Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
0x4
read-only
n
0x0
0x0
CN
Timer Control Register.
0x10
read-only
n
0x0
0x0
NOLHPOL
Timer PWM output 0A polarity bit.
10
1
dis
Disable.
0
en
Enable.
1
NOLLPOL
Timer PWM output 0A' polarity bit.
11
1
dis
Disable.
0
en
Enable.
1
PRES
Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
3
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
PRES3
MSB of prescaler value.
8
1
PWMCKBD
Timer PWM output 0A Mode Disable.
12
1
en
Enable.
0
dis
Disable.
1
PWMSYNC
Timer PWM Synchronization Mode Enable.
9
1
dis
Disable.
0
en
Enable.
1
TEN
Timer Enable.
7
1
dis
Disable.
0
en
Enable.
1
TMODE
Timer Mode.
0
3
oneShot
One Shot Mode.
0
continuous
Continuous Mode.
1
counter
Counter Mode.
2
pwm
PWM Mode.
3
capture
Capture Mode.
4
compare
Compare Mode.
5
gated
Gated Mode.
6
captureCompare
Capture/Compare Mode.
7
TPOL
Timer input/output polarity bit.
6
1
activeHi
Active High.
0
activeLo
Active Low.
1
CNT
Count. This register stores the current timer count.
0x0
read-only
n
0x0
0x0
INTR
Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
0xC
read-only
n
0x0
0x0
oneToClear
IRQ_CLR
Clear Interrupt.
0
1
NOLCMP
Timer Non-Overlapping Compare Register.
0x14
read-only
n
0x0
0x0
NOLHCMP
Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
8
8
NOLLCMP
Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
0
8
PWM
PWM. This register stores the value that is compared to the current timer count.
0x8
read-only
n
0x0
0x0
TMR2
32-bit reloadable timer that can be used for timing and event counting. 2
Timers
0x0
0x0
0x1000
registers
n
TMR2
TMR2 IRQ
7
CMP
Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
0x4
read-only
n
0x0
0x0
CN
Timer Control Register.
0x10
read-only
n
0x0
0x0
NOLHPOL
Timer PWM output 0A polarity bit.
10
1
dis
Disable.
0
en
Enable.
1
NOLLPOL
Timer PWM output 0A' polarity bit.
11
1
dis
Disable.
0
en
Enable.
1
PRES
Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
3
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
PRES3
MSB of prescaler value.
8
1
PWMCKBD
Timer PWM output 0A Mode Disable.
12
1
en
Enable.
0
dis
Disable.
1
PWMSYNC
Timer PWM Synchronization Mode Enable.
9
1
dis
Disable.
0
en
Enable.
1
TEN
Timer Enable.
7
1
dis
Disable.
0
en
Enable.
1
TMODE
Timer Mode.
0
3
oneShot
One Shot Mode.
0
continuous
Continuous Mode.
1
counter
Counter Mode.
2
pwm
PWM Mode.
3
capture
Capture Mode.
4
compare
Compare Mode.
5
gated
Gated Mode.
6
captureCompare
Capture/Compare Mode.
7
TPOL
Timer input/output polarity bit.
6
1
activeHi
Active High.
0
activeLo
Active Low.
1
CNT
Count. This register stores the current timer count.
0x0
read-only
n
0x0
0x0
INTR
Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
0xC
read-only
n
0x0
0x0
oneToClear
IRQ_CLR
Clear Interrupt.
0
1
NOLCMP
Timer Non-Overlapping Compare Register.
0x14
read-only
n
0x0
0x0
NOLHCMP
Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
8
8
NOLLCMP
Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
0
8
PWM
PWM. This register stores the value that is compared to the current timer count.
0x8
read-only
n
0x0
0x0
TMR3
32-bit reloadable timer that can be used for timing and event counting. 3
Timers
0x0
0x0
0x1000
registers
n
TMR3
TMR3 IRQ
8
CMP
Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
0x4
read-only
n
0x0
0x0
CN
Timer Control Register.
0x10
read-only
n
0x0
0x0
NOLHPOL
Timer PWM output 0A polarity bit.
10
1
dis
Disable.
0
en
Enable.
1
NOLLPOL
Timer PWM output 0A' polarity bit.
11
1
dis
Disable.
0
en
Enable.
1
PRES
Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
3
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
PRES3
MSB of prescaler value.
8
1
PWMCKBD
Timer PWM output 0A Mode Disable.
12
1
en
Enable.
0
dis
Disable.
1
PWMSYNC
Timer PWM Synchronization Mode Enable.
9
1
dis
Disable.
0
en
Enable.
1
TEN
Timer Enable.
7
1
dis
Disable.
0
en
Enable.
1
TMODE
Timer Mode.
0
3
oneShot
One Shot Mode.
0
continuous
Continuous Mode.
1
counter
Counter Mode.
2
pwm
PWM Mode.
3
capture
Capture Mode.
4
compare
Compare Mode.
5
gated
Gated Mode.
6
captureCompare
Capture/Compare Mode.
7
TPOL
Timer input/output polarity bit.
6
1
activeHi
Active High.
0
activeLo
Active Low.
1
CNT
Count. This register stores the current timer count.
0x0
read-only
n
0x0
0x0
INTR
Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
0xC
read-only
n
0x0
0x0
oneToClear
IRQ_CLR
Clear Interrupt.
0
1
NOLCMP
Timer Non-Overlapping Compare Register.
0x14
read-only
n
0x0
0x0
NOLHCMP
Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
8
8
NOLLCMP
Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
0
8
PWM
PWM. This register stores the value that is compared to the current timer count.
0x8
read-only
n
0x0
0x0
TMR4
32-bit reloadable timer that can be used for timing and event counting. 4
Timers
0x0
0x0
0x1000
registers
n
TMR4
TMR4 IRQ
9
CMP
Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
0x4
read-only
n
0x0
0x0
CN
Timer Control Register.
0x10
read-only
n
0x0
0x0
NOLHPOL
Timer PWM output 0A polarity bit.
10
1
dis
Disable.
0
en
Enable.
1
NOLLPOL
Timer PWM output 0A' polarity bit.
11
1
dis
Disable.
0
en
Enable.
1
PRES
Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
3
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
PRES3
MSB of prescaler value.
8
1
PWMCKBD
Timer PWM output 0A Mode Disable.
12
1
en
Enable.
0
dis
Disable.
1
PWMSYNC
Timer PWM Synchronization Mode Enable.
9
1
dis
Disable.
0
en
Enable.
1
TEN
Timer Enable.
7
1
dis
Disable.
0
en
Enable.
1
TMODE
Timer Mode.
0
3
oneShot
One Shot Mode.
0
continuous
Continuous Mode.
1
counter
Counter Mode.
2
pwm
PWM Mode.
3
capture
Capture Mode.
4
compare
Compare Mode.
5
gated
Gated Mode.
6
captureCompare
Capture/Compare Mode.
7
TPOL
Timer input/output polarity bit.
6
1
activeHi
Active High.
0
activeLo
Active Low.
1
CNT
Count. This register stores the current timer count.
0x0
read-only
n
0x0
0x0
INTR
Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
0xC
read-only
n
0x0
0x0
oneToClear
IRQ_CLR
Clear Interrupt.
0
1
NOLCMP
Timer Non-Overlapping Compare Register.
0x14
read-only
n
0x0
0x0
NOLHCMP
Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
8
8
NOLLCMP
Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
0
8
PWM
PWM. This register stores the value that is compared to the current timer count.
0x8
read-only
n
0x0
0x0
TMR5
32-bit reloadable timer that can be used for timing and event counting. 5
Timers
0x0
0x0
0x1000
registers
n
TMR5
TMR5 IRQ
10
CMP
Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
0x4
read-only
n
0x0
0x0
CN
Timer Control Register.
0x10
read-only
n
0x0
0x0
NOLHPOL
Timer PWM output 0A polarity bit.
10
1
dis
Disable.
0
en
Enable.
1
NOLLPOL
Timer PWM output 0A' polarity bit.
11
1
dis
Disable.
0
en
Enable.
1
PRES
Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
3
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
PRES3
MSB of prescaler value.
8
1
PWMCKBD
Timer PWM output 0A Mode Disable.
12
1
en
Enable.
0
dis
Disable.
1
PWMSYNC
Timer PWM Synchronization Mode Enable.
9
1
dis
Disable.
0
en
Enable.
1
TEN
Timer Enable.
7
1
dis
Disable.
0
en
Enable.
1
TMODE
Timer Mode.
0
3
oneShot
One Shot Mode.
0
continuous
Continuous Mode.
1
counter
Counter Mode.
2
pwm
PWM Mode.
3
capture
Capture Mode.
4
compare
Compare Mode.
5
gated
Gated Mode.
6
captureCompare
Capture/Compare Mode.
7
TPOL
Timer input/output polarity bit.
6
1
activeHi
Active High.
0
activeLo
Active Low.
1
CNT
Count. This register stores the current timer count.
0x0
read-only
n
0x0
0x0
INTR
Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
0xC
read-only
n
0x0
0x0
oneToClear
IRQ_CLR
Clear Interrupt.
0
1
NOLCMP
Timer Non-Overlapping Compare Register.
0x14
read-only
n
0x0
0x0
NOLHCMP
Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
8
8
NOLLCMP
Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
0
8
PWM
PWM. This register stores the value that is compared to the current timer count.
0x8
read-only
n
0x0
0x0
TRNG
Random Number Generator.
TRNG
0x0
0x0
0x1000
registers
n
TRNG
TRNG interrupt.
4
CN
TRNG Control Register.
0x0
read-only
n
0x0
0x0
AESKG
AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.
6
1
complete
No operation/complete.
0
start
Start operation.
1
RNG_I4S
Random Number 4 Word Status. This bit is set when a new 128 bit random number is ready to be read (using 4 consecutive reads of the TRNG Data Register). When set, an interrupt will be generated if the RNG_IE bit is also set. This bit is cleared by setting the RNG_ISC bit.
4
1
read-only
busy
Result not ready.
0
ready
Operation complete and result ready.
1
RNG_IE
Random Number Interrupt Enable. This bit enables an interrupt to be generated when a new, 128 bit, random number is ready to be read.
2
1
dis
Disable.
0
en
Enable.
1
RNG_IS
Random Number Word Status. This bit is set when at least one 32 bit random number is ready to be read. This bit is cleared by hardware if all the random words have been read. It is needed to poll this bit before reading the TRNG Data Register.
5
1
read-only
busy
Result not ready.
0
ready
Operation complete and result ready.
1
RNG_ISC
Random Number Interrupt Status Clear. Setting this bit to 1 clears the RNG_I4S bit and acknowledges the interrupt, if enabled. This bit is a write only bit and always reads as zero.
3
1
write-only
write
no_effect
No Effect.
0
clear
Clear the Status bit.
1
DATA
Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.
0x4
read-only
n
0x0
0x0
DATA
Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.
0
32
UART0
UART
UART0
0x0
0x0
0x1000
registers
n
UART0
UART0 IRQ
14
BAUD0
Baud rate register. Integer portion.
0x14
32
read-only
n
0x0
0x0
FACTOR
FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.
16
2
128
Baud Factor 128
0
64
Baud Factor 64
1
32
Baud Factor 32
2
16
Baud Factor 16
3
IBAUD
Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).
0
12
BAUD1
Baud rate register. Decimal Setting.
0x18
32
read-only
n
0x0
0x0
DBAUD
Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.
0
12
CTRL
Control Register.
0x0
32
read-only
n
0x0
0x0
BITACC
If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.
7
1
FRAME
Frame accuracy.
0
BIT
Bit accuracy.
1
BREAK
Break control bit. It causes a break condition to be transmitted to receiving UART.
14
1
DIS
Break characters are not generated.
0
EN
Break characters are sent(all the bits are at '0' including start/parity/stop).
1
CHAR_SIZE
Selects UART character size.
8
2
5
5 bits.
0
6
6 bits.
1
7
7 bits.
2
8
8 bits.
3
CLKSEL
Baud Rate Clock Source Select. Selects the baud rate clock.
15
1
SYSTEM
System clock.
0
ALTERNATE
Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.
1
ENABLE
UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.
0
1
dis
UART disabled. FIFOs are flushed. Clock is gated off for power savings.
0
en
UART enabled.
1
FLOW_CTRL
Enables/disables hardware flow control.
11
1
dis
HW Flow Control disabled
0
en
HW Flow Control with RTS/CTS enabled
1
FLOW_POL
RTS/CTS polarity.
12
1
0
RTS/CTS asserted is logic 0.
0
1
RTS/CTS asserted is logic 1.
1
NULL_MODEM
NULL Modem Support (RTS/CTS and TXD/RXD swap).
13
1
DIS
Direct convention.
0
EN
Null Modem Mode.
1
PARITY
When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1 Space parity = always 0.
2
2
Even
Even parity selected.
0
ODD
Odd parity selected.
1
MARK
Mark parity selected.
2
SPACE
Space parity selected.
3
PARITY_EN
Enable/disable Parity bit (9th character).
1
1
dis
No Parity
0
en
Parity enabled as 9th bit
1
PARMD
Selects parity based on 1s or 0s count (when PARITY_EN=1).
4
1
1
Parity calculation is based on number of 1s in frame.
0
0
Parity calculation is based on number of 0s in frame.
1
RX_FLUSH
Flushes the RX FIFO buffer.
6
1
RX_TO
RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read.
16
8
STOPBITS
Selects the number of stop bits that will be generated.
10
1
1
1 stop bit.
0
1_5
1.5 stop bits.
1
TX_FLUSH
Flushes the TX FIFO buffer.
5
1
DMA
DMA Configuration.
0x20
32
read-only
n
0x0
0x0
RXDMA_EN
RX DMA channel enable.
1
1
dis
DMA is disabled
0
en
DMA is enabled
1
RXDMA_LEVEL
RX threshold for DMA transmission.
16
6
TDMA_EN
TX DMA channel enable.
0
1
dis
DMA is disabled
0
en
DMA is enabled
1
TXDMA_LEVEL
TX threshold for DMA transmission.
8
6
FIFO
FIFO Data buffer.
0x1C
32
read-only
n
0x0
0x0
FIFO
Load/unload location for TX and RX FIFO buffers.
0
8
INT_EN
Interrupt Enable Register.
0xC
32
read-only
n
0x0
0x0
BREAK
Enable for received BREAK character interrupt.
7
1
CTS_CHANGE
Enable for CTS signal change interrupt.
2
1
LAST_BREAK
Enable for Last break character interrupt.
9
1
RX_FIFO_THRESH
Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
RX_FRAME_ERROR
Enable for RX Frame Error Interrupt.
0
1
RX_OVERRUN
Enable for RX FIFO OVerrun interrupt.
3
1
RX_PARITY_ERROR
Enable for RX Parity Error interrupt.
1
1
RX_TIMEOUT
Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
TX_FIFO_ALMOST_EMPTY
Enable for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_THRESH
Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
INT_FL
Interrupt Status Flags.
0x10
32
read-only
n
0x0
0x0
oneToClear
BREAK
FLAG for received BREAK character interrupt.
7
1
CTS_CHANGE
FLAG for CTS signal change interrupt.
2
1
LAST_BREAK
FLAG for Last break character interrupt.
9
1
RX_FIFO_THRESH
FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
RX_FRAME_ERROR
FLAG for RX Frame Error Interrupt.
0
1
RX_OVERRUN
FLAG for RX FIFO Overrun interrupt.
3
1
RX_PARITY_ERROR
FLAG for RX Parity Error interrupt.
1
1
RX_TIMEOUT
FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
TX_FIFO_ALMOST_EMPTY
FLAG for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_THRESH
FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
STATUS
Status Register.
0x8
32
read-only
n
0x0
0x0
BREAK
Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
3
1
read-only
PARITY
9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.
2
1
read-only
RX_BUSY
Read-only flag indicating the UARTreceiver status.
1
1
read-only
RX_EMPTY
Read-only flag indicating the RX FIFO state.
4
1
read-only
RX_FIFO_CNT
Indicates the number of bytes currently in the RX FIFO.
8
6
read-only
RX_FULL
Read-only flag indicating the RX FIFO state.
5
1
read-only
RX_TO
RX Timeout status.
24
1
read-only
TX_BUSY
Read-only flag indicating the UART transmit status.
0
1
read-only
TX_EMPTY
Read-only flag indicating the TX FIFO state.
6
1
read-only
TX_FIFO_CNT
Indicates the number of bytes currently in the TX FIFO.
16
6
read-only
TX_FULL
Read-only flag indicating the TX FIFO state.
7
1
read-only
THRESH_CTRL
Threshold Control register.
0x4
32
read-only
n
0x0
0x0
RTS_FIFO_THRESH
RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.
16
6
RX_FIFO_THRESH
RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.
0
6
TX_FIFO_THRESH
TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.
8
6
TX_FIFO
Transmit FIFO Status register.
0x24
32
read-only
n
0x0
0x0
DATA
Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).
0
7
UART1
UART 1
UART0
0x0
0x0
0x1000
registers
n
UART1
UART1 IRQ
15
BAUD0
Baud rate register. Integer portion.
0x14
32
read-only
n
0x0
0x0
FACTOR
FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.
16
2
128
Baud Factor 128
0
64
Baud Factor 64
1
32
Baud Factor 32
2
16
Baud Factor 16
3
IBAUD
Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).
0
12
BAUD1
Baud rate register. Decimal Setting.
0x18
32
read-only
n
0x0
0x0
DBAUD
Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.
0
12
CTRL
Control Register.
0x0
32
read-only
n
0x0
0x0
BITACC
If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.
7
1
FRAME
Frame accuracy.
0
BIT
Bit accuracy.
1
BREAK
Break control bit. It causes a break condition to be transmitted to receiving UART.
14
1
DIS
Break characters are not generated.
0
EN
Break characters are sent(all the bits are at '0' including start/parity/stop).
1
CHAR_SIZE
Selects UART character size.
8
2
5
5 bits.
0
6
6 bits.
1
7
7 bits.
2
8
8 bits.
3
CLKSEL
Baud Rate Clock Source Select. Selects the baud rate clock.
15
1
SYSTEM
System clock.
0
ALTERNATE
Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.
1
ENABLE
UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.
0
1
dis
UART disabled. FIFOs are flushed. Clock is gated off for power savings.
0
en
UART enabled.
1
FLOW_CTRL
Enables/disables hardware flow control.
11
1
dis
HW Flow Control disabled
0
en
HW Flow Control with RTS/CTS enabled
1
FLOW_POL
RTS/CTS polarity.
12
1
0
RTS/CTS asserted is logic 0.
0
1
RTS/CTS asserted is logic 1.
1
NULL_MODEM
NULL Modem Support (RTS/CTS and TXD/RXD swap).
13
1
DIS
Direct convention.
0
EN
Null Modem Mode.
1
PARITY
When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1 Space parity = always 0.
2
2
Even
Even parity selected.
0
ODD
Odd parity selected.
1
MARK
Mark parity selected.
2
SPACE
Space parity selected.
3
PARITY_EN
Enable/disable Parity bit (9th character).
1
1
dis
No Parity
0
en
Parity enabled as 9th bit
1
PARMD
Selects parity based on 1s or 0s count (when PARITY_EN=1).
4
1
1
Parity calculation is based on number of 1s in frame.
0
0
Parity calculation is based on number of 0s in frame.
1
RX_FLUSH
Flushes the RX FIFO buffer.
6
1
RX_TO
RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read.
16
8
STOPBITS
Selects the number of stop bits that will be generated.
10
1
1
1 stop bit.
0
1_5
1.5 stop bits.
1
TX_FLUSH
Flushes the TX FIFO buffer.
5
1
DMA
DMA Configuration.
0x20
32
read-only
n
0x0
0x0
RXDMA_EN
RX DMA channel enable.
1
1
dis
DMA is disabled
0
en
DMA is enabled
1
RXDMA_LEVEL
RX threshold for DMA transmission.
16
6
TDMA_EN
TX DMA channel enable.
0
1
dis
DMA is disabled
0
en
DMA is enabled
1
TXDMA_LEVEL
TX threshold for DMA transmission.
8
6
FIFO
FIFO Data buffer.
0x1C
32
read-only
n
0x0
0x0
FIFO
Load/unload location for TX and RX FIFO buffers.
0
8
INT_EN
Interrupt Enable Register.
0xC
32
read-only
n
0x0
0x0
BREAK
Enable for received BREAK character interrupt.
7
1
CTS_CHANGE
Enable for CTS signal change interrupt.
2
1
LAST_BREAK
Enable for Last break character interrupt.
9
1
RX_FIFO_THRESH
Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
RX_FRAME_ERROR
Enable for RX Frame Error Interrupt.
0
1
RX_OVERRUN
Enable for RX FIFO OVerrun interrupt.
3
1
RX_PARITY_ERROR
Enable for RX Parity Error interrupt.
1
1
RX_TIMEOUT
Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
TX_FIFO_ALMOST_EMPTY
Enable for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_THRESH
Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
INT_FL
Interrupt Status Flags.
0x10
32
read-only
n
0x0
0x0
oneToClear
BREAK
FLAG for received BREAK character interrupt.
7
1
CTS_CHANGE
FLAG for CTS signal change interrupt.
2
1
LAST_BREAK
FLAG for Last break character interrupt.
9
1
RX_FIFO_THRESH
FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
RX_FRAME_ERROR
FLAG for RX Frame Error Interrupt.
0
1
RX_OVERRUN
FLAG for RX FIFO Overrun interrupt.
3
1
RX_PARITY_ERROR
FLAG for RX Parity Error interrupt.
1
1
RX_TIMEOUT
FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
TX_FIFO_ALMOST_EMPTY
FLAG for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_THRESH
FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
STATUS
Status Register.
0x8
32
read-only
n
0x0
0x0
BREAK
Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
3
1
read-only
PARITY
9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.
2
1
read-only
RX_BUSY
Read-only flag indicating the UARTreceiver status.
1
1
read-only
RX_EMPTY
Read-only flag indicating the RX FIFO state.
4
1
read-only
RX_FIFO_CNT
Indicates the number of bytes currently in the RX FIFO.
8
6
read-only
RX_FULL
Read-only flag indicating the RX FIFO state.
5
1
read-only
RX_TO
RX Timeout status.
24
1
read-only
TX_BUSY
Read-only flag indicating the UART transmit status.
0
1
read-only
TX_EMPTY
Read-only flag indicating the TX FIFO state.
6
1
read-only
TX_FIFO_CNT
Indicates the number of bytes currently in the TX FIFO.
16
6
read-only
TX_FULL
Read-only flag indicating the TX FIFO state.
7
1
read-only
THRESH_CTRL
Threshold Control register.
0x4
32
read-only
n
0x0
0x0
RTS_FIFO_THRESH
RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.
16
6
RX_FIFO_THRESH
RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.
0
6
TX_FIFO_THRESH
TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.
8
6
TX_FIFO
Transmit FIFO Status register.
0x24
32
read-only
n
0x0
0x0
DATA
Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).
0
7
UART2
UART 2
UART0
0x0
0x0
0x1000
registers
n
UART2
UART2 IRQ
34
BAUD0
Baud rate register. Integer portion.
0x14
32
read-only
n
0x0
0x0
FACTOR
FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.
16
2
128
Baud Factor 128
0
64
Baud Factor 64
1
32
Baud Factor 32
2
16
Baud Factor 16
3
IBAUD
Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).
0
12
BAUD1
Baud rate register. Decimal Setting.
0x18
32
read-only
n
0x0
0x0
DBAUD
Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.
0
12
CTRL
Control Register.
0x0
32
read-only
n
0x0
0x0
BITACC
If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.
7
1
FRAME
Frame accuracy.
0
BIT
Bit accuracy.
1
BREAK
Break control bit. It causes a break condition to be transmitted to receiving UART.
14
1
DIS
Break characters are not generated.
0
EN
Break characters are sent(all the bits are at '0' including start/parity/stop).
1
CHAR_SIZE
Selects UART character size.
8
2
5
5 bits.
0
6
6 bits.
1
7
7 bits.
2
8
8 bits.
3
CLKSEL
Baud Rate Clock Source Select. Selects the baud rate clock.
15
1
SYSTEM
System clock.
0
ALTERNATE
Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.
1
ENABLE
UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.
0
1
dis
UART disabled. FIFOs are flushed. Clock is gated off for power savings.
0
en
UART enabled.
1
FLOW_CTRL
Enables/disables hardware flow control.
11
1
dis
HW Flow Control disabled
0
en
HW Flow Control with RTS/CTS enabled
1
FLOW_POL
RTS/CTS polarity.
12
1
0
RTS/CTS asserted is logic 0.
0
1
RTS/CTS asserted is logic 1.
1
NULL_MODEM
NULL Modem Support (RTS/CTS and TXD/RXD swap).
13
1
DIS
Direct convention.
0
EN
Null Modem Mode.
1
PARITY
When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1 Space parity = always 0.
2
2
Even
Even parity selected.
0
ODD
Odd parity selected.
1
MARK
Mark parity selected.
2
SPACE
Space parity selected.
3
PARITY_EN
Enable/disable Parity bit (9th character).
1
1
dis
No Parity
0
en
Parity enabled as 9th bit
1
PARMD
Selects parity based on 1s or 0s count (when PARITY_EN=1).
4
1
1
Parity calculation is based on number of 1s in frame.
0
0
Parity calculation is based on number of 0s in frame.
1
RX_FLUSH
Flushes the RX FIFO buffer.
6
1
RX_TO
RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read.
16
8
STOPBITS
Selects the number of stop bits that will be generated.
10
1
1
1 stop bit.
0
1_5
1.5 stop bits.
1
TX_FLUSH
Flushes the TX FIFO buffer.
5
1
DMA
DMA Configuration.
0x20
32
read-only
n
0x0
0x0
RXDMA_EN
RX DMA channel enable.
1
1
dis
DMA is disabled
0
en
DMA is enabled
1
RXDMA_LEVEL
RX threshold for DMA transmission.
16
6
TDMA_EN
TX DMA channel enable.
0
1
dis
DMA is disabled
0
en
DMA is enabled
1
TXDMA_LEVEL
TX threshold for DMA transmission.
8
6
FIFO
FIFO Data buffer.
0x1C
32
read-only
n
0x0
0x0
FIFO
Load/unload location for TX and RX FIFO buffers.
0
8
INT_EN
Interrupt Enable Register.
0xC
32
read-only
n
0x0
0x0
BREAK
Enable for received BREAK character interrupt.
7
1
CTS_CHANGE
Enable for CTS signal change interrupt.
2
1
LAST_BREAK
Enable for Last break character interrupt.
9
1
RX_FIFO_THRESH
Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
RX_FRAME_ERROR
Enable for RX Frame Error Interrupt.
0
1
RX_OVERRUN
Enable for RX FIFO OVerrun interrupt.
3
1
RX_PARITY_ERROR
Enable for RX Parity Error interrupt.
1
1
RX_TIMEOUT
Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
TX_FIFO_ALMOST_EMPTY
Enable for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_THRESH
Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
INT_FL
Interrupt Status Flags.
0x10
32
read-only
n
0x0
0x0
oneToClear
BREAK
FLAG for received BREAK character interrupt.
7
1
CTS_CHANGE
FLAG for CTS signal change interrupt.
2
1
LAST_BREAK
FLAG for Last break character interrupt.
9
1
RX_FIFO_THRESH
FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
RX_FRAME_ERROR
FLAG for RX Frame Error Interrupt.
0
1
RX_OVERRUN
FLAG for RX FIFO Overrun interrupt.
3
1
RX_PARITY_ERROR
FLAG for RX Parity Error interrupt.
1
1
RX_TIMEOUT
FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
TX_FIFO_ALMOST_EMPTY
FLAG for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_THRESH
FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
STATUS
Status Register.
0x8
32
read-only
n
0x0
0x0
BREAK
Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
3
1
read-only
PARITY
9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.
2
1
read-only
RX_BUSY
Read-only flag indicating the UARTreceiver status.
1
1
read-only
RX_EMPTY
Read-only flag indicating the RX FIFO state.
4
1
read-only
RX_FIFO_CNT
Indicates the number of bytes currently in the RX FIFO.
8
6
read-only
RX_FULL
Read-only flag indicating the RX FIFO state.
5
1
read-only
RX_TO
RX Timeout status.
24
1
read-only
TX_BUSY
Read-only flag indicating the UART transmit status.
0
1
read-only
TX_EMPTY
Read-only flag indicating the TX FIFO state.
6
1
read-only
TX_FIFO_CNT
Indicates the number of bytes currently in the TX FIFO.
16
6
read-only
TX_FULL
Read-only flag indicating the TX FIFO state.
7
1
read-only
THRESH_CTRL
Threshold Control register.
0x4
32
read-only
n
0x0
0x0
RTS_FIFO_THRESH
RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.
16
6
RX_FIFO_THRESH
RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.
0
6
TX_FIFO_THRESH
TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.
8
6
TX_FIFO
Transmit FIFO Status register.
0x24
32
read-only
n
0x0
0x0
DATA
Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).
0
7
USBHS
USB 2.0 High-speed Controller.
USBHS
0x0
0x0
0x1000
registers
n
USB
USB IRQ
2
COUNT0
Number of received bytes in EP 0 FIFO (INDEX == 0).
0x18
16
read-only
n
0x0
0x0
COUNT0
Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1
0
7
read-only
CSR0
Control status register for EP 0 (when INDEX == 0).
0x12
8
read-only
n
0x0
0x0
DATA_END
Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet.
3
1
read-write
INPKTRDY
EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared.
1
1
read-write
OUTPKTRDY
EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO.
0
1
read-only
SEND_STALL
Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set.
5
1
read-write
SENT_STALL
Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear.
2
1
read-write
SERV_OUTPKTRDY
Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set.
6
1
read-write
SERV_SETUP_END
Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set
7
1
read-write
SETUP_END
Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear.
4
1
read-only
CTHSRTN
Sets delay between HS resume to UTM normal operating mode.
0x82
16
read-only
n
0x0
0x0
C_T_HSTRN
High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation.
0
16
CTUCH
Chirp timeout timer setting.
0x80
16
read-only
n
0x0
0x0
C_T_UCH
HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host.
0
16
EARLYDMA
DMA timing control register.
0x7B
8
read-only
n
0x0
0x0
EDMAIN
1
1
read-write
EDMAOUT
0
1
read-write
EPINFO
Endpoint hardware information.
0x78
8
read-only
n
0x0
0x0
INTENDPOINTS
0
4
read-only
OUTENDPOINTS
4
4
read-only
FADDR
Function address register.
0x0
8
read-only
n
0x0
0x0
ADDR
Function address for this controller.
0
7
read-write
UPDATE
Set when ADDR is written, cleared when new address takes effect.
7
1
read-only
FIFO0
Read for OUT data FIFO, write for IN data FIFO.
0x20
read-only
n
0x0
0x0
USBHS_FIFO0
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO1
Read for OUT data FIFO, write for IN data FIFO.
0x24
read-only
n
0x0
0x0
USBHS_FIFO1
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO10
Read for OUT data FIFO, write for IN data FIFO.
0x48
read-only
n
0x0
0x0
USBHS_FIFO10
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO11
Read for OUT data FIFO, write for IN data FIFO.
0x4C
read-only
n
0x0
0x0
USBHS_FIFO11
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO12
Read for OUT data FIFO, write for IN data FIFO.
0x50
read-only
n
0x0
0x0
USBHS_FIFO12
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO13
Read for OUT data FIFO, write for IN data FIFO.
0x54
read-only
n
0x0
0x0
USBHS_FIFO13
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO14
Read for OUT data FIFO, write for IN data FIFO.
0x58
read-only
n
0x0
0x0
USBHS_FIFO14
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO15
Read for OUT data FIFO, write for IN data FIFO.
0x5C
read-only
n
0x0
0x0
USBHS_FIFO15
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO2
Read for OUT data FIFO, write for IN data FIFO.
0x28
read-only
n
0x0
0x0
USBHS_FIFO2
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO3
Read for OUT data FIFO, write for IN data FIFO.
0x2C
read-only
n
0x0
0x0
USBHS_FIFO3
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO4
Read for OUT data FIFO, write for IN data FIFO.
0x30
read-only
n
0x0
0x0
USBHS_FIFO4
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO5
Read for OUT data FIFO, write for IN data FIFO.
0x34
read-only
n
0x0
0x0
USBHS_FIFO5
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO6
Read for OUT data FIFO, write for IN data FIFO.
0x38
read-only
n
0x0
0x0
USBHS_FIFO6
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO7
Read for OUT data FIFO, write for IN data FIFO.
0x3C
read-only
n
0x0
0x0
USBHS_FIFO7
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO8
Read for OUT data FIFO, write for IN data FIFO.
0x40
read-only
n
0x0
0x0
USBHS_FIFO8
USBHS Endpoint FIFO Read/Write Register.
0
32
FIFO9
Read for OUT data FIFO, write for IN data FIFO.
0x44
read-only
n
0x0
0x0
USBHS_FIFO9
USBHS Endpoint FIFO Read/Write Register.
0
32
FRAME
Frame number.
0xC
16
read-only
n
0x0
0x0
FRAMENUM
Read the last received frame number, that is the 11-bit frame number received in the SOF packet.
0
11
read-only
HWVERS
HWVERS
0x6C
16
read-only
n
0x0
0x0
USBHS_HWVERS
USBHS Register.
0
16
INCSRL
Control status lower register for INx endpoint (x == INDEX).
CSR0
0x12
8
read-only
n
0x0
0x0
CLRDATATOG
Write 1 to clear IN endpoint data-toggle to 0.
6
1
read-write
FIFONOTEMPTY
Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear.
1
1
read-write
FLUSHFIFO
Flush Next Packet from IN FIFO. Write 1 to clear
3
1
read-write
INCOMPTX
Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear.
7
1
read-write
INPKTRDY
IN Packet Ready. Write a 1 to clear
0
1
read-only
SENDSTALL
Send STALL Handshake.
4
1
read-only
terminate
Terminate STALL handhsake
0
respond
Respond to an IN token with a STALL handshake
1
SENTSTALL
Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear.
5
1
read-write
UNDERRUN
Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear
2
1
read-write
INCSRU
Control status upper register for INx endpoint (x == INDEX).
0x13
8
read-only
n
0x0
0x0
AUTOSET
Auto Set inpktrdy.
7
1
read-write
set
USBHS_INCSRL_inpktrdy must be set by firmware.
0
auto
USBHS_INCSRL_inpktrdy is automatically set.
1
DMAREQEN
DMA Request Enable
4
1
read-write
dis
Disable DMA for this IN endpoint.
0
en
Enable DMA for this IN endpoint.
1
DMAREQMODE
DMA Request Mode Enable
2
1
read-write
0
Enable DMA Request Mode 0.
0
1
Enable DMA Request Mode 1.
1
DPKTBUFDIS
Double Packet Buffering Disable
1
1
read-write
en
Enable Double packet buffering.
0
dis
Disable Double Packet Buffering.
1
FRCDATATOG
Force In Data - Toggle
3
1
read-write
received
Toggle data-toglge only when an ACK is received.
0
dontcare
Toggle data-toggle regardless of ACK.
1
ISO
Isochronous Transfer Enable
6
1
read-write
interrupt
Enable IN Bulk and IN interrupt transfers.
0
isochronous
Enable IN Isochronous transfers.
1
MODE
Endpoint Direction Mode.
5
1
read-write
out
Endpoint direction is OUT.
0
in
Endpoint direction is IN.
1
INDEX
Index for banked registers.
0xE
8
read-only
n
0x0
0x0
INDEX
Index Register Access Selector.
0
4
read-write
INMAXP
Maximum packet size for INx endpoint (x == INDEX).
0x10
16
read-only
n
0x0
0x0
MAXPACKETSIZE
Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9
0
11
NUMPACKMINUS1
Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases.
11
5
INTRIN
Interrupt register for EP0 and IN EP1-15.
0x2
16
read-only
n
0x0
0x0
EP0_IN_INT
Endpoint 0 interrupt.
0
1
read-only
EP10_IN_INT
Endpoint 10 interrupt.
10
1
read-only
EP11_IN_INT
Endpoint 11 interrupt.
11
1
read-only
EP12_IN_INT
Endpoint 12 interrupt.
12
1
read-only
EP13_IN_INT
Endpoint 13 interrupt.
13
1
read-only
EP14_IN_INT
Endpoint 14 interrupt.
14
1
read-only
EP15_IN_INT
Endpoint 15 interrupt.
15
1
read-only
EP1_IN_INT
Endpoint 1 interrupt.
1
1
read-only
EP2_IN_INT
Endpoint 2 interrupt.
2
1
read-only
EP3_IN_INT
Endpoint 3 interrupt.
3
1
read-only
EP4_IN_INT
Endpoint 4 interrupt.
4
1
read-only
EP5_IN_INT
Endpoint 5 interrupt.
5
1
read-only
EP6_IN_INT
Endpoint 6 interrupt.
6
1
read-only
EP7_IN_INT
Endpoint 7 interrupt.
7
1
read-only
EP8_IN_INT
Endpoint 8 interrupt.
8
1
read-only
EP9_IN_INT
Endpoint 9 interrupt.
9
1
read-only
INTRINEN
Interrupt enable for EP 0 and IN EP 1-15.
0x6
16
read-only
n
0x0
0x0
EP0_INT_EN
Endpoint 0 interrupt enable.
0
1
read-write
EP10_IN_INT_EN
Endpoint 10 interrupt enable.
10
1
read-write
EP11_IN_INT_EN
Endpoint 11 interrupt enable.
11
1
read-write
EP12_IN_INT_EN
Endpoint 12 interrupt enable.
12
1
read-write
EP13_IN_INT_EN
Endpoint 13 interrupt enable.
13
1
read-write
EP14_IN_INT_EN
Endpoint 14 interrupt enable.
14
1
read-write
EP15_IN_INT_EN
Endpoint 15 interrupt enable.
15
1
read-write
EP1_IN_INT_EN
Endpoint 1 interrupt enable.
1
1
read-write
EP2_IN_INT_EN
Endpoint 2 interrupt enable.
2
1
read-write
EP3_IN_INT_EN
Endpoint 3 interrupt enable.
3
1
read-write
EP4_IN_INT_EN
Endpoint 4 interrupt enable.
4
1
read-write
EP5_IN_INT_EN
Endpoint 5 interrupt enable.
5
1
read-write
EP6_IN_INT_EN
Endpoint 6 interrupt enable.
6
1
read-write
EP7_IN_INT_EN
Endpoint 7 interrupt enable.
7
1
read-write
EP8_IN_INT_EN
Endpoint 8 interrupt enable.
8
1
read-write
EP9_IN_INT_EN
Endpoint 9 interrupt enable.
9
1
read-write
INTROUT
Interrupt register for OUT EP 1-15.
0x4
16
read-only
n
0x0
0x0
EP10_OUT_INT
Endpoint 10 interrupt.
10
1
read-only
EP11_OUT_INT
Endpoint 11 interrupt.
11
1
read-only
EP12_OUT_INT
Endpoint 12 interrupt.
12
1
read-only
EP13_OUT_INT
Endpoint 13 interrupt.
13
1
read-only
EP14_OUT_INT
Endpoint 14 interrupt.
14
1
read-only
EP15_OUT_INT
Endpoint 15 interrupt.
15
1
read-only
EP1_OUT_INT
Endpoint 1 interrupt.
1
1
read-only
EP2_OUT_INT
Endpoint 2 interrupt.
2
1
read-only
EP3_OUT_INT
Endpoint 3 interrupt.
3
1
read-only
EP4_OUT_INT
Endpoint 4 interrupt.
4
1
read-only
EP5_OUT_INT
Endpoint 5 interrupt.
5
1
read-only
EP6_OUT_INT
Endpoint 6 interrupt.
6
1
read-only
EP7_OUT_INT
Endpoint 7 interrupt.
7
1
read-only
EP8_OUT_INT
Endpoint 8 interrupt.
8
1
read-only
EP9_OUT_INT
Endpoint 9 interrupt.
9
1
read-only
INTROUTEN
Interrupt enable for OUT EP 1-15.
0x8
16
read-only
n
0x0
0x0
EP10_OUT_INT_EN
Endpoint 10 interrupt.
10
1
read-write
EP11_OUT_INT_EN
Endpoint 11 interrupt.
11
1
read-write
EP12_OUT_INT_EN
Endpoint 12 interrupt.
12
1
read-write
EP13_OUT_INT_EN
Endpoint 13 interrupt.
13
1
read-write
EP14_OUT_INT_EN
Endpoint 14 interrupt.
14
1
read-write
EP15_OUT_INT_EN
Endpoint 15 interrupt.
15
1
read-write
EP1_OUT_INT_EN
Endpoint 1 interrupt.
1
1
read-write
EP2_OUT_INT_EN
Endpoint 2 interrupt.
2
1
read-write
EP3_OUT_INT_EN
Endpoint 3 interrupt.
3
1
read-write
EP4_OUT_INT_EN
Endpoint 4 interrupt.
4
1
read-write
EP5_OUT_INT_EN
Endpoint 5 interrupt.
5
1
read-write
EP6_OUT_INT_EN
Endpoint 6 interrupt.
6
1
read-write
EP7_OUT_INT_EN
Endpoint 7 interrupt.
7
1
read-write
EP8_OUT_INT_EN
Endpoint 8 interrupt.
8
1
read-write
EP9_OUT_INT_EN
Endpoint 9 interrupt.
9
1
read-write
INTRUSB
Interrupt register for common USB interrupts.
0xA
8
read-only
n
0x0
0x0
RESET_INT
Bus reset detected.
2
1
read-only
RESUME_INT
Resume detected.
1
1
read-only
SOF_INT
Start of Frame.
3
1
read-only
SUSPEND_INT
Suspend detected.
0
1
read-only
INTRUSBEN
Interrupt enable for common USB interrupts.
0xB
8
read-only
n
0x0
0x0
RESET_INT_EN
Bus reset detected.
2
1
read-write
RESUME_INT_EN
Resume detected.
1
1
read-write
SOF_INT_EN
Start of Frame.
3
1
read-write
SUSPEND_INT_EN
Suspend detected.
0
1
read-write
M31_PHY_CORECLKIN
M31_PHY_CORECLKIN
0x448
read-only
n
0x0
0x0
M31_PHY_NONCRY_EN
M31_PHY_NONCRY_EN
0x418
read-only
n
0x0
0x0
M31_PHY_NONCRY_RSTB
M31_PHY_NONCRY_RSTB
0x414
read-only
n
0x0
0x0
M31_PHY_OSCOUTEN
M31_PHY_OSCOUTEN
0x43C
read-only
n
0x0
0x0
M31_PHY_OUTCLKSEL
M31_PHY_OUTCLKSEL
0x45C
read-only
n
0x0
0x0
M31_PHY_PLL_EN
M31_PHY_PLL_EN
0x430
read-only
n
0x0
0x0
M31_PHY_PONRST
M31_PHY_PONRST
0x410
read-only
n
0x0
0x0
M31_PHY_XTLSEL
M31_PHY_XTLSEL
0x44C
read-only
n
0x0
0x0
MXM_INT
USB Added Maxim Interrupt Flag Register.
0x498
read-only
n
0x0
0x0
NOVBUS
NOVBUS
1
1
VBUS
VBUS
0
1
MXM_INT_EN
USB Added Maxim Interrupt Enable Register.
0x49C
read-only
n
0x0
0x0
NOVBUS
NOVBUS
1
1
VBUS
VBUS
0
1
MXM_REG_A4
USB Added Maxim Power Status Register
0x4A4
read-only
n
0x0
0x0
DMA_INT
DMA_INT
1
1
VRST_VDDB_N_A
VRST_VDDB_N_A
0
1
MXM_SUSPEND
USB Added Maxim Suspend Register.
0x4A0
read-only
n
0x0
0x0
SEL
Suspend register
0
1
OUTCOUNT
Number of received bytes in OUT EPx FIFO (x == INDEX).
COUNT0
0x18
16
read-only
n
0x0
0x0
OUTCOUNT
Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO.
0
13
read-only
OUTCSRL
Control status lower register for OUTx endpoint (x == INDEX).
0x16
8
read-only
n
0x0
0x0
CLRDATATOG
7
1
read-write
DATAERROR
3
1
read-only
FIFOFULL
1
1
read-only
FLUSHFIFO
4
1
read-write
OUTPKTRDY
0
1
read-write
OVERRUN
2
1
read-write
SENDSTALL
5
1
read-write
SENTSTALL
6
1
read-write
OUTCSRU
Control status upper register for OUTx endpoint (x == INDEX).
0x17
8
read-only
n
0x0
0x0
AUTOCLEAR
7
1
read-write
DISNYET
4
1
read-write
DMAREQEN
5
1
read-write
DMAREQMODE
3
1
read-write
DPKTBUFDIS
1
1
read-write
INCOMPRX
0
1
read-only
ISO
6
1
read-write
OUTMAXP
Maximum packet size for OUTx endpoint (x == INDEX).
0x14
16
read-only
n
0x0
0x0
MAXPACKETSIZE
Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9.
0
11
NUMPACKMINUS1
Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize.
11
5
POWER
Power management register.
0x1
8
read-only
n
0x0
0x0
EN_SUSPENDM
Enable SUSPENDM signal.
0
1
read-write
HS_ENABLE
High-speed mode enable.
5
1
read-write
HS_MODE
High-speed mode detected.
4
1
read-only
ISO_UPDATE
Wait for SOF during Isochronous xfers.
7
1
read-write
RESET
Bus reset detected.
3
1
read-only
RESUME
Generate resume signaling.
2
1
read-write
SOFTCONN
Softconn.
6
1
read-write
SUSPEND
Suspend mode detected.
1
1
read-only
RAMINFO
RAM width and DMA hardware information.
0x79
8
read-only
n
0x0
0x0
DMACHANS
4
4
read-only
RAMBITS
0
4
read-only
SOFTRESET
Software reset register.
0x7A
8
read-only
n
0x0
0x0
RSTS
0
1
read-write
RSTXS
1
1
read-write
TESTMODE
USB 2.0 test mode enable register.
0xF
8
read-only
n
0x0
0x0
FORCE_FS
Force USB to Full-speed after reset.
5
1
read-write
FORCE_HS
Force USB to High-speed after reset.
4
1
read-write
TEST_J
Force USB to continuous J state.
1
1
read-write
TEST_K
Force USB to continuous K state.
2
1
read-write
TEST_PKT
Transmit fixed test packet.
3
1
read-write
TEST_SE0_NAK
Respond to any valid IN token with NAK.
0
1
read-write
WDT0
Watchdog Timer 0
WDT0
0x0
0x0
0x400
registers
n
WDT0
WDT0 IRQ
1
CTRL
Watchdog Timer Control Register.
0x0
read-only
n
0x0
0x0
INT_EN
Watchdog Timer Interrupt Enable.
10
1
dis
Disable.
0
en
Enable.
1
INT_FLAG
Watchdog Timer Interrupt Flag.
9
1
oneToClear
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
INT_PERIOD
Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
0
4
wdt2pow31
2**31 clock cycles.
0
wdt2pow30
2**30 clock cycles.
1
wdt2pow21
2**21 clock cycles.
10
wdt2pow20
2**20 clock cycles.
11
wdt2pow19
2**19 clock cycles.
12
wdt2pow18
2**18 clock cycles.
13
wdt2pow17
2**17 clock cycles.
14
wdt2pow16
2**16 clock cycles.
15
wdt2pow29
2**29 clock cycles.
2
wdt2pow28
2**28 clock cycles.
3
wdt2pow27
2^27 clock cycles.
4
wdt2pow26
2**26 clock cycles.
5
wdt2pow25
2**25 clock cycles.
6
wdt2pow24
2**24 clock cycles.
7
wdt2pow23
2**23 clock cycles.
8
wdt2pow22
2**22 clock cycles.
9
RST_EN
Watchdog Timer Reset Enable.
11
1
dis
Disable.
0
en
Enable.
1
RST_FLAG
Watchdog Timer Reset Flag.
31
1
read-write
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
RST_PERIOD
Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
4
4
wdt2pow31
2**31 clock cycles.
0
wdt2pow30
2**30 clock cycles.
1
wdt2pow21
2**21 clock cycles.
10
wdt2pow20
2**20 clock cycles.
11
wdt2pow19
2**19 clock cycles.
12
wdt2pow18
2**18 clock cycles.
13
wdt2pow17
2**17 clock cycles.
14
wdt2pow16
2**16 clock cycles.
15
wdt2pow29
2**29 clock cycles.
2
wdt2pow28
2**28 clock cycles.
3
wdt2pow27
2^27 clock cycles.
4
wdt2pow26
2**26 clock cycles.
5
wdt2pow25
2**25 clock cycles.
6
wdt2pow24
2**24 clock cycles.
7
wdt2pow23
2**23 clock cycles.
8
wdt2pow22
2**22 clock cycles.
9
WDT_EN
Watchdog Timer Enable.
8
1
dis
Disable.
0
en
Enable.
1
RST
Watchdog Timer Reset Register.
0x4
write-only
n
0x0
0x0
WDT_RST
Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.
0
8
seq1
The second value to be written to reset the WDT.
0x0000005A
seq0
The first value to be written to reset the WDT.
0x000000A5
WDT1
Watchdog Timer 0 1
WDT0
0x0
0x0
0x400
registers
n
WDT1
WDT1 IRQ
57
CTRL
Watchdog Timer Control Register.
0x0
read-only
n
0x0
0x0
INT_EN
Watchdog Timer Interrupt Enable.
10
1
dis
Disable.
0
en
Enable.
1
INT_FLAG
Watchdog Timer Interrupt Flag.
9
1
oneToClear
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
INT_PERIOD
Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
0
4
wdt2pow31
2**31 clock cycles.
0
wdt2pow30
2**30 clock cycles.
1
wdt2pow21
2**21 clock cycles.
10
wdt2pow20
2**20 clock cycles.
11
wdt2pow19
2**19 clock cycles.
12
wdt2pow18
2**18 clock cycles.
13
wdt2pow17
2**17 clock cycles.
14
wdt2pow16
2**16 clock cycles.
15
wdt2pow29
2**29 clock cycles.
2
wdt2pow28
2**28 clock cycles.
3
wdt2pow27
2^27 clock cycles.
4
wdt2pow26
2**26 clock cycles.
5
wdt2pow25
2**25 clock cycles.
6
wdt2pow24
2**24 clock cycles.
7
wdt2pow23
2**23 clock cycles.
8
wdt2pow22
2**22 clock cycles.
9
RST_EN
Watchdog Timer Reset Enable.
11
1
dis
Disable.
0
en
Enable.
1
RST_FLAG
Watchdog Timer Reset Flag.
31
1
read-write
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
RST_PERIOD
Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
4
4
wdt2pow31
2**31 clock cycles.
0
wdt2pow30
2**30 clock cycles.
1
wdt2pow21
2**21 clock cycles.
10
wdt2pow20
2**20 clock cycles.
11
wdt2pow19
2**19 clock cycles.
12
wdt2pow18
2**18 clock cycles.
13
wdt2pow17
2**17 clock cycles.
14
wdt2pow16
2**16 clock cycles.
15
wdt2pow29
2**29 clock cycles.
2
wdt2pow28
2**28 clock cycles.
3
wdt2pow27
2^27 clock cycles.
4
wdt2pow26
2**26 clock cycles.
5
wdt2pow25
2**25 clock cycles.
6
wdt2pow24
2**24 clock cycles.
7
wdt2pow23
2**23 clock cycles.
8
wdt2pow22
2**22 clock cycles.
9
WDT_EN
Watchdog Timer Enable.
8
1
dis
Disable.
0
en
Enable.
1
RST
Watchdog Timer Reset Register.
0x4
write-only
n
0x0
0x0
WDT_RST
Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.
0
8
seq1
The second value to be written to reset the WDT.
0x0000005A
seq0
The first value to be written to reset the WDT.
0x000000A5