Renesas R7FA2E1A93CBV 2024.04.28 R7FA2E1A93CBV false ACMPLP Low-Power Analog Comparator ACMPLP 0x0 0x0 0x3 registers n COMPFIR ACMPLP Filter Control Register 0x1 8 read-write n 0x0 0x0 C0EDG ACMPLP0 Edge Detection Selection 3 read-write 0 Interrupt and ELC event request by one-edge detection #0 1 Interrupt and ELC event request by both-edge detection #1 C0EPO ACMPLP0 Edge Polarity Switching 2 read-write 0 Interrupt and ELC event request on rising edge #0 1 Interrupt and ELC event request on falling edge #1 C0FCK ACMPLP0 Filter Select 0 1 read-write 00 No Sampling (bypass) #00 01 Sampling at PCLKB #01 10 Sampling at PCLKB/8 #10 11 Sampling at PCLKB/32 #11 C1EDG ACMPLP1 Edge Detection Selection 7 read-write 0 Interrupt and ELC event request by one-edge detection #0 1 Interrupt and ELC event request by both-edge detection #1 C1EPO ACMPLP1 Edge Polarity Switching 6 read-write 0 Interrupt and ELC event request on rising edge #0 1 Interrupt and ELC event request on falling edge #1 C1FCK ACMPLP1 Filter Select 4 1 read-write 00 No Sampling (bypass) #00 01 Sampling at PCLKB #01 10 Sampling at PCLKB/8 #10 11 Sampling at PCLKB/32 #11 COMPMDR ACMPLP Mode Setting Register 0x0 8 read-write n 0x0 0x0 C0ENB ACMPLP0 Operation Enable 0 read-write 0 Disable comparator channel ACMPLP0 #0 1 Enable comparator channel ACMPLP0 #1 C0MON ACMPLP0 Monitor Flag 3 read-only C0VRF ACMPLP0 Reference Voltage Selection 2 read-write 0 Select CMPREF0 input as ACMPLP0 reference voltage. #0 1 Select internal reference voltage (Vref) as ACMPLP0 reference voltage. #1 C0WDE ACMPLP0 Window Function Mode Enable 1 read-write 0 Disable window function for ACMPLP0 #0 1 Enable window function for ACMPLP0 #1 C1ENB ACMPLP1 Operation Enable 4 read-write 0 Disable ACMPLP1 operation #0 1 Enable ACMPLP1 operation #1 C1MON ACMPLP1 Monitor Flag 7 read-only C1VRF ACMPLP1 Reference Voltage Selection 6 read-write 0 Select CMPREF1 input as ACMPLP1 reference voltage. #0 1 Select internal reference voltage (Vref) as ACMPLP1 reference voltage. #1 C1WDE ACMPLP1 Window Function Mode Enable 5 read-write 0 Disable ACMPLP1 window function mode #0 1 Enable ACMPLP1 window function mode #1 COMPOCR ACMPLP Output Control Register 0x2 8 read-write n 0x0 0x0 C0OE ACMPLP0 VCOUT Pin Output Enable 1 read-write 0 Disabled #0 1 Enabled #1 C0OP ACMPLP0 VCOUT Output Polarity Selection 2 read-write 0 Non-inverted #0 1 Inverted #1 C1OE ACMPLP1 VCOUT Pin Output Enable 5 read-write 0 Disabled #0 1 Enabled #1 C1OP ACMPLP1 VCOUT Output Polarity Selection 6 read-write 0 Non-inverted #0 1 Inverted #1 SPDMD ACMPLP0/ACMPLP1 Speed Selection 7 read-write 0 Low-speed mode #0 1 High-speed mode #1 ADC120 12-bit A/D Converter ADC120 0x0 0x0 0x2 registers n 0x4 0x9 registers n 0x40 0xE registers n 0x7A 0x1 registers n 0x7E 0x1 registers n 0x80 0x2 registers n 0x84 0x4 registers n 0x8A 0x1 registers n 0x8C 0x1 registers n 0x90 0x15 registers n 0xA6 0x1 registers n 0xA8 0x5 registers n 0xDD 0xE registers n 0xE 0x28 registers n ADACSR A/D Conversion Operation Mode Select Register 0x7E 8 read-write n 0x0 0x0 ADSAC Successive Approximation Control Setting 1 read-write 0 Normal conversion mode (default) #0 1 Fast conversion mode #1 ADADC A/D-Converted Value Addition/Average Count Select Register 0xC 8 read-write n 0x0 0x0 ADC Addition/Average Count Select 0 2 read-write Others Setting prohibited 000 1-time conversion (no addition, same as normal conversion) #000 001 2-time conversion (one addition) #001 010 3-time conversion (two additions) #010 011 4-time conversion (three additions) #011 101 16-time conversion (15 additions) #101 AVEE Average Mode Select 7 read-write 0 Enable addition mode #0 1 Enable average mode #1 ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x8 16 read-write n 0x0 0x0 ADSn A/D-Converted Value Addition/Average Channel Select 0 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0xA 16 read-write n 0x0 0x0 ADSn A/D-Converted Value Addition/Average Channel Select 0 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSA0 A/D Channel Select Register A0 0x4 16 read-write n 0x0 0x0 ANSAn A/D Conversion Channels Select 0 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSA1 A/D Channel Select Register A1 0x6 16 read-write n 0x0 0x0 ANSAn A/D Conversion Channels Select 0 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSB0 A/D Channel Select Register B0 0x14 16 read-write n 0x0 0x0 ANSBn A/D Conversion Channels Select 0 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADANSB1 A/D Channel Select Register B1 0x16 16 read-write n 0x0 0x0 ANSBn A/D Conversion Channels Select 0 15 read-write 0 Do not select associated input channel. #0 1 Select associated input channel. #1 ADCER A/D Control Extended Register 0xE 16 read-write n 0x0 0x0 ACE A/D Data Register Automatic Clearing Enable 5 read-write 0 Disable automatic clearing #0 1 Enable automatic clearing #1 ADRFMT A/D Data Register Format Select 15 read-write 0 Select right-justified for the A/D data register format #0 1 Select left-justified for the A/D data register format #1 DIAGLD Self-Diagnosis Mode Select 10 read-write 0 Select rotation mode for self-diagnosis voltage #0 1 Select mixed mode for self-diagnosis voltage #1 DIAGM Self-Diagnosis Enable 11 read-write 0 Disable ADC12 self-diagnosis #0 1 Enable ADC12 self-diagnosis #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 1 read-write 00 Setting prohibited when self-diagnosis is enabled #00 01 0 volts #01 10 Reference power supply voltage × 1/2 #10 11 Reference power supply voltage #11 ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x92 8 read-write n 0x0 0x0 CMPOCA Internal Reference Voltage Compare Select 1 read-write 0 Exclude the internal reference voltage from the compare Window A target range. #0 1 Include the internal reference voltage in the compare Window A target range. #1 CMPTSA Temperature Sensor Output Compare Select 0 read-write 0 Exclude the temperature sensor output from the compare Window A target range. #0 1 Include the temperature sensor output in the compare Window A target range. #1 ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x94 16 read-write n 0x0 0x0 CMPCHAn Compare Window A Channel Select 0 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x96 16 read-write n 0x0 0x0 CMPCHAn Compare Window A Channel Select 0 15 read-write 0 Disable compare function for associated input channel #0 1 Enable compare function for associated input channel #1 ADCMPBNSR A/D Compare Function Window B Channel Select Register 0xA6 8 read-write n 0x0 0x0 CMPCHB Compare Window B Channel Select 0 5 read-write CMPLB Compare Window B Comparison Condition Setting 7 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADWINLLB value, or ADWINULB value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADWINLLB value < A/D-converted value < ADWINULB value #1 ADCMPBSR A/D Compare Function Window B Status Register 0xAC 8 read-write n 0x0 0x0 CMPSTB Compare Window B Flag 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPCR A/D Compare Function Control Register 0x90 16 read-write n 0x0 0x0 CMPAB Window A/B Composite Conditions Setting 0 1 read-write 00 Output ADC120_WCMPM when window A OR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #00 01 Output ADC120_WCMPM when window A EXOR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #01 10 Output ADC120_WCMPM when window A AND window B comparison conditions are met. Otherwise, output ADC120_WCMPUM. #10 11 Setting prohibited. #11 CMPAE Compare Window A Operation Enable 11 read-write 0 Disable compare window A operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window A operation. #1 CMPAIE Compare A Interrupt Enable 15 read-write 0 Disable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #0 1 Enable ADC120_CMPAI interrupt when comparison conditions (window A) are met. #1 CMPBE Compare Window B Operation Enable 9 read-write 0 Disable compare window B operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. #0 1 Enable compare window B operation. #1 CMPBIE Compare B Interrupt Enable 13 read-write 0 Disable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #0 1 Enable ADC120_CMPBI interrupt when comparison conditions (window B) are met. #1 WCMPE Window Function Setting 14 read-write 0 Disable window function Window A and window B operate as a comparator to compare the single value on the lower side with the A/D conversion result. #0 1 Enable window function Window A and window B operate as a comparator to compare the two values on the upper and lower sides with the A/D conversion result. #1 ADCMPDR0 A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register 0x9C 16 read-write n 0x0 0x0 ADCMPDR1 A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register 0x9E 16 read-write n 0x0 0x0 ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x93 8 read-write n 0x0 0x0 CMPLOCA Compare Window A Internal Reference Voltage Comparison Condition Select 1 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted valueCompare Window A Temperature Sensor Output Comparison Condition Select When window function is enabled (ADCMPCR.WCMPE = 1) : Compare Window A Temperature Sensor Output Comparison ConditionA/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1) : ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x98 16 read-write n 0x0 0x0 CMPLCHAn Compare Window A Comparison Condition Select 0 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x9A 16 read-write n 0x0 0x0 CMPLCHAn Compare Window A Comparison Condition Select 0 15 read-write 0 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value #0 1 When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value #1 ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0xA4 8 read-write n 0x0 0x0 CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag 1 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag 0 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0xA0 16 read-write n 0x0 0x0 CMPSTCHAn Compare Window A Flag 0 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register1 0xA2 16 read-write n 0x0 0x0 CMPSTCHAn Compare Window A Flag 0 15 read-write 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCSR A/D Control Register 0x0 16 read-write n 0x0 0x0 ADCS Scan Mode Select 13 1 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 ADHSC A/D Conversion Mode Select 10 read-write 0 High-speed A/D conversion mode #0 1 Low-power A/D conversion mode #1 ADST A/D Conversion Start 15 read-write 0 Stop A/D conversion process. #0 1 Start A/D conversion process. #1 DBLANS Double Trigger Channel Select 0 4 read-write DBLE Double Trigger Mode Select 7 read-write 0 Deselect double-trigger mode. #0 1 Select double-trigger mode. #1 EXTRG Trigger Select 8 read-write 0 Start A/D conversion by the synchronous trigger (ELC). #0 1 Start A/D conversion by the asynchronous trigger (ADTRG0). #1 GBADIE Group B Scan End Interrupt and ELC Event Enable 6 read-write 0 Disable ADC120_GBADI interrupt generation on group B scan completion. #0 1 Enable ADC120_GBADI interrupt generation on group B scan completion. #1 TRGE Trigger Start Enable 9 read-write 0 Disable A/D conversion to be started by the synchronous or asynchronous trigger #0 1 Enable A/D conversion to be started by the synchronous or asynchronous trigger #1 ADCTDR A/D CTSU TSCAP Voltage Data Register 0x40 16 read-only n 0x0 0x0 ADCTDR Converted Value 15 to 0 0 15 read-only ADDBLDR A/D Data Duplexing Register 0x18 16 read-only n 0x0 0x0 ADDBLDR Converted Value 15 to 0 0 15 read-only ADDBLDRA A/D Data Duplexing Register A 0x84 16 read-only n 0x0 0x0 ADDBLDRn Converted Value 15 to 0 0 15 read-only ADDBLDRB A/D Data Duplexing Register B 0x86 16 read-only n 0x0 0x0 ADDBLDRn Converted Value 15 to 0 0 15 read-only ADDISCR A/D Disconnection Detection Control Register 0x7A 8 read-write n 0x0 0x0 ADNDIS Disconnection Detection Assist Setting 0 3 read-write Others The number of states for the discharge or precharge period. 0x00 The disconnection detection assist function is disabled 0x00 0x01 Setting prohibited 0x01 PCHG Precharge/discharge select 4 read-write 0 Discharge #0 1 Precharge #1 ADDR0 A/D Data Registers %s 0x20 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR1 A/D Data Registers %s 0x22 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR10 A/D Data Registers %s 0x34 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR17 A/D Data Registers %s 0x42 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR18 A/D Data Registers %s 0x44 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR19 A/D Data Registers %s 0x46 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR2 A/D Data Registers %s 0x24 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR20 A/D Data Registers %s 0x48 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR21 A/D Data Registers %s 0x4A 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR22 A/D Data Registers %s 0x4C 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR3 A/D Data Registers %s 0x26 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR4 A/D Data Registers %s 0x28 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR5 A/D Data Registers %s 0x2A 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR6 A/D Data Registers %s 0x2C 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR7 A/D Data Registers %s 0x2E 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR8 A/D Data Registers %s 0x30 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADDR9 A/D Data Registers %s 0x32 16 read-only n 0x0 0x0 ADDRn Converted Value 15 to 0 0 15 read-only ADEXICR A/D Conversion Extended Input Control Registers 0x12 16 read-write n 0x0 0x0 OCSA Internal Reference Voltage A/D Conversion Select 9 read-write 0 Disable A/D conversion of internal reference voltage #0 1 Enable A/D conversion of internal reference voltage #1 OCSAD Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select 1 read-write 0 Do not select addition/average mode for internal reference voltage. #0 1 Select addition/average mode for internal reference voltage. #1 TSSA Temperature Sensor Output A/D Conversion Select 8 read-write 0 Disable A/D conversion of temperature sensor output #0 1 Enable A/D conversion of temperature sensor output #1 TSSAD Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select 0 read-write 0 Do not select addition/average mode for temperature sensor output. #0 1 Select addition/average mode for temperature sensor output. #1 ADGSPCR A/D Group Scan Priority Control Register 0x80 16 read-write n 0x0 0x0 GBRP Single Scan Continuous Start 15 read-write 0 Single scan is not continuously activated. #0 1 Single scan for the group with the lower-priority is continuously activated. #1 GBRSCN Lower-Priority Group Restart Setting 1 read-write 0 Disable rescanning of the group that was stopped in group priority operation #0 1 Enable rescanning of the group that was stopped in group priority operation. #1 PGS Group Priority Operation Setting 0 read-write 0 Operate without group priority control. #0 1 Operate with group priority control. #1 ADHVREFCNT A/D High-Potential/Low-Potential Reference Voltage Control Register 0x8A 8 read-write n 0x0 0x0 ADSLP Sleep 7 read-write 0 Normal operation #0 1 Standby state #1 HVSEL High-Potential Reference Voltage Select 0 1 read-write 00 AVCC0 is selected as the high-potential reference voltage #00 01 VREFH0 is selected as the high-potential reference voltage #01 10 Internal reference voltage is selected as the high-potential reference voltage #10 11 No reference voltage pin is selected (internal node discharge) #11 LVSEL Low-Potential Reference Voltage Select 4 read-write 0 AVSS0 is selected as the low-potential reference voltage. #0 1 VREFL0 is selected as the low-potential reference voltage. #1 ADOCDR A/D Internal Reference Voltage Data Register 0x1C 16 read-only n 0x0 0x0 ADOCDR Converted Value 15 to 0 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x1E 16 read-only n 0x0 0x0 AD Converted Value 11 to 0 0 11 read-only DIAGST Self-Diagnosis Status 14 1 read-only 00 Self-diagnosis not executed after power-on. #00 01 Self-diagnosis was executed using the 0 V voltage. #01 10 Self-diagnosis was executed using the reference power supply voltage x 1/2. #10 11 Self-diagnosis was executed using the reference power supply voltage. #11 ADSSTR0 A/D Sampling State Register 0xE0 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR1 A/D Sampling State Register 0xE1 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR10 A/D Sampling State Register 0xEA 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR2 A/D Sampling State Register 0xE2 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR3 A/D Sampling State Register 0xE3 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR4 A/D Sampling State Register 0xE4 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR5 A/D Sampling State Register 0xE5 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR6 A/D Sampling State Register 0xE6 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR7 A/D Sampling State Register 0xE7 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR8 A/D Sampling State Register 0xE8 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTR9 A/D Sampling State Register 0xE9 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTRL A/D Sampling State Register 0xDD 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTRO A/D Sampling State Register 0xDF 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSSTRT A/D Sampling State Register 0xDE 8 read-write n 0x0 0x0 SST Sampling Time Setting 0 7 read-write ADSTRGR A/D Conversion Start Trigger Select Register 0x10 16 read-write n 0x0 0x0 TRSA A/D Conversion Start Trigger Select 8 5 read-write TRSB A/D Conversion Start Trigger Select for Group B 0 5 read-write ADTSDR A/D Temperature Sensor Data Register 0x1A 16 read-only n 0x0 0x0 ADTSDR Converted Value 15 to 0 0 15 read-only ADWINLLB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0xA8 16 read-write n 0x0 0x0 ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x8C 8 read-only n 0x0 0x0 MONCMPA Comparison Result Monitor A 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCMPB Comparison Result Monitor B 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 MONCOMB Combination Result Monitor 0 read-only 0 Window A/B composite conditions are not met. #0 1 Window A/B composite conditions are met. #1 ADWINULB A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register 0xAA 16 read-write n 0x0 0x0 AGT0 Low Power Asynchronous General Purpose Timer 0 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 TCMEA AGT Compare Match A Register Enable 0 read-write 0 AGT Compare match A register disabled #0 1 AGT Compare match A register enabled #1 TCMEB AGT Compare Match B Register Enable 4 read-write 0 Compare match B register disabled #0 1 Compare match B register enabled #1 TOEA AGTOAn Pin Output Enable 1 read-write 0 AGTOAn pin output disabled #0 1 AGTOAn pin output enabled #1 TOEB AGTOBn Pin Output Enable 5 read-write 0 AGTOBn pin output disabled #0 1 AGTOBn pin output enabled #1 TOPOLA AGTOAn Pin Polarity Select 2 read-write 0 AGTOAn pin output is started on low. i.e. normal output #0 1 AGTOAn pin output is started on high. i.e. inverted output #1 TOPOLB AGTOBn Pin Polarity Select 6 read-write 0 AGTOBn pin output is started on low. i.e. normal output #0 1 AGTOBn pin output is started on high. i.e. inverted output #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 TCMAF Compare Match A Flag 6 read-write 0 No match #0 1 Match #1 TCMBF Compare Match B Flag 7 read-write 0 No match #0 1 Match #1 TCSTF AGT Count Status Flag 1 read-only 0 Count stopped #0 1 Count in progress #1 TEDGF Active Edge Judgment Flag 4 read-write 0 No active edge received #0 1 Active edge received #1 TSTART AGT Count Start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT Count Forced Stop 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped #1 TUNDF Underflow Flag 5 read-write 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 TEDGSEL I/O Polarity Switch 0 read-write TIOGT Count Control 6 1 read-write Others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn pin #01 TIPF Input Filter 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTOn pin Output Enable 2 read-write 0 AGTOn pin output disabled #0 1 AGTOn pin output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 SEL AGTIOn Pin Select 0 1 read-write 00 Select the AGTIOn except for the following pins #00 01 Setting prohibited #01 10 Select the P402/AGTIOn P402/AGTIOn as input only. It cannot be used for output. #10 11 Select the P403/AGTIOn P403/AGTIOn as input only. It cannot be used for output. #11 TIES AGTIOn Pin Input Enable 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEEn Polarity Selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 TCK Count Source 4 2 read-write Others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGT0 #101 110 Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register #110 TEDGPL Edge Polarity 3 read-write 0 Single-edge #0 1 Both-edge #1 TMOD Operating Mode 0 2 read-write Others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM Low Power Mode 7 read-write 0 Normal mode #0 1 Low power mode #1 AGT1 Low Power Asynchronous General Purpose Timer 1 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 TCMEA AGT Compare Match A Register Enable 0 read-write 0 AGT Compare match A register disabled #0 1 AGT Compare match A register enabled #1 TCMEB AGT Compare Match B Register Enable 4 read-write 0 Compare match B register disabled #0 1 Compare match B register enabled #1 TOEA AGTOAn Pin Output Enable 1 read-write 0 AGTOAn pin output disabled #0 1 AGTOAn pin output enabled #1 TOEB AGTOBn Pin Output Enable 5 read-write 0 AGTOBn pin output disabled #0 1 AGTOBn pin output enabled #1 TOPOLA AGTOAn Pin Polarity Select 2 read-write 0 AGTOAn pin output is started on low. i.e. normal output #0 1 AGTOAn pin output is started on high. i.e. inverted output #1 TOPOLB AGTOBn Pin Polarity Select 6 read-write 0 AGTOBn pin output is started on low. i.e. normal output #0 1 AGTOBn pin output is started on high. i.e. inverted output #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 TCMAF Compare Match A Flag 6 read-write 0 No match #0 1 Match #1 TCMBF Compare Match B Flag 7 read-write 0 No match #0 1 Match #1 TCSTF AGT Count Status Flag 1 read-only 0 Count stopped #0 1 Count in progress #1 TEDGF Active Edge Judgment Flag 4 read-write 0 No active edge received #0 1 Active edge received #1 TSTART AGT Count Start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT Count Forced Stop 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped #1 TUNDF Underflow Flag 5 read-write 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 TEDGSEL I/O Polarity Switch 0 read-write TIOGT Count Control 6 1 read-write Others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn pin #01 TIPF Input Filter 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTOn pin Output Enable 2 read-write 0 AGTOn pin output disabled #0 1 AGTOn pin output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 SEL AGTIOn Pin Select 0 1 read-write 00 Select the AGTIOn except for the following pins #00 01 Setting prohibited #01 10 Select the P402/AGTIOn P402/AGTIOn as input only. It cannot be used for output. #10 11 Select the P403/AGTIOn P403/AGTIOn as input only. It cannot be used for output. #11 TIES AGTIOn Pin Input Enable 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEEn Polarity Selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 TCK Count Source 4 2 read-write Others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGT0 #101 110 Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register #110 TEDGPL Edge Polarity 3 read-write 0 Single-edge #0 1 Both-edge #1 TMOD Operating Mode 0 2 read-write Others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM Low Power Mode 7 read-write 0 Normal mode #0 1 Low power mode #1 BUS BUS Control BUS 0x0 0x1008 0x2 registers n 0x100C 0x2 registers n 0x1820 0x5 registers n 0x1830 0x5 registers n BUS3ERRADD Bus Error Address Register 3 0x1820 32 read-only n 0x0 0x0 BERAD Bus Error Address 0 31 read-only BUS3ERRSTAT BUS Error Status Register 3 0x1824 8 read-only n 0x0 0x0 ACCSTAT Error Access Status 0 read-only 0 Read access #0 1 Write access #1 ERRSTAT Bus Error Status 7 read-only 0 No bus error occurred. #0 1 Bus error occurred. #1 BUS4ERRADD Bus Error Address Register 4 0x1830 32 read-only n 0x0 0x0 BERAD Bus Error Address 0 31 read-only BUS4ERRSTAT BUS Error Status Register 4 0x1834 8 read-only n 0x0 0x0 ACCSTAT Error Access Status 0 read-only 0 Read access #0 1 Write access #1 ERRSTAT Bus Error Status 7 read-only 0 No bus error occurred. #0 1 Bus error occurred. #1 BUSMCNTDMA Master Bus Control Register DMA 0x100C 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 A bus error is reported. #0 1 A bus error is not reported. #1 BUSMCNTSYS Master Bus Control Register SYS 0x1008 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 A bus error is reported. #0 1 A bus error is not reported. #1 CAC Clock Frequency Accuracy Measurement Circuit CAC 0x0 0x0 0x5 registers n 0x6 0x6 registers n CACNTBR CAC Counter Buffer Register 0xA 16 read-only n 0x0 0x0 CACR0 CAC Control Register 0 0x0 8 read-write n 0x0 0x0 CFME Clock Frequency Measurement Enable 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x1 8 read-write n 0x0 0x0 CACREFE CACREF Pin Input Enable 0 read-write 0 Disable #0 1 Enable #1 EDGES Valid Edge Select 6 1 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 FMCS Measurement Target Clock Select 1 2 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 TCSS Timer Count Clock Source Select 4 1 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 CACR2 CAC Control Register 2 0x2 8 read-write n 0x0 0x0 DFS Digital Filter Select 6 1 read-write 00 Disable digital filtering #00 01 Use sampling clock for the digital filter as the frequency measuring clock #01 10 Use sampling clock for the digital filter as the frequency measuring clock divided by 4 #10 11 Use sampling clock for the digital filter as the frequency measuring clock divided by 16. #11 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 1 read-write 00 x 1/32 clock #00 01 x 1/128 clock #01 10 x 1/1024 clock #10 11 x 1/8192 clock #11 RPS Reference Signal Select 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 RSCS Measurement Reference Clock Select 1 2 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO #011 100 LOCO clock #100 101 Peripheral module clock B (PCLKB) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 CAICR CAC Interrupt Control Register 0x3 8 read-write n 0x0 0x0 FERRFCL FERRF Clear 4 write-only 0 No effect #0 1 The CASTR.FERRF flag is cleared #1 FERRIE Frequency Error Interrupt Request Enable 0 read-write 0 Disable #0 1 Enable #1 MENDFCL MENDF Clear 5 write-only 0 No effect #0 1 The CASTR.MENDF flag is cleared #1 MENDIE Measurement End Interrupt Request Enable 1 read-write 0 Disable #0 1 Enable #1 OVFFCL OVFF Clear 6 write-only 0 No effect #0 1 The CASTR.OVFF flag is cleared. #1 OVFIE Overflow Interrupt Request Enable 2 read-write 0 Disable #0 1 Enable #1 CALLVR CAC Lower-Limit Value Setting Register 0x8 16 read-write n 0x0 0x0 CASTR CAC Status Register 0x4 8 read-only n 0x0 0x0 FERRF Frequency Error Flag 0 read-only 0 Clock frequency is within the allowable range #0 1 Clock frequency has deviated beyond the allowable range (frequency error). #1 MENDF Measurement End Flag 1 read-only 0 Measurement is in progress #0 1 Measurement ended #1 OVFF Overflow Flag 2 read-only 0 Counter has not overflowed #0 1 Counter overflowed #1 CAULVR CAC Upper-Limit Value Setting Register 0x6 16 read-write n 0x0 0x0 CRC Cyclic Redundancy Check Calculator CRC 0x0 0x0 0x2 registers n 0x4 0x4 registers n 0x8 0x4 registers n 0xC 0x2 registers n CRCCR0 CRC Control Register 0 0x0 8 read-write n 0x0 0x0 DORCLR CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear 7 write-only 0 No effect #0 1 Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register #1 GPS CRC Generating Polynomial Switching 0 2 read-write Others No calculation is executed 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1) #100 101 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1) #101 LMS CRC Calculation Switching 6 read-write 0 Generate CRC code for LSB-first communication #0 1 Generate CRC code for MSB-first communication #1 CRCCR1 CRC Control Register 1 0x1 8 read-write n 0x0 0x0 CRCSEN Snoop Enable 7 read-write 0 Disabled #0 1 Enabled #1 CRCSWR Snoop-On-Write/Read Switch 6 read-write 0 Snoop-on-read #0 1 Snoop-on-write #1 CRCDIR CRC Data Input Register 0x4 32 read-write n 0x0 0x0 CRCDIR_BY CRC Data Input Register CRCDIR 0x4 8 read-write n 0x0 0x0 CRCDOR CRC Data Output Register 0x8 32 read-write n 0x0 0x0 CRCDOR_BY CRC Data Output Register CRCDOR 0x8 8 read-write n 0x0 0x0 CRCDOR_HA CRC Data Output Register CRCDOR 0x8 16 read-write n 0x0 0x0 CRCSAR Snoop Address Register 0xC 16 read-write n 0x0 0x0 CRCSA Register Snoop Address 0 13 read-write CTSU Capacitive Touch Sensing Unit CTSU 0x0 0x0 0xC registers n 0x14 0x8 registers n 0x1C 0x4 registers n 0x20 0x8 registers n 0x28 0x10 registers n 0xC 0x8 registers n CTSUCALIB CTSU Calibration Register 0x28 32 read-write n 0x0 0x0 CCOCALIB CTSU CCO Calibration Mode Select 30 read-write 0 Normal mode #0 1 Oscillator calibration mode #1 CCOCLK CTSU CCO Modulation Circuit Clock Select 29 read-write 0 Divided PCLK specified by CTSUCRA.CLK[1:0] bits #0 1 SUCLK #1 CFCMODE CTSU CFC Current Source Switching 22 read-write 0 CFC current measurement (normal mode) #0 1 External current measurement for calibration #1 CFCRDMD CTSU CFC Counter Read Mode Select 10 read-write 0 Read by DTC #0 1 Read by CPU #1 DACCARRY CTSU DAC Upper Current Source Carry Control 25 read-write 0 Do not carry #0 1 Carry #1 DACCLK CTSU DAC Modulation Circuit Clock Select 28 read-write 0 Divided PCLK specified by CTSUCRA.CLK[1:0] bits #0 1 SUCLK #1 DCOFF CTSU Down Converter Control 11 read-write 0 Normal operation mode #0 1 The down converter is off. #1 DRV CTSU Calibration Setting Bit 1 3 read-write 0 Electrostatic capacitance measurement mode #0 1 Calibration setting 1 #1 IOC CTSU Transfer Pins Control 9 read-write 0 Low level #0 1 High level #1 SUCARRY CTSU CCO Carry Control 27 read-write 0 Do not carry #0 1 Carry #1 SUCLKEN CTSU SUCLK Enable Control 6 read-write 0 SUCLK operation is disabled. #0 1 SUCLK operation is enabled. #1 TSOC CTSU Calibration Setting Bit 2 7 read-write 0 Electrostatic capacitance measurement mode #0 1 Calibration setting 2 #1 TSOD CTSU TS Pins Fixed Output Select 2 read-write 0 Electrostatic capacitance measurement mode #0 1 TS pins fix output (High output/Low output). #1 CTSUCFCCNT CTSU CFC Counter Register 0x34 32 read-only n 0x0 0x0 CFCCNT CTSU CFC Counter 0 15 read-only CTSUCFCCNTL CTSU CFC Counter Register CTSUCFCCNT 0x34 16 read-only n 0x0 0x0 CTSUCHAC0 CTSU Channel Enable Control Register A CTSUCHACA 0xC 8 read-write n 0x0 0x0 CTSUCHAC1 CTSU Channel Enable Control Register A CTSUCHACA 0xD 8 read-write n 0x0 0x0 CTSUCHAC2 CTSU Channel Enable Control Register A CTSUCHACAH 0xE 8 read-write n 0x0 0x0 CTSUCHAC3 CTSU Channel Enable Control Register A CTSUCHACA 0xF 8 read-write n 0x0 0x0 CTSUCHAC4 CTSU Channel Enable Control Register B CTSUCHACB 0x10 8 read-write n 0x0 0x0 CTSUCHACA CTSU Channel Enable Control Register A 0xC 32 read-write n 0x0 0x0 CHAC00 CTSU Channel Enable Control A 0 read-write 0 Do not measure. #0 1 Measure. #1 CHAC02 CTSU Channel Enable Control A 2 read-write 0 Do not measure. #0 1 Measure. #1 CHAC04 CTSU Channel Enable Control A 4 read-write 0 Do not measure. #0 1 Measure. #1 CHAC05 CTSU Channel Enable Control A 5 read-write 0 Do not measure. #0 1 Measure. #1 CHAC06 CTSU Channel Enable Control A 6 read-write 0 Do not measure. #0 1 Measure. #1 CHAC07 CTSU Channel Enable Control A 7 read-write 0 Do not measure. #0 1 Measure. #1 CHAC08 CTSU Channel Enable Control A 8 read-write 0 Do not measure. #0 1 Measure. #1 CHAC09 CTSU Channel Enable Control A 9 read-write 0 Do not measure. #0 1 Measure. #1 CHAC10 CTSU Channel Enable Control A 10 read-write 0 Do not measure. #0 1 Measure. #1 CHAC11 CTSU Channel Enable Control A 11 read-write 0 Do not measure. #0 1 Measure. #1 CHAC12 CTSU Channel Enable Control A 12 read-write 0 Do not measure. #0 1 Measure. #1 CHAC13 CTSU Channel Enable Control A 13 read-write 0 Do not measure. #0 1 Measure. #1 CHAC14 CTSU Channel Enable Control A 14 read-write 0 Do not measure. #0 1 Measure. #1 CHAC15 CTSU Channel Enable Control A 15 read-write 0 Do not measure. #0 1 Measure. #1 CHAC16 CTSU Channel Enable Control A 16 read-write 0 Do not measure. #0 1 Measure. #1 CHAC17 CTSU Channel Enable Control A 17 read-write 0 Do not measure. #0 1 Measure. #1 CHAC18 CTSU Channel Enable Control A 18 read-write 0 Do not measure. #0 1 Measure. #1 CHAC21 CTSU Channel Enable Control A 21 read-write 0 Do not measure. #0 1 Measure. #1 CHAC22 CTSU Channel Enable Control A 22 read-write 0 Do not measure. #0 1 Measure. #1 CHAC23 CTSU Channel Enable Control A 23 read-write 0 Do not measure. #0 1 Measure. #1 CHAC24 CTSU Channel Enable Control A 24 read-write 0 Do not measure. #0 1 Measure. #1 CHAC25 CTSU Channel Enable Control A 25 read-write 0 Do not measure. #0 1 Measure. #1 CHAC26 CTSU Channel Enable Control A 26 read-write 0 Do not measure. #0 1 Measure. #1 CHAC27 CTSU Channel Enable Control A 27 read-write 0 Do not measure. #0 1 Measure. #1 CHAC28 CTSU Channel Enable Control A 28 read-write 0 Do not measure. #0 1 Measure. #1 CHAC30 CTSU Channel Enable Control A 30 read-write 0 Do not measure. #0 1 Measure. #1 CHAC31 CTSU Channel Enable Control A 31 read-write 0 Do not measure. #0 1 Measure. #1 CTSUCHACAH CTSU Channel Enable Control Register A CTSUCHACA 0xE 16 read-write n 0x0 0x0 CTSUCHACAL CTSU Channel Enable Control Register A CTSUCHACA 0xC 16 read-write n 0x0 0x0 CTSUCHACB CTSU Channel Enable Control Register B 0x10 32 read-write n 0x0 0x0 CHAC32 CTSU Channel Enable Control B 0 read-write 0 Do not measure. #0 1 Measure. #1 CHAC33 CTSU Channel Enable Control B 1 read-write 0 Do not measure. #0 1 Measure. #1 CHAC34 CTSU Channel Enable Control B 2 read-write 0 Do not measure. #0 1 Measure. #1 CTSUCHACBL CTSU Channel Enable Control Register B CTSUCHACB 0x10 16 read-write n 0x0 0x0 CTSUCHTRC0 CTSU Channel Transmit/Receive Control Register A CTSUCHTRCA 0x14 8 read-write n 0x0 0x0 CTSUCHTRC1 CTSU Channel Transmit/Receive Control Register A CTSUCHTRCA 0x15 8 read-write n 0x0 0x0 CTSUCHTRC2 CTSU Channel Transmit/Receive Control Register A CTSUCHTRCAH 0x16 8 read-write n 0x0 0x0 CTSUCHTRC3 CTSU Channel Transmit/Receive Control Register A CTSUCHTRCA 0x17 8 read-write n 0x0 0x0 CTSUCHTRC4 CTSU Channel Transmit/Receive Control Register B CTSUCHTRCB 0x18 8 read-write n 0x0 0x0 CTSUCHTRCA CTSU Channel Transmit/Receive Control Register A 0x14 32 read-write n 0x0 0x0 CHTRC00 CTSU Channel Transmit/Receive Control A 0 read-write 0 Reception #0 1 Transmission #1 CHTRC02 CTSU Channel Transmit/Receive Control A 2 read-write 0 Reception #0 1 Transmission #1 CHTRC04 CTSU Channel Transmit/Receive Control A 4 read-write 0 Reception #0 1 Transmission #1 CHTRC05 CTSU Channel Transmit/Receive Control A 5 read-write 0 Reception #0 1 Transmission #1 CHTRC06 CTSU Channel Transmit/Receive Control A 6 read-write 0 Reception #0 1 Transmission #1 CHTRC07 CTSU Channel Transmit/Receive Control A 7 read-write 0 Reception #0 1 Transmission #1 CHTRC08 CTSU Channel Transmit/Receive Control A 8 read-write 0 Reception #0 1 Transmission #1 CHTRC09 CTSU Channel Transmit/Receive Control A 9 read-write 0 Reception #0 1 Transmission #1 CHTRC10 CTSU Channel Transmit/Receive Control A 10 read-write 0 Reception #0 1 Transmission #1 CHTRC11 CTSU Channel Transmit/Receive Control A 11 read-write 0 Reception #0 1 Transmission #1 CHTRC12 CTSU Channel Transmit/Receive Control A 12 read-write 0 Reception #0 1 Transmission #1 CHTRC13 CTSU Channel Transmit/Receive Control A 13 read-write 0 Reception #0 1 Transmission #1 CHTRC14 CTSU Channel Transmit/Receive Control A 14 read-write 0 Reception #0 1 Transmission #1 CHTRC15 CTSU Channel Transmit/Receive Control A 15 read-write 0 Reception #0 1 Transmission #1 CHTRC16 CTSU Channel Transmit/Receive Control A 16 read-write 0 Reception #0 1 Transmission #1 CHTRC17 CTSU Channel Transmit/Receive Control A 17 read-write 0 Reception #0 1 Transmission #1 CHTRC18 CTSU Channel Transmit/Receive Control A 18 read-write 0 Reception #0 1 Transmission #1 CHTRC21 CTSU Channel Transmit/Receive Control A 21 read-write 0 Reception #0 1 Transmission #1 CHTRC22 CTSU Channel Transmit/Receive Control A 22 read-write 0 Reception #0 1 Transmission #1 CHTRC23 CTSU Channel Transmit/Receive Control A 23 read-write 0 Reception #0 1 Transmission #1 CHTRC24 CTSU Channel Transmit/Receive Control A 24 read-write 0 Reception #0 1 Transmission #1 CHTRC25 CTSU Channel Transmit/Receive Control A 25 read-write 0 Reception #0 1 Transmission #1 CHTRC26 CTSU Channel Transmit/Receive Control A 26 read-write 0 Reception #0 1 Transmission #1 CHTRC27 CTSU Channel Transmit/Receive Control A 27 read-write 0 Reception #0 1 Transmission #1 CHTRC28 CTSU Channel Transmit/Receive Control A 28 read-write 0 Reception #0 1 Transmission #1 CHTRC30 CTSU Channel Transmit/Receive Control A 30 read-write 0 Reception #0 1 Transmission #1 CHTRC31 CTSU Channel Transmit/Receive Control A 31 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRCAH CTSU Channel Transmit/Receive Control Register A CTSUCHTRCA 0x16 16 read-write n 0x0 0x0 CTSUCHTRCAL CTSU Channel Transmit/Receive Control Register A CTSUCHTRCA 0x14 16 read-write n 0x0 0x0 CTSUCHTRCB CTSU Channel Transmit/Receive Control Register B 0x18 32 read-write n 0x0 0x0 CHTRC32 CTSU Channel Transmit/Receive Control B 0 read-write 0 Reception #0 1 Transmission #1 CHTRC33 CTSU Channel Transmit/Receive Control B 1 read-write 0 Reception #0 1 Transmission #1 CHTRC34 CTSU Channel Transmit/Receive Control B 2 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRCBL CTSU Channel Transmit/Receive Control Register B CTSUCHTRCB 0x18 16 read-write n 0x0 0x0 CTSUCR0 CTSU Control Register A CTSUCRA 0x0 8 read-write n 0x0 0x0 CTSUCR1 CTSU Control Register A CTSUCRA 0x1 8 read-write n 0x0 0x0 CTSUCR2 CTSU Control Register A CTSUCRAH 0x2 8 read-write n 0x0 0x0 CTSUCR3 CTSU Control Register A CTSUCRA 0x3 8 read-write n 0x0 0x0 CTSUCRA CTSU Control Register A 0x0 32 read-write n 0x0 0x0 ATUNE0 CTSU Power Supply Operating Mode Setting 10 read-write 0 VCC ≥ 2.4 V: Normal operating mode VCC < 2.4 V: Setting prohibited #0 1 Low-voltage operating mode #1 ATUNE1 CTSU Current Range Adjustment 11 read-write 0 40 µA when CTSUATUNE2 = 0 20 µA when CTSUATUNE2 = 1 #0 1 80 µA when CTSUATUNE2 = 0 160 µA when CTSUATUNE2 = 1 #1 ATUNE2 CTSU Current Range Adjustment 17 read-write 0 40 µA when CTSUATUNE1 = 0 80 µA when CTSUATUNE2 = 1 #0 1 20 µA when CTSUATUNE1 = 0 160 µA when CTSUATUNE2 = 1 #1 CAP CTSU Measurement Operation Start Trigger Select 1 read-write 0 Software trigger #0 1 External trigger #1 CFCON CTSU CFC Power on Control 3 read-write 0 CFC power off #0 1 CFC power on #1 CLK CTSU Operating Clock Select 12 1 read-write 00 PCLKB #00 01 PCLKB/2 (PCLKB divided by 2) #01 10 PCLKB/4 (PCLKB divided by 4) #10 11 PCLKB/8 (PCLKB divided by 8) #11 CSW CTSU LPF Capacitance Charging Control 9 read-write 0 Turn off capacitance switch #0 1 Turn on capacitance switch #1 DCBACK CTSU Current Measurement Feedback Select 31 read-write 0 TSCAP pin is selected #0 1 Measurement pin is selected #1 DCMODE CTSU Current Measurement Mode Select 30 read-write 0 Normal mode #0 1 Current measurement mode #1 FCMODE CTSU SUCLK Control 23 read-write 0 SUCLK is used as frequency diffusion clock #0 1 SUCLK is used as recovery clock for multi-clock measurement #1 INIT CTSU Control Block Initialization 4 write-only LOAD CTSU Measurement Load Control 18 1 read-write 00 Normal measurement mode #00 01 Load off mode #01 10 Current load mode #10 11 Resistance load mode #11 MD0 CTSU Measurement Mode Select 0 14 read-write 0 Single scan mode #0 1 Multi-scan mode #1 MD1 CTSU Measurement Mode Select 1 15 read-write 0 Self-capacitance #0 1 Mutual capacitance #1 MD2 CTSU Measurement Mode Select 2 16 read-write 0 Measure the current that flows through the switched capacitor. #0 1 Measure the transfer charge in CFC circuit (high speed measurement) #1 PON CTSU Power Supply Enable 8 read-write 0 Power off the CTSU #0 1 Power on the CTSU #1 POSEL CTSU Non-measured Channel Output Select 20 1 read-write 00 Output low through GPIO #00 01 Hi-Z #01 10 Output low through the power setting in the TXVSEL[1:0] bits #10 11 Same phase pulse output as transmission channel through the power setting in the TXVSEL[1:0] bits #11 PUMPON CTSU Boost Circuit Control 5 read-write 0 Boost circuit off #0 1 Boost circuit on #1 SDPSEL CTSU Sensor Drive Pulse Select 22 read-write 0 Random pulse mode #0 1 High resolution pulse mode #1 SNZ CTSU Wait State Power-Saving Enable 2 read-write 0 Disable power-saving function during wait state #0 1 Enable power-saving function during wait state #1 STCLK CTSU STCLK Select 24 5 read-write STRT CTSU Measurement Operation Start 0 read-write 0 Stop measurement operation #0 1 Start measurement operation #1 TXVSEL CTSU Transmission Power Supply Selection 6 1 read-write 00 VCC is selected as the power supply for the transmit pins in measurement methods other than self-capacitance method. #00 01 VCC is selected as the power supply for the transmit pins in self-capacitance method. #01 10 VCL is selected as the power-supply voltage for the transmit pins. #10 11 Setting prohibited #11 CTSUCRAH CTSU Control Register A CTSUCRA 0x2 16 read-write n 0x0 0x0 CTSUCRAL CTSU Control Register A CTSUCRA 0x0 16 read-write n 0x0 0x0 CTSUCRB CTSU Control Register B 0x4 32 read-write n 0x0 0x0 PRMODE CTSU Base Period and Pulse Count Setting 4 1 read-write 00 510 pulses (512 pulses when PROFF bit is 1) #00 01 126 pulses (128 pulses when PROFF bit is 1) #01 10 62 pulses (recommended setting) (64 pulses when PROFF bit is 1) #10 11 Setting prohibited #11 PROFF CTSU Random Number Off Control 7 read-write 0 There is random number control. #0 1 There is no random number control. #1 PRRATIO CTSU Measurement Time and Pulse Count Adjustment 0 3 read-write SOFF CTSU High-Pass Noise Reduction Function Off Setting 6 read-write 0 Turn spectrum diffusion on. #0 1 Turn spectrum diffusion off. #1 SSCNT CTSU SUCLK Diffusion Control 28 1 read-write SSMOD CTSU SUCLK Diffusion Mode Select 24 2 read-write SST CTSU Sensor Stabilization Wait Control 8 7 read-write CTSUCRBH CTSU Control Register B CTSUCRB 0x6 16 read-write n 0x0 0x0 CTSUCRBL CTSU Control Register B CTSUCRB 0x4 16 read-write n 0x0 0x0 CTSUDBGR0 CTSU Calibration Register CTSUCALIB 0x28 16 read-write n 0x0 0x0 CTSUDBGR1 CTSU Calibration Register CTSUCALIB 0x2A 16 read-write n 0x0 0x0 CTSUDCLKC CTSU Control Register B CTSUCRB 0x7 8 read-write n 0x0 0x0 CTSUMCH CTSU Measurement Channel Register 0x8 32 read-write n 0x0 0x0 MCA0 CTSU Multiple Valid Clock Control 16 read-write 0 Valid #0 1 Invalid #1 MCA1 CTSU Multiple Valid Clock Control 17 read-write 0 Valid #0 1 Invalid #1 MCA2 CTSU Multiple Valid Clock Control 18 read-write 0 Valid #0 1 Invalid #1 MCA3 CTSU Multiple Valid Clock Control 19 read-write 0 Valid #0 1 Invalid #1 MCH0 CTSU Measurement Channel 0 0 5 read-write 0x00 TS00 0x00 0x02 TS02 0x02 0x04 TS04 0x04 0x05 TS05 0x05 0x06 TS06 0x06 0x07 TS07 0x07 0x08 TS08 0x08 0x09 TS09 0x09 0x0A TS10 0x0a 0x0B TS11 0x0b 0x0C TS12 0x0c 0x0D TS13 0x0d 0x0E TS14 0x0e 0x0F TS15 0x0f 0x10 TS16 0x10 0x11 TS17 0x11 0x12 TS18 0x12 0x15 TS21 0x15 0x16 TS22 0x16 0x17 TS23 0x17 0x18 TS24 0x18 0x19 TS25 0x19 0x1A TS26 0x1a 0x1B TS27 0x1b 0x1C TS28 0x1c 0x1E TS30 0x1e 0x1F TS31 0x1f 0x20 TS32 0x20 0x21 TS33 0x21 0x22 TS34 0x22 0x3F Measurement is being stopped. 0x3f MCH1 CTSU Measurement Channel 1 8 5 read-write 0x00 TS00 0x00 0x02 TS02 0x02 0x04 TS04 0x04 0x05 TS05 0x05 0x06 TS06 0x06 0x07 TS07 0x07 0x08 TS08 0x08 0x09 TS09 0x09 0x0A TS10 0x0a 0x0B TS11 0x0b 0x0C TS12 0x0c 0x0D TS13 0x0d 0x0E TS14 0x0e 0x0F TS15 0x0f 0x10 TS16 0x10 0x11 TS17 0x11 0x12 TS18 0x12 0x15 TS21 0x15 0x16 TS22 0x16 0x17 TS23 0x17 0x18 TS24 0x18 0x19 TS25 0x19 0x1A TS26 0x1a 0x1B TS27 0x1b 0x1C TS28 0x1c 0x1E TS30 0x1e 0x1F TS31 0x1f 0x20 TS32 0x20 0x21 TS33 0x21 0x22 TS34 0x22 0x3F Measurement is being stopped. 0x3f CTSUMCH0 CTSU Measurement Channel Register CTSUMCH 0x8 8 read-write n 0x0 0x0 CTSUMCH1 CTSU Measurement Channel Register CTSUMCH 0x9 8 read-write n 0x0 0x0 CTSUMCHH CTSU Measurement Channel Register CTSUMCH 0xA 16 read-write n 0x0 0x0 CTSUMCHL CTSU Measurement Channel Register CTSUMCH 0x8 16 read-write n 0x0 0x0 CTSUMFAF CTSU Measurement Channel Register CTSUMCHH 0xA 8 read-write n 0x0 0x0 CTSUSC CTSU Sensor Counter Register CTSUSCNT 0x24 16 read-only n 0x0 0x0 CTSUSCNT CTSU Sensor Counter Register 0x24 32 read-only n 0x0 0x0 SENSCNT CTSU Sensor Counter 0 15 read-only CTSUSDPRS CTSU Control Register B CTSUCRB 0x4 8 read-write n 0x0 0x0 CTSUSO CTSU Sensor Offset Register 0x20 32 read-write n 0x0 0x0 SDPA CTSU Base Clock Setting 24 7 read-write SNUM CTSU Measurement Count Setting 10 7 read-write SO CTSU Sensor Offset Adjustment 0 9 read-write SSDIV CTSU Spectrum Diffusion Frequency Division Setting 20 3 read-write CTSUSO0 CTSU Sensor Offset Register CTSUSO 0x20 16 read-write n 0x0 0x0 CTSUSO1 CTSU Sensor Offset Register CTSUSO 0x22 16 read-write n 0x0 0x0 CTSUSR CTSU Status Register 0x1C 32 read-write n 0x0 0x0 CFCRDCH CTSU CFC Read Channel Select 16 5 read-write 0x00 TS00 0x00 0x02 TS02 (CFC) 0x02 0x04 TS04 0x04 0x05 TS05 0x05 0x06 TS06 0x06 0x07 TS07 0x07 0x08 TS08 (CFC) 0x08 0x09 TS09 (CFC) 0x09 0x0A TS10 (CFC) 0x0a 0x0B TS11 (CFC) 0x0b 0x0C TS12 (CFC) 0x0c 0x0D TS13 (CFC) 0x0d 0x0E TS14 (CFC) 0x0e 0x0F TS15 (CFC) 0x0f 0x10 TS16 (CFC) 0x10 0x11 TS17 0x11 0x12 TS18 0x12 0x15 TS21 0x15 0x16 TS22 0x16 0x17 TS23 0x17 0x18 TS24 0x18 0x19 TS25 0x19 0x1A TS26 (CFC) 0x1a 0x1B TS27 (CFC) 0x1b 0x1C TS28 (CFC) 0x1c 0x1E TS30 (CFC) 0x1e 0x1F TS31 (CFC) 0x1f 0x20 TS32 (CFC) 0x20 0x21 TS33 (CFC) 0x21 0x22 TS34 (CFC) 0x22 DTSR CTSU Data Transfer Status Flag 12 read-only 0 Read #0 1 Not read #1 ICOMP0 TSCAP Voltage Error Monitor 7 read-only 0 Normal TSCAP voltage #0 1 Abnormal TSCAP voltage #1 ICOMP1 CTSU Sense Current Error Monitor 6 read-only 0 Normal sensor current #0 1 Abnormal sensor current #1 ICOMPRST CTSU CTSUICOMP1 Flag Reset 5 write-only MFC CTSU Multi-clock Counter 0 1 read-write 00 Multi-clock 0 #00 01 Multi-clock 1 #01 10 Multi-clock 2 #10 11 Multi-clock 3 #11 PS CTSU Mutual Capacitance Status Flag 15 read-only 0 First measurement #0 1 Second measurement #1 SENSOVF CTSU Sensor Counter Overflow Flag 13 read-write 0 No overflow occurred #0 1 Overflow occurred #1 STC CTSU Measurement Status Counter 8 2 read-only 000 Status 0 #000 001 Status 1 #001 010 Status 2 #010 011 Status 3 #011 100 Status 4 #100 101 Status 5 #101 CTSUSR0 CTSU Status Register CTSUSR 0x1C 8 read-write n 0x0 0x0 CTSUSR2 CTSU Status Register CTSUSRH 0x1E 8 read-write n 0x0 0x0 CTSUSRH CTSU Status Register CTSUSR 0x1E 16 read-write n 0x0 0x0 CTSUSRL CTSU Status Register CTSUSR 0x1C 16 read-write n 0x0 0x0 CTSUSST CTSU Control Register B CTSUCRB 0x5 8 read-write n 0x0 0x0 CTSUST CTSU Status Register CTSUSR 0x1D 8 read-write n 0x0 0x0 CTSUSUCLK0 CTSU Sensor Unit Clock Control Register A CTSUSUCLKA 0x2C 16 read-write n 0x0 0x0 CTSUSUCLK1 CTSU Sensor Unit Clock Control Register A CTSUSUCLKA 0x2E 16 read-write n 0x0 0x0 CTSUSUCLK2 CTSU Sensor Unit Clock Control Register B CTSUSUCLKB 0x30 16 read-write n 0x0 0x0 CTSUSUCLK3 CTSU Sensor Unit Clock Control Register B CTSUSUCLKB 0x32 16 read-write n 0x0 0x0 CTSUSUCLKA CTSU Sensor Unit Clock Control Register A 0x2C 32 read-write n 0x0 0x0 CTSUSUCLKB CTSU Sensor Unit Clock Control Register B 0x30 32 read-write n 0x0 0x0 SUADJ2 CTSU SUCLK Frequency Adjustment 0 7 read-write SUADJ3 CTSU SUCLK Frequency Adjustment 16 7 read-write SUMULTI2 CTSU SUCLK Multiplier Rate Setting 8 7 read-write SUMULTI3 CTSU SUCLK Multiplier Rate Setting 24 7 read-write DAC12 12-bit D/A converter DAC12 0x0 0x0 0x2 registers n 0x4 0x4 registers n DAADSCR D/A A/D Synchronous Start Control Register 0x6 8 read-write n 0x0 0x0 DAADST D/A A/D Synchronous Conversion 7 read-write 0 Do not synchronize DAC12 with ADC12 operation (disable interference reduction between D/A and A/D conversion). #0 1 Synchronize DAC12 with ADC12 operation (enable interference reduction between D/A and A/D conversion). #1 DACR D/A Control Register 0x4 8 read-write n 0x0 0x0 DAOE0 D/A Output Enable 0 6 read-write 0 Disable analog output of channel 0 (DA0) #0 1 Enable D/A conversion of channel 0 (DA0) #1 DADPR DADR0 Format Select Register 0x5 8 read-write n 0x0 0x0 DPSEL DADR0 Format Select 7 read-write 0 Right-justified format #0 1 Left-justified format #1 DADR0 D/A Data Register 0 0x0 16 read-write n 0x0 0x0 DAVREFCR D/A VREF Control Register 0x7 8 read-write n 0x0 0x0 REF D/A Reference Voltage Select 0 read-write 0 No reference voltage selected. #0 1 AVCC0/AVSS0 selected. #1 DBG Debug Function DBG 0x0 0x0 0x4 registers n 0x10 0x4 registers n DBGSTOPCR Debug Stop Control Register 0x10 32 read-write n 0x0 0x0 DBGSTOP_IWDT Mask bit for IWDT reset/interrupt 0 read-write 0 Enable IWDT reset/interrupt #0 1 Mask IWDT reset/interrupt and stop IWDT count when CPU is in OCD break mode #1 DBGSTOP_LVD0 Mask bit for LVD0 reset 16 read-write 0 Enable LVD0 reset #0 1 Mask LVD0 reset #1 DBGSTOP_LVD1 Mask bit for LVD1 reset/interrupt 17 read-write 0 Enable LVD1 reset/interrupt #0 1 Mask LVD1 reset/interrupt #1 DBGSTOP_LVD2 Mask bit for LVD2 reset/interrupt 18 read-write 0 Enable LVD2 reset/interrupt #0 1 Mask LVD2 reset/interrupt #1 DBGSTOP_RPER Mask bit for SRAM parity error reset/interrupt 24 read-write 0 Enable SRAM parity error reset/interrupt #0 1 Mask SRAM parity error reset/interrupt #1 DBGSTOP_WDT Mask bit for WDT reset/interrupt 1 read-write 0 Enable WDT reset/interrupt #0 1 Mask WDT reset/interrupt and stop WDT count when CPU is in OCD break mode #1 DBGSTR Debug Status Register 0x0 32 read-only n 0x0 0x0 CDBGPWRUPACK Debug power-up acknowledge 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 CDBGPWRUPREQ Debug power-up request 28 read-only 0 OCD is not requesting debug power up #0 1 OCD is requesting debug power up #1 DOC Data Operation Circuit DOC 0x0 0x0 0x1 registers n 0x2 0x4 registers n DOCR DOC Control Register 0x0 8 read-write n 0x0 0x0 DCSEL Detection Condition Select 2 read-write 0 Set DOPCF flag when data mismatch is detected #0 1 Set DOPCF flag when data match is detected #1 DOPCF DOC Flag 5 read-only DOPCFCL DOPCF Clear 6 read-write 0 Retain DOPCF flag state #0 1 Clear DOPCF flag #1 OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DODIR DOC Data Input Register 0x2 16 read-write n 0x0 0x0 DODSR DOC Data Setting Register 0x4 16 read-write n 0x0 0x0 DTC Data Transfer Controller DTC 0x0 0x0 0x1 registers n 0x4 0x4 registers n 0xC 0x1 registers n 0xE 0x2 registers n DTCCR DTC Control Register 0x0 8 read-write n 0x0 0x0 RRS DTC Transfer Information Read Skip Enable 4 read-write 0 Transfer information read is not skipped #0 1 Transfer information read is skipped when vector numbers match #1 DTCST DTC Module Start Register 0xC 8 read-write n 0x0 0x0 DTCST DTC Module Start 0 read-write 0 DTC module stopped #0 1 DTC module started #1 DTCSTS DTC Status Register 0xE 16 read-only n 0x0 0x0 ACT DTC Active Flag 15 read-only 0 DTC transfer operation is not in progress #0 1 DTC transfer operation is in progress #1 VECN DTC-Activating Vector Number Monitoring 0 7 read-only DTCVBR DTC Vector Base Register 0x4 32 read-write n 0x0 0x0 ELC Event Link Controller ELC 0x0 0x0 0x1 registers n 0x10 0x10 registers n 0x2 0x4 registers n 0x30 0x8 registers n 0x40 0x2 registers n 0x48 0x8 registers n 0x58 0x2 registers n ELCR Event Link Controller Register 0x0 8 read-write n 0x0 0x0 ELCON All Event Link Enable 7 read-write 0 ELC function is disabled. #0 1 ELC function is enabled. #1 ELSEGR0 Event Link Software Event Generation Register %s 0x2 8 read-write n 0x0 0x0 SEG Software Event Generation 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 read-write 0 Write to SEG bit disabled. #0 1 Write to SEG bit enabled. #1 WI ELSEGR Register Write Disable 7 write-only 0 Write to ELSEGR register enabled. #0 1 Write to ELSEGR register disabled. #1 ELSEGR1 Event Link Software Event Generation Register %s 0x4 8 read-write n 0x0 0x0 SEG Software Event Generation 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 read-write 0 Write to SEG bit disabled. #0 1 Write to SEG bit enabled. #1 WI ELSEGR Register Write Disable 7 write-only 0 Write to ELSEGR register enabled. #0 1 Write to ELSEGR register disabled. #1 ELSR0 Event Link Setting Register %s 0x10 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR1 Event Link Setting Register %s 0x14 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR12 Event Link Setting Register 12 0x40 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR14 Event Link Setting Register %s 0x48 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR15 Event Link Setting Register %s 0x4C 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR18 Event Link Setting Register 18 0x58 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR2 Event Link Setting Register %s 0x18 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR3 Event Link Setting Register %s 0x1C 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR8 Event Link Setting Register %s 0x30 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write ELSR9 Event Link Setting Register %s 0x34 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write FLCN Flash I/O Registers FLCN 0x0 0x100 0x1 registers n 0x104 0x1 registers n 0x110 0x2 registers n 0x114 0x1 registers n 0x118 0x2 registers n 0x120 0x2 registers n 0x124 0x1 registers n 0x128 0x2 registers n 0x12C 0x1 registers n 0x130 0x2 registers n 0x138 0x2 registers n 0x180 0x1 registers n 0x184 0x1 registers n 0x188 0x2 registers n 0x190 0x2 registers n 0x1C0 0x2 registers n 0x1C8 0x2 registers n 0x1D8 0x1 registers n 0x1DC 0x1 registers n 0x1E0 0x2 registers n 0x1E8 0x2 registers n 0x1F0 0x2 registers n 0x3A4 0x4 registers n 0x3FB0 0x2 registers n 0x3FC4 0x1 registers n 0x3FC8 0x1 registers n 0x90 0x1 registers n CTSUTRIMA CTSU Trimming Register A 0x3A4 32 read-write n 0x0 0x0 DACTRIM CTSU Current DAC Matching Coefficient Adjustment 1 8 7 read-write RTRIM CTSU Reference Resistance Adjustment 0 7 read-write SUADJD CTSU SUCLK Frequency Adjustment 16 7 read-write SUADJTRIM CTSU Current DAC Matching Coefficient Adjustment 2 24 7 read-write DFLCTL Data Flash Control Register 0x90 8 read-write n 0x0 0x0 DFLEN Data Flash Access Enable 0 read-write 0 Access to the data flash is disabled #0 1 Access to the data flash is enabled #1 FASR Flash Area Select Register 0x104 8 read-write n 0x0 0x0 EXS Extra Area Select 0 read-write 0 User area or data area #0 1 Extra area. #1 FAWEMR Flash Access Window End Address Monitor Register 0x1C8 16 read-only n 0x0 0x0 FAWE Access Window End Address 0 10 read-only SASMF Startup Area Setting Monitor Flag 15 read-only FAWSMR Flash Access Window Start Address Monitor Register FAWEMR 0x1C8 16 read-only n 0x0 0x0 FAWS Access Window Start Address 0 10 read-only FSPR Access Window Protection Flag 15 read-only FCR Flash Control Register 0x114 8 read-write n 0x0 0x0 CMD Software Command Setting 0 3 read-write Others Setting prohibited. 0x1 Program 0x1 0x3 Blank check (code flash) 0x3 0x4 Block erase 0x4 0x5 Consecutive read 0x5 0x6 Chip erase 0x6 0xB Blank check (data flash) 0xb DRC Data Read Completion 4 read-write 0 Data is not read or next data is requested #0 1 Data reading is complete. #1 OPST Processing Start 7 read-write 0 Processing stops #0 1 Processing starts. #1 STOP Forced Processing Stop 6 read-write FEAMH Flash Error Address Monitor Register H 0x1E8 16 read-write n 0x0 0x0 FEAMH Flash Error Address Monitor Register H 0 15 read-write FEAML Flash Error Address Monitor Register L 0x1E0 16 read-write n 0x0 0x0 FEAML Flash Error Address Monitor Register L 0 15 read-write FEARH Flash Processing End Address Register H 0x120 16 read-write n 0x0 0x0 FEARH Flash Processing End Address H 0 15 read-write FEARL Flash Processing End Address Register L 0x118 16 read-write n 0x0 0x0 FEARL Flash Processing End Address L 0 15 read-write FENTRYR Flash P/E Mode Entry Register 0x3FB0 16 read-write n 0x0 0x0 FEKEY Key Code 8 7 read-write FENTRY0 Code Flash P/E Mode Entry 0 0 read-write 0 The code flash is the read mode #0 1 The code flash is the P/E mode. #1 FENTRYD Data Flash P/E Mode Entry 7 read-write 0 The data flash is the read mode #0 1 The data flash is the P/E mode. #1 FEXCR Flash Extra Area Control Register 0x1DC 8 read-write n 0x0 0x0 CMD Software Command Setting 0 2 read-write Others Setting prohibited. 010 Access window information program Startup area selection and security setting #010 011 OCDID1 program #011 100 OCDID2 program #100 101 OCDID3 program #101 110 OCDID4 program #110 OPST Processing Start 7 read-write 0 Processing stops #0 1 Processing starts. #1 FISR Flash Initial Setting Register 0x1D8 8 read-write n 0x0 0x0 PCKA Peripheral Clock Notification 0 5 read-write SAS Startup Area Select 6 1 read-write Others The startup area is selected according to the settings of the extra area. 10 The startup area is switched to the default area temporarily #10 11 The startup area is switched to the alternate area temporarily. #11 FLDWAITR Memory Wait Cycle Control Register for Data Flash 0x3FC4 8 read-write n 0x0 0x0 FLDWAIT1 Memory Wait Cycle Select for Data Flash 0 read-write 0 1 wait access (Default) #0 1 2 wait access #1 FPMCR Flash P/E Mode Control Register 0x100 8 read-write n 0x0 0x0 FMS0 Flash Operating Mode Select 0 1 read-write 0 FMS1 = 0: Read mode FMS1 = 1: Data flash P/E mode. #0 1 FMS1 = 0: Code flash P/E mode FMS1 = 1: Discharge mode. #1 FMS1 Flash Operating Mode Select 1 4 read-write RPDIS Code Flash P/E Disable 3 read-write 0 Programming of the code flash is enabled #0 1 Programming of the code flash is disabled. #1 FPR Protection Unlock Register 0x180 8 read-write n 0x0 0x0 FPR Protection Unlock 0 7 read-write FPSR Protection Unlock Status Register 0x184 8 read-only n 0x0 0x0 PERR Protect Error Flag 0 read-only 0 No error #0 1 An error occurs #1 FRBH0 Flash Read Buffer Register H0 0x190 16 read-write n 0x0 0x0 RDATA Read Data H 0 15 read-write FRBL0 Flash Read Buffer Register L0 0x188 16 read-only n 0x0 0x0 RDATA Read Data L 0 15 read-only FRESETR Flash Reset Register 0x124 8 read-write n 0x0 0x0 FRESET Software reset of the registers 0 read-write 0 The registers related to the flash programming are not reset #0 1 The registers related to the flash programming are reset. #1 FSARH Flash Processing Start Address Register H 0x110 16 read-write n 0x0 0x0 FSARH Flash Processing Start Address H 0 15 read-write FSARL Flash Processing Start Address Register L FEARL 0x118 16 read-write n 0x0 0x0 FSARL Flash Processing Start Address L 0 15 read-write FSCMR Flash Start-Up Setting Monitor Register 0x1C0 16 read-only n 0x0 0x0 FSPR Access Window Protection Flag 14 read-only 0 Access window setting disabled. #0 1 Access window setting enabled. #1 SASMF Startup Area Setting Monitor Flag 8 read-only 0 Setting to start up using the alternative area #0 1 Setting to start up using the default area #1 FSTATR00 Flash Status Register 0 0x128 16 read-only n 0x0 0x0 BCERR0 Blank Check Error Flag 0 3 read-only 0 Blank checking terminates normally #0 1 An error occurs during blank checking. #1 EILGLERR Extra Area Illegal Command Error Flag 5 read-only 0 No illegal command or illegal access to the extra area is detected #0 1 An illegal command or illegal access to the extra area is detected. #1 ERERR0 Erase Error Flag 0 0 read-only 0 Erasure terminates normally #0 1 An error occurs during erasure. #1 ILGLERR Illegal Command Error Flag 4 read-only 0 No illegal software command or illegal access is detected #0 1 An illegal command or illegal access is detected. #1 PRGERR0 Program Error Flag 0 1 read-only 0 Programming terminates normally #0 1 An error occurs during programming. #1 PRGERR01 Program Error Flag 01 2 read-only 0 Programming by the FEXCR register terminates normally #0 1 An error occurs during programming. #1 FSTATR1 Flash Status Register 1 0x12C 8 read-only n 0x0 0x0 DRRDY Data Read Ready Flag 1 read-only 0 The read processing of the consecutive read command at each address is not terminated. #0 1 The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers. #1 EXRDY Extra Area Ready Flag 7 read-only 0 The software command of the FEXCR register is not terminated. #0 1 The software command of the FEXCR register is terminated. #1 FRDY Flash Ready Flag 6 read-only 0 The software command of the FCR register is not terminated. #0 1 The software command of the FCR register is terminated. #1 FSTATR2 Flash Status Register 2 0x1F0 16 read-only n 0x0 0x0 BCERR Blank Check Error Flag 3 read-only 0 Blank checking terminates normally #0 1 An error occurs during blank checking. #1 EILGLERR Extra Area Illegal Command Error Flag 5 read-only 0 No illegal command or illegal access to the extra area is detected #0 1 An illegal command or illegal access to the extra area is detected. #1 ERERR Erase Error Flag 0 read-only 0 Erasure terminates normally #0 1 An error occurs during erasure #1 ILGLERR Illegal Command Error Flag 4 read-only 0 No illegal software command or illegal access is detected #0 1 An illegal command or illegal access is detected. #1 PRGERR Program Error Flag 1 read-only 0 Programming terminates normally #0 1 An error occurs during programming. #1 PRGERR01 Program Error Flag 01 2 read-only 0 Programming by the FEXCR register terminates normally #0 1 An error occurs during programming. #1 FWBH0 Flash Write Buffer Register H0 0x138 16 read-write n 0x0 0x0 WDATA Write Data 0 15 read-write FWBL0 Flash Write Buffer Register L0 0x130 16 read-write n 0x0 0x0 WDATA Flash Write Buffer Register L0 0 15 read-write PFBER Prefetch Buffer Enable Register 0x3FC8 8 read-write n 0x0 0x0 PFBE Prefetch Buffer Enable bit 0 read-write 0 Prefetch buffer is disabled #0 1 Prefetch buffer is enabled #1 GPT164 General PWM 16-bit Timer 4 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 2 read-write Others Setting prohibited 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write Others Setting prohibited 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 read-write WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT165 General PWM 16-bit Timer 5 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 2 read-write Others Setting prohibited 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write Others Setting prohibited 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 read-write WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT166 General PWM 16-bit Timer 6 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 2 read-write Others Setting prohibited 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write Others Setting prohibited 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 read-write WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT167 General PWM 16-bit Timer 7 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 2 read-write Others Setting prohibited 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write Others Setting prohibited 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 read-write WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT168 General PWM 16-bit Timer 8 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 2 read-write Others Setting prohibited 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write Others Setting prohibited 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 read-write WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT169 General PWM 16-bit Timer 9 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 2 read-write Others Setting prohibited 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write Others Setting prohibited 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 read-write WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT320 General PWM 32-bit Timer 0 GPT320 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 24 2 read-write Others Setting prohibited 000 PCLKD/1 #000 001 PCLKD/4 #001 010 PCLKD/16 #010 011 PCLKD/64 #011 100 PCLKD/256 #100 101 PCLKD/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write Others Setting prohibited 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 read-write WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT_OPS Output Phase Switching Controller GPT_OPS 0x0 0x0 0x4 registers n OPSCR Output Phase Switching Control Register 0x0 32 read-write n 0x0 0x0 ALIGN Input Phase Alignment 21 read-write 0 Input phase aligned to PCLKD #0 1 Input phase aligned to PWM #1 EN Enable-Phase Output Control 8 read-write 0 Do not output (Hi-Z external pin) #0 1 Output #1 FB External Feedback Signal Enable 16 read-write 0 Select the external input #0 1 Select the soft setting (OPSCR.UF, VF, WF) #1 GODF Group Output Disable Function 26 read-write 0 This bit function is ignored #0 1 Group disable clears the OPSCR.EN bit #1 GRP Output Disabled Source Selection 24 1 read-write INV Invert-Phase Output Control 19 read-write 0 Positive logic (active-high) output #0 1 Negative logic (active-low) output #1 N Negative-Phase Output (N) Control 18 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT164) #1 NFCS External Input Noise Filter Clock Selection 30 1 read-write 00 PCLKD/1 #00 01 PCLKD/4 #01 10 PCLKD/16 #10 11 PCLKD/64 #11 NFEN External Input Noise Filter Enable 29 read-write 0 Do not use a noise filter on the external input #0 1 Use a noise filter on the external input #1 P Positive-Phase Output (P) Control 17 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT164) #1 RV Output Phase Rotation Direction Reversal Control 20 read-write 0 Positive rotation #0 1 Reverse rotation #1 U Input U-Phase Monitor 4 read-only UF 0 read-write V Input V-Phase Monitor 5 read-only VF 1 read-write W Input W-Phase Monitor 6 read-only WF 2 read-write ICU ICU for CPU ICU 0x0 0x0 0x8 registers n 0x100 0x1 registers n 0x120 0x2 registers n 0x130 0x2 registers n 0x140 0x2 registers n 0x1A0 0x4 registers n 0x1C0 0x1 registers n 0x200 0x2 registers n 0x300 0x80 registers n IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 IELEN ICU event Enable Register 0x1C0 8 read-write n 0x0 0x0 IELEN Parts Asynchronous Interrupts Enable except RTC (when LPOPTEN bit = 1) 1 read-write 0 Disable #0 1 Enable #1 RTCINTEN RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit = 1) 0 read-write 0 Disable #0 1 Enable #1 IELSR0 ICU Event Link Setting Register %s 0x300 32 read-write n 0x0 0x0 IELSR1 ICU Event Link Setting Register %s 0x304 32 read-write n 0x0 0x0 IELSR10 ICU Event Link Setting Register %s 0x328 32 read-write n 0x0 0x0 IELSR11 ICU Event Link Setting Register %s 0x32C 32 read-write n 0x0 0x0 IELSR12 ICU Event Link Setting Register %s 0x330 32 read-write n 0x0 0x0 IELSR13 ICU Event Link Setting Register %s 0x334 32 read-write n 0x0 0x0 IELSR14 ICU Event Link Setting Register %s 0x338 32 read-write n 0x0 0x0 IELSR15 ICU Event Link Setting Register %s 0x33C 32 read-write n 0x0 0x0 IELSR16 ICU Event Link Setting Register %s 0x340 32 read-write n 0x0 0x0 IELSR17 ICU Event Link Setting Register %s 0x344 32 read-write n 0x0 0x0 IELSR18 ICU Event Link Setting Register %s 0x348 32 read-write n 0x0 0x0 IELSR19 ICU Event Link Setting Register %s 0x34C 32 read-write n 0x0 0x0 IELSR2 ICU Event Link Setting Register %s 0x308 32 read-write n 0x0 0x0 IELSR20 ICU Event Link Setting Register %s 0x350 32 read-write n 0x0 0x0 IELSR21 ICU Event Link Setting Register %s 0x354 32 read-write n 0x0 0x0 IELSR22 ICU Event Link Setting Register %s 0x358 32 read-write n 0x0 0x0 IELSR23 ICU Event Link Setting Register %s 0x35C 32 read-write n 0x0 0x0 IELSR24 ICU Event Link Setting Register %s 0x360 32 read-write n 0x0 0x0 IELSR25 ICU Event Link Setting Register %s 0x364 32 read-write n 0x0 0x0 IELSR26 ICU Event Link Setting Register %s 0x368 32 read-write n 0x0 0x0 IELSR27 ICU Event Link Setting Register %s 0x36C 32 read-write n 0x0 0x0 IELSR28 ICU Event Link Setting Register %s 0x370 32 read-write n 0x0 0x0 IELSR29 ICU Event Link Setting Register %s 0x374 32 read-write n 0x0 0x0 IELSR3 ICU Event Link Setting Register %s 0x30C 32 read-write n 0x0 0x0 IELSR30 ICU Event Link Setting Register %s 0x378 32 read-write n 0x0 0x0 IELSR31 ICU Event Link Setting Register %s 0x37C 32 read-write n 0x0 0x0 IELSR4 ICU Event Link Setting Register %s 0x310 32 read-write n 0x0 0x0 IELSR5 ICU Event Link Setting Register %s 0x314 32 read-write n 0x0 0x0 IELSR6 ICU Event Link Setting Register %s 0x318 32 read-write n 0x0 0x0 IELSR7 ICU Event Link Setting Register %s 0x31C 32 read-write n 0x0 0x0 IELSR8 ICU Event Link Setting Register %s 0x320 32 read-write n 0x0 0x0 IELSR9 ICU Event Link Setting Register %s 0x324 32 read-write n 0x0 0x0 IRQCR0 IRQ Control Register 0x0 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR1 IRQ Control Register 0x1 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR2 IRQ Control Register 0x2 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR3 IRQ Control Register 0x3 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR4 IRQ Control Register 0x4 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR5 IRQ Control Register 0x5 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR6 IRQ Control Register 0x6 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR7 IRQ Control Register 0x7 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write n 0x0 0x0 BUSMCLR Bus Master Error Clear 11 read-write 0 No effect #0 1 Clear the NMISR.BUSMST flag #1 BUSSCLR Bus Slave Error Clear 10 read-write 0 No effect #0 1 Clear the NMISR.BUSSST flag #1 IWDTCLR IWDT Clear 0 read-write 0 No effect #0 1 Clear the NMISR.IWDTST flag #1 LVD1CLR LVD1 Clear 2 read-write 0 No effect #0 1 Clear the NMISR.LVD1ST flag #1 LVD2CLR LVD2 Clear 3 read-write 0 No effect #0 1 Clear the NMISR.LVD2ST flag. #1 NMICLR NMI Clear 7 read-write 0 No effect #0 1 Clear the NMISR.NMIST flag #1 OSTCLR OST Clear 6 read-write 0 No effect #0 1 Clear the NMISR.OSTST flag #1 RPECLR SRAM Parity Error Clear 8 read-write 0 No effect #0 1 Clear the NMISR.RPEST flag #1 SPECLR CPU Stack Pointer Monitor Interrupt Clear 12 read-write 0 No effect #0 1 Clear the NMISR.SPEST flag #1 WDTCLR WDT Clear 1 read-write 0 No effect #0 1 Clear the NMISR.WDTST flag #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write n 0x0 0x0 NFCLKSEL NMI Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 NFLTEN NMI Digital Filter Enable 7 read-write 0 Disabled #0 1 Enabled #1 NMIMD NMI Detection Set 0 read-write 0 Falling edge #0 1 Rising edge #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write n 0x0 0x0 BUSMEN MPU Bus Master Error Interrupt Enable 11 read-write 0 Disabled #0 1 Enabled #1 BUSSEN MPU Bus Slave Error Interrupt Enable 10 read-write 0 Disabled #0 1 Enabled #1 IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 read-write 0 Disabled #0 1 Enabled. #1 LVD1EN Voltage monitor 1 Interrupt Enable 2 read-write 0 Disabled #0 1 Enabled #1 LVD2EN Voltage monitor 2 Interrupt Enable 3 read-write 0 Disabled #0 1 Enabled #1 NMIEN NMI Pin Interrupt Enable 7 read-write 0 Disabled #0 1 Enabled #1 OSTEN Oscillation Stop Detection Interrupt Enable 6 read-write 0 Disabled #0 1 Enabled #1 RPEEN SRAM Parity Error Interrupt Enable 8 read-write 0 Disabled #0 1 Enabled #1 SPEEN CPU Stack Pointer Monitor Interrupt Enable 12 read-write 0 Disabled #0 1 Enabled #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 read-write 0 Disabled #0 1 Enabled #1 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only n 0x0 0x0 BUSMST MPU Bus Master Error Interrupt Status Flag 11 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 BUSSST MPU Bus Slave Error Interrupt Status Flag 10 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 IWDTST IWDT Underflow/Refresh Error Status Flag 0 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD1ST Voltage Monitor 1 Interrupt Status Flag 2 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD2ST Voltage Monitor 2 Interrupt Status Flag 3 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 NMIST NMI Status Flag 7 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 OSTST Oscillation Stop Detection Interrupt Status Flag 6 read-only 0 Interrupt not requested for main oscillation stop #0 1 Interrupt requested for main oscillation stop #1 RPEST SRAM Parity Error Interrupt Status Flag 8 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 SPEST CPU Stack Pointer Monitor Interrupt Status Flag 12 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 WDTST WDT Underflow/Refresh Error Status Flag 1 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 SELSR0 SYS Event Link Setting Register 0x200 16 read-write n 0x0 0x0 WUPEN Wake Up Interrupt Enable Register 0x1A0 32 read-write n 0x0 0x0 ACMPLP0WUPEN ACMPLP0 Interrupt Software Standby Returns Enable 23 read-write 0 Software Standby returns by ACMPLP0 interrupt disabled #0 1 Software Standby returns by ACMPLP0 interrupt enabled #1 AGT1CAWUPEN AGT1 Compare Match A Interrupt Software Standby Returns Enable 29 read-write 0 Software Standby returns by AGT1 compare match A interrupt disabled. #0 1 Software Standby returns by AGT1 compare match A interrupt enabled. #1 AGT1CBWUPEN AGT1 Compare Match B Interrupt Software Standby Returns Enable 30 read-write 0 Software Standby returns by AGT1 compare match B interrupt disabled. #0 1 Software Standby returns by AGT1 compare match B interrupt enabled. #1 AGT1UDWUPEN AGT1 Underflow Interrupt Software Standby Returns Enable 28 read-write 0 Software Standby returns by AGT1 underflow interrupt disabled #0 1 Software Standby returns by AGT1 underflow #1 IIC0WUPEN IIC0 Address Match Interrupt Software Standby Returns Enable 31 read-write 0 Software Standby returns by IIC0 address match interrupt disabled #0 1 Software Standby returns by IIC0 address match interrupt enabled #1 IRQWUPEN IRQ Interrupt Software Standby Returns Enable 0 7 read-write 0 Software Standby returns by IRQn interrupt disabled #0 1 Software Standby returns by IRQn interrupt enabled #1 IWDTWUPEN IWDT Interrupt Software Standby Returns Enable 16 read-write 0 Software Standby returns by IWDT interrupt disabled #0 1 Software Standby returns by IWDT interrupt enabled #1 KEYWUPEN Key Interrupt Software Standby Returns Enable 17 read-write 0 Software Standby returns by KEY interrupt disabled #0 1 Software Standby returns by KEY interrupt enabled #1 LVD1WUPEN LVD1 Interrupt Software Standby Returns Enable 18 read-write 0 Software Standby returns by LVD1 interrupt disabled #0 1 Software Standby returns by LVD1 interrupt enabled #1 LVD2WUPEN LVD2 Interrupt Software Standby Returns Enable 19 read-write 0 Software Standby returns by LVD2 interrupt disabled #0 1 Software Standby returns by LVD2 interrupt enabled #1 RTCALMWUPEN RTC Alarm Interrupt Software Standby Returns Enable 24 read-write 0 Software Standby returns by RTC alarm interrupt disabled #0 1 Software Standby returns by RTC alarm interrupt enabled. #1 RTCPRDWUPEN RTC Period Interrupt Software Standby Returns Enable 25 read-write 0 Software Standby returns by RTC period interrupt disabled #0 1 Software Standby returns by RTC period interrupt enabled #1 IIC0 Inter-Integrated Circuit 0 IIC0 0x0 0x0 0x14 registers n ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write n 0x0 0x0 BRH Bit Rate High-Level Period 0 4 read-write ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write n 0x0 0x0 BRL Bit Rate Low-Level Period 0 4 read-write ICCR1 I2C Bus Control Register 1 0x0 8 read-write n 0x0 0x0 CLO Extra SCL Clock Cycle Output 5 read-write 0 Do not output extra SCL clock cycle (default) #0 1 Output extra SCL clock cycle #1 ICE I2C Bus Interface Enable 7 read-write 0 Disable (SCL0 and SDA0 pins in inactive state) #0 1 Enable (SCL0 and SDA0 pins in active state) #1 IICRST I2C Bus Interface Internal Reset 6 read-write 0 Release IIC reset or internal reset #0 1 Initiate IIC reset or internal reset #1 SCLI SCL Line Monitor 1 read-only 0 SCL0 line is low #0 1 SCL0 line is high #1 SCLO SCL Output Control/Monitor 3 read-write 0 Read: IIC drives SCL0 pin low Write: IIC drives SCL0 pin low #0 1 Read: IIC releases SCL0 pin Write: IIC releases SCL0 pin #1 SDAI SDA Line Monitor 0 read-only 0 SDA0 line is low #0 1 SDA0 line is high #1 SDAO SDA Output Control/Monitor 2 read-write 0 Read: IIC drives SDA0 pin low Write: IIC drives SDA0 pin low #0 1 Read: IIC releases SDA0 pin Write: IIC releases SDA0 pin #1 SOWP SCLO/SDAO Write Protect 4 write-only 0 Write enable SCLO and SDAO bits #0 1 Write protect SCLO and SDAO bits #1 ICCR2 I2C Bus Control Register 2 0x1 8 read-write n 0x0 0x0 BBSY Bus Busy Detection Flag 7 read-only 0 I2C bus released (bus free state) #0 1 I2C bus occupied (bus busy state) #1 MST Master/Slave Mode 6 read-write 0 Slave mode #0 1 Master mode #1 RS Restart Condition Issuance Request 2 read-write 0 Do not issue a restart condition request #0 1 Issue a restart condition request #1 SP Stop Condition Issuance Request 3 read-write 0 Do not issue a stop condition request #0 1 Issue a stop condition request #1 ST Start Condition Issuance Request 1 read-write 0 Do not issue a start condition request #0 1 Issue a start condition request #1 TRS Transmit/Receive Mode 5 read-write 0 Receive mode #0 1 Transmit mode #1 ICDRR I2C Bus Receive Data Register 0x13 8 read-only n 0x0 0x0 ICDRT I2C Bus Transmit Data Register 0x12 8 read-write n 0x0 0x0 ICFER I2C Bus Function Enable Register 0x5 8 read-write n 0x0 0x0 MALE Master Arbitration-Lost Detection Enable 1 read-write 0 Disable the arbitration-lost detection function and disable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #0 1 Enable the arbitration-lost detection function and enable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #1 NACKE NACK Reception Transfer Suspension Enable 4 read-write 0 Do not suspend transfer operation during NACK reception (disable transfer suspension) #0 1 Suspend transfer operation during NACK reception (enable transfer suspension) #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 read-write 0 Disable #0 1 Enable #1 NFE Digital Noise Filter Circuit Enable 5 read-write 0 Do not use the digital noise filter circuit #0 1 Use the digital noise filter circuit #1 SALE Slave Arbitration-Lost Detection Enable 3 read-write 0 Disable #0 1 Enable #1 SCLE SCL Synchronous Circuit Enable 6 read-write 0 Do not use the SCL synchronous circuit #0 1 Use the SCL synchronous circuit #1 TMOE Timeout Function Enable 0 read-write 0 Disable #0 1 Enable #1 ICIER I2C Bus Interrupt Enable Register 0x7 8 read-write n 0x0 0x0 ALIE Arbitration-Lost Interrupt Request Enable 1 read-write 0 Disable arbitration-lost interrupt (ALI) request #0 1 Enable arbitration-lost interrupt (ALI) request #1 NAKIE NACK Reception Interrupt Request Enable 4 read-write 0 Disable NACK reception interrupt (NAKI) request #0 1 Enable NACK reception interrupt (NAKI) request #1 RIE Receive Data Full Interrupt Request Enable 5 read-write 0 Disable receive data full interrupt (IIC0_RXI) request #0 1 Enable receive data full interrupt (IIC0_RXI) request #1 SPIE Stop Condition Detection Interrupt Request Enable 3 read-write 0 Disable stop condition detection interrupt (SPI) request #0 1 Enable stop condition detection interrupt (SPI) request #1 STIE Start Condition Detection Interrupt Request Enable 2 read-write 0 Disable start condition detection interrupt (STI) request #0 1 Enable start condition detection interrupt (STI) request #1 TEIE Transmit End Interrupt Request Enable 6 read-write 0 Disable transmit end interrupt (IIC0_TEI) request #0 1 Enable transmit end interrupt (IIC0_TEI) request #1 TIE Transmit Data Empty Interrupt Request Enable 7 read-write 0 Disable transmit data empty interrupt (IIC0_TXI) request #0 1 Enable transmit data empty interrupt (IIC0_TXI) request #1 TMOIE Timeout Interrupt Request Enable 0 read-write 0 Disable timeout interrupt (TMOI) request #0 1 Enable timeout interrupt (TMOI) request #1 ICMR1 I2C Bus Mode Register 1 0x2 8 read-write n 0x0 0x0 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 BCWP BC Write Protect 3 write-only 0 Write enable BC[2:0] bits #0 1 Write protect BC[2:0] bits #1 CKS Internal Reference Clock Select 4 2 read-write MTWP MST/TRS Write Protect 7 read-write 0 Write protect MST and TRS bits in ICCR2 #0 1 Write enable MST and TRS bits in ICCR2 #1 ICMR2 I2C Bus Mode Register 2 0x3 8 read-write n 0x0 0x0 DLCS SDA Output Delay Clock Source Select 7 read-write 0 Select internal reference clock (IIC-phi) as the clock source for SDA output delay counter #0 1 Select internal reference clock divided by 2 (IIC-phi/2) as the clock source for SDA output delay counter #1 SDDL SDA Output Delay Counter 4 2 read-write 000 No output delay #000 001 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi)) 1 or 2 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #001 010 2 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 3 or 4 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #010 011 3 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 5 or 6 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #011 100 4 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 7 or 8 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #100 101 5 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 9 or 10 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #101 110 6 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 11 or 12 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #110 111 7 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 13 or 14 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #111 TMOH Timeout H Count Control 2 read-write 0 Disable count while SCL0 line is high #0 1 Enable count while SCL0 line is high #1 TMOL Timeout L Count Control 1 read-write 0 Disable count while SCL0 line is low #0 1 Enable count while SCL0 line is low #1 TMOS Timeout Detection Time Select 0 read-write 0 Select long mode #0 1 Select short mode #1 ICMR3 I2C Bus Mode Register 3 0x4 8 read-write n 0x0 0x0 ACKBR Receive Acknowledge 2 read-only 0 0 received as the acknowledge bit (ACK reception) #0 1 1 received as the acknowledge bit (NACK reception) #1 ACKBT Transmit Acknowledge 3 read-write 0 Send 0 as the acknowledge bit (ACK transmission) #0 1 Send 1 as the acknowledge bit (NACK transmission) #1 ACKWP ACKBT Write Protect 4 read-write 0 Write protect ACKBT bit #0 1 Write enable ACKBT bit #1 NF Noise Filter Stage Select 0 1 read-write 00 Filter out noise of up to 1 IIC-phi cycle (single-stage filter) #00 01 Filter out noise of up to 2 IIC-phi cycles (2-stage filter) #01 10 Filter out noise of up to 3 IIC-phi cycles (3-stage filter) #10 11 Filter out noise of up to 4 IIC-phi cycles (4-stage filter) #11 RDRFS RDRF Flag Set Timing Select 5 read-write 0 Set the RDRF flag on the rising edge of the 9th SCL clock cycle. The SCLn line is not held low on the falling edge of the 8th clock cycle. #0 1 Set the RDRF flag on the rising edge of the 8th SCL clock cycle. The SCLn line is held low on the falling edge of the 8th clock cycle. #1 SMBS SMBus/I2C Bus Select 7 read-write 0 Select I2C Bus #0 1 Select SMBus #1 WAIT Low-hold is released by reading ICDRR. 6 read-write 0 No wait (The SCLn line is not held low during the period between the 9th clock cycle and the 1st clock cycle.) #0 1 Wait (The SCLn line is held low during the period between the 9th clock cycle and the 1st clock cycle.) #1 ICSER I2C Bus Status Enable Register 0x6 8 read-write n 0x0 0x0 DIDE Device-ID Address Detection Enable 5 read-write 0 Disable device-ID address detection #0 1 Enable device-ID address detection #1 GCAE General Call Address Enable 3 read-write 0 Disable general call address detection #0 1 Enable general call address detection #1 HOAE Host Address Enable 7 read-write 0 Disable host address detection #0 1 Enable host address detection #1 SAR0E Slave Address Register 0 Enable 0 read-write 0 Disable slave address in SARL0 and SARU0 #0 1 Enable slave address in SARL0 and SARU0 #1 SAR1E Slave Address Register 1 Enable 1 read-write 0 Disable slave address in SARL1 and SARU1 #0 1 Enable slave address in SARL1 and SARU1 #1 SAR2E Slave Address Register 2 Enable 2 read-write 0 Disable slave address in SARL2 and SARU2 #0 1 Enable slave address in SARL2 and SARU2 #1 ICSR1 I2C Bus Status Register 1 0x8 8 read-write n 0x0 0x0 AAS0 Slave Address 0 Detection Flag 0 read-write 0 Slave address 0 not detected #0 1 Slave address 0 detected #1 AAS1 Slave Address 1 Detection Flag 1 read-write 0 Slave address 1 not detected #0 1 Slave address 1 detected #1 AAS2 Slave Address 2 Detection Flag 2 read-write 0 Slave address 2 not detected #0 1 Slave address 2 detected #1 DID Device-ID Address Detection Flag 5 read-write 0 Device-ID command not detected #0 1 Device-ID command detected #1 GCA General Call Address Detection Flag 3 read-write 0 General call address not detected #0 1 General call address detected #1 HOA Host Address Detection Flag 7 read-write 0 Host address not detected #0 1 Host address detected #1 ICSR2 I2C Bus Status Register 2 0x9 8 read-write n 0x0 0x0 AL Arbitration-Lost Flag 1 read-write 0 Arbitration not lost #0 1 Arbitration lost #1 NACKF NACK Detection Flag 4 read-write 0 NACK not detected #0 1 NACK detected #1 RDRF Receive Data Full Flag 5 read-write 0 ICDRR contains no receive data #0 1 ICDRR contains receive data #1 START Start Condition Detection Flag 2 read-write 0 Start condition not detected #0 1 Start condition detected #1 STOP Stop Condition Detection Flag 3 read-write 0 Stop condition not detected #0 1 Stop condition detected #1 TDRE Transmit Data Empty Flag 7 read-only 0 ICDRT contains transmit data #0 1 ICDRT contains no transmit data #1 TEND Transmit End Flag 6 read-write 0 Data being transmitted #0 1 Data transmit complete #1 TMOF Timeout Detection Flag 0 read-write 0 Timeout not detected #0 1 Timeout detected #1 SARL0 Slave Address Register Ly 0xA 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARL1 Slave Address Register Ly 0xC 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARL2 Slave Address Register Ly 0xE 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARU0 Slave Address Register Uy 0xB 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write SARU1 Slave Address Register Uy 0xD 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write SARU2 Slave Address Register Uy 0xF 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write IIC0WU Inter-Integrated Circuit 0 Wake-up Unit IIC0WU 0x0 0x2 0x2 registers n ICWUR I2C Bus Wakeup Unit Register 0x2 8 read-write n 0x0 0x0 WUACK ACK Bit for Wakeup Mode 4 read-write WUAFA Wakeup Analog Filter Additional Selection 0 read-write 0 Do not add the wakeup analog filter #0 1 Add the wakeup analog filter #1 WUE Wakeup Function Enable 7 read-write 0 Disable wakeup function #0 1 Enable wakeup function #1 WUF Wakeup Event Occurrence Flag 5 read-write 0 Slave address not matching during wakeup #0 1 Slave address matching during wakeup #1 WUIE Wakeup Interrupt Request Enable 6 read-write 0 Disable wakeup interrupt request (IIC0_WUI) #0 1 Enable wakeup interrupt request (IIC0_WUI) #1 ICWUR2 I2C Bus Wakeup Unit Register 2 0x3 8 read-write n 0x0 0x0 WUASYF Wakeup Function Asynchronous Operation Status Flag 1 read-only 0 IIC synchronous circuit enable condition #0 1 IIC asynchronous circuit enable condition #1 WUSEN Wakeup Function Synchronous Enable 0 read-write 0 IIC asynchronous circuit enable #0 1 IIC synchronous circuit enable #1 WUSYF Wakeup Function Synchronous Operation Status Flag 2 read-only 0 IIC asynchronous circuit enable condition #0 1 IIC synchronous circuit enable condition #1 IWDT Independent Watchdog Timer IWDT 0x0 0x0 0x1 registers n 0x4 0x2 registers n IWDTRR IWDT Refresh Register 0x0 8 read-write n 0x0 0x0 IWDTSR IWDT Status Register 0x4 16 read-write n 0x0 0x0 CNTVAL Down-counter Value 0 13 read-only REFEF Refresh Error Flag 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 KINT Key Interrupt Function KINT 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x8 0x1 registers n KRCTL Key Return Control Register 0x0 8 read-write n 0x0 0x0 KREG Detection Edge Selection (KR00 to KR07 pins) 0 read-write 0 Falling edge #0 1 Rising edge #1 KRMD Usage of Key Interrupt Flags (KRF.KIF0 to KRF.KIF7) 7 read-write 0 Do not use key interrupt flags #0 1 Use key interrupt flags #1 KRF Key Return Flag Register 0x4 8 read-write n 0x0 0x0 KIF0 Key Interrupt Flag n 0 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF1 Key Interrupt Flag n 1 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF2 Key Interrupt Flag n 2 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF3 Key Interrupt Flag n 3 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF4 Key Interrupt Flag n 4 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF5 Key Interrupt Flag n 5 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF6 Key Interrupt Flag n 6 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KIF7 Key Interrupt Flag n 7 read-write 0 No interrupt detected #0 1 Interrupt detected #1 KRM Key Return Mode Register 0x8 8 read-write n 0x0 0x0 KIMC0 Key Interrupt Mode Control n 0 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC1 Key Interrupt Mode Control n 1 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC2 Key Interrupt Mode Control n 2 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC3 Key Interrupt Mode Control n 3 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC4 Key Interrupt Mode Control n 4 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC5 Key Interrupt Mode Control n 5 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC6 Key Interrupt Mode Control n 6 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 KIMC7 Key Interrupt Mode Control n 7 read-write 0 Do not detect key interrupt signals #0 1 Detect key interrupt signals #1 MSTP Module Stop Control B, C, D MSTP 0x0 0x0 0xE registers n LSMRWDIS Low Speed Module R/W Disable Control Register 0xC 16 read-write n 0x0 0x0 IWDTIDS IWDT Register Clock Control 2 read-write 0 IWDT operates as normal #0 1 Stop the IWDT register R/W clock #1 PRKEY LSMRWDIS Key Code 8 7 write-only RTCRWDIS RTC Register R/W Enable Control 0 read-write 0 RTC register R/W clock always on #0 1 RTC register R/W clock stops #1 WDTDIS WDT Operate Clock Control 1 read-write 0 WDT operates as normal #0 1 Stop the WDT clock and register R/W clock #1 WREN Write Enable for bits [2:0] 7 read-write 0 Write protect for bits [2:0] #0 1 Write enable for bits [2:0] #1 MSTPCRB Module Stop Control Register B 0x0 32 read-write n 0x0 0x0 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB29 Serial Communication Interface 2 Module Stop 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB30 Serial Communication Interface 1 Module Stop 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB31 Serial Communication Interface 0 Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB9 I2C Bus Interface 0 Module Stop 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRC Module Stop Control Register C 0x4 32 read-write n 0x0 0x0 MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 Cyclic Redundancy Check Calculator Module Stop 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC28 Random Number Generator Module Stop 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC3 Capacitive Touch Sensing Unit Module Stop 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC31 AES Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0x8 32 read-write n 0x0 0x0 MSTPD14 Port Output Enable for GPT Module Stop 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 12-bit A/D Converter Module Stop 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD2 Low Power Asynchronous General Purpose Timer 1 Module Stop 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD29 Low-Power Analog Comparator Module Stop 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 Low Power Asynchronous General Purpose Timer 0 Module Stop 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD5 General PWM Timer 32n Module Stop 5 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD6 General PWM Timer 164 to 169 and PWM Delay Generation Circuit Module Stop 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 PFS Pmn Pin Function Control Register PFS 0x0 0x0 0x17 registers n 0x100 0x4F registers n 0x274 0xF registers n 0x28 0x53 registers n 0x503 0x1 registers n 0x50F 0x1 registers n 0x80 0x27 registers n 0xB0 0x27 registers n P000PFS Port 00%s Pin Function Select Register 0x0 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P000PFS_BY Port 00%s Pin Function Select Register P00%sPFS 0x3 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P000PFS_HA Port 00%s Pin Function Select Register P00%sPFS 0x2 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P001PFS Port 00%s Pin Function Select Register 0x4 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P001PFS_BY Port 00%s Pin Function Select Register P00%sPFS 0x7 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P001PFS_HA Port 00%s Pin Function Select Register P00%sPFS 0x6 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P002PFS Port 00%s Pin Function Select Register 0x8 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P002PFS_BY Port 00%s Pin Function Select Register P00%sPFS 0xB 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P002PFS_HA Port 00%s Pin Function Select Register P00%sPFS 0xA 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P003PFS Port 00%s Pin Function Select Register 0xC 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P003PFS_BY Port 00%s Pin Function Select Register P00%sPFS 0xF 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P003PFS_HA Port 00%s Pin Function Select Register P00%sPFS 0xE 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P004PFS Port 00%s Pin Function Select Register 0x10 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P004PFS_BY Port 00%s Pin Function Select Register P00%sPFS 0x13 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P004PFS_HA Port 00%s Pin Function Select Register P00%sPFS 0x12 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P010PFS Port 0%s Pin Function Select Register 0x28 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P010PFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x2B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P010PFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x2A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P011PFS Port 0%s Pin Function Select Register 0x2C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P011PFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x2F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P011PFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x2E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P012PFS Port 0%s Pin Function Select Register 0x30 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P012PFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x33 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P012PFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x32 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P013PFS Port 0%s Pin Function Select Register 0x34 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P013PFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x37 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P013PFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x36 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P014PFS Port 0%s Pin Function Select Register 0x38 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P014PFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x3B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P014PFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x3A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P015PFS Port 0%s Pin Function Select Register 0x3C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P015PFS_BY Port 0%s Pin Function Select Register P0%sPFS 0x3F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P015PFS_HA Port 0%s Pin Function Select Register P0%sPFS 0x3E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P100PFS Port 10%s Pin Function Select Register 0x40 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P100PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x43 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P100PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x42 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P101PFS Port 10%s Pin Function Select Register 0x44 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P101PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x47 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P101PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x46 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P102PFS Port 10%s Pin Function Select Register 0x48 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P102PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x4B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P102PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x4A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P103PFS Port 10%s Pin Function Select Register 0x4C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P103PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x4F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P103PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x4E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P104PFS Port 10%s Pin Function Select Register 0x50 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P104PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x53 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P104PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x52 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P105PFS Port 10%s Pin Function Select Register 0x54 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P105PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x57 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P105PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x56 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P106PFS Port 10%s Pin Function Select Register 0x58 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P106PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x5B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P106PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x5A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P107PFS Port 10%s Pin Function Select Register 0x5C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P107PFS_BY Port 10%s Pin Function Select Register P10%sPFS 0x5F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P107PFS_HA Port 10%s Pin Function Select Register P10%sPFS 0x5E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P108PFS Port 108 Pin Function Select Register 0x60 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P108PFS_BY Port 108 Pin Function Select Register P108PFS 0x63 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P108PFS_HA Port 108 Pin Function Select Register P108PFS 0x62 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P109PFS Port 109 Pin Function Select Register 0x64 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P109PFS_BY Port 109 Pin Function Select Register P109PFS 0x67 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P109PFS_HA Port 109 Pin Function Select Register P109PFS 0x66 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P110PFS Port 1%s Pin Function Select Register 0x68 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P110PFS_BY Port 1%s Pin Function Select Register P1%sPFS 0x6B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P110PFS_HA Port 1%s Pin Function Select Register P1%sPFS 0x6A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P111PFS Port 1%s Pin Function Select Register 0x6C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P111PFS_BY Port 1%s Pin Function Select Register P1%sPFS 0x6F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P111PFS_HA Port 1%s Pin Function Select Register P1%sPFS 0x6E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P112PFS Port 1%s Pin Function Select Register 0x70 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P112PFS_BY Port 1%s Pin Function Select Register P1%sPFS 0x73 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P112PFS_HA Port 1%s Pin Function Select Register P1%sPFS 0x72 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P113PFS Port 1%s Pin Function Select Register 0x74 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P113PFS_BY Port 1%s Pin Function Select Register P1%sPFS 0x77 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P113PFS_HA Port 1%s Pin Function Select Register P1%sPFS 0x76 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P200PFS Port 200 Pin Function Select Register 0x80 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P200PFS_BY Port 200 Pin Function Select Register P200PFS 0x83 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P200PFS_HA Port 200 Pin Function Select Register P200PFS 0x82 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P201PFS Port 201 Pin Function Select Register 0x84 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P201PFS_BY Port 201 Pin Function Select Register P201PFS 0x87 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P201PFS_HA Port 201 Pin Function Select Register P201PFS 0x86 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P202PFS Port 20%s Pin Function Select Register 0x88 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P202PFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x8B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P202PFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x8A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P203PFS Port 20%s Pin Function Select Register 0x8C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P203PFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x8F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P203PFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x8E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P204PFS Port 20%s Pin Function Select Register 0x90 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P204PFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x93 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P204PFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x92 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P205PFS Port 20%s Pin Function Select Register 0x94 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P205PFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x97 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P205PFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x96 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P206PFS Port 20%s Pin Function Select Register 0x98 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P206PFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x9B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P206PFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x9A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P207PFS Port 20%s Pin Function Select Register 0x9C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P207PFS_BY Port 20%s Pin Function Select Register P20%sPFS 0x9F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P207PFS_HA Port 20%s Pin Function Select Register P20%sPFS 0x9E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P208PFS Port 20%s Pin Function Select Register 0xA0 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P208PFS_BY Port 20%s Pin Function Select Register P20%sPFS 0xA3 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P208PFS_HA Port 20%s Pin Function Select Register P20%sPFS 0xA2 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P212PFS Port 2%s Pin Function Select Register 0xB0 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P212PFS_BY Port 2%s Pin Function Select Register P2%sPFS 0xB3 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P212PFS_HA Port 2%s Pin Function Select Register P2%sPFS 0xB2 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P213PFS Port 2%s Pin Function Select Register 0xB4 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P213PFS_BY Port 2%s Pin Function Select Register P2%sPFS 0xB7 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P213PFS_HA Port 2%s Pin Function Select Register P2%sPFS 0xB6 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P214PFS Port 2%s Pin Function Select Register 0xB8 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P214PFS_BY Port 2%s Pin Function Select Register P2%sPFS 0xBB 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P214PFS_HA Port 2%s Pin Function Select Register P2%sPFS 0xBA 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P215PFS Port 2%s Pin Function Select Register 0xBC 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P215PFS_BY Port 2%s Pin Function Select Register P2%sPFS 0xBF 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P215PFS_HA Port 2%s Pin Function Select Register P2%sPFS 0xBE 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 EOFR Event on Falling/Event on Rising 12 1 read-write 00 Don't care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P300PFS Port 300 Pin Function Select Register 0xC0 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P300PFS_BY Port 300 Pin Function Select Register P300PFS 0xC3 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P300PFS_HA Port 300 Pin Function Select Register P300PFS 0xC2 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P301PFS Port 30%s Pin Function Select Register 0xC4 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P301PFS_BY Port 30%s Pin Function Select Register P30%sPFS 0xC7 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P301PFS_HA Port 30%s Pin Function Select Register P30%sPFS 0xC6 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P302PFS Port 30%s Pin Function Select Register 0xC8 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P302PFS_BY Port 30%s Pin Function Select Register P30%sPFS 0xCB 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P302PFS_HA Port 30%s Pin Function Select Register P30%sPFS 0xCA 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P303PFS Port 30%s Pin Function Select Register 0xCC 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P303PFS_BY Port 30%s Pin Function Select Register P30%sPFS 0xCF 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P303PFS_HA Port 30%s Pin Function Select Register P30%sPFS 0xCE 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P304PFS Port 30%s Pin Function Select Register 0xD0 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P304PFS_BY Port 30%s Pin Function Select Register P30%sPFS 0xD3 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P304PFS_HA Port 30%s Pin Function Select Register P30%sPFS 0xD2 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P400PFS Port 40%s Pin Function Select Register 0x100 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P400PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x103 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P400PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x102 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P401PFS Port 40%s Pin Function Select Register 0x104 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P401PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x107 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P401PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x106 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P402PFS Port 40%s Pin Function Select Register 0x108 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P402PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x10B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P402PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x10A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P403PFS Port 40%s Pin Function Select Register 0x10C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P403PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x10F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P403PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x10E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P404PFS Port 40%s Pin Function Select Register 0x110 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P404PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x113 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P404PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x112 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P405PFS Port 40%s Pin Function Select Register 0x114 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P405PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x117 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P405PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x116 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P406PFS Port 40%s Pin Function Select Register 0x118 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P406PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x11B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P406PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x11A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P407PFS Port 40%s Pin Function Select Register 0x11C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P407PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x11F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P407PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x11E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P408PFS Port 40%s Pin Function Select Register 0x120 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P408PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x123 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P408PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x122 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P409PFS Port 40%s Pin Function Select Register 0x124 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P409PFS_BY Port 40%s Pin Function Select Register P40%sPFS 0x127 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P409PFS_HA Port 40%s Pin Function Select Register P40%sPFS 0x126 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P410PFS Port 4%s Pin Function Select Register 0x128 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P410PFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x12B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P410PFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x12A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P411PFS Port 4%s Pin Function Select Register 0x12C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P411PFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x12F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P411PFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x12E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P412PFS Port 4%s Pin Function Select Register 0x130 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P412PFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x133 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P412PFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x132 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P413PFS Port 4%s Pin Function Select Register 0x134 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P413PFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x137 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P413PFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x136 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P414PFS Port 4%s Pin Function Select Register 0x138 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P414PFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x13B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P414PFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x13A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P415PFS Port 4%s Pin Function Select Register 0x13C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P415PFS_BY Port 4%s Pin Function Select Register P4%sPFS 0x13F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P415PFS_HA Port 4%s Pin Function Select Register P4%sPFS 0x13E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P500PFS Port 50%s Pin Function Select Register 0x140 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P500PFS_BY Port 50%s Pin Function Select Register P50%sPFS 0x143 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P500PFS_HA Port 50%s Pin Function Select Register P50%sPFS 0x142 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P501PFS Port 50%s Pin Function Select Register 0x144 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P501PFS_BY Port 50%s Pin Function Select Register P50%sPFS 0x147 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P501PFS_HA Port 50%s Pin Function Select Register P50%sPFS 0x146 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P502PFS Port 50%s Pin Function Select Register 0x148 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P502PFS_BY Port 50%s Pin Function Select Register P50%sPFS 0x14B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P502PFS_HA Port 50%s Pin Function Select Register P50%sPFS 0x14A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P913PFS Port 9%s Pin Function Select Register 0x274 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P913PFS_BY Port 9%s Pin Function Select Register P9%sPFS 0x277 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P913PFS_HA Port 9%s Pin Function Select Register P9%sPFS 0x276 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P914PFS Port 9%s Pin Function Select Register 0x278 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P914PFS_BY Port 9%s Pin Function Select Register P9%sPFS 0x27B 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P914PFS_HA Port 9%s Pin Function Select Register P9%sPFS 0x27A 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P915PFS Port 9%s Pin Function Select Register 0x27C 32 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PMR Port Mode Control 16 read-write 0 Use as general I/O pin #0 1 Use as I/O port for peripheral functions #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PSEL Peripheral Select 24 4 read-write P915PFS_BY Port 9%s Pin Function Select Register P9%sPFS 0x27F 8 read-write n 0x0 0x0 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 P915PFS_HA Port 9%s Pin Function Select Register P9%sPFS 0x27E 16 read-write n 0x0 0x0 ASEL Analog Input Enable 15 read-write 0 Do not use as analog pin #0 1 Use as analog pin #1 ISEL IRQ Input Enable 14 read-write 0 Do not use as IRQn input pin #0 1 Use as IRQn input pin #1 NCODR N-Channel Open-Drain Control 6 read-write 0 Output CMOS #0 1 Output NMOS open-drain #1 PCR Pull-up Control 4 read-write 0 Disable input pull-up #0 1 Enable input pull-up #1 PDR Port Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port State 1 read-only 0 Low level #0 1 High level #1 PODR Port Output Data 0 read-write 0 Output low #0 1 Output high #1 PRWCNTR Port Read Wait Control Register 0x50F 8 read-write n 0x0 0x0 WAIT Wait Cycle Control 0 1 read-write 00 Setting prohibited #00 01 Insert a 1-cycle wait #01 10 Insert a 2-cycle wait #10 11 Insert a 3-cycle wait #11 PWPR Write-Protect Register 0x503 8 read-write n 0x0 0x0 B0WI PFSWE Bit Write Disable 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PFSWE PmnPFS Register Write Enable 6 read-write 0 Writing to the PmnPFS register is disabled #0 1 Writing to the PmnPFS register is enabled #1 POEG Port Output Enable Module for GPT POEG 0x0 0x0 0x4 registers n 0x100 0x4 registers n POEGGA POEG Group A Setting Register 0x0 32 read-write n 0x0 0x0 INV GTETRGn Input Reverse 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 IOCE Enable for GPT Output-Disable Request 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 IOCF Detection Flag for GPT Output-Disable Request 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 NFEN Noise Filter Enable 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 OSTPE Oscillation Stop Detection Enable 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 OSTPF Oscillation Stop Detection Flag 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 PIDE Port Input Detection Enable 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 PIDF Port Input Detection Flag 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 SSF Software Stop Flag 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 ST GTETRGn Input Status Flag 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 POEGGB POEG Group B Setting Register 0x100 32 read-write n 0x0 0x0 INV GTETRGn Input Reverse 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 IOCE Enable for GPT Output-Disable Request 5 read-write 0 Disable output-disable requests from GPT #0 1 Enable output-disable requests from GPT #1 IOCF Detection Flag for GPT Output-Disable Request 1 read-write 0 No output-disable request from GPT occurred. #0 1 Output-disable request from GPT occurred. #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sample GTETRGn pin input level three times every PCLKB #00 01 Sample GTETRGn pin input level three times every PCLKB/8 #01 10 Sample GTETRGn pin input level three times every PCLKB/32 #10 11 Sample GTETRGn pin input level three times every PCLKB/128 #11 NFEN Noise Filter Enable 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 OSTPE Oscillation Stop Detection Enable 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 OSTPF Oscillation Stop Detection Flag 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 PIDE Port Input Detection Enable 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 PIDF Port Input Detection Flag 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 SSF Software Stop Flag 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 ST GTETRGn Input Status Flag 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 PORT0 Port 0 Control Registers PORT0 0x0 0x0 0xC registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT1 Port 1 Control Registers PORT1 0x0 0x0 0x10 registers n EIDR Port Control Register 2 PCNTR2 0x4 16 read-only n 0x0 0x0 EIDR00 Port Event Input Data 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 read-only 0 Low input #0 1 High input #1 EORR Port Control Register 4 PCNTR4 0xC 16 read-write n 0x0 0x0 EORR00 Pmn Event Output Reset 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0xE 16 read-write n 0x0 0x0 EOSR00 Pmn Event Output Set 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 read-write 0 No effect on output #0 1 High output #1 PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR00 Port Event Input Data 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 read-only 0 Low input #0 1 High input #1 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PCNTR4 Port Control Register 4 0xC 32 read-write n 0x0 0x0 EORR00 Pmn Event Output Reset 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 read-write 0 No effect on output #0 1 Low output #1 EOSR00 Pmn Event Output Set 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 read-write 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT2 Port 2 Control Registers PORT1 0x0 0x0 0x10 registers n EIDR Port Control Register 2 PCNTR2 0x4 16 read-only n 0x0 0x0 EIDR00 Port Event Input Data 0 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 1 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 2 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 3 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 4 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 5 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 6 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 7 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 8 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 9 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 10 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 11 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 12 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 13 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 14 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 15 read-only 0 Low input #0 1 High input #1 EORR Port Control Register 4 PCNTR4 0xC 16 read-write n 0x0 0x0 EORR00 Pmn Event Output Reset 0 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 1 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 2 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 3 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 4 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 5 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 6 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 7 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 8 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 9 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 10 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 11 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 12 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 13 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 14 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 15 read-write 0 No effect on output #0 1 Low output #1 EOSR Port Control Register 4 PCNTR4 0xE 16 read-write n 0x0 0x0 EOSR00 Pmn Event Output Set 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 read-write 0 No effect on output #0 1 High output #1 PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR00 Port Event Input Data 16 read-only 0 Low input #0 1 High input #1 EIDR01 Port Event Input Data 17 read-only 0 Low input #0 1 High input #1 EIDR02 Port Event Input Data 18 read-only 0 Low input #0 1 High input #1 EIDR03 Port Event Input Data 19 read-only 0 Low input #0 1 High input #1 EIDR04 Port Event Input Data 20 read-only 0 Low input #0 1 High input #1 EIDR05 Port Event Input Data 21 read-only 0 Low input #0 1 High input #1 EIDR06 Port Event Input Data 22 read-only 0 Low input #0 1 High input #1 EIDR07 Port Event Input Data 23 read-only 0 Low input #0 1 High input #1 EIDR08 Port Event Input Data 24 read-only 0 Low input #0 1 High input #1 EIDR09 Port Event Input Data 25 read-only 0 Low input #0 1 High input #1 EIDR10 Port Event Input Data 26 read-only 0 Low input #0 1 High input #1 EIDR11 Port Event Input Data 27 read-only 0 Low input #0 1 High input #1 EIDR12 Port Event Input Data 28 read-only 0 Low input #0 1 High input #1 EIDR13 Port Event Input Data 29 read-only 0 Low input #0 1 High input #1 EIDR14 Port Event Input Data 30 read-only 0 Low input #0 1 High input #1 EIDR15 Port Event Input Data 31 read-only 0 Low input #0 1 High input #1 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PCNTR4 Port Control Register 4 0xC 32 read-write n 0x0 0x0 EORR00 Pmn Event Output Reset 16 read-write 0 No effect on output #0 1 Low output #1 EORR01 Pmn Event Output Reset 17 read-write 0 No effect on output #0 1 Low output #1 EORR02 Pmn Event Output Reset 18 read-write 0 No effect on output #0 1 Low output #1 EORR03 Pmn Event Output Reset 19 read-write 0 No effect on output #0 1 Low output #1 EORR04 Pmn Event Output Reset 20 read-write 0 No effect on output #0 1 Low output #1 EORR05 Pmn Event Output Reset 21 read-write 0 No effect on output #0 1 Low output #1 EORR06 Pmn Event Output Reset 22 read-write 0 No effect on output #0 1 Low output #1 EORR07 Pmn Event Output Reset 23 read-write 0 No effect on output #0 1 Low output #1 EORR08 Pmn Event Output Reset 24 read-write 0 No effect on output #0 1 Low output #1 EORR09 Pmn Event Output Reset 25 read-write 0 No effect on output #0 1 Low output #1 EORR10 Pmn Event Output Reset 26 read-write 0 No effect on output #0 1 Low output #1 EORR11 Pmn Event Output Reset 27 read-write 0 No effect on output #0 1 Low output #1 EORR12 Pmn Event Output Reset 28 read-write 0 No effect on output #0 1 Low output #1 EORR13 Pmn Event Output Reset 29 read-write 0 No effect on output #0 1 Low output #1 EORR14 Pmn Event Output Reset 30 read-write 0 No effect on output #0 1 Low output #1 EORR15 Pmn Event Output Reset 31 read-write 0 No effect on output #0 1 Low output #1 EOSR00 Pmn Event Output Set 0 read-write 0 No effect on output #0 1 High output #1 EOSR01 Pmn Event Output Set 1 read-write 0 No effect on output #0 1 High output #1 EOSR02 Pmn Event Output Set 2 read-write 0 No effect on output #0 1 High output #1 EOSR03 Pmn Event Output Set 3 read-write 0 No effect on output #0 1 High output #1 EOSR04 Pmn Event Output Set 4 read-write 0 No effect on output #0 1 High output #1 EOSR05 Pmn Event Output Set 5 read-write 0 No effect on output #0 1 High output #1 EOSR06 Pmn Event Output Set 6 read-write 0 No effect on output #0 1 High output #1 EOSR07 Pmn Event Output Set 7 read-write 0 No effect on output #0 1 High output #1 EOSR08 Pmn Event Output Set 8 read-write 0 No effect on output #0 1 High output #1 EOSR09 Pmn Event Output Set 9 read-write 0 No effect on output #0 1 High output #1 EOSR10 Pmn Event Output Set 10 read-write 0 No effect on output #0 1 High output #1 EOSR11 Pmn Event Output Set 11 read-write 0 No effect on output #0 1 High output #1 EOSR12 Pmn Event Output Set 12 read-write 0 No effect on output #0 1 High output #1 EOSR13 Pmn Event Output Set 13 read-write 0 No effect on output #0 1 High output #1 EOSR14 Pmn Event Output Set 14 read-write 0 No effect on output #0 1 High output #1 EOSR15 Pmn Event Output Set 15 read-write 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT3 Port 3 Control Registers PORT0 0x0 0x0 0xC registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT4 Port 4 Control Registers PORT0 0x0 0x0 0xC registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT5 Port 5 Control Registers PORT0 0x0 0x0 0xC registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT6 Port 6 Control Registers PORT0 0x0 0x0 0xC registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT7 Port 7 Control Registers PORT0 0x0 0x0 0xC registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PORT8 Port 8 Control Registers PORT0 0x0 0x0 0xC registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PODR00 Pmn Output Data 16 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 17 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 18 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 19 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 20 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 21 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 22 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 23 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 24 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 25 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 26 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 27 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 28 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 29 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 30 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 31 read-write 0 Low output #0 1 High output #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR00 Pmn Output Reset 16 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 17 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 18 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 19 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 20 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 21 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 22 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 23 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 24 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 25 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 26 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 27 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 28 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 29 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 30 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 31 write-only 0 No effect on output #0 1 Low output #1 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 PDR Port Control Register 1 PCNTR1 0x2 16 read-write n 0x0 0x0 PDR00 Pmn Direction 0 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR01 Pmn Direction 1 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR02 Pmn Direction 2 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR03 Pmn Direction 3 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR04 Pmn Direction 4 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR05 Pmn Direction 5 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR06 Pmn Direction 6 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR07 Pmn Direction 7 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR08 Pmn Direction 8 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR09 Pmn Direction 9 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR10 Pmn Direction 10 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR11 Pmn Direction 11 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR12 Pmn Direction 12 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR13 Pmn Direction 13 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR14 Pmn Direction 14 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PDR15 Pmn Direction 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin) #1 PIDR Port Control Register 2 PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR00 Pmn State 0 read-only 0 Low level #0 1 High level #1 PIDR01 Pmn State 1 read-only 0 Low level #0 1 High level #1 PIDR02 Pmn State 2 read-only 0 Low level #0 1 High level #1 PIDR03 Pmn State 3 read-only 0 Low level #0 1 High level #1 PIDR04 Pmn State 4 read-only 0 Low level #0 1 High level #1 PIDR05 Pmn State 5 read-only 0 Low level #0 1 High level #1 PIDR06 Pmn State 6 read-only 0 Low level #0 1 High level #1 PIDR07 Pmn State 7 read-only 0 Low level #0 1 High level #1 PIDR08 Pmn State 8 read-only 0 Low level #0 1 High level #1 PIDR09 Pmn State 9 read-only 0 Low level #0 1 High level #1 PIDR10 Pmn State 10 read-only 0 Low level #0 1 High level #1 PIDR11 Pmn State 11 read-only 0 Low level #0 1 High level #1 PIDR12 Pmn State 12 read-only 0 Low level #0 1 High level #1 PIDR13 Pmn State 13 read-only 0 Low level #0 1 High level #1 PIDR14 Pmn State 14 read-only 0 Low level #0 1 High level #1 PIDR15 Pmn State 15 read-only 0 Low level #0 1 High level #1 PODR Port Control Register 1 PCNTR1 0x0 16 read-write n 0x0 0x0 PODR00 Pmn Output Data 0 read-write 0 Low output #0 1 High output #1 PODR01 Pmn Output Data 1 read-write 0 Low output #0 1 High output #1 PODR02 Pmn Output Data 2 read-write 0 Low output #0 1 High output #1 PODR03 Pmn Output Data 3 read-write 0 Low output #0 1 High output #1 PODR04 Pmn Output Data 4 read-write 0 Low output #0 1 High output #1 PODR05 Pmn Output Data 5 read-write 0 Low output #0 1 High output #1 PODR06 Pmn Output Data 6 read-write 0 Low output #0 1 High output #1 PODR07 Pmn Output Data 7 read-write 0 Low output #0 1 High output #1 PODR08 Pmn Output Data 8 read-write 0 Low output #0 1 High output #1 PODR09 Pmn Output Data 9 read-write 0 Low output #0 1 High output #1 PODR10 Pmn Output Data 10 read-write 0 Low output #0 1 High output #1 PODR11 Pmn Output Data 11 read-write 0 Low output #0 1 High output #1 PODR12 Pmn Output Data 12 read-write 0 Low output #0 1 High output #1 PODR13 Pmn Output Data 13 read-write 0 Low output #0 1 High output #1 PODR14 Pmn Output Data 14 read-write 0 Low output #0 1 High output #1 PODR15 Pmn Output Data 15 read-write 0 Low output #0 1 High output #1 PORR Port Control Register 3 PCNTR3 0x8 16 write-only n 0x0 0x0 PORR00 Pmn Output Reset 0 write-only 0 No effect on output #0 1 Low output #1 PORR01 Pmn Output Reset 1 write-only 0 No effect on output #0 1 Low output #1 PORR02 Pmn Output Reset 2 write-only 0 No effect on output #0 1 Low output #1 PORR03 Pmn Output Reset 3 write-only 0 No effect on output #0 1 Low output #1 PORR04 Pmn Output Reset 4 write-only 0 No effect on output #0 1 Low output #1 PORR05 Pmn Output Reset 5 write-only 0 No effect on output #0 1 Low output #1 PORR06 Pmn Output Reset 6 write-only 0 No effect on output #0 1 Low output #1 PORR07 Pmn Output Reset 7 write-only 0 No effect on output #0 1 Low output #1 PORR08 Pmn Output Reset 8 write-only 0 No effect on output #0 1 Low output #1 PORR09 Pmn Output Reset 9 write-only 0 No effect on output #0 1 Low output #1 PORR10 Pmn Output Reset 10 write-only 0 No effect on output #0 1 Low output #1 PORR11 Pmn Output Reset 11 write-only 0 No effect on output #0 1 Low output #1 PORR12 Pmn Output Reset 12 write-only 0 No effect on output #0 1 Low output #1 PORR13 Pmn Output Reset 13 write-only 0 No effect on output #0 1 Low output #1 PORR14 Pmn Output Reset 14 write-only 0 No effect on output #0 1 Low output #1 PORR15 Pmn Output Reset 15 write-only 0 No effect on output #0 1 Low output #1 POSR Port Control Register 3 PCNTR3 0xA 16 write-only n 0x0 0x0 POSR00 Pmn Output Set 0 write-only 0 No effect on output #0 1 High output #1 POSR01 Pmn Output Set 1 write-only 0 No effect on output #0 1 High output #1 POSR02 Pmn Output Set 2 write-only 0 No effect on output #0 1 High output #1 POSR03 Pmn Output Set 3 write-only 0 No effect on output #0 1 High output #1 POSR04 Pmn Output Set 4 write-only 0 No effect on output #0 1 High output #1 POSR05 Pmn Output Set 5 write-only 0 No effect on output #0 1 High output #1 POSR06 Pmn Output Set 6 write-only 0 No effect on output #0 1 High output #1 POSR07 Pmn Output Set 7 write-only 0 No effect on output #0 1 High output #1 POSR08 Pmn Output Set 8 write-only 0 No effect on output #0 1 High output #1 POSR09 Pmn Output Set 9 write-only 0 No effect on output #0 1 High output #1 POSR10 Pmn Output Set 10 write-only 0 No effect on output #0 1 High output #1 POSR11 Pmn Output Set 11 write-only 0 No effect on output #0 1 High output #1 POSR12 Pmn Output Set 12 write-only 0 No effect on output #0 1 High output #1 POSR13 Pmn Output Set 13 write-only 0 No effect on output #0 1 High output #1 POSR14 Pmn Output Set 14 write-only 0 No effect on output #0 1 High output #1 POSR15 Pmn Output Set 15 write-only 0 No effect on output #0 1 High output #1 RMPU Renesas Memory Protection Unit RMPU 0x0 0x0 0x2 registers n 0x102 0x2 registers n 0x200 0x48 registers n 0xC00 0x2 registers n 0xC10 0x2 registers n 0xC14 0x2 registers n 0xC18 0x2 registers n 0xC20 0x2 registers n 0xC24 0x2 registers n 0xC28 0x2 registers n 0xD00 0x2 registers n 0xD04 0xE registers n 0xD14 0xC registers n MMPUACA0 Group A Region %s access control register 0x200 16 read-write n 0x0 0x0 ENABLE Region Enable 0 read-write 0 Group A region n disabled #0 1 Group A region n enabled #1 RP Read Protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write Protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA1 Group A Region %s access control register 0x210 16 read-write n 0x0 0x0 ENABLE Region Enable 0 read-write 0 Group A region n disabled #0 1 Group A region n enabled #1 RP Read Protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write Protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA2 Group A Region %s access control register 0x220 16 read-write n 0x0 0x0 ENABLE Region Enable 0 read-write 0 Group A region n disabled #0 1 Group A region n enabled #1 RP Read Protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write Protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA3 Group A Region %s access control register 0x230 16 read-write n 0x0 0x0 ENABLE Region Enable 0 read-write 0 Group A region n disabled #0 1 Group A region n enabled #1 RP Read Protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write Protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUCTLA Bus Master MPU Control Register 0x0 16 read-write n 0x0 0x0 ENABLE Master Group Enable 0 read-write 0 Master group A disabled #0 1 Master group A enabled #1 KEY Key Code 8 7 read-write OAD Operation After Detection 1 read-write 0 Non-maskable interrupt #0 1 Reset #1 MMPUEA0 Group A Region %s End Address Register 0x208 32 read-write n 0x0 0x0 MMPUEA Region End Address 0 31 read-write MMPUEA1 Group A Region %s End Address Register 0x218 32 read-write n 0x0 0x0 MMPUEA Region End Address 0 31 read-write MMPUEA2 Group A Region %s End Address Register 0x228 32 read-write n 0x0 0x0 MMPUEA Region End Address 0 31 read-write MMPUEA3 Group A Region %s End Address Register 0x238 32 read-write n 0x0 0x0 MMPUEA Region End Address 0 31 read-write MMPUPTA Group A Protection of Register 0x102 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write PROTECT Protection of Register 0 read-write 0 All bus master MPU group A register writes are permitted. #0 1 All bus master MPU group A register writes are protected. Reads are permitted. #1 MMPUSA0 Group A Region %s Start Address Register 0x204 32 read-write n 0x0 0x0 MMPUSA Region Start Address 0 31 read-write MMPUSA1 Group A Region %s Start Address Register 0x214 32 read-write n 0x0 0x0 MMPUSA Region Start Address 0 31 read-write MMPUSA2 Group A Region %s Start Address Register 0x224 32 read-write n 0x0 0x0 MMPUSA Region Start Address 0 31 read-write MMPUSA3 Group A Region %s Start Address Register 0x234 32 read-write n 0x0 0x0 MMPUSA Region Start Address 0 31 read-write MSPMPUCTL Stack Pointer Monitor Access Control Register 0xD04 16 read-write n 0x0 0x0 ENABLE Stack Pointer Monitor Enable 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 ERROR Stack Pointer Monitor Error Flag 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 MSPMPUEA Main Stack Pointer (MSP) Monitor End Address Register 0xD0C 32 read-write n 0x0 0x0 MSPMPUEA Region End Address 0 31 read-write MSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD00 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write OAD Operation after Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 MSPMPUPT Stack Pointer Monitor Protection Register 0xD06 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write PROTECT Protection of Register 0 read-write 0 Stack pointer monitor register writes are permitted. #0 1 Stack pointer monitor register writes are protected. Reads are permitted #1 MSPMPUSA Main Stack Pointer (MSP) Monitor Start Address Register 0xD08 32 read-write n 0x0 0x0 MSPMPUSA Region Start Address 0 31 read-write PSPMPUCTL Stack Pointer Monitor Access Control Register 0xD14 16 read-write n 0x0 0x0 ENABLE Stack Pointer Monitor Enable 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 ERROR Stack Pointer Monitor Error Flag 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 PSPMPUEA Process Stack Pointer (PSP) Monitor End Address Register 0xD1C 32 read-write n 0x0 0x0 PSPMPUEA Region End Address 0 31 read-write PSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD10 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write OAD Operation after Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 PSPMPUPT Stack Pointer Monitor Protection Register 0xD16 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write PROTECT Protection of Register 0 read-write 0 Stack pointer monitor register writes are permitted. #0 1 Stack pointer monitor register writes are protected. Reads are permitted #1 PSPMPUSA Process Stack Pointer (PSP) Monitor Start Address Register 0xD18 32 read-write n 0x0 0x0 PSPMPUSA Region Start Address 0 31 read-write SMPUCTL Slave MPU Control Register 0xC00 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write OAD Operation After Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 PROTECT Protection of Register 1 read-write 0 All bus slave register writes are permitted #0 1 All bus slave register writes are protected. Reads are permitted #1 SMPUFBIU Access Control Register for Internal Peripheral Bus 9 0xC14 16 read-write n 0x0 0x0 RPCPU CPU Read Protection 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 RPGRPA Master MPU Group A Read Protection 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPCPU CPU Write Protection 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 WPGRPA Master MPU Group A Write Protection 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 SMPUMBIU Access Control Register for Memory Bus 1 0xC10 16 read-write n 0x0 0x0 RPGRPA Master MPU Group A Read Protection 2 read-write 0 Memory protection read for master MPU group A disabled #0 1 Memory protection read for master MPU group A enabled #1 WPGRPA Master MPU Group A Write Protection 3 read-write 0 Memory protection write for master MPU group A disabled #0 1 Memory protection write for master MPU group A enabled #1 SMPUP0BIU Access Control Register for Internal Peripheral Bus 1 0xC20 16 read-write n 0x0 0x0 RPCPU CPU Read Protection 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 RPGRPA Master MPU Group A Read Protection 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPCPU CPU Write Protection 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 WPGRPA Master MPU Group A Write Protection 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 SMPUP2BIU Access Control Register for Internal Peripheral Bus 3 0xC24 16 read-write n 0x0 0x0 RPCPU CPU Read Protection 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 RPGRPA Master MPU Group A Read Protection 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPCPU CPU Write Protection 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 WPGRPA Master MPU Group A Write Protection 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 SMPUP6BIU Access Control Register for Internal Peripheral Bus 7 0xC28 16 read-write n 0x0 0x0 RPCPU CPU Read Protection 0 read-write 0 CPU read of memory protection disabled #0 1 CPU read of memory protection enabled #1 RPGRPA Master MPU Group A Read Protection 2 read-write 0 Master MPU group A read of memory protection disabled #0 1 Master MPU group A read of memory protection enabled #1 WPCPU CPU Write Protection 1 read-write 0 CPU write of memory protection disabled #0 1 CPU write of memory protection enabled #1 WPGRPA Master MPU Group A Write Protection 3 read-write 0 Master MPU group A write of memory protection disabled #0 1 Master MPU group A write of memory protection enabled #1 SMPUSRAM0 Access Control Register for Memory Bus 4 0xC18 16 read-write n 0x0 0x0 RPCPU CPU Read Protection 0 read-write 0 Memory protection for CPU read disabled #0 1 Memory protection for CPU read enabled #1 RPGRPA Master MPU Group A Read Protection 2 read-write 0 Memory protection for master MPU group A read disabled #0 1 Memory protection for master MPU group A read enabled #1 WPCPU CPU Write Protection 1 read-write 0 Memory protection for CPU write disabled #0 1 Memory protection for CPU write enabled #1 WPGRPA Master MPU Group A Write Protection 3 read-write 0 Memory protection for master MPU group A write disabled #0 1 Memory protection for master MPU group A write enabled #1 RTC Realtime Clock RTC 0x0 0x0 0x1 registers n 0x18 0x4 registers n 0x1C 0x3 registers n 0x2 0x8 registers n 0x22 0x1 registers n 0x24 0x1 registers n 0x28 0x1 registers n 0x2A 0x5 registers n 0xA 0x1 registers n 0xC 0x1 registers n 0xE 0xA registers n BCNT0 Binary Counter %s 0x2 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT0AER Binary Counter %s Alarm Enable Register 0x18 8 read-write n 0x0 0x0 BCNT0AR Binary Counter %s Alarm Register 0x10 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write BCNT1 Binary Counter %s 0x4 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT1AER Binary Counter %s Alarm Enable Register 0x1A 8 read-write n 0x0 0x0 BCNT1AR Binary Counter %s Alarm Register 0x12 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write BCNT2 Binary Counter %s 0x6 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT2AER Binary Counter 2 Alarm Enable Register 0x1C 16 read-write n 0x0 0x0 BCNT2AR Binary Counter %s Alarm Register 0x14 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write BCNT3 Binary Counter %s 0x8 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT3AER Binary Counter 3 Alarm Enable Register 0x1E 8 read-write n 0x0 0x0 BCNT3AR Binary Counter %s Alarm Register 0x16 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write R64CNT 64-Hz Counter 0x0 8 read-only n 0x0 0x0 F16HZ 16-Hz Flag 2 read-only F1HZ 1-Hz Flag 6 read-only F2HZ 2-Hz Flag 5 read-only F32HZ 32-Hz Flag 1 read-only F4HZ 4-Hz Flag 4 read-only F64HZ 64-Hz Flag 0 read-only F8HZ 8-Hz Flag 3 read-only R64OVF 7 read-only RADJ Time Error Adjustment Register 0x2E 8 read-write n 0x0 0x0 ADJ Adjustment Value 0 5 read-write PMADJ Plus-Minus 6 1 read-write 00 Do not perform adjustment. #00 01 In normal operation mode, adjustment is performed by the addition to the prescaler. In low-consumption clock mode, adjustment is performed by the addition to the 64-Hz counter. #01 10 In normal operation mode, adjustment is performed by the subtraction from the prescaler. In low-consumption clock mode, adjustment is performed by the subtraction from the 64-Hz counter. #10 11 Setting prohibited. #11 RCR1 RTC Control Register 1 0x22 8 read-write n 0x0 0x0 AIE Alarm Interrupt Enable 0 read-write 0 Disable alarm interrupt requests #0 1 Enable alarm interrupt requests #1 CIE Carry Interrupt Enable 1 read-write 0 Disable carry interrupt requests #0 1 Enable carry interrupt requests #1 PES Periodic Interrupt Select 4 3 read-write Others Do not generate periodic interrupts 0x6 Generate periodic interrupt every 1/256 second 0x6 0x7 Generate periodic interrupt every 1/128 second 0x7 0x8 Generate periodic interrupt every 1/64 second 0x8 0x9 Generate periodic interrupt every 1/32 second 0x9 0xA Generate periodic interrupt every 1/16 second 0xa 0xB Generate periodic interrupt every 1/8 second 0xb 0xC Generate periodic interrupt every 1/4 second 0xc 0xD Generate periodic interrupt every 1/2 second 0xd 0xE Generate periodic interrupt every 1 second 0xe 0xF Generate periodic interrupt every 2 seconds 0xf PIE Periodic Interrupt Enable 2 read-write 0 Disable periodic interrupt requests #0 1 Enable periodic interrupt requests #1 RTCOS RTCOUT Output Select 3 read-write 0 Outputs 1 Hz on RTCOUT #0 1 Outputs 64 Hz RTCOUT #1 RCR2 RTC Control Register 2 (in Calendar Count Mode) 0x24 8 read-write n 0x0 0x0 AADJE Automatic Adjustment Enable 4 read-write 0 Disable automatic adjustment #0 1 Enable automatic adjustment #1 AADJP Automatic Adjustment Period Select 5 read-write 0 In normal operation mode, adjust RADJ.ADJ[5:0] setting from the count value of the prescaler every minute. In low-consumption clock mode, adjust RADJ.ADJ[5:0] setting from the count value of the 64-Hz counter every day. #0 1 In normal operation mode, adjust RADJ.ADJ[5:0] setting from the count value of the prescaler every 10 seconds. In low-consumption clock mode, adjust RADJ.ADJ[5:0] setting from the count value of the 64-Hz counter every hour. #1 ADJ30 30-Second Adjustment 2 read-write 0 In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or 30-second adjustment has completed. #0 1 In writing: Execute 30-second adjustment. In reading: 30-second adjustment in progress. #1 CNTMD Count Mode Select 7 read-write 0 Calendar count mode #0 1 Binary count mode #1 HR24 Hours Mode 6 read-write 0 Operate RTC in 12-hour mode #0 1 Operate RTC in 24-hour mode #1 RESET RTC Software Reset 1 read-write 0 In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or an RTC software reset has completed. #0 1 In writing: Initialize the prescaler and target registers for RTC software reset. In reading: RTC software reset in progress. #1 RTCOE RTCOUT Output Enable 3 read-write 0 Disable RTCOUT output #0 1 Enable RTCOUT output #1 START Start 0 read-write 0 Stop prescaler and time counter #0 1 Operate prescaler and time counter normally #1 RCR2_BCNT RTC Control Register 2 (in Binary Count Mode) RCR2 0x24 8 read-write n 0x0 0x0 AADJE Automatic Adjustment Enable 4 read-write 0 Disable automatic adjustment #0 1 Enable automatic adjustment #1 AADJP Automatic Adjustment Period Select 5 read-write 0 In normal operation mode, add or subtract the RADJ.ADJ[5:0] bits from the prescaler count value every 32 seconds. In low-consumption clock mode, add or subtract the RADJ.ADJ[5:0] bits from the 64-Hz counter count value every 8192 seconds. #0 1 In normal operation mode, add or subtract the RADJ.ADJ[5:0] bits from the prescaler count value every 8 seconds. In low-consumption clock mode, add or subtract the RADJ.ADJ[5:0] bits from the 64-Hz counter count value every 2048 seconds. #1 CNTMD Count Mode Select 7 read-write 0 Calendar count mode #0 1 Binary count mode #1 RESET RTC Software Reset 1 read-write 0 In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or an RTC software reset has completed. #0 1 In writing: Initialize the prescaler and target registers for RTC software reset. In reading: RTC software reset in progress. #1 RTCOE RTCOUT Output Enable 3 read-write 0 Disable RTCOUT output #0 1 Enable RTCOUT output #1 START Start 0 read-write 0 Stop the 32-bit binary counter, 64-Hz counter, and prescaler #0 1 Operate the 32-bit binary counter, 64-Hz counter, and prescaler normally #1 RCR4 RTC Control Register 4 0x28 8 read-write n 0x0 0x0 RCKSEL Count Source Select in normal operation mode 0 read-write 0 Sub-clock oscillator is selected #0 1 LOCO is selected #1 ROPSEL RTC Operation Mode Select 7 read-write 0 Normal operation mode is selected. #0 1 Low-consumption clock mode is selected. #1 RDAYAR Date Alarm Register (in Calendar Count Mode) 0x18 8 read-write n 0x0 0x0 DATE1 1 Day 0 3 read-write DATE10 10 Days 4 1 read-write ENB ENB 7 read-write 0 Do not compare register value with RDAYCNT counter value #0 1 Compare register value with RDAYCNT counter value #1 RDAYCNT Day Counter 0xA 8 read-write n 0x0 0x0 DATE1 1-Day Count 0 3 read-write DATE10 10-Day Count 4 1 read-write RFRH Frequency Register H 0x2A 16 read-write n 0x0 0x0 RFC16 Write 0 before writing to the RFRL register after a cold start. 0 read-write RFRL Frequency Register L 0x2C 16 read-write n 0x0 0x0 RFC Frequency Comparison Value 0 15 read-write RHRAR Hour Alarm Register (in Calendar Count Mode) 0x14 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RHRCNT counter value #0 1 Compare register value with RHRCNT counter value #1 HR1 1 Hour 0 3 read-write HR10 10 Hours 4 1 read-write PM AM/PM select for alarm setting. 6 read-write 0 AM #0 1 PM #1 RHRCNT Hour Counter (in Calendar Count Mode) 0x6 8 read-write n 0x0 0x0 HR1 1-Hour Count 0 3 read-write HR10 10-Hour Count 4 1 read-write PM AM/PM select for time counter setting. 6 read-write 0 AM #0 1 PM #1 RMINAR Minute Alarm Register (in Calendar Count Mode) 0x12 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RMINCNT counter value #0 1 Compare register value with RMINCNT counter value #1 MIN1 1 Minute 0 3 read-write MIN10 10 Minutes 4 2 read-write RMINCNT Minute Counter (in Calendar Count Mode) 0x4 8 read-write n 0x0 0x0 MIN1 1-Minute Count 0 3 read-write MIN10 10-Minute Count 4 2 read-write RMONAR Month Alarm Register (in Calendar Count Mode) 0x1A 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RMONCNT counter value #0 1 Compare register value with RMONCNT counter value #1 MON1 1 Month 0 3 read-write MON10 10 Months 4 read-write RMONCNT Month Counter 0xC 8 read-write n 0x0 0x0 MON1 1-Month Count 0 3 read-write MON10 10-Month Count 4 read-write RSECAR Second Alarm Register (in Calendar Count Mode) 0x10 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RSECCNT counter value #0 1 Compare register value with RSECCNT counter value #1 SEC1 1 Second 0 3 read-write SEC10 10 Seconds 4 2 read-write RSECCNT Second Counter (in Calendar Count Mode) 0x2 8 read-write n 0x0 0x0 SEC1 1-Second Count 0 3 read-write SEC10 10-Second Count 4 2 read-write RWKAR Day-of-Week Alarm Register (in Calendar Count Mode) 0x16 8 read-write n 0x0 0x0 DAYW Day-of-Week Setting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting prohibited #111 ENB ENB 7 read-write 0 Do not compare register value with RWKCNT counter value #0 1 Compare register value with RWKCNT counter value #1 RWKCNT Day-of-Week Counter (in Calendar Count Mode) 0x8 8 read-write n 0x0 0x0 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting prohibited #111 RYRAR Year Alarm Register (in Calendar Count Mode) BCNT2AER 0x1C 16 read-write n 0x0 0x0 YR1 1 Year 0 3 read-write YR10 10 Years 4 3 read-write RYRAREN Year Alarm Enable Register (in Calendar Count Mode) BCNT3AER 0x1E 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with the RYRCNT counter value #0 1 Compare register value with the RYRCNT counter value #1 RYRCNT Year Counter 0xE 16 read-write n 0x0 0x0 YR1 1-Year Count 0 3 read-write YR10 10-Year Count 4 3 read-write SCI0 Serial Communication Interface SCI0 0x0 0x0 0x1D registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Serial receive data 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Serial receive data 0 7 read-only FTDRH Transmit FIFO Data Register FRDRHL 0x10 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register FRDRHL 0x10 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FRDRL 0x11 8 write-only n 0x0 0x0 TDAT Serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL - 1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write SCI1 Serial Communication Interface SCI0 0x0 0x0 0x1D registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Serial receive data 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Serial receive data 0 7 read-only FTDRH Transmit FIFO Data Register FRDRHL 0x10 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register FRDRHL 0x10 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FRDRL 0x11 8 write-only n 0x0 0x0 TDAT Serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL - 1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write SCI2 Serial Communication Interface SCI0 0x0 0x0 0x1D registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Serial receive data 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Serial receive data 0 7 read-only FTDRH Transmit FIFO Data Register FRDRHL 0x10 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register FRDRHL 0x10 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FRDRL 0x11 8 write-only n 0x0 0x0 TDAT Serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL - 1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write SCI9 Serial Communication Interface SCI0 0x0 0x0 0x1D registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Serial receive data 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Serial receive data 0 7 read-only FTDRH Transmit FIFO Data Register FRDRHL 0x10 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register FRDRHL 0x10 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FRDRL 0x11 8 write-only n 0x0 0x0 TDAT Serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR contents are transmitted as they are. Received data is stored as received in the RDR register. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL - 1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write SPI0 Serial Peripheral Interface SPI0 0x0 0x0 0x8 registers n 0xA 0x8 registers n SPBR SPI Bit Rate Register 0xA 8 read-write n 0x0 0x0 SPCKD SPI Clock Delay Register 0xC 8 read-write n 0x0 0x0 SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPCMD0 SPI Command Register 0 0x10 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 Base bit rate #00 01 Base bit rate divided by 2 #01 10 Base bit rate divided by 4 #10 11 Base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Select data sampling on leading edge, data change on trailing edge #0 1 Select data change on leading edge, data sampling on trailing edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 Set RSPCK low during idle #0 1 Set RSPCK high during idle #1 LSBF SPI LSB First 12 read-write 0 MSB-first #0 1 LSB-first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 Select RSPCK delay of 1 RSPCK #0 1 Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 Select SSL negation delay of 1 RSPCK #0 1 Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND) #1 SPB SPI Data Length Setting 8 3 read-write Others 8 bits 0x0 20 bits 0x0 0x1 24 bits 0x1 0x2 32 bits 0x2 0x3 32 bits 0x3 0x8 9 bits 0x8 0x9 10 bits 0x9 0xA 11 bits 0xa 0xB 12 bits 0xb 0xC 13 bits 0xc 0xD 14 bits 0xd 0xE 15 bits 0xe 0xF 16 bits 0xf SPNDEN SPI Next-Access Delay Enable 13 read-write 0 Select next-access delay of 1 RSPCK + 2 PCLKB #0 1 Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write Others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SPCR SPI Control Register 0x0 8 read-write n 0x0 0x0 MODFEN Mode Fault Error Detection Enable 2 read-write 0 Disable detection of mode fault errors #0 1 Enable detection of mode fault errors #1 MSTR SPI Master/Slave Mode Select 3 read-write 0 Select slave mode #0 1 Select master mode #1 SPE SPI Function Enable 6 read-write 0 Disable SPI function #0 1 Enable SPI function #1 SPEIE SPI Error Interrupt Enable 4 read-write 0 Disable SPI error interrupt requests #0 1 Enable SPI error interrupt requests #1 SPMS SPI Mode Select 0 read-write 0 Select SPI operation (4-wire method) #0 1 Select clock synchronous operation (3-wire method) #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 read-write 0 Disable SPI receive buffer full interrupt requests #0 1 Enable SPI receive buffer full interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 read-write 0 Disable transmit buffer empty interrupt requests #0 1 Enable transmit buffer empty interrupt requests #1 TXMD Communications Operating Mode Select 1 read-write 0 Select full-duplex synchronous serial communications #0 1 Select serial communications with transmit-only #1 SPCR2 SPI Control Register 2 0xF 8 read-write n 0x0 0x0 PTE Parity Self-Testing 3 read-write 0 Disable self-diagnosis function of the parity circuit #0 1 Enable self-diagnosis function of the parity circuit #1 SCKASE RSPCK Auto-Stop Function Enable 4 read-write 0 Disable RSPCK auto-stop function #0 1 Enable RSPCK auto-stop function #1 SPIIE SPI Idle Interrupt Enable 2 read-write 0 Disable idle interrupt requests #0 1 Enable idle interrupt requests #1 SPOE Parity Mode 1 read-write 0 Select even parity for transmission and reception #0 1 Select odd parity for transmission and reception #1 SPPE Parity Enable 0 read-write 0 Do not add parity bit to transmit data and do not check parity bit of receive data #0 1 When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data #1 SPDCR SPI Data Control Register 0xB 8 read-write n 0x0 0x0 SPLW SPI Word Access/Halfword Access Specification 5 read-write 0 Set SPDR_HA to valid for halfword access #0 1 Set SPDR to valid for word access #1 SPRDTD SPI Receive/Transmit Data Select 4 read-write 0 Read SPDR/SPDR_HA values from receive buffer #0 1 Read SPDR/SPDR_HA values from transmit buffer, but only if the transmit buffer is empty #1 SPDR SPI Data Register 0x4 32 read-write n 0x0 0x0 SPDR_HA SPI Data Register SPDR 0x4 16 read-write n 0x0 0x0 SPND SPI Next-Access Delay Register 0xE 8 read-write n 0x0 0x0 SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLKB #000 001 2 RSPCK + 2 PCLKB #001 010 3 RSPCK + 2 PCLKB #010 011 4 RSPCK + 2 PCLKB #011 100 5 RSPCK + 2 PCLKB #100 101 6 RSPCK + 2 PCLKB #101 110 7 RSPCK + 2 PCLKB #110 111 8 RSPCK + 2 PCLKB #111 SPPCR SPI Pin Control Register 0x2 8 read-write n 0x0 0x0 MOIFE MOSI Idle Value Fixing Enable 5 read-write 0 Set MOSI output value to equal final data from previous transfer #0 1 Set MOSI output value to equal value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 read-write 0 Set level output on MOSIn pin during MOSI idling to low #0 1 Set level output on MOSIn pin during MOSI idling to high #1 SPLP SPI Loopback 0 read-write 0 Normal mode #0 1 Loopback mode (receive data = inverted transmit data) #1 SPLP2 SPI Loopback 2 1 read-write 0 Normal mode #0 1 Loopback mode (receive data = transmit data) #1 SPSR SPI Status Register 0x3 8 read-write n 0x0 0x0 IDLNF SPI Idle Flag 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 read-write 0 No mode fault or underrun error occurred #0 1 Mode fault error or underrun error occurred #1 OVRF Overrun Error Flag 0 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PERF Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 SPRF SPI Receive Buffer Full Flag 7 read-write 0 No valid data is in SPDR/SPDR_HA #0 1 Valid data is in SPDR/SPDR_HA #1 SPTEF SPI Transmit Buffer Empty Flag 5 read-write 0 Data is in the transmit buffer #0 1 No data is in the transmit buffer #1 UDRF Underrun Error Flag 4 read-write 0 Mode fault error occurred (MODF = 1) #0 1 Underrun error occurred (MODF = 1) #1 SSLND SPI Slave Select Negation Delay Register 0xD 8 read-write n 0x0 0x0 SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLP SPI Slave Select Polarity Register 0x1 8 read-write n 0x0 0x0 SSL0P SSLn0 Signal Polarity Setting 0 read-write 0 Set SSLn0 signal to active-low #0 1 Set SSLn0 signal to active-high #1 SSL1P SSLn1 Signal Polarity Setting 1 read-write 0 Set SSLn1 signal to active-low #0 1 Set SSLn1 signal to active-high #1 SSL2P SSLn2 Signal Polarity Setting 2 read-write 0 Set SSLn2 signal to active-low #0 1 Set SSLn2 signal to active-high #1 SSL3P SSLn3 Signal Polarity Setting 3 read-write 0 Set SSLn3 signal to active-low #0 1 Set SSLn3 signal to active-high #1 SRAM SRAM Control SRAM 0x0 0x0 0x1 registers n 0x4 0x1 registers n PARIOAD SRAM Parity Error Operation After Detection Register 0x0 8 read-write n 0x0 0x0 OAD Operation After Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 SRAMPRCR SRAM Protection Register 0x4 8 read-write n 0x0 0x0 KW Write Key Code 1 6 write-only SRAMPRCR Register Write Control 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 SYSC System Control SYSC 0x0 0x1C 0x8 registers n 0x26 0x1 registers n 0x31 0x2 registers n 0x36 0x1 registers n 0x38 0x1 registers n 0x3C 0x1 registers n 0x3E 0x1 registers n 0x3FE 0x2 registers n 0x40 0x2 registers n 0x40E 0x1 registers n 0x410 0x2 registers n 0x413 0x1 registers n 0x417 0x2 registers n 0x41A 0x2 registers n 0x480 0x3 registers n 0x490 0x1 registers n 0x492 0x1 registers n 0x4C 0x1 registers n 0x61 0x2 registers n 0x92 0x1 registers n 0x94 0x1 registers n 0x98 0x4 registers n 0x9F 0x2 registers n 0xA2 0x1 registers n 0xAA 0x1 registers n 0xC 0x2 registers n 0xC0 0x2 registers n 0xE0 0x4 registers n CKOCR Clock Out Control Register 0x3E 8 read-write n 0x0 0x0 CKODIV Clock Output Frequency Division Ratio 4 2 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 111 x 1/128 #111 CKOEN Clock Out Enable 7 read-write 0 Disable clock out #0 1 Enable clock out #1 CKOSEL Clock Out Source Select 0 2 read-write Others Setting prohibited 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 SOSC #100 101 Setting prohibited #101 HOCOCR High-Speed On-Chip Oscillator Control Register 0x36 8 read-write n 0x0 0x0 HCSTP HOCO Stop 0 read-write 0 Operate the HOCO clock #0 1 Stop the HOCO clock #1 HOCOUTCR HOCO User Trimming Control Register 0x62 8 read-write n 0x0 0x0 HOCOUTRM HOCO User Trimming 0 7 read-write LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write n 0x0 0x0 LCSTP LOCO Stop 0 read-write 0 Operate the LOCO clock #0 1 Stop the LOCO clock #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write n 0x0 0x0 LOCOUTRM LOCO User Trimming 0 7 read-write LPOPT Lower Power Operation Control Register 0x4C 8 read-write n 0x0 0x0 BPFCLKDIS BPF Clock Disable Control 3 read-write 0 Flash register R/W clock operates as normal #0 1 Flash register R/W clock stops. #1 DCLKDIS Debug Clock Disable Control 1 1 read-write Others Debug clock stops (valid only when LPOPT.LPOPTEN = 1) 00 Debug clock does not stop #00 LPOPTEN Lower Power Operation Enable 7 read-write 0 All lower power counter measure disable #0 1 All lower power counter measure enable #1 MPUDIS MPU Clock Disable Control 0 read-write 0 MPU operates as normal #0 1 MPU operate clock stops (MPU function disable). #1 LVCMPCR Voltage Monitor Circuit Control Register 0x417 8 read-write n 0x0 0x0 LVD1E Voltage Detection 1 Enable 5 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVD2E Voltage Detection 2 Enable 6 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVD1CR0 Voltage Monitor 1 Circuit Control Register 0 0x41A 8 read-write n 0x0 0x0 CMPE Voltage Monitor 1 Circuit Comparison Result Output Enable 2 read-write 0 Disable voltage monitor 1 circuit comparison result output #0 1 Enable voltage monitor 1 circuit comparison result output #1 RI Voltage Monitor 1 Circuit Mode Select 6 read-write 0 Generate voltage monitor 1 interrupt on Vdet1 crossing #0 1 Enable voltage monitor 1 reset when the voltage falls to and below Vdet1 #1 RIE Voltage Monitor 1 Interrupt/Reset Enable 0 read-write 0 Disable #0 1 Enable #1 RN Voltage Monitor 1 Reset Negate Select 7 read-write 0 Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected #0 1 Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset #1 LVD1CR1 Voltage Monitor 1 Circuit Control Register 0xE0 8 read-write n 0x0 0x0 IDTSEL Voltage Monitor 1 Interrupt Generation Condition Select 0 1 read-write 00 When VCC >= Vdet1 (rise) is detected #00 01 When VCC < Vdet1 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 1 Interrupt Type Select 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD1SR Voltage Monitor 1 Circuit Status Register 0xE1 8 read-write n 0x0 0x0 DET Voltage Monitor 1 Voltage Variation Detection Flag 0 read-write 0 Not detected #0 1 Vdet1 crossing is detected #1 MON Voltage Monitor 1 Signal Monitor Flag 1 read-only 0 VCC < Vdet1 #0 1 VCC >= Vdet1 or MON is disabled #1 LVD2CR0 Voltage Monitor 2 Circuit Control Register 0 0x41B 8 read-write n 0x0 0x0 CMPE Voltage Monitor 2 Circuit Comparison Result Output Enable 2 read-write 0 Disable voltage monitor 2 circuit comparison result output #0 1 Enable voltage monitor 2 circuit comparison result output #1 RI Voltage Monitor 2 Circuit Mode Select 6 read-write 0 Generate voltage monitor 2 interrupt on Vdet2 crossing #0 1 Enable voltage monitor 2 reset when the voltage falls to and below Vdet2 #1 RIE Voltage Monitor 2 Interrupt/Reset Enable 0 read-write 0 Disable #0 1 Enable #1 RN Voltage Monitor 2 Reset Negate Select 7 read-write 0 Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected #0 1 Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset #1 LVD2CR1 Voltage Monitor 2 Circuit Control Register 1 0xE2 8 read-write n 0x0 0x0 IDTSEL Voltage Monitor 2 Interrupt Generation Condition Select 0 1 read-write 00 When VCC>= Vdet2 (rise) is detected #00 01 When VCC < Vdet2 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 2 Interrupt Type Select 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD2SR Voltage Monitor 2 Circuit Status Register 0xE3 8 read-write n 0x0 0x0 DET Voltage Monitor 2 Voltage Variation Detection Flag 0 read-write 0 Not detected #0 1 Vdet2 crossing is detected #1 MON Voltage Monitor 2 Signal Monitor Flag 1 read-only 0 VCC < Vdet2 #0 1 VCC>= Vdet2 or MON is disabled #1 LVDLVLR Voltage Detection Level Select Register 0x418 8 read-write n 0x0 0x0 LVD1LVL Voltage Detection 1 Level Select (Standard voltage during fall in voltage) 0 4 read-write Others Setting prohibited 0x00 Vdet1_0 0x00 0x01 Vdet1_1 0x01 0x02 Vdet1_2 0x02 0x03 Vdet1_3 0x03 0x04 Vdet1_4 0x04 0x05 Vdet1_5 0x05 0x06 Vdet1_6 0x06 0x07 Vdet1_7 0x07 0x08 Vdet1_8 0x08 0x09 Vdet1_9 0x09 0x0A Vdet1_A 0x0a 0x0B Vdet1_B 0x0b 0x0C Vdet1_C 0x0c 0x0D Vdet1_D 0x0d 0x0E Vdet1_E 0x0e 0x0F Vdet1_F 0x0f LVD2LVL Voltage Detection 2 Level Select (Standard voltage during fall in voltage) 5 2 read-write Others Setting prohibited 000 Vdet2_0 #000 001 Vdet2_1 #001 010 Vdet2_2 #010 011 Vdet2_3 #011 MEMWAIT Memory Wait Cycle Control Register for Code Flash 0x31 8 read-write n 0x0 0x0 MEMWAIT Memory Wait Cycle Select for Code Flash 0 read-write 0 No wait #0 1 Wait #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x38 8 read-write n 0x0 0x0 MCSTP MOCO Stop 0 read-write 0 MOCO clock is operating #0 1 MOCO clock is stopped #1 MOCOUTCR MOCO User Trimming Control Register 0x61 8 read-write n 0x0 0x0 MOCOUTRM MOCO User Trimming 0 7 read-write MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write n 0x0 0x0 MODRV1 Main Clock Oscillator Drive Capability 1 Switching 3 read-write 0 10 MHz to 20 MHz #0 1 1 MHz to 10 MHz #1 MOSEL Main Clock Oscillator Switching 6 read-write 0 Resonator #0 1 External clock input #1 MOSCCR Main Clock Oscillator Control Register 0x32 8 read-write n 0x0 0x0 MOSTP Main Clock Oscillator Stop 0 read-write 0 Operate the main clock oscillator #0 1 Stop the main clock oscillator #1 MOSCWTCR Main Clock Oscillator Wait Control Register 0xA2 8 read-write n 0x0 0x0 MSTS Main Clock Oscillator Wait Time Setting 0 3 read-write Others Setting prohibited 0x0 Wait time = 2 cycles (0.25 us) 0x0 0x1 Wait time = 1024 cycles (128 us) 0x1 0x2 Wait time = 2048 cycles (256 us) 0x2 0x3 Wait time = 4096 cycles (512 us) 0x3 0x4 Wait time = 8192 cycles (1024 us) 0x4 0x5 Wait time = 16384 cycles (2048 us) 0x5 0x6 Wait time = 32768 cycles (4096 us) 0x6 0x7 Wait time = 65536 cycles (8192 us) 0x7 0x8 Wait time = 131072 cycles (16384 us) 0x8 0x9 Wait time = 262144 cycles (32768 us) 0x9 MSTPCRA Module Stop Control Register A 0x1C 32 read-write n 0x0 0x0 MSTPA22 DTC Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 OPCCR Operating Power Control Register 0xA0 8 read-write n 0x0 0x0 OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Middle-speed mode #01 10 Setting prohibited #10 11 Low-speed mode #11 OPCMTSF Operating Power Control Mode Transition Status Flag 4 read-only 0 Transition completed #0 1 During transition #1 OSCSF Oscillation Stabilization Flag Register 0x3C 8 read-only n 0x0 0x0 HOCOSF HOCO Clock Oscillation Stabilization Flag 0 read-only 0 The HOCO clock is stopped or is not yet stable #0 1 The HOCO clock is stable, so is available for use as the system clock #1 MOSCSF Main Clock Oscillation Stabilization Flag 3 read-only 0 The main clock oscillator is stopped (MOSTP = 1) or is not yet stable #0 1 The main clock oscillator is stable, so is available for use as the system clock #1 OSTDCR Oscillation Stop Detection Control Register 0x40 8 read-write n 0x0 0x0 OSTDE Oscillation Stop Detection Function Enable 7 read-write 0 Disable oscillation stop detection function #0 1 Enable oscillation stop detection function #1 OSTDIE Oscillation Stop Detection Interrupt Enable 0 read-write 0 Disable oscillation stop detection interrupt (do not notify the POEG) #0 1 Enable oscillation stop detection interrupt (notify the POEG) #1 OSTDSR Oscillation Stop Detection Status Register 0x41 8 read-write n 0x0 0x0 OSTDF Oscillation Stop Detection Flag 0 read-write 0 Main clock oscillation stop not detected #0 1 Main clock oscillation stop detected #1 PRCR Protect Register 0x3FE 16 read-write n 0x0 0x0 PRC0 Enable writing to the registers related to the clock generation circuit 0 read-write 0 Disable writes #0 1 Enable writes #1 PRC1 Enable writing to the registers related to the low power modes 1 read-write 0 Disable writes #0 1 Enable writes #1 PRC3 Enable writing to the registers related to the LVD 3 read-write 0 Disable writes #0 1 Enable writes #1 PRKEY PRC Key Code 8 7 write-only PSMCR Power Save Memory Control Register 0x9F 8 read-write n 0x0 0x0 PSMC Power Save Memory Control 0 1 read-write 00 All SRAMs are on in Software Standby mode #00 01 8 KB SRAM (0x2000_4000 to 0x2000_5FFF) is on in Software Standby mode #01 10 Setting prohibited #10 11 Setting prohibited #11 RSTSR0 Reset Status Register 0 0x410 8 read-write n 0x0 0x0 LVD0RF Voltage Monitor 0 Reset Detect Flag 1 read-write 0 Voltage monitor 0 reset not detected #0 1 Voltage monitor 0 reset detected #1 LVD1RF Voltage Monitor 1 Reset Detect Flag 2 read-write 0 Voltage monitor 1 reset not detected #0 1 Voltage monitor 1 reset detected #1 LVD2RF Voltage Monitor 2 Reset Detect Flag 3 read-write 0 Voltage monitor 2 reset not detected #0 1 Voltage monitor 2 reset detected #1 PORF Power-On Reset Detect Flag 0 read-write 0 Power-on reset not detected #0 1 Power-on reset detected #1 RSTSR1 Reset Status Register 1 0xC0 16 read-write n 0x0 0x0 BUSMRF Bus Master MPU Error Reset Detect Flag 11 read-write 0 Bus master MPU error reset not detected #0 1 Bus master MPU error reset detected #1 BUSSRF Bus Slave MPU Error Reset Detect Flag 10 read-write 0 Bus slave MPU error reset not detected #0 1 Bus slave MPU error reset detected #1 IWDTRF Independent Watchdog Timer Reset Detect Flag 0 read-write 0 Independent watchdog timer reset not detected #0 1 Independent watchdog timer reset detected #1 RPERF SRAM Parity Error Reset Detect Flag 8 read-write 0 SRAM parity error reset not detected #0 1 SRAM parity error reset detected #1 SPERF CPU Stack Pointer Error Reset Detect Flag 12 read-write 0 CPU stack pointer error reset not detected #0 1 CPU stack pointer error reset detected #1 SWRF Software Reset Detect Flag 2 read-write 0 Software reset not detected #0 1 Software reset detected #1 WDTRF Watchdog Timer Reset Detect Flag 1 read-write 0 Watchdog timer reset not detected #0 1 Watchdog timer reset detected #1 RSTSR2 Reset Status Register 2 0x411 8 read-write n 0x0 0x0 CWSF Cold/Warm Start Determination Flag 0 read-write 0 Cold start #0 1 Warm start #1 SBYCR Standby Control Register 0xC 16 read-write n 0x0 0x0 SSBY Software Standby Mode Select 15 read-write 0 Sleep mode #0 1 Software Standby mode. #1 SCKDIVCR System Clock Division Control Register 0x20 32 read-write n 0x0 0x0 ICK System Clock (ICLK) Select 24 2 read-write Others Settings prohibited 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 PCKB Peripheral Module Clock B (PCLKB) Select 8 2 read-write Others Settings prohibited 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write Others Settings prohibited 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 SCKSCR System Clock Source Control Register 0x26 8 read-write n 0x0 0x0 CKSEL Clock Source Select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator (MOSC) #011 100 Sub-clock oscillator (SOSC) #100 SNZCR Snooze Control Register 0x92 8 read-write n 0x0 0x0 RXDREQEN RXD0 Snooze Request Enable 0 read-write 0 Ignore RXD0 falling edge in Software Standby mode #0 1 Detect RXD0 falling edge in Software Standby mode #1 SNZDTCEN DTC Enable in Snooze mode 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 SNZE Snooze mode Enable 7 read-write 0 Disable Snooze mode #0 1 Enable Snooze mode #1 SNZEDCR0 Snooze End Control Register 0 0x94 8 read-write n 0x0 0x0 AD0MATED AD120 Compare Match Snooze End Enable 3 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0UMTED AD120 Compare Mismatch Snooze End Enable 4 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AGTUNFED AGT1 Underflow Snooze End Enable 0 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SCI0UMTED SCI0 Address Mismatch Snooze End Enable 7 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SNZREQCR0 Snooze Request Control Register 0 0x98 32 read-write n 0x0 0x0 SNZREQEN0 Enable IRQ0 pin snooze request 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable IRQ1 pin snooze request 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN17 Enable KEY_INTKR snooze request 17 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable IRQ2 pin snooze request 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN23 Enable ACMPLP snooze request 23 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN24 Enable RTC alarm snooze request 24 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN25 Enable RTC period snooze request 25 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN28 Enable AGT1 underflow snooze request 28 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN29 Enable AGT1 compare match A snooze request 29 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN3 Enable IRQ3 pin snooze request 3 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN30 Enable AGT1 compare match B snooze request 30 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN4 Enable IRQ4 pin snooze request 4 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN5 Enable IRQ5 pin snooze request 5 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN6 Enable IRQ6 pin snooze request 6 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN7 Enable IRQ7 pin snooze request 7 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SOMCR Sub-Clock Oscillator Mode Control Register 0x481 8 read-write n 0x0 0x0 SODRV Sub-Clock Oscillator Drive Capability Switching 0 1 read-write 00 Normal Mode #00 01 Low Power Mode 1 #01 10 Low Power Mode 2 #10 11 Low Power Mode 3 #11 SOMRG Sub-Clock Oscillator Margin Check Register 0x482 8 read-write n 0x0 0x0 SOSCMRG Sub Clock Oscillator Margin check Switching 0 1 read-write 00 Normal Current #00 01 Lower Margin check #01 10 Upper Margin check #10 11 Setting prohibited #11 SOPCCR Sub Operating Power Control Register 0xAA 8 read-write n 0x0 0x0 SOPCM Sub Operating Power Control Mode Select 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 SOPCMTSF Operating Power Control Mode Transition Status Flag 4 read-only 0 Transition completed #0 1 During transition #1 SOSCCR Sub-Clock Oscillator Control Register 0x480 8 read-write n 0x0 0x0 SOSTP Sub Clock Oscillator Stop 0 read-write 0 Operate the sub-clock oscillator #0 1 Stop the sub-clock oscillator #1 SYOCDCR System Control OCD Control Register 0x40E 8 read-write n 0x0 0x0 DBGEN Debugger Enable bit 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 WDT Watchdog Timer WDT 0x0 0x0 0x1 registers n 0x2 0x5 registers n 0x8 0x1 registers n WDTCR WDT Control Register 0x2 16 read-write n 0x0 0x0 CKS Clock Division Ratio Select 4 3 read-write Others Setting prohibited 0x1 PCLKB/4 0x1 0x4 PCLKB/64 0x4 0x6 PCLKB/512 0x6 0x7 PCLKB/2048 0x7 0x8 PCLKB/8192 0x8 0xF PCLKB/128 0xf RPES Window End Position Select 8 1 read-write 00 75% #00 01 50% #01 10 25% #10 11 0% (do not specify window end position). #11 RPSS Window Start Position Select 12 1 read-write 00 25% #00 01 50% #01 10 75% #10 11 100% (do not specify window start position). #11 TOPS Timeout Period Select 0 1 read-write 00 1024 cycles (0x03FF) #00 01 4096 cycles (0x0FFF) #01 10 8192 cycles (0x1FFF) #10 11 16384 cycles (0x3FFF) #11 WDTCSTPR WDT Count Stop Control Register 0x8 8 read-write n 0x0 0x0 SLCSTP WDT Count Stop Control Register 7 read-write 0 Disable count stop #0 1 Stop count on transition to Sleep mode #1 WDTRCR WDT Reset Control Register 0x6 8 read-write n 0x0 0x0 RSTIRQS Reset Interrupt Request Select 7 read-write 0 Enable non-maskable interrupt request or interrupt request output #0 1 Enable reset output #1 WDTRR WDT Refresh Register 0x0 8 read-write n 0x0 0x0 WDTSR WDT Status Register 0x4 16 read-write n 0x0 0x0 CNTVAL Down-Counter Value 0 13 read-only REFEF Refresh Error Flag 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1