Renesas R7FA6M4AF_RAMLess 2024.05.06 R7FA6M4AF_RAMLess false ADC120 12bit A/D Converter 0 ADC120 0x0 0x0 0xD registers n 0x1A0 0x4 registers n 0x1B0 0x2 registers n 0x1B4 0x2 registers n 0x1E0 0x1 registers n 0x62 0x16 registers n 0x7A 0x4 registers n 0x80 0x9 registers n 0x8C 0x1 registers n 0x90 0x15 registers n 0xA6 0x1 registers n 0xA8 0x5 registers n 0xB0 0x21 registers n 0xD2 0x1 registers n 0xDD 0x23 registers n 0xE 0x52 registers n ADADC A/D-Converted Value Addition/Average Count Select Register 0xC 8 read-write n 0x0 0x0 ADC Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) 0 2 read-write others Setting prohibited 000 1-time conversion (no addition same as normal conversion) #000 001 2-time conversion (addition once) #001 010 3-time conversion (addition twice) #010 011 4-time conversion (addition three times) #011 101 16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy. #101 AVEE Average mode enable bit.Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode. 7 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x8 16 read-write n 0x0 0x0 ADS00 A/D-Converted Value Addition/Average Channel AN000 Select 0 read-write 0 AN000 is not selected. #0 1 AN000 is selected. #1 ADS01 A/D-Converted Value Addition/Average Channel AN001 Select 1 read-write 0 AN001 is not selected. #0 1 AN001 is selected. #1 ADS02 A/D-Converted Value Addition/Average Channel AN002 Select 2 read-write 0 AN002 is not selected. #0 1 AN002 is selected. #1 ADS03 A/D-Converted Value Addition/Average Channel AN003 Select 3 read-write 0 AN003 is not selected. #0 1 AN003 is selected. #1 ADS04 A/D-Converted Value Addition/Average Channel AN004 Select 4 read-write 0 AN004 is not selected. #0 1 AN004 is selected. #1 ADS05 A/D-Converted Value Addition/Average Channel AN005 Select 5 read-write 0 AN005 is not selected. #0 1 AN005 is selected. #1 ADS06 A/D-Converted Value Addition/Average Channel AN006 Select 6 read-write 0 AN006 is not selected. #0 1 AN006 is selected. #1 ADS07 A/D-Converted Value Addition/Average Channel AN007 Select 7 read-write 0 AN007 is not selected. #0 1 AN007 is selected. #1 ADS08 A/D-Converted Value Addition/Average Channel AN008 Select 8 read-write 0 AN008 is not selected. #0 1 AN008 is selected. #1 ADS09 A/D-Converted Value Addition/Average Channel AN009 Select 9 read-write 0 AN009 is not selected. #0 1 AN009 is selected. #1 ADS10 A/D-Converted Value Addition/Average Channel AN0010 Select 10 read-write 0 AN0010 is not selected. #0 1 AN0010 is selected. #1 ADS11 A/D-Converted Value Addition/Average Channel AN0011 Select 11 read-write 0 AN0011 is not selected. #0 1 AN0011 is selected. #1 ADS12 A/D-Converted Value Addition/Average Channel AN0012 Select 12 read-write 0 AN0012 is not selected. #0 1 AN0012 is selected. #1 ADS13 A/D-Converted Value Addition/Average Channel AN0013 Select 13 read-write 0 AN0013 is not selected. #0 1 AN0013 is selected. #1 ADS14 A/D-Converted Value Addition/Average Channel AN0014 Select 14 read-write 0 AN0014 is not selected. #0 1 AN0014 is selected. #1 ADS15 A/D-Converted Value Addition/Average Channel AN0015 Select 15 read-write 0 AN0015 is not selected. #0 1 AN0015 is selected. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0xA 16 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 0 15 read-write ADAMPOFF A/D RRAMP off state register 0x62 8 read-write n 0x0 0x0 OPOFF 0 7 read-write ADANSA0 A/D Channel Select Register A0 0x4 16 read-write n 0x0 0x0 ANSA00 AN000 Select 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ANSA01 AN001 Select 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSA010 AN0010 Select 10 read-write 0 AN0010 is not subjected to conversion. #0 1 AN0010 is subjected to conversion. #1 ANSA011 AN0011 Select 11 read-write 0 AN0011 is not subjected to conversion. #0 1 AN0011 is subjected to conversion. #1 ANSA012 AN0012 Select 12 read-write 0 AN0012 is not subjected to conversion. #0 1 AN0012 is subjected to conversion. #1 ANSA013 AN0013 Select 13 read-write 0 AN0013 is not subjected to conversion. #0 1 AN0013 is subjected to conversion. #1 ANSA014 AN0014 Select 14 read-write 0 AN0014 is not subjected to conversion. #0 1 AN0014 is subjected to conversion. #1 ANSA015 AN0015 Select 15 read-write 0 AN0015 is not subjected to conversion. #0 1 AN0015 is subjected to conversion. #1 ANSA02 AN002 Select 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSA03 AN003 Select 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSA04 AN004 Select 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSA05 AN005 Select 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSA06 AN006 Select 6 read-write 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSA07 AN007 Select 7 read-write 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSA08 AN008 Select 8 read-write 0 AN008 is not subjected to conversion. #0 1 AN008 is subjected to conversion. #1 ANSA09 AN009 Select 9 read-write 0 AN009 is not subjected to conversion. #0 1 AN009 is subjected to conversion. #1 ADANSA1 A/D Channel Select Register A1 0x6 16 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 0 15 read-write ADANSB0 A/D Channel Select Register B0 0x14 16 read-write n 0x0 0x0 ANSB00 AN000 Select 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ANSB01 AN001 Select 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSB010 AN0010 Select 10 read-write 0 AN0010 is not subjected to conversion. #0 1 AN0010 is subjected to conversion. #1 ANSB011 AN0011 Select 11 read-write 0 AN0011 is not subjected to conversion. #0 1 AN0011 is subjected to conversion. #1 ANSB012 AN0012 Select 12 read-write 0 AN0012 is not subjected to conversion. #0 1 AN0012 is subjected to conversion. #1 ANSB013 AN0013 Select 13 read-write 0 AN0013 is not subjected to conversion. #0 1 AN0013 is subjected to conversion. #1 ANSB014 AN0014 Select 14 read-write 0 AN0014 is not subjected to conversion. #0 1 AN0014 is subjected to conversion. #1 ANSB015 AN0015 Select 15 read-write 0 AN0015 is not subjected to conversion. #0 1 AN0015 is subjected to conversion. #1 ANSB02 AN002 Select 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSB03 AN003 Select 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSB04 AN004 Select 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSB05 AN005 Select 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSB06 AN006 Select 6 read-write 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSB07 AN007 Select 7 read-write 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSB08 AN008 Select 8 read-write 0 AN008 is not subjected to conversion. #0 1 AN008 is subjected to conversion. #1 ANSB09 AN009 Select 9 read-write 0 AN009 is not subjected to conversion. #0 1 AN009 is subjected to conversion. #1 ADANSB1 A/D Channel Select Register B1 0x16 16 read-write n 0x0 0x0 ANSB16 AN016 Select 0 read-write 0 AN016 is not subjected to conversion. #0 1 AN016 is subjected to conversion. #1 ANSB17 AN017 Select 1 read-write 0 AN017 is not subjected to conversion. #0 1 AN017 is subjected to conversion. #1 ANSB18 AN018 Select 2 read-write 0 AN018 is not subjected to conversion. #0 1 AN018 is subjected to conversion. #1 ANSB19 AN019 Select 3 read-write 0 AN019 is not subjected to conversion. #0 1 AN019 is subjected to conversion. #1 ANSB20 AN020 Select 4 read-write 0 AN020 is not subjected to conversion. #0 1 AN020 is subjected to conversion. #1 ANSB21 AN021 Select 5 read-write 0 AN021 is not subjected to conversion. #0 1 AN021 is subjected to conversion. #1 ANSB22 AN022 Select 6 read-write 0 AN022 is not subjected to conversion. #0 1 AN022 is subjected to conversion. #1 ANSB23 AN023 Select 7 read-write 0 AN023 is not subjected to conversion. #0 1 AN023 is subjected to conversion. #1 ANSB24 AN024 Select 8 read-write 0 AN024 is not subjected to conversion. #0 1 AN024 is subjected to conversion. #1 ANSB25 AN025 Select 9 read-write 0 AN025 is not subjected to conversion. #0 1 AN025 is subjected to conversion. #1 ANSB26 AN026 Select 10 read-write 0 AN026 is not subjected to conversion. #0 1 AN026 is subjected to conversion. #1 ANSB27 AN027 Select 11 read-write 0 AN027 is not subjected to conversion. #0 1 AN027 is subjected to conversion. #1 ANSB28 AN028 Select 12 read-write 0 AN028 is not subjected to conversion. #0 1 AN028 is subjected to conversion. #1 ANSB29 AN029 Select 13 read-write 0 AN029 is not subjected to conversion. #0 1 AN029 is subjected to conversion. #1 ANSB30 AN030 Select 14 read-write 0 AN030 is not subjected to conversion. #0 1 AN030 is subjected to conversion. #1 ANSB31 AN031 Select 15 read-write 0 AN031 is not subjected to conversion. #0 1 AN031 is subjected to conversion. #1 ADBUF0 A/D Data Buffer Register %s 0xB0 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF1 A/D Data Buffer Register %s 0xB2 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF10 A/D Data Buffer Register %s 0xC4 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF11 A/D Data Buffer Register %s 0xC6 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF12 A/D Data Buffer Register %s 0xC8 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF13 A/D Data Buffer Register %s 0xCA 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF14 A/D Data Buffer Register %s 0xCC 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF15 A/D Data Buffer Register %s 0xCE 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF2 A/D Data Buffer Register %s 0xB4 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF3 A/D Data Buffer Register %s 0xB6 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF4 A/D Data Buffer Register %s 0xB8 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF5 A/D Data Buffer Register %s 0xBA 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF6 A/D Data Buffer Register %s 0xBC 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF7 A/D Data Buffer Register %s 0xBE 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF8 A/D Data Buffer Register %s 0xC0 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF9 A/D Data Buffer Register %s 0xC2 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUFEN A/D Data Buffer Enable Register 0xD0 8 read-write n 0x0 0x0 BUFEN Data Buffer Enable 0 read-write 0 The data buffer is not used. #0 1 The data buffer is used. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADBUFPTR A/D Data Buffer Pointer Register 0xD2 8 read-write n 0x0 0x0 zeroToClear modify BUFPTR Data Buffer PointerThese bits indicate the number of data buffer to which the next A/D converted data is transferred. 0 3 read-only PTROVF Pointer Overflow Flag 4 read-only 0 The data buffer pointer has not overflowed. #0 1 The data buffer pointer has overflowed. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write ADCER A/D Control Extended Register 0xE 16 read-write n 0x0 0x0 ACE A/D Data Register Automatic Clearing Enable 5 read-write 0 Disables automatic clearing. #0 1 Enables automatic clearing. #1 ADPRC A/D Conversion Accuracy Specify 1 1 read-write 00 A/D conversion is performed with 12-bit accuracy. #00 01 A/D conversion is performed with 10-bit accuracy. #01 10 A/D conversion is performed with 8-bit accuracy. #10 11 Setting prohibited #11 ADRFMT A/D Data Register Format Select 15 read-write 0 Flush-right is selected for the A/D data register format. #0 1 Flush-left is selected for the A/D data register format. #1 DCE Discharge Enable 4 read-write 0 Discharge after the A/D conversion is disabled. #0 1 Discharge after the A/D conversion is enabled. #1 DIAGLD Self-Diagnosis Mode Select 10 read-write 0 Rotation mode for self-diagnosis voltage #0 1 Fixed mode for self-diagnosis voltage #1 DIAGM Self-Diagnosis Enable 11 read-write 0 Disables self-diagnosis of ADC12. #0 1 Enables self-diagnosis of ADC12. #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 1 read-write 00 When the self-diagnosis fixation mode is selected, it set prohibits it. #00 01 The self-diagnosis by using the voltage of 0V. #01 10 The self-diagnosis by using the voltage of reference supply x 1/2. #10 11 The self-diagnosis by using the voltage of the reference supply. #11 Reserved These bits are read as 000. The write value should be 000. 12 2 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 12 2 read-write ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x92 8 read-write n 0x0 0x0 CMPOCA Internal reference voltage Compare selection bit. 1 read-write 0 Excludes the internal reference voltage from the compare window A target range. #0 1 Includes the internal reference voltage in the compare window A target range. #1 CMPTSA Temperature sensor output Compare selection bit. 0 read-write 0 Excludes the temperature sensor output from the compare window A target range. #0 1 Includes the temperature sensor output in the compare window A target range. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x94 16 read-write n 0x0 0x0 CMPCHA00 Compare Window A Channel AN000 Select 0 read-write 0 Disable compare function for AN000 #0 1 Enable compare function for AN000 #1 CMPCHA01 Compare Window A Channel AN001 Select 1 read-write 0 Disable compare function for AN001 #0 1 Enable compare function for AN001 #1 CMPCHA02 Compare Window A Channel AN002 Select 2 read-write 0 Disable compare function for AN002 #0 1 Enable compare function for AN002 #1 CMPCHA03 Compare Window A Channel AN003 Select 3 read-write 0 Disable compare function for AN003 #0 1 Enable compare function for AN003 #1 CMPCHA04 Compare Window A Channel AN004 Select 4 read-write 0 Disable compare function for AN004 #0 1 Enable compare function for AN004 #1 CMPCHA05 Compare Window A Channel AN005 Select 5 read-write 0 Disable compare function for AN005 #0 1 Enable compare function for AN005 #1 CMPCHA06 Compare Window A Channel AN006 Select 6 read-write 0 Disable compare function for AN006 #0 1 Enable compare function for AN006 #1 CMPCHA07 Compare Window A Channel AN007 Select 7 read-write 0 Disable compare function for AN007 #0 1 Enable compare function for AN007 #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x96 16 read-write n 0x0 0x0 CMPCHA16 AN016 Select 0 read-write 0 Excludes AN016 from the compare window A target range. #0 1 Includes AN016 from the compare window A target range. #1 CMPCHA17 AN017 Select 1 read-write 0 Excludes AN017 from the compare window A target range. #0 1 Includes AN017 from the compare window A target range. #1 CMPCHA18 AN018 Select 2 read-write 0 Excludes AN018 from the compare window A target range. #0 1 Includes AN018 from the compare window A target range. #1 CMPCHA19 AN019 Select 3 read-write 0 Excludes AN019 from the compare window A target range. #0 1 Includes AN019 from the compare window A target range. #1 CMPCHA20 AN020 Select 4 read-write 0 Excludes AN020 from the compare window A target range. #0 1 Includes AN020 from the compare window A target range. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write ADCMPBNSR A/D Compare Function Window B Channel Selection Register 0xA6 8 read-write n 0x0 0x0 CMPCHB Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected. 0 5 read-write others Setting prohibited 0x00 AN000 0x00 0x01 AN001 0x01 0x02 AN002 0x02 0x03 AN003 0x03 0x04 AN004 0x04 0x05 AN005 0x05 0x06 AN006 0x06 0x07 AN007 0x07 0x10 AN016 0x10 0x11 AN017 0x11 0x12 AN018 0x12 0x13 AN019 0x13 0x14 AN020 0x14 0x20 Temperature sensor 0x20 0x21 Internal reference voltage 0x21 0x3F No channel is selected 0x3F CMPLB Compare window B Compare condition setting bit. 7 read-write 0 CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1) #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write ADCMPBSR A/D Compare Function Window B Status Register 0xAC 8 read-write n 0x0 0x0 CMPSTB Compare window B flag.It is a status flag that shows the comparative result of CH (AN000-AN007,AN016-AN020, temperature sensor, and internal reference voltage) made the object of window B relation condition. 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADCMPCR A/D Compare Function Control Register 0x90 16 read-write n 0x0 0x0 CMPAB Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1). 0 1 read-write 00 S12ADWMELC is output when window A comparison conditions are met OR window B comparison conditions are met. S12ADWUMELC is output in other cases. #00 01 S12ADWMELC is output when window A comparison conditions are met EXOR window B comparison conditions are met. S12ADWUMELC is output in other cases. #01 10 S12ADWMELC is output when window A comparison conditions are met and window B comparison conditions are met. S12ADWUMELC is output in other cases. #10 11 Setting prohibited. #11 CMPAE Compare Window A Operation Enable 11 read-write 0 Compare window A operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window A operation is enabled. #1 CMPAIE Compare A Interrupt Enable 15 read-write 0 S12ADCMPAIi interrupt is disabled when comparison conditions (window A) are met. #0 1 S12ADCMPAIi interrupt is enabled when comparison conditions (window A) are met. #1 CMPBE Compare Window B Operation Enable 9 read-write 0 Compare window B operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window B operation is enabled. #1 CMPBIE Compare B Interrupt Enable 13 read-write 0 S12ADCMPBIi interrupt is disabled when comparison conditions (window B) are met. #0 1 S12ADCMPBIi interrupt is enabled when comparison conditions (window B) are met. #1 Reserved This bit is read as 0. The write value should be 0. 12 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved This bit is read as 0. The write value should be 0. 12 read-write WCMPE Window Function Setting 14 read-write 0 Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result. #0 1 Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result. #1 ADCMPDR0 A/D Compare Function Window A Lower-Side Level Setting Register 0x9C 16 read-write n 0x0 0x0 ADCMPDR0 The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A. 0 15 read-write ADCMPDR1 A/D Compare Function Window A Upper-Side Level Setting Register 0x9E 16 read-write n 0x0 0x0 ADCMPDR1 The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.. 0 15 read-write ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x93 8 read-write n 0x0 0x0 CMPLOCA Compare Window A Internal Reference Voltage ComparisonCondition Select 1 read-write 0 ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1) #1 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 read-write 0 ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1). #0 1 ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x98 16 read-write n 0x0 0x0 CMPLCHA00 Comparison condition of AN000 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA01 Comparison condition of AN001 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA02 Comparison condition of AN002 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA03 Comparison condition of AN003 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA04 Comparison condition of AN004 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA05 Comparison condition of AN005 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA06 Comparison condition of AN006 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA07 Comparison condition of AN007 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x9A 16 read-write n 0x0 0x0 CMPLCHA16 Comparison condition of AN016 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA17 Comparison condition of AN017 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA18 Comparison condition of AN018 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA19 Comparison condition of AN019 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA20 Comparison condition of AN020 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0xA4 8 read-write n 0x0 0x0 CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0xA0 16 read-write n 0x0 0x0 CMPSTCHA00 Compare window A flag of AN000 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare window A flag of AN001 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare window A flag of AN002 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare window A flag of AN003 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA04 Compare window A flag of AN004 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare window A flag of AN005 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare window A flag of AN006 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA07 Compare window A flag of AN007 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ADCMPSR1 A/D Compare Function Window A Channel Status Register 1 0xA2 16 read-write n 0x0 0x0 CMPSTCHA16 Compare window A flag of AN016 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare window A flag of AN017 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare window A flag of AN018 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA19 Compare window A flag of AN019 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA20 Compare window A flag of AN020 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write ADCSR A/D Control Register 0x0 16 read-write n 0x0 0x0 ADCS Scan Mode Select 13 1 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 ADHSC A/D Conversion Operation Mode Select 10 read-write 0 High speed A/D conversion mode #0 1 Low current A/D conversion mode #1 ADIE Scan End Interrupt Enable 12 read-write 0 Disables S12ADI0 interrupt generation upon scan completion. #0 1 Enables S12ADI0 interrupt generation upon scan completion. #1 ADST A/D Conversion Start 15 read-write modify 0 Stops A/D conversion process. #0 1 Starts A/D conversion process. #1 DBLANS Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected. 0 4 read-write DBLE Double Trigger Mode Select 7 read-write 0 Double trigger mode non-selection #0 1 Double trigger mode selection #1 EXTRG Trigger Select 8 read-write 0 A/D conversion is started by the synchronous trigger (ELCTRG0). #0 1 A/D conversion is started by the asynchronous trigger (ADTRG0#). #1 GBADIE Group B Scan End Interrupt Enable 6 read-write 0 Disables S12GBADI0 interrupt generation upon group B scan completion. #0 1 Enables S12GBADI0 interrupt generation upon group B scan completion. #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write TRGE Trigger Start Enable 9 read-write 0 Disables A/D conversion to be started by the synchronous or asynchronous trigger. #0 1 Enables A/D conversion to be started by the synchronous or asynchronous trigger. #1 ADDBLDR A/D Data Duplication Register 0x18 16 read-only n 0x0 0x0 ADDBLDR This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode. 0 15 read-only ADDBLDRA A/D Data Duplication Register A 0x84 16 read-only n 0x0 0x0 ADDBLDRA This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDBLDRB A/D Data Duplication Register B 0x86 16 read-only n 0x0 0x0 ADDBLDRB This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDDACER A/D RRAMP Discharge Period Register 0x64 16 read-write n 0x0 0x0 ADHS 15 read-write Reserved These bits are read as 00. The write value should be 00. 13 1 read-write Reserved These bits are read as 00. The write value should be 00. 13 1 read-write WRIOFF 8 4 read-write WRION 0 4 read-write ADDISCR A/D Disconnection Detection Control Register 0x7A 8 read-write n 0x0 0x0 ADNDIS The charging time 0 3 read-write others ( 1 / ADCLK ) x ADNDIS 0000 Disconnection detection is disabled #0000 0001 Setting prohibited #0001 PCHG Selection of Precharge or Discharge 4 read-write 0 Discharge #0 1 Precharge #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write ADDR0 A/D Data Register %s 0x20 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR1 A/D Data Register %s 0x22 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR10 A/D Data Register %s 0x34 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR11 A/D Data Register %s 0x36 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR12 A/D Data Register %s 0x38 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR13 A/D Data Register %s 0x3A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR14 A/D Data Register %s 0x3C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR15 A/D Data Register %s 0x3E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR16 A/D Data Register %s 0x40 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR17 A/D Data Register %s 0x42 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR18 A/D Data Register %s 0x44 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR19 A/D Data Register %s 0x46 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR2 A/D Data Register %s 0x24 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR20 A/D Data Register %s 0x48 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR21 A/D Data Register %s 0x4A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR22 A/D Data Register %s 0x4C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR23 A/D Data Register %s 0x4E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR24 A/D Data Register %s 0x50 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR25 A/D Data Register %s 0x52 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR26 A/D Data Register %s 0x54 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR27 A/D Data Register %s 0x56 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR28 A/D Data Register %s 0x58 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR29 A/D Data Register %s 0x5A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR3 A/D Data Register %s 0x26 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR30 A/D Data Register %s 0x5C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR31 A/D Data Register %s 0x5E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR4 A/D Data Register %s 0x28 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR5 A/D Data Register %s 0x2A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR6 A/D Data Register %s 0x2C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR7 A/D Data Register %s 0x2E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR8 A/D Data Register %s 0x30 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR9 A/D Data Register %s 0x32 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADELCCR A/D Event Link Control Register 0x7D 8 read-write n 0x0 0x0 ELCC Event Link Control 0 1 read-write others ELC event is generated when completed all scan. 00 ELC event is generated when completed the scan other than group B in group scan mode. #00 01 ELC event is generated when completed the scan of group B in group scan mode. #01 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADEXICR A/D Conversion Extended Input Control Register 0x12 16 read-write n 0x0 0x0 EXOEN Extended Analog Output Control 15 read-write 0 Output is disabled. #0 1 Output is enabled. #1 EXSEL Extended Analog Input Select 14 read-write others Setting prohibited. 00 Analog input channel (ANnXX) #00 01 ANEX1 #01 OCSA Internal Reference Voltage A/D Conversion Select 9 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode. #1 OCSAD Internal Reference Voltage A/D converted Value Addition/Average Mode Select 1 read-write 0 Internal reference voltage A/D-converted value addition/average mode is not selected. #0 1 Internal reference voltage A/D-converted value addition/average mode is selected. #1 OCSB Internal Reference Voltage A/D Conversion Select for Group B 11 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group B in group scan mode. #1 Reserved This bit is read as 0. The write value should be 0. 12 read-write Reserved This bit is read as 0. The write value should be 0. 12 read-write TSSA Temperature Sensor Output A/D Conversion Select 8 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is selected. #1 TSSAD Temperature Sensor Output A/D converted Value Addition/Average Mode Select 0 read-write 0 Temperature sensor output A/D-converted value addition/average mode is not selected. #0 1 Temperature sensor output A/D-converted value addition/average mode is selected. #1 TSSB Temperature Sensor Output A/D Conversion Select for Group B 10 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is not selected for group B in group scan mode. #1 ADEXREF A/D enhancing status register 0x3 8 read-write n 0x0 0x0 GBADF Group B scanning end flag bit. 0 read-write zeroToClear modify 0 State of the idol or scanning. #0 1 End of scanning #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADEXTSTR A/D Enhancing Test Register 0x68 16 read-write n 0x0 0x0 ADTRM1 Trim bit 1 for A/D hard macro.Timing adjustment trim bit for A/D hard macro to hardening of process. 14 1 read-write ADTRM2 Trim bit 2 for A/D hard macro.Bias adjustment trim bit for A/D hard macro to hardening of process. 12 1 read-write ADTRM3 Trim bit 3 for A/D hard macro.3bit Flash comparator power save bit for A/D hard macro to hardening of process. 11 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write SHTEST Test mode bit for S and H circuit.Test mode bit of S and H circuit only for channel. 0 2 read-write SHTRM Current adjustment trim bit for S and H circuit.Trim bit for adjustment to hardening of process. 8 1 read-write SWTST Test selection bit for pressure switch. 4 1 read-write 00 Test non-selection #00 01 Pressure test mode #01 10 PMOS test mode #10 11 Setting prohibited (PMOS test mode) #11 ADGSCS A/D Conversion Channel Status Register (for Group Scan) 0x82 16 read-only n 0x0 0x0 CHSELGA Channel status of Group A scan 8 7 read-only 0x80 Group A scan start 0x80 0xFF Group A scan end 0xFF CHSELGB Channel status of Group B scan 0 7 read-only 0x80 Group B scan start 0x80 0xFF Group B scan end 0xFF ADGSPCR A/D Group Scan Priority Control Register 0x80 16 read-write n 0x0 0x0 GBEXTRG External trigger selection bit for group B. 8 read-write 0 An external trigger is not selected the trigger of group B. #0 1 An external trigger is selected the trigger of group B. #1 GBRP Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit. 15 read-write 0 Single scan for group B is not continuously activated. #0 1 Single scan for group B is continuously activated. #1 GBRSCN Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.) 1 read-write 0 Scanning for group B is not restarted after having been discontinued due to group A priority control. #0 1 Scanning for group B is restarted after having been discontinued due to group A priority control. #1 PGS Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed. 0 read-write 0 Operation is without group A priority control #0 1 Operation is with group A priority control #1 Reserved These bits are read as 000000. The write value should be 000000. 9 5 read-write Reserved These bits are read as 000000. The write value should be 000000. 9 5 read-write ADOCDR A/D Internal Reference Voltage Data Register 0x1C 16 read-only n 0x0 0x0 ADOCDR This is a 16-bit read-only register for storing the A/D result of internal reference voltage. 0 15 read-only ADPGACR A/D Programmable Gain Amplifier Control Register 0x1A0 16 read-write n 0x0 0x0 P000ENAMP Amplifier enable bit for PGA P000 2 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P000GEN PGA P000 gain setting and enable bit 3 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P000SEL0 A through amplifier is enable for PGA P000 0 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P000SEL1 The amplifier passing is enable for PGA P000 1 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P001ENAMP Amplifier enable bit for PGA P001 6 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P001GEN PGA P001 gain setting and enable bit 7 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P001SEL0 A through amplifier is enable for PGA P001 4 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P001SEL1 The amplifier passing is enable for PGA P001 5 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P002ENAMP Amplifier enable bit for PGA P002 10 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P002GEN PGA P002 gain setting and enable bit 11 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P002SEL0 A through amplifier is enable for PGA P002 8 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P002SEL1 The amplifier passing is enable for PGA P002 9 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P003ENAMP Amplifier enable bit for PGA P003 14 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P003GEN PGA P003 gain setting and enable bit 15 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P003SEL0 A through amplifier is enable for PGA P003 12 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P003SEL1 The amplifier passing is enable for PGA P003 13 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 ADPGADBS0 A/D Programmable Gain Amplifier Differential Input Bias Select Register 0 0x1B4 8 read-write n 0x0 0x0 P0BIAS Programmable Gain Amplifiers P000 to P002 Bias Voltage SelectNOTE: This bit selects the input bias voltage value when differential inputs are used. 0 read-write 0 AVCC x 0.5 #0 1 AVCC x 0.6 #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADPGADBS1 A/D Programmable Gain Amplifier Differential Input Bias Select Register 1 0x1B5 8 read-write n 0x0 0x0 P3BIAS Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: This bit selects the input bias voltage value when differential inputs are used. 0 read-write 0 AVCC x 0.5 #0 1 AVCC x 0.6 #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADPGADCR0 A/D Programmable Gain Amplifier Differential Input Control Register 0x1B0 16 read-write n 0x0 0x0 P000DEN P000 Differential Input Enable 3 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P000DG P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b. 0 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P001DEN P001 Differential Input Enable 7 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P001DG P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b. 4 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P002DEN P002 Differential Input Enable 11 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P002DG P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b. 8 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P003DEN P003 Differential Input Enable 15 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P003DG P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b. 12 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 Reserved This bit is read as 0. The write value should be 0. 14 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved This bit is read as 0. The write value should be 0. 14 read-write ADPGAGS0 A/D Programmable Gain Amplifier Gain Setting Register 0 0x1A2 16 read-write n 0x0 0x0 P000GAIN PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0. 0 3 read-write 0000 x 2.000 (ADPGADDCR0.P000DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P000DEN=0) / x 1.500 (ADPGADDCR0.P000DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P000DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P000DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P000DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P000DEN=0) / x 2.333 (ADPGADDCR0.P000DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P000DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P000DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P000DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P000DEN=0) / x 4.00 (ADPGADDCR0.P000DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P000DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P000DEN=0) / x 5.667 (ADPGADDCR0.P000DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P000DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P000DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P000DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P000DEN=0) #1111 P001GAIN PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0. 4 3 read-write 0000 x 2.000 (ADPGADDCR0.P001DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P001DEN=0) / x 1.500 (ADPGADDCR0.P001DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P001DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P001DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P001DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P001DEN=0) / x 2.333 (ADPGADDCR0.P001DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P001DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P001DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P001DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P001DEN=0) / x 4.00 (ADPGADDCR0.P001DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P001DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P001DEN=0) / x 5.667 (ADPGADDCR0.P001DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P001DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P001DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P001DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P001DEN=0) #1111 P002GAIN PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0. 8 3 read-write 0000 x 2.000 (ADPGADDCR0.P002DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P002DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P002DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P002DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P002DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P002DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P002DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P002DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P002DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P002DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P002DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0) #1111 P003GAIN PGA P003 gain setting bit.The gain magnification of (ADPGSDCR0.P003GEN=0b) when the shingle end is input and each PGA P003 is set. When the differential motion is input, (ADPGSDCR0.P003GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P003DG 1:0. 12 3 read-write 0000 x 2.000 (ADPGADDCR0.P003DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P003DEN=0) / x 1.500 (ADPGADDCR0.P003DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P003DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P003DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P003DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P003DEN=0) / x 2.333 (ADPGADDCR0.P003DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P003DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P003DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P003DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P003DEN=0) / x 4.00 (ADPGADDCR0.P003DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P003DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P003DEN=0) / x 5.667 (ADPGADDCR0.P003DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P003DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P003DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P003DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P003DEN=0) #1111 ADRD A/D Self-Diagnosis Data Register 0x1E 16 read-only n 0x0 0x0 AD A/D-converted value (right-justified)NOTE: Unused bits in the AD bit field are fixed 0 0 11 read-only DIAGST Self-Diagnosis Status 14 1 read-only 00 Self-diagnosis has never been executed since power-on. #00 01 Self-diagnosis using the voltage of 0 V has been executed. #01 10 Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. #10 11 Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. #11 Reserved These bits are read as 00. 12 1 read-only ADREF A/D status register 0x2 8 read-write n 0x0 0x0 ADF Scanning end flag bitThis bit is a status bit that becomes 1 while scanning. 0 read-write zeroToClear modify 0 State of the idol or scanning. #0 1 End of scanning #1 ADSCACT Scanning status bit 7 read-only 0 State of idol #0 1 It is Scanning #1 Reserved These bits are read as 000000. The write value should be 000000. 1 5 read-write ADREFMON A/D External Reference Voltage Monitor Register 0x1E0 8 read-write n 0x0 0x0 MONSEL Monitor output selection bit. 4 3 read-write others Setting prohibited. 0000 No monitor output is selected. #0000 1000 P000 is selected. #1000 1001 P001 is selected. #1001 1010 P002 is selected. #1010 1011 P003 is selected. #1011 PGAMON PGA Monitor Output Enable 0 2 read-write others Setting prohibited. 000 The monitor output is disabled. #000 001 The monitor output is enabled. #001 Reserved This bit is read as 0. The write value should be 0. 3 read-write ADSER A/D Sampling Extension Register 0x88 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write SMPEX Sampling extension control 7 read-write 0 Not extend sampling period #0 1 Extending sampling period #1 ADSHCR A/D Sample and Hold Circuit Control Register 0x66 16 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write SHANS0 AN000 sample-and-hold circuit Select 8 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS1 AN001 sample-and-hold circuit Select 9 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS2 AN002 sample-and-hold circuit Select 10 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SSTSH Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states) 0 7 read-write ADSHMSR A/D Sample and Hold Operation Mode Select Register 0x7C 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write SHMD Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select 0 read-write 0 Sampling by channel-dedicated sample-and-hold circuit is disable. #0 1 Sampling by channel-dedicated sample-and-hold circuit is enable. #1 ADSSTR0 A/D Sampling State Register %s 0xE0 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR1 A/D Sampling State Register %s 0xE1 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR10 A/D Sampling State Register %s 0xEA 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR11 A/D Sampling State Register %s 0xEB 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR12 A/D Sampling State Register %s 0xEC 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR13 A/D Sampling State Register %s 0xED 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR14 A/D Sampling State Register %s 0xEE 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR15 A/D Sampling State Register %s 0xEF 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR16 A/D Sampling State Register %s 0xF0 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR17 A/D Sampling State Register %s 0xF1 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR18 A/D Sampling State Register %s 0xF2 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR19 A/D Sampling State Register %s 0xF3 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR2 A/D Sampling State Register %s 0xE2 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR20 A/D Sampling State Register %s 0xF4 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR21 A/D Sampling State Register %s 0xF5 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR22 A/D Sampling State Register %s 0xF6 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR23 A/D Sampling State Register %s 0xF7 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR24 A/D Sampling State Register %s 0xF8 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR25 A/D Sampling State Register %s 0xF9 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR26 A/D Sampling State Register %s 0xFA 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR27 A/D Sampling State Register %s 0xFB 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR28 A/D Sampling State Register %s 0xFC 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR29 A/D Sampling State Register %s 0xFD 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR3 A/D Sampling State Register %s 0xE3 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR30 A/D Sampling State Register %s 0xFE 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR31 A/D Sampling State Register %s 0xFF 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR4 A/D Sampling State Register %s 0xE4 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR5 A/D Sampling State Register %s 0xE5 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR6 A/D Sampling State Register %s 0xE6 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR7 A/D Sampling State Register %s 0xE7 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR8 A/D Sampling State Register %s 0xE8 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR9 A/D Sampling State Register %s 0xE9 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTRL A/D Sampling State Register L 0xDD 8 read-write n 0x0 0x0 SST Sampling Time Setting (AN016-AN020) 0 7 read-write ADSSTRO A/D Sampling State Register O 0xDF 8 read-write n 0x0 0x0 SST Sampling Time Setting (Internal reference voltage) 0 7 read-write ADSSTRT A/D Sampling State Register T 0xDE 8 read-write n 0x0 0x0 SST Sampling Time Setting (temperature sensor output) 0 7 read-write ADSTRGR A/D Conversion Start Trigger Select Register 0x10 16 read-write n 0x0 0x0 Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write TRSA A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected. 8 5 read-write TRSB A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode. 0 5 read-write ADSWCR A/D Pressure Switch Control Register 0x7B 8 read-write n 0x0 0x0 ADSWREF These bits are read as 0. The write value should be 0.Refreshing the pressure switch in A/D analog module is set. 0 2 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write SHSWREF S and H Boost Switch Refresh Interval Setting 4 2 read-write 000 Non-Refresh #000 001 64 * ADCLK (Refresh Interval) / 1 * ADCLK (Refresh Period) #001 010 32 * ADCLK (Refresh Interval) / 1 * ADCLK (Refresh Period) #010 011 16 * ADCLK (Refresh Interval) / 1 * ADCLK (Refresh Period) #011 100 128 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) #100 101 64 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) #101 110 32 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) #110 111 16 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) #111 ADSWTSTR0 A/D Channel Switch Test Control Register 0 0x72 16 read-write n 0x0 0x0 CHSW00 Channel switch test control bit. 0 read-write 0 ch00 switch OFF #0 1 ch00 switch ON #1 CHSW01 Channel switch test control bit. 1 read-write 0 ch01 switch OFF #0 1 ch01 switch ON #1 CHSW02 Channel switch test control bit. 2 read-write 0 ch02 switch OFF #0 1 ch02 switch ON #1 CHSW03 Channel switch test control bit. 3 read-write 0 ch03 switch OFF #0 1 ch03 switch ON #1 CHSW04 Channel switch test control bit. 4 read-write 0 ch04 switch OFF #0 1 ch04 switch ON #1 CHSW05 Channel switch test control bit. 5 read-write 0 ch05 switch OFF #0 1 ch05 switch ON #1 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write ADSWTSTR1 A/D Channel Switch Test Control Register 1 0x74 16 read-write n 0x0 0x0 CHSW16 Channel switch test control bit. 0 read-write 0 ch16 switch OFF #0 1 ch16 switch ON #1 CHSW17 Channel switch test control bit. 1 read-write 0 ch17 switch OFF #0 1 ch17 switch ON #1 CHSW18 Channel switch test control bit. 2 read-write 0 ch18 switch OFF #0 1 ch18 switch ON #1 CHSW19 Channel switch test control bit. 3 read-write 0 ch19 switch OFF #0 1 ch19 switch ON #1 CHSW20 Channel switch test control bit. 4 read-write 0 ch20 switch OFF #0 1 ch20 switch ON #1 CHSW21 Channel switch test control bit. 5 read-write 0 ch21 switch OFF #0 1 ch21 switch ON #1 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write ADSWTSTR2 A/D Channel Switch Test Control Register 2 0x76 16 read-write n 0x0 0x0 EX0SW Test control of 0 enhancing input channel switches bit (ANEX0 switch) 0 read-write 0 Channel switch OFF #0 1 Channel switch ON #1 EX1SW Test control of one enhancing input channel switch bit (ANEX1 switch). 1 read-write 0 Channel switch OFF #0 1 Channel switch ON #1 GRP0SW Test control of 0 group switches bit. 8 read-write 0 Channel switch OFF #0 1 Channel switch ON #1 GRP1SW Test control of one group switch bit. 9 read-write 0 Channel switch OFF #0 1 Channel switch ON #1 GRP2SW Test control of two group switches bit 10 read-write 0 Channel switch OFF #0 1 Channel switch ON #1 GRP3SW Test control of two group switches bit 11 read-write 0 Channel switch OFF #0 1 Channel switch ON #1 GRPEX1SW Switch test control bit of enhancing analog ANEX1 12 read-write 0 Enhancing analog ANEX1 switch OFF #0 1 Enhancing analog ANEX1 switch ON #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write SHBYPS0 S and H circuit by-pass switch control bit 0. 4 read-write 0 S and H by-pass switch OFF #0 1 S and H by-pass switch ON #1 SHBYPS1 S and H circuit by-pass switch control bit 1. 5 read-write 0 S and H by-pass switch OFF #0 1 S and H by-pass switch ON #1 SHBYPS2 S and H circuit by-pass switch control bit 2. 6 read-write 0 S and H by-pass switch OFF #0 1 S and H by-pass switch ON #1 ADTSDR A/D Temperature Sensor Data Register 0x1A 16 read-only n 0x0 0x0 ADTSDR This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output. 0 15 read-only ADTSTPR A/D Test Protecting Release Register 0x63 8 read-write n 0x0 0x0 B0WI Bit 0 writing permission bit. 1 read-write PRO Test register protecting bit. 0 read-write 0 R/W is improper of ADEXTSTR, ADTSTRA/B/C/D, and ADSWTSTR0/1/2. #0 1 R/W is available of ADEXTSTR, ADTSTRA/B/C/D, and ADSWTSTR0/1/2. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADTSTRA A/D Test Register A 0x6A 16 read-write n 0x0 0x0 ADTEST_AD Test bit for A/D analog module Bit for test of A/D analog module Details are described to the bit explanation. 8 3 read-write others Setting prohibited 0000 Conversion mode usually #0000 0001 Self Test(VRB) #0001 0010 Self Test(1/4) #0010 0011 Self Test(2/4) #0011 0100 Self Test(3/4) #0100 0101 Self Test(VRT) #0101 1001 ADCOM input test #1001 1100 Resistance DAC output test #1100 1101 ADVAL input test #1101 ADTEST_IO Test bit for analog I/ODetails are described to the bit explanation. 12 3 read-write ATBUSSEL Analog test bus selection bit. 0 read-write 0 ATBUS use test non-selection #0 1 ATBUS use test selection #1 OCSW Internal reference voltage analog switch test control bit. 5 read-write 0 Internal reference voltage analog switch H/W control #0 1 Internal reference voltage analog switch ON #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TSSW Temperature sensor output analogue switch test control bit 6 read-write 0 Temperature sensor output analogue switch H/W control #0 1 Temperature sensor output analogue switch ON #1 TSTSWREF Pressure switch refreshing setting bit for S and H circuit amplifier test.Refreshing the pressure switch that opens for the DAC output voltage charge period when the amplifier of the S and H circuit is tested only for the channel is set. 1 2 read-write ADTSTRB A/D Test Register B 0x6C 16 read-write n 0x0 0x0 ADVAL Signal input bit bit14-0 for A/D analog module test.It corresponds to ADVAL 14:0 input of A/D analog module. 0 14 read-write Reserved This bit is read as 0. The write value should be 0. 15 read-write ADTSTRC A/D Test Register C 0x6E 16 read-write n 0x0 0x0 ADMD Bit for A/D analog module test.ADMODE 6:0 input of A/D analog module. 0 7 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write SYNCERR Synchronous analog to digital conversion error bit. 12 read-write 0 A/D analog module and the A/D control part (soft macro part) are lights as for synchronization or 0. #0 1 Neither A/D analog module nor the A/D control part (soft macro part) have synchronized nor it is a light as for one. #1 ADTSTRD A/D Test Register D 0x70 16 read-write n 0x0 0x0 ADVAL16 Signal input bit bit16 for A/D analog module test.It corresponds to ADVAL 16 input of A/D analog module. 0 read-write Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 14 read-write ADWINLLB A/D Compare Function Window B Lower-Side Level Setting Register 0xA8 16 read-write n 0x0 0x0 ADWINLLB This register is used to compare A window function is used to set the lower level of the window B. 0 15 read-write ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x8C 8 read-only n 0x0 0x0 MONCMPA Comparison Result Monitor A 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCMPB Comparison Result Monitor B 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 MONCOMB Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled. 0 read-only 0 Window A / window B composite conditions are not met. #0 1 Window A / window B composite conditions are met. #1 Reserved These bits are read as 00. 6 1 read-only Reserved These bits are read as 00. 6 1 read-only ADWINULB A/D Compare Function Window B Upper-Side Level Setting Register 0xAA 16 read-write n 0x0 0x0 ADWINULB This register is used to compare A window function is used to set the higher level of the window B. 0 15 read-write ADC121 12bit A/D Converter 1 ADC121 0x0 0x0 0xD registers n 0x1A0 0x4 registers n 0x1B0 0x2 registers n 0x1B4 0x2 registers n 0x1E0 0x1 registers n 0x62 0x16 registers n 0x7A 0x5 registers n 0x80 0x9 registers n 0x8C 0x1 registers n 0x90 0x15 registers n 0xA6 0x1 registers n 0xA8 0x5 registers n 0xB0 0x21 registers n 0xD2 0x1 registers n 0xDD 0x23 registers n 0xE 0x52 registers n ADADC A/D-Converted Value Addition/Average Count Select Register 0xC 8 read-write n 0x0 0x0 ADC Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) 0 2 read-write others Setting prohibited 000 1-time conversion (no addition same as normal conversion) #000 001 2-time conversion (addition once) #001 010 3-time conversion (addition twice) #010 011 4-time conversion (addition three times) #011 101 16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy. #101 AVEE Average mode enable bit.Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode. 7 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x8 16 read-write n 0x0 0x0 ADS00 A/D-Converted Value Addition/Average Channel AN100 Select 0 read-write 0 AN100 is not selected. #0 1 AN100 is selected. #1 ADS01 A/D-Converted Value Addition/Average Channel AN101 Select 1 read-write 0 AN101 is not selected. #0 1 AN101 is selected. #1 ADS02 A/D-Converted Value Addition/Average Channel AN102 Select 2 read-write 0 AN102 is not selected. #0 1 AN102 is selected. #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0xA 16 read-write n 0x0 0x0 ADS16 A/D-Converted Value Addition/Average Channel AN116 Select 0 read-write 0 AN116 is not selected. #0 1 AN116 is selected. #1 ADS17 A/D-Converted Value Addition/Average Channel AN117 Select 1 read-write 0 AN117 is not selected. #0 1 AN117 is selected. #1 ADS18 A/D-Converted Value Addition/Average Channel AN118 Select 2 read-write 0 AN118 is not selected. #0 1 AN118 is selected. #1 ADS19 A/D-Converted Value Addition/Average Channel AN119 Select 3 read-write 0 AN119 is not selected. #0 1 AN119 is selected. #1 ADS20 A/D-Converted Value Addition/Average Channel AN120 Select 4 read-write 0 AN120 is not selected. #0 1 AN120 is selected. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write ADANSA0 A/D Channel Select Register A0 0x4 16 read-write n 0x0 0x0 ANSA00 AN100 Select 0 read-write 0 AN100 is not subjected to conversion. #0 1 AN100 is subjected to conversion. #1 ANSA01 AN101 Select 1 read-write 0 AN101 is not subjected to conversion. #0 1 AN101 is subjected to conversion. #1 ANSA02 AN102 Select 2 read-write 0 AN102 is not subjected to conversion. #0 1 AN102 is subjected to conversion. #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write ADANSA1 A/D Channel Select Register A1 0x6 16 read-write n 0x0 0x0 ANSA16 AN116 Select 0 read-write 0 AN116 is not subjected to conversion. #0 1 AN116 is subjected to conversion. #1 ANSA17 AN117 Select 1 read-write 0 AN117 is not subjected to conversion. #0 1 AN117 is subjected to conversion. #1 ANSA18 AN118 Select 2 read-write 0 AN118 is not subjected to conversion. #0 1 AN118 is subjected to conversion. #1 ANSA19 AN119 Select 3 read-write 0 AN119 is not subjected to conversion. #0 1 AN119 is subjected to conversion. #1 ANSA20 AN120 Select 4 read-write 0 AN120 is not subjected to conversion. #0 1 AN120 is subjected to conversion. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write ADANSB0 A/D Channel Select Register B0 0x14 16 read-write n 0x0 0x0 ANSB00 AN100 Select 0 read-write 0 AN100 is not subjected to conversion. #0 1 AN100 is subjected to conversion. #1 ANSB01 AN101 Select 1 read-write 0 AN101 is not subjected to conversion. #0 1 AN101 is subjected to conversion. #1 ANSB02 AN102 Select 2 read-write 0 AN102 is not subjected to conversion. #0 1 AN102 is subjected to conversion. #1 ANSB03 AN103 Select 3 read-write 0 AN103 is not subjected to conversion. #0 1 AN103 is subjected to conversion. #1 ANSB05 AN105 Select 5 read-write 0 AN105 is not subjected to conversion. #0 1 AN105 is subjected to conversion. #1 ANSB06 AN106 Select 6 read-write 0 AN106 is not subjected to conversion. #0 1 AN106 is subjected to conversion. #1 ANSB07 AN107 Select 7 read-write 0 AN107 is not subjected to conversion. #0 1 AN107 is subjected to conversion. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ADANSB1 A/D Channel Select Register B1 0x16 16 read-write n 0x0 0x0 ANSB16 AN116 Select 0 read-write 0 AN116 is not subjected to conversion. #0 1 AN116 is subjected to conversion. #1 ANSB17 AN117 Select 1 read-write 0 AN117 is not subjected to conversion. #0 1 AN117 is subjected to conversion. #1 ANSB18 AN118 Select 2 read-write 0 AN118 is not subjected to conversion. #0 1 AN118 is subjected to conversion. #1 ANSB19 AN119 Select 3 read-write 0 AN119 is not subjected to conversion. #0 1 AN119 is subjected to conversion. #1 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write ADBUF0 A/D Data Buffer Register 0xB0 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF1 A/D Data Buffer Register 0xB2 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF10 A/D Data Buffer Register 0xC4 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF11 A/D Data Buffer Register 0xC6 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF12 A/D Data Buffer Register 0xC8 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF13 A/D Data Buffer Register 0xCA 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF14 A/D Data Buffer Register 0xCC 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF15 A/D Data Buffer Register 0xCE 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF2 A/D Data Buffer Register 0xB4 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF3 A/D Data Buffer Register 0xB6 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF4 A/D Data Buffer Register 0xB8 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF5 A/D Data Buffer Register 0xBA 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF6 A/D Data Buffer Register 0xBC 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF7 A/D Data Buffer Register 0xBE 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF8 A/D Data Buffer Register 0xC0 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUF9 A/D Data Buffer Register 0xC2 16 read-only n 0x0 0x0 ADBUF A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. 0 15 read-only ADBUFEN A/D Data Buffer Enable Register 0xD0 8 read-write n 0x0 0x0 BUFEN Data Buffer Enable 0 read-write 0 The data buffer is not used. #0 1 The data buffer is used. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADBUFPTR A/D Data Buffer Pointer Register 0xD2 8 read-write n 0x0 0x0 zeroToClear modify BUFPTR Data Buffer PointerThese bits indicate the number of data buffer to which the next A/D converted data is transferred. 0 3 read-only PTROVF Pointer Overflow Flag 4 read-only 0 The data buffer pointer has not overflowed. #0 1 The data buffer pointer has overflowed. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write ADCER A/D Control Extended Register 0xE 16 read-write n 0x0 0x0 ACE A/D Data Register Automatic Clearing Enable 5 read-write 0 Disables automatic clearing. #0 1 Enables automatic clearing. #1 ADPRC A/D Conversion Accuracy Specify 1 1 read-write 00 A/D conversion is performed with 12-bit accuracy. #00 01 A/D conversion is performed with 10-bit accuracy. #01 10 A/D conversion is performed with 8-bit accuracy. #10 11 Setting prohibited #11 ADRFMT A/D Data Register Format Select 15 read-write 0 Flush-right is selected for the A/D data register format. #0 1 Flush-left is selected for the A/D data register format. #1 DIAGLD Self-Diagnosis Mode Select 10 read-write 0 Rotation mode for self-diagnosis voltage #0 1 Fixed mode for self-diagnosis voltage #1 DIAGM Self-Diagnosis Enable 11 read-write 0 Disables self-diagnosis of ADC12. #0 1 Enables self-diagnosis of ADC12. #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 1 read-write 00 When the self-diagnosis fixation mode is selected, it set prohibits it. #00 01 The self-diagnosis by using the voltage of 0V. #01 10 The self-diagnosis by using the voltage of reference supply x 1/2. #10 11 The self-diagnosis by using the voltage of the reference supply. #11 Reserved These bits are read as 000. The write value should be 000. 12 2 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 12 2 read-write ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x92 8 read-write n 0x0 0x0 CMPOCA Internal reference voltage Compare selection bit. 1 read-write 0 Excludes the internal reference voltage from the compare window A target range. #0 1 Includes the internal reference voltage in the compare window A target range. #1 CMPTSA Temperature sensor output Compare selection bit. 0 read-write 0 Excludes the temperature sensor output from the compare window A target range. #0 1 Includes the temperature sensor output in the compare window A target range. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x94 16 read-write n 0x0 0x0 CMPCHA00 Compare Window A Channel AN100 Select 0 read-write 0 Disable compare function for AN100 #0 1 Enable compare function for AN100 #1 CMPCHA01 Compare Window A Channel AN101 Select 1 read-write 0 Disable compare function for AN101 #0 1 Enable compare function for AN101 #1 CMPCHA02 Compare Window A Channel AN102 Select 2 read-write 0 Disable compare function for AN102 #0 1 Enable compare function for AN102 #1 CMPCHA03 Compare Window A Channel AN103 Select 3 read-write 0 Disable compare function for AN103 #0 1 Enable compare function for AN103 #1 CMPCHA05 Compare Window A Channel AN105 Select 5 read-write 0 Disable compare function for AN105 #0 1 Enable compare function for AN105 #1 CMPCHA06 Compare Window A Channel AN106 Select 6 read-write 0 Disable compare function for AN106 #0 1 Enable compare function for AN106 #1 CMPCHA07 Compare Window A Channel AN107 Select 7 read-write 0 Disable compare function for AN107 #0 1 Enable compare function for AN107 #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x96 16 read-write n 0x0 0x0 CMPCHA16 AN116 Select 0 read-write 0 Excludes AN116 from the compare window A target range. #0 1 Includes AN116 from the compare window A target range. #1 CMPCHA17 AN117 Select 1 read-write 0 Excludes AN117 from the compare window A target range. #0 1 Includes AN117 from the compare window A target range. #1 CMPCHA18 AN118 Select 2 read-write 0 Excludes AN118 from the compare window A target range. #0 1 Includes AN118 from the compare window A target range. #1 CMPCHA19 AN119 Select 3 read-write 0 Excludes AN119 from the compare window A target range. #0 1 Includes AN119 from the compare window A target range. #1 CMPCHA20 AN120 Select 4 read-write 0 Excludes AN120 from the compare window A target range. #0 1 Includes AN120 from the compare window A target range. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write ADCMPBNSR A/D Compare Function Window B Channel Selection Register 0xA6 8 read-write n 0x0 0x0 CMPCHB Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected. 0 5 read-write others Setting prohibited 0x00 AN100 0x00 0x01 AN101 0x01 0x02 AN102 0x02 0x03 AN103 0x03 0x05 AN105 0x05 0x06 AN106 0x06 0x07 AN107 0x07 0x10 AN116 0x10 0x11 AN117 0x11 0x12 AN118 0x12 0x13 AN119 0x13 0x20 Temperature sensor 0x20 0x21 Internal reference voltage 0x21 0x3F No channel is selected 0x3F CMPLB Compare window B Compare condition setting bit. 7 read-write 0 CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1) #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write ADCMPBSR A/D Compare Function Window B Status Register 0xAC 8 read-write n 0x0 0x0 CMPSTB Compare window B flag.It is a status flag that shows the comparative result of CH (AN100-AN103, AN105-AN107, AN116-AN119, temperature sensor, and internal reference voltage) made the object of window B relation condition. 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADCMPCR A/D Compare Function Control Register 0x90 16 read-write n 0x0 0x0 CMPAB Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1). 0 1 read-write 00 S12ADWMELC is output when window A comparison conditions are met OR window B comparison conditions are met. S12ADWUMELC is output in other cases. #00 01 S12ADWMELC is output when window A comparison conditions are met EXOR window B comparison conditions are met. S12ADWUMELC is output in other cases. #01 10 S12ADWMELC is output when window A comparison conditions are met and window B comparison conditions are met. S12ADWUMELC is output in other cases. #10 11 Setting prohibited. #11 CMPAE Compare Window A Operation Enable 11 read-write 0 Compare window A operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window A operation is enabled. #1 CMPAIE Compare A Interrupt Enable 15 read-write 0 S12ADCMPAIi interrupt is disabled when comparison conditions (window A) are met. #0 1 S12ADCMPAIi interrupt is enabled when comparison conditions (window A) are met. #1 CMPBE Compare Window B Operation Enable 9 read-write 0 Compare window B operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window B operation is enabled. #1 CMPBIE Compare B Interrupt Enable 13 read-write 0 S12ADCMPBIi interrupt is disabled when comparison conditions (window B) are met. #0 1 S12ADCMPBIi interrupt is enabled when comparison conditions (window B) are met. #1 Reserved This bit is read as 0. The write value should be 0. 12 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved This bit is read as 0. The write value should be 0. 12 read-write WCMPE Window Function Setting 14 read-write 0 Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result. #0 1 Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result. #1 ADCMPDR0 A/D Compare Function Window A Lower-Side Level Setting Register 0x9C 16 read-write n 0x0 0x0 ADCMPDR0 The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A. 0 15 read-write ADCMPDR1 A/D Compare Function Window A Upper-Side Level Setting Register 0x9E 16 read-write n 0x0 0x0 ADCMPDR1 The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.. 0 15 read-write ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x93 8 read-write n 0x0 0x0 CMPLOCA Compare Window A Internal Reference Voltage ComparisonCondition Select 1 read-write 0 ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1) #1 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 read-write 0 ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1). #0 1 ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x98 16 read-write n 0x0 0x0 CMPLCHA00 Comparison condition of AN100 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA01 Comparison condition of AN101 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA02 Comparison condition of AN102 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA03 Comparison condition of AN103 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA05 Comparison condition of AN105 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA06 Comparison condition of AN106 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA07 Comparison condition of AN107 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x9A 16 read-write n 0x0 0x0 CMPLCHA16 Comparison condition of AN116 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA17 Comparison condition of AN117 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA18 Comparison condition of AN118 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA19 Comparison condition of AN119 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0xA4 8 read-write n 0x0 0x0 CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0xA0 16 read-write n 0x0 0x0 CMPSTCHA00 Compare window A flag of AN000 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare window A flag of AN001 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare window A flag of AN002 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare window A flag of AN003 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare window A flag of AN005 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare window A flag of AN006 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA07 Compare window A flag of AN007 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ADCMPSR1 A/D Compare Function Window A Channel Status Register 1 0xA2 16 read-write n 0x0 0x0 CMPSTCHA16 Compare window A flag of AN016 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare window A flag of AN017 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare window A flag of AN018 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write ADCSR A/D Control Register 0x0 16 read-write n 0x0 0x0 ADCS Scan Mode Select 13 1 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 ADHSC A/D Conversion Operation Mode Select 10 read-write 0 High speed A/D conversion mode #0 1 Low current A/D conversion mode #1 ADIE Scan End Interrupt Enable 12 read-write 0 Disables S12ADI1 interrupt generation upon scan completion. #0 1 Enables S12ADI1 interrupt generation upon scan completion. #1 ADST A/D Conversion Start 15 read-write modify 0 Stops A/D conversion process. #0 1 Starts A/D conversion process. #1 DBLANS Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected. 0 4 read-write DBLE Double Trigger Mode Select 7 read-write 0 Double trigger mode non-selection #0 1 Double trigger mode selection #1 EXTRG Trigger Select 8 read-write 0 A/D conversion is started by the synchronous trigger (ELCTRG1). #0 1 A/D conversion is started by the asynchronous trigger (ADTRG1#). #1 GBADIE Group B Scan End Interrupt Enable 6 read-write 0 Disables S12GBADI1 interrupt generation upon group B scan completion. #0 1 Enables S12GBADI1 interrupt generation upon group B scan completion. #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write TRGE Trigger Start Enable 9 read-write 0 Disables A/D conversion to be started by the synchronous or asynchronous trigger. #0 1 Enables A/D conversion to be started by the synchronous or asynchronous trigger. #1 ADDBLDR A/D Data Duplication Register 0x18 16 read-only n 0x0 0x0 ADDBLDR This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode. 0 15 read-only ADDBLDRA A/D Data Duplication Register A 0x84 16 read-only n 0x0 0x0 ADDBLDRA This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDBLDRB A/D Data Duplication Register B 0x86 16 read-only n 0x0 0x0 ADDBLDRB This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDISCR A/D Disconnection Detection Control Register 0x7A 8 read-write n 0x0 0x0 ADNDIS The charging time 0 3 read-write others ( 1 / ADCLK ) x ADNDIS 0000 Disconnection detection is disabled #0000 0001 Setting prohibited #0001 PCHG Selection of Precharge or Discharge 4 read-write 0 Discharge #0 1 Precharge #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write ADDR0 A/D Data Register %s 0x20 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR1 A/D Data Register %s 0x22 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR10 A/D Data Register %s 0x34 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR11 A/D Data Register %s 0x36 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR12 A/D Data Register %s 0x38 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR13 A/D Data Register %s 0x3A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR14 A/D Data Register %s 0x3C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR15 A/D Data Register %s 0x3E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR16 A/D Data Register %s 0x40 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR17 A/D Data Register %s 0x42 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR18 A/D Data Register %s 0x44 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR19 A/D Data Register %s 0x46 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR2 A/D Data Register %s 0x24 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR20 A/D Data Register %s 0x48 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR21 A/D Data Register %s 0x4A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR22 A/D Data Register %s 0x4C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR23 A/D Data Register %s 0x4E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR24 A/D Data Register %s 0x50 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR25 A/D Data Register %s 0x52 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR26 A/D Data Register %s 0x54 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR27 A/D Data Register %s 0x56 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR28 A/D Data Register %s 0x58 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR29 A/D Data Register %s 0x5A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR3 A/D Data Register %s 0x26 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR30 A/D Data Register %s 0x5C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR31 A/D Data Register %s 0x5E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR4 A/D Data Register %s 0x28 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR5 A/D Data Register %s 0x2A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR6 A/D Data Register %s 0x2C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR7 A/D Data Register %s 0x2E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR8 A/D Data Register %s 0x30 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR9 A/D Data Register %s 0x32 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADEXICR A/D Conversion Extended Input Control Register 0x12 16 read-write n 0x0 0x0 OCSA Internal Reference Voltage A/D Conversion Select 9 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode. #1 OCSAD Internal Reference Voltage A/D converted Value Addition/Average Mode Select 1 read-write 0 Internal reference voltage A/D-converted value addition/average mode is not selected. #0 1 Internal reference voltage A/D-converted value addition/average mode is selected. #1 OCSB Internal Reference Voltage A/D Conversion Select for Group B 11 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group B in group scan mode. #1 Reserved This bit is read as 0. The write value should be 0. 15 read-write Reserved This bit is read as 0. The write value should be 0. 12 read-write Reserved This bit is read as 0. The write value should be 0. 14 read-write Reserved This bit is read as 0. The write value should be 0. 15 read-write TSSA Temperature Sensor Output A/D Conversion Select 8 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is selected. #1 TSSAD Temperature Sensor Output A/D converted Value Addition/Average Mode Select 0 read-write 0 Temperature sensor output A/D-converted value addition/average mode is not selected. #0 1 Temperature sensor output A/D-converted value addition/average mode is selected. #1 TSSB Temperature Sensor Output A/D Conversion Select for Group B 10 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is not selected for group B in group scan mode. #1 ADGSPCR A/D Group Scan Priority Control Register 0x80 16 read-write n 0x0 0x0 GBRP Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit. 15 read-write 0 Single scan for group B is not continuously activated. #0 1 Single scan for group B is continuously activated. #1 GBRSCN Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.) 1 read-write 0 Scanning for group B is not restarted after having been discontinued due to group A priority control. #0 1 Scanning for group B is restarted after having been discontinued due to group A priority control. #1 PGS Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed. 0 read-write 0 Operation is without group A priority control #0 1 Operation is with group A priority control #1 Reserved These bits are read as 000000. The write value should be 000000. 9 5 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 000000. The write value should be 000000. 9 5 read-write ADOCDR A/D Internal Reference Voltage Data Register 0x1C 16 read-only n 0x0 0x0 ADOCDR This is a 16-bit read-only register for storing the A/D result of internal reference voltage. 0 15 read-only ADPGACR A/D Programmable Gain Amplifier Control Register 0x1A0 16 read-write n 0x0 0x0 P000ENAMP Amplifier enable bit for PGA P000 2 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P000GEN PGA P000 gain setting and enable bit 3 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P000SEL0 A through amplifier is enable for PGA P000 0 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P000SEL1 The amplifier passing is enable for PGA P000 1 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P001ENAMP Amplifier enable bit for PGA P001 6 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P001GEN PGA P001 gain setting and enable bit 7 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P001SEL0 A through amplifier is enable for PGA P001 4 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P001SEL1 The amplifier passing is enable for PGA P001 5 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P002ENAMP Amplifier enable bit for PGA P002 10 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P002GEN PGA P002 gain setting and enable bit 11 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P002SEL0 A through amplifier is enable for PGA P002 8 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P002SEL1 The amplifier passing is enable for PGA P002 9 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 Reserved This bit is read as 1. The write value should be 1. 15 read-write Reserved This bit is read as 0. The write value should be 0. 13 read-write Reserved This bit is read as 0. The write value should be 0. 14 read-write Reserved This bit is read as 1. The write value should be 1. 15 read-write ADPGADCR0 A/D Programmable Gain Amplifier Differential Input Control Register 0x1B0 16 read-write n 0x0 0x0 P000DEN P000 Differential Input Enable 3 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P000DG P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b. 0 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P001DEN P001 Differential Input Enable 7 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P001DG P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b. 4 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P002DEN P002 Differential Input Enable 11 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P002DG P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b. 8 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 Reserved This bit is read as 0. The write value should be 0. 15 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved These bits are read as 00. The write value should be 00. 12 1 read-write Reserved This bit is read as 0. The write value should be 0. 14 read-write Reserved This bit is read as 0. The write value should be 0. 15 read-write ADPGAGS0 A/D Programmable Gain Amplifier Gain Setting Register 0 0x1A2 16 read-write n 0x0 0x0 P000GAIN PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0. 0 3 read-write 0000 x 2.000 (ADPGADDCR0.P000DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P000DEN=0) / x 1.500 (ADPGADDCR0.P000DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P000DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P000DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P000DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P000DEN=0) / x 2.333 (ADPGADDCR0.P000DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P000DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P000DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P000DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P000DEN=0) / x 4.00 (ADPGADDCR0.P000DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P000DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P000DEN=0) / x 5.667 (ADPGADDCR0.P000DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P000DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P000DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P000DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P000DEN=0) #1111 P001GAIN PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0. 4 3 read-write 0000 x 2.000 (ADPGADDCR0.P001DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P001DEN=0) / x 1.500 (ADPGADDCR0.P001DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P001DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P001DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P001DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P001DEN=0) / x 2.333 (ADPGADDCR0.P001DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P001DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P001DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P001DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P001DEN=0) / x 4.00 (ADPGADDCR0.P001DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P001DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P001DEN=0) / x 5.667 (ADPGADDCR0.P001DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P001DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P001DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P001DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P001DEN=0) #1111 P002GAIN PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0. 8 3 read-write 0000 x 2.000 (ADPGADDCR0.P002DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P002DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P002DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P002DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P002DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P002DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P002DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P002DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P002DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P002DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P002DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0) #1111 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write ADRD A/D Self-Diagnosis Data Register 0x1E 16 read-only n 0x0 0x0 AD A/D-converted value (right-justified)NOTE: Unused bits in the AD bit field are fixed 0 0 11 read-only DIAGST Self-Diagnosis Status 14 1 read-only 00 Self-diagnosis has never been executed since power-on. #00 01 Self-diagnosis using the voltage of 0 V has been executed. #01 10 Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. #10 11 Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. #11 Reserved These bits are read as 00. 12 1 read-only ADREFMON A/D External Reference Voltage Monitor Register 0x1E0 8 read-write n 0x0 0x0 MONSEL Monitor output selection bit. 4 3 read-write others Setting prohibited. 0000 No monitor output is selected. #0000 1000 P000 is selected. #1000 1001 P001 is selected. #1001 1010 P002 is selected. #1010 1011 P003 is selected. #1011 PGAMON PGA Monitor Output Enable 0 2 read-write others Setting prohibited. 000 The monitor output is disabled. #000 001 The monitor output is enabled. #001 Reserved This bit is read as 0. The write value should be 0. 3 read-write ADSHCR A/D Sample and Hold Circuit Control Register 0x66 16 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write SHANS0 AN100 sample-and-hold circuit Select 8 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS1 AN101 sample-and-hold circuit Select 9 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS2 AN102 sample-and-hold circuit Select 10 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SSTSH Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states) 0 7 read-write ADSHMSR A/D Sample and Hold Operation Mode Select Register 0x7C 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write SHMD Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select 0 read-write 0 Sampling by channel-dedicated sample-and-hold circuit is disable. #0 1 Sampling by channel-dedicated sample-and-hold circuit is enable. #1 ADSSTR0 A/D Sampling State Register %s 0xE0 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR1 A/D Sampling State Register %s 0xE1 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR10 A/D Sampling State Register %s 0xEA 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR11 A/D Sampling State Register %s 0xEB 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR12 A/D Sampling State Register %s 0xEC 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR13 A/D Sampling State Register %s 0xED 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR14 A/D Sampling State Register %s 0xEE 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR15 A/D Sampling State Register %s 0xEF 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR16 A/D Sampling State Register %s 0xF0 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR17 A/D Sampling State Register %s 0xF1 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR18 A/D Sampling State Register %s 0xF2 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR19 A/D Sampling State Register %s 0xF3 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR2 A/D Sampling State Register %s 0xE2 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR20 A/D Sampling State Register %s 0xF4 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR21 A/D Sampling State Register %s 0xF5 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR22 A/D Sampling State Register %s 0xF6 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR23 A/D Sampling State Register %s 0xF7 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR24 A/D Sampling State Register %s 0xF8 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR25 A/D Sampling State Register %s 0xF9 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR26 A/D Sampling State Register %s 0xFA 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR27 A/D Sampling State Register %s 0xFB 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR28 A/D Sampling State Register %s 0xFC 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR29 A/D Sampling State Register %s 0xFD 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR3 A/D Sampling State Register %s 0xE3 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR30 A/D Sampling State Register %s 0xFE 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR31 A/D Sampling State Register %s 0xFF 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR4 A/D Sampling State Register %s 0xE4 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR5 A/D Sampling State Register %s 0xE5 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR6 A/D Sampling State Register %s 0xE6 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR7 A/D Sampling State Register %s 0xE7 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR8 A/D Sampling State Register %s 0xE8 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR9 A/D Sampling State Register %s 0xE9 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTRL A/D Sampling State Register L 0xDD 8 read-write n 0x0 0x0 SST Sampling Time Setting (AN116-AN119) 0 7 read-write ADSSTRO A/D Sampling State Register O 0xDF 8 read-write n 0x0 0x0 SST Sampling Time Setting (Internal reference voltage) 0 7 read-write ADSSTRT A/D Sampling State Register T 0xDE 8 read-write n 0x0 0x0 SST Sampling Time Setting (temperature sensor output) 0 7 read-write ADSTRGR A/D Conversion Start Trigger Select Register 0x10 16 read-write n 0x0 0x0 Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write TRSA A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected. 8 5 read-write TRSB A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode. 0 5 read-write ADTSDR A/D Temperature Sensor Data Register 0x1A 16 read-only n 0x0 0x0 ADTSDR This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output. 0 15 read-only ADWINLLB A/D Compare Function Window B Lower-Side Level Setting Register 0xA8 16 read-write n 0x0 0x0 ADWINLLB This register is used to compare A window function is used to set the lower level of the window B. 0 15 read-write ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x8C 8 read-only n 0x0 0x0 MONCMPA Comparison Result Monitor A 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCMPB Comparison Result Monitor B 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 MONCOMB Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled. 0 read-only 0 Window A / window B composite conditions are not met. #0 1 Window A / window B composite conditions are met. #1 Reserved These bits are read as 00. 6 1 read-only Reserved These bits are read as 00. 6 1 read-only ADWINULB A/D Compare Function Window B Upper-Side Level Setting Register 0xAA 16 read-write n 0x0 0x0 ADWINULB This register is used to compare A window function is used to set the higher level of the window B. 0 15 read-write AGT0 Asynchronous General purpose Timer 0 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF AGT compare match A flag 6 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCMBF AGT compare match B flag 7 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count starts #1 TEDGF Active edge judgement flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT count forced stop 2 write-only 0 no effect #0 1 The count is forcibly stopped. #1 TUNDF AGT underflow flag 5 read-write zeroToClear modify 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT AGTIO count control 6 1 read-write others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEE #01 TIPF AGTIO input filter select 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTO output enable 2 read-write 0 AGTO output disabled (port) #0 1 AGTO output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 AGTIO_A can not be used as AGTIO input pin in deep software standby mode #00 01 Setting prohibited #01 10 AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. #10 11 AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. #11 TIES AGTIO input enable 4 read-write 0 external event input disable during software standby mode #0 1 external event input enable during software standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK AGT count source select 4 2 read-write others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock LOCO specified by AGTMR2.CKS bit. #100 101 Underflow event signal from AGT #101 110 Divided clock fSUB specified by AGTMR2.CKS bit. #110 TEDGPL AGTIO edge polarity select 3 read-write 0 One edge #0 1 Both edges #1 TMOD AGT operating mode select 0 2 read-write others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS fsub/LOCO count source clock frequency division ratio select 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM AGT Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write AGT1 Asynchronous General purpose Timer 1 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF AGT compare match A flag 6 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCMBF AGT compare match B flag 7 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count starts #1 TEDGF Active edge judgement flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT count forced stop 2 write-only 0 no effect #0 1 The count is forcibly stopped. #1 TUNDF AGT underflow flag 5 read-write zeroToClear modify 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT AGTIO count control 6 1 read-write others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEE #01 TIPF AGTIO input filter select 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTO output enable 2 read-write 0 AGTO output disabled (port) #0 1 AGTO output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 AGTIO_A can not be used as AGTIO input pin in deep software standby mode #00 01 Setting prohibited #01 10 AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. #10 11 AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. #11 TIES AGTIO input enable 4 read-write 0 external event input disable during software standby mode #0 1 external event input enable during software standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK AGT count source select 4 2 read-write others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock LOCO specified by AGTMR2.CKS bit. #100 101 Underflow event signal from AGT #101 110 Divided clock fSUB specified by AGTMR2.CKS bit. #110 TEDGPL AGTIO edge polarity select 3 read-write 0 One edge #0 1 Both edges #1 TMOD AGT operating mode select 0 2 read-write others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS fsub/LOCO count source clock frequency division ratio select 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM AGT Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write AGT2 Asynchronous General purpose Timer 2 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF AGT compare match A flag 6 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCMBF AGT compare match B flag 7 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count starts #1 TEDGF Active edge judgement flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT count forced stop 2 write-only 0 no effect #0 1 The count is forcibly stopped. #1 TUNDF AGT underflow flag 5 read-write zeroToClear modify 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT AGTIO count control 6 1 read-write others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEE #01 TIPF AGTIO input filter select 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTO output enable 2 read-write 0 AGTO output disabled (port) #0 1 AGTO output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 AGTIO_A can not be used as AGTIO input pin in deep software standby mode #00 01 Setting prohibited #01 10 AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. #10 11 AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. #11 TIES AGTIO input enable 4 read-write 0 external event input disable during software standby mode #0 1 external event input enable during software standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK AGT count source select 4 2 read-write others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock LOCO specified by AGTMR2.CKS bit. #100 101 Underflow event signal from AGT #101 110 Divided clock fSUB specified by AGTMR2.CKS bit. #110 TEDGPL AGTIO edge polarity select 3 read-write 0 One edge #0 1 Both edges #1 TMOD AGT operating mode select 0 2 read-write others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS fsub/LOCO count source clock frequency division ratio select 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM AGT Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write AGT3 Asynchronous General purpose Timer 3 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF AGT compare match A flag 6 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCMBF AGT compare match B flag 7 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count starts #1 TEDGF Active edge judgement flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT count forced stop 2 write-only 0 no effect #0 1 The count is forcibly stopped. #1 TUNDF AGT underflow flag 5 read-write zeroToClear modify 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT AGTIO count control 6 1 read-write others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEE #01 TIPF AGTIO input filter select 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTO output enable 2 read-write 0 AGTO output disabled (port) #0 1 AGTO output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 AGTIO_A can not be used as AGTIO input pin in deep software standby mode #00 01 Setting prohibited #01 10 AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. #10 11 AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. #11 TIES AGTIO input enable 4 read-write 0 external event input disable during software standby mode #0 1 external event input enable during software standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK AGT count source select 4 2 read-write others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock LOCO specified by AGTMR2.CKS bit. #100 101 Underflow event signal from AGT #101 110 Divided clock fSUB specified by AGTMR2.CKS bit. #110 TEDGPL AGTIO edge polarity select 3 read-write 0 One edge #0 1 Both edges #1 TMOD AGT operating mode select 0 2 read-write others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS fsub/LOCO count source clock frequency division ratio select 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM AGT Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write AGT4 Asynchronous General purpose Timer 4 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF AGT compare match A flag 6 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCMBF AGT compare match B flag 7 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count starts #1 TEDGF Active edge judgement flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT count forced stop 2 write-only 0 no effect #0 1 The count is forcibly stopped. #1 TUNDF AGT underflow flag 5 read-write zeroToClear modify 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT AGTIO count control 6 1 read-write others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEE #01 TIPF AGTIO input filter select 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTO output enable 2 read-write 0 AGTO output disabled (port) #0 1 AGTO output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 AGTIO_A can not be used as AGTIO input pin in deep software standby mode #00 01 Setting prohibited #01 10 AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. #10 11 AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. #11 TIES AGTIO input enable 4 read-write 0 external event input disable during software standby mode #0 1 external event input enable during software standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK AGT count source select 4 2 read-write others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock LOCO specified by AGTMR2.CKS bit. #100 101 Underflow event signal from AGT #101 110 Divided clock fSUB specified by AGTMR2.CKS bit. #110 TEDGPL AGTIO edge polarity select 3 read-write 0 One edge #0 1 Both edges #1 TMOD AGT operating mode select 0 2 read-write others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS fsub/LOCO count source clock frequency division ratio select 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM AGT Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write AGT5 Asynchronous General purpose Timer 5 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF AGT compare match A flag 6 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCMBF AGT compare match B flag 7 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count starts #1 TEDGF Active edge judgement flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts #1 TSTOP AGT count forced stop 2 write-only 0 no effect #0 1 The count is forcibly stopped. #1 TUNDF AGT underflow flag 5 read-write zeroToClear modify 0 No underflow #0 1 Underflow #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT AGTIO count control 6 1 read-write others Setting prohibited 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEE #01 TIPF AGTIO input filter select 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTO output enable 2 read-write 0 AGTO output disabled (port) #0 1 AGTO output enabled #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 AGTIO_A can not be used as AGTIO input pin in deep software standby mode #00 01 Setting prohibited #01 10 AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. #10 11 AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. #11 TIES AGTIO input enable 4 read-write 0 external event input disable during software standby mode #0 1 external event input enable during software standby mode #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK AGT count source select 4 2 read-write others Setting prohibited 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock LOCO specified by AGTMR2.CKS bit. #100 101 Underflow event signal from AGT #101 110 Divided clock fSUB specified by AGTMR2.CKS bit. #110 TEDGPL AGTIO edge polarity select 3 read-write 0 One edge #0 1 Both edges #1 TMOD AGT operating mode select 0 2 read-write others Setting prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS fsub/LOCO count source clock frequency division ratio select 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 LPM AGT Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write BUS BUS Control BUS 0x0 0x1000 0x8 registers n 0x1100 0x8 registers n 0x1110 0x2 registers n 0x1120 0x2 registers n 0x1130 0x8 registers n 0x1140 0xC registers n 0x1800 0x44 registers n 0x1900 0x44 registers n 0x1A00 0x48 registers n 0x2 0x86 registers n 0x802 0x2 registers n 0x80A 0x80 registers n BTZF1ERRADD Bus TZF Error Address Register %s 0x1900 32 read-only n 0x0 0x0 BERAD Bus Error Address 0 31 read-only BTZF1ERRRW Bus ZTF Error RW Register %s 0x1904 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only TRWSTAT Trust zone filter error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BTZF2ERRADD Bus TZF Error Address Register %s 0x1910 32 read-only n 0x0 0x0 BERAD Bus Error Address 0 31 read-only BTZF2ERRRW Bus ZTF Error RW Register %s 0x1914 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only TRWSTAT Trust zone filter error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BTZF3ERRADD Bus TZF Error Address Register %s 0x1920 32 read-only n 0x0 0x0 BERAD Bus Error Address 0 31 read-only BTZF3ERRRW Bus ZTF Error RW Register %s 0x1924 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only TRWSTAT Trust zone filter error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BTZF4ERRADD Bus TZF Error Address Register %s 0x1930 32 read-only n 0x0 0x0 BERAD Bus Error Address 0 31 read-only BTZF4ERRRW Bus ZTF Error RW Register %s 0x1934 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only TRWSTAT Trust zone filter error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BUS1ERRADD Bus Error Address Register %s 0x1800 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS1ERRCLR Bus Error Status Register %s 0x1A08 8 read-write n 0x0 0x0 ILERRCLR ILlegal address access ERRor Clear 4 read-write MMERRCLR Master Mpu ERRor CLeaR 3 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SLERRCLR SLave bus ERRor CLeaR 0 read-write SMERRCLR Slave Mpu ERRor CLeaR 2 read-write STERRCLR Slave Trust zone filter ERRor CLeaR 1 read-write BUS1ERRRW Bus Error RW Register %s 0x1804 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only RWSTAT error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BUS1ERRSTAT Bus Error Status Register %s 0x1A00 8 read-only n 0x0 0x0 ILERRSTAT ILlegal address access ERRor STATus 4 read-only 0 No error occurred #0 1 Error occurred #1 MMERRSTAT Master Mpu ERRor STATus 3 read-only 0 No error occurred #0 1 Error occurred #1 Reserved These bits are read as 000. 5 2 read-only SLERRSTAT SLave bus ERRor STATus 0 read-only 0 No error occurred #0 1 Error occurred #1 SMERRSTAT Slave Mpu ERRor STATus 2 read-only 0 No error occurred #0 1 Error occurred. #1 STERRSTAT Slave Trust zone filter ERRor STATus 1 read-only 0 No error occurred #0 1 Error occurred #1 BUS2ERRADD Bus Error Address Register %s 0x1810 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS2ERRCLR Bus Error Status Register %s 0x1A18 8 read-write n 0x0 0x0 ILERRCLR ILlegal address access ERRor Clear 4 read-write MMERRCLR Master Mpu ERRor CLeaR 3 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SLERRCLR SLave bus ERRor CLeaR 0 read-write SMERRCLR Slave Mpu ERRor CLeaR 2 read-write STERRCLR Slave Trust zone filter ERRor CLeaR 1 read-write BUS2ERRRW Bus Error RW Register %s 0x1814 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only RWSTAT error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BUS2ERRSTAT Bus Error Status Register %s 0x1A10 8 read-only n 0x0 0x0 ILERRSTAT ILlegal address access ERRor STATus 4 read-only 0 No error occurred #0 1 Error occurred #1 MMERRSTAT Master Mpu ERRor STATus 3 read-only 0 No error occurred #0 1 Error occurred #1 Reserved These bits are read as 000. 5 2 read-only SLERRSTAT SLave bus ERRor STATus 0 read-only 0 No error occurred #0 1 Error occurred #1 SMERRSTAT Slave Mpu ERRor STATus 2 read-only 0 No error occurred #0 1 Error occurred. #1 STERRSTAT Slave Trust zone filter ERRor STATus 1 read-only 0 No error occurred #0 1 Error occurred #1 BUS3ERRADD Bus Error Address Register %s 0x1820 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS3ERRCLR Bus Error Status Register %s 0x1A28 8 read-write n 0x0 0x0 ILERRCLR ILlegal address access ERRor Clear 4 read-write MMERRCLR Master Mpu ERRor CLeaR 3 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SLERRCLR SLave bus ERRor CLeaR 0 read-write SMERRCLR Slave Mpu ERRor CLeaR 2 read-write STERRCLR Slave Trust zone filter ERRor CLeaR 1 read-write BUS3ERRRW Bus Error RW Register %s 0x1824 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only RWSTAT error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BUS3ERRSTAT Bus Error Status Register %s 0x1A20 8 read-only n 0x0 0x0 ILERRSTAT ILlegal address access ERRor STATus 4 read-only 0 No error occurred #0 1 Error occurred #1 MMERRSTAT Master Mpu ERRor STATus 3 read-only 0 No error occurred #0 1 Error occurred #1 Reserved These bits are read as 000. 5 2 read-only SLERRSTAT SLave bus ERRor STATus 0 read-only 0 No error occurred #0 1 Error occurred #1 SMERRSTAT Slave Mpu ERRor STATus 2 read-only 0 No error occurred #0 1 Error occurred. #1 STERRSTAT Slave Trust zone filter ERRor STATus 1 read-only 0 No error occurred #0 1 Error occurred #1 BUS4ERRADD Bus Error Address Register %s 0x1830 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS4ERRCLR Bus Error Status Register %s 0x1A38 8 read-write n 0x0 0x0 ILERRCLR ILlegal address access ERRor Clear 4 read-write MMERRCLR Master Mpu ERRor CLeaR 3 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SLERRCLR SLave bus ERRor CLeaR 0 read-write SMERRCLR Slave Mpu ERRor CLeaR 2 read-write STERRCLR Slave Trust zone filter ERRor CLeaR 1 read-write BUS4ERRRW Bus Error RW Register %s 0x1834 8 read-only n 0x0 0x0 Reserved These bits are read as 0000000. 1 6 read-only RWSTAT error access Read/Write STAtus 0 read-only 0 Read access #0 1 Write access #1 BUS4ERRSTAT Bus Error Status Register %s 0x1A30 8 read-only n 0x0 0x0 ILERRSTAT ILlegal address access ERRor STATus 4 read-only 0 No error occurred #0 1 Error occurred #1 MMERRSTAT Master Mpu ERRor STATus 3 read-only 0 No error occurred #0 1 Error occurred #1 Reserved These bits are read as 000. 5 2 read-only SLERRSTAT SLave bus ERRor STATus 0 read-only 0 No error occurred #0 1 Error occurred #1 SMERRSTAT Slave Mpu ERRor STATus 2 read-only 0 No error occurred #0 1 Error occurred. #1 STERRSTAT Slave Trust zone filter ERRor STATus 1 read-only 0 No error occurred #0 1 Error occurred #1 BUSMCNTM4D Master Bus Control Register %s 0x1004 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 Bus error will be reported. #0 1 Bus error will not be reported. #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 0 14 read-write BUSMCNTM4I Master Bus Control Register %s 0x1000 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 Bus error will be reported. #0 1 Bus error will not be reported. #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 0 14 read-write BUSSCNTECBIU Slave Bus Control Register %s 0x1148 16 read-write n 0x0 0x0 ARBS3 ARBitration Select for 3 master 0 1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 2 13 read-write BUSSCNTEOBIU Slave Bus Control Register %s 0x1144 16 read-write n 0x0 0x0 ARBS3 ARBitration Select for 3 master 0 1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 2 13 read-write BUSSCNTEQBIU Slave Bus Control Register %s 0x1140 16 read-write n 0x0 0x0 ARBS3 ARBitration Select for 3 master 0 1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 2 13 read-write BUSSCNTFHBIU Slave Bus Control Register %s 0x1100 16 read-write n 0x0 0x0 ARBS3 ARBitration Select for 3 master 0 1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 2 13 read-write BUSSCNTFLBIU Slave Bus Control Register %s 0x1104 16 read-write n 0x0 0x0 ARBS3 ARBitration Select for 3 master 0 1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 2 13 read-write BUSSCNTPHBIU Slave Bus Control Register %s 0x1134 16 read-write n 0x0 0x0 ARBS2 ARBitration Select for 2 master 0 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 14 read-write BUSSCNTPLBIU Slave Bus Control Register %s 0x1130 16 read-write n 0x0 0x0 ARBS2 ARBitration Select for 2 master 0 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 14 read-write BUSSCNTPSBIU Slave Bus Control Register S0BIU 0x1120 16 read-write n 0x0 0x0 ARBS2 ARBitration Select for 2 master 0 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 14 read-write BUSSCNTS0BIU Slave Bus Control Register S0BIU 0x1110 16 read-write n 0x0 0x0 ARBS3 ARBitration Select for 3 master 0 1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 2 13 read-write CS0CR CS0 Control Register 0x802 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS0MOD CS%s Mode Register 0x2 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS0REC CS%s Recovery Cycle Register 0x80A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS0WCR1 CS%s Wait Control Register 1 0x4 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS0WCR2 CS%s Wait Control Register 2 0x8 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS1CR CS%s Control Register 0x812 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS1MOD CS%s Mode Register 0x12 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS1REC CS%s Recovery Cycle Register 0x81A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS1WCR1 CS%s Wait Control Register 1 0x14 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS1WCR2 CS%s Wait Control Register 2 0x18 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS2CR CS%s Control Register 0x822 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS2MOD CS%s Mode Register 0x22 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS2REC CS%s Recovery Cycle Register 0x82A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS2WCR1 CS%s Wait Control Register 1 0x24 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS2WCR2 CS%s Wait Control Register 2 0x28 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS3CR CS%s Control Register 0x832 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS3MOD CS%s Mode Register 0x32 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS3REC CS%s Recovery Cycle Register 0x83A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS3WCR1 CS%s Wait Control Register 1 0x34 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS3WCR2 CS%s Wait Control Register 2 0x38 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS4CR CS%s Control Register 0x842 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS4MOD CS%s Mode Register 0x42 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS4REC CS%s Recovery Cycle Register 0x84A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS4WCR1 CS%s Wait Control Register 1 0x44 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS4WCR2 CS%s Wait Control Register 2 0x48 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS5CR CS%s Control Register 0x852 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS5MOD CS%s Mode Register 0x52 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS5REC CS%s Recovery Cycle Register 0x85A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS5WCR1 CS%s Wait Control Register 1 0x54 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS5WCR2 CS%s Wait Control Register 2 0x58 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS6CR CS%s Control Register 0x862 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS6MOD CS%s Mode Register 0x62 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS6REC CS%s Recovery Cycle Register 0x86A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS6WCR1 CS%s Wait Control Register 1 0x64 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS6WCR2 CS%s Wait Control Register 2 0x68 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS7CR CS%s Control Register 0x872 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disable operation #0 1 Enable operation #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write CS7MOD CS%s Mode Register 0x72 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 read-write 0 Disable #0 1 Enable #1 PRMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS7REC CS%s Recovery Cycle Register 0x87A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS7WCR1 CS%s Wait Control Register 1 0x74 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write CS7WCR2 CS%s Wait Control Register 2 0x78 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 31 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRECEN CS Recovery Cycle Insertion Enable Register 0x880 16 read-write n 0x0 0x0 RCVEN0 Separate Bus Recovery Cycle Insertion Enable 0 0 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN1 Separate Bus Recovery Cycle Insertion Enable 1 1 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN2 Separate Bus Recovery Cycle Insertion Enable 2 2 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN3 Separate Bus Recovery Cycle Insertion Enable 3 3 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN4 Separate Bus Recovery Cycle Insertion Enable 4 4 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN5 Separate Bus Recovery Cycle Insertion Enable 5 5 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN6 Separate Bus Recovery Cycle Insertion Enable 6 6 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN7 Separate Bus Recovery Cycle Insertion Enable 7 7 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM0 Multiplexed Bus Recovery Cycle Insertion Enable 0 8 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM1 Multiplexed Bus Recovery Cycle Insertion Enable 1 9 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM2 Multiplexed Bus Recovery Cycle Insertion Enable 2 10 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM3 Multiplexed Bus Recovery Cycle Insertion Enable 3 11 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM4 Multiplexed Bus Recovery Cycle Insertion Enable 4 12 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM5 Multiplexed Bus Recovery Cycle Insertion Enable 5 13 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM6 Multiplexed Bus Recovery Cycle Insertion Enable 6 14 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM7 Multiplexed Bus Recovery Cycle Insertion Enable 7 15 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 DMACDTCERRCLR DMAC_DTC_ERROR_CLR Register 0x1A2C 8 read-only n 0x0 0x0 MTERRCLR Master Trust zone filter ERRor STATus 0 read-only 0 No error occurred #0 1 Error occurred. #1 Reserved These bits are read as 0000000. 1 6 read-only DMACDTCERRSTAT DMAC_DTC_ERROR_STAT Register 0x1A24 8 read-only n 0x0 0x0 MTERRSTAT Master Trust zone filter ERRor STATus 0 read-only 0 No error occurred #0 1 Error occurred. #1 Reserved These bits are read as 0000000. 1 6 read-only CAC Clock Frequency Accuracy Measurement Circuit CAC 0x0 0x0 0x5 registers n 0x6 0x6 registers n CACNTBR CAC Counter Buffer Register 0xA 16 read-only n 0x0 0x0 CACR0 CAC Control Register 0 0x0 8 read-write n 0x0 0x0 CFME Clock Frequency Measurement Enable 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x1 8 read-write n 0x0 0x0 CACREFE CACREF Pin Input Enable 0 read-write 0 Disable #0 1 Enable #1 EDGES Valid Edge Select 6 1 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 FMCS Measurement Target Clock Select 1 2 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock L (PCLKL) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 TCSS Measurement Target Clock Frequency Division Ratio Select 4 1 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 CACR2 CAC Control Register 2 0x2 8 read-write n 0x0 0x0 DFS Digital Filter Select 6 1 read-write 00 Disable digital filtering #00 01 Use sampling clock for the digital filter as the frequency measuring clock #01 10 Use sampling clock for the digital filter as the frequency measuring clock divided by 4 #10 11 Use sampling clock for the digital filter as the frequency measuring clock divided by 16. #11 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 1 read-write 00 x 1/32 clock #00 01 x 1/128 clock #01 10 x 1/1024 clock #10 11 x 1/8192 clock #11 RPS Reference Signal Select 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 RSCS Measurement Reference Clock Select 1 2 read-write 000 Main clock oscillator #000 001 Sub-clock oscillator #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock L (PCLKL) #101 110 IWDT-dedicated clock #110 111 Setting prohibited #111 CAICR CAC Interrupt Control Register 0x3 8 read-write n 0x0 0x0 FERRFCL FERRF Clear 4 write-only 0 No effect #0 1 The CASTR.FERRF flag is cleared #1 FERRIE Frequency Error Interrupt Request Enable 0 read-write 0 Disable #0 1 Enable #1 MENDFCL MENDF Clear 5 write-only 0 No effect #0 1 The CASTR.MENDF flag is cleared #1 MENDIE Measurement End Interrupt Request Enable 1 read-write 0 Disable #0 1 Enable #1 OVFFCL OVFF Clear 6 write-only 0 No effect #0 1 The CASTR.OVFF flag is cleared. #1 OVFIE Overflow Interrupt Request Enable 2 read-write 0 Disable #0 1 Enable #1 CALLVR CAC Lower-Limit Value Setting Register 0x8 16 read-write n 0x0 0x0 CASTR CAC Status Register 0x4 8 read-only n 0x0 0x0 FERRF Frequency Error Flag 0 read-only 0 Clock frequency is within the allowable range #0 1 Clock frequency has deviated beyond the allowable range (frequency error). #1 MENDF Measurement End Flag 1 read-only 0 Measurement is in progress #0 1 Measurement ended #1 OVFF Overflow Flag 2 read-only 0 Counter has not overflowed #0 1 Counter overflowed #1 CAULVR CAC Upper-Limit Value Setting Register 0x6 16 read-write n 0x0 0x0 CAN0 Controller Area Network 0 CAN0 0x0 0x200 0x230 registers n 0x820 0x39 registers n AFSR Acceptance Filter Support Register 0x856 16 read-write n 0x0 0x0 BCR Bit Configuration Register 0x844 32 read-write n 0x0 0x0 BRP Baud Rate Prescaler Select 16 9 read-write CCLKS CAN Clock Source Selection 0 read-write 0 PCLKL (generated by the PLL clock) #0 1 CANMCLK (generated by the main clock oscillator) #1 SJW Synchronization Jump Width Control 12 1 read-write 00 1 Tq #00 01 2 Tq #01 10 3 Tq #10 11 4 Tq #11 TSEG1 Time Segment 1 Control 28 3 read-write Others Setting prohibited 0x3 4 Tq 0x3 0x4 5 Tq 0x4 0x5 6 Tq 0x5 0x6 7 Tq 0x6 0x7 8 Tq 0x7 0x8 9 Tq 0x8 0x9 10 Tq 0x9 0xA 11 Tq 0xa 0xB 12 Tq 0xb 0xC 13 Tq 0xc 0xD 14 Tq 0xd 0xE 15 Tq 0xe 0xF 16 Tq 0xf TSEG2 Time Segment 2 Control 8 2 read-write 000 Setting prohibited #000 001 2 Tq #001 010 3 Tq #010 011 4 Tq #011 100 5 Tq #100 101 6 Tq #101 110 7 Tq #110 111 8 Tq #111 CSSR Channel Search Support Register 0x851 8 read-write n 0x0 0x0 CTLR Control Register 0x840 16 read-write n 0x0 0x0 BOM Bus-Off Recovery Mode 11 1 read-write 00 Normal mode (ISO11898-1-compliant) #00 01 Enter CAN halt mode automatically on entering bus-off state #01 10 Enter CAN halt mode automatically at the end of bus-off state #10 11 Enter CAN halt mode during bus-off recovery period through a software request #11 CANM CAN Operating Mode Select 8 1 read-write 00 CAN operation mode #00 01 CAN reset mode #01 10 CAN halt mode #10 11 CAN reset mode (forced transition) #11 IDFM ID Format Mode Select 1 1 read-write 00 Standard ID mode All mailboxes, including FIFO mailboxes, handle only standard IDs #00 01 Extended ID mode All mailboxes, including FIFO mailboxes, handle only extended IDs #01 10 Mixed ID mode All mailboxes, including FIFO mailboxes, handle both standard and extended IDs. In normal mailbox mode, use the associated IDE bit to differentiate standard and extended IDs. In FIFO mailbox mode, the associated IDE bits are used for mailboxes 0 to 23, the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit associated with mailbox 24 is used for the transmit FIFO. #10 11 Setting prohibited #11 MBM CAN Mailbox Mode Select 0 read-write 0 Normal mailbox mode #0 1 FIFO mailbox mode #1 MLM Message Lost Mode Select 3 read-write 0 Overwrite mode #0 1 Overrun mode #1 RBOC Forcible Return from Bus-Off 13 read-write 0 No return occurred #0 1 Forced return from bus-off state #1 SLPM CAN Sleep Mode 10 read-write 0 All other modes #0 1 CAN sleep mode #1 TPM Transmission Priority Mode Select 4 read-write 0 ID priority transmit mode #0 1 Mailbox number priority transmit mode #1 TSPS Time Stamp Prescaler Select 6 1 read-write 00 Every 1-bit time #00 01 Every 2-bit time #01 10 Every 4-bit time #10 11 Every 8-bit time #11 TSRC Time Stamp Counter Reset Command 5 read-write 0 Do not reset time stamp counter #0 1 Reset time stamp counter #1 ECSR Error Code Store Register 0x850 8 read-write n 0x0 0x0 ADEF ACK Delimiter Error Flag 6 read-write 0 No ACK delimiter error detected #0 1 ACK delimiter error detected #1 AEF ACK Error Flag 2 read-write 0 No ACK error detected #0 1 ACK error detected #1 BE0F Bit Error (dominant) Flag 5 read-write 0 No bit error (dominant) detected #0 1 Bit error (dominant) detected #1 BE1F Bit Error (recessive) Flag 4 read-write 0 No bit error (recessive) detected #0 1 Bit error (recessive) detected #1 CEF CRC Error Flag 3 read-write 0 No CRC error detected #0 1 CRC error detected #1 EDPM Error Display Mode Select 7 read-write 0 Output first detected error code #0 1 Output accumulated error code #1 FEF Form Error Flag 1 read-write 0 No form error detected #0 1 Form error detected #1 SEF Stuff Error Flag 0 read-write 0 No stuff error detected #0 1 Stuff error detected #1 EIER Error Interrupt Enable Register 0x84C 8 read-write n 0x0 0x0 BEIE Bus Error Interrupt Enable 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BLIE Bus Lock Interrupt Enable 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BOEIE Bus-Off Entry Interrupt Enable 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BORIE Bus-Off Recovery Interrupt Enable 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EPIE Error-Passive Interrupt Enable 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EWIE Error-Warning Interrupt Enable 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 OLIE Overload Frame Transmit Interrupt Enable 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 ORIE Overrun Interrupt Enable 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EIFR Error Interrupt Factor Judge Register 0x84D 8 read-write n 0x0 0x0 BEIF Bus Error Detect Flag 0 read-write 0 No bus error detected #0 1 Bus error detected #1 BLIF Bus Lock Detect Flag 7 read-write 0 No bus lock detected #0 1 Bus lock detected #1 BOEIF Bus-Off Entry Detect Flag 3 read-write 0 No bus-off entry detected #0 1 Bus-off entry detected #1 BORIF Bus-Off Recovery Detect Flag 4 read-write 0 No bus-off recovery detected #0 1 Bus-off recovery detected #1 EPIF Error-Passive Detect Flag 2 read-write 0 No error-passive detected #0 1 Error-passive detected #1 EWIF Error-Warning Detect Flag 1 read-write 0 No error-warning detected #0 1 Error-warning detected #1 OLIF Overload Frame Transmission Detect Flag 6 read-write 0 No overload frame transmission detected #0 1 Overload frame transmission detected #1 ORIF Receive Overrun Detect Flag 5 read-write 0 No receive overrun detected #0 1 Receive overrun detected #1 FIDCR0 FIFO Received ID Compare Register %s 0x420 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write FIDCR1 FIFO Received ID Compare Register %s 0x424 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB0_D0 Mailbox Data Register %s 0x206 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB0_D1 Mailbox Data Register %s 0x207 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB0_D2 Mailbox Data Register %s 0x208 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB0_D3 Mailbox Data Register %s 0x209 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB0_D4 Mailbox Data Register %s 0x20A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB0_D5 Mailbox Data Register %s 0x20B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB0_D6 Mailbox Data Register %s 0x20C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB0_D7 Mailbox Data Register %s 0x20D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB0_DL Mailbox Data Length Register %s 0x204 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB0_ID Mailbox ID Register %s 0x200 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB0_TS Mailbox Time Stamp Register %s 0x20E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB10_D0 Mailbox Data Register %s 0x2A6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB10_D1 Mailbox Data Register %s 0x2A7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB10_D2 Mailbox Data Register %s 0x2A8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB10_D3 Mailbox Data Register %s 0x2A9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB10_D4 Mailbox Data Register %s 0x2AA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB10_D5 Mailbox Data Register %s 0x2AB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB10_D6 Mailbox Data Register %s 0x2AC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB10_D7 Mailbox Data Register %s 0x2AD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB10_DL Mailbox Data Length Register %s 0x2A4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB10_ID Mailbox ID Register %s 0x2A0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB10_TS Mailbox Time Stamp Register %s 0x2AE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB11_D0 Mailbox Data Register %s 0x2B6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB11_D1 Mailbox Data Register %s 0x2B7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB11_D2 Mailbox Data Register %s 0x2B8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB11_D3 Mailbox Data Register %s 0x2B9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB11_D4 Mailbox Data Register %s 0x2BA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB11_D5 Mailbox Data Register %s 0x2BB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB11_D6 Mailbox Data Register %s 0x2BC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB11_D7 Mailbox Data Register %s 0x2BD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB11_DL Mailbox Data Length Register %s 0x2B4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB11_ID Mailbox ID Register %s 0x2B0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB11_TS Mailbox Time Stamp Register %s 0x2BE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB12_D0 Mailbox Data Register %s 0x2C6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB12_D1 Mailbox Data Register %s 0x2C7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB12_D2 Mailbox Data Register %s 0x2C8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB12_D3 Mailbox Data Register %s 0x2C9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB12_D4 Mailbox Data Register %s 0x2CA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB12_D5 Mailbox Data Register %s 0x2CB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB12_D6 Mailbox Data Register %s 0x2CC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB12_D7 Mailbox Data Register %s 0x2CD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB12_DL Mailbox Data Length Register %s 0x2C4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB12_ID Mailbox ID Register %s 0x2C0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB12_TS Mailbox Time Stamp Register %s 0x2CE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB13_D0 Mailbox Data Register %s 0x2D6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB13_D1 Mailbox Data Register %s 0x2D7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB13_D2 Mailbox Data Register %s 0x2D8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB13_D3 Mailbox Data Register %s 0x2D9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB13_D4 Mailbox Data Register %s 0x2DA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB13_D5 Mailbox Data Register %s 0x2DB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB13_D6 Mailbox Data Register %s 0x2DC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB13_D7 Mailbox Data Register %s 0x2DD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB13_DL Mailbox Data Length Register %s 0x2D4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB13_ID Mailbox ID Register %s 0x2D0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB13_TS Mailbox Time Stamp Register %s 0x2DE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB14_D0 Mailbox Data Register %s 0x2E6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB14_D1 Mailbox Data Register %s 0x2E7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB14_D2 Mailbox Data Register %s 0x2E8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB14_D3 Mailbox Data Register %s 0x2E9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB14_D4 Mailbox Data Register %s 0x2EA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB14_D5 Mailbox Data Register %s 0x2EB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB14_D6 Mailbox Data Register %s 0x2EC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB14_D7 Mailbox Data Register %s 0x2ED 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB14_DL Mailbox Data Length Register %s 0x2E4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB14_ID Mailbox ID Register %s 0x2E0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB14_TS Mailbox Time Stamp Register %s 0x2EE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB15_D0 Mailbox Data Register %s 0x2F6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB15_D1 Mailbox Data Register %s 0x2F7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB15_D2 Mailbox Data Register %s 0x2F8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB15_D3 Mailbox Data Register %s 0x2F9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB15_D4 Mailbox Data Register %s 0x2FA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB15_D5 Mailbox Data Register %s 0x2FB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB15_D6 Mailbox Data Register %s 0x2FC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB15_D7 Mailbox Data Register %s 0x2FD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB15_DL Mailbox Data Length Register %s 0x2F4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB15_ID Mailbox ID Register %s 0x2F0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB15_TS Mailbox Time Stamp Register %s 0x2FE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB16_D0 Mailbox Data Register %s 0x306 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB16_D1 Mailbox Data Register %s 0x307 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB16_D2 Mailbox Data Register %s 0x308 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB16_D3 Mailbox Data Register %s 0x309 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB16_D4 Mailbox Data Register %s 0x30A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB16_D5 Mailbox Data Register %s 0x30B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB16_D6 Mailbox Data Register %s 0x30C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB16_D7 Mailbox Data Register %s 0x30D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB16_DL Mailbox Data Length Register %s 0x304 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB16_ID Mailbox ID Register %s 0x300 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB16_TS Mailbox Time Stamp Register %s 0x30E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB17_D0 Mailbox Data Register %s 0x316 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB17_D1 Mailbox Data Register %s 0x317 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB17_D2 Mailbox Data Register %s 0x318 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB17_D3 Mailbox Data Register %s 0x319 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB17_D4 Mailbox Data Register %s 0x31A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB17_D5 Mailbox Data Register %s 0x31B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB17_D6 Mailbox Data Register %s 0x31C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB17_D7 Mailbox Data Register %s 0x31D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB17_DL Mailbox Data Length Register %s 0x314 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB17_ID Mailbox ID Register %s 0x310 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB17_TS Mailbox Time Stamp Register %s 0x31E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB18_D0 Mailbox Data Register %s 0x326 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB18_D1 Mailbox Data Register %s 0x327 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB18_D2 Mailbox Data Register %s 0x328 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB18_D3 Mailbox Data Register %s 0x329 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB18_D4 Mailbox Data Register %s 0x32A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB18_D5 Mailbox Data Register %s 0x32B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB18_D6 Mailbox Data Register %s 0x32C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB18_D7 Mailbox Data Register %s 0x32D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB18_DL Mailbox Data Length Register %s 0x324 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB18_ID Mailbox ID Register %s 0x320 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB18_TS Mailbox Time Stamp Register %s 0x32E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB19_D0 Mailbox Data Register %s 0x336 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB19_D1 Mailbox Data Register %s 0x337 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB19_D2 Mailbox Data Register %s 0x338 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB19_D3 Mailbox Data Register %s 0x339 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB19_D4 Mailbox Data Register %s 0x33A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB19_D5 Mailbox Data Register %s 0x33B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB19_D6 Mailbox Data Register %s 0x33C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB19_D7 Mailbox Data Register %s 0x33D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB19_DL Mailbox Data Length Register %s 0x334 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB19_ID Mailbox ID Register %s 0x330 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB19_TS Mailbox Time Stamp Register %s 0x33E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB1_D0 Mailbox Data Register %s 0x216 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB1_D1 Mailbox Data Register %s 0x217 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB1_D2 Mailbox Data Register %s 0x218 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB1_D3 Mailbox Data Register %s 0x219 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB1_D4 Mailbox Data Register %s 0x21A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB1_D5 Mailbox Data Register %s 0x21B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB1_D6 Mailbox Data Register %s 0x21C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB1_D7 Mailbox Data Register %s 0x21D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB1_DL Mailbox Data Length Register %s 0x214 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB1_ID Mailbox ID Register %s 0x210 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB1_TS Mailbox Time Stamp Register %s 0x21E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB20_D0 Mailbox Data Register %s 0x346 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB20_D1 Mailbox Data Register %s 0x347 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB20_D2 Mailbox Data Register %s 0x348 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB20_D3 Mailbox Data Register %s 0x349 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB20_D4 Mailbox Data Register %s 0x34A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB20_D5 Mailbox Data Register %s 0x34B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB20_D6 Mailbox Data Register %s 0x34C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB20_D7 Mailbox Data Register %s 0x34D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB20_DL Mailbox Data Length Register %s 0x344 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB20_ID Mailbox ID Register %s 0x340 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB20_TS Mailbox Time Stamp Register %s 0x34E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB21_D0 Mailbox Data Register %s 0x356 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB21_D1 Mailbox Data Register %s 0x357 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB21_D2 Mailbox Data Register %s 0x358 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB21_D3 Mailbox Data Register %s 0x359 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB21_D4 Mailbox Data Register %s 0x35A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB21_D5 Mailbox Data Register %s 0x35B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB21_D6 Mailbox Data Register %s 0x35C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB21_D7 Mailbox Data Register %s 0x35D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB21_DL Mailbox Data Length Register %s 0x354 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB21_ID Mailbox ID Register %s 0x350 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB21_TS Mailbox Time Stamp Register %s 0x35E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB22_D0 Mailbox Data Register %s 0x366 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB22_D1 Mailbox Data Register %s 0x367 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB22_D2 Mailbox Data Register %s 0x368 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB22_D3 Mailbox Data Register %s 0x369 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB22_D4 Mailbox Data Register %s 0x36A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB22_D5 Mailbox Data Register %s 0x36B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB22_D6 Mailbox Data Register %s 0x36C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB22_D7 Mailbox Data Register %s 0x36D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB22_DL Mailbox Data Length Register %s 0x364 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB22_ID Mailbox ID Register %s 0x360 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB22_TS Mailbox Time Stamp Register %s 0x36E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB23_D0 Mailbox Data Register %s 0x376 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB23_D1 Mailbox Data Register %s 0x377 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB23_D2 Mailbox Data Register %s 0x378 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB23_D3 Mailbox Data Register %s 0x379 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB23_D4 Mailbox Data Register %s 0x37A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB23_D5 Mailbox Data Register %s 0x37B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB23_D6 Mailbox Data Register %s 0x37C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB23_D7 Mailbox Data Register %s 0x37D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB23_DL Mailbox Data Length Register %s 0x374 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB23_ID Mailbox ID Register %s 0x370 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB23_TS Mailbox Time Stamp Register %s 0x37E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB24_D0 Mailbox Data Register %s 0x386 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB24_D1 Mailbox Data Register %s 0x387 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB24_D2 Mailbox Data Register %s 0x388 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB24_D3 Mailbox Data Register %s 0x389 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB24_D4 Mailbox Data Register %s 0x38A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB24_D5 Mailbox Data Register %s 0x38B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB24_D6 Mailbox Data Register %s 0x38C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB24_D7 Mailbox Data Register %s 0x38D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB24_DL Mailbox Data Length Register %s 0x384 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB24_ID Mailbox ID Register %s 0x380 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB24_TS Mailbox Time Stamp Register %s 0x38E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB25_D0 Mailbox Data Register %s 0x396 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB25_D1 Mailbox Data Register %s 0x397 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB25_D2 Mailbox Data Register %s 0x398 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB25_D3 Mailbox Data Register %s 0x399 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB25_D4 Mailbox Data Register %s 0x39A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB25_D5 Mailbox Data Register %s 0x39B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB25_D6 Mailbox Data Register %s 0x39C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB25_D7 Mailbox Data Register %s 0x39D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB25_DL Mailbox Data Length Register %s 0x394 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB25_ID Mailbox ID Register %s 0x390 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB25_TS Mailbox Time Stamp Register %s 0x39E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB26_D0 Mailbox Data Register %s 0x3A6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB26_D1 Mailbox Data Register %s 0x3A7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB26_D2 Mailbox Data Register %s 0x3A8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB26_D3 Mailbox Data Register %s 0x3A9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB26_D4 Mailbox Data Register %s 0x3AA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB26_D5 Mailbox Data Register %s 0x3AB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB26_D6 Mailbox Data Register %s 0x3AC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB26_D7 Mailbox Data Register %s 0x3AD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB26_DL Mailbox Data Length Register %s 0x3A4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB26_ID Mailbox ID Register %s 0x3A0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB26_TS Mailbox Time Stamp Register %s 0x3AE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB27_D0 Mailbox Data Register %s 0x3B6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB27_D1 Mailbox Data Register %s 0x3B7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB27_D2 Mailbox Data Register %s 0x3B8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB27_D3 Mailbox Data Register %s 0x3B9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB27_D4 Mailbox Data Register %s 0x3BA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB27_D5 Mailbox Data Register %s 0x3BB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB27_D6 Mailbox Data Register %s 0x3BC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB27_D7 Mailbox Data Register %s 0x3BD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB27_DL Mailbox Data Length Register %s 0x3B4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB27_ID Mailbox ID Register %s 0x3B0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB27_TS Mailbox Time Stamp Register %s 0x3BE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB28_D0 Mailbox Data Register %s 0x3C6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB28_D1 Mailbox Data Register %s 0x3C7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB28_D2 Mailbox Data Register %s 0x3C8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB28_D3 Mailbox Data Register %s 0x3C9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB28_D4 Mailbox Data Register %s 0x3CA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB28_D5 Mailbox Data Register %s 0x3CB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB28_D6 Mailbox Data Register %s 0x3CC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB28_D7 Mailbox Data Register %s 0x3CD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB28_DL Mailbox Data Length Register %s 0x3C4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB28_ID Mailbox ID Register %s 0x3C0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB28_TS Mailbox Time Stamp Register %s 0x3CE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB29_D0 Mailbox Data Register %s 0x3D6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB29_D1 Mailbox Data Register %s 0x3D7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB29_D2 Mailbox Data Register %s 0x3D8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB29_D3 Mailbox Data Register %s 0x3D9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB29_D4 Mailbox Data Register %s 0x3DA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB29_D5 Mailbox Data Register %s 0x3DB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB29_D6 Mailbox Data Register %s 0x3DC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB29_D7 Mailbox Data Register %s 0x3DD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB29_DL Mailbox Data Length Register %s 0x3D4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB29_ID Mailbox ID Register %s 0x3D0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB29_TS Mailbox Time Stamp Register %s 0x3DE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB2_D0 Mailbox Data Register %s 0x226 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB2_D1 Mailbox Data Register %s 0x227 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB2_D2 Mailbox Data Register %s 0x228 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB2_D3 Mailbox Data Register %s 0x229 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB2_D4 Mailbox Data Register %s 0x22A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB2_D5 Mailbox Data Register %s 0x22B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB2_D6 Mailbox Data Register %s 0x22C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB2_D7 Mailbox Data Register %s 0x22D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB2_DL Mailbox Data Length Register %s 0x224 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB2_ID Mailbox ID Register %s 0x220 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB2_TS Mailbox Time Stamp Register %s 0x22E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB30_D0 Mailbox Data Register %s 0x3E6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB30_D1 Mailbox Data Register %s 0x3E7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB30_D2 Mailbox Data Register %s 0x3E8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB30_D3 Mailbox Data Register %s 0x3E9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB30_D4 Mailbox Data Register %s 0x3EA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB30_D5 Mailbox Data Register %s 0x3EB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB30_D6 Mailbox Data Register %s 0x3EC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB30_D7 Mailbox Data Register %s 0x3ED 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB30_DL Mailbox Data Length Register %s 0x3E4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB30_ID Mailbox ID Register %s 0x3E0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB30_TS Mailbox Time Stamp Register %s 0x3EE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB31_D0 Mailbox Data Register %s 0x3F6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB31_D1 Mailbox Data Register %s 0x3F7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB31_D2 Mailbox Data Register %s 0x3F8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB31_D3 Mailbox Data Register %s 0x3F9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB31_D4 Mailbox Data Register %s 0x3FA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB31_D5 Mailbox Data Register %s 0x3FB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB31_D6 Mailbox Data Register %s 0x3FC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB31_D7 Mailbox Data Register %s 0x3FD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB31_DL Mailbox Data Length Register %s 0x3F4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB31_ID Mailbox ID Register %s 0x3F0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB31_TS Mailbox Time Stamp Register %s 0x3FE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB3_D0 Mailbox Data Register %s 0x236 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB3_D1 Mailbox Data Register %s 0x237 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB3_D2 Mailbox Data Register %s 0x238 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB3_D3 Mailbox Data Register %s 0x239 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB3_D4 Mailbox Data Register %s 0x23A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB3_D5 Mailbox Data Register %s 0x23B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB3_D6 Mailbox Data Register %s 0x23C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB3_D7 Mailbox Data Register %s 0x23D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB3_DL Mailbox Data Length Register %s 0x234 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB3_ID Mailbox ID Register %s 0x230 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB3_TS Mailbox Time Stamp Register %s 0x23E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB4_D0 Mailbox Data Register %s 0x246 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB4_D1 Mailbox Data Register %s 0x247 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB4_D2 Mailbox Data Register %s 0x248 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB4_D3 Mailbox Data Register %s 0x249 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB4_D4 Mailbox Data Register %s 0x24A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB4_D5 Mailbox Data Register %s 0x24B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB4_D6 Mailbox Data Register %s 0x24C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB4_D7 Mailbox Data Register %s 0x24D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB4_DL Mailbox Data Length Register %s 0x244 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB4_ID Mailbox ID Register %s 0x240 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB4_TS Mailbox Time Stamp Register %s 0x24E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB5_D0 Mailbox Data Register %s 0x256 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB5_D1 Mailbox Data Register %s 0x257 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB5_D2 Mailbox Data Register %s 0x258 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB5_D3 Mailbox Data Register %s 0x259 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB5_D4 Mailbox Data Register %s 0x25A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB5_D5 Mailbox Data Register %s 0x25B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB5_D6 Mailbox Data Register %s 0x25C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB5_D7 Mailbox Data Register %s 0x25D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB5_DL Mailbox Data Length Register %s 0x254 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB5_ID Mailbox ID Register %s 0x250 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB5_TS Mailbox Time Stamp Register %s 0x25E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB6_D0 Mailbox Data Register %s 0x266 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB6_D1 Mailbox Data Register %s 0x267 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB6_D2 Mailbox Data Register %s 0x268 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB6_D3 Mailbox Data Register %s 0x269 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB6_D4 Mailbox Data Register %s 0x26A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB6_D5 Mailbox Data Register %s 0x26B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB6_D6 Mailbox Data Register %s 0x26C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB6_D7 Mailbox Data Register %s 0x26D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB6_DL Mailbox Data Length Register %s 0x264 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB6_ID Mailbox ID Register %s 0x260 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB6_TS Mailbox Time Stamp Register %s 0x26E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB7_D0 Mailbox Data Register %s 0x276 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB7_D1 Mailbox Data Register %s 0x277 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB7_D2 Mailbox Data Register %s 0x278 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB7_D3 Mailbox Data Register %s 0x279 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB7_D4 Mailbox Data Register %s 0x27A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB7_D5 Mailbox Data Register %s 0x27B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB7_D6 Mailbox Data Register %s 0x27C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB7_D7 Mailbox Data Register %s 0x27D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB7_DL Mailbox Data Length Register %s 0x274 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB7_ID Mailbox ID Register %s 0x270 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB7_TS Mailbox Time Stamp Register %s 0x27E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB8_D0 Mailbox Data Register %s 0x286 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB8_D1 Mailbox Data Register %s 0x287 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB8_D2 Mailbox Data Register %s 0x288 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB8_D3 Mailbox Data Register %s 0x289 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB8_D4 Mailbox Data Register %s 0x28A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB8_D5 Mailbox Data Register %s 0x28B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB8_D6 Mailbox Data Register %s 0x28C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB8_D7 Mailbox Data Register %s 0x28D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB8_DL Mailbox Data Length Register %s 0x284 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB8_ID Mailbox ID Register %s 0x280 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB8_TS Mailbox Time Stamp Register %s 0x28E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB9_D0 Mailbox Data Register %s 0x296 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB9_D1 Mailbox Data Register %s 0x297 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB9_D2 Mailbox Data Register %s 0x298 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB9_D3 Mailbox Data Register %s 0x299 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB9_D4 Mailbox Data Register %s 0x29A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB9_D5 Mailbox Data Register %s 0x29B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB9_D6 Mailbox Data Register %s 0x29C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB9_D7 Mailbox Data Register %s 0x29D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB9_DL Mailbox Data Length Register %s 0x294 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB9_ID Mailbox ID Register %s 0x290 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB9_TS Mailbox Time Stamp Register %s 0x29E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MCTL_RX0 Message Control Register for Receive 0x820 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX1 Message Control Register for Receive 0x821 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX10 Message Control Register for Receive 0x82A 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX11 Message Control Register for Receive 0x82B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX12 Message Control Register for Receive 0x82C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX13 Message Control Register for Receive 0x82D 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX14 Message Control Register for Receive 0x82E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX15 Message Control Register for Receive 0x82F 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX16 Message Control Register for Receive 0x830 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX17 Message Control Register for Receive 0x831 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX18 Message Control Register for Receive 0x832 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX19 Message Control Register for Receive 0x833 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX2 Message Control Register for Receive 0x822 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX20 Message Control Register for Receive 0x834 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX21 Message Control Register for Receive 0x835 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX22 Message Control Register for Receive 0x836 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX23 Message Control Register for Receive 0x837 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX24 Message Control Register for Receive 0x838 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX25 Message Control Register for Receive 0x839 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX26 Message Control Register for Receive 0x83A 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX27 Message Control Register for Receive 0x83B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX28 Message Control Register for Receive 0x83C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX29 Message Control Register for Receive 0x83D 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX3 Message Control Register for Receive 0x823 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX30 Message Control Register for Receive 0x83E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX31 Message Control Register for Receive 0x83F 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX4 Message Control Register for Receive 0x824 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX5 Message Control Register for Receive 0x825 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX6 Message Control Register for Receive 0x826 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX7 Message Control Register for Receive 0x827 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX8 Message Control Register for Receive 0x828 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX9 Message Control Register for Receive 0x829 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX0 Message Control Register for Transmit MCTL_RX[%s] 0x820 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX1 Message Control Register for Transmit MCTL_RX[%s] 0x821 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX10 Message Control Register for Transmit MCTL_RX[%s] 0x82A 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX11 Message Control Register for Transmit MCTL_RX[%s] 0x82B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX12 Message Control Register for Transmit MCTL_RX[%s] 0x82C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX13 Message Control Register for Transmit MCTL_RX[%s] 0x82D 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX14 Message Control Register for Transmit MCTL_RX[%s] 0x82E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX15 Message Control Register for Transmit MCTL_RX[%s] 0x82F 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX16 Message Control Register for Transmit MCTL_RX[%s] 0x830 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX17 Message Control Register for Transmit MCTL_RX[%s] 0x831 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX18 Message Control Register for Transmit MCTL_RX[%s] 0x832 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX19 Message Control Register for Transmit MCTL_RX[%s] 0x833 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX2 Message Control Register for Transmit MCTL_RX[%s] 0x822 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX20 Message Control Register for Transmit MCTL_RX[%s] 0x834 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX21 Message Control Register for Transmit MCTL_RX[%s] 0x835 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX22 Message Control Register for Transmit MCTL_RX[%s] 0x836 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX23 Message Control Register for Transmit MCTL_RX[%s] 0x837 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX24 Message Control Register for Transmit MCTL_RX[%s] 0x838 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX25 Message Control Register for Transmit MCTL_RX[%s] 0x839 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX26 Message Control Register for Transmit MCTL_RX[%s] 0x83A 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX27 Message Control Register for Transmit MCTL_RX[%s] 0x83B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX28 Message Control Register for Transmit MCTL_RX[%s] 0x83C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX29 Message Control Register for Transmit MCTL_RX[%s] 0x83D 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX3 Message Control Register for Transmit MCTL_RX[%s] 0x823 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX30 Message Control Register for Transmit MCTL_RX[%s] 0x83E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX31 Message Control Register for Transmit MCTL_RX[%s] 0x83F 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX4 Message Control Register for Transmit MCTL_RX[%s] 0x824 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX5 Message Control Register for Transmit MCTL_RX[%s] 0x825 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX6 Message Control Register for Transmit MCTL_RX[%s] 0x826 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX7 Message Control Register for Transmit MCTL_RX[%s] 0x827 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX8 Message Control Register for Transmit MCTL_RX[%s] 0x828 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX9 Message Control Register for Transmit MCTL_RX[%s] 0x829 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MIER Mailbox Interrupt Enable Register 0x42C 32 read-write n 0x0 0x0 MB00 Interrupt Enable 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB01 Interrupt Enable 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB02 Interrupt Enable 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB03 Interrupt Enable 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB04 Interrupt Enable 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB05 Interrupt Enable 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB06 Interrupt Enable 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB07 Interrupt Enable 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB08 Interrupt Enable 8 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB09 Interrupt Enable 9 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB10 Interrupt Enable 10 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB11 Interrupt Enable 11 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB12 Interrupt Enable 12 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB13 Interrupt Enable 13 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB14 Interrupt Enable 14 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB15 Interrupt Enable 15 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB16 Interrupt Enable 16 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB17 Interrupt Enable 17 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB18 Interrupt Enable 18 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB19 Interrupt Enable 19 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB20 Interrupt Enable 20 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB21 Interrupt Enable 21 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB22 Interrupt Enable 22 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB23 Interrupt Enable 23 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB24 Interrupt Enable 24 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB25 Interrupt Enable 25 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB26 Interrupt Enable 26 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB27 Interrupt Enable 27 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB28 Interrupt Enable 28 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB29 Interrupt Enable 29 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB30 Interrupt Enable 30 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB31 Interrupt Enable 31 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MIER_FIFO Mailbox Interrupt Enable Register for FIFO Mailbox Mode MIER 0x42C 32 read-write n 0x0 0x0 MB00 Interrupt Enable 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB01 Interrupt Enable 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB02 Interrupt Enable 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB03 Interrupt Enable 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB04 Interrupt Enable 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB05 Interrupt Enable 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB06 Interrupt Enable 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB07 Interrupt Enable 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB08 Interrupt Enable 8 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB09 Interrupt Enable 9 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB10 Interrupt Enable 10 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB11 Interrupt Enable 11 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB12 Interrupt Enable 12 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB13 Interrupt Enable 13 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB14 Interrupt Enable 14 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB15 Interrupt Enable 15 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB16 Interrupt Enable 16 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB17 Interrupt Enable 17 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB18 Interrupt Enable 18 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB19 Interrupt Enable 19 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB20 Interrupt Enable 20 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB21 Interrupt Enable 21 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB22 Interrupt Enable 22 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB23 Interrupt Enable 23 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB24 Transmit FIFO Interrupt Enable 24 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB25 Transmit FIFO Interrupt Generation Timing Control 25 read-write 0 Generate every time transmission completes #0 1 Generate when the transmit FIFO empties on transmission completion #1 MB28 Receive FIFO Interrupt Enable 28 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB29 Receive FIFO Interrupt Generation Timing Control 29 read-write 0 Generate every time reception completes #0 1 Generate when the receive FIFO becomes a buffer warning on reception completion #1 MKIVLR Mask Invalid Register 0x428 32 read-write n 0x0 0x0 MB00 Mask Invalid 0 read-write 0 Mask valid #0 1 Mask invalid #1 MB01 Mask Invalid 1 read-write 0 Mask valid #0 1 Mask invalid #1 MB02 Mask Invalid 2 read-write 0 Mask valid #0 1 Mask invalid #1 MB03 Mask Invalid 3 read-write 0 Mask valid #0 1 Mask invalid #1 MB04 Mask Invalid 4 read-write 0 Mask valid #0 1 Mask invalid #1 MB05 Mask Invalid 5 read-write 0 Mask valid #0 1 Mask invalid #1 MB06 Mask Invalid 6 read-write 0 Mask valid #0 1 Mask invalid #1 MB07 Mask Invalid 7 read-write 0 Mask valid #0 1 Mask invalid #1 MB08 Mask Invalid 8 read-write 0 Mask valid #0 1 Mask invalid #1 MB09 Mask Invalid 9 read-write 0 Mask valid #0 1 Mask invalid #1 MB10 Mask Invalid 10 read-write 0 Mask valid #0 1 Mask invalid #1 MB11 Mask Invalid 11 read-write 0 Mask valid #0 1 Mask invalid #1 MB12 Mask Invalid 12 read-write 0 Mask valid #0 1 Mask invalid #1 MB13 Mask Invalid 13 read-write 0 Mask valid #0 1 Mask invalid #1 MB14 Mask Invalid 14 read-write 0 Mask valid #0 1 Mask invalid #1 MB15 Mask Invalid 15 read-write 0 Mask valid #0 1 Mask invalid #1 MB16 Mask Invalid 16 read-write 0 Mask valid #0 1 Mask invalid #1 MB17 Mask Invalid 17 read-write 0 Mask valid #0 1 Mask invalid #1 MB18 Mask Invalid 18 read-write 0 Mask valid #0 1 Mask invalid #1 MB19 Mask Invalid 19 read-write 0 Mask valid #0 1 Mask invalid #1 MB20 Mask Invalid 20 read-write 0 Mask valid #0 1 Mask invalid #1 MB21 Mask Invalid 21 read-write 0 Mask valid #0 1 Mask invalid #1 MB22 Mask Invalid 22 read-write 0 Mask valid #0 1 Mask invalid #1 MB23 Mask Invalid 23 read-write 0 Mask valid #0 1 Mask invalid #1 MB24 Mask Invalid 24 read-write 0 Mask valid #0 1 Mask invalid #1 MB25 Mask Invalid 25 read-write 0 Mask valid #0 1 Mask invalid #1 MB26 Mask Invalid 26 read-write 0 Mask valid #0 1 Mask invalid #1 MB27 Mask Invalid 27 read-write 0 Mask valid #0 1 Mask invalid #1 MB28 Mask Invalid 28 read-write 0 Mask valid #0 1 Mask invalid #1 MB29 Mask Invalid 29 read-write 0 Mask valid #0 1 Mask invalid #1 MB30 Mask Invalid 30 read-write 0 Mask valid #0 1 Mask invalid #1 MB31 Mask Invalid 31 read-write 0 Mask valid #0 1 Mask invalid #1 MKR0 Mask Register %s 0x400 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR1 Mask Register %s 0x404 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR2 Mask Register %s 0x408 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR3 Mask Register %s 0x40C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR4 Mask Register %s 0x410 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR5 Mask Register %s 0x414 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR6 Mask Register %s 0x418 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR7 Mask Register %s 0x41C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MSMR Mailbox Search Mode Register 0x853 8 read-write n 0x0 0x0 MBSM Mailbox Search Mode Select 0 1 read-write 00 Receive mailbox search mode #00 01 Transmit mailbox search mode #01 10 Message lost search mode #10 11 Channel search mode #11 MSSR Mailbox Search Status Register 0x852 8 read-only n 0x0 0x0 MBNST Search Result Mailbox Number Status 0 4 read-only SEST Search Result Status 7 read-only 0 Search result found #0 1 No search result #1 RECR Receive Error Count Register 0x84E 8 read-only n 0x0 0x0 RFCR Receive FIFO Control Register 0x848 8 read-write n 0x0 0x0 RFE Receive FIFO Enable 0 read-write 0 Disable receive FIFO #0 1 Enable receive FIFO #1 RFEST Receive FIFO Empty Status Flag 7 read-only 0 Unread message in receive FIFO #0 1 No unread message in receive FIFO #1 RFFST Receive FIFO Full Status Flag 5 read-only 0 Receive FIFO not full #0 1 Receive FIFO full (4 unread messages) #1 RFMLF Receive FIFO Message Lost Flag 4 read-write 0 Receive FIFO message not lost #0 1 Receive FIFO message lost #1 RFUST Receive FIFO Unread Message Number Status 1 2 read-only 000 No unread message #000 001 1 unread message #001 010 2 unread messages #010 011 3 unread messages #011 100 4 unread messages #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RFWST Receive FIFO Buffer Warning Status Flag 6 read-only 0 Receive FIFO is not buffer warning #0 1 Receive FIFO is buffer warning (3 unread messages) #1 RFPCR Receive FIFO Pointer Control Register 0x849 8 write-only n 0x0 0x0 STR Status Register 0x842 16 read-only n 0x0 0x0 BOST Bus-Off Status Flag 12 read-only 0 Not in bus-off state #0 1 In bus-off state #1 EPST Error-Passive Status Flag 11 read-only 0 Not in error-passive state #0 1 In error-passive state #1 EST Error Status Flag 7 read-only 0 No error occurred #0 1 Error occurred #1 FMLST FIFO Mailbox Message Lost Status Flag 5 read-only 0 RFMLF = 0 #0 1 RFMLF = 1 #1 HLTST CAN Halt Status Flag 9 read-only 0 Not in CAN halt mode #0 1 In CAN halt mode #1 NDST NEWDATA Status Flag 0 read-only 0 No mailbox with NEWDATA = 1 #0 1 One or more mailboxes with NEWDATA = 1 #1 NMLST Normal Mailbox Message Lost Status Flag 4 read-only 0 No mailbox with MSGLOST = 1 #0 1 One or more mailboxes with MSGLOST = 1 #1 RECST Receive Status Flag 14 read-only 0 Bus idle or transmission in progress #0 1 Reception in progress #1 RFST Receive FIFO Status Flag 2 read-only 0 Receive FIFO empty #0 1 Message in receive FIFO #1 RSTST CAN Reset Status Flag 8 read-only 0 Not in CAN reset mode #0 1 In CAN reset mode #1 SDST SENTDATA Status Flag 1 read-only 0 No mailbox with SENTDATA = 1 #0 1 One or more mailboxes with SENTDATA = 1 #1 SLPST CAN Sleep Status Flag 10 read-only 0 Not in CAN sleep mode #0 1 In CAN sleep mode #1 TABST Transmission Abort Status Flag 6 read-only 0 No mailbox with TRMABT = 1 #0 1 One or more mailboxes with TRMABT = 1 #1 TFST Transmit FIFO Status Flag 3 read-only 0 Transmit FIFO is full #0 1 Transmit FIFO is not full #1 TRMST Transmit Status Flag 13 read-only 0 Bus idle or reception in progress #0 1 Transmission in progress or module in bus-off state #1 TCR Test Control Register 0x858 8 read-write n 0x0 0x0 TSTE CAN Test Mode Enable 0 read-write 0 Disable CAN test mode #0 1 Enable CAN test mode #1 TSTM CAN Test Mode Select 1 1 read-write 00 Not CAN test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (external loopback) #10 11 Self-test mode 1 (internal loopback) #11 TECR Transmit Error Count Register 0x84F 8 read-only n 0x0 0x0 TFCR Transmit FIFO Control Register 0x84A 8 read-write n 0x0 0x0 TFE Transmit FIFO Enable 0 read-write 0 Disable transmit FIFO #0 1 Enable transmit FIFO #1 TFEST Transmit FIFO Empty Status 7 read-only 0 Unsent message in transmit FIFO #0 1 No unsent message in transmit FIFO #1 TFFST Transmit FIFO Full Status 6 read-only 0 Transmit FIFO not full #0 1 Transmit FIFO full (4 unsent messages) #1 TFUST Transmit FIFO Unsent Message Number Status 1 2 read-only 000 0 unsent messages #000 001 1 unsent message #001 010 2 unsent messages #010 011 3 unread messages #011 100 4 unread messages #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TFPCR Transmit FIFO Pointer Control Register 0x84B 8 write-only n 0x0 0x0 TSR Time Stamp Register 0x854 16 read-only n 0x0 0x0 CAN1 CAN1 Module CAN0 0x0 0x200 0x230 registers n 0x820 0x39 registers n AFSR Acceptance Filter Support Register 0x856 16 read-write n 0x0 0x0 BCR Bit Configuration Register 0x844 32 read-write n 0x0 0x0 BRP Baud Rate Prescaler Select 16 9 read-write CCLKS CAN Clock Source Selection 0 read-write 0 PCLKL (generated by the PLL clock) #0 1 CANMCLK (generated by the main clock oscillator) #1 SJW Synchronization Jump Width Control 12 1 read-write 00 1 Tq #00 01 2 Tq #01 10 3 Tq #10 11 4 Tq #11 TSEG1 Time Segment 1 Control 28 3 read-write Others Setting prohibited 0x3 4 Tq 0x3 0x4 5 Tq 0x4 0x5 6 Tq 0x5 0x6 7 Tq 0x6 0x7 8 Tq 0x7 0x8 9 Tq 0x8 0x9 10 Tq 0x9 0xA 11 Tq 0xa 0xB 12 Tq 0xb 0xC 13 Tq 0xc 0xD 14 Tq 0xd 0xE 15 Tq 0xe 0xF 16 Tq 0xf TSEG2 Time Segment 2 Control 8 2 read-write 000 Setting prohibited #000 001 2 Tq #001 010 3 Tq #010 011 4 Tq #011 100 5 Tq #100 101 6 Tq #101 110 7 Tq #110 111 8 Tq #111 CSSR Channel Search Support Register 0x851 8 read-write n 0x0 0x0 CTLR Control Register 0x840 16 read-write n 0x0 0x0 BOM Bus-Off Recovery Mode 11 1 read-write 00 Normal mode (ISO11898-1-compliant) #00 01 Enter CAN halt mode automatically on entering bus-off state #01 10 Enter CAN halt mode automatically at the end of bus-off state #10 11 Enter CAN halt mode during bus-off recovery period through a software request #11 CANM CAN Operating Mode Select 8 1 read-write 00 CAN operation mode #00 01 CAN reset mode #01 10 CAN halt mode #10 11 CAN reset mode (forced transition) #11 IDFM ID Format Mode Select 1 1 read-write 00 Standard ID mode All mailboxes, including FIFO mailboxes, handle only standard IDs #00 01 Extended ID mode All mailboxes, including FIFO mailboxes, handle only extended IDs #01 10 Mixed ID mode All mailboxes, including FIFO mailboxes, handle both standard and extended IDs. In normal mailbox mode, use the associated IDE bit to differentiate standard and extended IDs. In FIFO mailbox mode, the associated IDE bits are used for mailboxes 0 to 23, the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit associated with mailbox 24 is used for the transmit FIFO. #10 11 Setting prohibited #11 MBM CAN Mailbox Mode Select 0 read-write 0 Normal mailbox mode #0 1 FIFO mailbox mode #1 MLM Message Lost Mode Select 3 read-write 0 Overwrite mode #0 1 Overrun mode #1 RBOC Forcible Return from Bus-Off 13 read-write 0 No return occurred #0 1 Forced return from bus-off state #1 SLPM CAN Sleep Mode 10 read-write 0 All other modes #0 1 CAN sleep mode #1 TPM Transmission Priority Mode Select 4 read-write 0 ID priority transmit mode #0 1 Mailbox number priority transmit mode #1 TSPS Time Stamp Prescaler Select 6 1 read-write 00 Every 1-bit time #00 01 Every 2-bit time #01 10 Every 4-bit time #10 11 Every 8-bit time #11 TSRC Time Stamp Counter Reset Command 5 read-write 0 Do not reset time stamp counter #0 1 Reset time stamp counter #1 ECSR Error Code Store Register 0x850 8 read-write n 0x0 0x0 ADEF ACK Delimiter Error Flag 6 read-write 0 No ACK delimiter error detected #0 1 ACK delimiter error detected #1 AEF ACK Error Flag 2 read-write 0 No ACK error detected #0 1 ACK error detected #1 BE0F Bit Error (dominant) Flag 5 read-write 0 No bit error (dominant) detected #0 1 Bit error (dominant) detected #1 BE1F Bit Error (recessive) Flag 4 read-write 0 No bit error (recessive) detected #0 1 Bit error (recessive) detected #1 CEF CRC Error Flag 3 read-write 0 No CRC error detected #0 1 CRC error detected #1 EDPM Error Display Mode Select 7 read-write 0 Output first detected error code #0 1 Output accumulated error code #1 FEF Form Error Flag 1 read-write 0 No form error detected #0 1 Form error detected #1 SEF Stuff Error Flag 0 read-write 0 No stuff error detected #0 1 Stuff error detected #1 EIER Error Interrupt Enable Register 0x84C 8 read-write n 0x0 0x0 BEIE Bus Error Interrupt Enable 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BLIE Bus Lock Interrupt Enable 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BOEIE Bus-Off Entry Interrupt Enable 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 BORIE Bus-Off Recovery Interrupt Enable 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EPIE Error-Passive Interrupt Enable 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EWIE Error-Warning Interrupt Enable 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 OLIE Overload Frame Transmit Interrupt Enable 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 ORIE Overrun Interrupt Enable 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 EIFR Error Interrupt Factor Judge Register 0x84D 8 read-write n 0x0 0x0 BEIF Bus Error Detect Flag 0 read-write 0 No bus error detected #0 1 Bus error detected #1 BLIF Bus Lock Detect Flag 7 read-write 0 No bus lock detected #0 1 Bus lock detected #1 BOEIF Bus-Off Entry Detect Flag 3 read-write 0 No bus-off entry detected #0 1 Bus-off entry detected #1 BORIF Bus-Off Recovery Detect Flag 4 read-write 0 No bus-off recovery detected #0 1 Bus-off recovery detected #1 EPIF Error-Passive Detect Flag 2 read-write 0 No error-passive detected #0 1 Error-passive detected #1 EWIF Error-Warning Detect Flag 1 read-write 0 No error-warning detected #0 1 Error-warning detected #1 OLIF Overload Frame Transmission Detect Flag 6 read-write 0 No overload frame transmission detected #0 1 Overload frame transmission detected #1 ORIF Receive Overrun Detect Flag 5 read-write 0 No receive overrun detected #0 1 Receive overrun detected #1 FIDCR0 FIFO Received ID Compare Register %s 0x420 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write FIDCR1 FIFO Received ID Compare Register %s 0x424 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB0_D0 Mailbox Data Register %s 0x206 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB0_D1 Mailbox Data Register %s 0x207 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB0_D2 Mailbox Data Register %s 0x208 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB0_D3 Mailbox Data Register %s 0x209 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB0_D4 Mailbox Data Register %s 0x20A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB0_D5 Mailbox Data Register %s 0x20B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB0_D6 Mailbox Data Register %s 0x20C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB0_D7 Mailbox Data Register %s 0x20D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB0_DL Mailbox Data Length Register %s 0x204 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB0_ID Mailbox ID Register %s 0x200 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB0_TS Mailbox Time Stamp Register %s 0x20E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB10_D0 Mailbox Data Register %s 0x2A6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB10_D1 Mailbox Data Register %s 0x2A7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB10_D2 Mailbox Data Register %s 0x2A8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB10_D3 Mailbox Data Register %s 0x2A9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB10_D4 Mailbox Data Register %s 0x2AA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB10_D5 Mailbox Data Register %s 0x2AB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB10_D6 Mailbox Data Register %s 0x2AC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB10_D7 Mailbox Data Register %s 0x2AD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB10_DL Mailbox Data Length Register %s 0x2A4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB10_ID Mailbox ID Register %s 0x2A0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB10_TS Mailbox Time Stamp Register %s 0x2AE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB11_D0 Mailbox Data Register %s 0x2B6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB11_D1 Mailbox Data Register %s 0x2B7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB11_D2 Mailbox Data Register %s 0x2B8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB11_D3 Mailbox Data Register %s 0x2B9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB11_D4 Mailbox Data Register %s 0x2BA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB11_D5 Mailbox Data Register %s 0x2BB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB11_D6 Mailbox Data Register %s 0x2BC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB11_D7 Mailbox Data Register %s 0x2BD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB11_DL Mailbox Data Length Register %s 0x2B4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB11_ID Mailbox ID Register %s 0x2B0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB11_TS Mailbox Time Stamp Register %s 0x2BE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB12_D0 Mailbox Data Register %s 0x2C6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB12_D1 Mailbox Data Register %s 0x2C7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB12_D2 Mailbox Data Register %s 0x2C8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB12_D3 Mailbox Data Register %s 0x2C9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB12_D4 Mailbox Data Register %s 0x2CA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB12_D5 Mailbox Data Register %s 0x2CB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB12_D6 Mailbox Data Register %s 0x2CC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB12_D7 Mailbox Data Register %s 0x2CD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB12_DL Mailbox Data Length Register %s 0x2C4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB12_ID Mailbox ID Register %s 0x2C0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB12_TS Mailbox Time Stamp Register %s 0x2CE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB13_D0 Mailbox Data Register %s 0x2D6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB13_D1 Mailbox Data Register %s 0x2D7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB13_D2 Mailbox Data Register %s 0x2D8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB13_D3 Mailbox Data Register %s 0x2D9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB13_D4 Mailbox Data Register %s 0x2DA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB13_D5 Mailbox Data Register %s 0x2DB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB13_D6 Mailbox Data Register %s 0x2DC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB13_D7 Mailbox Data Register %s 0x2DD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB13_DL Mailbox Data Length Register %s 0x2D4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB13_ID Mailbox ID Register %s 0x2D0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB13_TS Mailbox Time Stamp Register %s 0x2DE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB14_D0 Mailbox Data Register %s 0x2E6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB14_D1 Mailbox Data Register %s 0x2E7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB14_D2 Mailbox Data Register %s 0x2E8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB14_D3 Mailbox Data Register %s 0x2E9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB14_D4 Mailbox Data Register %s 0x2EA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB14_D5 Mailbox Data Register %s 0x2EB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB14_D6 Mailbox Data Register %s 0x2EC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB14_D7 Mailbox Data Register %s 0x2ED 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB14_DL Mailbox Data Length Register %s 0x2E4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB14_ID Mailbox ID Register %s 0x2E0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB14_TS Mailbox Time Stamp Register %s 0x2EE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB15_D0 Mailbox Data Register %s 0x2F6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB15_D1 Mailbox Data Register %s 0x2F7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB15_D2 Mailbox Data Register %s 0x2F8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB15_D3 Mailbox Data Register %s 0x2F9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB15_D4 Mailbox Data Register %s 0x2FA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB15_D5 Mailbox Data Register %s 0x2FB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB15_D6 Mailbox Data Register %s 0x2FC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB15_D7 Mailbox Data Register %s 0x2FD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB15_DL Mailbox Data Length Register %s 0x2F4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB15_ID Mailbox ID Register %s 0x2F0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB15_TS Mailbox Time Stamp Register %s 0x2FE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB16_D0 Mailbox Data Register %s 0x306 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB16_D1 Mailbox Data Register %s 0x307 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB16_D2 Mailbox Data Register %s 0x308 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB16_D3 Mailbox Data Register %s 0x309 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB16_D4 Mailbox Data Register %s 0x30A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB16_D5 Mailbox Data Register %s 0x30B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB16_D6 Mailbox Data Register %s 0x30C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB16_D7 Mailbox Data Register %s 0x30D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB16_DL Mailbox Data Length Register %s 0x304 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB16_ID Mailbox ID Register %s 0x300 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB16_TS Mailbox Time Stamp Register %s 0x30E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB17_D0 Mailbox Data Register %s 0x316 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB17_D1 Mailbox Data Register %s 0x317 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB17_D2 Mailbox Data Register %s 0x318 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB17_D3 Mailbox Data Register %s 0x319 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB17_D4 Mailbox Data Register %s 0x31A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB17_D5 Mailbox Data Register %s 0x31B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB17_D6 Mailbox Data Register %s 0x31C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB17_D7 Mailbox Data Register %s 0x31D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB17_DL Mailbox Data Length Register %s 0x314 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB17_ID Mailbox ID Register %s 0x310 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB17_TS Mailbox Time Stamp Register %s 0x31E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB18_D0 Mailbox Data Register %s 0x326 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB18_D1 Mailbox Data Register %s 0x327 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB18_D2 Mailbox Data Register %s 0x328 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB18_D3 Mailbox Data Register %s 0x329 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB18_D4 Mailbox Data Register %s 0x32A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB18_D5 Mailbox Data Register %s 0x32B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB18_D6 Mailbox Data Register %s 0x32C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB18_D7 Mailbox Data Register %s 0x32D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB18_DL Mailbox Data Length Register %s 0x324 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB18_ID Mailbox ID Register %s 0x320 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB18_TS Mailbox Time Stamp Register %s 0x32E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB19_D0 Mailbox Data Register %s 0x336 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB19_D1 Mailbox Data Register %s 0x337 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB19_D2 Mailbox Data Register %s 0x338 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB19_D3 Mailbox Data Register %s 0x339 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB19_D4 Mailbox Data Register %s 0x33A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB19_D5 Mailbox Data Register %s 0x33B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB19_D6 Mailbox Data Register %s 0x33C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB19_D7 Mailbox Data Register %s 0x33D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB19_DL Mailbox Data Length Register %s 0x334 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB19_ID Mailbox ID Register %s 0x330 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB19_TS Mailbox Time Stamp Register %s 0x33E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB1_D0 Mailbox Data Register %s 0x216 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB1_D1 Mailbox Data Register %s 0x217 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB1_D2 Mailbox Data Register %s 0x218 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB1_D3 Mailbox Data Register %s 0x219 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB1_D4 Mailbox Data Register %s 0x21A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB1_D5 Mailbox Data Register %s 0x21B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB1_D6 Mailbox Data Register %s 0x21C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB1_D7 Mailbox Data Register %s 0x21D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB1_DL Mailbox Data Length Register %s 0x214 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB1_ID Mailbox ID Register %s 0x210 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB1_TS Mailbox Time Stamp Register %s 0x21E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB20_D0 Mailbox Data Register %s 0x346 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB20_D1 Mailbox Data Register %s 0x347 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB20_D2 Mailbox Data Register %s 0x348 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB20_D3 Mailbox Data Register %s 0x349 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB20_D4 Mailbox Data Register %s 0x34A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB20_D5 Mailbox Data Register %s 0x34B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB20_D6 Mailbox Data Register %s 0x34C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB20_D7 Mailbox Data Register %s 0x34D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB20_DL Mailbox Data Length Register %s 0x344 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB20_ID Mailbox ID Register %s 0x340 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB20_TS Mailbox Time Stamp Register %s 0x34E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB21_D0 Mailbox Data Register %s 0x356 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB21_D1 Mailbox Data Register %s 0x357 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB21_D2 Mailbox Data Register %s 0x358 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB21_D3 Mailbox Data Register %s 0x359 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB21_D4 Mailbox Data Register %s 0x35A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB21_D5 Mailbox Data Register %s 0x35B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB21_D6 Mailbox Data Register %s 0x35C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB21_D7 Mailbox Data Register %s 0x35D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB21_DL Mailbox Data Length Register %s 0x354 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB21_ID Mailbox ID Register %s 0x350 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB21_TS Mailbox Time Stamp Register %s 0x35E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB22_D0 Mailbox Data Register %s 0x366 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB22_D1 Mailbox Data Register %s 0x367 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB22_D2 Mailbox Data Register %s 0x368 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB22_D3 Mailbox Data Register %s 0x369 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB22_D4 Mailbox Data Register %s 0x36A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB22_D5 Mailbox Data Register %s 0x36B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB22_D6 Mailbox Data Register %s 0x36C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB22_D7 Mailbox Data Register %s 0x36D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB22_DL Mailbox Data Length Register %s 0x364 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB22_ID Mailbox ID Register %s 0x360 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB22_TS Mailbox Time Stamp Register %s 0x36E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB23_D0 Mailbox Data Register %s 0x376 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB23_D1 Mailbox Data Register %s 0x377 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB23_D2 Mailbox Data Register %s 0x378 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB23_D3 Mailbox Data Register %s 0x379 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB23_D4 Mailbox Data Register %s 0x37A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB23_D5 Mailbox Data Register %s 0x37B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB23_D6 Mailbox Data Register %s 0x37C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB23_D7 Mailbox Data Register %s 0x37D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB23_DL Mailbox Data Length Register %s 0x374 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB23_ID Mailbox ID Register %s 0x370 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB23_TS Mailbox Time Stamp Register %s 0x37E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB24_D0 Mailbox Data Register %s 0x386 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB24_D1 Mailbox Data Register %s 0x387 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB24_D2 Mailbox Data Register %s 0x388 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB24_D3 Mailbox Data Register %s 0x389 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB24_D4 Mailbox Data Register %s 0x38A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB24_D5 Mailbox Data Register %s 0x38B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB24_D6 Mailbox Data Register %s 0x38C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB24_D7 Mailbox Data Register %s 0x38D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB24_DL Mailbox Data Length Register %s 0x384 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB24_ID Mailbox ID Register %s 0x380 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB24_TS Mailbox Time Stamp Register %s 0x38E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB25_D0 Mailbox Data Register %s 0x396 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB25_D1 Mailbox Data Register %s 0x397 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB25_D2 Mailbox Data Register %s 0x398 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB25_D3 Mailbox Data Register %s 0x399 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB25_D4 Mailbox Data Register %s 0x39A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB25_D5 Mailbox Data Register %s 0x39B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB25_D6 Mailbox Data Register %s 0x39C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB25_D7 Mailbox Data Register %s 0x39D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB25_DL Mailbox Data Length Register %s 0x394 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB25_ID Mailbox ID Register %s 0x390 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB25_TS Mailbox Time Stamp Register %s 0x39E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB26_D0 Mailbox Data Register %s 0x3A6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB26_D1 Mailbox Data Register %s 0x3A7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB26_D2 Mailbox Data Register %s 0x3A8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB26_D3 Mailbox Data Register %s 0x3A9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB26_D4 Mailbox Data Register %s 0x3AA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB26_D5 Mailbox Data Register %s 0x3AB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB26_D6 Mailbox Data Register %s 0x3AC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB26_D7 Mailbox Data Register %s 0x3AD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB26_DL Mailbox Data Length Register %s 0x3A4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB26_ID Mailbox ID Register %s 0x3A0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB26_TS Mailbox Time Stamp Register %s 0x3AE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB27_D0 Mailbox Data Register %s 0x3B6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB27_D1 Mailbox Data Register %s 0x3B7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB27_D2 Mailbox Data Register %s 0x3B8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB27_D3 Mailbox Data Register %s 0x3B9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB27_D4 Mailbox Data Register %s 0x3BA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB27_D5 Mailbox Data Register %s 0x3BB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB27_D6 Mailbox Data Register %s 0x3BC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB27_D7 Mailbox Data Register %s 0x3BD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB27_DL Mailbox Data Length Register %s 0x3B4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB27_ID Mailbox ID Register %s 0x3B0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB27_TS Mailbox Time Stamp Register %s 0x3BE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB28_D0 Mailbox Data Register %s 0x3C6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB28_D1 Mailbox Data Register %s 0x3C7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB28_D2 Mailbox Data Register %s 0x3C8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB28_D3 Mailbox Data Register %s 0x3C9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB28_D4 Mailbox Data Register %s 0x3CA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB28_D5 Mailbox Data Register %s 0x3CB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB28_D6 Mailbox Data Register %s 0x3CC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB28_D7 Mailbox Data Register %s 0x3CD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB28_DL Mailbox Data Length Register %s 0x3C4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB28_ID Mailbox ID Register %s 0x3C0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB28_TS Mailbox Time Stamp Register %s 0x3CE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB29_D0 Mailbox Data Register %s 0x3D6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB29_D1 Mailbox Data Register %s 0x3D7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB29_D2 Mailbox Data Register %s 0x3D8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB29_D3 Mailbox Data Register %s 0x3D9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB29_D4 Mailbox Data Register %s 0x3DA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB29_D5 Mailbox Data Register %s 0x3DB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB29_D6 Mailbox Data Register %s 0x3DC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB29_D7 Mailbox Data Register %s 0x3DD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB29_DL Mailbox Data Length Register %s 0x3D4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB29_ID Mailbox ID Register %s 0x3D0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB29_TS Mailbox Time Stamp Register %s 0x3DE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB2_D0 Mailbox Data Register %s 0x226 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB2_D1 Mailbox Data Register %s 0x227 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB2_D2 Mailbox Data Register %s 0x228 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB2_D3 Mailbox Data Register %s 0x229 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB2_D4 Mailbox Data Register %s 0x22A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB2_D5 Mailbox Data Register %s 0x22B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB2_D6 Mailbox Data Register %s 0x22C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB2_D7 Mailbox Data Register %s 0x22D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB2_DL Mailbox Data Length Register %s 0x224 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB2_ID Mailbox ID Register %s 0x220 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB2_TS Mailbox Time Stamp Register %s 0x22E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB30_D0 Mailbox Data Register %s 0x3E6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB30_D1 Mailbox Data Register %s 0x3E7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB30_D2 Mailbox Data Register %s 0x3E8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB30_D3 Mailbox Data Register %s 0x3E9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB30_D4 Mailbox Data Register %s 0x3EA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB30_D5 Mailbox Data Register %s 0x3EB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB30_D6 Mailbox Data Register %s 0x3EC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB30_D7 Mailbox Data Register %s 0x3ED 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB30_DL Mailbox Data Length Register %s 0x3E4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB30_ID Mailbox ID Register %s 0x3E0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB30_TS Mailbox Time Stamp Register %s 0x3EE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB31_D0 Mailbox Data Register %s 0x3F6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB31_D1 Mailbox Data Register %s 0x3F7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB31_D2 Mailbox Data Register %s 0x3F8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB31_D3 Mailbox Data Register %s 0x3F9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB31_D4 Mailbox Data Register %s 0x3FA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB31_D5 Mailbox Data Register %s 0x3FB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB31_D6 Mailbox Data Register %s 0x3FC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB31_D7 Mailbox Data Register %s 0x3FD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB31_DL Mailbox Data Length Register %s 0x3F4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB31_ID Mailbox ID Register %s 0x3F0 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB31_TS Mailbox Time Stamp Register %s 0x3FE 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB3_D0 Mailbox Data Register %s 0x236 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB3_D1 Mailbox Data Register %s 0x237 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB3_D2 Mailbox Data Register %s 0x238 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB3_D3 Mailbox Data Register %s 0x239 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB3_D4 Mailbox Data Register %s 0x23A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB3_D5 Mailbox Data Register %s 0x23B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB3_D6 Mailbox Data Register %s 0x23C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB3_D7 Mailbox Data Register %s 0x23D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB3_DL Mailbox Data Length Register %s 0x234 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB3_ID Mailbox ID Register %s 0x230 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB3_TS Mailbox Time Stamp Register %s 0x23E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB4_D0 Mailbox Data Register %s 0x246 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB4_D1 Mailbox Data Register %s 0x247 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB4_D2 Mailbox Data Register %s 0x248 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB4_D3 Mailbox Data Register %s 0x249 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB4_D4 Mailbox Data Register %s 0x24A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB4_D5 Mailbox Data Register %s 0x24B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB4_D6 Mailbox Data Register %s 0x24C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB4_D7 Mailbox Data Register %s 0x24D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB4_DL Mailbox Data Length Register %s 0x244 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB4_ID Mailbox ID Register %s 0x240 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB4_TS Mailbox Time Stamp Register %s 0x24E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB5_D0 Mailbox Data Register %s 0x256 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB5_D1 Mailbox Data Register %s 0x257 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB5_D2 Mailbox Data Register %s 0x258 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB5_D3 Mailbox Data Register %s 0x259 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB5_D4 Mailbox Data Register %s 0x25A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB5_D5 Mailbox Data Register %s 0x25B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB5_D6 Mailbox Data Register %s 0x25C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB5_D7 Mailbox Data Register %s 0x25D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB5_DL Mailbox Data Length Register %s 0x254 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB5_ID Mailbox ID Register %s 0x250 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB5_TS Mailbox Time Stamp Register %s 0x25E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB6_D0 Mailbox Data Register %s 0x266 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB6_D1 Mailbox Data Register %s 0x267 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB6_D2 Mailbox Data Register %s 0x268 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB6_D3 Mailbox Data Register %s 0x269 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB6_D4 Mailbox Data Register %s 0x26A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB6_D5 Mailbox Data Register %s 0x26B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB6_D6 Mailbox Data Register %s 0x26C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB6_D7 Mailbox Data Register %s 0x26D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB6_DL Mailbox Data Length Register %s 0x264 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB6_ID Mailbox ID Register %s 0x260 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB6_TS Mailbox Time Stamp Register %s 0x26E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB7_D0 Mailbox Data Register %s 0x276 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB7_D1 Mailbox Data Register %s 0x277 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB7_D2 Mailbox Data Register %s 0x278 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB7_D3 Mailbox Data Register %s 0x279 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB7_D4 Mailbox Data Register %s 0x27A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB7_D5 Mailbox Data Register %s 0x27B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB7_D6 Mailbox Data Register %s 0x27C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB7_D7 Mailbox Data Register %s 0x27D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB7_DL Mailbox Data Length Register %s 0x274 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB7_ID Mailbox ID Register %s 0x270 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB7_TS Mailbox Time Stamp Register %s 0x27E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB8_D0 Mailbox Data Register %s 0x286 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB8_D1 Mailbox Data Register %s 0x287 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB8_D2 Mailbox Data Register %s 0x288 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB8_D3 Mailbox Data Register %s 0x289 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB8_D4 Mailbox Data Register %s 0x28A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB8_D5 Mailbox Data Register %s 0x28B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB8_D6 Mailbox Data Register %s 0x28C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB8_D7 Mailbox Data Register %s 0x28D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB8_DL Mailbox Data Length Register %s 0x284 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB8_ID Mailbox ID Register %s 0x280 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB8_TS Mailbox Time Stamp Register %s 0x28E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MB9_D0 Mailbox Data Register %s 0x296 8 read-write n 0x0 0x0 DATA0 Data Bytes 0 0 7 read-write MB9_D1 Mailbox Data Register %s 0x297 8 read-write n 0x0 0x0 DATA1 Data Bytes 1 0 7 read-write MB9_D2 Mailbox Data Register %s 0x298 8 read-write n 0x0 0x0 DATA2 Data Bytes 2 0 7 read-write MB9_D3 Mailbox Data Register %s 0x299 8 read-write n 0x0 0x0 DATA3 Data Bytes 3 0 7 read-write MB9_D4 Mailbox Data Register %s 0x29A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4 0 7 read-write MB9_D5 Mailbox Data Register %s 0x29B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5 0 7 read-write MB9_D6 Mailbox Data Register %s 0x29C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6 0 7 read-write MB9_D7 Mailbox Data Register %s 0x29D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7 0 7 read-write MB9_DL Mailbox Data Length Register %s 0x294 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write Others Data length = 8 bytes 0x0 Data length = 0 byte 0x0 0x1 Data length = 1 byte 0x1 0x2 Data length = 2 bytes 0x2 0x3 Data length = 3 bytes 0x3 0x4 Data length = 4 bytes 0x4 0x5 Data length = 5 bytes 0x5 0x6 Data length = 6 bytes 0x6 0x7 Data length = 7 bytes 0x7 MB9_ID Mailbox ID Register %s 0x290 32 read-write n 0x0 0x0 EID Extended ID of data and remote frames 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID of data and remote frames 18 10 read-write MB9_TS Mailbox Time Stamp Register %s 0x29E 16 read-write n 0x0 0x0 TSH Time Stamp Higher Byte 8 7 read-write TSL Time Stamp Lower Byte 0 7 read-write MCTL_RX0 Message Control Register for Receive 0x820 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX1 Message Control Register for Receive 0x821 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX10 Message Control Register for Receive 0x82A 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX11 Message Control Register for Receive 0x82B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX12 Message Control Register for Receive 0x82C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX13 Message Control Register for Receive 0x82D 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX14 Message Control Register for Receive 0x82E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX15 Message Control Register for Receive 0x82F 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX16 Message Control Register for Receive 0x830 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX17 Message Control Register for Receive 0x831 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX18 Message Control Register for Receive 0x832 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX19 Message Control Register for Receive 0x833 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX2 Message Control Register for Receive 0x822 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX20 Message Control Register for Receive 0x834 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX21 Message Control Register for Receive 0x835 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX22 Message Control Register for Receive 0x836 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX23 Message Control Register for Receive 0x837 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX24 Message Control Register for Receive 0x838 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX25 Message Control Register for Receive 0x839 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX26 Message Control Register for Receive 0x83A 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX27 Message Control Register for Receive 0x83B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX28 Message Control Register for Receive 0x83C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX29 Message Control Register for Receive 0x83D 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX3 Message Control Register for Receive 0x823 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX30 Message Control Register for Receive 0x83E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX31 Message Control Register for Receive 0x83F 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX4 Message Control Register for Receive 0x824 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX5 Message Control Register for Receive 0x825 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX6 Message Control Register for Receive 0x826 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX7 Message Control Register for Receive 0x827 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX8 Message Control Register for Receive 0x828 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_RX9 Message Control Register for Receive 0x829 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag 2 read-write 0 Message not overwritten or overrun #0 1 Message overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data received, or 0 was written to the flag #0 1 New message being stored or was stored in the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot reception #0 1 Enable one-shot reception #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX0 Message Control Register for Transmit MCTL_RX[%s] 0x820 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX1 Message Control Register for Transmit MCTL_RX[%s] 0x821 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX10 Message Control Register for Transmit MCTL_RX[%s] 0x82A 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX11 Message Control Register for Transmit MCTL_RX[%s] 0x82B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX12 Message Control Register for Transmit MCTL_RX[%s] 0x82C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX13 Message Control Register for Transmit MCTL_RX[%s] 0x82D 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX14 Message Control Register for Transmit MCTL_RX[%s] 0x82E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX15 Message Control Register for Transmit MCTL_RX[%s] 0x82F 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX16 Message Control Register for Transmit MCTL_RX[%s] 0x830 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX17 Message Control Register for Transmit MCTL_RX[%s] 0x831 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX18 Message Control Register for Transmit MCTL_RX[%s] 0x832 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX19 Message Control Register for Transmit MCTL_RX[%s] 0x833 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX2 Message Control Register for Transmit MCTL_RX[%s] 0x822 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX20 Message Control Register for Transmit MCTL_RX[%s] 0x834 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX21 Message Control Register for Transmit MCTL_RX[%s] 0x835 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX22 Message Control Register for Transmit MCTL_RX[%s] 0x836 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX23 Message Control Register for Transmit MCTL_RX[%s] 0x837 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX24 Message Control Register for Transmit MCTL_RX[%s] 0x838 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX25 Message Control Register for Transmit MCTL_RX[%s] 0x839 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX26 Message Control Register for Transmit MCTL_RX[%s] 0x83A 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX27 Message Control Register for Transmit MCTL_RX[%s] 0x83B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX28 Message Control Register for Transmit MCTL_RX[%s] 0x83C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX29 Message Control Register for Transmit MCTL_RX[%s] 0x83D 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX3 Message Control Register for Transmit MCTL_RX[%s] 0x823 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX30 Message Control Register for Transmit MCTL_RX[%s] 0x83E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX31 Message Control Register for Transmit MCTL_RX[%s] 0x83F 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX4 Message Control Register for Transmit MCTL_RX[%s] 0x824 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX5 Message Control Register for Transmit MCTL_RX[%s] 0x825 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX6 Message Control Register for Transmit MCTL_RX[%s] 0x826 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX7 Message Control Register for Transmit MCTL_RX[%s] 0x827 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX8 Message Control Register for Transmit MCTL_RX[%s] 0x828 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MCTL_TX9 Message Control Register for Transmit MCTL_RX[%s] 0x829 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 Disable one-shot transmission #0 1 Enable one-shot transmission #1 RECREQ Receive Mailbox Request 6 read-write 0 Do not configure for reception #0 1 Configure for reception #1 SENTDATA Transmission Complete Flag 0 read-write 0 Transmission not complete #0 1 Transmission complete #1 TRMABT Transmission Abort Complete Flag 2 read-write 0 Transmission started, transmission abort failed because transmission completed, or transmission abort not requested #0 1 Transmission abort complete #1 TRMACTIVE Transmission-in-Progress Status Flag 1 read-only 0 Transmission pending or not requested #0 1 Transmission in progress #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Do not configure for transmission #0 1 Configure for transmission #1 MIER Mailbox Interrupt Enable Register 0x42C 32 read-write n 0x0 0x0 MB00 Interrupt Enable 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB01 Interrupt Enable 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB02 Interrupt Enable 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB03 Interrupt Enable 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB04 Interrupt Enable 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB05 Interrupt Enable 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB06 Interrupt Enable 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB07 Interrupt Enable 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB08 Interrupt Enable 8 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB09 Interrupt Enable 9 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB10 Interrupt Enable 10 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB11 Interrupt Enable 11 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB12 Interrupt Enable 12 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB13 Interrupt Enable 13 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB14 Interrupt Enable 14 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB15 Interrupt Enable 15 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB16 Interrupt Enable 16 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB17 Interrupt Enable 17 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB18 Interrupt Enable 18 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB19 Interrupt Enable 19 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB20 Interrupt Enable 20 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB21 Interrupt Enable 21 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB22 Interrupt Enable 22 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB23 Interrupt Enable 23 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB24 Interrupt Enable 24 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB25 Interrupt Enable 25 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB26 Interrupt Enable 26 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB27 Interrupt Enable 27 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB28 Interrupt Enable 28 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB29 Interrupt Enable 29 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB30 Interrupt Enable 30 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB31 Interrupt Enable 31 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MIER_FIFO Mailbox Interrupt Enable Register for FIFO Mailbox Mode MIER 0x42C 32 read-write n 0x0 0x0 MB00 Interrupt Enable 0 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB01 Interrupt Enable 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB02 Interrupt Enable 2 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB03 Interrupt Enable 3 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB04 Interrupt Enable 4 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB05 Interrupt Enable 5 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB06 Interrupt Enable 6 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB07 Interrupt Enable 7 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB08 Interrupt Enable 8 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB09 Interrupt Enable 9 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB10 Interrupt Enable 10 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB11 Interrupt Enable 11 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB12 Interrupt Enable 12 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB13 Interrupt Enable 13 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB14 Interrupt Enable 14 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB15 Interrupt Enable 15 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB16 Interrupt Enable 16 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB17 Interrupt Enable 17 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB18 Interrupt Enable 18 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB19 Interrupt Enable 19 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB20 Interrupt Enable 20 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB21 Interrupt Enable 21 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB22 Interrupt Enable 22 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB23 Interrupt Enable 23 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB24 Transmit FIFO Interrupt Enable 24 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB25 Transmit FIFO Interrupt Generation Timing Control 25 read-write 0 Generate every time transmission completes #0 1 Generate when the transmit FIFO empties on transmission completion #1 MB28 Receive FIFO Interrupt Enable 28 read-write 0 Disable interrupt #0 1 Enable interrupt #1 MB29 Receive FIFO Interrupt Generation Timing Control 29 read-write 0 Generate every time reception completes #0 1 Generate when the receive FIFO becomes a buffer warning on reception completion #1 MKIVLR Mask Invalid Register 0x428 32 read-write n 0x0 0x0 MB00 Mask Invalid 0 read-write 0 Mask valid #0 1 Mask invalid #1 MB01 Mask Invalid 1 read-write 0 Mask valid #0 1 Mask invalid #1 MB02 Mask Invalid 2 read-write 0 Mask valid #0 1 Mask invalid #1 MB03 Mask Invalid 3 read-write 0 Mask valid #0 1 Mask invalid #1 MB04 Mask Invalid 4 read-write 0 Mask valid #0 1 Mask invalid #1 MB05 Mask Invalid 5 read-write 0 Mask valid #0 1 Mask invalid #1 MB06 Mask Invalid 6 read-write 0 Mask valid #0 1 Mask invalid #1 MB07 Mask Invalid 7 read-write 0 Mask valid #0 1 Mask invalid #1 MB08 Mask Invalid 8 read-write 0 Mask valid #0 1 Mask invalid #1 MB09 Mask Invalid 9 read-write 0 Mask valid #0 1 Mask invalid #1 MB10 Mask Invalid 10 read-write 0 Mask valid #0 1 Mask invalid #1 MB11 Mask Invalid 11 read-write 0 Mask valid #0 1 Mask invalid #1 MB12 Mask Invalid 12 read-write 0 Mask valid #0 1 Mask invalid #1 MB13 Mask Invalid 13 read-write 0 Mask valid #0 1 Mask invalid #1 MB14 Mask Invalid 14 read-write 0 Mask valid #0 1 Mask invalid #1 MB15 Mask Invalid 15 read-write 0 Mask valid #0 1 Mask invalid #1 MB16 Mask Invalid 16 read-write 0 Mask valid #0 1 Mask invalid #1 MB17 Mask Invalid 17 read-write 0 Mask valid #0 1 Mask invalid #1 MB18 Mask Invalid 18 read-write 0 Mask valid #0 1 Mask invalid #1 MB19 Mask Invalid 19 read-write 0 Mask valid #0 1 Mask invalid #1 MB20 Mask Invalid 20 read-write 0 Mask valid #0 1 Mask invalid #1 MB21 Mask Invalid 21 read-write 0 Mask valid #0 1 Mask invalid #1 MB22 Mask Invalid 22 read-write 0 Mask valid #0 1 Mask invalid #1 MB23 Mask Invalid 23 read-write 0 Mask valid #0 1 Mask invalid #1 MB24 Mask Invalid 24 read-write 0 Mask valid #0 1 Mask invalid #1 MB25 Mask Invalid 25 read-write 0 Mask valid #0 1 Mask invalid #1 MB26 Mask Invalid 26 read-write 0 Mask valid #0 1 Mask invalid #1 MB27 Mask Invalid 27 read-write 0 Mask valid #0 1 Mask invalid #1 MB28 Mask Invalid 28 read-write 0 Mask valid #0 1 Mask invalid #1 MB29 Mask Invalid 29 read-write 0 Mask valid #0 1 Mask invalid #1 MB30 Mask Invalid 30 read-write 0 Mask valid #0 1 Mask invalid #1 MB31 Mask Invalid 31 read-write 0 Mask valid #0 1 Mask invalid #1 MKR0 Mask Register %s 0x400 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR1 Mask Register %s 0x404 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR2 Mask Register %s 0x408 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR3 Mask Register %s 0x40C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR4 Mask Register %s 0x410 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR5 Mask Register %s 0x414 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR6 Mask Register %s 0x418 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MKR7 Mask Register %s 0x41C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write 0 Do not compare associated EID[17:0] bits #0 1 Compare associated EID[17:0] bits #1 SID Standard ID 18 10 read-write 0 Do not compare associated SID[10:0] bits #0 1 Compare associated SID[10:0] bits #1 MSMR Mailbox Search Mode Register 0x853 8 read-write n 0x0 0x0 MBSM Mailbox Search Mode Select 0 1 read-write 00 Receive mailbox search mode #00 01 Transmit mailbox search mode #01 10 Message lost search mode #10 11 Channel search mode #11 MSSR Mailbox Search Status Register 0x852 8 read-only n 0x0 0x0 MBNST Search Result Mailbox Number Status 0 4 read-only SEST Search Result Status 7 read-only 0 Search result found #0 1 No search result #1 RECR Receive Error Count Register 0x84E 8 read-only n 0x0 0x0 RFCR Receive FIFO Control Register 0x848 8 read-write n 0x0 0x0 RFE Receive FIFO Enable 0 read-write 0 Disable receive FIFO #0 1 Enable receive FIFO #1 RFEST Receive FIFO Empty Status Flag 7 read-only 0 Unread message in receive FIFO #0 1 No unread message in receive FIFO #1 RFFST Receive FIFO Full Status Flag 5 read-only 0 Receive FIFO not full #0 1 Receive FIFO full (4 unread messages) #1 RFMLF Receive FIFO Message Lost Flag 4 read-write 0 Receive FIFO message not lost #0 1 Receive FIFO message lost #1 RFUST Receive FIFO Unread Message Number Status 1 2 read-only 000 No unread message #000 001 1 unread message #001 010 2 unread messages #010 011 3 unread messages #011 100 4 unread messages #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RFWST Receive FIFO Buffer Warning Status Flag 6 read-only 0 Receive FIFO is not buffer warning #0 1 Receive FIFO is buffer warning (3 unread messages) #1 RFPCR Receive FIFO Pointer Control Register 0x849 8 write-only n 0x0 0x0 STR Status Register 0x842 16 read-only n 0x0 0x0 BOST Bus-Off Status Flag 12 read-only 0 Not in bus-off state #0 1 In bus-off state #1 EPST Error-Passive Status Flag 11 read-only 0 Not in error-passive state #0 1 In error-passive state #1 EST Error Status Flag 7 read-only 0 No error occurred #0 1 Error occurred #1 FMLST FIFO Mailbox Message Lost Status Flag 5 read-only 0 RFMLF = 0 #0 1 RFMLF = 1 #1 HLTST CAN Halt Status Flag 9 read-only 0 Not in CAN halt mode #0 1 In CAN halt mode #1 NDST NEWDATA Status Flag 0 read-only 0 No mailbox with NEWDATA = 1 #0 1 One or more mailboxes with NEWDATA = 1 #1 NMLST Normal Mailbox Message Lost Status Flag 4 read-only 0 No mailbox with MSGLOST = 1 #0 1 One or more mailboxes with MSGLOST = 1 #1 RECST Receive Status Flag 14 read-only 0 Bus idle or transmission in progress #0 1 Reception in progress #1 RFST Receive FIFO Status Flag 2 read-only 0 Receive FIFO empty #0 1 Message in receive FIFO #1 RSTST CAN Reset Status Flag 8 read-only 0 Not in CAN reset mode #0 1 In CAN reset mode #1 SDST SENTDATA Status Flag 1 read-only 0 No mailbox with SENTDATA = 1 #0 1 One or more mailboxes with SENTDATA = 1 #1 SLPST CAN Sleep Status Flag 10 read-only 0 Not in CAN sleep mode #0 1 In CAN sleep mode #1 TABST Transmission Abort Status Flag 6 read-only 0 No mailbox with TRMABT = 1 #0 1 One or more mailboxes with TRMABT = 1 #1 TFST Transmit FIFO Status Flag 3 read-only 0 Transmit FIFO is full #0 1 Transmit FIFO is not full #1 TRMST Transmit Status Flag 13 read-only 0 Bus idle or reception in progress #0 1 Transmission in progress or module in bus-off state #1 TCR Test Control Register 0x858 8 read-write n 0x0 0x0 TSTE CAN Test Mode Enable 0 read-write 0 Disable CAN test mode #0 1 Enable CAN test mode #1 TSTM CAN Test Mode Select 1 1 read-write 00 Not CAN test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (external loopback) #10 11 Self-test mode 1 (internal loopback) #11 TECR Transmit Error Count Register 0x84F 8 read-only n 0x0 0x0 TFCR Transmit FIFO Control Register 0x84A 8 read-write n 0x0 0x0 TFE Transmit FIFO Enable 0 read-write 0 Disable transmit FIFO #0 1 Enable transmit FIFO #1 TFEST Transmit FIFO Empty Status 7 read-only 0 Unsent message in transmit FIFO #0 1 No unsent message in transmit FIFO #1 TFFST Transmit FIFO Full Status 6 read-only 0 Transmit FIFO not full #0 1 Transmit FIFO full (4 unsent messages) #1 TFUST Transmit FIFO Unsent Message Number Status 1 2 read-only 000 0 unsent messages #000 001 1 unsent message #001 010 2 unsent messages #010 011 3 unread messages #011 100 4 unread messages #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TFPCR Transmit FIFO Pointer Control Register 0x84B 8 write-only n 0x0 0x0 TSR Time Stamp Register 0x854 16 read-only n 0x0 0x0 CPSCU CPU System Security Control Unit CPSCU 0x0 0x130 0x8 registers n 0x14 0x4 registers n 0x1B0 0x4 registers n 0x30 0x8 registers n CPUDSAR CPU Debug Security Attribution Register 0x1B0 32 read-write n 0x0 0x0 CPUDSA0 CPU Debug Security Attribution 0 0 read-write 0 Secure #0 1 Non-secure #1 DMACSAR DMAC Controller Security Attribution Register 0x34 32 read-only n 0x0 0x0 DMASTSA DMAST Security Attribution 0 read-only 0 Secure #0 1 Non-secure #1 DTCSAR DTC Controller Security Attribution Register 0x30 32 read-only n 0x0 0x0 DTCSTSA DTC Security Attribution 0 read-only 0 Secure. #0 1 Non-Secure. #1 MMPUSARA Master Memory Protection Unit Security Attribution Register A 0x130 32 read-write n 0x0 0x0 MMPUAnSA MMPUAn Security Attribution (n = 0 to 7) 0 7 read-write 0 Secure #0 1 Non-Secure #1 MMPUSARB Master Memory Protection Unit Security Attribution Register B 0x134 32 read-write n 0x0 0x0 MMPUB0SA MMPUB0 Security Attribution 0 read-write 0 Secure #0 1 Non-Secure #1 STBRAMSAR Standby RAM memory Security Attribution Register 0x14 32 read-write n 0x0 0x0 NSBSTBR Security attributes of each region for Standby RAM 0 3 read-write Others Region7-0 are all Non-Secure. 0x0 Region7-0 are all Secure. 0x0 0x1 Region7 is Non-secure. Region6-0 are Secure 0x1 0x2 Region7-6 are Non-secure. Region5-0 are Secure. 0x2 0x3 Region7-5 are Non-secure. Region4-0 are Secure. 0x3 0x4 Region7-4 are Non-secure. Region 3-0 are Secure. 0x4 0x5 Region7-3 are Non-secure. Region 2-0 are Secure. 0x5 0x6 Region7-2 are Non-secure. Region 1-0 are Secure. 0x6 0x7 Region7-1 are Non-Secure. Region0 is Secure. 0x7 CRC Cyclic Redundancy Check Calculator CRC 0x0 0x0 0x1 registers n 0x4 0x4 registers n 0x8 0x4 registers n CRCCR0 CRC Control Register 0 0x0 8 read-write n 0x0 0x0 DORCLR CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear 7 write-only 0 No effect #0 1 Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register #1 GPS CRC Generating Polynomial Switching 0 2 read-write Others No calculation is executed 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1) #100 101 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1) #101 LMS CRC Calculation Switching 6 read-write 0 Generate CRC code for LSB-first communication #0 1 Generate CRC code for MSB-first communication #1 CRCDIR CRC Data Input Register 0x4 32 read-write n 0x0 0x0 CRCDIR_BY CRC Data Input Register CRCDIR 0x4 8 read-write n 0x0 0x0 CRCDOR CRC Data Output Register 0x8 32 read-write n 0x0 0x0 CRCDOR_BY CRC Data Output Register CRCDOR 0x8 8 read-write n 0x0 0x0 CRCDOR_HA CRC Data Output Register CRCDOR 0x8 16 read-write n 0x0 0x0 CTSU Capacitive Touch Sensing Unit CTSU 0x0 0x0 0x9 registers n 0x10 0xA registers n 0x1C 0x2 registers n 0x20 0x1 registers n 0xB 0x3 registers n CTSUCHAC0 CTSU Channel Enable Control Register 0 0x6 8 read-write n 0x0 0x0 CTSUCHAC1 CTSU Channel Enable Control Register 1 0x7 8 read-write n 0x0 0x0 CTSUCHAC2 CTSU Channel Enable Control Register 2 0x8 8 read-write n 0x0 0x0 CTSUCHTRC0 CTSU Channel Transmit/Receive Control Register 0 0xB 8 read-write n 0x0 0x0 CTSUCHTRC1 CTSU Channel Transmit/Receive Control Register 1 0xC 8 read-write n 0x0 0x0 CTSUCHTRC2 CTSU Channel Transmit/Receive Control Register 2 0xD 8 read-write n 0x0 0x0 CTSUCR0 CTSU Control Register 0 0x0 8 read-write n 0x0 0x0 CTSUCR1 CTSU Control Register 1 0x1 8 read-write n 0x0 0x0 CTSUDCLKC CTSU High-Pass Noise Reduction Control Register 0x10 8 read-write n 0x0 0x0 CTSUERRS CTSU Error Status Register 0x1C 16 read-write n 0x0 0x0 CTSUDRV Calibration Setting 1 3 read-write 0 Capacitance measurement mode #0 1 Calibration setting 1 #1 CTSUICOMP TSCAP Voltage Error Monitor 15 read-only 0 Normal TSCAP voltage #0 1 Abnormal TSCAP voltage #1 CTSUSPMD Calibration Mode 0 1 read-write Others Seting prohibited 00 Capacitance measurement mode #00 10 Calibration mode #10 CTSUTSOC Calibration Setting 2 7 read-write 0 Capacitance measurement mode #0 1 Calibration setting 2 #1 CTSUTSOD TS Pin Fixed Output 2 read-write 0 Capacitance measurement mode #0 1 TS pins are forced to be high or low #1 CTSUMCH0 CTSU Measurement Channel Register 0 0x4 8 read-write n 0x0 0x0 CTSUMCH1 CTSU Measurement Channel Register 1 0x5 8 read-only n 0x0 0x0 CTSUSC CTSU Sensor Counter 0x18 16 read-only n 0x0 0x0 CTSUSDPRS CTSU Synchronous Noise Reduction Setting Register 0x2 8 read-write n 0x0 0x0 CTSUSO0 CTSU Sensor Offset Register 0 0x14 16 read-write n 0x0 0x0 CTSUSO1 CTSU Sensor Offset Register 1 0x16 16 read-write n 0x0 0x0 CTSUSSC CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register 0x12 16 read-write n 0x0 0x0 CTSUSSDIV CTSU Spectrum Diffusion Frequency Division Setting 8 3 read-write CTSUSST CTSU Sensor Stabilization Wait Control Register 0x3 8 read-write n 0x0 0x0 CTSUST CTSU Status Register 0x11 8 read-write n 0x0 0x0 CTSUTRMR CTSU Reference Current Calibration Register 0x20 8 read-write n 0x0 0x0 DAC12 12-bit D/A converter DAC12 0x0 0x0 0x7 registers n 0x1C 0x1 registers n 0x8 0x1 registers n 0xC0 0x1 registers n DAADSCR D/A A/D Synchronous Start Control Register 0x6 8 read-write n 0x0 0x0 DAADST D/A A/D Synchronous Conversion 7 read-write 0 Do not synchronize DAC12 with ADC12 (unit 1) operation (disable interference reduction between D/A and A/D conversion). #0 1 Synchronize DAC12 with ADC12 (unit 1) operation (enable interference reduction between D/A and A/D conversion). #1 DAADUSR D/A A/D Synchronous Unit Select Register 0xC0 8 read-write n 0x0 0x0 AMADSEL1 A/D Unit 1 Select 1 read-write 0 Do not select unit 1 #0 1 Select unit 1 #1 DAAMPCR D/A Output Amplifier Control Register 0x8 8 read-write n 0x0 0x0 DAAMP0 Amplifier Control 0 6 read-write 0 Do not use channel 0 output amplifier #0 1 Use channel 0 output amplifier #1 DAAMP1 Amplifier Control 1 7 read-write 0 Do not use channel 1 output amplifier #0 1 Use channel 1 output amplifier #1 DAASWCR D/A Amplifier Stabilization Wait Control Register 0x1C 8 read-write n 0x0 0x0 DAASW0 D/A Amplifier Stabilization Wait 0 6 read-write 0 Amplifier stabilization wait off (output) for channel 0 #0 1 Amplifier stabilization wait on (high-Z) for channel 0 #1 DAASW1 D/A Amplifier Stabilization Wait 1 7 read-write 0 Amplifier stabilization wait off (output) for channel 1 #0 1 Amplifier stabilization wait on (high-Z) for channel 1 #1 DACR D/A Control Register 0x4 8 read-write n 0x0 0x0 DAE D/A Enable 5 read-write 0 Control D/A conversion of channels 0 and 1 individually #0 1 Control D/A conversion of channels 0 and 1 collectively #1 DAOE0 D/A Output Enable 0 6 read-write 0 Disable analog output of channel 0 (DA0) #0 1 Enable D/A conversion of channel 0 (DA0) #1 DAOE1 D/A Output Enable 1 7 read-write 0 Disable analog output of channel 1 (DA1) #0 1 Enable D/A conversion of channel 1 (DA1) #1 DADPR DADRn Format Select Register 0x5 8 read-write n 0x0 0x0 DPSEL DADRn Format Select 7 read-write 0 Right-justified format #0 1 Left-justified format #1 DADR0 D/A Data Register %s 0x0 16 read-write n 0x0 0x0 DADR1 D/A Data Register %s 0x2 16 read-write n 0x0 0x0 DBG Debug Function DBG 0x0 0x0 0x4 registers n 0x10 0x4 registers n DBGSTOPCR Debug Stop Control Register 0x10 32 read-write n 0x0 0x0 DBGSTOP_CPER Mask bit for Cache SRAM parity error reset/interrupt 31 read-write 0 Enable Cache SRAM parity error reset/interrupt #0 1 Mask Cache SRAM parity error reset/interrupt #1 DBGSTOP_IWDT Mask bit for IWDT reset/interrupt 0 read-write 0 Enable IWDT reset/interrupt #0 1 Mask IWDT reset/interrupt and stop WDT count when CPU is in OCD break mode #1 DBGSTOP_LVD0 Mask bit for LVD0 reset 16 read-write 0 Enable LVD0 reset #0 1 Mask LVD0 reset #1 DBGSTOP_LVD1 Mask bit for LVD1 reset/interrupt 17 read-write 0 Enable LVD1 reset/interrupt #0 1 Mask LVD1 reset/interrupt #1 DBGSTOP_LVD2 Mask bit for LVD2 reset/interrupt 18 read-write 0 Enable LVD2 reset/interrupt #0 1 Mask LVD2 reset/interrupt #1 DBGSTOP_RECCR Mask bit for SRAM ECC error reset/interrupt 25 read-write 0 Enable SRAM ECC error reset/interrupt #0 1 Mask SRAM ECC error reset/interrupt #1 DBGSTOP_RPER Mask bit for SRAM parity error reset/interrupt 24 read-write 0 Enable SRAM parity error reset/interrupt #0 1 Mask SRAM parity error reset/interrupt #1 DBGSTOP_WDT Mask bit for WDT reset/interrupt 1 read-write 0 Enable WDT reset/interrupt #0 1 Mask WDT reset/interrupt and stop WDT count when CPU is in OCD break mode #1 DBGSTR Debug Status Register 0x0 32 read-only n 0x0 0x0 CDBGPWRUPACK Debug power-up acknowledge 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 CDBGPWRUPREQ Debug power-up request 28 read-only 0 OCD is not requesting debug power up #0 1 OCD is requesting debug power up #1 DMA DMAC Module Activation DMA 0x0 0x0 0x1 registers n 0x40 0x4 registers n DMAST DMA Module Activation Register 0x0 8 read-write n 0x0 0x0 DMST DMAC Operation Enable 0 read-write 0 DMAC activation is disabled #0 1 DMAC activation is enabled #1 DMECHR DMAC Error Channel Register 0x40 32 read-write n 0x0 0x0 DMECH DMAC Error channel 0 2 read-only DMECHSAM DMAC Error channel Security Attribution Monitor 8 read-only 0 secure channel #0 1 non-secure channel #1 DMESTA DMAC Error Status 16 read-write 0 No DMA transfer error occurred #0 1 DMA transfer error occurred #1 DMAC0 Direct memory access controller 0 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DMAC1 Direct memory access controller 1 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DMAC2 Direct memory access controller 2 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DMAC3 Direct memory access controller 3 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DMAC4 Direct memory access controller 4 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DMAC5 Direct memory access controller 5 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DMAC6 Direct memory access controller 6 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DMAC7 Direct memory access controller 7 DMAC0 0x0 0x0 0x12 registers n 0x13 0x3 registers n 0x18 0x7 registers n 0x20 0x11 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DADR Destination Address Update Select After Reload 5 read-write 0 Only reloading #0 1 Add index after reloading #1 DARA Destination Address Extended Repeat Area 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Destination address is fixed #00 01 Offset addition #01 10 Destination address is incremented #10 11 Destination address is decremented #11 SADR Source Address Update Select After Reload 13 read-write 0 Only reloading #0 1 Add index after reloading #1 SARA Source Address Extended Repeat Area 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Source address is fixed #00 01 Offset addition #01 10 Source address is incremented #10 11 Source address is decremented #11 DMBWR DMA Bufferable Write Enable Register 0x30 8 read-write n 0x0 0x0 BWE Bufferable Write Enable 0 read-write 0 Disables Bufferable Write #0 1 Enables Bufferable Write #1 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write 0 Disables DMA transfer #0 1 Enables DMA transfer #1 DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0xC 32 read-write n 0x0 0x0 DMCRBH Specifies the number of block, repeat or repeat-block transfer operations. 16 15 read-write DMCRBL Functions as a number of block, repeat or repeat-block transfer counter. 0 15 read-write DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDBS DMA Destination Buffer Size Register 0x2C 32 read-write n 0x0 0x0 DMDBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMDBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMDRR DMA Destination Reload Address Register 0x24 32 read-write n 0x0 0x0 DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disables an interrupt request for an extended repeat area overflow on the destination address #0 1 Enables an interrupt request for an extended repeat area overflow on the destination address #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disables the transfer end interrupt request #0 1 Enables the transfer end interrupt request #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disables the transfer escape end interrupt request #0 1 Enables the transfer escape end interrupt request #1 RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disables the repeat size end interrupt request #0 1 Enables the repeat size end interrupt request #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disables an interrupt request for an extended repeat area overflow on the source address #0 1 Enables an interrupt request for an extended repeat area overflow on the source address #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software #0 1 SWREQ bit is not cleared after DMA transfer is started by software #1 SWREQ DMA Software Start 0 read-write 0 DMA transfer is not requested #0 1 DMA transfer is requested #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSBS DMA Source Buffer Size Register 0x28 32 read-write n 0x0 0x0 DMSBSH Specifies the repeat-area size in repeat-block transfer mode 16 15 read-write DMSBSL Functions as data transfer counter in repeat-block transfer mode 0 15 read-write DMSRR DMA Source Reload Address Register 0x20 32 read-write n 0x0 0x0 DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMAC Active Flag 7 read-only 0 DMAC is in the idle state #0 1 DMAC is operating #1 DTIF Transfer End Interrupt Flag 4 read-write 0 A transfer end interrupt has not been generated #0 1 A transfer end interrupt has been generated #1 ESIF Transfer Escape End Interrupt Flag 0 read-write 0 A transfer escape end interrupt has not been generated #0 1 A transfer escape end interrupt has been generated #1 DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software request #00 01 Hardware request #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area #00 01 The source is specified as the repeat area or block area #01 10 The repeat area or block area is not specified #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Repeat-block transfer #11 SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 TKP Transfer Keeping 10 read-write 0 Transfer is stopped by completion of specified total number of transfer operations. #0 1 Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 DOC Data Operation Circuit DOC 0x0 0x0 0x1 registers n 0x2 0x4 registers n DOCR DOC Control Register 0x0 8 read-write n 0x0 0x0 DCSEL Detection Condition Select 2 read-write 0 Set DOPCF when data mismatch is detected #0 1 Set DOPCF when data match is detected #1 DOPCF DOC Flag 5 read-only DOPCFCL DOPCF Clear 6 read-write 0 Retain DOPCF flag state #0 1 Clear DOPCF flag #1 OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DODIR DOC Data Input Register 0x2 16 read-write n 0x0 0x0 DODSR DOC Data Setting Register 0x4 16 read-write n 0x0 0x0 DTC Data Transfer Controller DTC 0x0 0x0 0x1 registers n 0x14 0x4 registers n 0x20 0x4 registers n 0x4 0x4 registers n 0xC 0x1 registers n 0xE 0x3 registers n DTCCR DTC Control Register 0x0 8 read-write n 0x0 0x0 RRS DTC Transfer Information Read Skip Enable 4 read-write 0 Transfer information read is not skipped #0 1 Transfer information read is skipped when vector numbers match #1 DTCCR_SEC DTC Control Register for secure Region 0x10 8 read-write n 0x0 0x0 RRSS DTC Transfer Information Read Skip Enable for Secure 4 read-write 0 Transfer information read is not skipped. #0 1 Transfer information read is skipped when vector numbers match. #1 DTCST DTC Module Start Register 0xC 8 read-write n 0x0 0x0 DTCST DTC Module Start 0 read-write 0 DTC module stopped #0 1 DTC module started #1 DTCSTS DTC Status Register 0xE 16 read-only n 0x0 0x0 ACT DTC Active Flag 15 read-only 0 DTC transfer operation is not in progress #0 1 DTC transfer operation is in progress #1 VECN DTC-Activating Vector Number Monitoring 0 7 read-only DTCVBR DTC Vector Base Register 0x4 32 read-write n 0x0 0x0 DTCVBR_SEC DTC Vector Base Register for secure Region 0x14 32 read-write n 0x0 0x0 DTEVR DTC Error Vector Register 0x20 32 read-write n 0x0 0x0 DTESTA DTC Error Status Flag 16 read-write 0 No DTC transfer error occurred #0 1 DTC transfer error occurred #1 DTEV DTC Error Vector Number 0 7 read-only DTEVSAM DTC Error Vector Number SA Monitor 8 read-only 0 Secure vector number #0 1 Non-Secure vector number #1 EDMAC0 DMA Controller for the Ethernet Controller Channel 0 EDMAC0 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x18 0x4 registers n 0x20 0x4 registers n 0x28 0x4 registers n 0x30 0x4 registers n 0x38 0x4 registers n 0x40 0x4 registers n 0x48 0x4 registers n 0x50 0x4 registers n 0x58 0x4 registers n 0x64 0x10 registers n 0x78 0x8 registers n 0x8 0x4 registers n 0xC8 0x8 registers n 0xD4 0x8 registers n EDMR EDMAC Mode Register 0x0 32 read-write n 0x0 0x0 DE Big Endian Mode/Little Endian Mode 6 read-write 0 Big endian mode #0 1 Little endian mode. #1 DL Transmit/Receive Descriptor Length 4 1 read-write 00 16 bytes #00 01 32 bytes #01 10 64 bytes #10 11 16 bytes. #11 SWR Software Reset 0 read-write EDRRR EDMAC Receive Request Register 0x10 32 read-write n 0x0 0x0 RR Receive Request 0 read-write 0 Disable the receive function #0 1 Read receive descriptor and enable the receive function. #1 EDTRR EDMAC Transmit Request Register 0x8 32 read-write n 0x0 0x0 TR Transmit Request 0 read-write EESIPR ETHERC/EDMAC Status Interrupt Enable Register 0x30 32 read-write n 0x0 0x0 ADEIP Address Error Interrupt Request Enable 23 read-write 0 Disable address error interrupt requests #0 1 Enable address error interrupt requests. #1 CDIP Late Collision Detect Interrupt Request Enable 9 read-write 0 Disable late collision detected interrupt requests #0 1 Enable late collision detected interrupt requests. #1 CERFIP CRC Error Interrupt Request Enable 0 read-write 0 Disable CRC error interrupt requests #0 1 Enable CRC error interrupt requests. #1 CNDIP Carrier Not Detect Interrupt Request Enable 11 read-write 0 Disable carrier not detected interrupt requests #0 1 Enable carrier not detected interrupt requests. #1 DLCIP Loss of Carrier Detect Interrupt Request Enable 10 read-write 0 Disable loss of carrier detected interrupt requests #0 1 Enable loss of carrier detected interrupt requests. #1 ECIIP ETHERC Status Register Source Interrupt Request Enable 22 read-write 0 Disable ETHERC status interrupt requests #0 1 Enable ETHERC status interrupt requests. #1 FRIP Frame Receive Interrupt Request Enable 18 read-write 0 Disable frame reception interrupt requests #0 1 Enable frame reception interrupt requests. #1 PREIP PHY-LSI Receive Error Interrupt Request Enable 1 read-write 0 Disable PHY-LSI receive error interrupt requests #0 1 Enable PHY-LSI receive error interrupt requests. #1 RABTIP Receive Abort Detect Interrupt Request Enable 25 read-write 0 Disable receive abort detected interrupt requests #0 1 Enable receive abort detected interrupt requests. #1 RDEIP Receive Descriptor Empty Interrupt Request Enable 17 read-write 0 Disable receive descriptor empty interrupt requests #0 1 Enable receive descriptor empty interrupt requests. #1 RFCOFIP Receive Frame Counter Overflow Interrupt Request Enable 24 read-write 0 Disable receive frame counter overflow interrupt requests #0 1 Enable receive frame counter overflow interrupt requests. #1 RFOFIP Receive FIFO Overflow Interrupt Request Enable 16 read-write 0 Disable overflow interrupt requests #0 1 Enable overflow interrupt requests. #1 RMAFIP Multicast Address Frame Receive Interrupt Request Enable 7 read-write 0 Disable multicast address frame receive interrupt requests #0 1 Enable multicast address frame receive interrupt requests. #1 RRFIP Alignment Error Interrupt Request Enable 4 read-write 0 Disable alignment error interrupt requests #0 1 Enable alignment error interrupt requests. #1 RTLFIP Frame-Too-Long Error Interrupt Request Enable 3 read-write 0 Disable frame-too-long error interrupt requests #0 1 Enable frame-too-long error interrupt requests. #1 RTSFIP Frame-Too-Short Error Interrupt Request Enable 2 read-write 0 Disable frame-too-short error interrupt requests #0 1 Enable frame-too-short error interrupt requests. #1 TABTIP Transmit Abort Detect Interrupt Request Enable 26 read-write 0 Disable transmit abort detected interrupt requests #0 1 Enable transmit abort detected interrupt requests. #1 TCIP Frame Transfer Complete Interrupt Request Enable 21 read-write 0 Disable frame transmission complete interrupt requests #0 1 Enable frame transmission complete interrupt requests. #1 TDEIP Transmit Descriptor Empty Interrupt Request Enable 20 read-write 0 Disable transmit descriptor empty interrupt requests #0 1 Enable transmit descriptor empty interrupt requests. #1 TFUFIP Transmit FIFO Underflow Interrupt Request Enable 19 read-write 0 Disable underflow interrupt requests #0 1 Enable underflow interrupt requests. #1 TROIP Transmit Retry Over Interrupt Request Enable 8 read-write 0 Disable transmit retry over interrupt requests #0 1 Enable transmit retry over interrupt requests. #1 TWBIP Write-Back Complete Interrupt Request Enable 30 read-write 0 Disable write-back complete interrupt requests #0 1 Enable write-back complete interrupt requests. #1 EESR ETHERC/EDMAC Status Register 0x28 32 read-write n 0x0 0x0 ADE Address Error Flag 23 read-write 0 Invalid memory address not detected (normal operation) #0 1 Invalid memory address detected. #1 CD Late Collision Detect Flag 9 read-write 0 Late collision not detected #0 1 Late collision detected during frame transmission. #1 CERF CRC Error Flag 0 read-write 0 CRC error not detected #0 1 CRC error detected. #1 CND Carrier Not Detect Flag 11 read-write 0 Carrier detected when transmission started #0 1 Carrier not detected during preamble transmission. #1 DLC Loss of Carrier Detect Flag 10 read-write 0 Loss of carrier not detected #0 1 Loss of carrier detected during frame transmission. #1 ECI ETHERC Status Register Source Flag 22 read-only 0 ETHERC status interrupt source not detected #0 1 ETHERC status interrupt source detected. #1 FR Frame Receive Flag 18 read-write 0 Frame not received #0 1 Frame received and update of the receive descriptor is complete. #1 PRE PHY-LSI Receive Error Flag 1 read-write 0 PHY-LSI receive error not detected #0 1 PHY-LSI receive error detected. #1 RABT Receive Abort Detect Flag 25 read-write 0 Frame reception not aborted or no reception requested #0 1 Frame reception aborted. #1 RDE Receive Descriptor Empty Flag 17 read-write 0 EDMAC detected that the receive descriptor valid bit (RD0.RACT) is 1 #0 1 EDMAC detected that the receive descriptor valid bit (RD0.RACT) is 0. #1 RFCOF Receive Frame Counter Overflow Flag 24 read-write 0 Receive frame counter did not overflow #0 1 Receive frame counter overflowed. #1 RFOF Receive FIFO Overflow Flag 16 read-write 0 No overflow occurred #0 1 Overflow occurred. #1 RMAF Multicast Address Frame Receive Flag 7 read-write 0 Multicast address frame not received #0 1 Multicast address frame received. #1 RRF Alignment Error Flag 4 read-write 0 Alignment error not detected #0 1 Alignment error detected. #1 RTLF Frame-Too-Long Error Flag 3 read-write 0 Frame-too-long error not detected #0 1 Frame-too-long error detected. #1 RTSF Frame-Too-Short Error Flag 2 read-write 0 Frame-too-short error not detected #0 1 Frame-too-short error detected. #1 TABT Transmit Abort Detect Flag 26 read-write 0 Frame transmission not aborted or no transmission requested. #0 1 Frame transmission aborted. #1 TC Frame Transfer Complete Flag 21 read-write 0 Transfer not complete or no transfer requested #0 1 All frames indicated in the transmit descriptor were completely transferred to the transmit FIFO. #1 TDE Transmit Descriptor Empty Flag 20 read-write 0 EDMAC detected that the transmit descriptor valid bit (TD0.TACT) is 1 #0 1 EDMAC detected that the transmit descriptor valid bit (TD0.TACT) is 0. #1 TFUF Transmit FIFO Underflow Flag 19 read-write 0 No underflow occurred #0 1 Underflow occurred. #1 TRO Transmit Retry Over Flag 8 read-write 0 Transmit retry-over condition not detected #0 1 Transmit retry-over condition detected. #1 TWB Write-Back Complete Flag 30 read-write 0 Write-back not complete or no transmission requested #0 1 Write-back to the transmit descriptor completed. #1 FCFTR Flow Control Start FIFO Threshold Setting Register 0x70 32 read-write n 0x0 0x0 RFDO Receive FIFO Data PAUSE Output Threshold 0 2 read-write RFFO Receive FIFO Frame PAUSE Output Threshold 16 2 read-write FDR FIFO Depth Register 0x50 32 read-write n 0x0 0x0 RFD Receive FIFO Depth 0 4 read-write Others settings prohibited. 0x0F 4096 bytes. 0x0f TFD Transmit FIFO Depth 8 4 read-write Others settings prohibited. 0x07 2048 bytes. 0x07 IOSR Independent Output Signal Setting Register 0x6C 32 read-write n 0x0 0x0 ELB External Loopback Mode 0 read-write 0 Output low on the ET0_EXOUT pin #0 1 Output high on the ET0_EXOUT pin. #1 RBWAR Receive Buffer Write Address Register 0xC8 32 read-only n 0x0 0x0 RDFAR Receive Descriptor Fetch Address Register 0xCC 32 read-only n 0x0 0x0 RDLAR Receive Descriptor List Start Address Register 0x20 32 read-write n 0x0 0x0 RFOCR Receive FIFO Overflow Counter 0x68 32 read-write n 0x0 0x0 OVER Receive FIFO Overflow Count 0 15 read-write RMCR Receive Method Control Register 0x58 32 read-write n 0x0 0x0 RNR Receive Request Reset 0 read-write 0 EDRRR.RR bit (receive request bit) is cleared to 0 when one frame is received #0 1 EDRRR.RR bit (receive request bit) is not cleared to 0 when one frame is received. #1 RMFCR Missed-Frame Counter Register 0x40 32 read-write n 0x0 0x0 MFC Missed-Frame Counter 0 15 read-write RPADIR Receive Data Padding Insert Register 0x78 32 read-write n 0x0 0x0 PADR Padding Slot 0 5 read-write PADS Padding Size 16 1 read-write Others settings prohibited 00 Do not insert padding #00 TBRAR Transmit Buffer Read Address Register 0xD4 32 read-only n 0x0 0x0 TDFAR Transmit Descriptor Fetch Address Register 0xD8 32 read-only n 0x0 0x0 TDLAR Transmit Descriptor List Start Address Register 0x18 32 read-write n 0x0 0x0 TFTR Transmit FIFO Threshold Register 0x48 32 read-write n 0x0 0x0 TFT Transmit FIFO Threshold 0 10 read-write Other The threshold is the set value multiplied by 4. 0x000 Store-and-forward mode 0x000 0x01 Setting prohibited 0x01 0x02 Setting prohibited 0x02 0x03 Setting prohibited 0x03 0x04 Setting prohibited 0x04 0x05 Setting prohibited 0x05 0x06 Setting prohibited 0x06 0x07 Setting prohibited 0x07 0x08 Setting prohibited 0x08 0x09 Setting prohibited 0x09 0x0a Setting prohibited 0x10 0x0b Setting prohibited 0x11 0x0c Setting prohibited 0x12 TFUCR Transmit FIFO Underflow Counter 0x64 32 read-write n 0x0 0x0 UNDER Transmit FIFO Underflow Count 0 15 read-write TRIMD Transmit Interrupt Setting Register 0x7C 32 read-write n 0x0 0x0 TIM Transmit Interrupt Mode 4 read-write 0 Select transmission complete interrupt mode, where an interrupt occurs when a frame is transmitted #0 1 Select write-back complete interrupt mode, where an interrupt occurs when write-back to the transmit descriptor is complete while the TWBI bit is 1. #1 TIS Transmit Interrupt Enable 0 read-write 0 Disable transmit interrupts #0 1 Enable transmit Interrupts. #1 TRSCER ETHERC/EDMAC Transmit/Receive Status Copy Enable Register 0x38 32 read-write n 0x0 0x0 RMAFCE RMAF Flag Copy Enable 7 read-write 0 Reflect the EESR.RMAF flag status in the RD0.RFE bit of the receive descriptor #0 1 Do not reflect the EESR.RMAF flag status in the RD0.RFE bit of the receive descriptor. #1 RRFCE RRF Flag Copy Enable 4 read-write 0 Reflect the EESR.RRF flag status in the RD0.RFE bit of the receive descriptor #0 1 Do not reflect the EESR.RRF flag status in the RD0.RFE bit of the receive descriptor. #1 ELC Event Link Controller ELC 0x0 0x0 0x1 registers n 0x10 0x4C registers n 0x2 0x4 registers n 0x74 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n ELCR Event Link Controller Register 0x0 8 read-write n 0x0 0x0 ELCON All Event Link Enable 7 read-write 0 Disable ELC function #0 1 Enable ELC function. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write ELCSARA Event Link Controller Security Attribution Register A 0x74 16 read-write n 0x0 0x0 ELCR Event Link Controller RegisterSecurity Attribution 2 read-write 0 Secure #0 1 NonSecure #1 ELSEGR0 Event Link Software Event Generation Register 0 Security Attribution 0 0 Secure #0 1 NonSecure #1 ELSEGR1 Event Link Software Event Generation Register 1Security Attribution 1 0 Secure #0 1 NonSecure #1 Reserved These bits are read as 1111111111111. The write value should be 1111111111111. 3 12 read-write ELCSARB Event Link Controller Security Attribution Register B 0x78 16 read-write n 0x0 0x0 ELSR0 Event Link Setting Register 0Security Attribution 0 0 Secure #0 1 NonSecure #1 ELSR1 Event Link Setting Register 1Security Attribution 1 0 Secure #0 1 NonSecure #1 ELSR10 Event Link Setting Register 10Security Attribution 10 0 Secure #0 1 NonSecure #1 ELSR11 Event Link Setting Register 11Security Attribution 11 0 Secure #0 1 NonSecure #1 ELSR12 Event Link Setting Register 12Security Attribution 12 0 Secure #0 1 NonSecure #1 ELSR13 Event Link Setting Register 13Security Attribution 13 0 Secure #0 1 NonSecure #1 ELSR14 Event Link Setting Register 14Security Attribution 14 0 Secure #0 1 NonSecure #1 ELSR15 Event Link Setting Register 15Security Attribution 15 read-write 0 Secure #0 1 NonSecure #1 ELSR2 Event Link Setting Register 2Security Attribution 2 0 Secure #0 1 NonSecure #1 ELSR3 Event Link Setting Register 3Security Attribution 3 0 Secure #0 1 NonSecure #1 ELSR4 Event Link Setting Register 4Security Attribution 4 0 Secure #0 1 NonSecure #1 ELSR5 Event Link Setting Register 5Security Attribution 5 0 Secure #0 1 NonSecure #1 ELSR6 Event Link Setting Register 6Security Attribution 6 0 Secure #0 1 NonSecure #1 ELSR7 Event Link Setting Register 7Security Attribution 7 0 Secure #0 1 NonSecure #1 ELSR8 Event Link Setting Register 8Security Attribution 8 0 Secure #0 1 NonSecure #1 ELSR9 Event Link Setting Register 9Security Attribution 9 0 Secure #0 1 NonSecure #1 ELCSARC Event Link Controller Security Attribution Register C 0x7C 16 read-write n 0x0 0x0 ELSR16 Event Link Setting Register 16Security Attribution 0 0 Secure #0 1 NonSecure #1 ELSR17 Event Link Setting Register 17Security Attribution 1 0 Secure #0 1 NonSecure #1 ELSR18 Event Link Setting Register 18Security Attribution 2 read-write 0 Secure #0 1 NonSecure #1 Reserved These bits are read as 1111111111111. The write value should be 1111111111111. 3 12 read-write ELSEGR0 Event Link Software Event Generation Register %s 0x2 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 1 4 read-write SEG Software Event Generation 0 write-only 0 Normal operation #0 1 Generate a software event #1 WE SEG Bit Write Enable 6 read-write 0 Disable writes to SEG bit #0 1 Enable writes to SEG bit #1 WI ELSEGR Register Write Disable 7 write-only 0 Enable writes to ELSEGR register #0 1 Disable writes to ELSEGR register. #1 ELSEGR1 Event Link Software Event Generation Register %s 0x4 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 1 4 read-write SEG Software Event Generation 0 write-only 0 Normal operation #0 1 Generate a software event #1 WE SEG Bit Write Enable 6 read-write 0 Disable writes to SEG bit #0 1 Enable writes to SEG bit #1 WI ELSEGR Register Write Disable 7 write-only 0 Enable writes to ELSEGR register #0 1 Disable writes to ELSEGR register. #1 ELSR0 Event Link Setting Register %s 0x10 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR1 Event Link Setting Register %s 0x14 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR10 Event Link Setting Register %s 0x38 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR11 Event Link Setting Register %s 0x3C 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR12 Event Link Setting Register %s 0x40 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR13 Event Link Setting Register %s 0x44 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR14 Event Link Setting Register %s 0x48 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR15 Event Link Setting Register %s 0x4C 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR16 Event Link Setting Register %s 0x50 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR17 Event Link Setting Register %s 0x54 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR18 Event Link Setting Register %s 0x58 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR2 Event Link Setting Register %s 0x18 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR3 Event Link Setting Register %s 0x1C 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR4 Event Link Setting Register %s 0x20 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR5 Event Link Setting Register %s 0x24 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR6 Event Link Setting Register %s 0x28 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR7 Event Link Setting Register %s 0x2C 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR8 Event Link Setting Register %s 0x30 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ELSR9 Event Link Setting Register %s 0x34 16 read-write n 0x0 0x0 ELS Event Link Select 0 8 read-write others Set the number for the event signal to be linked. 0x000 Event output to the corresponding peripheral module is disabled. 0x000 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write ETHERC0 Ethernet Controller Channel 0 ETHERC0 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x18 0x4 registers n 0x20 0x4 registers n 0x28 0x4 registers n 0x40 0x4 registers n 0x50 0xC registers n 0x60 0x8 registers n 0x6C 0x4 registers n 0x8 0x4 registers n 0xC0 0x4 registers n 0xC8 0x4 registers n 0xD0 0x10 registers n 0xE4 0x18 registers n APR Automatic PAUSE Frame Register 0x54 32 read-write n 0x0 0x0 AP Automatic PAUSE Time Setting 0 15 read-write BCFRR Broadcast Frame Receive Count Setting Register 0x6C 32 read-write n 0x0 0x0 BCF 0 15 read-write CDCR Late Collision Detect Counter Register 0xD4 32 read-write n 0x0 0x0 CDCR Late Collision Detect Counter 0 31 read-write CEFCR CRC Error Frame Receive Counter Register 0xE4 32 read-write n 0x0 0x0 CEFCR CRC Error Frame Receive Counter 0 31 read-write CNDCR Carrier Not Detect Counter Register 0xDC 32 read-write n 0x0 0x0 CNDCR Carrier Not Detect Counter 0 31 read-write ECMR ETHERC Mode Register 0x0 32 read-write n 0x0 0x0 DM Duplex Mode 1 read-write 0 Half-duplex mode #0 1 Full-duplex mode. #1 ILB Internal Loopback Mode 3 read-write 0 Perform normal data transmission or reception #0 1 Loop data back in the ETHERC when full-duplex mode is selected. #1 MPDE Magic Packet Detection Enable 9 read-write 0 Disable Magic Packet detection #0 1 Enable Magic Packet detection. #1 PFR PAUSE Frame Receive Mode 18 read-write 0 Do not transfer PAUSE frame to the EDMAC #0 1 Transfer PAUSE frame to the EDMAC. #1 PRCEF CRC Error Frame Receive Mode 12 read-write 0 Notify EDMAC of a CRC error #0 1 Do not notify EDMAC of a CRC error. #1 PRM Promiscuous Mode 0 read-write 0 Disable promiscuous mode #0 1 Enable promiscuous mode. #1 RE Reception Enable 6 read-write 0 Disable receive function #0 1 Enable receive function. #1 RTM Bit Rate 2 read-write 0 10 Mbps #0 1 100 Mbps. #1 RXF Receive Flow Control Operating Mode 17 read-write 0 Disable PAUSE frame detection #0 1 Enable PAUSE frame detection. #1 TE Transmission Enable 5 read-write 0 Disable transmit function #0 1 Enable transmit function. #1 TPC PAUSE Frame Transmit 20 read-write 0 Transmit PAUSE frame even during a PAUSE period #0 1 Do not transmit PAUSE frame during a PAUSE period. #1 TXF Transmit Flow Control Operating Mode 16 read-write 0 Disable automatic PAUSE frame transmission (PAUSE frame is not automatically transmitted) #0 1 Enable automatic PAUSE frame transmission (PAUSE frame is automatically transmitted as required). #1 ZPF 0 Time PAUSE Frame Enable 19 read-write 0 Do not use PAUSE frames that containing a pause_time parameter of 0 #0 1 Use PAUSE frames that containing a pause_time parameter of 0. #1 ECSIPR ETHERC Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 BFSIPR Continuous Broadcast Frame Reception Interrupt Enable 5 read-write 0 Disable interrupt notification #0 1 Enable interrupt notification. #1 ICDIP False Carrier Detect Interrupt Enable 0 read-write 0 Disable interrupt notification #0 1 Enable interrupt notification. #1 LCHNGIP LINK Signal Change Interrupt Enable 2 read-write 0 Disable interrupt notification #0 1 Enable interrupt notification. #1 MPDIP Magic Packet Detect Interrupt Enable 1 read-write 0 Disable interrupt notification #0 1 Enable interrupt notification. #1 PSRTOIP PAUSE Frame Retransmit Over Interrupt Enable 4 read-write 0 Disable interrupt notification #0 1 Enable interrupt notification. #1 ECSR ETHERC Status Register 0x10 32 read-write n 0x0 0x0 BFR Continuous Broadcast Frame Reception Flag 5 read-write 0 Continuous reception of broadcast frames not detected #0 1 Continuous reception of broadcast frames detected. #1 ICD False Carrier Detect Flag 0 read-write 0 PHY-LSI has not detected a false carrier on the line #0 1 PHY-LSI detected a false carrier on the line. #1 LCHNG Link Signal Change Flag 2 read-write 0 Change in the ET0_LINKSTA signal not detected #0 1 Change in the ET0_LINKSTA signal detected (high to low, or low to high). #1 MPD Magic Packet Detect Flag 1 read-write 0 Magic Packet not detected #0 1 Magic Packet detected. #1 PSRTO PAUSE Frame Retransmit Over Flag 4 read-write 0 PAUSE frame retransmit count has not reached the upper limit #0 1 PAUSE frame retransmit count reached the upper limit. #1 FRECR Frame Receive Error Counter Register 0xE8 32 read-write n 0x0 0x0 FRECR Frame Receive Error Counter 0 31 read-write IPGR Interpacket Gap Register 0x50 32 read-write n 0x0 0x0 IPG 0 4 read-write LCCR Lost Carrier Counter Register 0xD8 32 read-write n 0x0 0x0 LCCR Lost Carrier Counter 0 31 read-write MAFCR Multicast Address Frame Receive Counter Register 0xF8 32 read-write n 0x0 0x0 MAFCR Multicast Address Frame Receive Counter 0 31 read-write MAHR MAC Address Upper Bit Register 0xC0 32 read-write n 0x0 0x0 MAHR MAC Address Upper Bit 0 31 read-write MALR MAC Address Lower Bit Register 0xC8 32 read-write n 0x0 0x0 MALR MAC Address Lower Bit 0 15 read-write MPR Manual PAUSE Frame Register 0x58 32 read-write n 0x0 0x0 MP Manual PAUSE Time Setting 0 15 read-write PIR PHY Interface Register 0x20 32 read-write n 0x0 0x0 MDC MII/RMII Management Data Clock 0 read-write MDI MII/RMII Management Data-In 3 read-only MDO MII/RMII Management Data-Out 2 read-write MMD MII/RMII Management Mode 1 read-write 0 Read #0 1 Write. #1 PSR PHY Status Register 0x28 32 read-only n 0x0 0x0 LMON ET0_LINKSTA Pin Status Flag 0 read-only RDMLR Random Number Generation Counter Upper Limit Setting Register 0x40 32 read-write n 0x0 0x0 RMD Random Number Generation Counter 0 19 read-write RFCF Received PAUSE Frame Counter 0x60 32 read-only n 0x0 0x0 RPAUSE Received PAUSE Frame Count 0 7 read-only RFCR Received Alignment Error Frame Counter Register 0xF4 32 read-write n 0x0 0x0 RFCR Received Alignment Error Frame Counter 0 31 read-write RFLR Receive Frame Maximum Length Register 0x8 32 read-write n 0x0 0x0 RFL Receive Frame Maximum Length 0 11 read-write TLFRCR Too-Long Frame Receive Counter Register 0xF0 32 read-write n 0x0 0x0 TLFRCR Too-Long Frame Receive Counter 0 31 read-write TPAUSECR PAUSE Frame Retransmit Counter RFCF 0x60 32 read-only n 0x0 0x0 TXP PAUSE Frame Retransmit Count 0 7 read-only TPAUSER PAUSE Frame Retransmit Count Setting Register 0x64 32 read-write n 0x0 0x0 TPAUSE 0 15 read-write TROCR Transmit Retry Over Counter Register 0xD0 32 read-write n 0x0 0x0 TROCR Transmit Retry Over Counter 0 31 read-write TSFRCR Too-Short Frame Receive Counter Register 0xEC 32 read-write n 0x0 0x0 TSFRCR Too-Short Frame Receive Counter 0 31 read-write FACI Flash/CPU Interface FACI 0x0 0x10 0x1 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x30 0x8 registers n 0x44 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n 0x80 0x6 registers n 0x8C 0x2 registers n 0xA0 0x2 registers n 0xD0 0x1 registers n 0xD4 0x1 registers n 0xD8 0xA registers n 0xE4 0x2 registers n 0xE8 0x2 registers n FAEINT Flash Access Error Interrupt Enable Register 0x14 8 read-write n 0x0 0x0 CFAEIE Code Flash Memory Access Violation Interrupt Enable 7 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CFAE is set to 1. #1 CMDLKIE Command Lock Interrupt Enable 4 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.CMDLK is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.CMDLK is set to 1. #1 DFAEIE Data Flash Memory Access Violation Interrupt Enable 3 read-write 0 Generation of an FIFERR interrupt request is disabled when FASTAT.DFAE is set to 1 #0 1 Generation of an FIFERR interrupt request is enabled when FASTAT.DFAE is set to 1. #1 FASTAT Flash Access Status Register 0x10 8 read-write n 0x0 0x0 CFAE Code Flash Memory Access Violation Flag 7 read-write 0 No code flash memory access violation has occurred #0 1 A code flash memory access violation has occurred. #1 CMDLK Command Lock Flag 4 read-only 0 The flash sequencer is not in the command-locked state #0 1 The flash sequencer is in the command-locked state. #1 DFAE Data Flash Memory Access Violation Flag 3 read-write 0 No data flash memory access violation has occurred #0 1 A data flash memory access violation has occurred. #1 FBCCNT Blank Check Control Register 0xD0 8 read-write n 0x0 0x0 BCDIR Blank Check Direction 0 read-write 0 Blank checking is executed from the lower addresses to the higher addresses (incremental mode) #0 1 Blank checking is executed from the higher addresses to the lower addresses (decremental mode). #1 FBCSTAT Blank Check Status Register 0xD4 8 read-write n 0x0 0x0 BCST Blank Check Status Flag 0 read-only 0 The target area is in the non-programmed state, that is, the area has been erased but has not yet been reprogrammed #0 1 The target area has been programmed with 0s or 1s. #1 FBPROT0 Flash Block Protection Register 0x78 16 read-write n 0x0 0x0 BPCN0 Block Protection for Non-secure Cancel 0 read-write 0 User area is protected #0 1 User area is not protected. #1 KEY Key Code 8 7 read-write FBPROT1 Flash Block Protection for Secure Register 0x7C 16 read-write n 0x0 0x0 BPCN1 Block Protection for Secure Cancel 0 read-write 0 Block protection is protected #0 1 Block protection is not protected. #1 KEY Key Code 8 7 read-write FCMDR FACI Command Register 0xA0 16 read-only n 0x0 0x0 CMDR Command Flag 8 7 read-only PCMDR Pre-command Flag 0 7 read-only FCPSR Flash Sequencer Processing Switching Register 0xE0 16 read-write n 0x0 0x0 ESUSPMD Erasure Suspend Mode 0 read-write 0 Suspension priority mode #0 1 Erasure priority mode. #1 FEADDR FACI Command End Address Register 0x34 32 read-write n 0x0 0x0 FEADDR End Address for FACI Command Processing 0 31 read-write FENTRYR Flash P/E Mode Entry Register 0x84 16 read-write n 0x0 0x0 FENTRYC Code Flash P/E Mode Entry 0 read-write 0 Code flash is in read mode #0 1 Code flash is in P/E mode. #1 FENTRYD Data Flash P/E Mode Entry 7 read-write 0 Data flash is in read mode #0 1 Data flash is in P/E mode. #1 KEY Key Code 8 7 read-write FMEPROT Flash P/E Mode Entry Protection Register 0x44 16 read-write n 0x0 0x0 CEPROT Code Flash P/E Mode Entry Protection 0 read-write 0 FENTRYC bit is not protected #0 1 FENTRYC bit is protected. #1 KEY Key Code 8 7 read-write FPCKAR Flash Sequencer Processing Clock Notification Register 0xE4 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write PCKA Flash Sequencer Operating Clock Notification 0 7 read-write FPSADDR Data Flash Programming Start Address Register 0xD8 32 read-write n 0x0 0x0 PSADR Programmed Area Start Address 0 16 read-only FRDYIE Flash Ready Interrupt Enable Register 0x18 8 read-write n 0x0 0x0 FRDYIE Flash Ready Interrupt Enable 0 read-write 0 Generation of an FRDY interrupt request is disabled #0 1 Generation of an FRDY interrupt request is enabled. #1 FSADDR FACI Command Start Address Register 0x30 32 read-write n 0x0 0x0 FSTATR Flash Status Register 0x80 32 read-write n 0x0 0x0 DBFULL Data Buffer Full Flag 10 read-only 0 The data buffer is empty #0 1 The data buffer is full. #1 ERSERR Erasure Error Flag 13 read-only 0 Erasure has completed successfully #0 1 An error has occurred during erasure. #1 ERSSPD Erasure Suspend Status Flag 9 read-only 0 The flash sequencer is in a state other than those corresponding to the value 1 #0 1 The flash sequencer is in the erasure suspension processing state or the erasure suspended state. #1 FESETERR FENTRY Setting Error 22 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 FLWEERR Flash Write/Erase Protect Error Flag 6 read-only 0 An error has not occurred #0 1 An error has occurred. #1 FRDY Flash Ready Flag 15 read-only 0 Program, block erase, multi block erase, P/E suspend, P/E resume, Forced Stop, Blank Check, or configuration set command processing is in progress #0 1 None of the above is in progress. #1 ILGCOMERR Illegal Command Error 23 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 ILGLERR Illegal Command Error Flag 14 read-only 0 The flash sequencer has not detected an illegal FACI command or illegal flash memory access #0 1 The flash sequencer has detected an illegal FACI command or illegal flash memory access. #1 OTERR Other Error 20 read-only 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 PRGERR Programming Error Flag 12 read-only 0 Programming has completed successfully #0 1 An error has occurred during programming. #1 PRGSPD Programming Suspend Status Flag 8 read-only 0 The flash sequencer is in a state other than those corresponding to the value 1 #0 1 The flash sequencer is in the programming suspension processing state or programming suspended state. #1 SECERR Security Error 21 read-write 0 A status clear or forced stop command processing is complete #0 1 An error has occurred. #1 SUSRDY Suspend Ready Flag 11 read-only 0 The flash sequencer cannot receive P/E suspend commands #0 1 The flash sequencer can receive P/E suspend commands. #1 FSUACR Flash Startup Area Control Register 0xE8 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write SAS Startup Area Select 0 1 read-write 00 Startup area is selected by BTFLG bit #00 10 Startup area is temporarily switched to the default area (block 0) #10 11 Startup area is temporarily switched to the alternate area (block 1). #11 FSUASMON Flash Startup Area Select Monitor Register 0xDC 32 read-only n 0x0 0x0 BTFLG Flag of Startup Area Select for Boot Swap 31 read-only 0 The startup area is the alternate block (block 1) #0 1 The startup area is the default block (block 0). #1 FSPR Protection Programming Flag to set Boot Flag and Startup Area Control 15 read-only 0 Protected state #0 1 Non-protected state. #1 FSUINITR Flash Sequencer Setup Initialization Register 0x8C 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write SUINIT Set-Up Initialization 0 read-write 0 The FSADDR, FEADDR, FBPROT0, FBPROT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers keep their current values #0 1 The FSADDR, FEADDR, FBPROT0, FBRPOT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers are initialized. #1 FCACHE Flash Cache FCACHE 0x0 0x100 0x2 registers n 0x104 0x2 registers n 0x11C 0x1 registers n 0x140 0x2 registers n FCACHEE Flash Cache Enable Register 0x100 16 read-write n 0x0 0x0 FCACHEEN Flash Cache Enable 0 read-write 0 FCACHE is disabled #0 1 FCACHE is enabled #1 FCACHEIV Flash Cache Invalidate Register 0x104 16 read-write n 0x0 0x0 FCACHEIV Flash Cache Invalidate 0 read-write 0 Read: Do not invalidate. Write: The setting is ignored. #0 1 Invalidate FCACHE is invalidated. #1 FLWT Flash Wait Cycle Register 0x11C 8 read-write n 0x0 0x0 FLWT Flash Wait Cycle 0 2 read-write Others Setting prohibited 000 0 wait (product dependent) #000 001 1 wait (product dependent) #001 010 2 wait (product dependent) #010 011 3 wait (product dependent) #011 100 4 wait (product dependent) #100 101 5 wait (product dependent) #101 FSAR Flash Security Attribution Register 0x140 16 read-write n 0x0 0x0 FCKMHZSA FCKMHZSA Security Attribution 8 read-write 0 Secure #0 1 Non-Secure #1 FLWTSA FLWT Security Attribution 0 read-write 0 Secure #0 1 Non-Secure #1 FLAD Data Flash FLAD 0x0 0x40 0x1 registers n FCKMHZ Data Flash Access Frequency Register 0x40 8 read-write n 0x0 0x0 FCKMHZ Data Flash Access Frequency Register 0 7 read-write GPT164 General PWM 16-bit Timer 4 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT165 General PWM 16-bit Timer 5 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT166 General PWM 16-bit Timer 6 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT167 General PWM 16-bit Timer 7 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT168 General PWM 16-bit Timer 8 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT169 General PWM 16-bit Timer 9 GPT164 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT320 General PWM 32-bit Timer 0 GPT320 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT321 General PWM 32-bit Timer 1 GPT320 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT322 General PWM 32-bit Timer 2 GPT320 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT323 General PWM 32-bit Timer 3 GPT320 0x0 0x0 0x44 registers n 0x48 0x24 registers n 0x88 0x8 registers n 0xB8 0x8 registers n 0xD0 0x8 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD0 GTCCR Buffer Operation Disable 0 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 BD1 GTPR Buffer Operation Disable 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write Others Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD) 00 No buffer operation #00 01 Single buffer operation (GTCCRA <---->GTCCRC) #01 CCRB GTCCRB Buffer Operation 18 1 read-write Others Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF) 00 No buffer operation #00 01 Single buffer operation (GTCCRB <----> GTCCRE) #01 CCRSWT GTCCRA and GTCCRB Forcible Buffer Operation 22 read-write PR GTPR Buffer Operation 20 1 read-write Others Setting prohibited 00 No buffer operation #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel n GTCNT Count Clear (n : the same as bit position value) 0 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR1 Channel n GTCNT Count Clear (n : the same as bit position value) 1 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR2 Channel n GTCNT Count Clear (n : the same as bit position value) 2 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR3 Channel n GTCNT Count Clear (n : the same as bit position value) 3 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR4 Channel n GTCNT Count Clear (n : the same as bit position value) 4 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR5 Channel n GTCNT Count Clear (n : the same as bit position value) 5 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR6 Channel n GTCNT Count Clear (n : the same as bit position value) 6 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR7 Channel n GTCNT Count Clear (n : the same as bit position value) 7 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR8 Channel n GTCNT Count Clear (n : the same as bit position value) 8 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 CCLR9 Channel n GTCNT Count Clear (n : the same as bit position value) 9 write-only 0 GTCNT counter is not cleared #0 1 GTCNT counter is cleared #1 GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation) #110 111 Setting prohibited #111 TPCS Timer Prescaler Select 23 3 read-write 0x0 PCLKGPT/1 0x0 0x1 PCLKGPT/2 0x1 0x2 PCLKGPT/4 0x2 0x3 PCLKGPT/8 0x3 0x4 PCLKGPT/16 0x4 0x5 PCLKGPT/32 0x5 0x6 PCLKGPT/64 0x6 0x7 Setting prohibited 0x7 0x8 PCLKGPT/256 0x8 0x9 Setting prohibited 0x9 0xA PCLKGPT/1024 0xa 0xB Setting prohibited 0xb 0xC GTETRGA (Via the POEG) 0xc 0xD GTETRGB (Via the POEG) 0xd 0xE GTETRGC (Via the POEG) 0xe 0xF GTETRGD (Via the POEG)POEG接続数に応じた、GTETRGA-D表示制御必要。 0xf GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear disabled by the GTCLR register #0 1 Counter clear enabled by the GTCLR register #1 CSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 11 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 9 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 CSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 CSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 15 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 CSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 13 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 CSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear disabled at the ELC_GPTA input #0 1 Counter clear enabled at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear disabled at the ELC_GPTB input #0 1 Counter clear enabled at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear disabled at the ELC_GPTC input #0 1 Counter clear enabled at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear disabled at the ELC_GPTD input #0 1 Counter clear enabled at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear disabled at the ELC_GPTE input #0 1 Counter clear enabled at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear disabled at the ELC_GPTF input #0 1 Counter clear enabled at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear disabled at the ELC_GPTG input #0 1 Counter clear enabled at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear disabled at the ELC_GPTH input #0 1 Counter clear enabled at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear disabled on the falling edge of GTETRGA input #0 1 Counter clear enabled on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear disabled on the rising edge of GTETRGA input #0 1 Counter clear enabled on the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear disabled on the falling edge of GTETRGB input #0 1 Counter clear enabled on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 read-write 0 Counter clear disabled on the falling edge of GTETRGC input #0 1 Counter clear enabled on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 read-write 0 Counter clear disabled on the falling edge of GTETRGD input #0 1 Counter clear enabled on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 DSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 DSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 DSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 DSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down disabled at the ELC_GPTA input #0 1 Counter count down enabled at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down disabled at the ELC_GPTB input #0 1 Counter count down enabled at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down disabled at the ELC_GPTC input #0 1 Counter count down enabled at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down disabled at the ELC_GPTD input #0 1 Counter count down enabled at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down disabled at the ELC_GPTE input #0 1 Counter count down enabled at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down disabled at the ELC_GPTG input #0 1 Counter count down enabled at the ELC_GPTG input #1 DSELCH ELC_GPTF Event Source Counter Count Down Enable 23 read-write 0 Counter count down disabled at the ELC_GPTF input #0 1 Counter count down enabled at the ELC_GPTF input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down disabled on the falling edge of GTETRGA input #0 1 Counter count down enabled on the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down disabled on the rising edge of GTETRGA input #0 1 Counter count down enabled on the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down disabled on the falling edge of GTETRGB input #0 1 Counter count down enabled on the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down disabled on the rising edge of GTETRGB input #0 1 Counter count down enabled on the rising edge of GTETRGB input #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 read-write 0 Counter count down disabled on the falling edge of GTETRGC input #0 1 Counter count down enabled on the falling edge of GTETRGC input #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 read-write 0 Counter count down disabled on the rising edge of GTETRGC input #0 1 Counter count down enabled on the rising edge of GTETRGC input #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 read-write 0 Counter count down disabled on the falling edge of GTETRGD input #0 1 Counter count down enabled on the falling edge of GTETRGD input #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 read-write 0 Counter count down disabled on the rising edge of GTETRGD input #0 1 Counter count down enabled on the rising edge of GTETRGD input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU #0 1 GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 ASCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 ASCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 ASCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 ASCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture disabled at the ELC_GPTA input #0 1 GTCCRA input capture enabled at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture disabled at the ELC_GPTB input #0 1 GTCCRA input capture enabled at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture disabled at the ELC_GPTC input #0 1 GTCCRA input capture enabled at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture disabled at the ELC_GPTD input #0 1 GTCCRA input capture enabled at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture disabled at the ELC_GPTE input #0 1 GTCCRA input capture enabled at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture disabled at the ELC_GPTF input #0 1 GTCCRA input capture enabled at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture disabled at the ELC_GPTG input #0 1 GTCCRA input capture enabled at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture disabled at the ELC_GPTH input #0 1 GTCCRA input capture enabled at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGB input #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGC input #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 read-write 0 GTCCRA input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRA input capture enabled on the falling edge of GTETRGD input #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 read-write 0 GTCCRA input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRA input capture enabled on the rising edge of GTETRGD input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 BSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 BSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 BSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture disabled at the ELC_GPTA input #0 1 GTCCRB input capture enabled at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture disabled at the ELC_GPTB input #0 1 GTCCRB input capture enabled at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture disabled at the ELC_GPTC input #0 1 GTCCRB input capture enabled at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture disabled at the ELC_GPTD input #0 1 GTCCRB input capture enabled at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture disabled at the ELC_GPTE input #0 1 GTCCRB input capture enabled at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture disabled at the ELC_GPTF input #0 1 GTCCRB input capture enabled at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture disabled at the ELC_GPTG input #0 1 GTCCRB input capture enabled at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture disabled at the ELC_GPTH input #0 1 GTCCRB input capture enabled at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGA input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGA input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGB input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGB input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGB input #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGC input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGC input #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGC input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGC input #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 read-write 0 GTCCRB input capture disabled on the falling edge of GTETRGD input #0 1 GTCCRB input capture enabled on the falling edge of GTETRGD input #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 read-write 0 GTCCRB input capture disabled on the rising edge of GTETRGD input #0 1 GTCCRB input capture enabled on the rising edge of GTETRGD input #1 GTICLF General PWM Timer Inter Channel Logical Operation Function Setting Register 0xB8 32 read-write n 0x0 0x0 ICLFA GTIOCnA Output Logical Operation Function Select 0 2 read-write 000 A (no delay) #000 001 NOT A (no delay) #001 010 C (1PCLKGPT delay) #010 011 NOT C (1PCLKGPT delay) #011 100 A AND C (1PCLKGPT delay) #100 101 A OR C (1PCLKGPT delay) #101 110 A EXOR C (1PCLKGPT delay) #110 111 A NOR C (1PCLKGPT delay) #111 ICLFB GTIOCnB Output Logical Operation Function Select 16 2 read-write 000 B (no delay) #000 001 NOT B (no delay) #001 010 D (1PCLKGPT delay) #010 011 NOT D (1PCLKGPT delay) #011 100 B AND D (1PCLKGPT delay) #100 101 B OR D (1PCLKGPTn delay) #101 110 B EXOR D (1PCLKGPT delay) #110 111 B NOR D (1PCLKGPT delay) #111 ICLFSELC Inter Channel Signal C Select 4 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 ICLFSELD Inter Channel Signal D Select 20 5 read-write Others Setting prohibited 0x00 GTIOC0A 0x00 0x01 GTIOC0B 0x01 0x02 GTIOC1A 0x02 0x03 GTIOC1B 0x03 0x04 GTIOC2A 0x04 0x05 GTIOC2B 0x05 0x06 GTIOC3A 0x06 0x07 GTIOC3B 0x07 0x08 GTIOC4A 0x08 0x09 GTIOC4B 0x09 0x0A GTIOC5A 0x0a 0x0B GTIOC5B 0x0b 0x0C GTIOC6A 0x0c 0x0D GTIOC6B 0x0d 0x0E GTIOC7A 0x0e 0x0F GTIOC7B 0x0f 0x10 GTIOC8A 0x10 0x11 GTIOC8B 0x11 0x12 GTIOC9A 0x12 0x13 GTIOC9B 0x13 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write 00 Group A output disable request is selected #00 01 Group B output disable request is selected #01 10 Group C output disable request is selected #10 11 Group D output disable request is selected #11 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request disabled #0 1 Same time output level high disable request enabled #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request disabled #0 1 Same time output level low disable request enabled #1 GTINTPC Period Count Function Finish Interrupt Enable 31 read-write 0 Interrupt request is disabled #0 1 Interrupt request is enabled #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCnA Pin Function Select 0 4 read-write GTIOB GTIOCnB Pin Function Select 16 4 read-write NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCnA pin is disabled #0 1 The noise filter for the GTIOCnA pin is enabled #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for theGTIOCnB pin is disabled #0 1 The noise filter for the GTIOCnB pin is enabled #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 OADF GTIOCnA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited #00 01 GTIOCnA pin is set to Hi-Z on output disable #01 10 GTIOCnA pin is set to 0 on output disable #10 11 GTIOCnA pin is set to 1 on output disable #11 OADFLT GTIOCnA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCnA pin outputs low when counting stops #0 1 The GTIOCnA pin outputs high when counting stops #1 OAE GTIOCnA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCnA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCnA pin output level at the start or stop of counting depends on the register setting #0 1 The GTIOCnA pin output level is retained at the start or stop of counting #1 OBDF GTIOCnB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited #00 01 GTIOCnB pin is set to Hi-Z on output disable #01 10 GTIOCnB pin is set to 0 on output disable #10 11 GTIOCnB pin is set to 1 on output disable #11 OBDFLT GTIOCnB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCnB pin outputs low when counting stops #0 1 The GTIOCnB pin outputs high when counting stops #1 OBE GTIOCnB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCnB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCnB pin output level at the start/stop of counting depends on the register setting #0 1 The GTIOCnB pin output level is retained at the start/stop of counting #1 GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPC General PWM Timer Period Count Register 0xBC 32 read-write n 0x0 0x0 ASTP Automatic Stop Function Enable 8 read-write 0 Automatic stop function is disabled #0 1 Automatic stop function is enabled #1 PCEN Period Count Function Enable 0 read-write 0 Period count function is disabled #0 1 Period count function is enabled #1 PCNT Period Counter 16 11 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop disabled by the GTSTP register #0 1 Counter stop enabled by the GTSTP register #1 PSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 11 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 9 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 PSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 PSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 15 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 13 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop disabled at the ELC_GPTA input #0 1 Counter stop enabled at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop disabled at the ELC_GPTB input #0 1 Counter stop enabled at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop disabled at the ELC_GPTC input #0 1 Counter stop enabled at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop disabled at the ELC_GPTD input #0 1 Counter stop enabled at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop disabled at the ELC_GPTE input #0 1 Counter stop enabled at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop disabled at the ELC_GPTF input #0 1 Counter stop enabled at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop disabled at the ELC_GPTG input #0 1 Counter stop enabled at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop disabled at the ELC_GPTH input #0 1 Counter stop enabled at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop disabled on the falling edge of GTETRGA input #0 1 Counter stop enabled on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop disabled on the rising edge of GTETRGA input #0 1 Counter stop enabled on the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop disabled on the falling edge of GTETRGB input #0 1 Counter stop enabled on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop disabled on the rising edge of GTETRGB input #0 1 Counter stop enabled on the rising edge of GTETRGB input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 read-write 0 Counter stop disabled on the falling edge of GTETRGC input #0 1 Counter stop enabled on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 read-write 0 Counter stop disabled on the rising edge of GTETRGC input #0 1 Counter stop enabled on the rising edge of GTETRGC input #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 read-write 0 Counter stop disabled on the falling edge of GTETRGD input #0 1 Counter stop enabled on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 read-write 0 Counter stop disabled on the rising edge of GTETRGD input #0 1 Counter stop enabled on the rising edge of GTETRGD input #1 GTSECR General PWM Timer Operation Enable Bit Simultaneous Control Register 0xD4 32 read-write n 0x0 0x0 SBDCD GTCCR Register Buffer Operation Simultaneous Disable 8 read-write 0 Disable simultaneous disabling GTCCR buffer operations #0 1 Disable GTCCR register buffer operations simultaneously #1 SBDCE GTCCR Register Buffer Operation Simultaneous Enable 0 read-write 0 Disable simultaneous enabling GTCCR buffer operations #0 1 Enable GTCCR register buffer operations simultaneously #1 SBDPD GTPR Register Buffer Operation Simultaneous Disable 9 read-write 0 Disable simultaneous disabling GTPR buffer operations #0 1 Disable GTPR register buffer operations simultaneously #1 SBDPE GTPR Register Buffer Operation Simultaneous Enable 1 read-write 0 Disable simultaneous enabling GTPR buffer operations #0 1 Enable GTPR register buffer operations simultaneously #1 SPCD Period Count Function Simultaneous Disable 24 read-write 0 Disable simultaneous disabling period count function #0 1 Disable period count function simultaneously #1 SPCE Period Count Function Simultaneous Enable 16 read-write 0 Disable simultaneous enabling period count function #0 1 Enable period count function simultaneously #1 GTSECSR General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register 0xD0 32 read-write n 0x0 0x0 SECSEL0 Channel 0 Operation Enable Bit Simultaneous Control Channel Select 0 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL1 Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL2 Channel 2 Operation Enable Bit Simultaneous Control Channel Select 2 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL3 Channel 3 Operation Enable Bit Simultaneous Control Channel Select 3 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL4 Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL5 Channel 5 Operation Enable Bit Simultaneous Control Channel Select 5 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL6 Channel 6 Operation Enable Bit Simultaneous Control Channel Select 6 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL7 Channel 7 Operation Enable Bit Simultaneous Control Channel Select 7 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL8 Channel 8 Operation Enable Bit Simultaneous Control Channel Select 8 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 SECSEL9 Channel 9 Operation Enable Bit Simultaneous Control Channel Select 9 read-write 0 Disable simultaneous control #0 1 Enable simultaneous control #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start disabled by the GTSTR register #0 1 Counter start enabled by the GTSTR register #1 SSCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 11 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 10 read-write 0 Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 9 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 SSCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 8 read-write 0 Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 SSCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 15 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 14 read-write 0 Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 SSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 13 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 SSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 12 read-write 0 Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start disabled at the ELC_GPTA input #0 1 Counter start enabled at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start disabled at the ELC_GPTB input #0 1 Counter start enabled at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start disabled at the ELC_GPTC input #0 1 Counter start enabled at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start disabled at the ELC_GPTD input #0 1 Counter start enabled at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start disabled at the ELC_GPTE input #0 1 Counter start enabled at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start disabled at the ELC_GPTF input #0 1 Counter start enabled at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start disabled at the ELC_GPTG input #0 1 Counter start enabled at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start disabled at the ELC_GPTH input #0 1 Counter start enabled at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start disabled on the falling edge of GTETRGA input #0 1 Counter start enabled on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start disabled on the rising edge of GTETRGA input #0 1 Counter start enabled on the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start disabled on the falling edge of GTETRGB input #0 1 Counter start enabled on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start disabled on the rising edge of GTETRGB input #0 1 Counter start enabled on the rising edge of GTETRGB input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 read-write 0 Counter start disabled on the falling edge of GTETRGC input #0 1 Counter start enabled on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 read-write 0 Counter start disabled on the rising edge of GTETRGC input #0 1 Counter start enabled on the rising edge of GTETRGC input #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 read-write 0 Counter start disabled on the falling edge of GTETRGD input #0 1 Counter start enabled on the falling edge of GTETRGD input #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 read-write 0 Counter start disabled on the rising edge of GTETRGD input #0 1 Counter start enabled on the rising edge of GTETRGD input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Flag 29 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 1 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 1 at the same time #1 OABLF Same Time Output Level Low Flag 30 read-only 0 GTIOCnA pin and GTIOCnB pin do not output 0 at the same time #0 1 GTIOCnA pin and GTIOCnB pin output 0 at the same time #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated #0 1 An output disable request is generated #1 PCF Period Count Function Finish Flag 31 read-write 0 No period count function finish has occurred #0 1 A period count function finish has occurred #1 TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated #0 1 An input capture/compare match of GTCCRA is generated #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated #0 1 An input capture/compare match of GTCCRB is generated #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated #0 1 A compare match of GTCCRC is generated #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated #0 1 A compare match of GTCCRD is generated #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated #0 1 A compare match of GTCCRE is generated #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated #0 1 A compare match of GTCCRF is generated #1 TCFPO Overflow Flag 6 read-write 0 No overflow (crest) occurred #0 1 An overflow (crest) occurred #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) occurred #0 1 An underflow (trough) occurred #1 TUCF Count Direction Flag 15 read-only 0 GTCNT counter counts downward #0 1 GTCNT counter counts upward #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel n GTCNT Count Stop (n : the same as bit position value) 0 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP1 Channel n GTCNT Count Stop (n : the same as bit position value) 1 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP2 Channel n GTCNT Count Stop (n : the same as bit position value) 2 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP3 Channel n GTCNT Count Stop (n : the same as bit position value) 3 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP4 Channel n GTCNT Count Stop (n : the same as bit position value) 4 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP5 Channel n GTCNT Count Stop (n : the same as bit position value) 5 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP6 Channel n GTCNT Count Stop (n : the same as bit position value) 6 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP7 Channel n GTCNT Count Stop (n : the same as bit position value) 7 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP8 Channel n GTCNT Count Stop (n : the same as bit position value) 8 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 CSTOP9 Channel n GTCNT Count Stop (n : the same as bit position value) 9 read-write 0 GTCNT counter not stop #0 1 GTCNT counter stop #1 GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel n GTCNT Count Start (n : the same as bit position value) 0 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT1 Channel n GTCNT Count Start (n : the same as bit position value) 1 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT2 Channel n GTCNT Count Start (n : the same as bit position value) 2 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT3 Channel n GTCNT Count Start (n : the same as bit position value) 3 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT4 Channel n GTCNT Count Start (n : the same as bit position value) 4 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT5 Channel n GTCNT Count Start (n : the same as bit position value) 5 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT6 Channel n GTCNT Count Start (n : the same as bit position value) 6 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT7 Channel n GTCNT Count Start (n : the same as bit position value) 7 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT8 Channel n GTCNT Count Start (n : the same as bit position value) 8 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 CSTRT9 Channel n GTCNT Count Start (n : the same as bit position value) 9 read-write 0 GTCNT counter not start #0 1 GTCNT counter start #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCnA Output Duty Setting 16 1 read-write 00 GTIOCnA pin duty depends on the compare match #00 01 GTIOCnA pin duty depends on the compare match #01 10 GTIOCnA pin duty 0% #10 11 GTIOCnA pin duty 100% #11 OADTYF Forcible GTIOCnA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 19 read-write 0 Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting #1 OBDTY GTIOCnB Output Duty Setting 24 1 read-write 00 GTIOCnB pin duty depends on the compare match #00 01 GTIOCnB pin duty depends on the compare match #01 10 GTIOCnB pin duty 0% #10 11 GTIOCnB pin duty 100% #11 OBDTYF Forcible GTIOCnB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 27 read-write 0 Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting #1 UD Count Direction Setting 0 read-write 0 GTCNT counts down #0 1 GTCNT counts up #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 #1 USCAFBL GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 #1 USCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 #1 USCARBL GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 #1 USCBFAH GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBFAL GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 #1 USCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 #1 USCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #0 1 Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up disabled at the ELC_GPTA input #0 1 Counter count up enabled at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up disabled at the ELC_GPTB input #0 1 Counter count up enabled at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up disabled at the ELC_GPTC input #0 1 Counter count up enabled at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up disabled at the ELC_GPTD input #0 1 Counter count up enabled at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up disabled at the ELC_GPTE input #0 1 Counter count up enabled at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up disabled at the ELC_GPTF input #0 1 Counter count up enabled at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up disabled at the ELC_GPTG input #0 1 Counter count up enabled at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up disabled at the ELC_GPTH input #0 1 Counter count up enabled at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up disabled on the falling edge of GTETRGA input #0 1 Counter count up enabled on the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up disabled on the rising edge of GTETRGA input #0 1 Counter count up enabled on the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up disabled on the falling edge of GTETRGB input #0 1 Counter count up enabled on the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up disabled on the rising edge of GTETRGB input #0 1 Counter count up enabled on the rising edge of GTETRGB input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 read-write 0 Counter count up disabled on the falling edge of GTETRGC input #0 1 Counter count up enabled on the falling edge of GTETRGC input #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 read-write 0 Counter count up disabled on the rising edge of GTETRGC input #0 1 Counter count up enabled on the rising edge of GTETRGC input #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 read-write 0 Counter count up disabled on the falling edge of GTETRGD input #0 1 Counter count up enabled on the falling edge of GTETRGD input #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 read-write 0 Counter count up disabled on the rising edge of GTETRGD input #0 1 Counter count up enabled on the rising edge of GTETRGD input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 CLRWP GTCLR.CCLR Bit Write Disable 3 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 CMNWP Common Register Write Disabled 4 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 PRKEY GTWP Key Code 8 7 read-write STPWP GTSTP.CSTOP Bit Write Disable 2 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 STRWP GTSTR.CSTRT Bit Write Disable 1 read-write 0 Write to the bit is enabled #0 1 Write to the bit is disabled #1 WP Register Write Disable 0 read-write 0 Write to the register enabled #0 1 Write to the register disabled #1 GPT_OPS Output Phase Switching Controller GPT_OPS 0x0 0x0 0x4 registers n OPSCR Output Phase Switching Control Register 0x0 32 read-write n 0x0 0x0 ALIGN Input Phase Alignment 21 read-write 0 Input phase aligned to PCLKGPT #0 1 Input phase aligned to PWM #1 EN Enable-Phase Output Control 8 read-write 0 Do not output (Hi-Z external pin) #0 1 Output #1 FB External Feedback Signal Enable 16 read-write 0 Select the external input #0 1 Select the soft setting (OPSCR.UF, VF, WF) #1 GODF Group Output Disable Function 26 read-write 0 This bit function is ignored #0 1 Group disable clears the OPSCR.EN bit #1 GRP Output Disabled Source Selection 24 1 read-write INV Invert-Phase Output Control 19 read-write 0 Positive logic (active-high) output #0 1 Negative logic (active-low) output #1 N Negative-Phase Output (N) Control 18 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT320) #1 NFCS External Input Noise Filter Clock Selection 30 1 read-write 00 PCLKGPT/1 #00 01 PCLKGPT/4 #01 10 PCLKGPT/16 #10 11 PCLKGPT/64 #11 NFEN External Input Noise Filter Enable 29 read-write 0 Do not use a noise filter on the external input #0 1 Use a noise filter on the external input #1 P Positive-Phase Output (P) Control 17 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT320) #1 RV Output Phase Rotation Direction Reversal Control 20 read-write 0 Positive rotation #0 1 Reverse rotation #1 U Input U-Phase Monitor 4 read-only UF 0 read-write V Input V-Phase Monitor 5 read-only VF 1 read-write W Input W-Phase Monitor 6 read-only WF 2 read-write ICU Interrupt Controller ICU 0x0 0x0 0x10 registers n 0x100 0x1 registers n 0x120 0x2 registers n 0x130 0x2 registers n 0x140 0x2 registers n 0x1A0 0x8 registers n 0x200 0x2 registers n 0x280 0x20 registers n 0x300 0x180 registers n 0x40 0x10 registers n 0x54 0x4 registers n 0x70 0xC registers n IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 IEL32 ICU Interrupt 32 32 IEL33 ICU Interrupt 33 33 IEL34 ICU Interrupt 34 34 IEL35 ICU Interrupt 35 35 IEL36 ICU Interrupt 36 36 IEL37 ICU Interrupt 37 37 IEL38 ICU Interrupt 38 38 IEL39 ICU Interrupt 39 39 IEL40 ICU Interrupt 40 40 IEL41 ICU Interrupt 41 41 IEL42 ICU Interrupt 42 42 IEL43 ICU Interrupt 43 43 IEL44 ICU Interrupt 44 44 IEL45 ICU Interrupt 45 45 IEL46 ICU Interrupt 46 46 IEL47 ICU Interrupt 47 47 IEL48 ICU Interrupt 48 48 IEL49 ICU Interrupt 49 49 IEL50 ICU Interrupt 50 50 IEL51 ICU Interrupt 51 51 IEL52 ICU Interrupt 52 52 IEL53 ICU Interrupt 53 53 IEL54 ICU Interrupt 54 54 IEL55 ICU Interrupt 55 55 IEL56 ICU Interrupt 56 56 IEL57 ICU Interrupt 57 57 IEL58 ICU Interrupt 58 58 IEL59 ICU Interrupt 59 59 IEL60 ICU Interrupt 60 60 IEL61 ICU Interrupt 61 61 IEL62 ICU Interrupt 62 62 IEL63 ICU Interrupt 63 63 IEL64 ICU Interrupt 64 64 IEL65 ICU Interrupt 65 65 IEL66 ICU Interrupt 66 66 IEL67 ICU Interrupt 67 67 IEL68 ICU Interrupt 68 68 IEL69 ICU Interrupt 69 69 IEL70 ICU Interrupt 70 70 IEL71 ICU Interrupt 71 71 IEL72 ICU Interrupt 72 72 IEL73 ICU Interrupt 73 73 IEL74 ICU Interrupt 74 74 IEL75 ICU Interrupt 75 75 IEL76 ICU Interrupt 76 76 IEL77 ICU Interrupt 77 77 IEL78 ICU Interrupt 78 78 IEL79 ICU Interrupt 79 79 IEL80 ICU Interrupt 80 80 IEL81 ICU Interrupt 81 81 IEL82 ICU Interrupt 82 82 IEL83 ICU Interrupt 83 83 IEL84 ICU Interrupt 84 84 IEL85 ICU Interrupt 85 85 IEL86 ICU Interrupt 86 86 IEL87 ICU Interrupt 87 87 IEL88 ICU Interrupt 88 88 IEL89 ICU Interrupt 89 89 IEL90 ICU Interrupt 90 90 IEL91 ICU Interrupt 91 91 IEL92 ICU Interrupt 92 92 IEL93 ICU Interrupt 93 93 IEL94 ICU Interrupt 94 94 IEL95 ICU Interrupt 95 95 DELSR0 DMAC Event Link Setting Register %s 0x280 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 DELSR1 DMAC Event Link Setting Register %s 0x284 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 DELSR2 DMAC Event Link Setting Register %s 0x288 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 DELSR3 DMAC Event Link Setting Register %s 0x28C 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 DELSR4 DMAC Event Link Setting Register %s 0x290 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 DELSR5 DMAC Event Link Setting Register %s 0x294 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 DELSR6 DMAC Event Link Setting Register %s 0x298 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 DELSR7 DMAC Event Link Setting Register %s 0x29C 32 read-write n 0x0 0x0 DELS DMAC Event Link Select 0 8 read-write Others Event signal number to be linked. For details, see . 0x00 Disable interrupts to the associated DMAC module 0x00 IR DMAC Activation Request Status flag 16 read-write 0 No DMAC activation request occurred #0 1 DMAC activation request occurred. #1 ICUSARA Interrupt Controller Unit Security Attribution Register A 0x40 32 read-write n 0x0 0x0 SAIRQCR00 Security attributes of registers for the IRQCRn register 0 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR01 Security attributes of registers for the IRQCRn register 1 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR02 Security attributes of registers for the IRQCRn register 2 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR03 Security attributes of registers for the IRQCRn register 3 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR04 Security attributes of registers for the IRQCRn register 4 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR05 Security attributes of registers for the IRQCRn register 5 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR06 Security attributes of registers for the IRQCRn register 6 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR07 Security attributes of registers for the IRQCRn register 7 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR08 Security attributes of registers for the IRQCRn register 8 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR09 Security attributes of registers for the IRQCRn register 9 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR10 Security attributes of registers for the IRQCRn register 10 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR11 Security attributes of registers for the IRQCRn register 11 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR12 Security attributes of registers for the IRQCRn register 12 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR13 Security attributes of registers for the IRQCRn register 13 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR14 Security attributes of registers for the IRQCRn register 14 read-write 0 Secure #0 1 Non-secure #1 SAIRQCR15 Security attributes of registers for the IRQCRn register 15 read-write 0 Secure #0 1 Non-secure #1 ICUSARB Interrupt Controller Unit Security Attribution Register B 0x44 32 read-write n 0x0 0x0 SANMI Security attributes of registers for nonmaskable interrupt 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARC Interrupt Controller Unit Security Attribution Register C 0x48 32 read-write n 0x0 0x0 SADMAC0 Security attributes of registers for DMAC channel 0 read-write 0 Secure #0 1 Non-secure #1 SADMAC1 Security attributes of registers for DMAC channel 1 read-write 0 Secure #0 1 Non-secure #1 SADMAC2 Security attributes of registers for DMAC channel 2 read-write 0 Secure #0 1 Non-secure #1 SADMAC3 Security attributes of registers for DMAC channel 3 read-write 0 Secure #0 1 Non-secure #1 SADMAC4 Security attributes of registers for DMAC channel 4 read-write 0 Secure #0 1 Non-secure #1 SADMAC5 Security attributes of registers for DMAC channel 5 read-write 0 Secure #0 1 Non-secure #1 SADMAC6 Security attributes of registers for DMAC channel 6 read-write 0 Secure #0 1 Non-secure #1 SADMAC7 Security attributes of registers for DMAC channel 7 read-write 0 Secure #0 1 Non-secure #1 ICUSARD Interrupt Controller Unit Security Attribution Register D 0x4C 32 read-write n 0x0 0x0 SASELSR0 Security attributes of registers for SELSR0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARF Interrupt Controller Unit Security Attribution Register F 0x54 32 read-write n 0x0 0x0 SAAGT3CAWUP Security attributes of registers for WUPEN1.b1 1 read-write 0 Secure #0 1 Non-secure #1 SAAGT3CBWUP Security attributes of registers for WUPEN1.b2 2 read-write 0 Secure #0 1 Non-secure #1 SAAGT3UDWUP Security attributes of registers for WUPEN1.b0 0 read-write 0 Secure #0 1 Non-secure #1 ICUSARG Interrupt Controller Unit Security Attribution Register G 0x70 32 read-write n 0x0 0x0 SAIELSR00 Security attributes of registers for IELSR31 to IELSR0 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR01 Security attributes of registers for IELSR31 to IELSR0 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR02 Security attributes of registers for IELSR31 to IELSR0 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR03 Security attributes of registers for IELSR31 to IELSR0 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR04 Security attributes of registers for IELSR31 to IELSR0 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR05 Security attributes of registers for IELSR31 to IELSR0 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR06 Security attributes of registers for IELSR31 to IELSR0 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR07 Security attributes of registers for IELSR31 to IELSR0 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR08 Security attributes of registers for IELSR31 to IELSR0 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR09 Security attributes of registers for IELSR31 to IELSR0 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR10 Security attributes of registers for IELSR31 to IELSR0 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR11 Security attributes of registers for IELSR31 to IELSR0 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR12 Security attributes of registers for IELSR31 to IELSR0 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR13 Security attributes of registers for IELSR31 to IELSR0 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR14 Security attributes of registers for IELSR31 to IELSR0 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR15 Security attributes of registers for IELSR31 to IELSR0 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR16 Security attributes of registers for IELSR31 to IELSR0 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR17 Security attributes of registers for IELSR31 to IELSR0 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR18 Security attributes of registers for IELSR31 to IELSR0 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR19 Security attributes of registers for IELSR31 to IELSR0 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR20 Security attributes of registers for IELSR31 to IELSR0 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR21 Security attributes of registers for IELSR31 to IELSR0 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR22 Security attributes of registers for IELSR31 to IELSR0 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR23 Security attributes of registers for IELSR31 to IELSR0 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR24 Security attributes of registers for IELSR31 to IELSR0 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR25 Security attributes of registers for IELSR31 to IELSR0 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR26 Security attributes of registers for IELSR31 to IELSR0 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR27 Security attributes of registers for IELSR31 to IELSR0 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR28 Security attributes of registers for IELSR31 to IELSR0 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR29 Security attributes of registers for IELSR31 to IELSR0 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR30 Security attributes of registers for IELSR31 to IELSR0 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR31 Security attributes of registers for IELSR31 to IELSR0 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARH Interrupt Controller Unit Security Attribution Register H 0x74 32 read-write n 0x0 0x0 SAIELSR32 Security attributes of registers for IELSR63 to IELSR32 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR33 Security attributes of registers for IELSR63 to IELSR32 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR34 Security attributes of registers for IELSR63 to IELSR32 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR35 Security attributes of registers for IELSR63 to IELSR32 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR36 Security attributes of registers for IELSR63 to IELSR32 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR37 Security attributes of registers for IELSR63 to IELSR32 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR38 Security attributes of registers for IELSR63 to IELSR32 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR39 Security attributes of registers for IELSR63 to IELSR32 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR40 Security attributes of registers for IELSR63 to IELSR32 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR41 Security attributes of registers for IELSR63 to IELSR32 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR42 Security attributes of registers for IELSR63 to IELSR32 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR43 Security attributes of registers for IELSR63 to IELSR32 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR44 Security attributes of registers for IELSR63 to IELSR32 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR45 Security attributes of registers for IELSR63 to IELSR32 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR46 Security attributes of registers for IELSR63 to IELSR32 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR47 Security attributes of registers for IELSR63 to IELSR32 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR48 Security attributes of registers for IELSR63 to IELSR32 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR49 Security attributes of registers for IELSR63 to IELSR32 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR50 Security attributes of registers for IELSR63 to IELSR32 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR51 Security attributes of registers for IELSR63 to IELSR32 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR52 Security attributes of registers for IELSR63 to IELSR32 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR53 Security attributes of registers for IELSR63 to IELSR32 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR54 Security attributes of registers for IELSR63 to IELSR32 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR55 Security attributes of registers for IELSR63 to IELSR32 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR56 Security attributes of registers for IELSR63 to IELSR32 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR57 Security attributes of registers for IELSR63 to IELSR32 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR58 Security attributes of registers for IELSR63 to IELSR32 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR59 Security attributes of registers for IELSR63 to IELSR32 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR60 Security attributes of registers for IELSR63 to IELSR32 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR61 Security attributes of registers for IELSR63 to IELSR32 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR62 Security attributes of registers for IELSR63 to IELSR32 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR63 Security attributes of registers for IELSR63 to IELSR32 31 read-write 0 Secure #0 1 Non-secure #1 ICUSARI Interrupt Controller Unit Security Attribution Register I 0x78 32 read-write n 0x0 0x0 SAIELSR64 Security attributes of registers for IELSR95 to IELSR64 0 read-write 0 Secure #0 1 Non-secure #1 SAIELSR65 Security attributes of registers for IELSR95 to IELSR64 1 read-write 0 Secure #0 1 Non-secure #1 SAIELSR66 Security attributes of registers for IELSR95 to IELSR64 2 read-write 0 Secure #0 1 Non-secure #1 SAIELSR67 Security attributes of registers for IELSR95 to IELSR64 3 read-write 0 Secure #0 1 Non-secure #1 SAIELSR68 Security attributes of registers for IELSR95 to IELSR64 4 read-write 0 Secure #0 1 Non-secure #1 SAIELSR69 Security attributes of registers for IELSR95 to IELSR64 5 read-write 0 Secure #0 1 Non-secure #1 SAIELSR70 Security attributes of registers for IELSR95 to IELSR64 6 read-write 0 Secure #0 1 Non-secure #1 SAIELSR71 Security attributes of registers for IELSR95 to IELSR64 7 read-write 0 Secure #0 1 Non-secure #1 SAIELSR72 Security attributes of registers for IELSR95 to IELSR64 8 read-write 0 Secure #0 1 Non-secure #1 SAIELSR73 Security attributes of registers for IELSR95 to IELSR64 9 read-write 0 Secure #0 1 Non-secure #1 SAIELSR74 Security attributes of registers for IELSR95 to IELSR64 10 read-write 0 Secure #0 1 Non-secure #1 SAIELSR75 Security attributes of registers for IELSR95 to IELSR64 11 read-write 0 Secure #0 1 Non-secure #1 SAIELSR76 Security attributes of registers for IELSR95 to IELSR64 12 read-write 0 Secure #0 1 Non-secure #1 SAIELSR77 Security attributes of registers for IELSR95 to IELSR64 13 read-write 0 Secure #0 1 Non-secure #1 SAIELSR78 Security attributes of registers for IELSR95 to IELSR64 14 read-write 0 Secure #0 1 Non-secure #1 SAIELSR79 Security attributes of registers for IELSR95 to IELSR64 15 read-write 0 Secure #0 1 Non-secure #1 SAIELSR80 Security attributes of registers for IELSR95 to IELSR64 16 read-write 0 Secure #0 1 Non-secure #1 SAIELSR81 Security attributes of registers for IELSR95 to IELSR64 17 read-write 0 Secure #0 1 Non-secure #1 SAIELSR82 Security attributes of registers for IELSR95 to IELSR64 18 read-write 0 Secure #0 1 Non-secure #1 SAIELSR83 Security attributes of registers for IELSR95 to IELSR64 19 read-write 0 Secure #0 1 Non-secure #1 SAIELSR84 Security attributes of registers for IELSR95 to IELSR64 20 read-write 0 Secure #0 1 Non-secure #1 SAIELSR85 Security attributes of registers for IELSR95 to IELSR64 21 read-write 0 Secure #0 1 Non-secure #1 SAIELSR86 Security attributes of registers for IELSR95 to IELSR64 22 read-write 0 Secure #0 1 Non-secure #1 SAIELSR87 Security attributes of registers for IELSR95 to IELSR64 23 read-write 0 Secure #0 1 Non-secure #1 SAIELSR88 Security attributes of registers for IELSR95 to IELSR64 24 read-write 0 Secure #0 1 Non-secure #1 SAIELSR89 Security attributes of registers for IELSR95 to IELSR64 25 read-write 0 Secure #0 1 Non-secure #1 SAIELSR90 Security attributes of registers for IELSR95 to IELSR64 26 read-write 0 Secure #0 1 Non-secure #1 SAIELSR91 Security attributes of registers for IELSR95 to IELSR64 27 read-write 0 Secure #0 1 Non-secure #1 SAIELSR92 Security attributes of registers for IELSR95 to IELSR64 28 read-write 0 Secure #0 1 Non-secure #1 SAIELSR93 Security attributes of registers for IELSR95 to IELSR64 29 read-write 0 Secure #0 1 Non-secure #1 SAIELSR94 Security attributes of registers for IELSR95 to IELSR64 30 read-write 0 Secure #0 1 Non-secure #1 SAIELSR95 Security attributes of registers for IELSR95 to IELSR64 31 read-write 0 Secure #0 1 Non-secure #1 IELSR0 ICU Event Link Setting Register %s 0x300 32 read-write n 0x0 0x0 IELSR1 ICU Event Link Setting Register %s 0x304 32 read-write n 0x0 0x0 IELSR10 ICU Event Link Setting Register %s 0x328 32 read-write n 0x0 0x0 IELSR11 ICU Event Link Setting Register %s 0x32C 32 read-write n 0x0 0x0 IELSR12 ICU Event Link Setting Register %s 0x330 32 read-write n 0x0 0x0 IELSR13 ICU Event Link Setting Register %s 0x334 32 read-write n 0x0 0x0 IELSR14 ICU Event Link Setting Register %s 0x338 32 read-write n 0x0 0x0 IELSR15 ICU Event Link Setting Register %s 0x33C 32 read-write n 0x0 0x0 IELSR16 ICU Event Link Setting Register %s 0x340 32 read-write n 0x0 0x0 IELSR17 ICU Event Link Setting Register %s 0x344 32 read-write n 0x0 0x0 IELSR18 ICU Event Link Setting Register %s 0x348 32 read-write n 0x0 0x0 IELSR19 ICU Event Link Setting Register %s 0x34C 32 read-write n 0x0 0x0 IELSR2 ICU Event Link Setting Register %s 0x308 32 read-write n 0x0 0x0 IELSR20 ICU Event Link Setting Register %s 0x350 32 read-write n 0x0 0x0 IELSR21 ICU Event Link Setting Register %s 0x354 32 read-write n 0x0 0x0 IELSR22 ICU Event Link Setting Register %s 0x358 32 read-write n 0x0 0x0 IELSR23 ICU Event Link Setting Register %s 0x35C 32 read-write n 0x0 0x0 IELSR24 ICU Event Link Setting Register %s 0x360 32 read-write n 0x0 0x0 IELSR25 ICU Event Link Setting Register %s 0x364 32 read-write n 0x0 0x0 IELSR26 ICU Event Link Setting Register %s 0x368 32 read-write n 0x0 0x0 IELSR27 ICU Event Link Setting Register %s 0x36C 32 read-write n 0x0 0x0 IELSR28 ICU Event Link Setting Register %s 0x370 32 read-write n 0x0 0x0 IELSR29 ICU Event Link Setting Register %s 0x374 32 read-write n 0x0 0x0 IELSR3 ICU Event Link Setting Register %s 0x30C 32 read-write n 0x0 0x0 IELSR30 ICU Event Link Setting Register %s 0x378 32 read-write n 0x0 0x0 IELSR31 ICU Event Link Setting Register %s 0x37C 32 read-write n 0x0 0x0 IELSR32 ICU Event Link Setting Register %s 0x380 32 read-write n 0x0 0x0 IELSR33 ICU Event Link Setting Register %s 0x384 32 read-write n 0x0 0x0 IELSR34 ICU Event Link Setting Register %s 0x388 32 read-write n 0x0 0x0 IELSR35 ICU Event Link Setting Register %s 0x38C 32 read-write n 0x0 0x0 IELSR36 ICU Event Link Setting Register %s 0x390 32 read-write n 0x0 0x0 IELSR37 ICU Event Link Setting Register %s 0x394 32 read-write n 0x0 0x0 IELSR38 ICU Event Link Setting Register %s 0x398 32 read-write n 0x0 0x0 IELSR39 ICU Event Link Setting Register %s 0x39C 32 read-write n 0x0 0x0 IELSR4 ICU Event Link Setting Register %s 0x310 32 read-write n 0x0 0x0 IELSR40 ICU Event Link Setting Register %s 0x3A0 32 read-write n 0x0 0x0 IELSR41 ICU Event Link Setting Register %s 0x3A4 32 read-write n 0x0 0x0 IELSR42 ICU Event Link Setting Register %s 0x3A8 32 read-write n 0x0 0x0 IELSR43 ICU Event Link Setting Register %s 0x3AC 32 read-write n 0x0 0x0 IELSR44 ICU Event Link Setting Register %s 0x3B0 32 read-write n 0x0 0x0 IELSR45 ICU Event Link Setting Register %s 0x3B4 32 read-write n 0x0 0x0 IELSR46 ICU Event Link Setting Register %s 0x3B8 32 read-write n 0x0 0x0 IELSR47 ICU Event Link Setting Register %s 0x3BC 32 read-write n 0x0 0x0 IELSR48 ICU Event Link Setting Register %s 0x3C0 32 read-write n 0x0 0x0 IELSR49 ICU Event Link Setting Register %s 0x3C4 32 read-write n 0x0 0x0 IELSR5 ICU Event Link Setting Register %s 0x314 32 read-write n 0x0 0x0 IELSR50 ICU Event Link Setting Register %s 0x3C8 32 read-write n 0x0 0x0 IELSR51 ICU Event Link Setting Register %s 0x3CC 32 read-write n 0x0 0x0 IELSR52 ICU Event Link Setting Register %s 0x3D0 32 read-write n 0x0 0x0 IELSR53 ICU Event Link Setting Register %s 0x3D4 32 read-write n 0x0 0x0 IELSR54 ICU Event Link Setting Register %s 0x3D8 32 read-write n 0x0 0x0 IELSR55 ICU Event Link Setting Register %s 0x3DC 32 read-write n 0x0 0x0 IELSR56 ICU Event Link Setting Register %s 0x3E0 32 read-write n 0x0 0x0 IELSR57 ICU Event Link Setting Register %s 0x3E4 32 read-write n 0x0 0x0 IELSR58 ICU Event Link Setting Register %s 0x3E8 32 read-write n 0x0 0x0 IELSR59 ICU Event Link Setting Register %s 0x3EC 32 read-write n 0x0 0x0 IELSR6 ICU Event Link Setting Register %s 0x318 32 read-write n 0x0 0x0 IELSR60 ICU Event Link Setting Register %s 0x3F0 32 read-write n 0x0 0x0 IELSR61 ICU Event Link Setting Register %s 0x3F4 32 read-write n 0x0 0x0 IELSR62 ICU Event Link Setting Register %s 0x3F8 32 read-write n 0x0 0x0 IELSR63 ICU Event Link Setting Register %s 0x3FC 32 read-write n 0x0 0x0 IELSR64 ICU Event Link Setting Register %s 0x400 32 read-write n 0x0 0x0 IELSR65 ICU Event Link Setting Register %s 0x404 32 read-write n 0x0 0x0 IELSR66 ICU Event Link Setting Register %s 0x408 32 read-write n 0x0 0x0 IELSR67 ICU Event Link Setting Register %s 0x40C 32 read-write n 0x0 0x0 IELSR68 ICU Event Link Setting Register %s 0x410 32 read-write n 0x0 0x0 IELSR69 ICU Event Link Setting Register %s 0x414 32 read-write n 0x0 0x0 IELSR7 ICU Event Link Setting Register %s 0x31C 32 read-write n 0x0 0x0 IELSR70 ICU Event Link Setting Register %s 0x418 32 read-write n 0x0 0x0 IELSR71 ICU Event Link Setting Register %s 0x41C 32 read-write n 0x0 0x0 IELSR72 ICU Event Link Setting Register %s 0x420 32 read-write n 0x0 0x0 IELSR73 ICU Event Link Setting Register %s 0x424 32 read-write n 0x0 0x0 IELSR74 ICU Event Link Setting Register %s 0x428 32 read-write n 0x0 0x0 IELSR75 ICU Event Link Setting Register %s 0x42C 32 read-write n 0x0 0x0 IELSR76 ICU Event Link Setting Register %s 0x430 32 read-write n 0x0 0x0 IELSR77 ICU Event Link Setting Register %s 0x434 32 read-write n 0x0 0x0 IELSR78 ICU Event Link Setting Register %s 0x438 32 read-write n 0x0 0x0 IELSR79 ICU Event Link Setting Register %s 0x43C 32 read-write n 0x0 0x0 IELSR8 ICU Event Link Setting Register %s 0x320 32 read-write n 0x0 0x0 IELSR80 ICU Event Link Setting Register %s 0x440 32 read-write n 0x0 0x0 IELSR81 ICU Event Link Setting Register %s 0x444 32 read-write n 0x0 0x0 IELSR82 ICU Event Link Setting Register %s 0x448 32 read-write n 0x0 0x0 IELSR83 ICU Event Link Setting Register %s 0x44C 32 read-write n 0x0 0x0 IELSR84 ICU Event Link Setting Register %s 0x450 32 read-write n 0x0 0x0 IELSR85 ICU Event Link Setting Register %s 0x454 32 read-write n 0x0 0x0 IELSR86 ICU Event Link Setting Register %s 0x458 32 read-write n 0x0 0x0 IELSR87 ICU Event Link Setting Register %s 0x45C 32 read-write n 0x0 0x0 IELSR88 ICU Event Link Setting Register %s 0x460 32 read-write n 0x0 0x0 IELSR89 ICU Event Link Setting Register %s 0x464 32 read-write n 0x0 0x0 IELSR9 ICU Event Link Setting Register %s 0x324 32 read-write n 0x0 0x0 IELSR90 ICU Event Link Setting Register %s 0x468 32 read-write n 0x0 0x0 IELSR91 ICU Event Link Setting Register %s 0x46C 32 read-write n 0x0 0x0 IELSR92 ICU Event Link Setting Register %s 0x470 32 read-write n 0x0 0x0 IELSR93 ICU Event Link Setting Register %s 0x474 32 read-write n 0x0 0x0 IELSR94 ICU Event Link Setting Register %s 0x478 32 read-write n 0x0 0x0 IELSR95 ICU Event Link Setting Register %s 0x47C 32 read-write n 0x0 0x0 IRQCR0 IRQ Control Register 0x0 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR1 IRQ Control Register 0x1 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR10 IRQ Control Register 0xA 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR11 IRQ Control Register 0xB 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR12 IRQ Control Register 0xC 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR13 IRQ Control Register 0xD 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR14 IRQ Control Register 0xE 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR15 IRQ Control Register 0xF 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR2 IRQ Control Register 0x2 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR3 IRQ Control Register 0x3 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR4 IRQ Control Register 0x4 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR5 IRQ Control Register 0x5 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR6 IRQ Control Register 0x6 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR7 IRQ Control Register 0x7 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR8 IRQ Control Register 0x8 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 IRQCR9 IRQ Control Register 0x9 8 read-write n 0x0 0x0 FCLKSEL IRQi Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 FLTEN IRQi Digital Filter Enable 7 read-write 0 Digital filter is disabled #0 1 Digital filter is enabled. #1 IRQMD IRQi Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write n 0x0 0x0 BUSMCLR Bus Master Error Clear 11 read-write 0 No effect #0 1 Clear the NMISR.BUSMST flag #1 CPECLR 15 read-write 0 No effect #0 1 Clear the NMISR.CPECLR flag #1 IWDTCLR IWDT Clear 0 read-write 0 No effect #0 1 Clear the NMISR.IWDTST flag #1 LVD1CLR LVD1 Clear 2 read-write 0 No effect #0 1 Clear the NMISR.LVD1ST flag #1 LVD2CLR LVD2 Clear 3 read-write 0 No effect #0 1 Clear the NMISR.LVD2ST flag. #1 NMICLR NMI Clear 7 read-write 0 No effect #0 1 Clear the NMISR.NMIST flag #1 OSTCLR OST Clear 6 read-write 0 No effect #0 1 Clear the NMISR.OSTST flag #1 RECCCLR SRAM ECC Error Clear 9 read-write 0 No effect #0 1 Clear the NMISR.RECCST flag #1 RPECLR SRAM Parity Error Clear 8 read-write 0 No effect #0 1 Clear the NMISR.RPEST flag #1 TZFCLR 13 read-write 0 No effect #0 1 Clear the NMISR.TZFCLR flag #1 WDTCLR WDT Clear 1 read-write 0 No effect #0 1 Clear the NMISR.WDTST flag #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write n 0x0 0x0 NFCLKSEL NMI Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKL #00 01 PCLKL/8 #01 10 PCLKL/32 #10 11 PCLKL/64 #11 NFLTEN NMI Digital Filter Enable 7 read-write 0 Disabled #0 1 Enabled #1 NMIMD NMI Detection Set 0 read-write 0 Falling edge #0 1 Rising edge #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write n 0x0 0x0 BUSMEN MPU Bus Master Error Interrupt Enable 11 read-write 0 Disabled #0 1 Enabled #1 CPEEN 15 read-write 0 Disabled #0 1 Enabled #1 IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 read-write 0 Disabled #0 1 Enabled. #1 LVD1EN Voltage monitor 1 Interrupt Enable 2 read-write 0 Disabled #0 1 Enabled #1 LVD2EN Voltage monitor 2 Interrupt Enable 3 read-write 0 Disabled #0 1 Enabled #1 NMIEN NMI Pin Interrupt Enable 7 read-write 0 Disabled #0 1 Enabled #1 OSTEN Oscillation Stop Detection Interrupt Enable 6 read-write 0 Disabled #0 1 Enabled #1 RECCEN SRAM ECC Error Interrupt Enable 9 read-write 0 Disabled #0 1 Enabled #1 RPEEN SRAM Parity Error Interrupt Enable 8 read-write 0 Disabled #0 1 Enabled #1 TZFEN 13 read-write 0 Disabled #0 1 Enabled #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 read-write 0 Disabled #0 1 Enabled #1 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only n 0x0 0x0 BUSMST MPU Bus Master Error Interrupt Status Flag 11 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 CPEST 15 read-only 0 Cache RAM Parity Error interrupt is not requested. #0 1 Cache RAM Parity Error interrupt is requested. #1 IWDTST IWDT Underflow/Refresh Error Status Flag 0 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD1ST Voltage Monitor 1 Interrupt Status Flag 2 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 LVD2ST Voltage Monitor 2 Interrupt Status Flag 3 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 NMIST NMI Status Flag 7 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 OSTST Oscillation Stop Detection Interrupt Status Flag 6 read-only 0 Interrupt not requested for main oscillation stop #0 1 Interrupt requested for main oscillation stop #1 RECCST SRAM ECC Error Interrupt Status Flag 9 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 RPEST SRAM Parity Error Interrupt Status Flag 8 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 TZFST 13 read-only 0 TRUST Zone Filter Error interrupt is not requested. #0 1 TRUST Zone Filter Error interrupt is requested. #1 WDTST WDT Underflow/Refresh Error Status Flag 1 read-only 0 Interrupt not requested #0 1 Interrupt requested #1 SELSR0 SYS Event Link Setting Register 0x200 16 read-write n 0x0 0x0 WUPEN0 Wake Up Interrupt Enable Register 0 0x1A0 32 read-write n 0x0 0x0 AGT1CAWUPEN AGT1 compare match A interrupt S/W standby returns enable bit 29 read-write 0 S/W standby returns by AGT1 compare match A interrupt is disabled #0 1 S/W standby returns by AGT1 compare match A interrupt is enabled #1 AGT1CBWUPEN AGT1 compare match B interrupt S/W standby returns enable bit 30 read-write 0 S/W standby returns by AGT1 compare match B interrupt is disabled #0 1 S/W standby returns by AGT1 compare match B interrupt is enabled #1 AGT1UDWUPEN AGT1 underflow interrupt S/W standby returns enable bit 28 read-write 0 S/W standby returns by AGT1 underflow interrupt is disabled #0 1 S/W standby returns by AGT1 underflow interrupt is enabled #1 IRQWUPEN IRQn interrupt S/W standby returns enable bit 0 15 read-write 0 S/W standby returns by IRQn interrupt is disabled #0 1 S/W standby returns by IRQn interrupt is enabled #1 IWDTWUPEN IWDT interrupt S/W standby returns enable bit 16 read-write 0 S/W standby returns by IWDT interrupt is disabled #0 1 S/W standby returns by IWDT interrupt is enabled #1 LVD1WUPEN LVD1 interrupt S/W standby returns enable bit 18 read-write 0 S/W standby returns by LVD1 interrupt is disabled #0 1 S/W standby returns by LVD1 interrupt is enabled #1 LVD2WUPEN LVD2 interrupt S/W standby returns enable bit 19 read-write 0 S/W standby returns by LVD2 interrupt is disabled #0 1 S/W standby returns by LVD2 interrupt is enabled #1 RIIC0WUPEN RIIC0 address match interrupt S/W standby returns enable bit 31 read-write 0 S/W standby returns by RIIC0 address match interrupt is disabled #0 1 S/W standby returns by RIIC0 address match interrupt is enabled #1 RTCALMWUPEN RTC alarm interrupt S/W standby returns enable bit 24 read-write 0 S/W standby returns by RTC alarm interrupt is disabled #0 1 S/W standby returns by RTC alarm interrupt is enabled #1 RTCPRDWUPEN RTC period interrupt S/W standby returns enable bit 25 0 S/W standby returns by RTC period interrupt is disabled #0 1 S/W standby returns by RTC period interrupt is enabled #1 USBFS0WUPEN USBFS0 interrupt S/W standby returns enable bit 27 read-write 0 S/W standby returns by USBFS0 interrupt is disabled #0 1 S/W standby returns by USBFS0 interrupt is enabled #1 WUPEN1 Wake Up interrupt enable register 1 0x1A4 32 read-write n 0x0 0x0 AGT3CAWUPEN AGT3 compare match A interrupt S/W standby returns enable bit 1 read-write 0 S/W standby returns by AGT3 compare match A interrupt is disabled #0 1 S/W standby returns by AGT3 compare match A interrupt is enabled #1 AGT3CBWUPEN AGT3 compare match B interrupt S/W standby returns enable bit 2 read-write 0 S/W standby returns by AGT3 compare match B interrupt is disabled #0 1 S/W standby returns by AGT3 compare match B interrupt is enabled #1 AGT3UDWUPEN AGT3 underflow interrupt S/W standby returns enable bit 0 read-write 0 S/W standby returns by AGT3 underflow interrupt is disabled #0 1 S/W standby returns by AGT3 underflow interrupt is enabled #1 IIC0 Inter-Integrated Circuit 0 IIC0 0x0 0x0 0x14 registers n ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write n 0x0 0x0 BRH Bit Rate High-Level Period 0 4 read-write ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write n 0x0 0x0 BRL Bit Rate Low-Level Period 0 4 read-write ICCR1 I2C Bus Control Register 1 0x0 8 read-write n 0x0 0x0 CLO Extra SCL Clock Cycle Output 5 read-write 0 Do not output extra SCL clock cycle (default) #0 1 Output extra SCL clock cycle #1 ICE I2C Bus Interface Enable 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal Reset 6 read-write 0 Release IIC reset or internal reset #0 1 Initiate IIC reset or internal reset #1 SCLI SCL Line Monitor 1 read-only 0 SCLn line is low #0 1 SCLn line is high #1 SCLO SCL Output Control/Monitor 3 read-write 0 Read: IIC drives SCLn pin low Write: IIC drives SCLn pin low #0 1 Read: IIC releases SCLn pin Write: IIC releases SCLn pin #1 SDAI SDA Line Monitor 0 read-only 0 SDAn line is low #0 1 SDAn line is high #1 SDAO SDA Output Control/Monitor 2 read-write 0 Read: IIC drives SDAn pin low Write: IIC drives SDAn pin low #0 1 Read: IIC releases SDAn pin Write: IIC releases SDAn pin #1 SOWP SCLO/SDAO Write Protect 4 write-only 0 Write enable SCLO and SDAO bits #0 1 Write protect SCLO and SDAO bits #1 ICCR2 I2C Bus Control Register 2 0x1 8 read-write n 0x0 0x0 BBSY Bus Busy Detection Flag 7 read-only 0 I2C bus released (bus free state) #0 1 I2C bus occupied (bus busy state) #1 MST Master/Slave Mode 6 read-write 0 Slave mode #0 1 Master mode #1 RS Restart Condition Issuance Request 2 read-write 0 Do not issue a restart condition request #0 1 Issue a restart condition request #1 SP Stop Condition Issuance Request 3 read-write 0 Do not issue a stop condition request #0 1 Issue a stop condition request #1 ST Start Condition Issuance Request 1 read-write 0 Do not issue a start condition request #0 1 Issue a start condition request #1 TRS Transmit/Receive Mode 5 read-write 0 Receive mode #0 1 Transmit mode #1 ICDRR I2C Bus Receive Data Register 0x13 8 read-only n 0x0 0x0 ICDRT I2C Bus Transmit Data Register 0x12 8 read-write n 0x0 0x0 ICFER I2C Bus Function Enable Register 0x5 8 read-write n 0x0 0x0 FMPE Fast-Mode Plus Enable 7 read-write 0 Do not use the Fm+ slope control circuit for the SCLn and SDAn pins #0 1 Use the Fm+ slope control circuit for the SCLn and SDAn pins. #1 MALE Master Arbitration-Lost Detection Enable 1 read-write 0 Disable the arbitration-lost detection function and disable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #0 1 Enable the arbitration-lost detection function and enable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #1 NACKE NACK Reception Transfer Suspension Enable 4 read-write 0 Do not suspend transfer operation during NACK reception (disable transfer suspension) #0 1 Suspend transfer operation during NACK reception (enable transfer suspension) #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 read-write 0 Disable #0 1 Enable #1 NFE Digital Noise Filter Circuit Enable 5 read-write 0 Do not use the digital noise filter circuit #0 1 Use the digital noise filter circuit #1 SALE Slave Arbitration-Lost Detection Enable 3 read-write 0 Disable #0 1 Enable #1 SCLE SCL Synchronous Circuit Enable 6 read-write 0 Do not use the SCL synchronous circuit #0 1 Use the SCL synchronous circuit #1 TMOE Timeout Function Enable 0 read-write 0 Disable #0 1 Enable #1 ICIER I2C Bus Interrupt Enable Register 0x7 8 read-write n 0x0 0x0 ALIE Arbitration-Lost Interrupt Request Enable 1 read-write 0 Disable arbitration-lost interrupt (ALI) request #0 1 Enable arbitration-lost interrupt (ALI) request #1 NAKIE NACK Reception Interrupt Request Enable 4 read-write 0 Disable NACK reception interrupt (NAKI) request #0 1 Enable NACK reception interrupt (NAKI) request #1 RIE Receive Data Full Interrupt Request Enable 5 read-write 0 Disable receive data full interrupt (IICn_RXI) request #0 1 Enable receive data full interrupt (IICn_RXI) request #1 SPIE Stop Condition Detection Interrupt Request Enable 3 read-write 0 Disable stop condition detection interrupt (SPI) request #0 1 Enable stop condition detection interrupt (SPI) request #1 STIE Start Condition Detection Interrupt Request Enable 2 read-write 0 Disable start condition detection interrupt (STI) request #0 1 Enable start condition detection interrupt (STI) request #1 TEIE Transmit End Interrupt Request Enable 6 read-write 0 Disable transmit end interrupt (IICn_TEI) request #0 1 Enable transmit end interrupt (IICn_TEI) request #1 TIE Transmit Data Empty Interrupt Request Enable 7 read-write 0 Disable transmit data empty interrupt (IICn_TXI) request #0 1 Enable transmit data empty interrupt (IICn_TXI) request #1 TMOIE Timeout Interrupt Request Enable 0 read-write 0 Disable timeout interrupt (TMOI) request #0 1 Enable timeout interrupt (TMOI) request #1 ICMR1 I2C Bus Mode Register 1 0x2 8 read-write n 0x0 0x0 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 BCWP BC Write Protect 3 write-only 0 Write enable BC[2:0] bits #0 1 Write protect BC[2:0] bits #1 CKS Internal Reference Clock Select 4 2 read-write MTWP MST/TRS Write Protect 7 read-write 0 Write protect MST and TRS bits in ICCR2 #0 1 Write enable MST and TRS bits in ICCR2 #1 ICMR2 I2C Bus Mode Register 2 0x3 8 read-write n 0x0 0x0 DLCS SDA Output Delay Clock Source Select 7 read-write 0 Select internal reference clock (IIC-phi) as the clock source for SDA output delay counter #0 1 Select internal reference clock divided by 2 (IIC-phi/2) as the clock source for SDA output delay counter #1 SDDL SDA Output Delay Counter 4 2 read-write 000 No output delay #000 001 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi)) 1 or 2 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #001 010 2 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 3 or 4 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #010 011 3 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 5 or 6 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #011 100 4 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 7 or 8 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #100 101 5 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 9 or 10 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #101 110 6 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 11 or 12 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #110 111 7 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 13 or 14 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #111 TMOH Timeout H Count Control 2 read-write 0 Disable count while SCLn line is high #0 1 Enable count while SCLn line is high #1 TMOL Timeout L Count Control 1 read-write 0 Disable count while SCLn line is low #0 1 Enable count while SCLn line is low #1 TMOS Timeout Detection Time Select 0 read-write 0 Select long mode #0 1 Select short mode #1 ICMR3 I2C Bus Mode Register 3 0x4 8 read-write n 0x0 0x0 ACKBR Receive Acknowledge 2 read-only 0 0 received as the acknowledge bit (ACK reception) #0 1 1 received as the acknowledge bit (NACK reception) #1 ACKBT Transmit Acknowledge 3 read-write 0 Send 0 as the acknowledge bit (ACK transmission) #0 1 Send 1 as the acknowledge bit (NACK transmission) #1 ACKWP ACKBT Write Protect 4 read-write 0 Write protect ACKBT bit #0 1 Write enable ACKBT bit #1 NF Noise Filter Stage Select 0 1 read-write 00 Filter out noise of up to 1 IIC-phi cycle (single-stage filter) #00 01 Filter out noise of up to 2 IIC-phi cycles (2-stage filter) #01 10 Filter out noise of up to 3 IIC-phi cycles (3-stage filter) #10 11 Filter out noise of up to 4 IIC-phi cycles (4-stage filter) #11 RDRFS RDRF Flag Set Timing Select 5 read-write 0 Set the RDRF flag on the rising edge of the 9th SCL clock cycle. The SCLn line is not held low on the falling edge of the 8th clock cycle. #0 1 Set the RDRF flag on the rising edge of the 8th SCL clock cycle. The SCLn line is held low on the falling edge of the 8th clock cycle. #1 SMBS SMBus/I2C Bus Select 7 read-write 0 Select I2C Bus #0 1 Select SMBus #1 WAIT Low-hold is released by reading ICDRR. 6 read-write 0 No wait (The SCLn line is not held low during the period between the 9th clock cycle and the 1st clock cycle.) #0 1 Wait (The SCLn line is held low during the period between the 9th clock cycle and the 1st clock cycle.) #1 ICSER I2C Bus Status Enable Register 0x6 8 read-write n 0x0 0x0 DIDE Device-ID Address Detection Enable 5 read-write 0 Disable device-ID address detection #0 1 Enable device-ID address detection #1 GCAE General Call Address Enable 3 read-write 0 Disable general call address detection #0 1 Enable general call address detection #1 HOAE Host Address Enable 7 read-write 0 Disable host address detection #0 1 Enable host address detection #1 SAR0E Slave Address Register 0 Enable 0 read-write 0 Disable slave address in SARL0 and SARU0 #0 1 Enable slave address in SARL0 and SARU0 #1 SAR1E Slave Address Register 1 Enable 1 read-write 0 Disable slave address in SARL1 and SARU1 #0 1 Enable slave address in SARL1 and SARU1 #1 SAR2E Slave Address Register 2 Enable 2 read-write 0 Disable slave address in SARL2 and SARU2 #0 1 Enable slave address in SARL2 and SARU2 #1 ICSR1 I2C Bus Status Register 1 0x8 8 read-write n 0x0 0x0 AAS0 Slave Address 0 Detection Flag 0 read-write 0 Slave address 0 not detected #0 1 Slave address 0 detected #1 AAS1 Slave Address 1 Detection Flag 1 read-write 0 Slave address 1 not detected #0 1 Slave address 1 detected #1 AAS2 Slave Address 2 Detection Flag 2 read-write 0 Slave address 2 not detected #0 1 Slave address 2 detected #1 DID Device-ID Address Detection Flag 5 read-write 0 Device-ID command not detected #0 1 Device-ID command detected #1 GCA General Call Address Detection Flag 3 read-write 0 General call address not detected #0 1 General call address detected #1 HOA Host Address Detection Flag 7 read-write 0 Host address not detected #0 1 Host address detected #1 ICSR2 I2C Bus Status Register 2 0x9 8 read-write n 0x0 0x0 AL Arbitration-Lost Flag 1 read-write 0 Arbitration not lost #0 1 Arbitration lost #1 NACKF NACK Detection Flag 4 read-write 0 NACK not detected #0 1 NACK detected #1 RDRF Receive Data Full Flag 5 read-write 0 ICDRR contains no receive data #0 1 ICDRR contains receive data #1 START Start Condition Detection Flag 2 read-write 0 Start condition not detected #0 1 Start condition detected #1 STOP Stop Condition Detection Flag 3 read-write 0 Stop condition not detected #0 1 Stop condition detected #1 TDRE Transmit Data Empty Flag 7 read-only 0 ICDRT contains transmit data #0 1 ICDRT contains no transmit data #1 TEND Transmit End Flag 6 read-write 0 Data being transmitted #0 1 Data transmit complete #1 TMOF Timeout Detection Flag 0 read-write 0 Timeout not detected #0 1 Timeout detected #1 SARL0 Slave Address Register Ly 0xA 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARL1 Slave Address Register Ly 0xC 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARL2 Slave Address Register Ly 0xE 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARU0 Slave Address Register Uy 0xB 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write SARU1 Slave Address Register Uy 0xD 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write SARU2 Slave Address Register Uy 0xF 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write IIC0WU Inter-Integrated Circuit 0 Wake-up Unit IIC0WU 0x0 0x2 0x2 registers n ICWUR I2C Bus Wakeup Unit Register 0x2 8 read-write n 0x0 0x0 WUACK ACK Bit for Wakeup Mode 4 read-write WUAFA Wakeup Analog Filter Additional Selection 0 read-write 0 Do not add the wakeup analog filter #0 1 Add the wakeup analog filter #1 WUE Wakeup Function Enable 7 read-write 0 Disable wakeup function #0 1 Enable wakeup function #1 WUF Wakeup Event Occurrence Flag 5 read-write 0 Slave address not matching during wakeup #0 1 Slave address matching during wakeup #1 WUIE Wakeup Interrupt Request Enable 6 read-write 0 Disable wakeup interrupt request (IIC0_WUI) #0 1 Enable wakeup interrupt request (IIC0_WUI) #1 ICWUR2 I2C Bus Wakeup Unit Register 2 0x3 8 read-write n 0x0 0x0 WUASYF Wakeup Function Asynchronous Operation Status Flag 1 read-only 0 IIC synchronous circuit enable condition #0 1 IIC asynchronous circuit enable condition #1 WUSEN Wakeup Function Synchronous Enable 0 read-write 0 IIC asynchronous circuit enable #0 1 IIC synchronous circuit enable #1 WUSYF Wakeup Function Synchronous Operation Status Flag 2 read-only 0 IIC asynchronous circuit enable condition #0 1 IIC synchronous circuit enable condition #1 IIC1 Inter-Integrated Circuit 1 IIC0 0x0 0x0 0x14 registers n ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write n 0x0 0x0 BRH Bit Rate High-Level Period 0 4 read-write ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write n 0x0 0x0 BRL Bit Rate Low-Level Period 0 4 read-write ICCR1 I2C Bus Control Register 1 0x0 8 read-write n 0x0 0x0 CLO Extra SCL Clock Cycle Output 5 read-write 0 Do not output extra SCL clock cycle (default) #0 1 Output extra SCL clock cycle #1 ICE I2C Bus Interface Enable 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal Reset 6 read-write 0 Release IIC reset or internal reset #0 1 Initiate IIC reset or internal reset #1 SCLI SCL Line Monitor 1 read-only 0 SCLn line is low #0 1 SCLn line is high #1 SCLO SCL Output Control/Monitor 3 read-write 0 Read: IIC drives SCLn pin low Write: IIC drives SCLn pin low #0 1 Read: IIC releases SCLn pin Write: IIC releases SCLn pin #1 SDAI SDA Line Monitor 0 read-only 0 SDAn line is low #0 1 SDAn line is high #1 SDAO SDA Output Control/Monitor 2 read-write 0 Read: IIC drives SDAn pin low Write: IIC drives SDAn pin low #0 1 Read: IIC releases SDAn pin Write: IIC releases SDAn pin #1 SOWP SCLO/SDAO Write Protect 4 write-only 0 Write enable SCLO and SDAO bits #0 1 Write protect SCLO and SDAO bits #1 ICCR2 I2C Bus Control Register 2 0x1 8 read-write n 0x0 0x0 BBSY Bus Busy Detection Flag 7 read-only 0 I2C bus released (bus free state) #0 1 I2C bus occupied (bus busy state) #1 MST Master/Slave Mode 6 read-write 0 Slave mode #0 1 Master mode #1 RS Restart Condition Issuance Request 2 read-write 0 Do not issue a restart condition request #0 1 Issue a restart condition request #1 SP Stop Condition Issuance Request 3 read-write 0 Do not issue a stop condition request #0 1 Issue a stop condition request #1 ST Start Condition Issuance Request 1 read-write 0 Do not issue a start condition request #0 1 Issue a start condition request #1 TRS Transmit/Receive Mode 5 read-write 0 Receive mode #0 1 Transmit mode #1 ICDRR I2C Bus Receive Data Register 0x13 8 read-only n 0x0 0x0 ICDRT I2C Bus Transmit Data Register 0x12 8 read-write n 0x0 0x0 ICFER I2C Bus Function Enable Register 0x5 8 read-write n 0x0 0x0 FMPE Fast-Mode Plus Enable 7 read-write 0 Do not use the Fm+ slope control circuit for the SCLn and SDAn pins #0 1 Use the Fm+ slope control circuit for the SCLn and SDAn pins. #1 MALE Master Arbitration-Lost Detection Enable 1 read-write 0 Disable the arbitration-lost detection function and disable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #0 1 Enable the arbitration-lost detection function and enable automatic clearing of the MST and TRS bits in ICCR2 when arbitration is lost #1 NACKE NACK Reception Transfer Suspension Enable 4 read-write 0 Do not suspend transfer operation during NACK reception (disable transfer suspension) #0 1 Suspend transfer operation during NACK reception (enable transfer suspension) #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 read-write 0 Disable #0 1 Enable #1 NFE Digital Noise Filter Circuit Enable 5 read-write 0 Do not use the digital noise filter circuit #0 1 Use the digital noise filter circuit #1 SALE Slave Arbitration-Lost Detection Enable 3 read-write 0 Disable #0 1 Enable #1 SCLE SCL Synchronous Circuit Enable 6 read-write 0 Do not use the SCL synchronous circuit #0 1 Use the SCL synchronous circuit #1 TMOE Timeout Function Enable 0 read-write 0 Disable #0 1 Enable #1 ICIER I2C Bus Interrupt Enable Register 0x7 8 read-write n 0x0 0x0 ALIE Arbitration-Lost Interrupt Request Enable 1 read-write 0 Disable arbitration-lost interrupt (ALI) request #0 1 Enable arbitration-lost interrupt (ALI) request #1 NAKIE NACK Reception Interrupt Request Enable 4 read-write 0 Disable NACK reception interrupt (NAKI) request #0 1 Enable NACK reception interrupt (NAKI) request #1 RIE Receive Data Full Interrupt Request Enable 5 read-write 0 Disable receive data full interrupt (IICn_RXI) request #0 1 Enable receive data full interrupt (IICn_RXI) request #1 SPIE Stop Condition Detection Interrupt Request Enable 3 read-write 0 Disable stop condition detection interrupt (SPI) request #0 1 Enable stop condition detection interrupt (SPI) request #1 STIE Start Condition Detection Interrupt Request Enable 2 read-write 0 Disable start condition detection interrupt (STI) request #0 1 Enable start condition detection interrupt (STI) request #1 TEIE Transmit End Interrupt Request Enable 6 read-write 0 Disable transmit end interrupt (IICn_TEI) request #0 1 Enable transmit end interrupt (IICn_TEI) request #1 TIE Transmit Data Empty Interrupt Request Enable 7 read-write 0 Disable transmit data empty interrupt (IICn_TXI) request #0 1 Enable transmit data empty interrupt (IICn_TXI) request #1 TMOIE Timeout Interrupt Request Enable 0 read-write 0 Disable timeout interrupt (TMOI) request #0 1 Enable timeout interrupt (TMOI) request #1 ICMR1 I2C Bus Mode Register 1 0x2 8 read-write n 0x0 0x0 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 BCWP BC Write Protect 3 write-only 0 Write enable BC[2:0] bits #0 1 Write protect BC[2:0] bits #1 CKS Internal Reference Clock Select 4 2 read-write MTWP MST/TRS Write Protect 7 read-write 0 Write protect MST and TRS bits in ICCR2 #0 1 Write enable MST and TRS bits in ICCR2 #1 ICMR2 I2C Bus Mode Register 2 0x3 8 read-write n 0x0 0x0 DLCS SDA Output Delay Clock Source Select 7 read-write 0 Select internal reference clock (IIC-phi) as the clock source for SDA output delay counter #0 1 Select internal reference clock divided by 2 (IIC-phi/2) as the clock source for SDA output delay counter #1 SDDL SDA Output Delay Counter 4 2 read-write 000 No output delay #000 001 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi)) 1 or 2 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #001 010 2 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 3 or 4 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #010 011 3 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 5 or 6 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #011 100 4 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 7 or 8 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #100 101 5 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 9 or 10 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #101 110 6 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 11 or 12 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #110 111 7 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 13 or 14 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) #111 TMOH Timeout H Count Control 2 read-write 0 Disable count while SCLn line is high #0 1 Enable count while SCLn line is high #1 TMOL Timeout L Count Control 1 read-write 0 Disable count while SCLn line is low #0 1 Enable count while SCLn line is low #1 TMOS Timeout Detection Time Select 0 read-write 0 Select long mode #0 1 Select short mode #1 ICMR3 I2C Bus Mode Register 3 0x4 8 read-write n 0x0 0x0 ACKBR Receive Acknowledge 2 read-only 0 0 received as the acknowledge bit (ACK reception) #0 1 1 received as the acknowledge bit (NACK reception) #1 ACKBT Transmit Acknowledge 3 read-write 0 Send 0 as the acknowledge bit (ACK transmission) #0 1 Send 1 as the acknowledge bit (NACK transmission) #1 ACKWP ACKBT Write Protect 4 read-write 0 Write protect ACKBT bit #0 1 Write enable ACKBT bit #1 NF Noise Filter Stage Select 0 1 read-write 00 Filter out noise of up to 1 IIC-phi cycle (single-stage filter) #00 01 Filter out noise of up to 2 IIC-phi cycles (2-stage filter) #01 10 Filter out noise of up to 3 IIC-phi cycles (3-stage filter) #10 11 Filter out noise of up to 4 IIC-phi cycles (4-stage filter) #11 RDRFS RDRF Flag Set Timing Select 5 read-write 0 Set the RDRF flag on the rising edge of the 9th SCL clock cycle. The SCLn line is not held low on the falling edge of the 8th clock cycle. #0 1 Set the RDRF flag on the rising edge of the 8th SCL clock cycle. The SCLn line is held low on the falling edge of the 8th clock cycle. #1 SMBS SMBus/I2C Bus Select 7 read-write 0 Select I2C Bus #0 1 Select SMBus #1 WAIT Low-hold is released by reading ICDRR. 6 read-write 0 No wait (The SCLn line is not held low during the period between the 9th clock cycle and the 1st clock cycle.) #0 1 Wait (The SCLn line is held low during the period between the 9th clock cycle and the 1st clock cycle.) #1 ICSER I2C Bus Status Enable Register 0x6 8 read-write n 0x0 0x0 DIDE Device-ID Address Detection Enable 5 read-write 0 Disable device-ID address detection #0 1 Enable device-ID address detection #1 GCAE General Call Address Enable 3 read-write 0 Disable general call address detection #0 1 Enable general call address detection #1 HOAE Host Address Enable 7 read-write 0 Disable host address detection #0 1 Enable host address detection #1 SAR0E Slave Address Register 0 Enable 0 read-write 0 Disable slave address in SARL0 and SARU0 #0 1 Enable slave address in SARL0 and SARU0 #1 SAR1E Slave Address Register 1 Enable 1 read-write 0 Disable slave address in SARL1 and SARU1 #0 1 Enable slave address in SARL1 and SARU1 #1 SAR2E Slave Address Register 2 Enable 2 read-write 0 Disable slave address in SARL2 and SARU2 #0 1 Enable slave address in SARL2 and SARU2 #1 ICSR1 I2C Bus Status Register 1 0x8 8 read-write n 0x0 0x0 AAS0 Slave Address 0 Detection Flag 0 read-write 0 Slave address 0 not detected #0 1 Slave address 0 detected #1 AAS1 Slave Address 1 Detection Flag 1 read-write 0 Slave address 1 not detected #0 1 Slave address 1 detected #1 AAS2 Slave Address 2 Detection Flag 2 read-write 0 Slave address 2 not detected #0 1 Slave address 2 detected #1 DID Device-ID Address Detection Flag 5 read-write 0 Device-ID command not detected #0 1 Device-ID command detected #1 GCA General Call Address Detection Flag 3 read-write 0 General call address not detected #0 1 General call address detected #1 HOA Host Address Detection Flag 7 read-write 0 Host address not detected #0 1 Host address detected #1 ICSR2 I2C Bus Status Register 2 0x9 8 read-write n 0x0 0x0 AL Arbitration-Lost Flag 1 read-write 0 Arbitration not lost #0 1 Arbitration lost #1 NACKF NACK Detection Flag 4 read-write 0 NACK not detected #0 1 NACK detected #1 RDRF Receive Data Full Flag 5 read-write 0 ICDRR contains no receive data #0 1 ICDRR contains receive data #1 START Start Condition Detection Flag 2 read-write 0 Start condition not detected #0 1 Start condition detected #1 STOP Stop Condition Detection Flag 3 read-write 0 Stop condition not detected #0 1 Stop condition detected #1 TDRE Transmit Data Empty Flag 7 read-only 0 ICDRT contains transmit data #0 1 ICDRT contains no transmit data #1 TEND Transmit End Flag 6 read-write 0 Data being transmitted #0 1 Data transmit complete #1 TMOF Timeout Detection Flag 0 read-write 0 Timeout not detected #0 1 Timeout detected #1 SARL0 Slave Address Register Ly 0xA 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARL1 Slave Address Register Ly 0xC 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARL2 Slave Address Register Ly 0xE 8 read-write n 0x0 0x0 SVA 7-bit Address/10-bit Address Lower Bits 1 6 read-write SVA0 10-bit Address LSB 0 read-write SARU0 Slave Address Register Uy 0xB 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write SARU1 Slave Address Register Uy 0xD 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write SARU2 Slave Address Register Uy 0xF 8 read-write n 0x0 0x0 FS 7-bit/10-bit Address Format Select 0 read-write 0 Select 7-bit address format #0 1 Select 10-bit address format #1 SVA 10-bit Address Upper Bits 1 1 read-write IWDT Independent Watchdog Timer IWDT 0x0 0x0 0x1 registers n 0x4 0x2 registers n IWDTRR IWDT Refresh Register 0x0 8 read-write n 0x0 0x0 IWDTSR IWDT Status Register 0x4 16 read-write n 0x0 0x0 CNTVAL Counter Value 0 13 read-only REFEF Refresh Error Flag 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1 MSTP Module Stop Control MSTP 0x0 0x4 0xC registers n MSTPCRB Module Stop Control Register B 0x4 32 read-write n 0x0 0x0 MSTPB1 Controller Area Network 1 Module Stop 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB11 Universal Serial Bus 2.0 FS Interface 0 Module Stop 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB15 ETHERC0 and EDMAC0 Module Stop 15 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB16 OSPI Module Stop 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB18 Serial Peripheral Interface 1 Module Stop 18 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB2 Controller Area Network 0 Module Stop 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB23 Serial Communication Interface 8 Module Stop 23 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB24 Serial Communication Interface 7 Module Stop 24 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB25 Serial Communication Interface 6 Module Stop 25 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB26 Serial Communication Interface 5 Module Stop 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB27 Serial Communication Interface 4 Module Stop 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB28 Serial Communication Interface 3 Module Stop 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB29 Serial Communication Interface 2 Module Stop 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB30 Serial Communication Interface 1 Module Stop 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB31 Serial Communication Interface 0 Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB6 Quad Serial Peripheral Interface Module Stop 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB8 I2C Bus Interface 1 Module Stop 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB9 I2C Bus Interface 0 Module Stop 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRC Module Stop Control Register C 0x8 32 read-write n 0x0 0x0 MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 Cyclic Redundancy Check Calculator Module Stop 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC12 Secure Digital HOST IF / Multi Media Card 0 Module Stop 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC3 Capacitive Touch Sensing Unit Module Stop 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC31 SCE9 Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC8 Serial Sound Interface Enhanced Module Stop 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0xC 32 read-write n 0x0 0x0 MSTPD0 Low Power Asynchronous General Purpose Timer 3 Module Stop 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD1 Low Power Asynchronous General Purpose Timer 2 Module Stop 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD11 Port Output Enable for GPT 3 Module Stop 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD12 Port Output Enable for GPT 2 Module Stop 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD13 Port Output Enable for GPT 1 Module Stop 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD14 Port Output Enable for GPT 0 Module Stop 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD15 12-bit A/D Converter 1 Module Stop 15 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 12-bit A/D Converter 0 Module Stop 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD2 Low Power Asynchronous General Purpose Timer 1 Module Stop 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD20 12-bit D/A Converter Module Stop 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD22 Temperature Sensor Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 Low Power Asynchronous General Purpose Timer 0 Module Stop 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 OSPI Octa Serial Peripheral Interface OSPI 0x0 0x0 0x24 registers n 0x34 0x34 registers n 0x7C 0x8 registers n ACAR0 Auto-Calibration Address Register 0 0x1C 32 read-write n 0x0 0x0 CAD0 Automatic calibration address 0 31 read-write ACAR1 Auto-Calibration Address Register 1 0x20 32 read-write n 0x0 0x0 CAD1 Automatic calibration address 0 31 read-write ACSR Auto-Calibration Status Register 0x64 32 read-only n 0x0 0x0 ACSR0 Auto-calibration status of device 0 0 2 read-only 000 Initial state #000 001 Reserved #001 010 Reserved #010 011 Normal end #011 100 Error end #100 ACSR1 Auto-calibration status of device 1 3 2 read-only 000 Initial state #000 001 Reserved #001 010 Reserved #010 011 Normal end #011 100 Error end #100 ACTR Auto-Calibration Timer Register 0x18 32 read-write n 0x0 0x0 CTP Automatic calibration cycle time setting 0 31 read-write CDSR Controller and Device Setting Register 0x40 32 read-write n 0x0 0x0 ACMEME0 Automatic calibration memory enable setting for device 0 10 read-write 0 Disable #0 1 Enable #1 ACMEME1 Automatic calibration memory enable setting for device 1 11 0 Disable #0 1 Enable #1 ACMODE Automatic calibration mode 12 1 read-write 00 Automatic calibration is disabled #00 01 Automatic calibration is enabled and modify MDTR #01 10 Automatic calibration immediately is executed for all trim code, but it will not modify MDTR #10 11 Setting prohibited #11 DLFT Deadlock Free Timer Enable 31 read-write 0 Enable timer #0 1 Disable timer #1 DV0PC Device0_memory precycle setting 4 read-write 0 Disable #0 1 Enable #1 DV0TTYP Device0_transfer_type setting 0 1 read-write 00 SPI mode #00 01 SOPI mode #01 10 DOPI mode #10 11 Setting prohibited #11 DV1PC Device1_memory precycle setting 5 read-write 0 Disable #0 1 Enable #1 DV1TTYP Device1_transfer_type setting 2 1 read-write 00 SPI mode #00 01 SOPI mode #01 10 DOPI mode #10 11 Setting prohibited #11 CRR Configure Read Register 0x60 32 read-only n 0x0 0x0 RD0 Read data 0 0 7 read-only RD1 Read data 1 8 7 read-only RD2 Read data 2 16 7 read-only RD3 Read data 3 24 7 read-only CWDR Configure Write Data Register 0x5C 32 write-only n 0x0 0x0 WD0 Write data 0 0 7 write-only WD1 Write data 1 8 7 write-only WD2 Write data 2 16 7 write-only WD3 Write data 3 24 7 write-only CWNDR Configure Write without Data Register 0x58 32 write-only n 0x0 0x0 WND The write value should be 0. 0 31 write-only DAR Device Address Register 0x4 32 read-write n 0x0 0x0 DVAD0 Device Address data 0 0 7 read-write DVAD1 Device Address data 1 8 7 read-write DVAD2 Device Address data 2 16 7 read-write DVAD3 Device Address data 3 24 7 read-write DCR Device Command Register 0x0 32 read-write n 0x0 0x0 DVCMD0 Device Command data 0 7 read-write DVCMD1 Device Command data 8 7 read-write DCSMXR Device Chip Select Maximum Period Register 0x7C 32 read-write n 0x0 0x0 CTWMX0 Indicates the maximum period that OM_CS0 and OM_CS1 are Low in single continuous write of OctaRAM. 0 8 read-write CTWMX1 Indicates the maximum period that OM_CS0 and OM_CS1 are Low in single continuous read of OctaRAM. 16 8 read-write DCSR Device Command Setting Register 0x8 32 read-write n 0x0 0x0 ACDA Data Access Control 28 read-write 0 Register access Do not arrange the transfer data. #0 1 Data access #1 ACDV Access Device setting 19 read-write 0 Send commands to device 0. #0 1 Send commands to device 1. #1 ADLEN Transfer address length setting 24 2 read-write CMDLEN Transfer command length setting 20 2 read-write DALEN Transfer data length setting 0 7 read-write DAOR Data order setting 23 read-write 0 byte0, byte1, byte2, byte3 #0 1 byte1, byte0, byte3, byte2 #1 DMLEN Dummy cycle setting 8 7 read-write DOPI DOPI single byte setting 27 read-write 0 Each cycle has two bytes data. (normal DOPI mode) #0 1 Each cycle has one byte data. (The byte data changes at the rising edge of the clock and does not change at the falling edge of the clock.) #1 PREN Preamble bit enable for OctaRAM 29 read-write 0 No check preamble bit from OctaRAM #0 1 Check preamble bit from OctaRAM #1 DCSTR Device Chip Select Timing Setting Register 0x3C 32 read-write n 0x0 0x0 DVSELCMD Device Command execution interval setting 8 2 read-write 000 2 clock cycles #000 001 5 clock cycles #001 010 7 clock cycles #010 011 9 clock cycles #011 100 11 clock cycles #100 101 13 clock cycles #101 110 15 clock cycles #110 111 17 clock cycles #111 DVSELHI Device select signal pull-up timing setting 11 2 read-write 000 Setting prohibited #000 001 Setting prohibited #001 010 Setting prohibited #010 011 Setting prohibited (DOPI mode) 5 clock cycles (Other mode) #011 100 Setting prohibited (DOPI mode) 6 clock cycles (Other mode) #100 101 6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode) #101 110 7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode) #110 111 8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode) #111 DVSELLO Device select signal pull-down timing setting 14 1 read-write 00 Setting prohibit #00 01 2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode) #01 10 3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode) #10 11 4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode) #11 DRCSTR Device Memory Map Read Chip Select Timing Setting Register 0x34 32 read-write n 0x0 0x0 CTR0 Device 0 single continuous read mode setting 7 read-write 0 Single continuous read mode is disabled for device 0. #0 1 Single continuous read mode is enabled for device 0. #1 CTR1 Device 1 single continuous read mode setting 23 read-write 0 Single continuous read mode is disabled for device 1. #0 1 Single continuous read mode is enabled for device 1. #1 CTRW0 Device 0 single continuous read waiting cycle setting in PCLKH units 0 6 read-write CTRW1 Device 1 single continuous read waiting cycle setting in PCLKH units 16 6 read-write DVRDCMD0 Device 0 Command execution interval setting 8 2 read-write 000 2 clock cycles #000 001 5 clock cycles #001 010 7 clock cycles #010 011 9 clock cycles #011 100 11 clock cycles #100 101 13 clock cycles #101 110 15 clock cycles #110 111 17 clock cycles #111 DVRDCMD1 Device 1 Command execution interval 24 2 read-write 000 2 clock cycles #000 001 5 clock cycles #001 010 7 clock cycles #010 011 9 clock cycles #011 100 11 clock cycles #100 101 13 clock cycles #101 110 15 clock cycles #110 111 17 clock cycles #111 DVRDHI0 Device 0 select signal pull-up timing setting 11 2 read-write 000 Setting prohibit #000 001 Setting prohibit #001 010 Setting prohibit #010 011 Setting prohibit (DOPI mode) 5 clock cycles (Other mode) #011 100 Setting prohibit (DOPI mode) 6 clock cycles (Other mode) #100 101 6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode) #101 110 7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode) #110 111 8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode) #111 DVRDHI1 Device 1 select signal High timing setting 27 2 read-write 000 Setting prohibit #000 001 Setting prohibit #001 010 Setting prohibit #010 011 Setting prohibit (DOPI mode) 5 clock cycles (Other mode) #011 100 Setting prohibit (DOPI mode) 6 clock cycles (Other mode) #100 101 6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode) #101 110 7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode) #110 111 8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode) #111 DVRDLO0 Device 0 select signal pull-down timing setting 14 1 read-write 00 Setting prohibit #00 01 2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode) #01 10 3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode) #10 11 4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode) #11 DVRDLO1 Device 1 select signal pull-down timing setting 30 1 read-write 00 Setting prohibited #00 01 2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode) #01 10 3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode) #10 11 4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode) #11 DSR0 Device Size Register 0 0xC 32 read-write n 0x0 0x0 DV0SZ Device 0 size setting 0 29 read-write DV0TYP Device 0 type setting 30 1 read-write 00 flash on device 0 #00 01 RAM on device 0 #01 10 no connection on device 0 #10 11 forbidden #11 DSR1 Device Size Register 1 0x10 32 read-write n 0x0 0x0 DV1SZ Device 1 size setting 0 29 read-write DV1TYP Device 1 type setting 30 1 read-write 00 flash on device 1 #00 01 RAM on device 1 #01 10 no connection on device 1 #10 11 forbidden #11 DWCSTR Device Memory Map Write Chip Select Timing Setting Register 0x38 32 read-write n 0x0 0x0 CTW0 Device 0 single continuous write mode setting 7 read-write 0 Single continuous write mode is disabled for device 0 #0 1 Single continuous write mode is enabled for device 0 #1 CTW1 Device 1 single continuous write mode setting 23 read-write 0 Single continuous write mode is disabled for device 1 #0 1 Single continuous write mode is enabled for device 1 #1 CTWW0 Device 0 single continuous write waiting cycle setting in PCLKH units 0 6 read-write CTWW1 Device 1 single continuous write waiting cycle setting in PCLKH units 16 6 read-write DVWCMD0 Device 0 Command execution interval setting 8 2 read-write 000 2 clock cycles #000 001 5 clock cycles #001 010 7 clock cycles #010 011 9 clock cycles #011 100 11 clock cycles #100 101 13 clock cycles #101 110 15 clock cycles #110 111 17 clock cycles #111 DVWCMD1 Device 1 Command execution interval setting 24 2 read-write 000 setting prohibited #000 001 5 clock cycles #001 010 7 clock cycles #010 011 9 clock cycles #011 100 11 clock cycles #100 101 13 clock cycles #101 110 15 clock cycles #110 111 17 clock cycles #111 DVWHI0 Device 0 select signal pull-up timing setting 11 2 read-write 000 1.5 clock cycles (DOPI mode) 2 clock cycles (Other mode) #000 001 2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode) #001 010 3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode) #010 011 4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode) #011 100 5.5 clock cycles (DOPI mode) 6 clock cycles (Other mode) #100 101 6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode) #101 110 7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode) #110 111 8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode) #111 DVWHI1 Device 1 select signal pull-up timing setting 27 2 read-write 000 1.5 clock cycles (DOPI mode) 2 clock cycles (Other mode) #000 001 2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode) #001 010 3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode) #010 011 4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode) #011 100 5.5 clock cycles (DOPI mode) 6 clock cycles (Other mode) #100 101 6.5 clock cycles (DOPI mode) 7 clock cycles (Other mode) #101 110 7.5 clock cycles (DOPI mode) 8 clock cycles (Other mode) #110 111 8.5 clock cycles (DOPI mode) 9 clock cycles (Other mode) #111 DVWLO0 Device 0 select signal pull-down timing setting 14 1 read-write 00 Setting prohibit #00 01 2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode) #01 10 3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode) #10 11 4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode) #11 DVWLO1 Device 1 select signal pull-down timing setting 30 1 read-write 00 Setting prohibit #00 01 2.5 clock cycles (DOPI mode) 3 clock cycles (Other mode) #01 10 3.5 clock cycles (DOPI mode) 4 clock cycles (Other mode) #10 11 4.5 clock cycles (DOPI mode) 5 clock cycles (Other mode) #11 DWSCTSR Device Memory Map Write single continuous translating size Register 0x80 32 read-write n 0x0 0x0 CTSN0 Indicates the number of bytes to translate in single continuous write of device 0. 0 10 read-write CTSN1 Indicates the number of bytes to translate in single continuous write of device 1. 16 10 read-write ESR Error Status Register 0x54 32 read-only n 0x0 0x0 MRESR Memory map read error status 0 7 read-only Others Reserved 0x01 ECC error 0x01 0x02 Preamble error 0x02 0x03 Wait OM_DQS timeout 0x03 0x80 Invalid command 0x80 MWESR Memory map write error status 8 7 read-only Others Reserved 0x80 Invalid command 0x80 MDLR Memory Map Dummy Length Register 0x44 32 read-write n 0x0 0x0 DV0RDL Device 0 Read dummy length setting 0 7 read-write DV0WDL Device 0 Write dummy length setting 8 7 read-write DV1RDL Device 1 Read dummy length setting 16 7 read-write DV1WDL Device 1 Write dummy length setting 24 7 read-write MDTR Memory Delay Trim Register 0x14 32 read-write n 0x0 0x0 DQSEDOPI OM_DQS enable counter 24 3 read-write DQSERAM OM_DQS enable counter 8 3 read-write DQSESOPI OM_DQS enable counter 12 3 read-write DV0DEL Device 0 delay setting 0 7 read-write DV1DEL Device 1 delay setting 16 7 read-write MRWCR0 Memory Map Read/Write Command Register 0 0x48 32 read-write n 0x0 0x0 D0MRCMD0 Memory map read command 0 setting 0 7 read-write D0MRCMD1 Memory map read command 1 setting 8 7 read-write D0MWCMD0 Memory map write command 0 setting 16 7 read-write D0MWCMD1 Memory map write command 1 setting 24 7 read-write MRWCR1 Memory Map Read/Write Command Register 1 0x4C 32 read-write n 0x0 0x0 D1MRCMD0 Memory map read command 0 setting 0 7 read-write D1MRCMD1 Memory map read command 1 setting 8 7 read-write D1MWCMD0 Memory map write command 0 setting 16 7 read-write D1MWCMD1 Memory map write command 1 setting 24 7 read-write MRWCSR Memory Map Read/Write Setting Register 0x50 32 read-write n 0x0 0x0 MRAL0 Device 0 read address length setting 0 2 read-write MRAL1 Device 1 read address length setting 16 2 read-write MRCL0 Device 0 read command length setting 3 2 read-write MRCL1 Device 1 read command length setting 19 2 read-write MRO0 Device 0 read order setting 6 read-write 0 Read order is byte0, byte1, byte2, byte3. #0 1 Read order is byte1, byte0, byte3, byte2. #1 MRO1 Device 1 read order setting 22 read-write 0 Read order is byte0, byte1, byte2, byte3. #0 1 Read order is byte1, byte0, byte3, byte2. #1 MWAL0 Device 0 write address length setting 8 2 read-write MWAL1 Device 1 write address length setting 24 2 read-write MWCL0 Device 0 write command length setting 11 2 read-write MWCL1 Device 1 write command length setting 27 2 read-write MWO0 Device 0 write order setting 14 read-write 0 Write order is byte0, byte1, byte2, byte3. #0 1 Write order is byte1, byte0, byte3, byte2. #1 MWO1 Device 1 write order setting 30 read-write 0 Write order is byte0, byte1, byte2, byte3. #0 1 Write order is byte1, byte0, byte3, byte2. #1 PREN0 Preamble bit enable for mem0 memory-map read 7 read-write 0 No check preamble bit #0 1 Check preamble bit from OctaFlash (if OctaFlash is connected to device 0) #1 PREN1 Preamble bit enable for mem1 memory-map read 23 read-write 0 No check preamble bit #0 1 Check preamble bit from OctaFlash (if OctaFlash is connected to device 1) #1 PFS Pmn Pin Function Control Register PFS 0x0 0x0 0x243 registers n P000PFS P000 Pin Function Control Register 0x0 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved These bits are read as 00. The write value should be 00. 12 1 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write P000PFS_BY P000 Pin Function Control Register P000PFS 0x3 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write P000PFS_HA P000 Pin Function Control Register P000PFS 0x2 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved These bits are read as 00. The write value should be 00. 12 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved These bits are read as 00. The write value should be 00. 12 1 read-write P001PFS P00%s Pin Function Control Register 0x4 32 read-write n 0x0 0x0 P001PFS_BY P00%s Pin Function Control Register P00%sPFS 0x7 8 read-write n 0x0 0x0 P001PFS_HA P00%s Pin Function Control Register P00%sPFS 0x6 16 read-write n 0x0 0x0 P002PFS P00%s Pin Function Control Register 0x8 32 read-write n 0x0 0x0 P002PFS_BY P00%s Pin Function Control Register P00%sPFS 0xB 8 read-write n 0x0 0x0 P002PFS_HA P00%s Pin Function Control Register P00%sPFS 0xA 16 read-write n 0x0 0x0 P003PFS P00%s Pin Function Control Register 0xC 32 read-write n 0x0 0x0 P003PFS_BY P00%s Pin Function Control Register P00%sPFS 0xF 8 read-write n 0x0 0x0 P003PFS_HA P00%s Pin Function Control Register P00%sPFS 0xE 16 read-write n 0x0 0x0 P004PFS P00%s Pin Function Control Register 0x10 32 read-write n 0x0 0x0 P004PFS_BY P00%s Pin Function Control Register P00%sPFS 0x13 8 read-write n 0x0 0x0 P004PFS_HA P00%s Pin Function Control Register P00%sPFS 0x12 16 read-write n 0x0 0x0 P005PFS P00%s Pin Function Control Register 0x14 32 read-write n 0x0 0x0 P005PFS_BY P00%s Pin Function Control Register P00%sPFS 0x17 8 read-write n 0x0 0x0 P005PFS_HA P00%s Pin Function Control Register P00%sPFS 0x16 16 read-write n 0x0 0x0 P006PFS P00%s Pin Function Control Register 0x18 32 read-write n 0x0 0x0 P006PFS_BY P00%s Pin Function Control Register P00%sPFS 0x1B 8 read-write n 0x0 0x0 P006PFS_HA P00%s Pin Function Control Register P00%sPFS 0x1A 16 read-write n 0x0 0x0 P007PFS P00%s Pin Function Control Register 0x1C 32 read-write n 0x0 0x0 P007PFS_BY P00%s Pin Function Control Register P00%sPFS 0x1F 8 read-write n 0x0 0x0 P007PFS_HA P00%s Pin Function Control Register P00%sPFS 0x1E 16 read-write n 0x0 0x0 P008PFS P00%s Pin Function Control Register 0x20 32 read-write n 0x0 0x0 P008PFS_BY P00%s Pin Function Control Register P00%sPFS 0x23 8 read-write n 0x0 0x0 P008PFS_HA P00%s Pin Function Control Register P00%sPFS 0x22 16 read-write n 0x0 0x0 P009PFS P00%s Pin Function Control Register 0x24 32 read-write n 0x0 0x0 P009PFS_BY P00%s Pin Function Control Register P00%sPFS 0x27 8 read-write n 0x0 0x0 P009PFS_HA P00%s Pin Function Control Register P00%sPFS 0x26 16 read-write n 0x0 0x0 P010PFS P0%s Pin Function Control Register 0x28 32 read-write n 0x0 0x0 P010PFS_BY P0%s Pin Function Control Register 0x2B 8 read-write n 0x0 0x0 P010PFS_HA P0%s Pin Function Control Register 0x2A 16 read-write n 0x0 0x0 P011PFS P0%s Pin Function Control Register 0x2C 32 read-write n 0x0 0x0 P011PFS_BY P0%s Pin Function Control Register 0x2F 8 read-write n 0x0 0x0 P011PFS_HA P0%s Pin Function Control Register 0x2E 16 read-write n 0x0 0x0 P012PFS P0%s Pin Function Control Register 0x30 32 read-write n 0x0 0x0 P012PFS_BY P0%s Pin Function Control Register 0x33 8 read-write n 0x0 0x0 P012PFS_HA P0%s Pin Function Control Register 0x32 16 read-write n 0x0 0x0 P013PFS P0%s Pin Function Control Register 0x34 32 read-write n 0x0 0x0 P013PFS_BY P0%s Pin Function Control Register 0x37 8 read-write n 0x0 0x0 P013PFS_HA P0%s Pin Function Control Register 0x36 16 read-write n 0x0 0x0 P014PFS P0%s Pin Function Control Register 0x38 32 read-write n 0x0 0x0 P014PFS_BY P0%s Pin Function Control Register 0x3B 8 read-write n 0x0 0x0 P014PFS_HA P0%s Pin Function Control Register 0x3A 16 read-write n 0x0 0x0 P015PFS P0%s Pin Function Control Register 0x3C 32 read-write n 0x0 0x0 P015PFS_BY P0%s Pin Function Control Register 0x3F 8 read-write n 0x0 0x0 P015PFS_HA P0%s Pin Function Control Register 0x3E 16 read-write n 0x0 0x0 P100PFS P100 Pin Function Control Register 0x40 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write P100PFS_BY P100 Pin Function Control Register 0x43 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write P100PFS_HA P100 Pin Function Control Register 0x42 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write P101PFS P10%s Pin Function Control Register P10%sPFS 0x44 32 read-write n 0x0 0x0 P101PFS_BY P10%s Pin Function Control Register P10%sPFS 0x47 8 read-write n 0x0 0x0 P101PFS_HA P10%s Pin Function Control Register P10%sPFS 0x46 16 read-write n 0x0 0x0 P102PFS P10%s Pin Function Control Register P10%sPFS 0x48 32 read-write n 0x0 0x0 P102PFS_BY P10%s Pin Function Control Register P10%sPFS 0x4B 8 read-write n 0x0 0x0 P102PFS_HA P10%s Pin Function Control Register P10%sPFS 0x4A 16 read-write n 0x0 0x0 P103PFS P10%s Pin Function Control Register P10%sPFS 0x4C 32 read-write n 0x0 0x0 P103PFS_BY P10%s Pin Function Control Register P10%sPFS 0x4F 8 read-write n 0x0 0x0 P103PFS_HA P10%s Pin Function Control Register P10%sPFS 0x4E 16 read-write n 0x0 0x0 P104PFS P10%s Pin Function Control Register P10%sPFS 0x50 32 read-write n 0x0 0x0 P104PFS_BY P10%s Pin Function Control Register P10%sPFS 0x53 8 read-write n 0x0 0x0 P104PFS_HA P10%s Pin Function Control Register P10%sPFS 0x52 16 read-write n 0x0 0x0 P105PFS P10%s Pin Function Control Register P10%sPFS 0x54 32 read-write n 0x0 0x0 P105PFS_BY P10%s Pin Function Control Register P10%sPFS 0x57 8 read-write n 0x0 0x0 P105PFS_HA P10%s Pin Function Control Register P10%sPFS 0x56 16 read-write n 0x0 0x0 P106PFS P10%s Pin Function Control Register P10%sPFS 0x58 32 read-write n 0x0 0x0 P106PFS_BY P10%s Pin Function Control Register P10%sPFS 0x5B 8 read-write n 0x0 0x0 P106PFS_HA P10%s Pin Function Control Register P10%sPFS 0x5A 16 read-write n 0x0 0x0 P107PFS P10%s Pin Function Control Register P10%sPFS 0x5C 32 read-write n 0x0 0x0 P107PFS_BY P10%s Pin Function Control Register P10%sPFS 0x5F 8 read-write n 0x0 0x0 P107PFS_HA P10%s Pin Function Control Register P10%sPFS 0x5E 16 read-write n 0x0 0x0 P108PFS P108 Pin Function Control Register 0x60 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write P108PFS_BY P108 Pin Function Control Register P108PFS 0x63 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write P108PFS_HA P108 Pin Function Control Register P108PFS 0x62 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write P109PFS P109 Pin Function Control Register 0x64 32 read-write n 0x0 0x0 P109PFS_BY P109 Pin Function Control Register P109PFS 0x67 8 read-write n 0x0 0x0 P109PFS_HA P109 Pin Function Control Register P109PFS 0x66 16 read-write n 0x0 0x0 P110PFS P110 Pin Function Control Register 0x68 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write P110PFS_BY P110 Pin Function Control Register P110PFS 0x6B 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write P110PFS_HA P110 Pin Function Control Register P110PFS 0x6A 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write P111PFS P1%s Pin Function Control Register 0x6C 32 read-write n 0x0 0x0 P111PFS_BY P1%s Pin Function Control Register P1%sPFS 0x6F 8 read-write n 0x0 0x0 P111PFS_HA P1%s Pin Function Control Register P1%sPFS 0x6E 16 read-write n 0x0 0x0 P112PFS P1%s Pin Function Control Register 0x70 32 read-write n 0x0 0x0 P112PFS_BY P1%s Pin Function Control Register P1%sPFS 0x73 8 read-write n 0x0 0x0 P112PFS_HA P1%s Pin Function Control Register P1%sPFS 0x72 16 read-write n 0x0 0x0 P113PFS P1%s Pin Function Control Register 0x74 32 read-write n 0x0 0x0 P113PFS_BY P1%s Pin Function Control Register P1%sPFS 0x77 8 read-write n 0x0 0x0 P113PFS_HA P1%s Pin Function Control Register P1%sPFS 0x76 16 read-write n 0x0 0x0 P114PFS P1%s Pin Function Control Register 0x78 32 read-write n 0x0 0x0 P114PFS_BY P1%s Pin Function Control Register P1%sPFS 0x7B 8 read-write n 0x0 0x0 P114PFS_HA P1%s Pin Function Control Register P1%sPFS 0x7A 16 read-write n 0x0 0x0 P115PFS P1%s Pin Function Control Register 0x7C 32 read-write n 0x0 0x0 P115PFS_BY P1%s Pin Function Control Register P1%sPFS 0x7F 8 read-write n 0x0 0x0 P115PFS_HA P1%s Pin Function Control Register P1%sPFS 0x7E 16 read-write n 0x0 0x0 P200PFS P200 Pin Function Control Register 0x80 32 read-write n 0x0 0x0 P200PFS_BY P200 Pin Function Control Register P200PFS 0x83 8 read-write n 0x0 0x0 P200PFS_HA P200 Pin Function Control Register P200PFS 0x82 16 read-write n 0x0 0x0 P201PFS P201 Pin Function Control Register 0x84 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write P201PFS_BY P201 Pin Function Control Register P201PFS 0x87 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write P201PFS_HA P201 Pin Function Control Register P201PFS 0x86 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 1 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Extra high drive #10 11 High-drive output #11 EOFR Event on Falling/Event on Rising 12 1 read-write 00 No need to care #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write P202PFS P20%s Pin Function Control Register 0x88 32 read-write n 0x0 0x0 P202PFS_BY P20%s Pin Function Control Register P20%sPFS 0x8B 8 read-write n 0x0 0x0 P202PFS_HA P20%s Pin Function Control Register P20%sPFS 0x8A 16 read-write n 0x0 0x0 P203PFS P20%s Pin Function Control Register 0x8C 32 read-write n 0x0 0x0 P203PFS_BY P20%s Pin Function Control Register P20%sPFS 0x8F 8 read-write n 0x0 0x0 P203PFS_HA P20%s Pin Function Control Register P20%sPFS 0x8E 16 read-write n 0x0 0x0 P204PFS P20%s Pin Function Control Register 0x90 32 read-write n 0x0 0x0 P204PFS_BY P20%s Pin Function Control Register P20%sPFS 0x93 8 read-write n 0x0 0x0 P204PFS_HA P20%s Pin Function Control Register P20%sPFS 0x92 16 read-write n 0x0 0x0 P205PFS P20%s Pin Function Control Register 0x94 32 read-write n 0x0 0x0 P205PFS_BY P20%s Pin Function Control Register P20%sPFS 0x97 8 read-write n 0x0 0x0 P205PFS_HA P20%s Pin Function Control Register P20%sPFS 0x96 16 read-write n 0x0 0x0 P206PFS P20%s Pin Function Control Register 0x98 32 read-write n 0x0 0x0 P206PFS_BY P20%s Pin Function Control Register P20%sPFS 0x9B 8 read-write n 0x0 0x0 P206PFS_HA P20%s Pin Function Control Register P20%sPFS 0x9A 16 read-write n 0x0 0x0 P207PFS P20%s Pin Function Control Register 0x9C 32 read-write n 0x0 0x0 P207PFS_BY P20%s Pin Function Control Register P20%sPFS 0x9F 8 read-write n 0x0 0x0 P207PFS_HA P20%s Pin Function Control Register P20%sPFS 0x9E 16 read-write n 0x0 0x0 P208PFS P20%s Pin Function Control Register 0xA0 32 read-write n 0x0 0x0 P208PFS_BY P20%s Pin Function Control Register P20%sPFS 0xA3 8 read-write n 0x0 0x0 P208PFS_HA P20%s Pin Function Control Register P20%sPFS 0xA2 16 read-write n 0x0 0x0 P209PFS P20%s Pin Function Control Register 0xA4 32 read-write n 0x0 0x0 P209PFS_BY P20%s Pin Function Control Register P20%sPFS 0xA7 8 read-write n 0x0 0x0 P209PFS_HA P20%s Pin Function Control Register P20%sPFS 0xA6 16 read-write n 0x0 0x0 P210PFS P2%s Pin Function Control Register 0xA8 32 read-write n 0x0 0x0 P210PFS_BY P2%s Pin Function Control Register P2%sPFS 0xAB 8 read-write n 0x0 0x0 P210PFS_HA P2%s Pin Function Control Register P2%sPFS 0xAA 16 read-write n 0x0 0x0 P211PFS P2%s Pin Function Control Register 0xAC 32 read-write n 0x0 0x0 P211PFS_BY P2%s Pin Function Control Register P2%sPFS 0xAF 8 read-write n 0x0 0x0 P211PFS_HA P2%s Pin Function Control Register P2%sPFS 0xAE 16 read-write n 0x0 0x0 P212PFS P2%s Pin Function Control Register 0xB0 32 read-write n 0x0 0x0 P212PFS_BY P2%s Pin Function Control Register P2%sPFS 0xB3 8 read-write n 0x0 0x0 P212PFS_HA P2%s Pin Function Control Register P2%sPFS 0xB2 16 read-write n 0x0 0x0 P213PFS P2%s Pin Function Control Register 0xB4 32 read-write n 0x0 0x0 P213PFS_BY P2%s Pin Function Control Register P2%sPFS 0xB7 8 read-write n 0x0 0x0 P213PFS_HA P2%s Pin Function Control Register P2%sPFS 0xB6 16 read-write n 0x0 0x0 P214PFS P2%s Pin Function Control Register 0xB8 32 read-write n 0x0 0x0 P214PFS_BY P2%s Pin Function Control Register P2%sPFS 0xBB 8 read-write n 0x0 0x0 P214PFS_HA P2%s Pin Function Control Register P2%sPFS 0xBA 16 read-write n 0x0 0x0 P215PFS P2%s Pin Function Control Register 0xBC 32 read-write n 0x0 0x0 P215PFS_BY P2%s Pin Function Control Register P2%sPFS 0xBF 8 read-write n 0x0 0x0 P215PFS_HA P2%s Pin Function Control Register P2%sPFS 0xBE 16 read-write n 0x0 0x0 P300PFS P300 Pin Function Control Register 0xC0 32 read-write n 0x0 0x0 P300PFS_BY P300 Pin Function Control Register P300PFS 0xC3 8 read-write n 0x0 0x0 P300PFS_HA P300 Pin Function Control Register P300PFS 0xC2 16 read-write n 0x0 0x0 P301PFS P30%s Pin Function Control Register 0xC4 32 read-write n 0x0 0x0 P301PFS_BY P30%s Pin Function Control Register P30%sPFS 0xC7 8 read-write n 0x0 0x0 P301PFS_HA P30%s Pin Function Control Register P30%sPFS 0xC6 16 read-write n 0x0 0x0 P302PFS P30%s Pin Function Control Register 0xC8 32 read-write n 0x0 0x0 P302PFS_BY P30%s Pin Function Control Register P30%sPFS 0xCB 8 read-write n 0x0 0x0 P302PFS_HA P30%s Pin Function Control Register P30%sPFS 0xCA 16 read-write n 0x0 0x0 P303PFS P30%s Pin Function Control Register 0xCC 32 read-write n 0x0 0x0 P303PFS_BY P30%s Pin Function Control Register P30%sPFS 0xCF 8 read-write n 0x0 0x0 P303PFS_HA P30%s Pin Function Control Register P30%sPFS 0xCE 16 read-write n 0x0 0x0 P304PFS P30%s Pin Function Control Register 0xD0 32 read-write n 0x0 0x0 P304PFS_BY P30%s Pin Function Control Register P30%sPFS 0xD3 8 read-write n 0x0 0x0 P304PFS_HA P30%s Pin Function Control Register P30%sPFS 0xD2 16 read-write n 0x0 0x0 P305PFS P30%s Pin Function Control Register 0xD4 32 read-write n 0x0 0x0 P305PFS_BY P30%s Pin Function Control Register P30%sPFS 0xD7 8 read-write n 0x0 0x0 P305PFS_HA P30%s Pin Function Control Register P30%sPFS 0xD6 16 read-write n 0x0 0x0 P306PFS P30%s Pin Function Control Register 0xD8 32 read-write n 0x0 0x0 P306PFS_BY P30%s Pin Function Control Register P30%sPFS 0xDB 8 read-write n 0x0 0x0 P306PFS_HA P30%s Pin Function Control Register P30%sPFS 0xDA 16 read-write n 0x0 0x0 P307PFS P30%s Pin Function Control Register 0xDC 32 read-write n 0x0 0x0 P307PFS_BY P30%s Pin Function Control Register P30%sPFS 0xDF 8 read-write n 0x0 0x0 P307PFS_HA P30%s Pin Function Control Register P30%sPFS 0xDE 16 read-write n 0x0 0x0 P308PFS P30%s Pin Function Control Register 0xE0 32 read-write n 0x0 0x0 P308PFS_BY P30%s Pin Function Control Register P30%sPFS 0xE3 8 read-write n 0x0 0x0 P308PFS_HA P30%s Pin Function Control Register P30%sPFS 0xE2 16 read-write n 0x0 0x0 P309PFS P30%s Pin Function Control Register 0xE4 32 read-write n 0x0 0x0 P309PFS_BY P30%s Pin Function Control Register P30%sPFS 0xE7 8 read-write n 0x0 0x0 P309PFS_HA P30%s Pin Function Control Register P30%sPFS 0xE6 16 read-write n 0x0 0x0 P310PFS P3%s Pin Function Control Register 0xE8 32 read-write n 0x0 0x0 P310PFS_BY P30%s Pin Function Control Register P3%sPFS 0xEB 8 read-write n 0x0 0x0 P310PFS_HA P30%s Pin Function Control Register P3%sPFS 0xEA 16 read-write n 0x0 0x0 P311PFS P3%s Pin Function Control Register 0xEC 32 read-write n 0x0 0x0 P311PFS_BY P30%s Pin Function Control Register P3%sPFS 0xEF 8 read-write n 0x0 0x0 P311PFS_HA P30%s Pin Function Control Register P3%sPFS 0xEE 16 read-write n 0x0 0x0 P312PFS P3%s Pin Function Control Register 0xF0 32 read-write n 0x0 0x0 P312PFS_BY P30%s Pin Function Control Register P3%sPFS 0xF3 8 read-write n 0x0 0x0 P312PFS_HA P30%s Pin Function Control Register P3%sPFS 0xF2 16 read-write n 0x0 0x0 P313PFS P3%s Pin Function Control Register 0xF4 32 read-write n 0x0 0x0 P313PFS_BY P30%s Pin Function Control Register P3%sPFS 0xF7 8 read-write n 0x0 0x0 P313PFS_HA P30%s Pin Function Control Register P3%sPFS 0xF6 16 read-write n 0x0 0x0 P314PFS P3%s Pin Function Control Register 0xF8 32 read-write n 0x0 0x0 P314PFS_BY P30%s Pin Function Control Register P3%sPFS 0xFB 8 read-write n 0x0 0x0 P314PFS_HA P30%s Pin Function Control Register P3%sPFS 0xFA 16 read-write n 0x0 0x0 P315PFS P3%s Pin Function Control Register 0xFC 32 read-write n 0x0 0x0 P315PFS_BY P30%s Pin Function Control Register P3%sPFS 0xFF 8 read-write n 0x0 0x0 P315PFS_HA P30%s Pin Function Control Register P3%sPFS 0xFE 16 read-write n 0x0 0x0 P400PFS P40%s Pin Function Control Register 0x100 32 read-write n 0x0 0x0 P400PFS_BY P40%s Pin Function Control Register P40%sPFS 0x103 8 read-write n 0x0 0x0 P400PFS_HA P40%s Pin Function Control Register P40%sPFS 0x102 16 read-write n 0x0 0x0 P401PFS P40%s Pin Function Control Register 0x104 32 read-write n 0x0 0x0 P401PFS_BY P40%s Pin Function Control Register P40%sPFS 0x107 8 read-write n 0x0 0x0 P401PFS_HA P40%s Pin Function Control Register P40%sPFS 0x106 16 read-write n 0x0 0x0 P402PFS P40%s Pin Function Control Register 0x108 32 read-write n 0x0 0x0 P402PFS_BY P40%s Pin Function Control Register P40%sPFS 0x10B 8 read-write n 0x0 0x0 P402PFS_HA P40%s Pin Function Control Register P40%sPFS 0x10A 16 read-write n 0x0 0x0 P403PFS P40%s Pin Function Control Register 0x10C 32 read-write n 0x0 0x0 P403PFS_BY P40%s Pin Function Control Register P40%sPFS 0x10F 8 read-write n 0x0 0x0 P403PFS_HA P40%s Pin Function Control Register P40%sPFS 0x10E 16 read-write n 0x0 0x0 P404PFS P40%s Pin Function Control Register 0x110 32 read-write n 0x0 0x0 P404PFS_BY P40%s Pin Function Control Register P40%sPFS 0x113 8 read-write n 0x0 0x0 P404PFS_HA P40%s Pin Function Control Register P40%sPFS 0x112 16 read-write n 0x0 0x0 P405PFS P40%s Pin Function Control Register 0x114 32 read-write n 0x0 0x0 P405PFS_BY P40%s Pin Function Control Register P40%sPFS 0x117 8 read-write n 0x0 0x0 P405PFS_HA P40%s Pin Function Control Register P40%sPFS 0x116 16 read-write n 0x0 0x0 P406PFS P40%s Pin Function Control Register 0x118 32 read-write n 0x0 0x0 P406PFS_BY P40%s Pin Function Control Register P40%sPFS 0x11B 8 read-write n 0x0 0x0 P406PFS_HA P40%s Pin Function Control Register P40%sPFS 0x11A 16 read-write n 0x0 0x0 P407PFS P40%s Pin Function Control Register 0x11C 32 read-write n 0x0 0x0 P407PFS_BY P40%s Pin Function Control Register P40%sPFS 0x11F 8 read-write n 0x0 0x0 P407PFS_HA P40%s Pin Function Control Register P40%sPFS 0x11E 16 read-write n 0x0 0x0 P408PFS P40%s Pin Function Control Register 0x120 32 read-write n 0x0 0x0 P408PFS_BY P40%s Pin Function Control Register P40%sPFS 0x123 8 read-write n 0x0 0x0 P408PFS_HA P40%s Pin Function Control Register P40%sPFS 0x122 16 read-write n 0x0 0x0 P409PFS P40%s Pin Function Control Register 0x124 32 read-write n 0x0 0x0 P409PFS_BY P40%s Pin Function Control Register P40%sPFS 0x127 8 read-write n 0x0 0x0 P409PFS_HA P40%s Pin Function Control Register P40%sPFS 0x126 16 read-write n 0x0 0x0 P410PFS P4%s Pin Function Control Register 0x128 32 read-write n 0x0 0x0 P410PFS_BY P4%s Pin Function Control Register P4%sPFS 0x12B 8 read-write n 0x0 0x0 P410PFS_HA P4%s Pin Function Control Register P4%sPFS 0x12A 16 read-write n 0x0 0x0 P411PFS P4%s Pin Function Control Register 0x12C 32 read-write n 0x0 0x0 P411PFS_BY P4%s Pin Function Control Register P4%sPFS 0x12F 8 read-write n 0x0 0x0 P411PFS_HA P4%s Pin Function Control Register P4%sPFS 0x12E 16 read-write n 0x0 0x0 P412PFS P4%s Pin Function Control Register 0x130 32 read-write n 0x0 0x0 P412PFS_BY P4%s Pin Function Control Register P4%sPFS 0x133 8 read-write n 0x0 0x0 P412PFS_HA P4%s Pin Function Control Register P4%sPFS 0x132 16 read-write n 0x0 0x0 P413PFS P4%s Pin Function Control Register 0x134 32 read-write n 0x0 0x0 P413PFS_BY P4%s Pin Function Control Register P4%sPFS 0x137 8 read-write n 0x0 0x0 P413PFS_HA P4%s Pin Function Control Register P4%sPFS 0x136 16 read-write n 0x0 0x0 P414PFS P4%s Pin Function Control Register 0x138 32 read-write n 0x0 0x0 P414PFS_BY P4%s Pin Function Control Register P4%sPFS 0x13B 8 read-write n 0x0 0x0 P414PFS_HA P4%s Pin Function Control Register P4%sPFS 0x13A 16 read-write n 0x0 0x0 P415PFS P4%s Pin Function Control Register 0x13C 32 read-write n 0x0 0x0 P415PFS_BY P4%s Pin Function Control Register P4%sPFS 0x13F 8 read-write n 0x0 0x0 P415PFS_HA P4%s Pin Function Control Register P4%sPFS 0x13E 16 read-write n 0x0 0x0 P500PFS P50%s Pin Function Control Register 0x140 32 read-write n 0x0 0x0 P500PFS_BY P50%s Pin Function Control Register P50%sPFS 0x143 8 read-write n 0x0 0x0 P500PFS_HA P50%s Pin Function Control Register P50%sPFS 0x142 16 read-write n 0x0 0x0 P501PFS P50%s Pin Function Control Register 0x144 32 read-write n 0x0 0x0 P501PFS_BY P50%s Pin Function Control Register P50%sPFS 0x147 8 read-write n 0x0 0x0 P501PFS_HA P50%s Pin Function Control Register P50%sPFS 0x146 16 read-write n 0x0 0x0 P502PFS P50%s Pin Function Control Register 0x148 32 read-write n 0x0 0x0 P502PFS_BY P50%s Pin Function Control Register P50%sPFS 0x14B 8 read-write n 0x0 0x0 P502PFS_HA P50%s Pin Function Control Register P50%sPFS 0x14A 16 read-write n 0x0 0x0 P503PFS P50%s Pin Function Control Register 0x14C 32 read-write n 0x0 0x0 P503PFS_BY P50%s Pin Function Control Register P50%sPFS 0x14F 8 read-write n 0x0 0x0 P503PFS_HA P50%s Pin Function Control Register P50%sPFS 0x14E 16 read-write n 0x0 0x0 P504PFS P50%s Pin Function Control Register 0x150 32 read-write n 0x0 0x0 P504PFS_BY P50%s Pin Function Control Register P50%sPFS 0x153 8 read-write n 0x0 0x0 P504PFS_HA P50%s Pin Function Control Register P50%sPFS 0x152 16 read-write n 0x0 0x0 P505PFS P50%s Pin Function Control Register 0x154 32 read-write n 0x0 0x0 P505PFS_BY P50%s Pin Function Control Register P50%sPFS 0x157 8 read-write n 0x0 0x0 P505PFS_HA P50%s Pin Function Control Register P50%sPFS 0x156 16 read-write n 0x0 0x0 P506PFS P50%s Pin Function Control Register 0x158 32 read-write n 0x0 0x0 P506PFS_BY P50%s Pin Function Control Register P50%sPFS 0x15B 8 read-write n 0x0 0x0 P506PFS_HA P50%s Pin Function Control Register P50%sPFS 0x15A 16 read-write n 0x0 0x0 P507PFS P50%s Pin Function Control Register 0x15C 32 read-write n 0x0 0x0 P507PFS_BY P50%s Pin Function Control Register P50%sPFS 0x15F 8 read-write n 0x0 0x0 P507PFS_HA P50%s Pin Function Control Register P50%sPFS 0x15E 16 read-write n 0x0 0x0 P508PFS P50%s Pin Function Control Register 0x160 32 read-write n 0x0 0x0 P508PFS_BY P50%s Pin Function Control Register P50%sPFS 0x163 8 read-write n 0x0 0x0 P508PFS_HA P50%s Pin Function Control Register P50%sPFS 0x162 16 read-write n 0x0 0x0 P509PFS P50%s Pin Function Control Register 0x164 32 read-write n 0x0 0x0 P509PFS_BY P50%s Pin Function Control Register P50%sPFS 0x167 8 read-write n 0x0 0x0 P509PFS_HA P50%s Pin Function Control Register P50%sPFS 0x166 16 read-write n 0x0 0x0 P510PFS P5%s Pin Function Control Register 0x168 32 read-write n 0x0 0x0 P510PFS_BY P5%s Pin Function Control Register P5%sPFS 0x16B 8 read-write n 0x0 0x0 P510PFS_HA P5%s Pin Function Control Register P5%sPFS 0x16A 16 read-write n 0x0 0x0 P511PFS P5%s Pin Function Control Register 0x16C 32 read-write n 0x0 0x0 P511PFS_BY P5%s Pin Function Control Register P5%sPFS 0x16F 8 read-write n 0x0 0x0 P511PFS_HA P5%s Pin Function Control Register P5%sPFS 0x16E 16 read-write n 0x0 0x0 P512PFS P5%s Pin Function Control Register 0x170 32 read-write n 0x0 0x0 P512PFS_BY P5%s Pin Function Control Register P5%sPFS 0x173 8 read-write n 0x0 0x0 P512PFS_HA P5%s Pin Function Control Register P5%sPFS 0x172 16 read-write n 0x0 0x0 P513PFS P5%s Pin Function Control Register 0x174 32 read-write n 0x0 0x0 P513PFS_BY P5%s Pin Function Control Register P5%sPFS 0x177 8 read-write n 0x0 0x0 P513PFS_HA P5%s Pin Function Control Register P5%sPFS 0x176 16 read-write n 0x0 0x0 P514PFS P5%s Pin Function Control Register 0x178 32 read-write n 0x0 0x0 P514PFS_BY P5%s Pin Function Control Register P5%sPFS 0x17B 8 read-write n 0x0 0x0 P514PFS_HA P5%s Pin Function Control Register P5%sPFS 0x17A 16 read-write n 0x0 0x0 P515PFS P5%s Pin Function Control Register 0x17C 32 read-write n 0x0 0x0 P515PFS_BY P5%s Pin Function Control Register P5%sPFS 0x17F 8 read-write n 0x0 0x0 P515PFS_HA P5%s Pin Function Control Register P5%sPFS 0x17E 16 read-write n 0x0 0x0 P600PFS P60%s Pin Function Control Register 0x180 32 read-write n 0x0 0x0 P600PFS_BY P60%s Pin Function Control Register P60%sPFS 0x183 8 read-write n 0x0 0x0 P600PFS_HA P60%s Pin Function Control Register P60%sPFS 0x182 16 read-write n 0x0 0x0 P601PFS P60%s Pin Function Control Register 0x184 32 read-write n 0x0 0x0 P601PFS_BY P60%s Pin Function Control Register P60%sPFS 0x187 8 read-write n 0x0 0x0 P601PFS_HA P60%s Pin Function Control Register P60%sPFS 0x186 16 read-write n 0x0 0x0 P602PFS P60%s Pin Function Control Register 0x188 32 read-write n 0x0 0x0 P602PFS_BY P60%s Pin Function Control Register P60%sPFS 0x18B 8 read-write n 0x0 0x0 P602PFS_HA P60%s Pin Function Control Register P60%sPFS 0x18A 16 read-write n 0x0 0x0 P603PFS P60%s Pin Function Control Register 0x18C 32 read-write n 0x0 0x0 P603PFS_BY P60%s Pin Function Control Register P60%sPFS 0x18F 8 read-write n 0x0 0x0 P603PFS_HA P60%s Pin Function Control Register P60%sPFS 0x18E 16 read-write n 0x0 0x0 P604PFS P60%s Pin Function Control Register 0x190 32 read-write n 0x0 0x0 P604PFS_BY P60%s Pin Function Control Register P60%sPFS 0x193 8 read-write n 0x0 0x0 P604PFS_HA P60%s Pin Function Control Register P60%sPFS 0x192 16 read-write n 0x0 0x0 P605PFS P60%s Pin Function Control Register 0x194 32 read-write n 0x0 0x0 P605PFS_BY P60%s Pin Function Control Register P60%sPFS 0x197 8 read-write n 0x0 0x0 P605PFS_HA P60%s Pin Function Control Register P60%sPFS 0x196 16 read-write n 0x0 0x0 P606PFS P60%s Pin Function Control Register 0x198 32 read-write n 0x0 0x0 P606PFS_BY P60%s Pin Function Control Register P60%sPFS 0x19B 8 read-write n 0x0 0x0 P606PFS_HA P60%s Pin Function Control Register P60%sPFS 0x19A 16 read-write n 0x0 0x0 P607PFS P60%s Pin Function Control Register 0x19C 32 read-write n 0x0 0x0 P607PFS_BY P60%s Pin Function Control Register P60%sPFS 0x19F 8 read-write n 0x0 0x0 P607PFS_HA P60%s Pin Function Control Register P60%sPFS 0x19E 16 read-write n 0x0 0x0 P608PFS P60%s Pin Function Control Register 0x1A0 32 read-write n 0x0 0x0 P608PFS_BY P60%s Pin Function Control Register P60%sPFS 0x1A3 8 read-write n 0x0 0x0 P608PFS_HA P60%s Pin Function Control Register P60%sPFS 0x1A2 16 read-write n 0x0 0x0 P609PFS P60%s Pin Function Control Register 0x1A4 32 read-write n 0x0 0x0 P609PFS_BY P60%s Pin Function Control Register P60%sPFS 0x1A7 8 read-write n 0x0 0x0 P609PFS_HA P60%s Pin Function Control Register P60%sPFS 0x1A6 16 read-write n 0x0 0x0 P610PFS P6%s Pin Function Control Register 0x1A8 32 read-write n 0x0 0x0 P610PFS_BY P6%s Pin Function Control Register P6%sPFS 0x1AB 8 read-write n 0x0 0x0 P610PFS_HA P6%s Pin Function Control Register P6%sPFS 0x1AA 16 read-write n 0x0 0x0 P611PFS P6%s Pin Function Control Register 0x1AC 32 read-write n 0x0 0x0 P611PFS_BY P6%s Pin Function Control Register P6%sPFS 0x1AF 8 read-write n 0x0 0x0 P611PFS_HA P6%s Pin Function Control Register P6%sPFS 0x1AE 16 read-write n 0x0 0x0 P612PFS P6%s Pin Function Control Register 0x1B0 32 read-write n 0x0 0x0 P612PFS_BY P6%s Pin Function Control Register P6%sPFS 0x1B3 8 read-write n 0x0 0x0 P612PFS_HA P6%s Pin Function Control Register P6%sPFS 0x1B2 16 read-write n 0x0 0x0 P613PFS P6%s Pin Function Control Register 0x1B4 32 read-write n 0x0 0x0 P613PFS_BY P6%s Pin Function Control Register P6%sPFS 0x1B7 8 read-write n 0x0 0x0 P613PFS_HA P6%s Pin Function Control Register P6%sPFS 0x1B6 16 read-write n 0x0 0x0 P614PFS P6%s Pin Function Control Register 0x1B8 32 read-write n 0x0 0x0 P614PFS_BY P6%s Pin Function Control Register P6%sPFS 0x1BB 8 read-write n 0x0 0x0 P614PFS_HA P6%s Pin Function Control Register P6%sPFS 0x1BA 16 read-write n 0x0 0x0 P615PFS P6%s Pin Function Control Register 0x1BC 32 read-write n 0x0 0x0 P615PFS_BY P6%s Pin Function Control Register P6%sPFS 0x1BF 8 read-write n 0x0 0x0 P615PFS_HA P6%s Pin Function Control Register P6%sPFS 0x1BE 16 read-write n 0x0 0x0 P700PFS P70%s Pin Function Control Register 0x1C0 32 read-write n 0x0 0x0 P700PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1C3 8 read-write n 0x0 0x0 P700PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1C2 16 read-write n 0x0 0x0 P701PFS P70%s Pin Function Control Register 0x1C4 32 read-write n 0x0 0x0 P701PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1C7 8 read-write n 0x0 0x0 P701PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1C6 16 read-write n 0x0 0x0 P702PFS P70%s Pin Function Control Register 0x1C8 32 read-write n 0x0 0x0 P702PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1CB 8 read-write n 0x0 0x0 P702PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1CA 16 read-write n 0x0 0x0 P703PFS P70%s Pin Function Control Register 0x1CC 32 read-write n 0x0 0x0 P703PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1CF 8 read-write n 0x0 0x0 P703PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1CE 16 read-write n 0x0 0x0 P704PFS P70%s Pin Function Control Register 0x1D0 32 read-write n 0x0 0x0 P704PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1D3 8 read-write n 0x0 0x0 P704PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1D2 16 read-write n 0x0 0x0 P705PFS P70%s Pin Function Control Register 0x1D4 32 read-write n 0x0 0x0 P705PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1D7 8 read-write n 0x0 0x0 P705PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1D6 16 read-write n 0x0 0x0 P706PFS P70%s Pin Function Control Register 0x1D8 32 read-write n 0x0 0x0 P706PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1DB 8 read-write n 0x0 0x0 P706PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1DA 16 read-write n 0x0 0x0 P707PFS P70%s Pin Function Control Register 0x1DC 32 read-write n 0x0 0x0 P707PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1DF 8 read-write n 0x0 0x0 P707PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1DE 16 read-write n 0x0 0x0 P708PFS P70%s Pin Function Control Register 0x1E0 32 read-write n 0x0 0x0 P708PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1E3 8 read-write n 0x0 0x0 P708PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1E2 16 read-write n 0x0 0x0 P709PFS P70%s Pin Function Control Register 0x1E4 32 read-write n 0x0 0x0 P709PFS_BY P70%s Pin Function Control Register P70%sPFS 0x1E7 8 read-write n 0x0 0x0 P709PFS_HA P70%s Pin Function Control Register P70%sPFS 0x1E6 16 read-write n 0x0 0x0 P710PFS P7%s Pin Function Control Register 0x1E8 32 read-write n 0x0 0x0 P710PFS_BY P7%s Pin Function Control Register P7%sPFS 0x1EB 8 read-write n 0x0 0x0 P710PFS_HA P7%s Pin Function Control Register P7%sPFS 0x1EA 16 read-write n 0x0 0x0 P711PFS P7%s Pin Function Control Register 0x1EC 32 read-write n 0x0 0x0 P711PFS_BY P7%s Pin Function Control Register P7%sPFS 0x1EF 8 read-write n 0x0 0x0 P711PFS_HA P7%s Pin Function Control Register P7%sPFS 0x1EE 16 read-write n 0x0 0x0 P712PFS P7%s Pin Function Control Register 0x1F0 32 read-write n 0x0 0x0 P712PFS_BY P7%s Pin Function Control Register P7%sPFS 0x1F3 8 read-write n 0x0 0x0 P712PFS_HA P7%s Pin Function Control Register P7%sPFS 0x1F2 16 read-write n 0x0 0x0 P713PFS P7%s Pin Function Control Register 0x1F4 32 read-write n 0x0 0x0 P713PFS_BY P7%s Pin Function Control Register P7%sPFS 0x1F7 8 read-write n 0x0 0x0 P713PFS_HA P7%s Pin Function Control Register P7%sPFS 0x1F6 16 read-write n 0x0 0x0 P714PFS P7%s Pin Function Control Register 0x1F8 32 read-write n 0x0 0x0 P714PFS_BY P7%s Pin Function Control Register P7%sPFS 0x1FB 8 read-write n 0x0 0x0 P714PFS_HA P7%s Pin Function Control Register P7%sPFS 0x1FA 16 read-write n 0x0 0x0 P715PFS P7%s Pin Function Control Register 0x1FC 32 read-write n 0x0 0x0 P715PFS_BY P7%s Pin Function Control Register P7%sPFS 0x1FF 8 read-write n 0x0 0x0 P715PFS_HA P7%s Pin Function Control Register P7%sPFS 0x1FE 16 read-write n 0x0 0x0 P800PFS P80%s Pin Function Control Register 0x200 32 read-write n 0x0 0x0 P800PFS_BY P80%s Pin Function Control Register P80%sPFS 0x203 8 read-write n 0x0 0x0 P800PFS_HA P80%s Pin Function Control Register P80%sPFS 0x202 16 read-write n 0x0 0x0 P801PFS P80%s Pin Function Control Register 0x204 32 read-write n 0x0 0x0 P801PFS_BY P80%s Pin Function Control Register P80%sPFS 0x207 8 read-write n 0x0 0x0 P801PFS_HA P80%s Pin Function Control Register P80%sPFS 0x206 16 read-write n 0x0 0x0 P802PFS P80%s Pin Function Control Register 0x208 32 read-write n 0x0 0x0 P802PFS_BY P80%s Pin Function Control Register P80%sPFS 0x20B 8 read-write n 0x0 0x0 P802PFS_HA P80%s Pin Function Control Register P80%sPFS 0x20A 16 read-write n 0x0 0x0 P803PFS P80%s Pin Function Control Register 0x20C 32 read-write n 0x0 0x0 P803PFS_BY P80%s Pin Function Control Register P80%sPFS 0x20F 8 read-write n 0x0 0x0 P803PFS_HA P80%s Pin Function Control Register P80%sPFS 0x20E 16 read-write n 0x0 0x0 P804PFS P80%s Pin Function Control Register 0x210 32 read-write n 0x0 0x0 P804PFS_BY P80%s Pin Function Control Register P80%sPFS 0x213 8 read-write n 0x0 0x0 P804PFS_HA P80%s Pin Function Control Register P80%sPFS 0x212 16 read-write n 0x0 0x0 P805PFS P80%s Pin Function Control Register 0x214 32 read-write n 0x0 0x0 P805PFS_BY P80%s Pin Function Control Register P80%sPFS 0x217 8 read-write n 0x0 0x0 P805PFS_HA P80%s Pin Function Control Register P80%sPFS 0x216 16 read-write n 0x0 0x0 P806PFS P80%s Pin Function Control Register 0x218 32 read-write n 0x0 0x0 P806PFS_BY P80%s Pin Function Control Register P80%sPFS 0x21B 8 read-write n 0x0 0x0 P806PFS_HA P80%s Pin Function Control Register P80%sPFS 0x21A 16 read-write n 0x0 0x0 P807PFS P80%s Pin Function Control Register 0x21C 32 read-write n 0x0 0x0 P807PFS_BY P80%s Pin Function Control Register P80%sPFS 0x21F 8 read-write n 0x0 0x0 P807PFS_HA P80%s Pin Function Control Register P80%sPFS 0x21E 16 read-write n 0x0 0x0 P808PFS P80%s Pin Function Control Register 0x220 32 read-write n 0x0 0x0 P808PFS_BY P80%s Pin Function Control Register P80%sPFS 0x223 8 read-write n 0x0 0x0 P808PFS_HA P80%s Pin Function Control Register P80%sPFS 0x222 16 read-write n 0x0 0x0 P809PFS P80%s Pin Function Control Register 0x224 32 read-write n 0x0 0x0 P809PFS_BY P80%s Pin Function Control Register P80%sPFS 0x227 8 read-write n 0x0 0x0 P809PFS_HA P80%s Pin Function Control Register P80%sPFS 0x226 16 read-write n 0x0 0x0 P810PFS P8%s Pin Function Control Register 0x228 32 read-write n 0x0 0x0 P810PFS_BY P8%s Pin Function Control Register P8%sPFS 0x22B 8 read-write n 0x0 0x0 P810PFS_HA P8%s Pin Function Control Register P8%sPFS 0x22A 16 read-write n 0x0 0x0 P811PFS P8%s Pin Function Control Register 0x22C 32 read-write n 0x0 0x0 P811PFS_BY P8%s Pin Function Control Register P8%sPFS 0x22F 8 read-write n 0x0 0x0 P811PFS_HA P8%s Pin Function Control Register P8%sPFS 0x22E 16 read-write n 0x0 0x0 P812PFS P8%s Pin Function Control Register 0x230 32 read-write n 0x0 0x0 P812PFS_BY P8%s Pin Function Control Register P8%sPFS 0x233 8 read-write n 0x0 0x0 P812PFS_HA P8%s Pin Function Control Register P8%sPFS 0x232 16 read-write n 0x0 0x0 P813PFS P8%s Pin Function Control Register 0x234 32 read-write n 0x0 0x0 P813PFS_BY P8%s Pin Function Control Register P8%sPFS 0x237 8 read-write n 0x0 0x0 P813PFS_HA P8%s Pin Function Control Register P8%sPFS 0x236 16 read-write n 0x0 0x0 P814PFS P8%s Pin Function Control Register 0x238 32 read-write n 0x0 0x0 P814PFS_BY P8%s Pin Function Control Register P8%sPFS 0x23B 8 read-write n 0x0 0x0 P814PFS_HA P8%s Pin Function Control Register P8%sPFS 0x23A 16 read-write n 0x0 0x0 P815PFS P8%s Pin Function Control Register 0x23C 32 read-write n 0x0 0x0 P815PFS_BY P8%s Pin Function Control Register P8%sPFS 0x23F 8 read-write n 0x0 0x0 P815PFS_HA P8%s Pin Function Control Register P8%sPFS 0x23E 16 read-write n 0x0 0x0 POEG Port Output Enable Module for GPT POEG 0x0 0x0 0x4 registers n 0x100 0x4 registers n 0x200 0x4 registers n 0x300 0x4 registers n POEGGA POEG Group A Setting Register 0x0 32 read-write n 0x0 0x0 INV GTETRGn Input Reverse 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 IOCE Enable for GPT Output-Disable Request 5 read-write 0 Disable output-disable requests from GPT disable request #0 1 Enable output-disable requests from GPT disable request #1 IOCF Detection Flag for GPT Output-Disable Request 1 read-write 0 No output-disable request from GPT disable request or comparator interrupt occurred #0 1 Output-disable request from GPT disable request or comparator interrupt occurred #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sample GTETRGn pin input level three times every PCLKL #00 01 Sample GTETRGn pin input level three times every PCLKL/8 #01 10 Sample GTETRGn pin input level three times every PCLKL/32 #10 11 Sample GTETRGn pin input level three times every PCLKL/128 #11 NFEN Noise Filter Enable 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 OSTPE Oscillation Stop Detection Enable 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 OSTPF Oscillation Stop Detection Flag 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 PIDE Port Input Detection Enable 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 PIDF Port Input Detection Flag 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 SSF Software Stop Flag 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 ST GTETRGn Input Status Flag 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 POEGGB POEG Group B Setting Register 0x100 32 read-write n 0x0 0x0 INV GTETRGn Input Reverse 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 IOCE Enable for GPT Output-Disable Request 5 read-write 0 Disable output-disable requests from GPT disable request #0 1 Enable output-disable requests from GPT disable request #1 IOCF Detection Flag for GPT Output-Disable Request 1 read-write 0 No output-disable request from GPT disable request or comparator interrupt occurred #0 1 Output-disable request from GPT disable request or comparator interrupt occurred #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sample GTETRGn pin input level three times every PCLKL #00 01 Sample GTETRGn pin input level three times every PCLKL/8 #01 10 Sample GTETRGn pin input level three times every PCLKL/32 #10 11 Sample GTETRGn pin input level three times every PCLKL/128 #11 NFEN Noise Filter Enable 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 OSTPE Oscillation Stop Detection Enable 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 OSTPF Oscillation Stop Detection Flag 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 PIDE Port Input Detection Enable 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 PIDF Port Input Detection Flag 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 SSF Software Stop Flag 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 ST GTETRGn Input Status Flag 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 POEGGC POEG Group C Setting Register 0x200 32 read-write n 0x0 0x0 INV GTETRGn Input Reverse 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 IOCE Enable for GPT Output-Disable Request 5 read-write 0 Disable output-disable requests from GPT disable request #0 1 Enable output-disable requests from GPT disable request #1 IOCF Detection Flag for GPT Output-Disable Request 1 read-write 0 No output-disable request from GPT disable request or comparator interrupt occurred #0 1 Output-disable request from GPT disable request or comparator interrupt occurred #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sample GTETRGn pin input level three times every PCLKL #00 01 Sample GTETRGn pin input level three times every PCLKL/8 #01 10 Sample GTETRGn pin input level three times every PCLKL/32 #10 11 Sample GTETRGn pin input level three times every PCLKL/128 #11 NFEN Noise Filter Enable 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 OSTPE Oscillation Stop Detection Enable 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 OSTPF Oscillation Stop Detection Flag 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 PIDE Port Input Detection Enable 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 PIDF Port Input Detection Flag 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 SSF Software Stop Flag 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 ST GTETRGn Input Status Flag 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 POEGGD POEG Group D Setting Register 0x300 32 read-write n 0x0 0x0 INV GTETRGn Input Reverse 28 read-write 0 Input GTETRGn as-is #0 1 Input GTETRGn in reverse #1 IOCE Enable for GPT Output-Disable Request 5 read-write 0 Disable output-disable requests from GPT disable request #0 1 Enable output-disable requests from GPT disable request #1 IOCF Detection Flag for GPT Output-Disable Request 1 read-write 0 No output-disable request from GPT disable request or comparator interrupt occurred #0 1 Output-disable request from GPT disable request or comparator interrupt occurred #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sample GTETRGn pin input level three times every PCLKL #00 01 Sample GTETRGn pin input level three times every PCLKL/8 #01 10 Sample GTETRGn pin input level three times every PCLKL/32 #10 11 Sample GTETRGn pin input level three times every PCLKL/128 #11 NFEN Noise Filter Enable 29 read-write 0 Disable noise filtering #0 1 Enable noise filtering #1 OSTPE Oscillation Stop Detection Enable 6 read-write 0 Disable output-disable requests from oscillation stop detection #0 1 Enable output-disable requests from oscillation stop detection #1 OSTPF Oscillation Stop Detection Flag 2 read-write 0 No output-disable request from oscillation stop detection occurred #0 1 Output-disable request from oscillation stop detection occurred #1 PIDE Port Input Detection Enable 4 read-write 0 Disable output-disable requests from the GTETRGn pins #0 1 Enable output-disable requests from the GTETRGn pins #1 PIDF Port Input Detection Flag 0 read-write 0 No output-disable request from the GTETRGn pin occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 SSF Software Stop Flag 3 read-write 0 No output-disable request from software occurred #0 1 Output-disable request from software occurred #1 ST GTETRGn Input Status Flag 16 read-only 0 GTETRGn input after filtering was 0 #0 1 GTETRGn input after filtering was 1 #1 PSCU Peripheral Security Control Unit PSCU 0x0 0x4 0x2C registers n CFSAMONA Code Flash Security Attribution Monitor Register A 0x18 32 read-only n 0x0 0x0 CFS1 Code Flash Secure area 1 15 8 read-only CFSAMONB Code Flash Security Attribution Monitor Register B 0x1C 32 read-only n 0x0 0x0 CFS2 Code Flash Secure area 2 10 13 read-only DFSAMON Data Flash Security Attribution Monitor Register 0x20 32 read-only n 0x0 0x0 DFS Data flash Secure area 10 5 read-only DLMMON Device Lifecycle Management State Monitor Register 0x2C 32 read-only n 0x0 0x0 DLMMON Device Lifecycle Management State Monitor 0 3 read-only Others Reserved 0x0 CM 0x0 0x1 SHIPPED 0x1 0x2 SSD 0x2 0x3 NSECSD 0x3 0x4 DPL 0x4 0x5 LCK_DBG 0x5 0x6 LCK_BOOT 0x6 0x7 RMA_REQ 0x7 0x8 RMA_ACK 0x8 MSSAR Module Stop Security Attribution Register 0x14 32 read-write n 0x0 0x0 MSSAR0 The MSTPCRC.MSTPC14 bit security attribution 0 read-write 0 Secure #0 1 Non-secure #1 MSSAR1 The MSTPCRA.MSTPA22 bit security attribution 1 read-write 0 Secure #0 1 Non-secure #1 MSSAR2 The MSTPCRA.MSTPA7 bit security attribution 2 read-write 0 Secure #0 1 Non-secure #1 MSSAR3 The MSTPCRA.MSTPA0 bit security attribution 3 read-write 0 Secure #0 1 Non-secure #1 PSARB Peripheral Security Attribution Register B 0x4 32 read-write n 0x0 0x0 PSARB1 CAN1 and the MSTPCRB.MSTPB1 bit security attribution 1 read-write 0 Secure #0 1 Non-secure #1 PSARB11 USBFS and the MSTPCRB.MSTPB11 bit security attribution 11 read-write 0 Secure #0 1 Non-secure #1 PSARB12 USBHS and the MSTPCRB.MSTPB12 bit security attribution 12 read-write 0 Secure #0 1 Non-secure #1 PSARB15 ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 bit security attribution 15 read-only 0 Secure #0 1 Non-secure #1 PSARB16 OSPI and the MSTPCRB.MSTPB16 bit security attribution 16 read-only 0 Secure #0 1 Non-secure #1 PSARB18 RSPI1 and the MSTPCRB.MSTPB18 bit security attribution 18 read-write 0 Secure #0 1 Non-secure #1 PSARB19 RSPI0 and the MSTPCRB.MSTPB19 bit security attribution 19 read-write 0 Secure #0 1 Non-secure #1 PSARB2 CAN0 and the MSTPCRB.MSTPB2 bit security attribution 2 read-write 0 Secure #0 1 Non-secure #1 PSARB22 SCI9 and the MSTPCRB.MSTPB22 bit security attribution 22 read-write 0 Secure #0 1 Non-secure #1 PSARB23 SCI8 and the MSTPCRB.MSTPB23 bit security attribution 23 read-write 0 Secure #0 1 Non-secure #1 PSARB24 SCI7 and the MSTPCRB.MSTPB24 bit security attribution 24 read-write 0 Secure #0 1 Non-secure #1 PSARB25 SCI6 and the MSTPCRB.MSTPB25 bit security attribution 25 read-write 0 Secure #0 1 Non-secure #1 PSARB26 SCI5 and the MSTPCRB.MSTPB26 bit security attribution 26 read-write 0 Secure #0 1 Non-secure #1 PSARB27 SCI4 and the MSTPCRB.MSTPB27 bit security attribution 27 read-write 0 Secure #0 1 Non-secure #1 PSARB28 SCI3 and the MSTPCRB.MSTPB28 bit security attribution 28 read-write 0 Secure #0 1 Non-secure #1 PSARB29 SCI2 and the MSTPCRB.MSTPB29 bit security attribution 29 read-write 0 Secure #0 1 Non-secure #1 PSARB3 CEC and the MSTPCRB.MSTPB3 bit security attribution 3 read-write 0 Secure #0 1 Non-secure #1 PSARB30 SCI1 and the MSTPCRB.MSTPB30 bit security attribution 30 read-write 0 Secure #0 1 Non-secure #1 PSARB31 SCI0 and the MSTPCRB.MSTPB31 bit security attribution 31 read-write 0 Secure #0 1 Non-secure #1 PSARB6 QSPI and the MSTPCRB.MSTPB6 bit security attribution 6 read-only 0 Secure #0 1 Non-secure #1 PSARB7 IIC2 and the MSTPCRB.MSTPB7 bit security attribution 7 read-write 0 Secure #0 1 Non-secure #1 PSARB8 IIC1 and the MSTPCRB.MSTPB8 bit security attribution 8 read-write 0 Secure #0 1 Non-secure #1 PSARB9 IIC0 and the MSTPCRB.MSTPB9 bit security attribution 9 read-write 0 Secure #0 1 Non-secure #1 PSARC Peripheral Security Attribution Register C 0x8 32 read-write n 0x0 0x0 PSARC0 CAC and the MSTPCRC.MSTPC0 bit security attribution 0 read-write 0 Secure #0 1 Non-secure #1 PSARC1 CRC and the MSTPCRC.MSTPC1 bit security attribution 1 read-write 0 Secure #0 1 Non-secure #1 PSARC12 SDHI0 and the MSTPCRC.MSTPC12 bit security attribution 12 read-write 0 Secure #0 1 Non-secure #1 PSARC13 DOC and the MSTPCRC.MSTPC13 bit security attribution 13 read-write 0 Secure #0 1 Non-secure #1 PSARC26 CANFD1 and the MSTPCRC.MSTPC26 bit security attribution 26 read-write 0 Secure #0 1 Non-secure #1 PSARC27 CANFD0 and the MSTPCRC.MSTPC27 bit security attribution 27 read-write 0 Secure #0 1 Non-secure #1 PSARC3 CTSU and the MSTPCRC.MSTPC3 bit security attribution 3 read-write 0 Secure #0 1 Non-secure #1 PSARC31 TSIP and the MSTPCRC.MSTPC31 bit security attribution 31 read-write 0 Secure #0 1 Non-secure #1 PSARC8 SSIE0 and the MSTPCRC.MSTPC8 bit security attribution 8 read-write 0 Secure #0 1 Non-secure #1 PSARD Peripheral Security Attribution Register D 0xC 32 read-write n 0x0 0x0 PSARD0 AGT3 and the MSTPCRD.MSTPD0 bit security attribution 0 read-write 0 Secure #0 1 Non-secure #1 PSARD1 AGT2 and the MSTPCRD.MSTPD1 bit security attribution 1 read-write 0 Secure #0 1 Non-secure #1 PSARD11 PGI3 and the MSTPCRD.MSTPD11 bit security attribution 11 read-write 0 Secure #0 1 Non-secure #1 PSARD12 PGI2 and the MSTPCRD.MSTPD12 bit security attribution 12 read-write 0 Secure #0 1 Non-secure #1 PSARD13 PGI1 and the MSTPCRD.MSTPD13 bit security attribution 13 read-write 0 Secure #0 1 Non-secure #1 PSARD14 PGI0 and the MSTPCRD.MSTPD14 bit security attribution 14 read-write 0 Secure #0 1 Non-secure #1 PSARD15 ADC1 and the MSTPCRD.MSTPD15 bit security attribution 15 read-write 0 Secure #0 1 Non-secure #1 PSARD16 ADC0 and the MSTPCRD.MSTPD16 bit security attribution 16 read-write 0 Secure #0 1 Non-secure #1 PSARD2 AGT1 and the MSTPCRD.MSTPD2 bit security attribution 2 read-write 0 Secure #0 1 Non-secure #1 PSARD20 DAC12 and the MSTPCRD.MSTPD20 bit security attribution 20 read-write 0 Secure #0 1 Non-secure #1 PSARD22 TSN and the MSTPCRD.MSTPD22 bit security attribution 22 read-write 0 Secure #0 1 Non-secure #1 PSARD3 AGT0 and the MSTPCRD.MSTPD3 bit security attribution 3 read-write 0 Secure #0 1 Non-secure #1 PSARE Peripheral Security Attribution Register E 0x10 32 read-write n 0x0 0x0 PSARE0 WDT security attribution 0 read-write 0 Secure #0 1 Non-secure #1 PSARE1 IWDT security attribution 1 read-write 0 Secure #0 1 Non-secure #1 PSARE14 AGT5 and the MSTPCRE.MSTPE14 bit security attribution 14 read-write 0 Secure #0 1 Non-secure #1 PSARE15 AGT4 and the MSTPCRE.MSTPE15 bit security attribution 15 read-write 0 Secure #0 1 Non-secure #1 PSARE2 RTC security attribution 2 read-write 0 Secure #0 1 Non-secure #1 PSARE22 GPT9 and the MSTPCRE.MSTPE22 bit security attribution 22 read-write 0 Secure #0 1 Non-secure #1 PSARE23 GPT8 and the MSTPCRE.MSTPE23 bit security attribution 23 read-write 0 Secure #0 1 Non-secure #1 PSARE24 GPT7 and the MSTPCRE.MSTPE24 bit security attribution 24 read-write 0 Secure #0 1 Non-secure #1 PSARE25 GPT6 and the MSTPCRE.MSTPE25 bit security attribution 25 read-write 0 Secure #0 1 Non-secure #1 PSARE26 GPT5 and the MSTPCRE.MSTPE26 bit security attribution 26 read-write 0 Secure #0 1 Non-secure #1 PSARE27 GPT4 and the MSTPCRE.MSTPE27 bit security attribution 27 read-write 0 Secure #0 1 Non-secure #1 PSARE28 GPT3 and the MSTPCRE.MSTPE28 bit security attribution 28 read-write 0 Secure #0 1 Non-secure #1 PSARE29 GPT2 and the MSTPCRE.MSTPE29 bit security attribution 29 read-write 0 Secure #0 1 Non-secure #1 PSARE30 GPT1 and the MSTPCRE.MSTPE30 bit security attribution 30 read-write 0 Secure #0 1 Non-secure #1 PSARE31 GPT0 and the MSTPCRE.MSTPE31 bit security attribution 31 read-write 0 Secure #0 1 Non-secure #1 SSAMONA SRAM Security Attribution Monitor Register A 0x24 32 read-only n 0x0 0x0 SS1 SRAM Secure area 1 13 7 read-only SSAMONB SRAM Security Attribution Monitor Register B 0x28 32 read-only n 0x0 0x0 SS2 SRAM secure area 2 10 10 read-only QSPI Quad Serial Peripheral Interface QSPI 0x0 0x0 0x1C registers n 0x20 0xC registers n 0x30 0x8 registers n 0x804 0x4 registers n SFMCMD Communication Mode Control Register 0x14 32 read-write n 0x0 0x0 DCOM Mode select for communication with the SPI bus 0 read-write 0 ROM access mode #0 1 Direct communication mode #1 SFMCNT1 External QSPI Address Register 0x804 32 read-write n 0x0 0x0 QSPI_EXT Bank switching address 26 5 read-write SFMCOM Communication Port Register 0x10 32 read-write n 0x0 0x0 SFMD Port select for direct communication with the SPI bus 0 7 read-write SFMCST Communication Status Register 0x18 32 read-write n 0x0 0x0 COMBSY SPI bus cycle completion state in direct communication 0 read-only 0 No serial transfer being processed #0 1 Serial transfer being processed #1 EROMR ROM access detection status in direct communication mode 7 read-write 0 ROM access not detected #0 1 ROM access detected #1 SFMPMD Port Control Register 0x34 32 read-write n 0x0 0x0 SFMWPL WP pin level specification 2 read-write 0 Low level #0 1 High level #1 SFMSAC Address Mode Control Register 0x24 32 read-write n 0x0 0x0 SFM4BC Default instruction code select, when the serial interface address width is 4 bytes 4 read-write 0 Do not use 4-byte address read instruction code #0 1 Use 4-byte address read instruction code #1 SFMAS Number of address bytes select for the serial interface 0 1 read-write 00 1 byte #00 01 2 bytes #01 10 3 bytes #10 11 4 bytes #11 SFMSDC Dummy Cycle Control Register 0x28 32 read-write n 0x0 0x0 SFMDN Number of dummy cycles select for Fast Read instructions 0 3 read-write 0x0 Default dummy cycles for each instruction: - Fast Read Quad I/O: 6 QSPCLK - Fast Read Quad Output: 8 QSPCLK - Fast Read Dual I/O: 4 QSPCLK - Fast Read Dual Output: 8 QSPCLK - Fast Read: 8 QSPCLK 0x0 0x1 3 QSPCLK 0x1 0x2 4 QSPCLK 0x2 0x3 5 QSPCLK 0x3 0x4 6 QSPCLK 0x4 0x5 7 QSPCLK 0x5 0x6 8 QSPCLK 0x6 0x7 9 QSPCLK 0x7 0x8 10 QSPCLK 0x8 0x9 11 QSPCLK 0x9 0xA 12 QSPCLK 0xa 0xB 13 QSPCLK 0xb 0xC 14 QSPCLK 0xc 0xD 15 QSPCLK 0xd 0xE 16 QSPCLK 0xe 0xF 17 QSPCLK 0xf SFMXD Mode data for serial flash (Controls XIP mode.) 8 7 read-write SFMXEN XIP mode permission 7 read-write 0 Prohibit XIP mode #0 1 Permit XIP mode #1 SFMXST XIP mode status 6 read-only 0 Normal (non-XIP) mode #0 1 XIP mode #1 SFMSIC Instruction Code Register 0x20 32 read-write n 0x0 0x0 SFMCIC Serial flash instruction code to substitute 0 7 read-write SFMSKC Clock Control Register 0x8 32 read-write n 0x0 0x0 SFMDTY Duty ratio correction function select for the QSPCLK signal 5 read-write 0 Make no correction #0 1 Delay the rising of the QSPCLK signal by 0.5 PCLKH cycles (Valid when PCLKH is multiplied by an odd number.) #1 SFMDV Serial interface reference cycle select. (Pay attention to irregularities.) 0 4 read-write 0x00 2 PCLKH 0x00 0x01 3 PCLKH (multiplied by an odd number) 0x01 0x02 4 PCLKH 0x02 0x03 5 PCLKH (multiplied by an odd number) 0x03 0x04 6 PCLKH 0x04 0x05 7 PCLKH (multiplied by an odd number) 0x05 0x06 8 PCLKH 0x06 0x07 9 PCLKH (multiplied by an odd number) 0x07 0x08 10 PCLKH 0x08 0x09 11 PCLKH (multiplied by an odd number) 0x09 0x0A 12 PCLKH 0x0a 0x0B 13 PCLKH (multiplied by an odd number) 0x0b 0x0C 14 PCLKH 0x0c 0x0D 15 PCLKH (multiplied by an odd number) 0x0d 0x0E 16 PCLKH 0x0e 0x0F 17 PCLKH (multiplied by an odd number) 0x0f 0x10 18 PCLKH 0x10 0x11 20 PCLKH 0x11 0x12 22 PCLKH 0x12 0x13 24 PCLKH 0x13 0x14 26 PCLKH 0x14 0x15 28 PCLKH 0x15 0x16 30 PCLKH 0x16 0x17 32 PCLKH 0x17 0x18 34 PCLKH 0x18 0x19 36 PCLKH 0x19 0x1A 38 PCLKH 0x1a 0x1B 40 PCLKH 0x1b 0x1C 42 PCLKH 0x1c 0x1D 44 PCLKH 0x1d 0x1E 46 PCLKH 0x1e 0x1F 48 PCLKH 0x1f SFMSMD Transfer Mode Control Register 0x0 32 read-write n 0x0 0x0 SFMCCE Read instruction code select 15 read-write 0 Set default instruction code for each instruction #0 1 Write instruction code in the SFMSIC register #1 SFMMD3 SPI mode select. Initial value determined by input to CFGMD3 8 read-write 0 SPI mode 0 #0 1 SPI mode 3 #1 SFMOEX Extension select for the I/O buffer output enable signal for the serial interface 9 read-write 0 Do not extend #0 1 Extend by 1 QSPCLK #1 SFMOHW Hold time adjustment for serial transmission 10 read-write 0 Do not extend high-level width of QSPCLK during transmission #0 1 Extend high-level width of QSPCLK by 1 PCLKH during transmission #1 SFMOSW Setup time adjustment for serial transmission 11 read-write 0 Do not extend low-level width of QSPCLK during transmission #0 1 Extend low-level width of QSPCLK by 1 PCLKH during transmission #1 SFMPAE Function select for stopping prefetch at locations other than on byte boundaries 7 read-write 0 Disable function #0 1 Enable function #1 SFMPFE Prefetch function select 6 read-write 0 Disable function #0 1 Enable function #1 SFMRM Serial interface read mode select 0 2 read-write Others Setting prohibited 000 Standard Read #000 001 Fast Read #001 010 Fast Read Dual Output #010 011 Fast Read Dual I/O #011 100 Fast Read Quad Output #100 101 Fast Read Quad I/O #101 SFMSE QSSL extension function select after SPI bus access 4 1 read-write 00 Do not extend QSSL #00 01 Extend QSSL by 33 QSPCLK #01 10 Extend QSSL by 129 QSPCLK #10 11 Extend QSSL infinitely #11 SFMSPC SPI Protocol Control Register 0x30 32 read-write n 0x0 0x0 SFMSDE Minimum time select for input/output switch, when Dual SPI or Quad SPI protocol is selected and in standard read mode 4 read-write 0 Do not allocate minimum switch time #0 1 Allocate minimum switch time equivalent to 1 QSPCLK #1 SFMSPI SPI protocol select 0 1 read-write 00 Single/Extended SPI protocol #00 01 Dual SPI protocol #01 10 Quad SPI protocol #10 11 Setting prohibited #11 SFMSSC Chip Selection Control Register 0x4 32 read-write n 0x0 0x0 SFMSHD QSSL signal release timing select 4 read-write 0 Release QSSL 0.5 QSPCLK cycles after the last rising edge of QSPCLK #0 1 Release QSSL 1.5 QSPCLK cycles after the last rising edge of QSPCLK #1 SFMSLD QSSL signal output timing select 5 read-write 0 Output QSSL 0.5 QSPCLK cycles before the first rising edge of QSPCLK #0 1 Output QSSL 1.5 QSPCLK cycles before the first rising edge of QSPCLK #1 SFMSW Minimum high-level width select for QSSL signal 0 3 read-write 0x0 1 QSPCLK 0x0 0x1 2 QSPCLK 0x1 0x2 3 QSPCLK 0x2 0x3 4 QSPCLK 0x3 0x4 5 QSPCLK 0x4 0x5 6 QSPCLK 0x5 0x6 7 QSPCLK 0x6 0x7 8 QSPCLK 0x7 0x8 9 QSPCLK 0x8 0x9 10 QSPCLK 0x9 0xA 11 QSPCLK 0xa 0xB 12 QSPCLK 0xb 0xC 13 QSPCLK 0xc 0xD 14 QSPCLK 0xd 0xE 15 QSPCLK 0xe 0xF 16 QSPCLK 0xf SFMSST Status Register 0xC 32 read-only n 0x0 0x0 PFCNT Number of bytes of prefetched data 0 4 read-only Others Reserved 0x00 0 byte 0x00 0x01 1 byte 0x01 0x02 2 bytes 0x02 0x03 3 bytes 0x03 0x04 4 bytes 0x04 0x05 5 bytes 0x05 0x06 6 bytes 0x06 0x07 7 bytes 0x07 0x08 8 bytes 0x08 0x09 9 bytes 0x09 0x0A 10 bytes 0x0a 0x0B 11 bytes 0x0b 0x0C 12 bytes 0x0c 0x0D 13 bytes 0x0d 0x0E 14 bytes 0x0e 0x0F 15 bytes 0x0f 0x10 16 bytes 0x10 0x11 17 bytes 0x11 0x12 18 bytes 0x12 PFFUL Prefetch buffer state 6 read-only 0 Prefetch buffer has free space #0 1 Prefetch buffer is full #1 PFOFF Prefetch function operating state 7 read-only 0 Prefetch function operating #0 1 Prefetch function not enabled or not operating #1 RMPU Renesas Memory Protection Unit RMPU 0x0 0x0 0x2 registers n 0x100 0x2 registers n 0x104 0x2 registers n 0x108 0x2 registers n 0x10C 0x2 registers n 0x200 0x88 registers n 0x4 0x2 registers n 0x500 0x2 registers n 0x504 0x2 registers n 0x508 0x2 registers n 0x600 0x44 registers n 0xD00 0x2 registers n 0xD04 0xE registers n 0xD14 0xC registers n MMPUACDMAC0 MMPU Access Control Register for DMAC 0x200 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACDMAC1 MMPU Access Control Register for DMAC 0x210 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACDMAC2 MMPU Access Control Register for DMAC 0x220 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACDMAC3 MMPU Access Control Register for DMAC 0x230 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACDMAC4 MMPU Access Control Register for DMAC 0x240 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACDMAC5 MMPU Access Control Register for DMAC 0x250 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACDMAC6 MMPU Access Control Register for DMAC 0x260 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACDMAC7 MMPU Access Control Register for DMAC 0x270 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 DMAC Region n unit is disabled #0 1 DMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACEDMAC0 MMPU Access Control Register for EDMAC 0x600 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 EDMAC Region n unit is disabled #0 1 EDMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACEDMAC1 MMPU Access Control Register for EDMAC 0x610 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 EDMAC Region n unit is disabled #0 1 EDMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACEDMAC2 MMPU Access Control Register for EDMAC 0x620 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 EDMAC Region n unit is disabled #0 1 EDMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACEDMAC3 MMPU Access Control Register for EDMAC 0x630 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 EDMAC Region n unit is disabled #0 1 EDMAC Region n unit is enabled #1 RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUEDMAC0 MMPU End Address Register for DMAC 0x208 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUEDMAC1 MMPU End Address Register for DMAC 0x218 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUEDMAC2 MMPU End Address Register for DMAC 0x228 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUEDMAC3 MMPU End Address Register for DMAC 0x238 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUEDMAC4 MMPU End Address Register for DMAC 0x248 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUEDMAC5 MMPU End Address Register for DMAC 0x258 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUEDMAC6 MMPU End Address Register for DMAC 0x268 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUEDMAC7 MMPU End Address Register for DMAC 0x278 32 read-write n 0x0 0x0 MMPUE Region end address register 5 26 read-write MMPUENDMAC MMPU Enable Register for DMAC 0x100 16 read-write n 0x0 0x0 ENABLE Bus Master MPU of DMAC enable 0 read-write 0 Bus Master MPU of DMAC is disabled. #0 1 Bus Master MPU of DMAC is enabled. #1 KEY This bit is used to enable or disable writing of the ENABLE bit. 8 7 write-only MMPUENEDMAC MMPU Enable Register for EDMAC 0x500 16 read-write n 0x0 0x0 ENABLE Bus Master MPU of EDMAC enable 0 read-write 0 Bus Master MPU of EDMAC is disabled. #0 1 Bus Master MPU of EDMAC is enabled. #1 KEY This bit is used to enable or disable writing of the ENABLE bit. 8 7 write-only MMPUENPTDMAC MMPU Enable Protect Register for DMAC 0x104 16 read-write n 0x0 0x0 KEY This bit is used to enable or disable writing of the PROTECT bit. 8 7 write-only PROTECT Protection of register 0 read-write 0 MMPUENDMAC register writing is possible. #0 1 MMPUENDMAC register writing is protected. Read is possible. #1 MMPUENPTEDMAC MMPU Enable Protect Register for EDMAC 0x504 16 read-write n 0x0 0x0 KEY This bit is used to enable or disable writing of the PROTECT bit. 8 7 write-only PROTECT Protection of register 0 read-write 0 MMPUENEDMAC register writing is possible. #0 1 MMPUENEDMAC register writing is protected. Read is possible. #1 MMPUOAD MMPU Operation After Detection Register 0x0 16 read-write n 0x0 0x0 KEY This bit is used to enable or disable writing of the OAD bit. 8 7 write-only OAD Operation after detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 MMPUOADPT MMPU Operation After Detection Protect Register 0x4 16 read-write n 0x0 0x0 KEY Key code 8 7 write-only PROTECT Protection of register 0 read-write 0 MMPUOAD register writing is possible. #0 1 MMPUOAD register writing is protected. Read is possible. #1 MMPURPTDMAC MMPU Regions Protect Register for DMAC 0x108 16 read-write n 0x0 0x0 KEY This bit is used to enable or disable writing of the PROTECT bit. 8 7 write-only PROTECT Protection of register 0 read-write 0 Bus Master MPU register for DMAC writing is possible. #0 1 Bus Master MPU register for DMAC writing is protected. Read is possible. #1 MMPURPTDMAC_SEC MMPU Regions Protect register for DMAC Secure 0x10C 16 read-write n 0x0 0x0 KEY This bit is used to enable or disable writing of the PROTECT bit. 8 7 write-only PROTECT Protection of register 0 read-write 0 Bus Master MPU register for DMAC Secure writing is possible. #0 1 Bus Master MPU register for DMAC Secure writing is protected. Read is possible. #1 MMPURPTEDMAC MMPU Regions Protect Register for EDMAC 0x508 16 read-write n 0x0 0x0 KEY This bit is used to enable or disable writing of the PROTECT bit. 8 7 write-only PROTECT Protection of register 0 read-write 0 Bus Master MPU register for EDMAC writing is possible. #0 1 Bus Master MPU register for EDMAC writing is protected. Read is possible. #1 MMPUSDMAC0 MMPU Start Address Register for DMAC 0x204 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSDMAC1 MMPU Start Address Register for DMAC 0x214 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSDMAC2 MMPU Start Address Register for DMAC 0x224 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSDMAC3 MMPU Start Address Register for DMAC 0x234 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSDMAC4 MMPU Start Address Register for DMAC 0x244 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSDMAC5 MMPU Start Address Register for DMAC 0x254 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSDMAC6 MMPU Start Address Register for DMAC 0x264 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSDMAC7 MMPU Start Address Register for DMAC 0x274 32 read-write n 0x0 0x0 MMPUS Region start address register 5 26 read-write MMPUSEDMAC0 MMPU Start Address Register for EDMAC 0x604 32 read-write n 0x0 0x0 MMPUS Region start address register for EDMAC 5 26 read-write MMPUSEDMAC1 MMPU Start Address Register for EDMAC 0x614 32 read-write n 0x0 0x0 MMPUS Region start address register for EDMAC 5 26 read-write MMPUSEDMAC2 MMPU Start Address Register for EDMAC 0x624 32 read-write n 0x0 0x0 MMPUS Region start address register for EDMAC 5 26 read-write MMPUSEDMAC3 MMPU Start Address Register for EDMAC 0x634 32 read-write n 0x0 0x0 MMPUS Region start address register for EDMAC 5 26 read-write MSPMPUCTL Stack Pointer Monitor Access Control Register 0xD04 16 read-write n 0x0 0x0 ENABLE Stack Pointer Monitor Enable 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 ERROR Stack Pointer Monitor Error Flag 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 MSPMPUEA Main Stack Pointer (MSP) Monitor End Address Register 0xD0C 32 read-write n 0x0 0x0 MSPMPUEA Region End Address 0 31 read-write MSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD00 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write OAD Operation after Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 MSPMPUPT Stack Pointer Monitor Protection Register 0xD06 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write PROTECT Protection of Register 0 read-write 0 Stack pointer monitor register writes are permitted. #0 1 Stack pointer monitor register writes are protected. Reads are permitted #1 MSPMPUSA Main Stack Pointer (MSP) Monitor Start Address Register 0xD08 32 read-write n 0x0 0x0 MSPMPUSA Region Start Address 0 31 read-write PSPMPUCTL Stack Pointer Monitor Access Control Register 0xD14 16 read-write n 0x0 0x0 ENABLE Stack Pointer Monitor Enable 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 ERROR Stack Pointer Monitor Error Flag 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 PSPMPUEA Process Stack Pointer (PSP) Monitor End Address Register 0xD1C 32 read-write n 0x0 0x0 PSPMPUEA Region End Address 0 31 read-write PSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0xD10 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write OAD Operation after Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 PSPMPUPT Stack Pointer Monitor Protection Register 0xD16 16 read-write n 0x0 0x0 KEY Key Code 8 7 read-write PROTECT Protection of Register 0 read-write 0 Stack pointer monitor register writes are permitted. #0 1 Stack pointer monitor register writes are protected. Reads are permitted #1 PSPMPUSA Process Stack Pointer (PSP) Monitor Start Address Register 0xD18 32 read-write n 0x0 0x0 PSPMPUSA Region Start Address 0 31 read-write RTC Realtime Clock RTC 0x0 0x0 0x1 registers n 0x18 0x4 registers n 0x1C 0x3 registers n 0x2 0x8 registers n 0x22 0x1 registers n 0x24 0x1 registers n 0x28 0x1 registers n 0x2A 0x5 registers n 0x40 0x6 registers n 0x52 0x3A registers n 0xA 0x1 registers n 0xC 0x1 registers n 0xE 0xA registers n BCNT0 Binary Counter %s 0x2 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT0AER Binary Counter %s Alarm Enable Register 0x18 8 read-write n 0x0 0x0 ENB Setting the alarm enable associated with the 32-bit binary counter 0 7 read-write BCNT0AR Binary Counter %s Alarm Register 0x10 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write BCNT0CP0 BCNT0 Capture Register %s 0x52 8 read-only n 0x0 0x0 BCNT0CP1 BCNT0 Capture Register %s 0x62 8 read-only n 0x0 0x0 BCNT0CP2 BCNT0 Capture Register %s 0x72 8 read-only n 0x0 0x0 BCNT1 Binary Counter %s 0x4 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT1AER Binary Counter %s Alarm Enable Register 0x1A 8 read-write n 0x0 0x0 ENB Setting the alarm enable associated with the 32-bit binary counter 0 7 read-write BCNT1AR Binary Counter %s Alarm Register 0x12 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write BCNT1CP0 BCNT1 Capture Register %s 0x54 8 read-only n 0x0 0x0 BCNT1CP1 BCNT1 Capture Register %s 0x64 8 read-only n 0x0 0x0 BCNT1CP2 BCNT1 Capture Register %s 0x74 8 read-only n 0x0 0x0 BCNT2 Binary Counter %s 0x6 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT2AER Binary Counter 2 Alarm Enable Register 0x1C 16 read-write n 0x0 0x0 ENB Set the alarm enable associated with the 32-bit binary counter 0 7 read-write BCNT2AR Binary Counter %s Alarm Register 0x14 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write BCNT2CP0 BCNT2 Capture Register %s 0x56 8 read-only n 0x0 0x0 BCNT2CP1 BCNT2 Capture Register %s 0x66 8 read-only n 0x0 0x0 BCNT2CP2 BCNT2 Capture Register %s 0x76 8 read-only n 0x0 0x0 BCNT3 Binary Counter %s 0x8 8 read-write n 0x0 0x0 BCNT Binary Counter 0 7 read-write BCNT3AER Binary Counter 3 Alarm Enable Register 0x1E 8 read-write n 0x0 0x0 ENB Setting the alarm enable associated with the 32-bit binary counter 0 7 read-write BCNT3AR Binary Counter %s Alarm Register 0x16 8 read-write n 0x0 0x0 BCNTAR Alarm register associated with the 32-bit binary counter 0 7 read-write BCNT3CP0 BCNT3 Capture Register %s 0x5A 8 read-only n 0x0 0x0 BCNT3CP1 BCNT3 Capture Register %s 0x6A 8 read-only n 0x0 0x0 BCNT3CP2 BCNT3 Capture Register %s 0x7A 8 read-only n 0x0 0x0 R64CNT 64-Hz Counter 0x0 8 read-only n 0x0 0x0 F16HZ This bit indicates the 16-Hz state of the sub-second digit. 2 read-only F1HZ This bit indicates the 1-Hz state of the sub-second digit. 6 read-only F2HZ This bit indicates the 2-Hz state of the sub-second digit. 5 read-only F32HZ This bit indicates the 32-Hz state of the sub-second digit. 1 read-only F4HZ This bit indicates the 4-Hz state of the sub-second digit. 4 read-only F64HZ This bit indicates the 64-Hz state of the sub-second digit. 0 read-only F8HZ This bit indicates the 8-Hz state of the sub-second digit. 3 read-only RADJ Time Error Adjustment Register 0x2E 8 read-write n 0x0 0x0 ADJ Adjustment Value 0 5 read-write PMADJ Plus-Minus 6 1 read-write 00 Do not perform adjustment. #00 01 Adjustment is performed by the addition to the prescaler #01 10 Adjustment is performed by the subtraction from the prescaler #10 11 Setting prohibited. #11 RCR1 RTC Control Register 1 0x22 8 read-write n 0x0 0x0 AIE Alarm Interrupt Enable 0 read-write 0 Disable alarm interrupt requests #0 1 Enable alarm interrupt requests #1 CIE Carry Interrupt Enable 1 read-write 0 Disable carry interrupt requests #0 1 Enable carry interrupt requests #1 PES Periodic Interrupt Select 4 3 read-write Others Do not generate periodic interrupts 0x6 Generate periodic interrupt every 1/256 second 0x6 0x7 Generate periodic interrupt every 1/128 second 0x7 0x8 Generate periodic interrupt every 1/64 second 0x8 0x9 Generate periodic interrupt every 1/32 second 0x9 0xA Generate periodic interrupt every 1/16 second 0xa 0xB Generate periodic interrupt every 1/8 second 0xb 0xC Generate periodic interrupt every 1/4 second 0xc 0xD Generate periodic interrupt every 1/2 second 0xd 0xE Generate periodic interrupt every 1 second 0xe 0xF Generate periodic interrupt every 2 seconds 0xf PIE Periodic Interrupt Enable 2 read-write 0 Disable periodic interrupt requests #0 1 Enable periodic interrupt requests #1 RTCOS RTCOUT Output Select 3 read-write 0 Outputs 1 Hz on RTCOUT #0 1 Outputs 64 Hz RTCOUT #1 RCR2 RTC Control Register 2 0x24 8 read-write n 0x0 0x0 AADJE Automatic Adjustment Enable 4 read-write 0 Disable automatic adjustment #0 1 Enable automatic adjustment #1 AADJP Automatic Adjustment Period Select 5 read-write 0 Add or subtract RADJ.ADJ [5:0] bits from prescaler count value every 32 seconds #0 1 Add or subtract RADJ.ADJ [5:0] bits from prescaler countvalue every 8 seconds. #1 CNTMD Count Mode Select 7 read-write 0 Calendar count mode #0 1 Binary count mode #1 RESET RTC Software Reset 1 read-write 0 In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or an RTC software reset has completed. #0 1 In writing: Initialize the prescaler and target registers for RTC software reset. In reading: RTC software reset in progress. #1 RTCOE RTCOUT Output Enable 3 read-write 0 Disable RTCOUT output #0 1 Enable RTCOUT output #1 START Start 0 read-write 0 Stop counter and prescaler #0 1 Operate counter, and prescaler normally #1 RCR4 RTC Control Register 4 0x28 8 read-write n 0x0 0x0 RCKSEL Count Source Select 0 read-write 0 Sub-clock oscillator is selected #0 1 LOCO is selected #1 RDAYAR Date Alarm Register (in Calendar Count Mode) 0x18 8 read-write n 0x0 0x0 DATE1 1 Day 0 3 read-write DATE10 10 Days 4 1 read-write ENB ENB 7 read-write 0 Do not compare register value with RDAYCNT counter value #0 1 Compare register value with RDAYCNT counter value #1 RDAYCNT Day Counter 0xA 8 read-write n 0x0 0x0 DATE1 1-Day Count 0 3 read-write DATE10 10-Day Count 4 1 read-write RDAYCP0 Date Capture Register %s BCNT3CP%s 0x5A 8 read-only n 0x0 0x0 DATE1 1-Day Capture 0 3 read-only DATE10 10-Day Capture 4 1 read-only RDAYCP1 Date Capture Register %s BCNT3CP%s 0x6A 8 read-only n 0x0 0x0 DATE1 1-Day Capture 0 3 read-only DATE10 10-Day Capture 4 1 read-only RDAYCP2 Date Capture Register %s BCNT3CP%s 0x7A 8 read-only n 0x0 0x0 DATE1 1-Day Capture 0 3 read-only DATE10 10-Day Capture 4 1 read-only RFRH Frequency Register H 0x2A 16 read-write n 0x0 0x0 RFC16 Write 0 before writing to the RFRL register after a cold start. 0 read-write RFRL Frequency Register L 0x2C 16 read-write n 0x0 0x0 RFC Frequency Comparison Value 0 15 read-write RHRAR Hour Alarm Register (in Calendar Count Mode) 0x14 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RHRCNT counter value #0 1 Compare register value with RHRCNT counter value #1 HR1 1 Hour 0 3 read-write HR10 10 Hours 4 1 read-write PM AM/PM select for alarm setting. 6 read-write 0 AM #0 1 PM #1 RHRCNT Hour Counter (in Calendar Count Mode) 0x6 8 read-write n 0x0 0x0 HR1 1-Hour Count 0 3 read-write HR10 10-Hour Count 4 1 read-write PM AM/PM select for time counter setting. 6 read-write 0 AM #0 1 PM #1 RHRCP0 Hour Capture Register %s BCNT2CP%s 0x56 8 read-only n 0x0 0x0 HR1 1-Hour Capture 0 3 read-only HR10 10-Hour Capture 4 1 read-only PM PM 6 read-only 0 AM #0 1 PM #1 RHRCP1 Hour Capture Register %s BCNT2CP%s 0x66 8 read-only n 0x0 0x0 HR1 1-Hour Capture 0 3 read-only HR10 10-Hour Capture 4 1 read-only PM PM 6 read-only 0 AM #0 1 PM #1 RHRCP2 Hour Capture Register %s BCNT2CP%s 0x76 8 read-only n 0x0 0x0 HR1 1-Hour Capture 0 3 read-only HR10 10-Hour Capture 4 1 read-only PM PM 6 read-only 0 AM #0 1 PM #1 RMINAR Minute Alarm Register (in Calendar Count Mode) 0x12 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RMINCNT counter value #0 1 Compare register value with RMINCNT counter value #1 MIN1 1 Minute 0 3 read-write MIN10 10 Minutes 4 2 read-write RMINCNT Minute Counter (in Calendar Count Mode) 0x4 8 read-write n 0x0 0x0 MIN1 1-Minute Count 0 3 read-write MIN10 10-Minute Count 4 2 read-write RMINCP0 Minute Capture Register %s BCNT1CP%s 0x54 8 read-only n 0x0 0x0 MIN1 1-Minute Capture 0 3 read-only MIN10 10-Minute Capture 4 2 read-only RMINCP1 Minute Capture Register %s BCNT1CP%s 0x64 8 read-only n 0x0 0x0 MIN1 1-Minute Capture 0 3 read-only MIN10 10-Minute Capture 4 2 read-only RMINCP2 Minute Capture Register %s BCNT1CP%s 0x74 8 read-only n 0x0 0x0 MIN1 1-Minute Capture 0 3 read-only MIN10 10-Minute Capture 4 2 read-only RMONAR Month Alarm Register (in Calendar Count Mode) 0x1A 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RMONCNT counter value #0 1 Compare register value with RMONCNT counter value #1 MON1 1 Month 0 3 read-write MON10 10 Months 4 read-write RMONCNT Month Counter 0xC 8 read-write n 0x0 0x0 MON1 1-Month Count 0 3 read-write MON10 10-Month Count 4 read-write RMONCP0 Month Capture Register %s 0x5C 8 read-only n 0x0 0x0 MON1 1-Month Capture 0 3 read-only MON10 10-Month Capture 4 read-only RMONCP1 Month Capture Register %s 0x6C 8 read-only n 0x0 0x0 MON1 1-Month Capture 0 3 read-only MON10 10-Month Capture 4 read-only RMONCP2 Month Capture Register %s 0x7C 8 read-only n 0x0 0x0 MON1 1-Month Capture 0 3 read-only MON10 10-Month Capture 4 read-only RSECAR Second Alarm Register (in Calendar Count Mode) 0x10 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with RSECCNT counter value #0 1 Compare register value with RSECCNT counter value #1 SEC1 1 Second 0 3 read-write SEC10 10 Seconds 4 2 read-write RSECCNT Second Counter (in Calendar Count Mode) 0x2 8 read-write n 0x0 0x0 SEC1 1-Second Count 0 3 read-write SEC10 10-Second Count 4 2 read-write RSECCP0 Second Capture Register %s BCNT0CP%s 0x52 8 read-only n 0x0 0x0 SEC1 1-Second Capture 0 3 read-only SEC10 10-Second Capture 4 2 read-only RSECCP1 Second Capture Register %s BCNT0CP%s 0x62 8 read-only n 0x0 0x0 SEC1 1-Second Capture 0 3 read-only SEC10 10-Second Capture 4 2 read-only RSECCP2 Second Capture Register %s BCNT0CP%s 0x72 8 read-only n 0x0 0x0 SEC1 1-Second Capture 0 3 read-only SEC10 10-Second Capture 4 2 read-only RTCCR0 Time Capture Control Register %s 0x40 8 read-write n 0x0 0x0 TCCT Time Capture Control 0 1 read-write 00 Do not detect events #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 TCEN Time Capture Event Input Pin Enable 7 read-write 0 Disable the RTCICn pin as the time capture event input pin #0 1 Enable the RTCICn pin as the time capture event input pin #1 TCNF Time Capture Noise Filter Control 4 1 read-write 00 Turn noise filter off #00 01 Setting prohibited #01 10 Turn noise filter on (count source) #10 11 Turn noise filter on (count source by divided by 32) #11 TCST Time Capture Status 2 read-write 0 No event detected #0 1 Event detected #1 RTCCR1 Time Capture Control Register %s 0x42 8 read-write n 0x0 0x0 TCCT Time Capture Control 0 1 read-write 00 Do not detect events #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 TCEN Time Capture Event Input Pin Enable 7 read-write 0 Disable the RTCICn pin as the time capture event input pin #0 1 Enable the RTCICn pin as the time capture event input pin #1 TCNF Time Capture Noise Filter Control 4 1 read-write 00 Turn noise filter off #00 01 Setting prohibited #01 10 Turn noise filter on (count source) #10 11 Turn noise filter on (count source by divided by 32) #11 TCST Time Capture Status 2 read-write 0 No event detected #0 1 Event detected #1 RTCCR2 Time Capture Control Register %s 0x44 8 read-write n 0x0 0x0 TCCT Time Capture Control 0 1 read-write 00 Do not detect events #00 01 Detect rising edge #01 10 Detect falling edge #10 11 Detect both edges #11 TCEN Time Capture Event Input Pin Enable 7 read-write 0 Disable the RTCICn pin as the time capture event input pin #0 1 Enable the RTCICn pin as the time capture event input pin #1 TCNF Time Capture Noise Filter Control 4 1 read-write 00 Turn noise filter off #00 01 Setting prohibited #01 10 Turn noise filter on (count source) #10 11 Turn noise filter on (count source by divided by 32) #11 TCST Time Capture Status 2 read-write 0 No event detected #0 1 Event detected #1 RWKAR Day-of-Week Alarm Register (in Calendar Count Mode) 0x16 8 read-write n 0x0 0x0 DAYW Day-of-Week Setting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting prohibited #111 ENB ENB 7 read-write 0 Do not compare register value with RWKCNT counter value #0 1 Compare register value with RWKCNT counter value #1 RWKCNT Day-of-Week Counter (in Calendar Count Mode) 0x8 8 read-write n 0x0 0x0 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting prohibited #111 RYRAR Year Alarm Register (in Calendar Count Mode) BCNT2AER 0x1C 16 read-write n 0x0 0x0 YR1 1 Year 0 3 read-write YR10 10 Years 4 3 read-write RYRAREN Year Alarm Enable Register (in Calendar Count Mode) BCNT3AER 0x1E 8 read-write n 0x0 0x0 ENB ENB 7 read-write 0 Do not compare register value with the RYRCNT counter value #0 1 Compare register value with the RYRCNT counter value #1 RYRCNT Year Counter 0xE 16 read-write n 0x0 0x0 YR1 1-Year Count 0 3 read-write YR10 10-Year Count 4 3 read-write SCI0 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SCI1 Serial Communication Interface 0 SCI1 0x0 0x0 0x14 registers n 0x1A 0x3 registers n 0x20 0x14 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write CF0CR Control Field 0 Compare Enable Register 0x2A 8 read-write n 0x0 0x0 CF0CE0 Control Field 0 Bit 0 Compare Enable 0 read-write 0 Comparison with bit 0 of Control Field 0 is disabled. #0 1 Comparison with bit 0 of Control Field 0 is enabled. #1 CF0CE1 Control Field 1 Bit 0 Compare Enable 1 read-write 0 Comparison with bit 1 of Control Field 0 is disabled. #0 1 Comparison with bit 1 of Control Field 0 is enabled. #1 CF0CE2 Control Field 2 Bit 0 Compare Enable 2 read-write 0 Comparison with bit 2 of Control Field 0 is disabled. #0 1 Comparison with bit 2 of Control Field 0 is enabled. #1 CF0CE3 Control Field 3 Bit 0 Compare Enable 3 read-write 0 Comparison with bit 3 of Control Field 0 is disabled. #0 1 Comparison with bit 3 of Control Field 0 is enabled. #1 CF0CE4 Control Field 4 Bit 0 Compare Enable 4 read-write 0 Comparison with bit 4 of Control Field 0 is disabled. #0 1 Comparison with bit 4 of Control Field 0 is enabled. #1 CF0CE5 Control Field 5 Bit 0 Compare Enable 5 read-write 0 Comparison with bit 5 of Control Field 0 is disabled. #0 1 Comparison with bit 5 of Control Field 0 is enabled. #1 CF0CE6 Control Field 6 Bit 0 Compare Enable 6 read-write 0 Comparison with bit 6 of Control Field 0 is disabled. #0 1 Comparison with bit 6 of Control Field 0 is enabled. #1 CF0CE7 Control Field 7 Bit 0 Compare Enable 7 read-write 0 Comparison with bit 7 of Control Field 0 is disabled. #0 1 Comparison with bit 7 of Control Field 0 is enabled. #1 CF0DR Control Field 0 Data Register 0x29 8 read-write n 0x0 0x0 CF0RR Control Field 0 Receive Data Register 0x2B 8 read-write n 0x0 0x0 CF1CR Control Field 1 Compare Enable Register 0x2E 8 read-write n 0x0 0x0 CF1CE0 Control Field 1 Bit 0 Compare Enable 0 read-write 0 Comparison with bit 0 of Control Field 1 is disabled. #0 1 Comparison with bit 0 of Control Field 1 is enabled. #1 CF1CE1 Control Field 1 Bit 1 Compare Enable 1 read-write 0 Comparison with bit 1 of Control Field 1 is disabled. #0 1 Comparison with bit 1 of Control Field 1 is enabled. #1 CF1CE2 Control Field 1 Bit 2 Compare Enable 2 read-write 0 Comparison with bit 2 of Control Field 1 is disabled. #0 1 Comparison with bit 2 of Control Field 1 is enabled. #1 CF1CE3 Control Field 1 Bit 3 Compare Enable 3 read-write 0 Comparison with bit 3 of Control Field 1 is disabled. #0 1 Comparison with bit 3 of Control Field 1 is enabled. #1 CF1CE4 Control Field 1 Bit 4 Compare Enable 4 read-write 0 Comparison with bit 4 of Control Field 1 is disabled. #0 1 Comparison with bit 4 of Control Field 1 is enabled. #1 CF1CE5 Control Field 1 Bit 5 Compare Enable 5 read-write 0 Comparison with bit 5 of Control Field 1 is disabled. #0 1 Comparison with bit 5 of Control Field 1 is enabled. #1 CF1CE6 Control Field 1 Bit 6 Compare Enable 6 read-write 0 Comparison with bit 6 of Control Field 1 is disabled. #0 1 Comparison with bit 6 of Control Field 1 is enabled. #1 CF1CE7 Control Field 1 Bit 7 Compare Enable 7 read-write 0 Comparison with bit 7 of Control Field 1 is disabled. #0 1 Comparison with bit 7 of Control Field 1 is enabled. #1 CF1RR Control Field 1 Receive Data Register 0x2F 8 read-write n 0x0 0x0 CR0 Control Register 0 0x21 8 read-write n 0x0 0x0 BRME Bit Rate Measurement Enable 3 read-write 0 Measurement of bit rate is disabled. #0 1 Measurement of bit rate is enabled. #1 RXDSF RXDXn Input Status Flag 2 read-only 0 RXDXn input is enabled. #0 1 RXDXn input is disabled. #1 SFSF Start Frame Status Flag 1 read-only 0 Start Frame detection function is disabled. #0 1 Start Frame detection function is enabled. #1 CR1 Control Register 1 0x22 8 read-write n 0x0 0x0 BFE Break Field Enable 0 read-write 0 Break Field detection is disabled. #0 1 Break Field detection is enabled. #1 CF0RE Control Field 0 Reception Enable 1 read-write 0 Reception of Control Field 0 is disabled. #0 1 Reception of Control Field 0 is enabled. #1 CF1DS Control Field 1 Data Register Select 2 1 read-write 00 Selects comparison with the value in PCF1DR. #00 01 Selects comparison with the value in SCF1DR. #01 10 Selects comparison with the values in PCF1DR and SCF1DR. #10 11 Setting prohibited. #11 PIBE Priority Interrupt Bit Enable 4 read-write 0 The priority interrupt bit is disabled. #0 1 The priority interrupt bit is enabled. #1 PIBS Priority Interrupt Bit Select 5 2 read-write 000 0th bit of Control Field 1 #000 001 1st bit of Control Field 1 #001 010 2nd bit of Control Field 1 #010 011 3rd bit of Control Field 1 #011 100 4th bit of Control Field 1 #100 101 5th bit of Control Field 1 #101 110 6th bit of Control Field 1 #110 111 7th bit of Control Field 1 #111 CR2 Control Register 2 0x23 8 read-write n 0x0 0x0 BCCS Bus Collision Detection Clock Select 4 1 read-write 00 SCI base clock #00 01 SCI base clock frequency divided by 2 #01 10 SCI base clock frequency divided by 4 #10 11 Setting prohibited #11 DFCS RXDXn Signal Digital Filter Clock Select 0 2 read-write 000 Filter is disabled. #000 001 Filter clock is SCI base clock #001 010 Filter clock is PCLK/8 #010 011 Filter clock is PCLK/16 #011 100 Filter clock is PCLK/32 #100 101 Filter clock is PCLK/64 #101 110 Filter clock is PCLK/128 #110 111 Setting prohibited #111 RTS RXDXn Reception Sampling Timing Select 6 1 read-write 00 Rising edge of the 8th cycle of SCI base clock #00 01 Rising edge of the 10th cycle of SCI base clock #01 10 Rising edge of the 12th cycle of SCI base clock #10 11 Rising edge of the 14th cycle of SCI base clock #11 CR3 Control Register 3 0x24 8 read-write n 0x0 0x0 SDST Start Frame Detection Start 0 read-write 0 Detection of Start Frame is not performed. #0 1 Detection of Start Frame is performed. #1 DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 ESMER Extended Serial Module Enable Register 0x20 8 read-write n 0x0 0x0 ESME Extended Serial Mode Enable 0 read-write 0 The extended serial mode is disabled. #0 1 The extended serial mode is enabled. #1 ICR Interrupt Control Register 0x26 8 read-write n 0x0 0x0 AEDIE Valid Edge Detected Interrupt Enable 5 read-write 0 Interrupts on detection of a valid edge are disabled. #0 1 Interrupts on detection of a valid edge are enabled. #1 BCDIE Bus Collision Detected Interrupt Enable 4 read-write 0 Interrupts on detection of a bus collision are disabled. #0 1 Interrupts on detection of a bus collision are enabled. #1 BFDIE Break Field Low Width Detected Interrupt Enable 0 read-write 0 Interrupts on detection of the low width for a Break Field are disabled. #0 1 Interrupts on detection of the low width for a Break Field are enabled. #1 CF0MIE Control Field 0 Match Detected Interrupt Enable 1 read-write 0 Interrupts on detection of a match with Control Field 0 are disabled. #0 1 Interrupts on detection of a match with Control Field 0 are enabled. #1 CF1MIE Control Field 1 Match Detected Interrupt Enable 2 read-write 0 Interrupts on detection of a match with Control Field 1 are disabled. #0 1 Interrupts on detection of a match with Control Field 1 are enabled. #1 PIBDIE Priority Interrupt Bit Detected Interrupt Enable 3 read-write 0 Interrupts on detection of the priority interrupt bit are disabled. #0 1 Interrupts on detection of the priority interrupt bit are enabled. #1 MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 PCF1DR Primary Control Field 1 Data Register 0x2C 8 read-write n 0x0 0x0 PCR Port Control Register 0x25 8 read-write n 0x0 0x0 RXDXPS RXDXn Signal Polarity Select 1 read-write 0 The polarity of RXDXn signal is not inverted for input. #0 1 The polarity of RXDXn signal is inverted for input. #1 SHARPS TXDXn/RXDXn Pin Multiplexing Select 4 read-write 0 The TXDXn and RXDXn pins are independent. #0 1 The TXDXn and RXDXn signals are multiplexed on the same pin. #1 TXDXPS TXDXn Signal Polarity Select 0 read-write 0 The polarity of TXDXn signal is not inverted for output. #0 1 The polarity of TXDXn signal is inverted for output. #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only SCF1DR Secondary Control Field 1 Data Register 0x2D 8 read-write n 0x0 0x0 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 STCR Status Clear Register 0x28 8 read-write n 0x0 0x0 AEDCL AEDF Clear 5 read-write BCDCL BCDF Clear 4 read-write BFDCL BFDF Clear 0 read-write CF0MCL CF0MF Clear 1 read-write CF1MCL CF1MF Clear 2 read-write PIBDCL PIBDF Clear 3 read-write STR Status Register 0x27 8 read-only n 0x0 0x0 AEDF Valid Edge Detection Flag 5 read-only BCDF Bus Collision Detected Flag 4 read-only BFDF Break Field Low Width Detection Flag 0 read-only CF0MF Control Field 0 Match Flag 1 read-only CF1MF Control Field 1 Match Flag 2 read-only PIBDF Priority Interrupt Bit Detection Flag 3 read-only TCNT Timer Count Register 0x33 8 read-write n 0x0 0x0 TCR Timer Control Register 0x30 8 read-write n 0x0 0x0 TCST Timer Count Start 0 read-write 0 Stops the timer counting #0 1 Starts the timer counting #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMR Timer Mode Register 0x31 8 read-write n 0x0 0x0 TCSS Timer Count Clock Source Select 4 2 read-write 000 PCLK #000 001 PCLK/2 #001 010 PCLK/4 #010 011 PCLK/8 #011 100 PCLK/16 #100 101 PCLK/32 #101 110 PCLK/64 #110 111 PCLK/128 #111 TOMS Timer Operating Mode Select 0 1 read-write 00 Timer mode #00 01 Break Field low width determination mode #01 10 Break Field low width output mode #10 11 Setting prohibited #11 TWRC Counter Write Control 3 read-write 0 Data is written to the reload register and counter #0 1 Data is written to the reload register only #1 TPRE Timer Prescaler Register 0x32 8 read-write n 0x0 0x0 SCI2 Serial Communication Interface 0 SCI1 0x0 0x0 0x14 registers n 0x1A 0x3 registers n 0x20 0x14 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write CF0CR Control Field 0 Compare Enable Register 0x2A 8 read-write n 0x0 0x0 CF0CE0 Control Field 0 Bit 0 Compare Enable 0 read-write 0 Comparison with bit 0 of Control Field 0 is disabled. #0 1 Comparison with bit 0 of Control Field 0 is enabled. #1 CF0CE1 Control Field 1 Bit 0 Compare Enable 1 read-write 0 Comparison with bit 1 of Control Field 0 is disabled. #0 1 Comparison with bit 1 of Control Field 0 is enabled. #1 CF0CE2 Control Field 2 Bit 0 Compare Enable 2 read-write 0 Comparison with bit 2 of Control Field 0 is disabled. #0 1 Comparison with bit 2 of Control Field 0 is enabled. #1 CF0CE3 Control Field 3 Bit 0 Compare Enable 3 read-write 0 Comparison with bit 3 of Control Field 0 is disabled. #0 1 Comparison with bit 3 of Control Field 0 is enabled. #1 CF0CE4 Control Field 4 Bit 0 Compare Enable 4 read-write 0 Comparison with bit 4 of Control Field 0 is disabled. #0 1 Comparison with bit 4 of Control Field 0 is enabled. #1 CF0CE5 Control Field 5 Bit 0 Compare Enable 5 read-write 0 Comparison with bit 5 of Control Field 0 is disabled. #0 1 Comparison with bit 5 of Control Field 0 is enabled. #1 CF0CE6 Control Field 6 Bit 0 Compare Enable 6 read-write 0 Comparison with bit 6 of Control Field 0 is disabled. #0 1 Comparison with bit 6 of Control Field 0 is enabled. #1 CF0CE7 Control Field 7 Bit 0 Compare Enable 7 read-write 0 Comparison with bit 7 of Control Field 0 is disabled. #0 1 Comparison with bit 7 of Control Field 0 is enabled. #1 CF0DR Control Field 0 Data Register 0x29 8 read-write n 0x0 0x0 CF0RR Control Field 0 Receive Data Register 0x2B 8 read-write n 0x0 0x0 CF1CR Control Field 1 Compare Enable Register 0x2E 8 read-write n 0x0 0x0 CF1CE0 Control Field 1 Bit 0 Compare Enable 0 read-write 0 Comparison with bit 0 of Control Field 1 is disabled. #0 1 Comparison with bit 0 of Control Field 1 is enabled. #1 CF1CE1 Control Field 1 Bit 1 Compare Enable 1 read-write 0 Comparison with bit 1 of Control Field 1 is disabled. #0 1 Comparison with bit 1 of Control Field 1 is enabled. #1 CF1CE2 Control Field 1 Bit 2 Compare Enable 2 read-write 0 Comparison with bit 2 of Control Field 1 is disabled. #0 1 Comparison with bit 2 of Control Field 1 is enabled. #1 CF1CE3 Control Field 1 Bit 3 Compare Enable 3 read-write 0 Comparison with bit 3 of Control Field 1 is disabled. #0 1 Comparison with bit 3 of Control Field 1 is enabled. #1 CF1CE4 Control Field 1 Bit 4 Compare Enable 4 read-write 0 Comparison with bit 4 of Control Field 1 is disabled. #0 1 Comparison with bit 4 of Control Field 1 is enabled. #1 CF1CE5 Control Field 1 Bit 5 Compare Enable 5 read-write 0 Comparison with bit 5 of Control Field 1 is disabled. #0 1 Comparison with bit 5 of Control Field 1 is enabled. #1 CF1CE6 Control Field 1 Bit 6 Compare Enable 6 read-write 0 Comparison with bit 6 of Control Field 1 is disabled. #0 1 Comparison with bit 6 of Control Field 1 is enabled. #1 CF1CE7 Control Field 1 Bit 7 Compare Enable 7 read-write 0 Comparison with bit 7 of Control Field 1 is disabled. #0 1 Comparison with bit 7 of Control Field 1 is enabled. #1 CF1RR Control Field 1 Receive Data Register 0x2F 8 read-write n 0x0 0x0 CR0 Control Register 0 0x21 8 read-write n 0x0 0x0 BRME Bit Rate Measurement Enable 3 read-write 0 Measurement of bit rate is disabled. #0 1 Measurement of bit rate is enabled. #1 RXDSF RXDXn Input Status Flag 2 read-only 0 RXDXn input is enabled. #0 1 RXDXn input is disabled. #1 SFSF Start Frame Status Flag 1 read-only 0 Start Frame detection function is disabled. #0 1 Start Frame detection function is enabled. #1 CR1 Control Register 1 0x22 8 read-write n 0x0 0x0 BFE Break Field Enable 0 read-write 0 Break Field detection is disabled. #0 1 Break Field detection is enabled. #1 CF0RE Control Field 0 Reception Enable 1 read-write 0 Reception of Control Field 0 is disabled. #0 1 Reception of Control Field 0 is enabled. #1 CF1DS Control Field 1 Data Register Select 2 1 read-write 00 Selects comparison with the value in PCF1DR. #00 01 Selects comparison with the value in SCF1DR. #01 10 Selects comparison with the values in PCF1DR and SCF1DR. #10 11 Setting prohibited. #11 PIBE Priority Interrupt Bit Enable 4 read-write 0 The priority interrupt bit is disabled. #0 1 The priority interrupt bit is enabled. #1 PIBS Priority Interrupt Bit Select 5 2 read-write 000 0th bit of Control Field 1 #000 001 1st bit of Control Field 1 #001 010 2nd bit of Control Field 1 #010 011 3rd bit of Control Field 1 #011 100 4th bit of Control Field 1 #100 101 5th bit of Control Field 1 #101 110 6th bit of Control Field 1 #110 111 7th bit of Control Field 1 #111 CR2 Control Register 2 0x23 8 read-write n 0x0 0x0 BCCS Bus Collision Detection Clock Select 4 1 read-write 00 SCI base clock #00 01 SCI base clock frequency divided by 2 #01 10 SCI base clock frequency divided by 4 #10 11 Setting prohibited #11 DFCS RXDXn Signal Digital Filter Clock Select 0 2 read-write 000 Filter is disabled. #000 001 Filter clock is SCI base clock #001 010 Filter clock is PCLK/8 #010 011 Filter clock is PCLK/16 #011 100 Filter clock is PCLK/32 #100 101 Filter clock is PCLK/64 #101 110 Filter clock is PCLK/128 #110 111 Setting prohibited #111 RTS RXDXn Reception Sampling Timing Select 6 1 read-write 00 Rising edge of the 8th cycle of SCI base clock #00 01 Rising edge of the 10th cycle of SCI base clock #01 10 Rising edge of the 12th cycle of SCI base clock #10 11 Rising edge of the 14th cycle of SCI base clock #11 CR3 Control Register 3 0x24 8 read-write n 0x0 0x0 SDST Start Frame Detection Start 0 read-write 0 Detection of Start Frame is not performed. #0 1 Detection of Start Frame is performed. #1 DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 ESMER Extended Serial Module Enable Register 0x20 8 read-write n 0x0 0x0 ESME Extended Serial Mode Enable 0 read-write 0 The extended serial mode is disabled. #0 1 The extended serial mode is enabled. #1 ICR Interrupt Control Register 0x26 8 read-write n 0x0 0x0 AEDIE Valid Edge Detected Interrupt Enable 5 read-write 0 Interrupts on detection of a valid edge are disabled. #0 1 Interrupts on detection of a valid edge are enabled. #1 BCDIE Bus Collision Detected Interrupt Enable 4 read-write 0 Interrupts on detection of a bus collision are disabled. #0 1 Interrupts on detection of a bus collision are enabled. #1 BFDIE Break Field Low Width Detected Interrupt Enable 0 read-write 0 Interrupts on detection of the low width for a Break Field are disabled. #0 1 Interrupts on detection of the low width for a Break Field are enabled. #1 CF0MIE Control Field 0 Match Detected Interrupt Enable 1 read-write 0 Interrupts on detection of a match with Control Field 0 are disabled. #0 1 Interrupts on detection of a match with Control Field 0 are enabled. #1 CF1MIE Control Field 1 Match Detected Interrupt Enable 2 read-write 0 Interrupts on detection of a match with Control Field 1 are disabled. #0 1 Interrupts on detection of a match with Control Field 1 are enabled. #1 PIBDIE Priority Interrupt Bit Detected Interrupt Enable 3 read-write 0 Interrupts on detection of the priority interrupt bit are disabled. #0 1 Interrupts on detection of the priority interrupt bit are enabled. #1 MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 PCF1DR Primary Control Field 1 Data Register 0x2C 8 read-write n 0x0 0x0 PCR Port Control Register 0x25 8 read-write n 0x0 0x0 RXDXPS RXDXn Signal Polarity Select 1 read-write 0 The polarity of RXDXn signal is not inverted for input. #0 1 The polarity of RXDXn signal is inverted for input. #1 SHARPS TXDXn/RXDXn Pin Multiplexing Select 4 read-write 0 The TXDXn and RXDXn pins are independent. #0 1 The TXDXn and RXDXn signals are multiplexed on the same pin. #1 TXDXPS TXDXn Signal Polarity Select 0 read-write 0 The polarity of TXDXn signal is not inverted for output. #0 1 The polarity of TXDXn signal is inverted for output. #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only SCF1DR Secondary Control Field 1 Data Register 0x2D 8 read-write n 0x0 0x0 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 STCR Status Clear Register 0x28 8 read-write n 0x0 0x0 AEDCL AEDF Clear 5 read-write BCDCL BCDF Clear 4 read-write BFDCL BFDF Clear 0 read-write CF0MCL CF0MF Clear 1 read-write CF1MCL CF1MF Clear 2 read-write PIBDCL PIBDF Clear 3 read-write STR Status Register 0x27 8 read-only n 0x0 0x0 AEDF Valid Edge Detection Flag 5 read-only BCDF Bus Collision Detected Flag 4 read-only BFDF Break Field Low Width Detection Flag 0 read-only CF0MF Control Field 0 Match Flag 1 read-only CF1MF Control Field 1 Match Flag 2 read-only PIBDF Priority Interrupt Bit Detection Flag 3 read-only TCNT Timer Count Register 0x33 8 read-write n 0x0 0x0 TCR Timer Control Register 0x30 8 read-write n 0x0 0x0 TCST Timer Count Start 0 read-write 0 Stops the timer counting #0 1 Starts the timer counting #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMR Timer Mode Register 0x31 8 read-write n 0x0 0x0 TCSS Timer Count Clock Source Select 4 2 read-write 000 PCLK #000 001 PCLK/2 #001 010 PCLK/4 #010 011 PCLK/8 #011 100 PCLK/16 #100 101 PCLK/32 #101 110 PCLK/64 #110 111 PCLK/128 #111 TOMS Timer Operating Mode Select 0 1 read-write 00 Timer mode #00 01 Break Field low width determination mode #01 10 Break Field low width output mode #10 11 Setting prohibited #11 TWRC Counter Write Control 3 read-write 0 Data is written to the reload register and counter #0 1 Data is written to the reload register only #1 TPRE Timer Prescaler Register 0x32 8 read-write n 0x0 0x0 SCI3 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SCI4 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SCI5 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SCI6 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SCI7 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SCI8 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SCI9 Serial Communication Interface SCI0 0x0 0x0 0x1E registers n 0x20 0x1 registers n 0x22 0x4 registers n 0x4 0x1 registers n ACTR Adjustment Communication Timing Register 0x1D 8 read-write n 0x0 0x0 AET Adjustment edge for transmit timing 7 read-write 0 Adjust the rising edge timing. #0 1 Adjust the falling edge timing. #1 AJD Adjustment Direction for receive sampling timing 3 read-write 0 The sampling timing is adjusted backward to the middle of bit. #0 1 The sampling timing is adjusted forward to the middle of bit. #1 AST Adjustment value for receive Sampling Timing 0 2 read-write ATT Adjustment value for Transmit timing 4 2 read-write BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match Data 0 8 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable 7 read-write 0 Disable address match function #0 1 Enable address match function #1 DCMF Data Compare Match Flag 0 read-write 0 Not matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 IDSEL ID Frame Select 6 read-write 0 Always compare data regardless of the MPB bit value #0 1 Only compare data when MPB bit = 1 (ID frame) #1 FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive Data Ready Error Select Bit 3 read-write 0 Receive data full interrupt (SCIn_RXI) #0 1 Receive error interrupt (SCIn_ERI) #1 FM FIFO Mode Select 0 read-write 0 Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication. #0 1 FIFO mode. Selects FTDRHL/FRDRHL for communication. #1 RFRST Receive FIFO Data Register Reset 1 read-write 0 Do not reset FRDRHL #0 1 Reset FRDRHL #1 RSTRG RTS Output Active Trigger Number Select 12 3 read-write RTRG Receive FIFO Data Trigger Number 8 3 read-write TFRST Transmit FIFO Data Register Reset 2 read-write 0 Do not reset FTDRHL #0 1 Reset FTDRHL #1 TTRG Transmit FIFO Data Trigger Number 4 3 read-write FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data Count 0 4 read-only T Transmit FIFO Data Count 8 4 read-only FRDRH Receive FIFO Data Register FRDRHL 0x10 8 read-only n 0x0 0x0 DR Receive Data Ready Flag 2 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 4 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDF Receive FIFO Data Full Flag 6 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRHL Receive FIFO Data Register 0x10 16 read-only n 0x0 0x0 DR Receive Data Ready Flag 10 read-only 0 Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception #0 1 Next receive data is not received for a period after successfully completed reception #1 FER Framing Error Flag 12 read-only 0 No framing error occurred in the first data of FRDRH and FRDRL #0 1 Framing error occurred in the first data of FRDRH and FRDRL #1 MPB Multi-Processor Bit Flag 9 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 13 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 11 read-only 0 No parity error occurred in the first data of FRDRH and FRDRL #0 1 Parity error occurred in the first data of FRDRH and FRDRL #1 RDAT Stores the serial receive data. 0 8 read-only RDF Receive FIFO Data Full Flag 14 read-only 0 The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number #1 FRDRL Receive FIFO Data Register FRDRHL 0x11 8 read-only n 0x0 0x0 RDAT Stores the serial receive data. 0 7 read-only FTDRH Transmit FIFO Data Register FTDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 1 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 FTDRHL Transmit FIFO Data Register 0xE 16 write-only n 0x0 0x0 MPBT Multi-Processor Transfer Bit Flag 9 write-only 0 Data transmission cycle #0 1 ID transmission cycle #1 TDAT Specifies the serial transmit data 0 8 write-only FTDRL Transmit FIFO Data Register FTDRHL 0xF 8 write-only n 0x0 0x0 TDAT Specifies the serial transmit data 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error Count 2 4 read-only ORER Overrun Error Flag 0 read-only 0 No overrun error occurred #0 1 Overrun error occurred #1 PNUM Parity Error Count 8 4 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MECR Manchester Extended Error Control Register 0x25 8 read-write n 0x0 0x0 PFEREN Preface Error Enable 0 read-write 0 Does not handle a preface error as an interrupt source #0 1 Handles a preface error as an interrupt source #1 SBEREN Start Bit Error Enable 2 read-write 0 Does not handle a start bit error as an interrupt source #0 1 Handles a start bit error as an interrupt source #1 SYEREN Receive SYNC Error Enable 1 read-write 0 Does not handle a receive SYNC error as an interrupt source #0 1 Handles a receive SYNC error as an interrupt source #1 MESR Manchester Extended Error Status Register 0x24 8 read-write n 0x0 0x0 PFER Preface Error flag 0 read-write 0 No preface error detected #0 1 Preface error detected #1 SBER Start Bit Error flag 2 read-write 0 No start bit error detected #0 1 Start bit error detected #1 SYER SYNC Error flag 1 read-write 0 No receive SYNC error detected #0 1 Receive SYNC error detected #1 MMR Manchester Mode Register 0x20 8 read-write n 0x0 0x0 ERTEN Manchester Edge Retiming Enable 2 read-write 0 Disables the receive retiming function #0 1 Enables the receive retiming function #1 MANEN Manchester Mode Enable 7 read-write 0 Disables the Manchester mode #0 1 Enables the Manchester mode #1 RMPOL Polarity of Received Manchester Code 0 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 SBSEL Start Bit Select 6 read-write 0 The start bit area consists of one bit. #0 1 The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) #1 SYNSEL SYNC Select 5 read-write 0 The start bit pattern is set with the SYNVAL bit #0 1 The start bit pattern is set with the TSYNC bit. #1 SYNVAL SYNC value Setting 4 read-write 0 The start bit is added as a zero-to-one transition. #0 1 The start bit is added as a one-to-zero transition. #1 TMPOL Polarity of Transmit Manchester Code 1 read-write 0 Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code #0 1 Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code #1 RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDRHL Receive Data Register FRDRHL 0x10 16 read-only n 0x0 0x0 RDAT Serial Receive Data 0 8 read-only RMPR Receive Manchester Preface Setting Register 0x23 8 read-write n 0x0 0x0 RPLEN Receive Preface Length 0 3 read-write Other Receive preface length (bit length) 0 Disables the receive preface generation #0 RPPAT Receive Preface Pattern 4 1 read-write 0 ALL ZERO #0 1 ZERO ONE #1 2 ONE ZERO #10 3 ALL ONE #11 SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2 7 read-write CHR1 Character Length 1 4 read-write 0 When SMR.CHR = 0: Transmit/receive in 9-bit data length When SMR.CHR = 1: Transmit/receive in 9-bit data length #0 1 When SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) When SMR.CHR = 1: Transmit/receive in 7-bit data length #1 SDIR Transmitted/Received Data Transfer Direction 3 read-write 0 Transfer LSB-first #0 1 Transfer MSB-first #1 SINV Transmitted/Received Data Invert 2 read-write 0 TDR register contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. #0 1 TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode) #0 1 Smart card interface mode #1 SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write Others In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin. 00 In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. #00 01 In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin. #01 MPIE Multi-Processor Interrupt Enable 3 read-write 0 Normal reception #0 1 When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write 0 Disable SCIn_TEI interrupt requests #0 1 Enable SCIn_TEI interrupt requests #1 TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low #00 01 When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock #01 10 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high #10 11 When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Disable serial reception #0 1 Enable serial reception #1 RIE Receive Interrupt Enable 6 read-write 0 Disable SCIn_RXI and SCIn_ERI interrupt requests #0 1 Enable SCIn_RXI and SCIn_ERI interrupt requests #1 TE Transmit Enable 5 read-write 0 Disable serial transmission #0 1 Enable serial transmission #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 Disable SCIn_TXI interrupt requests #0 1 Enable SCIn_TXI interrupt requests #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select 4 read-write 0 Select 16 base clock cycles for 1-bit period #0 1 Select 8 base clock cycles for 1-bit period #1 ABCSE Asynchronous Mode Extended Base Clock Select 1 3 read-write 0 Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register #0 1 Baud rate is 6 base clock cycles for 1-bit period #1 BGDM Baud Rate Generator Double-Speed Mode Select 6 read-write 0 Output clock from baud rate generator with normal frequency #0 1 Output clock from baud rate generator with doubled frequency #1 BRME Bit Rate Modulation Enable 2 read-write 0 Disable bit rate modulation function #0 1 Enable bit rate modulation function #1 NFEN Digital Noise Filter Function Enable 5 read-write 0 In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals #0 1 In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals #1 RXDESEL Asynchronous Start Bit Edge Detection Select 7 read-write 0 Detect low level on RXDn pin as start bit #0 1 Detect falling edge of RXDn pin as start bit #1 SIMR1 IIC Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDAn Delay Output Select 3 4 read-write Others (IICDL-1) to (IICDL) cycles 0x00 No output delay 0x00 IICM Simple IIC Mode Select 0 read-write 0 SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode #0 1 SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited #1 SIMR2 IIC Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and ACK/NACK reception #1 IICCSC Clock Synchronization 1 read-write 0 Do not synchronize with clock signal #0 1 Synchronize with clock signal #1 IICINTM IIC Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts #0 1 Use reception and transmission interrupts #1 SIMR3 IIC Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 Do not generate restart condition #0 1 Generate restart condition #1 IICSCLS SCLn Output Select 6 1 read-write 00 Output serial clock #00 01 Generate start, restart, or stop condition #01 10 Output low on SCLn pin #10 11 Drive SCLn pin to high-impedance state #11 IICSDAS SDAn Output Select 4 1 read-write 00 Output serial data #00 01 Generate start, restart, or stop condition #01 10 Output low on SDAn pin #10 11 Drive SDAn pin to high-impedance state #11 IICSTAREQ Start Condition Generation 0 read-write 0 Do not generate start condition #0 1 Generate start condition #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag 3 read-write 0 No requests are being made for generating conditions, or a condition is being generated #0 1 Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0 #1 IICSTPREQ Stop Condition Generation 2 read-write 0 Do not generate stop condition #0 1 Generate stop condition #1 SISR IIC Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length 6 read-write 0 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value) #0 1 When SCMR.CHR1 = 0: Transmit/receive in 9-bit data length When SCMR.CHR1 = 1: Transmit/receive in 7-bit data length #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple IIC mode #0 1 Clock synchronous mode or simple SPI mode #1 MP Multi-Processor Mode 2 read-write 0 Disable multi-processor communications function #0 1 Enable multi-processor communications function #1 PE Parity Enable 5 read-write 0 When transmitting: Do not add parity bit When receiving: Do not check parity bit #0 1 When transmitting: Add parity bit When receiving: Check parity bit #1 PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 STOP Stop Bit Length 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse 2 1 read-write BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock (n = 0) #00 01 PCLK/4 clock (n = 1) #01 10 PCLK/16 clock (n = 2) #10 11 PCLK/64 clock (n = 3) #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable 5 read-write PM Parity Mode 4 read-write 0 Even parity #0 1 Odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write Others Setting prohibited 000 In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited #000 001 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter #001 010 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter #010 011 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter #011 100 In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter #100 SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Do not delay clock #0 1 Delay clock #1 CKPOL Clock Polarity Select 6 read-write 0 Do not invert clock polarity #0 1 Invert clock polarity #1 CTSE CTS Enable 1 read-write 0 Disable CTS function (enable RTS output function) #0 1 Enable CTS function #1 MFF Mode Fault Flag 4 read-write 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmit through TXDn pin and receive through RXDn pin (master mode) #0 1 Receive through TXDn pin and transmit through RXDn pin (slave mode) #1 SSE SSn Pin Function Enable 0 read-write 0 Disable SSn pin function #0 1 Enable SSn pin function #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 ASEN Adjust receive sampling timing enable 6 read-write 0 Adjust sampling timing disable. #0 1 Adjust sampling timing enable. #1 ATEN Adjust transmit timing enable 7 read-write 0 Adjust transmit timing disable. #0 1 Adjust transmit timing enable. #1 RINV RXD invert bit 4 read-write 0 Received data from RXD is not inverted and input. #0 1 Received data from RXD is inverted and input. #1 RXDMON Serial Input Data Monitor 0 read-only SPB2DT Serial Port Break Data Select 1 read-write SPB2IO Serial Port Break I/O 2 read-write 0 Do not output value of SPB2DT bit on TXD pin #0 1 Output value of SPB2DT bit on TXD pin #1 TINV TXD invert bit 5 read-write 0 Transmit data is not inverted and output to TXD. #0 1 Transmit data is inverted and output to TXD. #1 SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycle #0 1 ID transmission cycle #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycle #0 1 ID transmission cycle #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready Flag 0 read-write 0 Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty) #0 1 Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number #1 FER Framing Error Flag 4 read-write 0 No framing error occurred #0 1 Framing error occurred #1 ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDF Receive FIFO Data Full Flag 6 read-write 0 The amount of receive data written in FRDRHL is less than the specified receive triggering number #0 1 The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number #1 TDFE Transmit FIFO Data Empty Flag 7 read-write 0 The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number #0 1 The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write 0 A character is being transmitted #0 1 Character transfer is complete #1 SSR_SMCI Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write 0 No low error signal response #0 1 Low error signal response occurred #1 MPB Multi-Processor 1 read-only MPBT Multi-Processor Bit Transfer 0 read-write ORER Overrun Error Flag 5 read-write 0 No overrun error occurred #0 1 Overrun error occurred #1 PER Parity Error Flag 3 read-write 0 No parity error occurred #0 1 Parity error occurred #1 RDRF Receive Data Full Flag 6 read-write 0 No received data in RDR register #0 1 Received data in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write 0 Transmit data in TDR register #0 1 No transmit data in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted #0 1 Character transfer is complete #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDRHL Transmit Data Register FTDRHL 0xE 16 read-write n 0x0 0x0 TDAT Serial Transmit Data 0 8 read-write TMPR Transmit Manchester Preface Setting Register 0x22 8 read-write n 0x0 0x0 TPLEN Transmit preface length 0 3 read-write Others Transmit preface length (bit length) 0x0 Disables the transmit preface generation 0x0 TPPAT Transmit preface pattern 4 1 read-write 00 ALL ZERO #00 01 ZERO ONE #01 10 ONE ZERO #10 11 ALL ONE #11 SDHI0 SD Host Interface 0 SDHI0 0x0 0x0 0x54 registers n 0x1B0 0x4 registers n 0x1C0 0x10 registers n 0x1E0 0x20 registers n 0x58 0xC registers n 0x68 0xC registers n EXT_SWAP Swap Control Register 0x1E0 32 read-write n 0x0 0x0 BRSWP SD_BUF0 Swap Read 7 read-write 0 The current data are read without swapping. #0 1 Swapping of the positions of the higher- and lower-order bytes of data for reading proceeds. #1 BWSWP SD_BUF0 Swap Write 6 read-write 0 The current data are written without swapping. #0 1 Swapping of the positions of the higher- and lower-order bytes of data for writing proceeds. #1 Reserved These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000. 8 23 read-write Reserved These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000. 8 23 read-write SDIF_MODE SD Interface Mode Setting Register 0x1CC 32 read-write n 0x0 0x0 NOCHKCR CRC Check Mask (for MMC test commands) 8 read-write 0 CRC check is valid #0 1 CRC check is invalid(CRC16 value is ignored when read and CRC Status value is ignored when write) #1 Reserved These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000. 9 22 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write Reserved These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000. 9 22 read-write SDIO_INFO1 SDIO Interrupt Flag Register 1 0x6C 32 read-write n 0x0 0x0 EXPUB52 EXPUB52 Status FlagNOTE: See manual 14 read-write zeroToClear modify EXWT EXWT Status FlagNOTE: See manual 15 read-write zeroToClear modify IOIRQ SDIO Interrupt Status 0 read-write zeroToClear modify 0 SDIO interrupt not accepted #0 1 SDIO interrupt accepted #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 00000000000. The write value should be 00000000000. 3 10 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SDIO_INFO1_MASK SDIO_INFO1 Interrupt Mask Register 0x70 32 read-write n 0x0 0x0 EXPUB52M EXPUB52 Interrupt Request Mask Control 14 read-write 0 EXPUB52 interrupt request not masked #0 1 EXPUB52 interrupt request masked #1 EXWTM EXWT Interrupt Request Mask Control 15 read-write 0 EXWT interrupt request not masked #0 1 EXWT interrupt request masked #1 IOIRQM IOIRQ Interrupt Mask Control 0 read-write 0 IOIRQ interrupt not masked #0 1 IOIRQ interrupt masked #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 00000000000. The write value should be 00000000000. 3 10 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SDIO_MODE SDIO Mode Control Register 0x68 32 read-write n 0x0 0x0 C52PUB SDIO None AbortNOTE: See manual 9 read-write INTEN SDIO Mode 0 read-write 0 Disables the SD host interface to receive SDIO interrupt from the SDIO card #0 1 Enables the SD host interface to receive SDIO interrupt from the SDIO card #1 IOABT SDIO AbortNOTE: See manual 8 read-write Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write RWREQ Read Wait Request 2 read-write 0 Allow SD/MMC to exit read wait state #0 1 Request for SD/MMC to enter read wait state. #1 SD_ARG SD Command Argument Register 0x8 32 read-write n 0x0 0x0 SD_ARG Argument RegisterSet command format[39:8] (argument) 0 31 read-write SD_ARG1 SD Command Argument Register 1 0xC 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SD_ARG1 Argument Register 1Set command format[39:24] (argument) 0 15 read-write SD_BUF0 SD Buffer Register 0x60 32 read-write n 0x0 0x0 SD_BUF SD Buffer RegisterWhen writing to the SD card, the write data is written to this register. When reading from the SD card, the read data is read from this register. This register is internally connected to two 512-byte buffers.If both buffers are not empty when executing multiple block read, SD/MMC clock is stopped to suspend receiving data. When one of buffers is empty, SD/MMC clock is supplied to resume receiving data. 0 31 read-write SD_CLK_CTRL SD Clock Control Register 0x48 32 read-write n 0x0 0x0 CLKCTRLEN SD/MMC Clock Output Automatic Control Enable 9 read-write 0 Automatic control for SD/MMC Clock output is disabled. #0 1 Automatic control for SD/MMC Clock output is enabled. #1 CLKEN SD/MMC Clock Output Control Enable 8 read-write 0 SD/MMC Clock output is disabled. The SDCLK signal is fixed 0. #0 1 SD/MMC Clock output is enabled. #1 CLKSEL SDHI Clock Frequency Select 0 7 read-write others Settings prohibited. 0x00 PCLKA divided by 2 0x00 0x01 PCLKA divided by 4 0x01 0x02 PCLKA divided by 8 0x02 0x04 PCLKA divided by 16 0x04 0x08 PCLKA divided by 32 0x08 0x10 PCLKA divided by 64 0x10 0x20 PCLKA divided by 128 0x20 0x40 PCLKA divided by 256 0x40 0x80 PCLKA divided by 512 0x80 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SD_CMD Command Type Register 0x0 32 read-write n 0x0 0x0 ACMD Command Type Select 6 1 read-write others Setting prohibited 00 CMD #00 01 ACMD #01 CMD12AT Multiple Block Transfer Mode (enabled at multiple block transfer) 14 1 read-write 00 CMD12 is automatically issued at multiple block transfer. #00 01 CMD12 is not automatically issued at multiple block transfer. #01 10 Setting prohibited #10 11 Setting prohibited #11 CMDIDX Command IndexThese bits specify Command Format[45:40] (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 0 5 read-write CMDRW Write/Read Mode (enabled when the command with data is handled) 12 read-write 0 Write (SD/MMC host interface -> SD card/MMC) #0 1 Read (SD/MMC host interface <- SD card/MMC) #1 CMDTP Data Mode (Command Type) 11 read-write 0 Command does not include data transfer (bc, bcr, or ac) #0 1 Command includes data transfer (adtc) #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write RSPTP Mode/Response TypeNOTE: As some commands cannot be used in normal mode, see section 1.4.10, Example of SD_CMD Register Setting to select mode/response type. 8 2 read-write others Settings prohibited. 000 Normal mode The response type and the transfer mode are selected by SD_CMD[7:0], and the SD_CMD[15:11] setting is disabled. #000 011 Expansion mode and no response #011 100 Expansion mode and R1, R5, R6, or R7 response #100 101 Expansion mode and R1b response #101 110 Expansion mode and R2 response #110 111 Expansion mode and R3 or R4 response #111 TRSTP Single/Multiple Block Transfer (enabled when the command with data is handled) 13 read-write 0 Single block transfer #0 1 Multiple block transfer #1 SD_DMAEN DMA Mode Enable Register 0x1B0 32 read-write n 0x0 0x0 DMAEN SD_BUF Read/Write DMA Transfer 1 read-write 0 The SD_BUF read/write DMA transfer is disabled. #0 1 The SD_BUF read/write DMA transfer is enabled. #1 Reserved These bits are read as 0000000000000000000. The write value should be 0000000000000000000. 13 18 read-write Reserved These bits are read as 00. The write value should be 00. 2 1 read-write Reserved This bit is read as 1. The write value should be 1. 4 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 5 6 read-write Reserved This bit is read as 1. The write value should be 1. 12 read-write Reserved These bits are read as 0000000000000000000. The write value should be 0000000000000000000. 13 18 read-write SD_ERR_STS1 SD Error Status Register 1 0x58 32 read-only n 0x0 0x0 CMDE0 Command Error 0NOTE: other than a response to a command issued within a command sequence 0 read-only 0 An error has not occured in the command index of a response. #0 1 An error has occured in the command index of a response. #1 CMDE1 Command Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is Indicated in CMDE0. 1 read-only 0 An error has not occurs in the command index of the response to a command issued within a command sequence. #0 1 An error has occured in the command index of the response to a command issued within a command sequence. #1 CRCLENE CRC Status Token Length Error 5 read-only 0 An error has not occured in the CRC status length. #0 1 An error has occured in the CRC status length (and the end bit has not been detected) #1 CRCTK CRC Status TokenStore the CRC status token value (normal value is 010b) 12 2 read-only CRCTKE CRC Status Token Error 11 read-only 0 An error has not occured in the CRC status. #0 1 An error has occured in the CRC status. #1 RDCRCE Read Data CRC Error 10 read-only 0 CRC error has detected in read data #0 1 CRC error has not detected in read data #1 RDLENE Read Data Length Error 4 read-only 0 An error has occurred not in the read data length. #0 1 An error has occured in the read data length (and the end bit has not been detected among the valid bits). #1 Reserved These bits are read as 00000000000000000. 15 16 read-only Reserved These bits are read as 00000000000000000. 15 16 read-only RSPCRCE0 Response CRC Error 0NOTE: other than a response to a command issued within a command sequence 8 read-only 0 A CRC error has not occur in a response #0 1 A CRC error has occured in a response #1 RSPCRCE1 Response CRC Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPCRCE0. 9 read-only 0 CRC error has not occured. #0 1 CRC error has occured in the response to a command issued within a command sequence. #1 RSPLENE0 Response Length Error 0NOTE: other than a response to a command issued within a command sequence 2 read-only 0 An error has not occured in the response length #0 1 An error has occured in the response length #1 RSPLENE1 Response Length Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPLENE0. 3 read-only 0 An error has not occurred in the response length to a command issued within a command sequence. #0 1 An error has occured in the response length to a command issued within a command sequence. #1 SD_ERR_STS2 SD Error Status Register 2 0x5C 32 read-only n 0x0 0x0 BSYTO0 Busy Timeout 0 2 read-only 0 Not timeout. #0 1 The busy state for longer than N-cycle continues after R1b response. #1 BSYTO1 Busy Timeout 1 3 read-only 0 Not timeout. #0 1 The busy state for longer than N-cycle continues after CMD12 has been issued within a command sequence. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in BSYTO0. #1 CRCBSYTO CRC Status Token Busy Timeout 6 read-only 0 Not timeout #0 1 The busy state continues for longer than N-cycle after the CRC status #1 CRCTO CRC Status Token Timeout 5 read-only 0 Not timeout #0 1 The CRC status is not received though a longer time than N-cycle has elapsed after data writing. #1 RDTO Read Data Timeout 4 read-only 0 Not timeout #0 1 The read data is not received though a longer time than N-cycle has elapsed after read command. / The read data for the next block are not received though a longer time than N-cycle has elapsed after the reception of read data. / The read data for the next block are not received though a longer time than N-cycle has elapsed after release of the read wait state. #1 Reserved These bits are read as 0000000000000000000000000. 7 24 read-only RSPTO0 Response Timeout 0 0 read-only 0 Not timeout. #0 1 The response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. #1 RSPTO1 Response Timeout 1 1 read-only 0 Not timeout. #0 1 The response to a command issued within a command sequence*2 is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPTO0. #1 SD_INFO1 SD Card Interrupt Flag Register 1 0x38 32 read-write n 0x0 0x0 ACEND Access End 2 read-write zeroToClear modify 0 Access end is not detected #0 1 Access end is detected #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write RSPEND Response End Detection 0 read-write 0 Response end is not detected #0 1 Response end is detected #1 SDCDIN SDnCD Card Insertion 4 read-write zeroToClear modify 0 Card insertion not detected #0 1 Card insertion detected #1 SDCDMON Indicates the SDnCD state 5 read-only 0 Indicates that Mcycle has elapsed with SDnCD held 1.(Mcycle is set by bits 3 to 0 in SD_OPTION.) #0 1 Indicates that Mcycle has elapsed with SDnCD held 0. (Mcycle is set by bits 3 to 0 in SD_OPTION.) #1 SDCDRM SDnCD Card Removal 3 read-write zeroToClear modify 0 Card removal not detected #0 1 Card removal detected #1 SDD3IN SDnDAT3 Card Insertion 9 read-write zeroToClear modify 0 SD card insertion not detected #0 1 SD card insertion detected #1 SDD3MON Inticates the SDnDAT3 State 10 read-only 0 SDnDAT3 is set to 0. #0 1 SDnDAT3 is set to 1. #1 SDD3RM SDnDAT3 Card Removal 8 read-write zeroToClear modify 0 SD card removal not detected #0 1 SD card removal detected #1 SDWPMON Indicates the SDnWP state 7 read-only 0 SDnWP is set to 1. #0 1 SDnWP is set to 0. #1 SD_INFO1_MASK SD_INFO1 Interrupt Mask Register 0x40 32 read-write n 0x0 0x0 ACENDM Access End Interrupt Request Mask 2 read-write 0 Access end interrupt request is not masked #0 1 Access end interrupt request is masked #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write RSPENDM Response End Interrupt Request Mask 0 read-write 0 Response end interrupt request is not masked #0 1 Response end interrupt request is masked #1 SDCDINM SDnCD card Insertion Interrupt Request Mask 4 read-write 0 Card insertion interrupt request by the SDnCD is not masked #0 1 Card insertion interrupt request by the SDnCD is masked #1 SDCDRMM SDnCD card Removal Interrupt Request Mask 3 read-write 0 Card removal interrupt request by the by the SDnCD is not masked #0 1 Card removal interrupt request by the by the SDnCD is masked #1 SDD3INM SDnDAT3 Card Insertion Interrupt Request Mask 9 read-write 0 SD card insertion interrupt request by the SDnDAT3 is not masked #0 1 SD card insertion interrupt request by the SDnDAT3 is masked #1 SDD3RMM SDnDAT3 Card Removal Interrupt Request Mask 8 read-write 0 SD card removal interrupt request by the SDnDAT3 is not masked #0 1 SD card removal interrupt request by the SDnDAT3 is masked #1 SD_INFO2 SD Card Interrupt Flag Register 2 0x3C 32 read-write n 0x0 0x0 BRE SD_BUF Read Enable 8 read-write zeroToClear modify 0 Data cannot be read from SD_BUF0. #0 1 Data can be read from SD_BUF0. #1 BWE SD_BUF Write Enable 9 read-write zeroToClear modify 0 Data cannot be written in SD_BUF0. #0 1 Data can be written in SD_BUF0. #1 CBSY Command Type Register Busy 14 read-only 0 A command sequence is being executed. #0 1 A command sequence has been completed. #1 CMDE Command Error 0 read-write zeroToClear modify 0 Command error not detected #0 1 Command error detected #1 CRCE CRC Error 1 read-write zeroToClear modify 0 CRC error not detected #0 1 CRC error detected #1 DTO Data Timeout 3 read-write zeroToClear modify 0 Data timeout not detected #0 1 Data timeout detected #1 ENDE END Error 2 read-write zeroToClear modify 0 End bit error not detected #0 1 End bit error detected #1 ILA Illegal Access Error 15 read-write zeroToClear modify 0 Illegal access error not detected #0 1 Illegal access error detected #1 ILR SD_BUF Illegal Read Access 5 read-write zeroToClear modify 0 Illegal read access to the SD_BUF register not detected #0 1 Illegal read access to the SD_BUF register detected #1 ILW SD_BUF Illegal Write Access 4 read-write zeroToClear modify 0 Illegal write access to the SD_BUF register not detected #0 1 Illegal write access to the SD_BUF register detected #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write RSPTO Response Timeout 6 read-write zeroToClear modify 0 Response timeout not detected #0 1 Response timeout detected #1 SDD0MON SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL. 7 read-only 0 SDDAT0 is set to 0. #0 1 SDDAT0 is set to 1. #1 SD_CLK_CTRLEN When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence. 13 read-only 0 The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible. #0 1 The SD/MMC bus (CMD, DAT) is not busy. #1 SD_INFO2_MASK SD_INFO2 Interrupt Mask Register 0x44 32 read-write n 0x0 0x0 BREM BRE Interrupt Request Mask 8 read-write 0 Read enable interrupt request for the SD buffer not masked #0 1 Read enable interrupt request for the SD buffer masked #1 BWEM BWE Interrupt Request Mask 9 read-write 0 Write enable interrupt request for the SD_BUF register not masked #0 1 Write enable interrupt request for the SD_BUF register masked #1 CMDEM Command Error Interrupt Request Mask 0 read-write 0 Command error interrupt request not masked #0 1 Command error interrupt request masked #1 CRCEM CRC Error Interrupt Request Mask 1 read-write 0 CRC error interrupt request not masked #0 1 CRC error interrupt request masked #1 DTOM Data Timeout Interrupt Request Mask 3 read-write 0 Data timeout interrupt request not masked #0 1 Data timeout interrupt request masked #1 ENDEM End Bit Error Interrupt Request Mask 2 read-write 0 End bit detection error interrupt request not masked #0 1 End bit detection error interrupt request masked #1 ILAM Illegal Access Error Interrupt Request Mask 15 read-write 0 Illegal access error interrupt request not masked #0 1 Illegal access error interrupt request masked #1 ILRM SD_BUF Register Illegal Read Interrupt Request Mask 5 read-write 0 Illegal read detection interrupt request for the SD_BUF register not masked #0 1 Illegal read detection interrupt request for the SD_BUF register masked #1 ILWM SD_BUF Register Illegal Write Interrupt Request Mask 4 read-write 0 Illegal write detection interrupt request for the SD_BUF register not masked #0 1 Illegal write detection interrupt request for the SD_BUF register masked #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved This bit is read as 1. The write value should be 1. 11 read-write Reserved These bits are read as 000. The write value should be 000. 12 2 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write RSPTOM Response Timeout Interrupt Request Mask 6 read-write 0 Response timeout interrupt request not masked #0 1 Response timeout interrupt request masked #1 SD_OPTION SD Card Access Control Option Register 0x50 32 read-write n 0x0 0x0 CTOP Card Detect Time Counter 0 3 read-write others IMCLK x 2^(CTOP+10) 1111 Setting prohibited #1111 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved This bit is read as 1. The write value should be 1. 14 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write TOP Timeout Counter 4 3 read-write others SDHI clock x 2^(TOP+13) 1111 Setting prohibited #1111 TOUTMASK Timeout MASKWhen timeout occurs in case of inactivating timeout, software reset should be executed to terminate command sequence. 8 read-write 0 Activate Timeout #0 1 Inactivate Timeout(RSPTO bit and DTO bit of SD_INFO2 and SD_ERR_STS2 won't be set) #1 WIDTH Bus WidthNOTE: The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0. 15 read-write 0 4-bit width (WIDTH8=0) / 8-bit width (WIDTH8=1) #0 1 1-bit width (WIDTH8=0 or 1 ) #1 WIDTH8 Bus Widthsee b15, WIDTH bit 13 read-write SD_RSP1 SD Card Response Register 1 0x1C 32 read-only n 0x0 0x0 Reserved These bits are read as 0000000000000000. 16 15 read-only SD_RSP1 Store the response from the SD card/MMC 0 15 read-only SD_RSP10 SD Card Response Register 10 0x18 32 read-only n 0x0 0x0 SD_RSP10 Store the response from the SD card/MMC 0 31 read-only SD_RSP3 SD Card Response Register 3 0x24 32 read-only n 0x0 0x0 Reserved These bits are read as 0000000000000000. 16 15 read-only SD_RSP3 Store the response from the SD card/MMC 0 15 read-only SD_RSP32 SD Card Response Register 32 0x20 32 read-only n 0x0 0x0 SD_RSP32 Store the response from the SD card/MMC 0 31 read-only SD_RSP5 SD Card Response Register 5 0x2C 32 read-only n 0x0 0x0 Reserved These bits are read as 0000000000000000. 16 15 read-only SD_RSP5 Store the response from the SD card/MMC 0 15 read-only SD_RSP54 SD Card Response Register 54 0x28 32 read-only n 0x0 0x0 SD_RSP54 Store the response from the SD card/MMC 0 31 read-only SD_RSP7 SD Card Response Register 7 0x34 32 read-only n 0x0 0x0 Reserved These bits are read as 000000000000000000000000. 8 23 read-only SD_RSP7 Store the response from the SD card/MMC 0 7 read-only SD_RSP76 SD Card Response Register 76 0x30 32 read-only n 0x0 0x0 Reserved These bits are read as 00000000. 24 7 read-only SD_RSP76 Store the response from the SD card/MMC 0 23 read-only SD_SECCNT Block Count Register 0x14 32 read-write n 0x0 0x0 SD_SECCNT Number of Transfer BlocksNOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. 0 31 read-write SD_SIZE Transfer Data Length Register 0x4C 32 read-write n 0x0 0x0 LEN Transfer Data SizeThese bits specify a size between 1 and 512 bytes for the transfer of single blocks.In cases of multiple block transfer with automatic issuing of CMD12 (CMD18 and CMD25), the only specifiable transfer data size is 512 bytes. Furthermore, in cases of multiple block transfer without automatic issuing of CMD12, as well as 512 bytes, 32, 64, 128, and 256 bytes are specifiable. However, in the reading of 32, 64, 128, and 256 bytes for the transfer of multiple blocks, this is restricted to multiple block transfer by CMD53.Additionally, if a command accompanies data transfer, do not set these bits to 0. 0 9 read-write Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write SD_STOP Data Stop Register 0x10 32 read-write n 0x0 0x0 Reserved These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000. 9 22 read-write Reserved These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000. 9 22 read-write SEC Block Count EnableSet SEC to 1 at multiple block transfer.When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued.NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. 8 read-write 0 Disables SD_SECCNT setting value. #0 1 Enables SD_SECCNT setting value. #1 STP Stop- When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface.However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.- When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.- When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.- Set STP to 1 after the response end flag has been set.- Set STP to 0 after the response end flag has been set. 0 read-write SOFT_RST Software Reset Register 0x1C0 32 read-write n 0x0 0x0 Reserved These bits are read as 00000000000000000000000000000. The write value should be 00000000000000000000000000000. 3 28 read-write Reserved These bits are read as 00000000000000000000000000000. The write value should be 00000000000000000000000000000. 3 28 read-write SDRST Software Reset of SD I/F Unit 0 read-write 0 Reset #0 1 Reset released #1 SPI0 Serial Peripheral Interface 0 SPI0 0x0 0x0 0x8 registers n 0x3E 0x2 registers n 0x8 0x1A registers n SPBR SPI Bit Rate Register 0xA 8 read-write n 0x0 0x0 SPR SPBR sets the bit rate in master mode. 0 7 read-write SPCKD SPI Clock Delay Register 0xC 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPCMD0 SPI Command Register %s 0x10 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD1 SPI Command Register %s 0x12 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD2 SPI Command Register %s 0x14 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD3 SPI Command Register %s 0x16 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD4 SPI Command Register %s 0x18 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD5 SPI Command Register %s 0x1A 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD6 SPI Command Register %s 0x1C 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD7 SPI Command Register %s 0x1E 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCR SPI Control Register 0x0 8 read-write n 0x0 0x0 MODFEN Mode Fault Error Detection Enable 2 read-write 0 Disables the detection of mode fault error #0 1 Enables the detection of mode fault error #1 MSTR SPI Master/Slave Mode Select 3 read-write 0 Slave mode #0 1 Master mode #1 SPE SPI Function Enable 6 read-write 0 Disables the SPI function #0 1 Enables the SPI function #1 SPEIE SPI Error Interrupt Enable 4 read-write 0 Disables the generation of SPI error interrupt requests #0 1 Enables the generation of SPI error interrupt requests #1 SPMS SPI Mode Select 0 read-write 0 SPI operation (4-wire method) #0 1 Clock synchronous operation (3-wire method) #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 read-write 0 Disables the generation of SPI receive buffer full interrupt requests #0 1 Enables the generation of SPI receive buffer full interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 read-write 0 Disables the generation of transmit buffer empty interrupt requests #0 1 Enables the generation of transmit buffer empty interrupt requests #1 TXMD Communications Operating Mode Select 1 read-write 0 Full-duplex synchronous serial communications #0 1 Serial communications consisting of only transmit operations #1 SPCR2 SPI Control Register 2 0xF 8 read-write n 0x0 0x0 PTE Parity Self-Testing 3 read-write 0 Disables the self-diagnosis function of the parity circuit #0 1 Enables the self-diagnosis function of the parity circuit #1 SCKASE RSPCK Auto-Stop Function Enable 4 read-write 0 Disables the RSPCK auto-stop function #0 1 Enables the RSPCK auto-stop function #1 SPIIE SPI Idle Interrupt Enable 2 read-write 0 Disables the generation of idle interrupt requests #0 1 Enables the generation of idle interrupt requests #1 SPOE Parity Mode 1 read-write 0 Selects even parity for use in transmission and reception #0 1 Selects odd parity for use in transmission and reception #1 SPPE Parity Enable 0 read-write 0 Does not add the parity bit to transmit data and does not check the parity bit of receive data #0 1 Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) #1 SPTDDL RSPI Transmit Data Delay 5 2 read-write 010 Same as above #010 011 Same as above #011 100 Same as above #100 101 Same as above #101 110 Same as above #110 111 Same as above #111 SPCR3 RSPI Control Register 3 0x21 8 read-write n 0x0 0x0 BFDS Between Burst Transfer Frames Delay Select 1 read-write 0 Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer #0 1 Delay between frames is not inserted in burst transfer. #1 CENDIE RSPI Communication End Interrupt Enable 4 read-write 0 Communication end interrupt request is disabled. #0 1 Communication end interrupt request is enabled. #1 ETXMD Extended Communication Mode Select 0 read-write 0 Full-duplex synchronous or transmit-only serial communications. #0 1 Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SPDCR SPI Data Control Register 0xB 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write SLSEL SSL Pin Output Select 2 1 read-write 00 SSL2 to SSL7->output, SSL1->output #00 01 SSL2 to SSL7->I/O, SSL1->I/O #01 10 SSL2 to SSL7->I/O, SSL1->output #10 11 Setting prohibited #11 SPBYT SPI Byte Access Specification 6 read-write 0 SPDR is accessed in word or longword (SPLW is valid) #0 1 SPDR is accessed in byte (SPLW is invalid) #1 SPFC Number of Frames Specification 0 1 read-write 00 1 frame #00 01 2 frames #01 10 3 frames #10 11 4 frames. #11 SPLW SPI Word Access/Halfword Access Specification 5 read-write 0 SPDR_HA is valid to access in halfwords #0 1 SPDR is valid (to access in words). #1 SPRDTD RSPI Receive/Transmit Data Selection 4 read-write 0 SPDR values are read from the receive buffer #0 1 SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) #1 SPDCR2 SPI Data Control Register 2 0x20 8 read-write n 0x0 0x0 BYSW Byte Swap Operating Mode Select 0 read-write 0 Byte Swap Operating Mode disabled #0 1 Byte Swap Operating Mode enabled #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write SINV Serial data invert bit 1 read-write 0 Not invert serial data #0 1 Invert serial data. #1 SPDR SPI Data Register 0x4 32 read-write n 0x0 0x0 SPDR SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR. 0 31 read-write SPDR_HA SPI Data Register ( halfword access ) SPDR 0x4 16 read-write n 0x0 0x0 SPDR_HA SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA. 0 15 read-write SPND SPI Next-Access Delay Register 0xE 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLK #000 001 2 RSPCK + 2 PCLK #001 010 3 RSPCK + 2 PCLK #010 011 4 RSPCK + 2 PCLK #011 100 5 RSPCK + 2 PCLK #100 101 6 RSPCK + 2 PCLK #101 110 7 RSPCK + 2 PCLK #110 111 8 RSPCK + 2 PCLK #111 SPPCR RSPI Pin Control Register 0x2 8 read-write n 0x0 0x0 MOIFE MOSI Idle Value Fixing Enable 5 read-write 0 MOSI output value equals final data from previous transfer #0 1 MOSI output value equals the value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 read-write 0 The level output on the MOSIn pin during MOSI idling corresponds to low. #0 1 The level output on the MOSIn pin during MOSI idling corresponds to high. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SPLP RSPI Loopback 0 read-write 0 Normal mode #0 1 Loopback mode (data is inverted for transmission) #1 SPLP2 RSPI Loopback 2 1 read-write 0 Normal mode #0 1 Loopback mode (data is not inverted for transmission) #1 SPPR RSPI Parameter Read Register 0x3E 16 read-write n 0x0 0x0 BUFNUM Buffer Number check 8 2 read-write 001 1 Buffer #001 100 4 Buffer #100 BUFWID Buffer Width check 4 read-write 0 16bit #0 1 32bit #1 CMDNUM Command Number check 12 3 read-write 0001 1 Command #0001 1000 8 Command #1000 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write SPSCR SPI Sequence Control Register 0x8 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPSLN RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0. 0 2 read-write 000 Length 1 SPDMDx x = 0->0->... #000 001 Length 2 SPDMDx x = 0->1->0->... #001 010 Length 3 SPDMDx x = 0->1->2->0->... #010 011 Length 4 SPDMDx x = 0->1->2->3->0->... #011 100 Length 5 SPDMDx x = 0->1->2->3->4->0->... #100 101 Length 6 SPDMDx x = 0->1->2->3->4->5->0->... #101 110 Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->... #110 111 Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->... #111 SPSR SPI Status Register 0x3 8 read-write n 0x0 0x0 CENDF Communication End Flag 6 read-write 0 The RSPI is not communicating or communicating. #0 1 The RSPI communication completed. #1 IDLNF SPI Idle Flag 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 read-write 0 Neither mode fault error nor underrun error occurs #0 1 A mode fault error or an underrun error occurs. #1 OVRF Overrun Error Flag 0 read-write 0 No overrun error occurs #0 1 An overrun error occurs #1 PERF Parity Error Flag 3 read-write 0 No parity error occurs #0 1 A parity error occurs #1 SPRF SPI Receive Buffer Full Flag 7 read-only 0 No valid data in SPDR #0 1 Valid data found in SPDR #1 SPTEF SPI Transmit Buffer Empty Flag 5 read-only 0 Data found in the transmit buffer #0 1 No data in the transmit buffer #1 UDRF Underrun Error Flag(When MODF is 0, This bit is invalid.) 4 read-write 0 A mode fault error occurs (MODF=1) #0 1 An underrun error occurs (MODF=1) #1 SPSSR SPI Sequence Status Register 0x9 8 read-only n 0x0 0x0 Reserved This bit is read as 0. 7 read-only Reserved This bit is read as 0. 7 read-only SPCP RSPI Command Pointer 0 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPECM RSPI Error Command 4 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SSLND SPI Slave Select Negation Delay Register 0xD 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLP SPI Slave Select Polarity Register 0x1 8 read-write n 0x0 0x0 SSL0P SSL0 Signal Polarity Setting 0 read-write 0 SSL0 signal is active low #0 1 SSL0 signal is active high #1 SSL1P SSL1 Signal Polarity Setting 1 read-write 0 SSL1 signal is active low #0 1 SSL1 signal is active high #1 SSL2P SSL2 Signal Polarity Setting 2 read-write 0 SSL2 signal is active low #0 1 SSL2 signal is active high #1 SSL3P SSL3 Signal Polarity Setting 3 read-write 0 SSL3 signal is active low #0 1 SSL3 signal is active high #1 SSL4P SSL4 Signal Polarity Setting 4 read-write 0 SSL4 signal is active low #0 1 SSL4 signal is active high #1 SSL5P SSL5 Signal Polarity Setting 5 read-write 0 SSL5 signal is active low #0 1 SSL5 signal is active high #1 SSL6P SSL6 Signal Polarity Setting 6 read-write 0 SSL6 signal is active low #0 1 SSL6 signal is active high #1 SSL7P SSL7 Signal Polarity Setting 7 read-write 0 SSL7 signal is active low #0 1 SSL7 signal is active high #1 SPI1 Serial Peripheral Interface 1 SPI0 0x0 0x0 0x8 registers n 0x3E 0x2 registers n 0x8 0x1A registers n SPBR SPI Bit Rate Register 0xA 8 read-write n 0x0 0x0 SPR SPBR sets the bit rate in master mode. 0 7 read-write SPCKD SPI Clock Delay Register 0xC 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPCMD0 SPI Command Register %s 0x10 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD1 SPI Command Register %s 0x12 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD2 SPI Command Register %s 0x14 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD3 SPI Command Register %s 0x16 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD4 SPI Command Register %s 0x18 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD5 SPI Command Register %s 0x1A 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD6 SPI Command Register %s 0x1C 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCMD7 SPI Command Register %s 0x1E 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 100 SSL4 #100 101 SSL5 #101 110 SSL6 #110 111 SSL7 #111 SSLKP SSL Signal Level Keeping 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning of the next access. #1 SPCR SPI Control Register 0x0 8 read-write n 0x0 0x0 MODFEN Mode Fault Error Detection Enable 2 read-write 0 Disables the detection of mode fault error #0 1 Enables the detection of mode fault error #1 MSTR SPI Master/Slave Mode Select 3 read-write 0 Slave mode #0 1 Master mode #1 SPE SPI Function Enable 6 read-write 0 Disables the SPI function #0 1 Enables the SPI function #1 SPEIE SPI Error Interrupt Enable 4 read-write 0 Disables the generation of SPI error interrupt requests #0 1 Enables the generation of SPI error interrupt requests #1 SPMS SPI Mode Select 0 read-write 0 SPI operation (4-wire method) #0 1 Clock synchronous operation (3-wire method) #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 read-write 0 Disables the generation of SPI receive buffer full interrupt requests #0 1 Enables the generation of SPI receive buffer full interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 read-write 0 Disables the generation of transmit buffer empty interrupt requests #0 1 Enables the generation of transmit buffer empty interrupt requests #1 TXMD Communications Operating Mode Select 1 read-write 0 Full-duplex synchronous serial communications #0 1 Serial communications consisting of only transmit operations #1 SPCR2 SPI Control Register 2 0xF 8 read-write n 0x0 0x0 PTE Parity Self-Testing 3 read-write 0 Disables the self-diagnosis function of the parity circuit #0 1 Enables the self-diagnosis function of the parity circuit #1 SCKASE RSPCK Auto-Stop Function Enable 4 read-write 0 Disables the RSPCK auto-stop function #0 1 Enables the RSPCK auto-stop function #1 SPIIE SPI Idle Interrupt Enable 2 read-write 0 Disables the generation of idle interrupt requests #0 1 Enables the generation of idle interrupt requests #1 SPOE Parity Mode 1 read-write 0 Selects even parity for use in transmission and reception #0 1 Selects odd parity for use in transmission and reception #1 SPPE Parity Enable 0 read-write 0 Does not add the parity bit to transmit data and does not check the parity bit of receive data #0 1 Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) #1 SPTDDL RSPI Transmit Data Delay 5 2 read-write 010 Same as above #010 011 Same as above #011 100 Same as above #100 101 Same as above #101 110 Same as above #110 111 Same as above #111 SPCR3 RSPI Control Register 3 0x21 8 read-write n 0x0 0x0 BFDS Between Burst Transfer Frames Delay Select 1 read-write 0 Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer #0 1 Delay between frames is not inserted in burst transfer. #1 CENDIE RSPI Communication End Interrupt Enable 4 read-write 0 Communication end interrupt request is disabled. #0 1 Communication end interrupt request is enabled. #1 ETXMD Extended Communication Mode Select 0 read-write 0 Full-duplex synchronous or transmit-only serial communications. #0 1 Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SPDCR SPI Data Control Register 0xB 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write SLSEL SSL Pin Output Select 2 1 read-write 00 SSL2 to SSL7->output, SSL1->output #00 01 SSL2 to SSL7->I/O, SSL1->I/O #01 10 SSL2 to SSL7->I/O, SSL1->output #10 11 Setting prohibited #11 SPBYT SPI Byte Access Specification 6 read-write 0 SPDR is accessed in word or longword (SPLW is valid) #0 1 SPDR is accessed in byte (SPLW is invalid) #1 SPFC Number of Frames Specification 0 1 read-write 00 1 frame #00 01 2 frames #01 10 3 frames #10 11 4 frames. #11 SPLW SPI Word Access/Halfword Access Specification 5 read-write 0 SPDR_HA is valid to access in halfwords #0 1 SPDR is valid (to access in words). #1 SPRDTD RSPI Receive/Transmit Data Selection 4 read-write 0 SPDR values are read from the receive buffer #0 1 SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) #1 SPDCR2 SPI Data Control Register 2 0x20 8 read-write n 0x0 0x0 BYSW Byte Swap Operating Mode Select 0 read-write 0 Byte Swap Operating Mode disabled #0 1 Byte Swap Operating Mode enabled #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write SINV Serial data invert bit 1 read-write 0 Not invert serial data #0 1 Invert serial data. #1 SPDR SPI Data Register 0x4 32 read-write n 0x0 0x0 SPDR SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR. 0 31 read-write SPDR_HA SPI Data Register ( halfword access ) SPDR 0x4 16 read-write n 0x0 0x0 SPDR_HA SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA. 0 15 read-write SPND SPI Next-Access Delay Register 0xE 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLK #000 001 2 RSPCK + 2 PCLK #001 010 3 RSPCK + 2 PCLK #010 011 4 RSPCK + 2 PCLK #011 100 5 RSPCK + 2 PCLK #100 101 6 RSPCK + 2 PCLK #101 110 7 RSPCK + 2 PCLK #110 111 8 RSPCK + 2 PCLK #111 SPPCR RSPI Pin Control Register 0x2 8 read-write n 0x0 0x0 MOIFE MOSI Idle Value Fixing Enable 5 read-write 0 MOSI output value equals final data from previous transfer #0 1 MOSI output value equals the value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 read-write 0 The level output on the MOSIn pin during MOSI idling corresponds to low. #0 1 The level output on the MOSIn pin during MOSI idling corresponds to high. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SPLP RSPI Loopback 0 read-write 0 Normal mode #0 1 Loopback mode (data is inverted for transmission) #1 SPLP2 RSPI Loopback 2 1 read-write 0 Normal mode #0 1 Loopback mode (data is not inverted for transmission) #1 SPPR RSPI Parameter Read Register 0x3E 16 read-write n 0x0 0x0 BUFNUM Buffer Number check 8 2 read-write 001 1 Buffer #001 100 4 Buffer #100 BUFWID Buffer Width check 4 read-write 0 16bit #0 1 32bit #1 CMDNUM Command Number check 12 3 read-write 0001 1 Command #0001 1000 8 Command #1000 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write SPSCR SPI Sequence Control Register 0x8 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPSLN RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0. 0 2 read-write 000 Length 1 SPDMDx x = 0->0->... #000 001 Length 2 SPDMDx x = 0->1->0->... #001 010 Length 3 SPDMDx x = 0->1->2->0->... #010 011 Length 4 SPDMDx x = 0->1->2->3->0->... #011 100 Length 5 SPDMDx x = 0->1->2->3->4->0->... #100 101 Length 6 SPDMDx x = 0->1->2->3->4->5->0->... #101 110 Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->... #110 111 Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->... #111 SPSR SPI Status Register 0x3 8 read-write n 0x0 0x0 CENDF Communication End Flag 6 read-write 0 The RSPI is not communicating or communicating. #0 1 The RSPI communication completed. #1 IDLNF SPI Idle Flag 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 read-write 0 Neither mode fault error nor underrun error occurs #0 1 A mode fault error or an underrun error occurs. #1 OVRF Overrun Error Flag 0 read-write 0 No overrun error occurs #0 1 An overrun error occurs #1 PERF Parity Error Flag 3 read-write 0 No parity error occurs #0 1 A parity error occurs #1 SPRF SPI Receive Buffer Full Flag 7 read-only 0 No valid data in SPDR #0 1 Valid data found in SPDR #1 SPTEF SPI Transmit Buffer Empty Flag 5 read-only 0 Data found in the transmit buffer #0 1 No data in the transmit buffer #1 UDRF Underrun Error Flag(When MODF is 0, This bit is invalid.) 4 read-write 0 A mode fault error occurs (MODF=1) #0 1 An underrun error occurs (MODF=1) #1 SPSSR SPI Sequence Status Register 0x9 8 read-only n 0x0 0x0 Reserved This bit is read as 0. 7 read-only Reserved This bit is read as 0. 7 read-only SPCP RSPI Command Pointer 0 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPECM RSPI Error Command 4 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SSLND SPI Slave Select Negation Delay Register 0xD 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLP SPI Slave Select Polarity Register 0x1 8 read-write n 0x0 0x0 SSL0P SSL0 Signal Polarity Setting 0 read-write 0 SSL0 signal is active low #0 1 SSL0 signal is active high #1 SSL1P SSL1 Signal Polarity Setting 1 read-write 0 SSL1 signal is active low #0 1 SSL1 signal is active high #1 SSL2P SSL2 Signal Polarity Setting 2 read-write 0 SSL2 signal is active low #0 1 SSL2 signal is active high #1 SSL3P SSL3 Signal Polarity Setting 3 read-write 0 SSL3 signal is active low #0 1 SSL3 signal is active high #1 SSL4P SSL4 Signal Polarity Setting 4 read-write 0 SSL4 signal is active low #0 1 SSL4 signal is active high #1 SSL5P SSL5 Signal Polarity Setting 5 read-write 0 SSL5 signal is active low #0 1 SSL5 signal is active high #1 SSL6P SSL6 Signal Polarity Setting 6 read-write 0 SSL6 signal is active low #0 1 SSL6 signal is active high #1 SSL7P SSL7 Signal Polarity Setting 7 read-write 0 SSL7 signal is active low #0 1 SSL7 signal is active high #1 SRAM SRAM Control SRAM 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0xC0 0x5 registers n 0xD0 0x1 registers n 0xD4 0x1 registers n 0xD8 0x1 registers n ECC1STS ECC 1-Bit Error Status Register 0xC3 8 read-write n 0x0 0x0 ECC1ERR ECC 1-Bit Error Status 0 read-write 0 No 1-bit ECC error occurred #0 1 1-bit ECC error occurred #1 ECC1STSEN ECC 1-Bit Error Information Update Enable Register 0xC2 8 read-write n 0x0 0x0 E1STSEN ECC 1-Bit Error Information Update Enable 0 read-write 0 Disable updating of 1-bit ECC error information #0 1 Enable updating of 1-bit ECC error information #1 ECC2STS ECC 2-Bit Error Status Register 0xC1 8 read-write n 0x0 0x0 ECC2ERR ECC 2-Bit Error Status 0 read-write 0 No 2-bit ECC error occurred #0 1 2-bit ECC error occurred #1 ECCETST ECC Test Control Register 0xD4 8 read-write n 0x0 0x0 TSTBYP ECC Bypass Select 0 read-write 0 Disable ECC bypass #0 1 Enable ECC bypass #1 ECCMODE ECC Operating Mode Control Register 0xC0 8 read-write n 0x0 0x0 ECCMOD ECC Operating Mode Select 0 1 read-write 00 Disable ECC function #00 01 Setting prohibited #01 10 Enable ECC function without error checking #10 11 Enable ECC function with error checking #11 ECCOAD SRAM ECC Error Operation After Detection Register 0xD8 8 read-write n 0x0 0x0 OAD Operation After Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 ECCPRCR ECC Protection Register 0xC4 8 read-write n 0x0 0x0 ECCPRCR Register Write Control 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW Write Key Code 1 6 read-write Others Disable write to the ECCPRCR bit 0x78 Enable write to the ECCPRCR bit 0x78 ECCPRCR2 ECC Protection Register 2 0xD0 8 read-write n 0x0 0x0 ECCPRCR2 Register Write Control 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW2 Write Key Code 1 6 read-write Others Disable write to the ECCPRCR2 bit 0x78 Enable write to the ECCPRCR2 bit 0x78 PARIOAD SRAM Parity Error Operation After Detection Register 0x0 8 read-write n 0x0 0x0 OAD Operation After Detection 0 read-write 0 Reset #0 1 Non-maskable interrupt #1 SRAMPRCR SRAM Protection Register 0x4 8 read-write n 0x0 0x0 KW Write Key Code 1 6 write-only SRAMPRCR Register Write Control 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 SSIE0 Serial Sound Interface Enhanced (SSIE) SSIE0 0x0 0x0 0x8 registers n 0x10 0x18 registers n SSICR Control Register 0x0 32 read-write n 0x0 0x0 BCKP Selects Bit Clock Polarity 13 read-write 0 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a falling edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a rising edge of SSIBCK). #0 1 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a rising edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a falling edge of SSIBCK). #1 CKDV Selects Bit Clock Division Ratio 4 3 read-write Others Setting prohibited 0x0 AUDIO_MCK 0x0 0x1 AUDIO_MCK/2 0x1 0x2 AUDIO_MCK/4 0x2 0x3 AUDIO_MCK/8 0x3 0x4 AUDIO_MCK/16 0x4 0x5 AUDIO_MCK/32 0x5 0x6 AUDIO_MCK/64 0x6 0x7 AUDIO_MCK/128 0x7 0x8 AUDIO_MCK/6 0x8 0x9 AUDIO_MCK/12 0x9 0xA AUDIO_MCK/24 0xa 0xB AUDIO_MCK/48 0xb 0xC AUDIO_MCK/96 0xc CKS Selects an Audio Clock for Master-mode Communication 30 read-write 0 Selects the AUDIO_CLK input #0 1 Selects the GTIOC2A (GPT output) #1 DEL Selects Serial Data Delay 8 read-write 0 Delay of 1 cycle of SSIBCK between SSILRCK/SSIFS and SSITXD0/SSIRXD0 #0 1 No delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0 #1 DWL Selects Data Word Length 19 2 read-write 000 8 bits #000 001 16 bits #001 010 18 bits #010 011 20 bits #011 100 22 bits #100 101 24 bits #101 110 32 bits #110 111 Setting prohibited #111 FRM Selects Frame Word Number 22 1 read-write IIEN Idle Mode Interrupt Output Enable 25 read-write 0 Disables idle mode interrupt output #0 1 Enables idle mode interrupt output #1 LRCKP Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal 12 read-write 0 The initial value is at a high level. The start trigger for a frame is synchronized with a falling edge of SSILRCK/SSIFS. #0 1 The initial value is at a low level. The start trigger for a frame is synchronized with a rising edge of SSILRCK/SSIFS. #1 MST Master Enable 14 read-write 0 Slave-mode communication #0 1 Master-mode communication #1 MUEN Mute Enable 3 read-write 0 Disables muting on the next frame boundary #0 1 Enables muting on the next frame boundary #1 PDTA Selects Placement Data Alignment 9 read-write 0 Left-justifies placement data (SSIFTDR, SSIFRDR) #0 1 Right-justifies placement data (SSIFTDR, SSIFRDR) #1 REN Reception Enable 0 read-write 0 Disables reception #0 1 Enables reception (starts reception) #1 ROIEN Receive Overflow Interrupt Output Enable 26 read-write 0 Disables receive overflow interrupt output #0 1 Enables receive overflow interrupt output #1 RUIEN Receive Underflow Interrupt Output Enable 27 read-write 0 Disables receive underflow interrupt output #0 1 Enables receive underflow interrupt output #1 SDTA Selects Serial Data Alignment 10 read-write 0 Transmits and receives serial data first and then padding bits #0 1 Transmit and receives padding bits first and then serial data #1 SPDP Selects Serial Padding Polarity 11 read-write 0 Padding data is at a low level #0 1 Padding data is at a high level #1 SWL Selects System Word Length 16 2 read-write 000 8 bits #000 001 16 bits #001 010 24 bits #010 011 32 bits #011 100 48 bits #100 101 64 bits #101 110 128 bits #110 111 256 bits #111 TEN Transmission Enable 1 read-write 0 Disables transmission #0 1 Enables transmission (starts transmission) #1 TOIEN Transmit Overflow Interrupt Output Enable 28 read-write 0 Disables transmit overflow interrupt output #0 1 Enables transmit overflow interrupt output #1 TUIEN Transmit Underflow Interrupt Output Enable 29 read-write 0 Disables transmit underflow interrupt output #0 1 Enables transmit underflow interrupt output #1 SSIFCR FIFO Control Register 0x10 32 read-write n 0x0 0x0 AUCKE AUDIO_MCK Enable in Mastermode Communication 31 read-write 0 Disables supply of AUDIO_MCK #0 1 Enables supply of AUDIO_MCK #1 BSW Byte Swap Enable 11 read-write 0 Disables byte swap #0 1 Enables byte swap #1 RFRST Receive FIFO Data Register Reset 0 read-write 0 Clears a receive data FIFO reset condition #0 1 Sets a receive data FIFO reset condition #1 RIE Receive Data Full Interrupt Output Enable 2 read-write 0 Disables receive data full interrupts #0 1 Enables receive data full interrupts #1 SSIRST Software Reset 16 read-write 0 Clears a software reset condition #0 1 Sets a software reset condition #1 TFRST Transmit FIFO Data Register Reset 1 read-write 0 Clears a transmit data FIFO reset condition #0 1 Sets a transmit data FIFO reset condition #1 TIE Transmit Data Empty Interrupt Output Enable 3 read-write 0 Disables transmit data empty interrupts #0 1 Enables transmit data empty interrupts #1 SSIFRDR Receive FIFO Data Register 0x1C 32 read-only n 0x0 0x0 SSIFRDR Receive FIFO Data 0 31 read-only SSIFSR FIFO Status Register 0x14 32 read-write n 0x0 0x0 RDC Number of Receive FIFO Data Indication Flag 8 5 read-only RDF Receive Data Full Flag 0 read-write 0 The size of received data in SSIFRDR is not more than the value of SSISCR.RDFS. #0 1 The size of received data in SSIFRDR is not less than the value of SSISCR.RDFS plus one. #1 TDC Number of Transmit FIFO Data Indication Flag 24 5 read-only TDE Transmit Data Empty Flag 16 read-write 0 The free space of SSIFTDR is not more than the value of SSISCR.TDES. #0 1 The free space of SSIFTDR is not less than the value of SSISCR.TDES plus one. #1 SSIFTDR Transmit FIFO Data Register 0x18 32 write-only n 0x0 0x0 SSIFTDR Transmit FIFO Data 0 31 write-only SSIOFR Audio Format Register 0x20 32 read-write n 0x0 0x0 BCKASTP Whether to Enable Stopping BCK Output When SSIE is in Idle Status 9 read-write 0 Always outputs BCK to the SSIBCK pin #0 1 Automatically controls output of BCK to the SSIBCK pin #1 LRCONT Whether to Enable LRCK/FS Continuation 8 read-write 0 Disables LRCK/FS continuation #0 1 Enables LRCK/FS continuation #1 OMOD Audio Format Select 0 1 read-write 00 I2S format #00 01 TDM format #01 10 Monaural format #10 11 Setting prohibited #11 SSISCR Status Control Register 0x24 32 read-write n 0x0 0x0 RDFS RDF Setting Condition Select 0 4 read-write TDES TDE Setting Condition Select 8 4 read-write SSISR Status Register 0x4 32 read-write n 0x0 0x0 IIRQ Idle Mode Status Flag 25 read-only 0 In the communication state #0 1 In the idle state #1 ROIRQ Receive Overflow Error Status Flag 26 read-write 0 No receive overflow error is generated. #0 1 A receive overflow error is generated. #1 RUIRQ Receive Underflow Error Status Flag 27 read-write 0 No receive underflow error is generated. #0 1 A receive underflow error is generated. #1 TOIRQ Transmit Overflow Error Status Flag 28 read-write 0 No transmit overflow error is generated. #0 1 A transmit overflow error is generated. #1 TUIRQ Transmit Underflow Error Status flag 29 read-write 0 No transmit underflow error is generated. #0 1 A transmit underflow error is generated. #1 SYSC System Control SYSC 0x0 0x10 0x4 registers n 0x16 0x1 registers n 0x1C 0x8 registers n 0x26 0x1 registers n 0x28 0x3 registers n 0x30 0x1 registers n 0x32 0x1 registers n 0x36 0x1 registers n 0x38 0x5 registers n 0x3C0 0x4 registers n 0x3C8 0xC registers n 0x3E 0x4 registers n 0x3E0 0x4 registers n 0x3FE 0xF registers n 0x40E 0x1 registers n 0x410 0x2 registers n 0x413 0x1 registers n 0x417 0x2 registers n 0x41A 0x2 registers n 0x41D 0x2 registers n 0x48 0x3 registers n 0x480 0x2 registers n 0x490 0x1 registers n 0x492 0x1 registers n 0x4BB 0x1 registers n 0x4C0 0x1 registers n 0x500 0x80 registers n 0x52 0x1 registers n 0x61 0x2 registers n 0x6C 0x2 registers n 0x74 0x2 registers n 0x88 0x4 registers n 0x92 0x1 registers n 0x94 0x2 registers n 0x98 0x4 registers n 0xA0 0x1 registers n 0xA2 0x1 registers n 0xAA 0x1 registers n 0xC 0x2 registers n 0xC0 0x2 registers n 0xE0 0x4 registers n BBFSAR Battery Backup Function Security Attribute Register 0x3D0 32 read-write n 0x0 0x0 NONSEC0 Non Secure Attribute bit 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 read-write 0 Secure #0 1 Non Secure #1 NONSEC16 Non Secure Attribute bit 16 16 read-write 0 Secure #0 1 Non Secure #1 NONSEC17 Non Secure Attribute bit 17 17 read-write 0 Secure #0 1 Non Secure #1 NONSEC18 Non Secure Attribute bit 18 18 read-write 0 Secure #0 1 Non Secure #1 NONSEC19 Non Secure Attribute bit 19 19 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC20 Non Secure Attribute bit 20 20 read-write 0 Secure #0 1 Non Secure #1 NONSEC21 Non Secure Attribute bit 21 21 read-write 0 Secure #0 1 Non Secure #1 NONSEC22 Non Secure Attribute bit 22 22 read-write 0 Secure #0 1 Non Secure #1 NONSEC23 Non Secure Attribute bit 23 23 read-write 0 Secure #0 1 Non Secure #1 BCKCR External Bus Clock Control Register 0x30 8 read-write n 0x0 0x0 BCLKDIV BCLK Pin Output Select 0 read-write 0 BCLK #0 1 BCLK ∕ 2. #1 CGFSAR Clock Generation Function Security Attribute Register 0x3C0 32 read-write n 0x0 0x0 NONSEC00 Non Secure Attribute bit 00 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC02 Non Secure Attribute bit 02 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC03 Non Secure Attribute bit 03 3 read-write 0 Secure #0 1 Non Secure #1 NONSEC04 Non Secure Attribute bit 04 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC05 Non Secure Attribute bit 05 5 read-write 0 Secure #0 1 Non Secure #1 NONSEC06 Non Secure Attribute bit 06 6 read-write 0 Secure #0 1 Non Secure #1 NONSEC07 Non Secure Attribute bit 07 7 read-write 0 Secure #0 1 Non Secure #1 NONSEC08 Non Secure Attribute bit 08 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC09 Non Secure Attribute bit 09 9 read-write 0 Secure #0 1 Non Secure #1 NONSEC11 Non Secure Attribute bit 11 11 read-write 0 Secure #0 1 Non Secure #1 NONSEC12 Non Secure Attribute bit 12 12 read-write 0 Secure #0 1 Non Secure #1 NONSEC16 Non Secure Attribute bit 16 16 read-write 0 Secure #0 1 Non Secure #1 NONSEC17 Non Secure Attribute bit 17 17 read-write 0 Secure #0 1 Non Secure #1 CKOCR Clock Out Control Register 0x3E 8 read-write n 0x0 0x0 CKODIV Clock Output Frequency Division Ratio 4 2 read-write 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 111 x 1/128 #111 CKOEN Clock Out Enable 7 read-write 0 Disable clock out #0 1 Enable clock out #1 CKOSEL Clock Out Source Select 0 2 read-write Others Setting prohibited 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 SOSC #100 101 Setting prohibited #101 DPFSAR Deep Standby Interrupt Factor Security Attribution Register 0x3E0 32 read-write n 0x0 0x0 DPFSA0_DPFSA7 Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7) 0 7 read-write 0 Secure #0 1 Non Secure #1 DPFSA16 Deep Standby Interrupt Factor Security Attribute bit 16 16 read-write 0 Secure #0 1 Non Secure #1 DPFSA17 Deep Standby Interrupt Factor Security Attribute bit 17 17 read-write 0 Secure #0 1 Non Secure #1 DPFSA18 Deep Standby Interrupt Factor Security Attribute bit 18 18 read-write 0 Secure #0 1 Non Secure #1 DPFSA19 Deep Standby Interrupt Factor Security Attribute bit 19 19 read-write 0 Secure #0 1 Non Secure #1 DPFSA20 Deep Standby Interrupt Factor Security Attribute bit 20 20 read-write 0 Secure #0 1 Non Secure #1 DPFSA24 Deep Standby Interrupt Factor Security Attribute bit 24 24 read-write 0 Secure #0 1 Non Secure #1 DPFSA26 Deep Standby Interrupt Factor Security Attribute bit 26 26 read-write 0 Secure #0 1 Non Secure #1 DPFSA27 Deep Standby Interrupt Factor Security Attribute bit 27 27 read-write 0 Secure #0 1 Non Secure #1 DPFSA8_DPFSA15 Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15) 8 7 read-write 0 Secure #0 1 Non Secure #1 DPSBYCR Deep Standby Control Register 0x400 8 read-write n 0x0 0x0 DEEPCUT Power-Supply Control 0 1 read-write 00 Power to the standby RAM, Low-speed on-chip oscillator, AGTn (n = 0 to 3), and USBFS resume detecting unit is supplied in Deep Software Standby mode. #00 01 Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode. #01 10 Setting prohibited #10 11 Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS/USBHS resume detecting unit is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. #11 DPSBY Deep Software Standby 7 read-write 0 Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) #0 1 Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) #1 IOKEEP I/O Port Rentention 6 read-write 0 When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. #0 1 When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. #1 DPSIEGR0 Deep Standby Interrupt Edge Register 0 0x40A 8 read-write n 0x0 0x0 DIRQ0EG IRQ0-DS Pin Edge Select 0 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ1EG IRQ1-DS Pin Edge Select 1 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ2EG IRQ2-DS Pin Edge Select 2 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ3EG IRQ3-DS Pin Edge Select 3 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ4EG IRQ4-DS Pin Edge Select 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ5EG IRQ5-DS Pin Edge Select 5 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ6EG IRQ6-DS Pin Edge Select 6 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ7EG IRQ7-DS Pin Edge Select 7 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DPSIEGR1 Deep Standby Interrupt Edge Register 1 0x40B 8 read-write n 0x0 0x0 DIRQ10EG IRQ10-DS Pin Edge Select 2 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge #1 DIRQ11EG IRQ11-DS Pin Edge Select 3 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ12EG IRQ12-DS Pin Edge Select 4 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ13EG IRQ13-DS Pin Edge Select 5 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ14EG IRQ14-DS Pin Edge Select 6 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ15EG IRQ15-DS Pin Edge Select 7 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ8EG IRQ8-DS Pin Edge Select 0 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DIRQ9EG IRQ9-DS Pin Edge Select 1 read-write 0 A cancel request is generated at a falling edge. #0 1 A cancel request is generated at a rising edge. #1 DPSIEGR2 Deep Standby Interrupt Edge Register 2 0x40C 8 read-write n 0x0 0x0 DLVD1EG LVD1 Edge Select 0 read-write 0 A cancel request is generated when VCC < Vdet1 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet1 (rise) is detected #1 DLVD2EG LVD2 Edge Select 1 read-write 0 A cancel request is generated when VCC < Vdet2 (fall) is detected #0 1 A cancel request is generated when VCC ≥ Vdet2 (rise) is detected #1 DNMIEG NMI Pin Edge Select 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DPSIER0 Deep Standby Interrupt Enable Register 0 0x402 8 read-write n 0x0 0x0 DIRQ0E IRQ0-DS Pin Enable 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ1E IRQ1-DS Pin Enable 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ2E IRQ2-DS Pin Enable 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ3E IRQ3-DS Pin Enable 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ4E IRQ4-DS Pin Enable 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ5E IRQ5-DS Pin Enable 5 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ6E IRQ6-DS Pin Enable 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ7E IRQ7-DS Pin Enable 7 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER1 Deep Standby Interrupt Enable Register 1 0x403 8 read-write n 0x0 0x0 DIRQ10E IRQ10-DS Pin Enable 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ11E IRQ11-DS Pin Enable 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ12E IRQ12-DS Pin Enable 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ13E IRQ13-DS Pin Enable 5 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ14E IRQ14-DS Pin Enable 6 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ15E IRQ15-DS Pin Enable 7 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ8E IRQ8-DS Pin Enable 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DIRQ9E IRQ9-DS Pin Enable 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER2 Deep Standby Interrupt Enable Register 2 0x404 8 read-write n 0x0 0x0 DLVD1IE LVD1 Deep Standby Cancel Signal Enable 0 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DLVD2IE LVD2 Deep Standby Cancel Signal Enable 1 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DNMIE NMI Pin Enable 4 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DRTCAIE RTC Alarm interrupt Deep Standby Cancel Signal Enable 3 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DRTCIIE RTC Interval interrupt Deep Standby Cancel Signal Enable 2 read-write 0 Cancelling Deep Software Standby mode is disabled #0 1 Cancelling Deep Software Standby mode is enabled #1 DPSIER3 Deep Standby Interrupt Enable Register 3 0x405 8 read-write n 0x0 0x0 DAGT1IE AGT1 Underflow Deep Standby Cancel Signal Enable 2 read-write 0 Cancelling deep standby mode is disabled #0 1 Cancelling deep standby mode is enabled #1 DAGT3IE AGT3 Underflow Deep Standby Cancel Signal Enable 3 read-write 0 Cancelling deep standby mode is disabled #0 1 Cancelling deep standby mode is enabled #1 DUSBFS0IE USBFS0 Suspend/Resume Deep Standby Cancel Signal Enable 0 read-write 0 Cancelling deep standby mode is disabled #0 1 Cancelling deep standby mode is enabled #1 DUSBHSIE USBHS Suspend/Resume Deep Standby Cancel Signal Enable 1 read-write 0 Cancelling deep standby mode is disabled #0 1 Cancelling deep standby mode is enabled #1 DPSIFR0 Deep Standby Interrupt Flag Register 0 0x406 8 read-write n 0x0 0x0 DIRQ0F IRQ0-DS Pin Deep Standby Cancel Flag 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ1F IRQ1-DS Pin Deep Standby Cancel Flag 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ2F IRQ2-DS Pin Deep Standby Cancel Flag 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ3F IRQ3-DS Pin Deep Standby Cancel Flag 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ4F IRQ4-DS Pin Deep Standby Cancel Flag 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ5F IRQ5-DS Pin Deep Standby Cancel Flag 5 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ6F IRQ6-DS Pin Deep Standby Cancel Flag 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ7F IRQ7-DS Pin Deep Standby Cancel Flag 7 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR1 Deep Standby Interrupt Flag Register 1 0x407 8 read-write n 0x0 0x0 DIRQ10F IRQ10-DS Pin Deep Standby Cancel Flag 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ11F IRQ11-DS Pin Deep Standby Cancel Flag 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ12F IRQ12-DS Pin Deep Standby Cancel Flag 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ13F IRQ13-DS Pin Deep Standby Cancel Flag 5 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ14F IRQ14-DS Pin Deep Standby Cancel Flag 6 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ15F IRQ15-DS Pin Deep Standby Cancel Flag 7 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ8F IRQ8-DS Pin Deep Standby Cancel Flag 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ9F IRQ9-DS Pin Deep Standby Cancel Flag 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR2 Deep Standby Interrupt Flag Register 2 0x408 8 read-write n 0x0 0x0 DLVD1IF LVD1 Deep Standby Cancel Flag 0 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DLVD2IF LVD2 Deep Standby Cancel Flag 1 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DNMIF NMI Pin Deep Standby Cancel Flag 4 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DRTCAIF RTC Alarm Interrupt Deep Standby Cancel Flag 3 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DRTCIIF RTC Interval Interrupt Deep Standby Cancel Flag 2 read-write 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR3 Deep Standby Interrupt Flag Register 3 0x409 8 read-write n 0x0 0x0 DAGT1IF AGT1 Underflow Deep Standby Cancel Flag 2 read-write 0 The cancel request is not generated. #0 1 The cancel request is generated. #1 DAGT3IF AGT3 Underflow Deep Standby Cancel Flag 3 read-write 0 The cancel request is not generated. #0 1 The cancel request is generated. #1 DUSBFS0IF USBFS0 Suspend/Resume Deep Standby Cancel Flag 0 read-write 0 The cancel request is not generated. #0 1 The cancel request is generated. #1 DPSWCR Deep Standby Wait Control Register 0x401 8 read-write n 0x0 0x0 WTSTS Deep Software Wait Standby Time Setting Bit 0 5 read-write Others Setting prohibited 0x0E Wait cycle for fast recovery 0x0e 0x19 Wait cycle for slow recovery 0x19 EBCKOCR External Bus Clock Output Control Register 0x52 8 read-write n 0x0 0x0 EBCKOEN EBCLK Pin Output Control 0 read-write 0 EBCLK pin output is disabled (fixed high) #0 1 EBCLK pin output is enabled. #1 FLLCR1 FLL Control Register1 0x39 8 read-write n 0x0 0x0 FLLEN FLL Enable 0 read-write 0 FLL function is disabled #0 1 FLL function is enabled. #1 FLLCR2 FLL Control Register2 0x3A 16 read-write n 0x0 0x0 FLLCNTL FLL Multiplication Control 0 10 read-write FWEPROR Flash P/E Protect Register 0x16 8 read-write n 0x0 0x0 FLWE Flash Programming and Erasure 0 1 read-write 00 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #00 01 Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #01 10 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #10 11 Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing. #11 HOCOCR High-Speed On-Chip Oscillator Control Register 0x36 8 read-write n 0x0 0x0 HCSTP HOCO Stop 0 read-write 0 Operate the HOCO clock #0 1 Stop the HOCO clock #1 HOCOUTCR HOCO User Trimming Control Register 0x62 8 read-write n 0x0 0x0 HOCOUTRM HOCO User Trimming 0 7 read-write LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write n 0x0 0x0 LCSTP LOCO Stop 0 read-write 0 Operate the LOCO clock #0 1 Stop the LOCO clock #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write n 0x0 0x0 LOCOUTRM LOCO User Trimming 0 7 read-write LPMSAR Low Power Mode Security Attribution Register 0x3C8 32 read-write n 0x0 0x0 NONSEC0 Non Secure Attribute bit 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 read-write 0 Secure #0 1 Non Secure #1 NONSEC4 Non Secure Attribute bit 4 4 read-write 0 Secure #0 1 Non Secure #1 NONSEC8 Non Secure Attribute bit 8 8 read-write 0 Secure #0 1 Non Secure #1 NONSEC9 Non Secure Attribute bit 9 9 read-write 0 Secure #0 1 Non Secure #1 LVD1CMPCR Voltage Monitoring 1 Comparator Control Register 0x417 8 read-write n 0x0 0x0 LVD1E Voltage Detection 1 Enable 7 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVD1LVL Voltage Detection 1 Level Select (Standard voltage during drop in voltage) 0 4 read-write Others Setting prohibited 0x11 2.99 V (Vdet1_11) 0x11 0x12 2.92 V (Vdet1_12) 0x12 0x13 2.85 V (Vdet1_13) 0x13 LVD1CR0 Voltage Monitor 1 Circuit Control Register 0 0x41A 8 read-write n 0x0 0x0 CMPE Voltage Monitor 1 Circuit Comparison Result Output Enable 2 read-write 0 Disable voltage monitor 1 circuit comparison result output #0 1 Enable voltage monitor 1 circuit comparison result output #1 DFDIS Voltage monitor 1 Digital Filter Disabled Mode Select 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 FSAMP Sampling Clock Select 4 1 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 1 Circuit Mode Select 6 read-write 0 Generate voltage monitor 1 interrupt on Vdet1 crossing #0 1 Enable voltage monitor 1 reset when the voltage falls to and below Vdet1 #1 RIE Voltage Monitor 1 Interrupt/Reset Enable 0 read-write 0 Disable #0 1 Enable #1 RN Voltage Monitor 1 Reset Negate Select 7 read-write 0 Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected #0 1 Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset #1 LVD1CR1 Voltage Monitor 1 Circuit Control Register 0xE0 8 read-write n 0x0 0x0 IDTSEL Voltage Monitor 1 Interrupt Generation Condition Select 0 1 read-write 00 When VCC >= Vdet1 (rise) is detected #00 01 When VCC < Vdet1 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 1 Interrupt Type Select 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD1SR Voltage Monitor 1 Circuit Status Register 0xE1 8 read-write n 0x0 0x0 DET Voltage Monitor 1 Voltage Variation Detection Flag 0 read-write 0 Not detected #0 1 Vdet1 crossing is detected #1 MON Voltage Monitor 1 Signal Monitor Flag 1 read-only 0 VCC < Vdet1 #0 1 VCC >= Vdet1 or MON is disabled #1 LVD2CMPCR Voltage Monitoring 2 Comparator Control Register 0x418 8 read-write n 0x0 0x0 LVD2E Voltage Detection 2 Enable 7 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVD2LVL Voltage Detection 2 Level Select (Standard voltage during drop in voltage) 0 2 read-write Others Setting prohibited 101 2.99 V (Vdet2_5) #101 110 2.92 V (Vdet2_6) #110 111 2.85 V (Vdet2_7) #111 LVD2CR0 Voltage Monitor 2 Circuit Control Register 0 0x41B 8 read-write n 0x0 0x0 CMPE Voltage Monitor 2 Circuit Comparison Result Output Enable 2 read-write 0 Disable voltage monitor 2 circuit comparison result output #0 1 Enable voltage monitor 2 circuit comparison result output #1 DFDIS Voltage monitor 2 Digital Filter Disabled Mode Select 1 read-write 0 Enable the digital filter #0 1 Disable the digital filter #1 FSAMP Sampling Clock Select 4 1 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 RI Voltage Monitor 2 Circuit Mode Select 6 read-write 0 Generate voltage monitor 2 interrupt on Vdet2 crossing #0 1 Enable voltage monitor 2 reset when the voltage falls to and below Vdet2 #1 RIE Voltage Monitor 2 Interrupt/Reset Enable 0 read-write 0 Disable #0 1 Enable #1 RN Voltage Monitor 2 Reset Negate Select 7 read-write 0 Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected #0 1 Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset #1 LVD2CR1 Voltage Monitor 2 Circuit Control Register 1 0xE2 8 read-write n 0x0 0x0 IDTSEL Voltage Monitor 2 Interrupt Generation Condition Select 0 1 read-write 00 When VCC>= Vdet2 (rise) is detected #00 01 When VCC < Vdet2 (fall) is detected #01 10 When fall and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor 2 Interrupt Type Select 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 LVD2SR Voltage Monitor 2 Circuit Status Register 0xE3 8 read-write n 0x0 0x0 DET Voltage Monitor 2 Voltage Variation Detection Flag 0 read-write 0 Not detected #0 1 Vdet2 crossing is detected #1 MON Voltage Monitor 2 Signal Monitor Flag 1 read-only 0 VCC < Vdet2 #0 1 VCC>= Vdet2 or MON is disabled #1 LVDSAR Low Voltage Detection Security Attribution Register 0x3CC 32 read-write n 0x0 0x0 NONSEC0 Non Secure Attribute bit 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 read-write 0 Secure #0 1 Non Secure #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x38 8 read-write n 0x0 0x0 MCSTP MOCO Stop 0 read-write 0 MOCO clock is operating #0 1 MOCO clock is stopped #1 MOCOUTCR MOCO User Trimming Control Register 0x61 8 read-write n 0x0 0x0 MOCOUTRM MOCO User Trimming 0 7 read-write MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write n 0x0 0x0 MODRV Main Clock Oscillator Drive Capability 0 Switching 4 1 read-write 00 20 MHz to 24 MHz #00 01 16 MHz to 20 MHz #01 10 8 MHz to 16 MHz #10 11 8 MHz #11 MOSEL Main Clock Oscillator Switching 6 read-write 0 Resonator #0 1 External clock input #1 MOSCCR Main Clock Oscillator Control Register 0x32 8 read-write n 0x0 0x0 MOSTP Main Clock Oscillator Stop 0 read-write 0 Operate the main clock oscillator #0 1 Stop the main clock oscillator #1 MOSCWTCR Main Clock Oscillator Wait Control Register 0xA2 8 read-write n 0x0 0x0 MSTS Main Clock Oscillator Wait Time Setting 0 3 read-write Others Setting prohibited 0x0 Setting prohibited 0x0 0x1 Wait time = 35 cycles (133.5 us) 0x1 0x2 Wait time = 67 cycles (255.6 us) 0x2 0x3 Wait time = 131 cycles (499.7 us) 0x3 0x4 Wait time = 259 cycles (988.0 us) 0x4 0x5 Wait time = 547 cycles (2086.6 us) 0x5 0x6 Wait time = 1059 cycles (4039.8 us) 0x6 0x7 Wait time = 2147 cycles (8190.2 us) 0x7 0x8 Wait time = 4291 cycles (16368.9 us) 0x8 0x9 Wait time = 8163 cycles (31139.4 us) 0x9 MSTPCRA Module Stop Control Register A 0x1C 32 read-write n 0x0 0x0 MSTPA0 SRAM0 Module Stop 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA22 DMA Controller/Data Transfer Controller Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA7 Standby SRAM Module Stop 7 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRE Module Stop Control Register E 0x10 32 read-write n 0x0 0x0 MSTPE14 Low Power Asynchronous General Purpose Timer 5 Module Stop 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE15 Low Power Asynchronous General Purpose Timer 4 Module Stop 15 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE22 GPT9 Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE23 GPT8 Module Stop 23 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE24 GPT7 Module Stop 24 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE25 GPT6 Module Stop 25 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE26 GPT5 Module Stop 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE27 GPT4 Module Stop 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE28 GPT3 Module Stop 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE29 GPT2 Module Stop 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE30 GPT1 Module Stop 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPE31 GPT0 Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 OCTACKCR Octal-SPI Clock Control Register 0x75 8 read-write n 0x0 0x0 OCTACKSEL Octal-SPI Clock (OCTACLK) Source Select 0 2 read-write Others Setting prohibited. 000 HOCO #000 001 MOCO (value after reset) #001 010 LOCO #010 011 Main clock oscillator #011 100 Sub-clock oscillator #100 101 PLL #101 110 PLL2 #110 OCTACKSRDY Octal-SPI Clock (OCTACLK) Switching Ready state flag 7 read-only 0 Switching not possible #0 1 Switching possible. #1 OCTACKSREQ Octal-SPI Clock (OCTACLK) Switching Request 6 read-write 0 No request #0 1 Request switching. #1 OCTACKDIVCR Octal-SPI Clock Division Control Register 0x6D 8 read-write n 0x0 0x0 OCTACKDIV Octal-SPI Clock (OCTACLK) Division Select 0 2 read-write Others Setting prohibited. 000 ∕ 1 (value after reset) #000 001 ∕ 2 #001 010 ∕ 4 #010 011 ∕ 6 #011 100 ∕ 8 #100 OPCCR Operating Power Control Register 0xA0 8 read-write n 0x0 0x0 OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Setting prohibited #01 10 Setting prohibited #10 11 Low-speed mode #11 OPCMTSF Operating Power Control Mode Transition Status Flag 4 read-only 0 Transition completed #0 1 During transition #1 OSCSF Oscillation Stabilization Flag Register 0x3C 8 read-only n 0x0 0x0 HOCOSF HOCO Clock Oscillation Stabilization Flag 0 read-only 0 The HOCO clock is stopped or is not yet stable #0 1 The HOCO clock is stable, so is available for use as the system clock #1 MOSCSF Main Clock Oscillation Stabilization Flag 3 read-only 0 The main clock oscillator is stopped (MOSTP = 1) or is not yet stable #0 1 The main clock oscillator is stable, so is available for use as the system clock #1 PLL2SF PLL2 Clock Oscillation Stabilization Flag 6 read-only 0 The PLL2 clock is stopped, or oscillation of the PLL2 clock is not stable yet #0 1 The PLL2 clock is stable, so is available for use as the system clock #1 PLLSF PLL Clock Oscillation Stabilization Flag 5 read-only 0 The PLL clock is stopped, or oscillation of the PLL clock is not stable yet #0 1 The PLL clock is stable, so is available for use as the system clock #1 OSTDCR Oscillation Stop Detection Control Register 0x40 8 read-write n 0x0 0x0 OSTDE Oscillation Stop Detection Function Enable 7 read-write 0 Disable oscillation stop detection function #0 1 Enable oscillation stop detection function #1 OSTDIE Oscillation Stop Detection Interrupt Enable 0 read-write 0 Disable oscillation stop detection interrupt (do not notify the POEG) #0 1 Enable oscillation stop detection interrupt (notify the POEG) #1 OSTDSR Oscillation Stop Detection Status Register 0x41 8 read-write n 0x0 0x0 OSTDF Oscillation Stop Detection Flag 0 read-write 0 Main clock oscillation stop not detected #0 1 Main clock oscillation stop detected #1 PLL2CCR PLL2 Clock Control Register 0x48 16 read-write n 0x0 0x0 PL2IDIV PLL2 Input Frequency Division Ratio Select 0 1 read-write Others Setting prohibited. 00 ∕ 1 (value after reset) #00 01 ∕ 2 #01 10 ∕ 3 #10 PL2SRCSEL PLL2 Clock Source Select 4 read-write 0 Main clock oscillator #0 1 HOCO. #1 PLL2MUL PLL2 Frequency Multiplication Factor Select 8 5 read-write PLL2CR PLL2 Control Register 0x4A 8 read-write n 0x0 0x0 PLL2STP PLL2 Stop Control 0 read-write 0 PLL2 is operating #0 1 PLL2 is stopped. #1 PLLCCR PLL Clock Control Register 0x28 16 read-write n 0x0 0x0 PLIDIV PLL Input Frequency Division Ratio Select 0 1 read-write Others Setting prohibited. 00 /1 #00 01 /2 #01 10 /3 #10 PLLMUL PLL Frequency Multiplication Factor Select 8 5 read-write PLSRCSEL PLL Clock Source Select 4 read-write 0 Main clock oscillator #0 1 HOCO #1 PLLCR PLL Control Register 0x2A 8 read-write n 0x0 0x0 PLLSTP PLL Stop Control 0 read-write 0 PLL is operating #0 1 PLL is stopped. #1 PRCR Protect Register 0x3FE 16 read-write n 0x0 0x0 PRC0 Enable writing to the registers related to the clock generation circuit 0 read-write 0 Write disabled #0 1 Write enabled #1 PRC1 Enable writing to the registers related to the low power modes, and the battery backup function 1 read-write 0 Write disabled #0 1 Write enabled #1 PRC3 Enable writing to the registers related to the LVD 3 read-write 0 Write disabled #0 1 Write enabled #1 PRC4 4 read-write 0 Write disabled #0 1 Write enabled #1 PRKEY PRC Key Code 8 7 write-only RSTSAR Reset Security Attribution Register LVDSAR 0x3CC 32 read-write n 0x0 0x0 NONSEC0 Non Secure Attribute bit 0 0 read-write 0 Secure #0 1 Non Secure #1 NONSEC1 Non Secure Attribute bit 1 1 read-write 0 Secure #0 1 Non Secure #1 NONSEC2 Non Secure Attribute bit 2 2 read-write 0 Secure #0 1 Non Secure #1 RSTSR0 Reset Status Register 0 0x410 8 read-write n 0x0 0x0 DPSRSTF Deep Software Standby Reset Flag 7 read-write 0 Deep software standby mode cancellation not requested by an interrupt. #0 1 Deep software standby mode cancellation requested by an interrupt. #1 LVD0RF Voltage Monitor 0 Reset Detect Flag 1 read-write 0 Voltage monitor 0 reset not detected #0 1 Voltage monitor 0 reset detected #1 LVD1RF Voltage Monitor 1 Reset Detect Flag 2 read-write 0 Voltage monitor 1 reset not detected #0 1 Voltage monitor 1 reset detected #1 LVD2RF Voltage Monitor 2 Reset Detect Flag 3 read-write 0 Voltage monitor 2 reset not detected #0 1 Voltage monitor 2 reset detected #1 PORF Power-On Reset Detect Flag 0 read-write 0 Power-on reset not detected #0 1 Power-on reset detected #1 RSTSR1 Reset Status Register 1 0xC0 16 read-write n 0x0 0x0 BUSMRF Bus Master MPU Error Reset Detect Flag 11 read-write 0 Bus master MPU error reset not detected #0 1 Bus master MPU error reset detected #1 CPERF Cache Parity Error Reset Detect Flag 15 read-write 0 Cache Parity error reset not detected. #0 1 Cache Parity error reset detected. #1 IWDTRF Independent Watchdog Timer Reset Detect Flag 0 read-write 0 Independent watchdog timer reset not detected #0 1 Independent watchdog timer reset detected #1 REERF SRAM ECC Error Reset Detect Flag 9 read-write 0 SRAM ECC error reset not detected #0 1 SRAM ECC error reset detected #1 RPERF SRAM Parity Error Reset Detect Flag 8 read-write 0 SRAM parity error reset not detected #0 1 SRAM parity error reset detected #1 SWRF Software Reset Detect Flag 2 read-write 0 Software reset not detected #0 1 Software reset detected #1 TZERF Trust Zone Error Reset Detect Flag 13 read-write 0 Trust Zone error reset not detected. #0 1 TrustZone error reset detected. #1 WDTRF Watchdog Timer Reset Detect Flag 1 read-write 0 Watchdog timer reset not detected #0 1 Watchdog timer reset detected #1 RSTSR2 Reset Status Register 2 0x411 8 read-write n 0x0 0x0 CWSF Cold/Warm Start Determination Flag 0 read-write 0 Cold start #0 1 Warm start #1 SBYCR Standby Control Register 0xC 16 read-write n 0x0 0x0 OPE Output Port Enable 14 read-write 0 In Software Standby mode or Deep Software Standby mode, set the address bus and other bus control signal to the high-impedance state. In snooze mode, the status of the address bus and bus control signals are same as before entering Software Standby mode. #0 1 In Software Standby mode or Deep Software Standby mode, address bus and other bus control signal retain the output state. #1 SSBY Software Standby 15 read-write 0 Sleep mode #0 1 Software Standby mode #1 SCKDIVCR System Clock Division Control Register 0x20 32 read-write n 0x0 0x0 FCK FlashIF Clock (FCLK) Select 28 2 read-write Others Setting prohibited. 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 (value after reset) #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 ICK System Clock (ICLK) Select 24 2 read-write Others Setting prohibited. 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 (value after reset) #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 PCKADC Peripheral Module Clock for ADC (PCLKADC) Select 4 2 read-write Others Setting prohibited. 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 PCKGPT Peripheral Module Clock for GPT (PCLKGPT) Select 0 2 read-write Others Setting prohibited. 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 PCKH Peripheral Module Clock H (PCLKH) Select 12 2 read-write Others Setting prohibited. 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 (value after reset) #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 PCKL Peripheral Module Clock L (PCLKL) Select 8 2 read-write Others Setting prohibited. 000 x 1/1 #000 001 x 1/2 #001 010 x 1/4 #010 011 x 1/8 #011 100 x 1/16 #100 101 x 1/32 #101 110 x 1/64 #110 SCKSCR System Clock Source Control Register 0x26 8 read-write n 0x0 0x0 CKSEL Clock Source Select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator (MOSC) #011 100 Sub-clock oscillator (SOSC) #100 SNZCR Snooze Control Register 0x92 8 read-write n 0x0 0x0 RXDREQEN RXD0 Snooze Request Enable 0 read-write 0 Ignore RXD0 falling edge in Software Standby mode #0 1 Detect RXD0 falling edge in Software Standby mode #1 SNZDTCEN DTC Enable in Snooze mode 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 SNZE Snooze mode Enable 7 read-write 0 Disable Snooze mode #0 1 Enable Snooze mode #1 SNZEDCR0 Snooze End Control Register 0 0x94 8 read-write n 0x0 0x0 AD0MATED ADC120 Compare Match Snooze End Enable 3 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD0UMTED ADC120 Compare Mismatch Snooze End Enable 4 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD1MATED ADC121 Compare Match Snooze End Enable 5 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AD1UMTED ADC121 Compare Mismatch Snooze End Enable 6 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 AGTUNFED AGT1 Underflow Snooze End Enable 0 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SCI0UMTED SCI0 Address Mismatch Snooze End Enable 7 read-write 0 Disable the snooze end request #0 1 Enable the snooze end request #1 SNZEDCR1 Snooze End Control Register 1 0x95 8 read-write n 0x0 0x0 AGT3UNFED AGT3 underflow Snooze End Enable 0 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 SNZREQCR0 Snooze Request Control Register 0 0x98 32 read-write n 0x0 0x0 SNZREQEN0 Enable IRQ0 pin snooze request 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable IRQ1 pin snooze request 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN10 Enable IRQ10 pin snooze request 10 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN11 Enable IRQ11 pin snooze request 11 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN12 Enable IRQ12 pin snooze request 12 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN13 Enable IRQ13 pin snooze request 13 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN14 Enable IRQ14 pin snooze request 14 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN15 Enable IRQ15 pin snooze request 15 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable IRQ2 pin snooze request 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN24 Enable RTC alarm snooze request 24 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN25 Enable RTC period snooze request 25 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN28 Enable AGT1 underflow snooze request 28 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN29 Enable AGT1 compare match A snooze request 29 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN3 Enable IRQ3 pin snooze request 3 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN30 Enable AGT1 compare match B snooze request 30 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN4 Enable IRQ4 pin snooze request 4 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN5 Enable IRQ5 pin snooze request 5 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN6 Enable IRQ6 pin snooze request 6 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN7 Enable IRQ7 pin snooze request 7 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN8 Enable IRQ8 pin snooze request 8 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN9 Enable IRQ9 pin snooze request 9 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQCR1 Snooze Request Control Register 1 0x88 32 read-write n 0x0 0x0 SNZREQEN0 Enable AGT3 underflow snooze request 0 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN1 Enable AGT3 underflow snooze request 1 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SNZREQEN2 Enable AGT3 underflow snooze request 2 read-write 0 Disable the snooze request #0 1 Enable the snooze request #1 SOMCR Sub-Clock Oscillator Mode Control Register 0x481 8 read-write n 0x0 0x0 SODRV Sub-Clock Oscillator Drive Capability Switching 1 read-write 0 Standard #0 1 Middle #1 SOPCCR Sub Operating Power Control Register 0xAA 8 read-write n 0x0 0x0 SOPCM Sub Operating Power Control Mode Select 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 SOPCMTSF Operating Power Control Mode Transition Status Flag 4 read-only 0 Transition completed #0 1 During transition #1 SOSCCR Sub-Clock Oscillator Control Register 0x480 8 read-write n 0x0 0x0 SOSTP Sub Clock Oscillator Stop 0 read-write 0 Operate the sub-clock oscillator #0 1 Stop the sub-clock oscillator #1 SYOCDCR System Control OCD Control Register 0x40E 8 read-write n 0x0 0x0 DBGEN Debugger Enable bit 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 DOCDF Deep Standby OCD flag 0 read-write 0 DBIRQ is not generated #0 1 DBIRQ is generated #1 TRCKCR Trace Clock Control Register 0x3F 8 read-write n 0x0 0x0 TRCK Trace Clock operating frequency select 0 3 read-write 0x0 /1 0x0 0x1 /2 (value after reset) 0x1 0x2 /4 0x2 TRCKEN Trace Clock operating Enable 7 read-write 0 Stop #0 1 Operation enable #1 USBCKCR USB Clock Control Register 0x74 8 read-write n 0x0 0x0 USBCKSEL USB Clock (USBCLK) Source Select 0 2 read-write Others Setting prohibited. 101 PLL #101 110 PLL2 #110 USBCKSRDY USB Clock (USBCLK) Switching Ready state flag 7 read-only 0 Impossible to Switch #0 1 Possible to Switch #1 USBCKSREQ USB Clock (USBCLK) Switching Request 6 read-write 0 No request #0 1 Request switching. #1 USBCKDIVCR USB Clock Division Control Register 0x6C 8 read-write n 0x0 0x0 USBCKDIV USB Clock (USBCLK) Division Select 0 2 read-write Others Setting prohibited. 010 ∕ 4 #010 101 ∕ 3 #101 110 ∕ 5 #110 VBATTMNSELR Battery Backup Voltage Monitor Function Select Register 0x41D 8 read-write n 0x0 0x0 VBATTMNSEL VBATT Low Voltage Detect Function Select Bit 0 read-write 0 Disables VBATT low voltage detect function #0 1 Enables VBATT low voltage detect function #1 VBATTMONR Battery Backup Voltage Monitor Register 0x41E 8 read-only n 0x0 0x0 VBATTMON VBATT Voltage Monitor Bit 0 read-only 0 VBATT ≥ Vbattldet #0 1 VBATT < Vbattldet #1 VBTBER VBATT Backup Enable Register 0x4C0 8 read-write n 0x0 0x0 VBAE VBATT backup register access enable bit 3 read-write 0 Disable to access VBTBKR #0 1 Enable to access VBTBKR #1 VBTBKR0 VBATT Backup Register (n = 0 to 127) 0x500 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR1 VBATT Backup Register (n = 0 to 127) 0x501 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR10 VBATT Backup Register (n = 0 to 127) 0x50A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR100 VBATT Backup Register (n = 0 to 127) 0x564 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR101 VBATT Backup Register (n = 0 to 127) 0x565 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR102 VBATT Backup Register (n = 0 to 127) 0x566 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR103 VBATT Backup Register (n = 0 to 127) 0x567 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR104 VBATT Backup Register (n = 0 to 127) 0x568 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR105 VBATT Backup Register (n = 0 to 127) 0x569 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR106 VBATT Backup Register (n = 0 to 127) 0x56A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR107 VBATT Backup Register (n = 0 to 127) 0x56B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR108 VBATT Backup Register (n = 0 to 127) 0x56C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR109 VBATT Backup Register (n = 0 to 127) 0x56D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR11 VBATT Backup Register (n = 0 to 127) 0x50B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR110 VBATT Backup Register (n = 0 to 127) 0x56E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR111 VBATT Backup Register (n = 0 to 127) 0x56F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR112 VBATT Backup Register (n = 0 to 127) 0x570 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR113 VBATT Backup Register (n = 0 to 127) 0x571 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR114 VBATT Backup Register (n = 0 to 127) 0x572 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR115 VBATT Backup Register (n = 0 to 127) 0x573 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR116 VBATT Backup Register (n = 0 to 127) 0x574 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR117 VBATT Backup Register (n = 0 to 127) 0x575 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR118 VBATT Backup Register (n = 0 to 127) 0x576 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR119 VBATT Backup Register (n = 0 to 127) 0x577 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR12 VBATT Backup Register (n = 0 to 127) 0x50C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR120 VBATT Backup Register (n = 0 to 127) 0x578 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR121 VBATT Backup Register (n = 0 to 127) 0x579 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR122 VBATT Backup Register (n = 0 to 127) 0x57A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR123 VBATT Backup Register (n = 0 to 127) 0x57B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR124 VBATT Backup Register (n = 0 to 127) 0x57C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR125 VBATT Backup Register (n = 0 to 127) 0x57D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR126 VBATT Backup Register (n = 0 to 127) 0x57E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR127 VBATT Backup Register (n = 0 to 127) 0x57F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR13 VBATT Backup Register (n = 0 to 127) 0x50D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR14 VBATT Backup Register (n = 0 to 127) 0x50E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR15 VBATT Backup Register (n = 0 to 127) 0x50F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR16 VBATT Backup Register (n = 0 to 127) 0x510 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR17 VBATT Backup Register (n = 0 to 127) 0x511 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR18 VBATT Backup Register (n = 0 to 127) 0x512 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR19 VBATT Backup Register (n = 0 to 127) 0x513 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR2 VBATT Backup Register (n = 0 to 127) 0x502 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR20 VBATT Backup Register (n = 0 to 127) 0x514 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR21 VBATT Backup Register (n = 0 to 127) 0x515 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR22 VBATT Backup Register (n = 0 to 127) 0x516 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR23 VBATT Backup Register (n = 0 to 127) 0x517 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR24 VBATT Backup Register (n = 0 to 127) 0x518 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR25 VBATT Backup Register (n = 0 to 127) 0x519 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR26 VBATT Backup Register (n = 0 to 127) 0x51A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR27 VBATT Backup Register (n = 0 to 127) 0x51B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR28 VBATT Backup Register (n = 0 to 127) 0x51C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR29 VBATT Backup Register (n = 0 to 127) 0x51D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR3 VBATT Backup Register (n = 0 to 127) 0x503 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR30 VBATT Backup Register (n = 0 to 127) 0x51E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR31 VBATT Backup Register (n = 0 to 127) 0x51F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR32 VBATT Backup Register (n = 0 to 127) 0x520 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR33 VBATT Backup Register (n = 0 to 127) 0x521 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR34 VBATT Backup Register (n = 0 to 127) 0x522 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR35 VBATT Backup Register (n = 0 to 127) 0x523 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR36 VBATT Backup Register (n = 0 to 127) 0x524 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR37 VBATT Backup Register (n = 0 to 127) 0x525 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR38 VBATT Backup Register (n = 0 to 127) 0x526 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR39 VBATT Backup Register (n = 0 to 127) 0x527 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR4 VBATT Backup Register (n = 0 to 127) 0x504 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR40 VBATT Backup Register (n = 0 to 127) 0x528 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR41 VBATT Backup Register (n = 0 to 127) 0x529 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR42 VBATT Backup Register (n = 0 to 127) 0x52A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR43 VBATT Backup Register (n = 0 to 127) 0x52B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR44 VBATT Backup Register (n = 0 to 127) 0x52C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR45 VBATT Backup Register (n = 0 to 127) 0x52D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR46 VBATT Backup Register (n = 0 to 127) 0x52E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR47 VBATT Backup Register (n = 0 to 127) 0x52F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR48 VBATT Backup Register (n = 0 to 127) 0x530 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR49 VBATT Backup Register (n = 0 to 127) 0x531 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR5 VBATT Backup Register (n = 0 to 127) 0x505 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR50 VBATT Backup Register (n = 0 to 127) 0x532 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR51 VBATT Backup Register (n = 0 to 127) 0x533 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR52 VBATT Backup Register (n = 0 to 127) 0x534 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR53 VBATT Backup Register (n = 0 to 127) 0x535 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR54 VBATT Backup Register (n = 0 to 127) 0x536 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR55 VBATT Backup Register (n = 0 to 127) 0x537 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR56 VBATT Backup Register (n = 0 to 127) 0x538 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR57 VBATT Backup Register (n = 0 to 127) 0x539 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR58 VBATT Backup Register (n = 0 to 127) 0x53A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR59 VBATT Backup Register (n = 0 to 127) 0x53B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR6 VBATT Backup Register (n = 0 to 127) 0x506 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR60 VBATT Backup Register (n = 0 to 127) 0x53C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR61 VBATT Backup Register (n = 0 to 127) 0x53D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR62 VBATT Backup Register (n = 0 to 127) 0x53E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR63 VBATT Backup Register (n = 0 to 127) 0x53F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR64 VBATT Backup Register (n = 0 to 127) 0x540 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR65 VBATT Backup Register (n = 0 to 127) 0x541 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR66 VBATT Backup Register (n = 0 to 127) 0x542 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR67 VBATT Backup Register (n = 0 to 127) 0x543 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR68 VBATT Backup Register (n = 0 to 127) 0x544 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR69 VBATT Backup Register (n = 0 to 127) 0x545 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR7 VBATT Backup Register (n = 0 to 127) 0x507 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR70 VBATT Backup Register (n = 0 to 127) 0x546 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR71 VBATT Backup Register (n = 0 to 127) 0x547 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR72 VBATT Backup Register (n = 0 to 127) 0x548 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR73 VBATT Backup Register (n = 0 to 127) 0x549 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR74 VBATT Backup Register (n = 0 to 127) 0x54A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR75 VBATT Backup Register (n = 0 to 127) 0x54B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR76 VBATT Backup Register (n = 0 to 127) 0x54C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR77 VBATT Backup Register (n = 0 to 127) 0x54D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR78 VBATT Backup Register (n = 0 to 127) 0x54E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR79 VBATT Backup Register (n = 0 to 127) 0x54F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR8 VBATT Backup Register (n = 0 to 127) 0x508 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR80 VBATT Backup Register (n = 0 to 127) 0x550 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR81 VBATT Backup Register (n = 0 to 127) 0x551 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR82 VBATT Backup Register (n = 0 to 127) 0x552 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR83 VBATT Backup Register (n = 0 to 127) 0x553 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR84 VBATT Backup Register (n = 0 to 127) 0x554 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR85 VBATT Backup Register (n = 0 to 127) 0x555 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR86 VBATT Backup Register (n = 0 to 127) 0x556 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR87 VBATT Backup Register (n = 0 to 127) 0x557 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR88 VBATT Backup Register (n = 0 to 127) 0x558 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR89 VBATT Backup Register (n = 0 to 127) 0x559 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR9 VBATT Backup Register (n = 0 to 127) 0x509 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR90 VBATT Backup Register (n = 0 to 127) 0x55A 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR91 VBATT Backup Register (n = 0 to 127) 0x55B 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR92 VBATT Backup Register (n = 0 to 127) 0x55C 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR93 VBATT Backup Register (n = 0 to 127) 0x55D 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR94 VBATT Backup Register (n = 0 to 127) 0x55E 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR95 VBATT Backup Register (n = 0 to 127) 0x55F 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR96 VBATT Backup Register (n = 0 to 127) 0x560 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR97 VBATT Backup Register (n = 0 to 127) 0x561 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR98 VBATT Backup Register (n = 0 to 127) 0x562 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTBKR99 VBATT Backup Register (n = 0 to 127) 0x563 8 read-write n 0x0 0x0 VBTBKRn VBATT Backup Register 0 7 read-write VBTICTLR VBATT Input Control Register 0x4BB 8 read-write n 0x0 0x0 VCH0INEN VBATT CH0 Input Enable 0 read-write 0 RTCIC0 inputs disable #0 1 RTCIC0 inputs enable #1 VCH1INEN VBATT CH1 Input Enable 1 read-write 0 RTCIC1 inputs disable #0 1 RTCIC1 inputs enable #1 VCH2INEN VBATT CH2 Input Enable 2 read-write 0 RTCIC2 inputs disable #0 1 RTCIC2 inputs enable #1 TSN Temperature Sensor TSN 0x0 0x0 0x1 registers n TSCR Temperature Sensor Control Register 0x0 8 read-write n 0x0 0x0 TSEN Temperature Sensor Enable 7 read-write 0 Stop the temperature sensor #0 1 Start the temperature sensor. #1 TSOE Temperature Sensor Output Enable 4 read-write 0 Disable output from the temperature sensor to the ADC12 #0 1 Enable output from the temperature sensor to the ADC12 #1 TZF TrustZone Filter TZF 0x0 0x0 0x2 registers n 0x180 0x4 registers n 0x4 0x2 registers n TZFOAD TrustZone Filter Operation After Detection Register 0x0 16 read-write n 0x0 0x0 KEY KeyCode 8 7 write-only OAD Operation after detection 0 read-write 0 Reset #0 1 Non-maskable interrupt #1 TZFPT TrustZone Filter Protect Register 0x4 16 read-write n 0x0 0x0 KEY KeyCode 8 7 write-only PROTECT Protection of register 0 read-write 0 All Bus TrustZone Filter register writing is protected. Read is possible. #0 1 All Bus TrustZone Filter register writing is possible. #1 TZFSAR TrustZone Filter Security Attribution Register 0x180 32 read-write n 0x0 0x0 TZFSA0 Security attributes of registers for TrustZone Filter 0 read-write 0 Secure #0 1 Non-secure #1 USBFS USB 2.0 Full-Speed Module USBFS 0x0 0x0 0x2 registers n 0x14 0x2 registers n 0x18 0xC registers n 0x28 0xC registers n 0x36 0x8 registers n 0x4 0x2 registers n 0x40 0x4 registers n 0x400 0xC registers n 0x46 0xC registers n 0x54 0xE registers n 0x64 0x2 registers n 0x68 0x2 registers n 0x6C 0x16 registers n 0x90 0x16 registers n 0xB0 0x8 registers n 0xD0 0xC registers n BCCTRL1 Battery Charging Control Register 1 0xB0 32 read-write n 0x0 0x0 CHGDETE CHGDET Enable 5 read-write 0 Disable CHGDET #0 1 Enable CHGDET #1 CHGDETST CHGDET Status Flag 9 read-only 0 The CHGDET pin is at low level #0 1 The CHGDET pin is at high level #1 IDPSRCE IDPSRC Control 1 read-write 0 Disable IDP_SRC circuit #0 1 Enable IDP_SRC circuit #1 PDDETE PDDET Enable 4 read-write 0 Disable PDDET #0 1 Enable PDDET #1 PDDETSTS PDDET Status Flag 8 read-only 0 The PDDET pin is at low level #0 1 The PDDET pin is at high level #1 RPDME UDM Pull-down Control 0 read-write 0 Disable UDM Pull-down #0 1 Enable UDM Pull-down #1 VDMSRCE VDMSRC Control 2 read-write 0 Disable VDM_SRC circuit #0 1 Enable VDM_SRC circuit #1 VDPSRCE VDPSRC Control 3 read-write 0 Disable VDP_SRC circuit #0 1 Enable VDP_SRC circuit #1 BCCTRL2 Battery Charging Control Register 2 0xB4 32 read-write n 0x0 0x0 BATCHGE Battery Charging Enable 7 read-write 0 Disable Battery Charging #0 1 Enable Battery Charging #1 DCPMODE DCP Mode Control 6 read-write 0 Disable DCP #0 1 Enable DCP #1 PHYDET Detect Sensitivity Adjustment 12 1 read-write BEMPENB BEMP Interrupt Enable Register 0x3A 16 read-write n 0x0 0x0 PIPE0BEMPE BEMP Interrupt Enable for Pipe 0 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE1BEMPE BEMP Interrupt Enable for Pipe 1 1 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE2BEMPE BEMP Interrupt Enable for Pipe 2 2 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE3BEMPE BEMP Interrupt Enable for Pipe 3 3 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE4BEMPE BEMP Interrupt Enable for Pipe 4 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE5BEMPE BEMP Interrupt Enable for Pipe 5 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE6BEMPE BEMP Interrupt Enable for Pipe 6 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE7BEMPE BEMP Interrupt Enable for Pipe 7 7 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE8BEMPE BEMP Interrupt Enable for Pipe 8 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE9BEMPE BEMP Interrupt Enable for Pipe 9 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BEMPSTS BEMP Interrupt Status Register 0x4A 16 read-write n 0x0 0x0 PIPE0BEMP BEMP Interrupt Status for Pipe 0 0 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE1BEMP BEMP Interrupt Status for Pipe 1 1 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE2BEMP BEMP Interrupt Status for Pipe 2 2 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE3BEMP BEMP Interrupt Status for Pipe 3 3 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE4BEMP BEMP Interrupt Status for Pipe 4 4 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE5BEMP BEMP Interrupt Status for Pipe 5 5 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE6BEMP BEMP Interrupt Status for Pipe 6 6 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE7BEMP BEMP Interrupt Status for Pipe 7 7 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE8BEMP BEMP Interrupt Status for Pipe 8 8 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 PIPE9BEMP BEMP Interrupt Status for Pipe 9 9 read-write 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 BRDYENB BRDY Interrupt Enable Register 0x36 16 read-write n 0x0 0x0 PIPE0BRDYE BRDY Interrupt Enable for Pipe 0 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE1BRDYE BRDY Interrupt Enable for Pipe 1 1 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE2BRDYE BRDY Interrupt Enable for Pipe 2 2 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE3BRDYE BRDY Interrupt Enable for Pipe 3 3 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE4BRDYE BRDY Interrupt Enable for Pipe 4 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE5BRDYE BRDY Interrupt Enable for Pipe 5 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE6BRDYE BRDY Interrupt Enable for Pipe 6 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE7BRDYE BRDY Interrupt Enable for Pipe 7 7 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE8BRDYE BRDY Interrupt Enable for Pipe 8 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE9BRDYE BRDY Interrupt Enable for Pipe 9 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BRDYSTS BRDY Interrupt Status Register 0x46 16 read-write n 0x0 0x0 PIPE0BRDY BRDY Interrupt Status for Pipe 0 0 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE1BRDY BRDY Interrupt Status for Pipe 1 1 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE2BRDY BRDY Interrupt Status for Pipe 2 2 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE3BRDY BRDY Interrupt Status for Pipe 3 3 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE4BRDY BRDY Interrupt Status for Pipe 4 4 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE5BRDY BRDY Interrupt Status for Pipe 5 5 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE6BRDY BRDY Interrupt Status for Pipe 6 6 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE7BRDY BRDY Interrupt Status for Pipe 7 7 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE8BRDY BRDY Interrupt Status for Pipe 8 8 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 PIPE9BRDY BRDY Interrupt Status for Pipe 9 9 read-write 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 CFIFO CFIFO Port Register 0x14 16 read-write n 0x0 0x0 FIFOPORT FIFO Port 0 15 read-write CFIFOCTR CFIFO Port Control Register 0x22 16 read-write n 0x0 0x0 BCLR CPU Buffer Clear 14 write-only 0 No operation #0 1 Clear FIFO buffer on the CPU side #1 BVAL Buffer Memory Valid Flag 15 read-write 0 Invalid (writing 0 has no effect) #0 1 Writing ended #1 DTLN Receive Data Length 0 8 read-only FRDY FIFO Port Ready 13 read-only 0 FIFO port access disabled #0 1 FIFO port access enabled #1 CFIFOL CFIFO Port Register CFIFO 0x14 8 read-write n 0x0 0x0 CFIFOSEL CFIFO Port Select Register 0x20 16 read-write n 0x0 0x0 BIGEND CFIFO Port Endian Control 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE CFIFO Port Access Pipe Specification 0 3 read-write Others Setting prohibited 0x0 Default Control Pipe 0x0 0x1 Pipe 1 0x1 0x2 Pipe 2 0x2 0x3 Pipe 3 0x3 0x4 Pipe 4 0x4 0x5 Pipe 5 0x5 0x6 Pipe 6 0x6 0x7 Pipe 7 0x7 0x8 Pipe 8 0x8 0x9 Pipe 9 0x9 ISEL CFIFO Port Access Direction When DCP Is Selected 5 read-write 0 Select reading from the FIFO buffer #0 1 Select writing to the FIFO buffer #1 MBW CFIFO Port Access Bit Width 10 read-write 0 8-bit width #0 1 16-bit width #1 RCNT Read Count Mode 15 read-write 0 The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN[8:0] value is cleared when all data is read from only a single plane. #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. #1 REW Buffer Pointer Rewind 14 write-only 0 Do not rewind buffer pointer #0 1 Rewind buffer pointer #1 D0FIFO D%sFIFO Port Register 0x18 16 read-write n 0x0 0x0 FIFOPORT FIFO Port 0 15 read-write D0FIFOCTR D%sFIFO Port Control Register 0x2A 16 read-write n 0x0 0x0 BCLR CPU Buffer Clear 14 read-write 0 No operation #0 1 Clear FIFO buffer on the CPU side #1 BVAL Buffer Memory Valid Flag 15 read-write 0 Invalid (writing 0 has no effect) #0 1 Writing ended #1 DTLN Receive Data Length 0 8 read-only FRDY FIFO Port Ready 13 read-only 0 FIFO port access disabled #0 1 FIFO port access enabled #1 D0FIFOL D%sFIFO Port Register D%sFIFO 0x18 8 read-write n 0x0 0x0 D0FIFOSEL D%sFIFO Port Select Register 0x28 16 read-write n 0x0 0x0 BIGEND FIFO Port Endian Control 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write Others Setting prohibited 0x0 Default Control Pipe 0x0 0x1 Pipe 1 0x1 0x2 Pipe 2 0x2 0x3 Pipe 3 0x3 0x4 Pipe 4 0x4 0x5 Pipe 5 0x5 0x6 Pipe 6 0x6 0x7 Pipe 7 0x7 0x8 Pipe 8 0x8 0x9 Pipe 9 0x9 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 read-write 0 Disable auto buffer clear mode #0 1 Enable auto buffer clear mode #1 DREQE DMA/DTC Transfer Request Enable 12 read-write 0 Disable DMA/DTC transfer request #0 1 Enable DMA/DTC transfer request #1 MBW FIFO Port Access Bit Width 10 read-write 0 8-bit width #0 1 16-bit width #1 RCNT Read Count Mode 15 read-write 0 Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode) #0 1 Decrement DTLN[8:0] bits each time receive data is read from DnFIFO #1 REW Buffer Pointer Rewind 14 write-only 0 Do not rewind buffer pointer #0 1 Rewind buffer pointer #1 D1FIFO D%sFIFO Port Register 0x1C 16 read-write n 0x0 0x0 FIFOPORT FIFO Port 0 15 read-write D1FIFOCTR D%sFIFO Port Control Register 0x2E 16 read-write n 0x0 0x0 BCLR CPU Buffer Clear 14 read-write 0 No operation #0 1 Clear FIFO buffer on the CPU side #1 BVAL Buffer Memory Valid Flag 15 read-write 0 Invalid (writing 0 has no effect) #0 1 Writing ended #1 DTLN Receive Data Length 0 8 read-only FRDY FIFO Port Ready 13 read-only 0 FIFO port access disabled #0 1 FIFO port access enabled #1 D1FIFOL D%sFIFO Port Register D%sFIFO 0x1C 8 read-write n 0x0 0x0 D1FIFOSEL D%sFIFO Port Select Register 0x2C 16 read-write n 0x0 0x0 BIGEND FIFO Port Endian Control 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write Others Setting prohibited 0x0 Default Control Pipe 0x0 0x1 Pipe 1 0x1 0x2 Pipe 2 0x2 0x3 Pipe 3 0x3 0x4 Pipe 4 0x4 0x5 Pipe 5 0x5 0x6 Pipe 6 0x6 0x7 Pipe 7 0x7 0x8 Pipe 8 0x8 0x9 Pipe 9 0x9 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 read-write 0 Disable auto buffer clear mode #0 1 Enable auto buffer clear mode #1 DREQE DMA/DTC Transfer Request Enable 12 read-write 0 Disable DMA/DTC transfer request #0 1 Enable DMA/DTC transfer request #1 MBW FIFO Port Access Bit Width 10 read-write 0 8-bit width #0 1 16-bit width #1 RCNT Read Count Mode 15 read-write 0 Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode) #0 1 Decrement DTLN[8:0] bits each time receive data is read from DnFIFO #1 REW Buffer Pointer Rewind 14 write-only 0 Do not rewind buffer pointer #0 1 Rewind buffer pointer #1 DCPCFG DCP Configuration Register 0x5C 16 read-write n 0x0 0x0 DIR Transfer Direction 4 read-write 0 Data receiving direction #0 1 Data transmitting direction #1 SHTNAK Pipe Disabled at End of Transfer 7 read-write 0 Keep pipe open after transfer ends #0 1 Disable pipe after transfer ends #1 DCPCTR DCP Control Register 0x60 16 read-write n 0x0 0x0 BSTS Buffer Status 15 read-only 0 Buffer access disabled #0 1 Buffer access enabled #1 CCPL Control Transfer End Enable 2 read-write 0 Disable control transfer completion #0 1 Enable control transfer completion #1 PBUSY Pipe Busy 5 read-only 0 DCP not used for the USB bus #0 1 DCP in use for the USB bus #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends on the buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Monitor 6 read-only 0 DATA0 #0 1 ATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 SUREQ Setup Token Transmission 14 read-write 0 Invalid (writing 0 has no effect) #0 1 Transmit setup packet #1 SUREQCLR SUREQ Bit Clear 11 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear SUREQ to 0 #1 DCPMAXP DCP Maximum Packet Size Register 0x5E 16 read-write n 0x0 0x0 DEVSEL Device Select 12 3 read-write Others Setting prohibited 0x0 Address 0000b 0x0 0x1 Address 0001b 0x1 0x2 Address 0010b 0x2 0x3 Address 0011b 0x3 0x4 Address 0100b 0x4 0x5 Address 0101b 0x5 MXPS Maximum Packet Size 0 6 read-write DEVADD0 Device Address %s Configuration Register 0xD0 16 read-write n 0x0 0x0 USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 Do not use DEVADDn #00 01 Low-speed #01 10 Full-speed #10 11 Setting prohibited #11 DEVADD1 Device Address %s Configuration Register 0xD2 16 read-write n 0x0 0x0 USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 Do not use DEVADDn #00 01 Low-speed #01 10 Full-speed #10 11 Setting prohibited #11 DEVADD2 Device Address %s Configuration Register 0xD4 16 read-write n 0x0 0x0 USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 Do not use DEVADDn #00 01 Low-speed #01 10 Full-speed #10 11 Setting prohibited #11 DEVADD3 Device Address %s Configuration Register 0xD6 16 read-write n 0x0 0x0 USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 Do not use DEVADDn #00 01 Low-speed #01 10 Full-speed #10 11 Setting prohibited #11 DEVADD4 Device Address %s Configuration Register 0xD8 16 read-write n 0x0 0x0 USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 Do not use DEVADDn #00 01 Low-speed #01 10 Full-speed #10 11 Setting prohibited #11 DEVADD5 Device Address %s Configuration Register 0xDA 16 read-write n 0x0 0x0 USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 Do not use DEVADDn #00 01 Low-speed #01 10 Full-speed #10 11 Setting prohibited #11 DPBCCTRL Deep Software Standby USB Battery Charging Control Register 0x408 32 read-write n 0x0 0x0 DPBATCHGE Battery Charging Enable 7 read-write 0 Disable Battery Charging #0 1 Enable Battery Charging #1 DPDCPMODE DCP Mode Control 6 read-write 0 Disable DCP #0 1 Enable DCP #1 DPPDDETE PDDET Enable 4 read-write 0 Disable PDDET #0 1 Enable PDDET #1 DPPHYDET Adjusts the detect sensitivity of Portable Device and Charging D- Port 12 1 read-write DPUSR0R Deep Software Standby USB Transceiver Control/Pin Monitor Register 0x400 32 read-write n 0x0 0x0 DM0 USB D– Input 17 read-only DOVCA0 USB OVRCURA Input 20 read-only DOVCB0 USB OVRCURB Input 21 read-only DP0 USB D+ Input 16 read-only DPDDET0 USB PDDET Input 22 read-only DRPD0 D+/D– Pull-Down Resistor Control 3 read-write 0 Disable DP/DM pull-down resistor #0 1 Enable DP/DM pull-down resistor #1 DVBSTS0 USB VBUS Input 23 read-only FIXPHY0 USB Transceiver Output Fix 4 read-write 0 Fix outputs in Normal mode and on return from Deep Software Standby mode #0 1 Fix outputs on transition to Deep Software Standby mode #1 RPUE0 DP Pull-Up Resistor Control 1 read-write 0 Disable DP pull-up resistor #0 1 Enable DP pull-up resistor #1 SRPC0 USB Single-ended Receiver Control 0 read-write 0 Disable input through DP and DM inputs #0 1 Enable input through DP and DM inputs #1 DPUSR1R Deep Software Standby USB Suspend/Resume Interrupt Register 0x404 32 read-write n 0x0 0x0 DMINT0 USB DM Interrupt Source Recovery 17 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of DM input #1 DMINTE0 USB DM Interrupt Enable/Clear 1 read-write 0 Disable recovery from Deep Software Standby mode by DM input #0 1 Enable recovery from Deep Software Standby mode by DM input #1 DOVRCRA0 USB OVRCURA Interrupt Source Recovery 20 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of OVRCURA input #1 DOVRCRAE0 USB OVRCURA Interrupt Enable/Clear 4 read-write 0 Disable recovery from Deep Software Standby mode by OVRCURA input #0 1 Enable recovery from Deep Software Standby mode by OVRCURA input #1 DOVRCRB0 USB OVRCURB Interrupt Source Recovery 21 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of OVRCURB input #1 DOVRCRBE0 USB OVRCURB Interrupt Enable/Clear 5 read-write 0 Disable recovery from Deep Software Standby mode by OVRCURB input #0 1 Enable recovery from Deep Software Standby mode by OVRCURB input #1 DPDDETE0 USB PDDET Interrupt Enable/Clear 6 read-write 0 Disable recovery from Deep Software Standby mode by PDDET input #0 1 Enable recovery from Deep Software Standby mode by PDDET input #1 DPDDETINT0 USB PDDET Interrupt Source Recovery 22 read-write 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of PDDET input #1 DPINT0 USB DP Interrupt Source Recovery 16 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of DP #1 DPINTE0 USB DP Interrupt Enable/Clear 0 read-write 0 Disable recovery from Deep Software Standby mode by DP input #0 1 Enable recovery from Deep Software Standby mode by DP input #1 DVBINT0 USB VBUS Interrupt Source Recovery 23 read-only 0 System has not recovered from Deep Software Standby mode #0 1 System recovered from Deep Software Standby mode because of VBUS input #1 DVBSE0 USB VBUS Interrupt Enable/Clear 7 read-write 0 Disable recovery from Deep Software Standby mode by VBUS input #0 1 Enable recovery from Deep Software Standby mode by VBUS input #1 DVCHGR Device State Change Register 0x4E 16 read-write n 0x0 0x0 DVCHG Device State Change 15 read-write 0 Disable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits #0 1 Enable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits #1 DVSTCTR0 Device State Control Register 0 0x1E 16 read-write n 0x0 0x0 EXICEN USB_EXICEN Output Pin Control 10 read-write 0 Output low on external USB_EXICEN pin #0 1 Output high on external USB_EXICEN pin #1 HNPBTOA Host Negotiation Protocol (HNP) Control 11 read-write RESUME Resume Output 5 read-write 0 Do not output resume signal #0 1 Output resume signal #1 RHST USB Bus Reset Status 0 2 read-only Others In host controller mode: USB bus reset in progress In device controller mode: Setting prohibited 000 In host controller mode: Communication speed indeterminate (powered state or no connection) In device controller mode: Communication speed indeterminate #000 001 In host controller mode: Low-speed connection In device controller mode: USB bus reset in progress #001 010 In host controller mode: Full-speed connection In device controller mode: USB bus reset in progress or full-speed connection #010 011 Setting prohibited #011 RWUPE Wakeup Detection Enable 7 read-write 0 Disable downstream port remote wakeup #0 1 Enable downstream port remote wakeup #1 UACT USB Bus Enable 4 read-write 0 Disable downstream port (disable SOF transmission) #0 1 Enable downstream port (enable SOF transmission) #1 USBRST USB Bus Reset Output 6 read-write 0 Do not output USB bus reset signal #0 1 Output USB bus reset signal #1 VBUSEN USB_VBUSEN Output Pin Control 9 read-write 0 Output low on external USB_VBUSEN pin #0 1 Output high on external USB_VBUSEN pin #1 WKUP Wakeup Output 8 read-write 0 Do not output remote wakeup signal #0 1 Output remote wakeup signal #1 FRMNUM Frame Number Register 0x4C 16 read-write n 0x0 0x0 CRCE Receive Data Error 14 read-write 0 No error occurred #0 1 Error occurred #1 FRNM Frame Number 0 10 read-only OVRN Overrun/Underrun Detection Status 15 read-write 0 No error occurred #0 1 Error occurred #1 INTENB0 Interrupt Enable Register 0 0x30 16 read-write n 0x0 0x0 BEMPE Buffer Empty Interrupt Enable 10 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BRDYE Buffer Ready Interrupt Enable 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 CTRE Control Transfer Stage Transition Interrupt Enable 11 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 DVSE Device State Transition Interrupt Enable 12 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 NRDYE Buffer Not Ready Response Interrupt Enable 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 RSME Resume Interrupt Enable 14 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 SOFE Frame Number Update Interrupt Enable 13 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 VBSE VBUS Interrupt Enable 15 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 INTENB1 Interrupt Enable Register 1 0x32 16 read-write n 0x0 0x0 ATTCHE Connection Detection Interrupt Enable 11 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 BCHGE USB Bus Change Interrupt Enable 14 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 DTCHE Disconnection Detection Interrupt Enable 12 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 EOFERRE EOF Error Detection Interrupt Enable 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 OVRCRE Overcurrent Input Change Interrupt Enable 15 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PDDETINTE PDDETINT Detection Interrupt Request Enable 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 SACKE Setup Transaction Normal Response Interrupt Enable 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 SIGNE Setup Transaction Error Interrupt Enable 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 INTSTS0 Interrupt Status Register 0 0x40 16 read-write n 0x0 0x0 BEMP Buffer Empty Interrupt Status 10 read-only 0 No BEMP interrupt occurred #0 1 BEMP interrupt occurred #1 BRDY Buffer Ready Interrupt Status 8 read-only 0 No BRDY interrupt occurred #0 1 BRDY interrupt occurred #1 CTRT Control Transfer Stage Transition Interrupt Status 11 read-write 0 No control transfer stage transition interrupt occurred #0 1 Control transfer stage transition interrupt occurred #1 CTSQ Control Transfer Stage 0 2 read-only 000 Idle or setup stage #000 001 Control read data stage #001 010 Control read status stage #010 011 Control write data stage #011 100 Control write status stage #100 101 Control write (no data) status stage #101 110 Control transfer sequence error #110 DVSQ Device State 4 2 read-only Others Suspend state 000 Powered state #000 001 Default state #001 010 Address state #010 011 Configured state #011 DVST Device State Transition Interrupt Status 12 read-write 0 No device state transition interrupt occurred #0 1 Device state transition interrupt occurred #1 NRDY Buffer Not Ready Interrupt Status 9 read-only 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 RESM Resume Interrupt Status 14 read-write 0 No resume interrupt occurred #0 1 Resume interrupt occurred #1 SOFR Frame Number Refresh Interrupt Status 13 read-write 0 No SOF interrupt occurred #0 1 SOF interrupt occurred #1 VALID USB Request Reception 3 read-write 0 Setup packet not received #0 1 Setup packet received #1 VBINT VBUS Interrupt Status 15 read-write 0 No VBUS interrupt occurred #0 1 VBUS interrupt occurred #1 VBSTS VBUS Input Status 7 read-only 0 USB_VBUS pin is low #0 1 USB_VBUS pin is high #1 INTSTS1 Interrupt Status Register 1 0x42 16 read-write n 0x0 0x0 ATTCH ATTCH Interrupt Status 11 read-write 0 No ATTCH interrupt occurred #0 1 ATTCH interrupt occurred #1 BCHG USB Bus Change Interrupt Status 14 read-write 0 No BCHG interrupt occurred #0 1 BCHG interrupt occurred #1 DTCH USB Disconnection Detection Interrupt Status 12 read-write 0 No DTCH interrupt occurred #0 1 DTCH interrupt occurred #1 EOFERR EOF Error Detection Interrupt Status 6 read-write 0 No EOFERR interrupt occurred #0 1 EOFERR interrupt occurred #1 OVRCR Overcurrent Input Change Interrupt Status 15 read-write 0 No OVRCR interrupt occurred #0 1 OVRCR interrupt occurred #1 PDDETINT PDDET Detection Interrupt Status Flag 0 read-write 0 No PDDET interrupt occurred #0 1 PDDET interrupt occurred #1 SACK Setup Transaction Normal Response Interrupt Status 4 read-write 0 No SACK interrupt occurred #0 1 SACK interrupt occurred #1 SIGN Setup Transaction Error Interrupt Status 5 read-write 0 No SIGN interrupt occurred #0 1 SIGN interrupt occurred #1 NRDYENB NRDY Interrupt Enable Register 0x38 16 read-write n 0x0 0x0 PIPE0NRDYE NRDY Interrupt Enable for Pipe 0 0 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE1NRDYE NRDY Interrupt Enable for Pipe 1 1 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE2NRDYE NRDY Interrupt Enable for Pipe 2 2 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE3NRDYE NRDY Interrupt Enable for Pipe 3 3 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE4NRDYE NRDY Interrupt Enable for Pipe 4 4 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE5NRDYE NRDY Interrupt Enable for Pipe 5 5 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE6NRDYE NRDY Interrupt Enable for Pipe 6 6 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE7NRDYE NRDY Interrupt Enable for Pipe 7 7 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE8NRDYE NRDY Interrupt Enable for Pipe 8 8 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 PIPE9NRDYE NRDY Interrupt Enable for Pipe 9 9 read-write 0 Disable interrupt request #0 1 Enable interrupt request #1 NRDYSTS NRDY Interrupt Status Register 0x48 16 read-write n 0x0 0x0 PIPE0NRDY NRDY Interrupt Status for Pipe 0 0 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE1NRDY NRDY Interrupt Status for Pipe 1 1 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE2NRDY NRDY Interrupt Status for Pipe 2 2 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE3NRDY NRDY Interrupt Status for Pipe 3 3 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE4NRDY NRDY Interrupt Status for Pipe 4 4 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE5NRDY NRDY Interrupt Status for Pipe 5 5 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE6NRDY NRDY Interrupt Status for Pipe 6 6 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE7NRDY NRDY Interrupt Status for Pipe 7 7 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE8NRDY NRDY Interrupt Status for Pipe 8 8 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE9NRDY NRDY Interrupt Status for Pipe 9 9 read-write 0 No NRDY interrupt occurred #0 1 NRDY interrupt occurred #1 PIPE1CTR PIPE%s Control Registers 0x70 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (initialize all buffers) #1 ATREPM Auto Response Mode 10 read-write 0 Disable auto response mode #0 1 Enable auto response mode #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU disabled #0 1 Buffer access by the CPU enabled #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 PIPE1TRE PIPE%s Transaction Counter Enable Register 0x90 16 read-write n 0x0 0x0 TRCLR Transaction Counter Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear counter value #1 TRENB Transaction Counter Enable 9 read-write 0 Disable transaction counter #0 1 Enable transaction counter #1 PIPE1TRN PIPE%s Transaction Counter Register 0x92 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE2CTR PIPE%s Control Registers 0x72 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (initialize all buffers) #1 ATREPM Auto Response Mode 10 read-write 0 Disable auto response mode #0 1 Enable auto response mode #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU disabled #0 1 Buffer access by the CPU enabled #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 PIPE2TRE PIPE%s Transaction Counter Enable Register 0x94 16 read-write n 0x0 0x0 TRCLR Transaction Counter Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear counter value #1 TRENB Transaction Counter Enable 9 read-write 0 Disable transaction counter #0 1 Enable transaction counter #1 PIPE2TRN PIPE%s Transaction Counter Register 0x96 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE3CTR PIPE%s Control Registers 0x74 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (initialize all buffers) #1 ATREPM Auto Response Mode 10 read-write 0 Disable auto response mode #0 1 Enable auto response mode #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU disabled #0 1 Buffer access by the CPU enabled #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 PIPE3TRE PIPE%s Transaction Counter Enable Register 0x98 16 read-write n 0x0 0x0 TRCLR Transaction Counter Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear counter value #1 TRENB Transaction Counter Enable 9 read-write 0 Disable transaction counter #0 1 Enable transaction counter #1 PIPE3TRN PIPE%s Transaction Counter Register 0x9A 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE4CTR PIPE%s Control Registers 0x76 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (initialize all buffers) #1 ATREPM Auto Response Mode 10 read-write 0 Disable auto response mode #0 1 Enable auto response mode #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU disabled #0 1 Buffer access by the CPU enabled #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 PIPE4TRE PIPE%s Transaction Counter Enable Register 0x9C 16 read-write n 0x0 0x0 TRCLR Transaction Counter Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear counter value #1 TRENB Transaction Counter Enable 9 read-write 0 Disable transaction counter #0 1 Enable transaction counter #1 PIPE4TRN PIPE%s Transaction Counter Register 0x9E 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE5CTR PIPE%s Control Registers 0x78 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (initialize all buffers) #1 ATREPM Auto Response Mode 10 read-write 0 Disable auto response mode #0 1 Enable auto response mode #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU disabled #0 1 Buffer access by the CPU enabled #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA1 #1 PIPE5TRE PIPE%s Transaction Counter Enable Register 0xA0 16 read-write n 0x0 0x0 TRCLR Transaction Counter Clear 8 read-write 0 Invalid (writing 0 has no effect) #0 1 Clear counter value #1 TRENB Transaction Counter Enable 9 read-write 0 Disable transaction counter #0 1 Enable transaction counter #1 PIPE5TRN PIPE%s Transaction Counter Register 0xA2 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE6CTR PIPE%s Control Registers 0x7A 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (all buffers initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access disabled #0 1 Buffer access enabled #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA0 #1 PIPE7CTR PIPE%s Control Registers 0x7C 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (all buffers initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access disabled #0 1 Buffer access enabled #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA0 #1 PIPE8CTR PIPE%s Control Registers 0x7E 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (all buffers initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access disabled #0 1 Buffer access enabled #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA0 #1 PIPE9CTR PIPE%s Control Registers 0x80 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disable #0 1 Enable (all buffers initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access disabled #0 1 Buffer access enabled #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depends buffer state) #01 10 STALL response #10 11 STALL response #11 SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid (writing 0 has no effect) #0 1 Clear the expected value for the next transaction to DATA0 #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid (writing 0 has no effect) #0 1 Set the expected value for the next transaction to DATA0 #1 PIPECFG Pipe Configuration Register 0x68 16 read-write n 0x0 0x0 BFRE BRDY Interrupt Operation Specification 10 read-write 0 Generate BRDY interrupt on transmitting or receiving data #0 1 Generate BRDY interrupt on completion of reading data #1 DBLB Double Buffer Mode 9 read-write 0 Single buffer #0 1 Double buffer #1 DIR Transfer Direction 4 read-write 0 Receiving direction #0 1 Transmitting direction #1 EPNUM Endpoint Number 0 3 read-write SHTNAK Pipe Disabled at End of Transfer 7 read-write 0 Continue pipe operation after transfer ends #0 1 Disable pipe after transfer ends #1 TYPE Transfer Type 14 1 read-write 00 Pipe not used #00 01 Pipes 1 and 2: Bulk transfer Pipes 3 to 5: Bulk transfer Pipes 6 to 9: Setting prohibited #01 10 Pipes 1 and 2: Setting prohibited Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Interrupt transfer #10 11 Pipes 1 and 2: Isochronous transfer Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Setting prohibited #11 PIPEMAXP Pipe Maximum Packet Size Register 0x6C 16 read-write n 0x0 0x0 DEVSEL Device Select 12 3 read-write Others Setting prohibited 0x0 Address 0000b 0x0 0x1 Address 0001b 0x1 0x2 Address 0010b 0x2 0x3 Address 0011b 0x3 0x4 Address 0100b 0x4 0x5 Address 0101b 0x5 MXPS Maximum Packet Size 0 8 read-write PIPEPERI Pipe Cycle Control Register 0x6E 16 read-write n 0x0 0x0 IFIS Isochronous IN Buffer Flush 12 read-write 0 Do not flush buffer #0 1 Flush buffer #1 IITV Interval Error Detection Interval 0 2 read-write PIPESEL Pipe Window Select Register 0x64 16 read-write n 0x0 0x0 PIPESEL Pipe Window Select 0 3 read-write Others Setting prohibited 0x0 No pipe selected 0x0 0x1 Pipe 1 0x1 0x2 Pipe 2 0x2 0x3 Pipe 3 0x3 0x4 Pipe 4 0x4 0x5 Pipe 5 0x5 0x6 Pipe 6 0x6 0x7 Pipe 7 0x7 0x8 Pipe 8 0x8 0x9 Pipe 9 0x9 SOFCFG SOF Output Configuration Register 0x3C 16 read-write n 0x0 0x0 BRDYM BRDY Interrupt Status Clear Timing 6 read-write 0 Clear BRDY flag by software #0 1 Clear BRDY flag by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer #1 EDGESTS Edge Interrupt Output Status Monitor 4 read-only TRNENSEL Transaction-Enabled Time Select 8 read-write 0 Not low-speed communication #0 1 Low-speed communication #1 SYSCFG System Configuration Control Register 0x0 16 read-write n 0x0 0x0 DCFM Controller Function Select 6 read-write 0 Select device controller #0 1 Select host controller #1 DPRPU D+ Line Resistor Control 4 read-write 0 Disable line pull-up #0 1 Enable line pull-up #1 DRPD D+/D– Line Resistor Control 5 read-write 0 Disable line pull-down #0 1 Enable line pull-down #1 SCKE USB Clock Enable 10 read-write 0 Stop clock supply to the USBFS #0 1 Enable clock supply to the USBFS #1 USBE USBFS Operation Enable 0 read-write 0 Disable #0 1 Enable #1 SYSSTS0 System Configuration Status Register 0 0x4 16 read-only n 0x0 0x0 HTACT USB Host Sequencer Status Monitor 6 read-only 0 Host sequencer completely stopped #0 1 Host sequencer not completely stopped #1 IDMON External ID0 Input Pin Monitor 2 read-only 0 USB_ID pin is low #0 1 USB_ID pin is high #1 LNST USB Data Line Status Monitor 0 1 read-only OVCMON External USB_OVRCURA/ USB_OVRCURB Input Pin Monitor 14 1 read-only SOFEA Active Monitor When the Host Controller Is Selected 5 read-only 0 SOF output stopped #0 1 SOF output operating #1 USBADDR USB Address Register 0x50 16 read-write n 0x0 0x0 STSRECOV Status Recovery 8 3 read-write Others Setting prohibited 0x4 Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the low-speed state (bits DVSTCTR0.RHST[2:0] = 001b) 0x4 0x8 Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b) 0x8 0x9 Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (default state) Recovery in host controller mode: Setting prohibited 0x9 0xA Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (address state) Recovery in host controller mode: Setting prohibited 0xa 0xB Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (configured state) Recovery in host controller mode: Setting prohibited 0xb USBADDR USB Address 0 6 read-write USBINDX USB Request Index Register 0x58 16 read-write n 0x0 0x0 WINDEX Index 0 15 read-write USBLENG USB Request Length Register 0x5A 16 read-write n 0x0 0x0 WLENTUH Length 0 15 read-write USBREQ USB Request Type Register 0x54 16 read-write n 0x0 0x0 BMREQUESTTYPE Request Type 0 7 read-write BREQUEST Request 8 7 read-write USBVAL USB Request Value Register 0x56 16 read-write n 0x0 0x0 WVALUE Value 0 15 read-write WDT Watchdog Timer WDT 0x0 0x0 0x1 registers n 0x2 0x5 registers n 0x8 0x1 registers n WDTCR WDT Control Register 0x2 16 read-write n 0x0 0x0 CKS Clock Division Ratio Select 4 3 read-write Others Setting prohibited 0x1 PCLKL/4 0x1 0x4 PCLKL/64 0x4 0x6 PCLKL/512 0x6 0x7 PCLKL/2048 0x7 0x8 PCLKL/8192 0x8 0xF PCLKL/128 0xf RPES Window End Position Select 8 1 read-write 00 75% #00 01 50% #01 10 25% #10 11 0% (do not specify window end position). #11 RPSS Window Start Position Select 12 1 read-write 00 25% #00 01 50% #01 10 75% #10 11 100% (do not specify window start position). #11 TOPS Timeout Period Select 0 1 read-write 00 1024 cycles (0x03FF) #00 01 4096 cycles (0x0FFF) #01 10 8192 cycles (0x1FFF) #10 11 16384 cycles (0x3FFF) #11 WDTCSTPR WDT Count Stop Control Register 0x8 8 read-write n 0x0 0x0 SLCSTP WDT Count Stop Control Register 7 read-write 0 Disable count stop #0 1 Stop count on transition to Sleep mode #1 WDTRCR WDT Reset Control Register 0x6 8 read-write n 0x0 0x0 RSTIRQS Reset Interrupt Request Select 7 read-write 0 Enable non-maskable interrupt request or interrupt request output #0 1 Enable reset output #1 WDTRR WDT Refresh Register 0x0 8 read-write n 0x0 0x0 WDTSR WDT Status Register 0x4 16 read-write n 0x0 0x0 CNTVAL Counter Value 0 13 read-only REFEF Refresh Error Flag 15 read-write 0 No refresh error occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 read-write 0 No underflow occurred #0 1 Underflow occurred #1