Renesas
RIN32M4_CL2
2024.04.29
ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 100MHz, etc.
CM4
r0p1
little
true
true
4
false
8
32
ADC
A/D Converter
ADC
0x0
0x0
0x2C
registers
n
ADC
AD completion interrupt
127
ADCR0
A/D Converter Result Register n
0x30
32
read-only
n
0x0
0x0
ADCR1
A/D Converter Result Register n
0x34
32
read-only
n
0x0
0x0
ADCR2
A/D Converter Result Register n
0x38
32
read-only
n
0x0
0x0
ADCR3
A/D Converter Result Register n
0x3C
32
read-only
n
0x0
0x0
ADCR4
A/D Converter Result Register n
0x40
32
read-only
n
0x0
0x0
ADCR5
A/D Converter Result Register n
0x44
32
read-only
n
0x0
0x0
ADCR6
A/D Converter Result Register n
0x48
32
read-only
n
0x0
0x0
ADCR7
A/D Converter Result Register n
0x4C
32
read-only
n
0x0
0x0
ADINT
A/D Converter Interrupt Control Register
0x20
32
read-write
n
0x0
0x0
ADIVC
A/D Converter Clock Division Setting Register
0x28
32
read-write
n
0x0
0x0
ADM0
A/D Converter Mode Register n
0x0
32
read-write
n
0x0
0x0
ADM1
A/D Converter Mode Register n
0x4
32
read-write
n
0x0
0x0
ADM2
A/D Converter Mode Register n
0x8
32
read-write
n
0x0
0x0
ADM3
A/D Converter Mode Register n
0xC
32
read-write
n
0x0
0x0
ADSTS
A/D Converter Status Register
0x24
32
read-write
n
0x0
0x0
CAN0
CAN
CAN
0x0
0x0
0x20000
registers
n
FCN0REC
FCN0 reception completion interrupt
16
FCN0TRX
FCN0 transmission completion interrupt
17
FCN0WUP
FCN0 sleep and wakeup/transmission suspension interrupt
18
FCN0ERR
FCN0 error detection interrupt
86
FCNnCMBRPRS
module bit-rate prescaler and clock selector register
0x268
8
read-write
n
0x0
0x0
FCNnCMBTCTL
module bit-rate register
0x8270
16
read-write
n
0x0
0x0
FCNnCMCLCTL
module control register
0x8240
16
read-write
n
0x0
0x0
FCNnCMERCNT
module error counter register
0x8250
16
read-only
n
0x0
0x0
FCNnCMIECTL
module interrupt enable register
0x8258
16
read-write
n
0x0
0x0
FCNnCMINSTR
module information register
0x24C
8
read-only
n
0x0
0x0
FCNnCMISCTL
module interrupt status register
0x8260
16
read-write
n
0x0
0x0
FCNnCMLCSTR
module last error information register
0x248
8
read-write
n
0x0
0x0
FCNnCMLISTR
module last receive pointer register
0x278
8
read-only
n
0x0
0x0
FCNnCMLOSTR
module last transmit pointer register
0x288
8
read-only
n
0x0
0x0
FCNnCMMKCTL01H
module mask 1 register [15 to 0]
0x8300
16
read-write
n
0x0
0x0
FCNnCMMKCTL01W
module mask 1 register [28 to 0]
0x10300
32
read-write
n
0x0
0x0
FCNnCMMKCTL02H
module mask 1 register [28 to 16]
0x8308
16
read-write
n
0x0
0x0
FCNnCMMKCTL03H
module mask 2 register [15 to 0]
0x8310
16
read-write
n
0x0
0x0
FCNnCMMKCTL03W
module mask 2 register [28 to 0]
0x10310
32
read-write
n
0x0
0x0
FCNnCMMKCTL04H
module mask 2 register [28 to 16]
0x8318
16
read-write
n
0x0
0x0
FCNnCMMKCTL05H
module mask 3 register [15 to 0]
0x8320
16
read-write
n
0x0
0x0
FCNnCMMKCTL05W
module mask 3 register [28 to 0]
0x10320
32
read-write
n
0x0
0x0
FCNnCMMKCTL06H
module mask 3 register [28 to 16]
0x8328
16
read-write
n
0x0
0x0
FCNnCMMKCTL07H
module mask 4 register [15 to 0]
0x8330
16
read-write
n
0x0
0x0
FCNnCMMKCTL07W
module mask 4 register [28 to 0]
0x10330
32
read-write
n
0x0
0x0
FCNnCMMKCTL08H
module mask 4 register [28 to 16]
0x8338
16
read-write
n
0x0
0x0
FCNnCMMKCTL09H
module mask 5 register [15 to 0]
0x8340
16
read-write
n
0x0
0x0
FCNnCMMKCTL09W
module mask 5 register [28 to 0]
0x10340
32
read-write
n
0x0
0x0
FCNnCMMKCTL10H
module mask 5 register [28 to 16]
0x8348
16
read-write
n
0x0
0x0
FCNnCMMKCTL11H
module mask 6 register [15 to 0]
0x8350
16
read-write
n
0x0
0x0
FCNnCMMKCTL11W
module mask 6 register [28 to 0]
0x10350
32
read-write
n
0x0
0x0
FCNnCMMKCTL12H
module mask 6 register [28 to 16]
0x8358
16
read-write
n
0x0
0x0
FCNnCMMKCTL13H
module mask 7 register [15 to 0]
0x8360
16
read-write
n
0x0
0x0
FCNnCMMKCTL13W
module mask 7 register [28 to 0]
0x10360
32
read-write
n
0x0
0x0
FCNnCMMKCTL14H
module mask 7 register [28 to 16]
0x8368
16
read-write
n
0x0
0x0
FCNnCMMKCTL15H
module mask 8 register [15 to 0]
0x8370
16
read-write
n
0x0
0x0
FCNnCMMKCTL15W
module mask 8 register [28 to 0]
0x10370
32
read-write
n
0x0
0x0
FCNnCMMKCTL16H
module mask 8 register [28 to 16]
0x8378
16
read-write
n
0x0
0x0
FCNnCMRGRX
module receive history list register
0x8280
16
read-write
n
0x0
0x0
FCNnCMTGTX
module transmit history list register
0x8290
16
read-write
n
0x0
0x0
FCNnCMTSCTL
module time stamp register
0x8298
16
read-write
n
0x0
0x0
FCNnDNBMRX0
global data update bit monitor register 0
0x100C0
32
read-only
n
0x0
0x0
FCNnDNBMRX1
global data update bit monitor register 1
0x100D0
32
read-only
n
0x0
0x0
FCNnGMABCTL
global automatic block transmission control register
0x8018
16
read-write
n
0x0
0x0
FCNnGMADCTL
global automatic block transmission delay setting register
0x20
8
read-write
n
0x0
0x0
FCNnGMCLCTL
global control register
0x8000
16
read-write
n
0x0
0x0
FCNnGMCSPRE
global clock selection register
0x8
8
read-write
n
0x0
0x0
FCNnMmCTL
Message control register
0x9038
16
read-write
n
0x0
0x0
FCNnMmDAT0B
Message buffer register a (Byte data)
0x1000
8
read-write
n
0x0
0x0
FCNnMmDAT0H
Message buffer register a (Half word data)
0x9000
16
read-write
n
0x0
0x0
FCNnMmDAT0W
Message buffer register a (Word data)
0x11000
32
read-write
n
0x0
0x0
FCNnMmDAT1B
Message buffer register a (Byte data)
0x1004
8
read-write
n
0x0
0x0
FCNnMmDAT2B
Message buffer register a (Byte data)
0x1008
8
read-write
n
0x0
0x0
FCNnMmDAT2H
Message buffer register a (Half word data)
0x9008
16
read-write
n
0x0
0x0
FCNnMmDAT3B
Message buffer register a (Byte data)
0x100C
8
read-write
n
0x0
0x0
FCNnMmDAT4B
Message buffer register a (Byte data)
0x1010
8
read-write
n
0x0
0x0
FCNnMmDAT4H
Message buffer register a (Half word data)
0x9010
16
read-write
n
0x0
0x0
FCNnMmDAT4W
Message buffer register a (Word data)
0x11010
32
read-write
n
0x0
0x0
FCNnMmDAT5B
Message buffer register a (Byte data)
0x1014
8
read-write
n
0x0
0x0
FCNnMmDAT6B
Message buffer register a (Byte data)
0x1018
8
read-write
n
0x0
0x0
FCNnMmDAT6H
Message buffer register a (Half word data)
0x9018
16
read-write
n
0x0
0x0
FCNnMmDAT7B
Message buffer register a (Byte data)
0x101C
8
read-write
n
0x0
0x0
FCNnMmDTLGB
Message data length register
0x1020
8
read-write
n
0x0
0x0
FCNnMmMID0H
Message ID register a (Half word data)
0x9028
16
read-write
n
0x0
0x0
FCNnMmMID0W
Message ID register 0 (Word data)
0x11028
32
read-write
n
0x0
0x0
FCNnMmMID1H
Message ID register a (Half word data)
0x9030
16
read-write
n
0x0
0x0
FCNnMmSTRB
Message configuration register
0x1024
8
read-write
n
0x0
0x0
CAN1
CAN
CAN
0x0
0x0
0x20000
registers
n
FCN1REC
FCN1 reception completion interrupt
19
FCN1TRX
FCN1 transmission completion interrupt
20
FCN1WUP
FCN1 sleep and wakeup/transmission suspension interrupt
21
FCN1ERR
FCN1 error detection interrupt
87
FCNnCMBRPRS
module bit-rate prescaler and clock selector register
0x268
8
read-write
n
0x0
0x0
FCNnCMBTCTL
module bit-rate register
0x8270
16
read-write
n
0x0
0x0
FCNnCMCLCTL
module control register
0x8240
16
read-write
n
0x0
0x0
FCNnCMERCNT
module error counter register
0x8250
16
read-only
n
0x0
0x0
FCNnCMIECTL
module interrupt enable register
0x8258
16
read-write
n
0x0
0x0
FCNnCMINSTR
module information register
0x24C
8
read-only
n
0x0
0x0
FCNnCMISCTL
module interrupt status register
0x8260
16
read-write
n
0x0
0x0
FCNnCMLCSTR
module last error information register
0x248
8
read-write
n
0x0
0x0
FCNnCMLISTR
module last receive pointer register
0x278
8
read-only
n
0x0
0x0
FCNnCMLOSTR
module last transmit pointer register
0x288
8
read-only
n
0x0
0x0
FCNnCMMKCTL01H
module mask 1 register [15 to 0]
0x8300
16
read-write
n
0x0
0x0
FCNnCMMKCTL01W
module mask 1 register [28 to 0]
0x10300
32
read-write
n
0x0
0x0
FCNnCMMKCTL02H
module mask 1 register [28 to 16]
0x8308
16
read-write
n
0x0
0x0
FCNnCMMKCTL03H
module mask 2 register [15 to 0]
0x8310
16
read-write
n
0x0
0x0
FCNnCMMKCTL03W
module mask 2 register [28 to 0]
0x10310
32
read-write
n
0x0
0x0
FCNnCMMKCTL04H
module mask 2 register [28 to 16]
0x8318
16
read-write
n
0x0
0x0
FCNnCMMKCTL05H
module mask 3 register [15 to 0]
0x8320
16
read-write
n
0x0
0x0
FCNnCMMKCTL05W
module mask 3 register [28 to 0]
0x10320
32
read-write
n
0x0
0x0
FCNnCMMKCTL06H
module mask 3 register [28 to 16]
0x8328
16
read-write
n
0x0
0x0
FCNnCMMKCTL07H
module mask 4 register [15 to 0]
0x8330
16
read-write
n
0x0
0x0
FCNnCMMKCTL07W
module mask 4 register [28 to 0]
0x10330
32
read-write
n
0x0
0x0
FCNnCMMKCTL08H
module mask 4 register [28 to 16]
0x8338
16
read-write
n
0x0
0x0
FCNnCMMKCTL09H
module mask 5 register [15 to 0]
0x8340
16
read-write
n
0x0
0x0
FCNnCMMKCTL09W
module mask 5 register [28 to 0]
0x10340
32
read-write
n
0x0
0x0
FCNnCMMKCTL10H
module mask 5 register [28 to 16]
0x8348
16
read-write
n
0x0
0x0
FCNnCMMKCTL11H
module mask 6 register [15 to 0]
0x8350
16
read-write
n
0x0
0x0
FCNnCMMKCTL11W
module mask 6 register [28 to 0]
0x10350
32
read-write
n
0x0
0x0
FCNnCMMKCTL12H
module mask 6 register [28 to 16]
0x8358
16
read-write
n
0x0
0x0
FCNnCMMKCTL13H
module mask 7 register [15 to 0]
0x8360
16
read-write
n
0x0
0x0
FCNnCMMKCTL13W
module mask 7 register [28 to 0]
0x10360
32
read-write
n
0x0
0x0
FCNnCMMKCTL14H
module mask 7 register [28 to 16]
0x8368
16
read-write
n
0x0
0x0
FCNnCMMKCTL15H
module mask 8 register [15 to 0]
0x8370
16
read-write
n
0x0
0x0
FCNnCMMKCTL15W
module mask 8 register [28 to 0]
0x10370
32
read-write
n
0x0
0x0
FCNnCMMKCTL16H
module mask 8 register [28 to 16]
0x8378
16
read-write
n
0x0
0x0
FCNnCMRGRX
module receive history list register
0x8280
16
read-write
n
0x0
0x0
FCNnCMTGTX
module transmit history list register
0x8290
16
read-write
n
0x0
0x0
FCNnCMTSCTL
module time stamp register
0x8298
16
read-write
n
0x0
0x0
FCNnDNBMRX0
global data update bit monitor register 0
0x100C0
32
read-only
n
0x0
0x0
FCNnDNBMRX1
global data update bit monitor register 1
0x100D0
32
read-only
n
0x0
0x0
FCNnGMABCTL
global automatic block transmission control register
0x8018
16
read-write
n
0x0
0x0
FCNnGMADCTL
global automatic block transmission delay setting register
0x20
8
read-write
n
0x0
0x0
FCNnGMCLCTL
global control register
0x8000
16
read-write
n
0x0
0x0
FCNnGMCSPRE
global clock selection register
0x8
8
read-write
n
0x0
0x0
FCNnMmCTL
Message control register
0x9038
16
read-write
n
0x0
0x0
FCNnMmDAT0B
Message buffer register a (Byte data)
0x1000
8
read-write
n
0x0
0x0
FCNnMmDAT0H
Message buffer register a (Half word data)
0x9000
16
read-write
n
0x0
0x0
FCNnMmDAT0W
Message buffer register a (Word data)
0x11000
32
read-write
n
0x0
0x0
FCNnMmDAT1B
Message buffer register a (Byte data)
0x1004
8
read-write
n
0x0
0x0
FCNnMmDAT2B
Message buffer register a (Byte data)
0x1008
8
read-write
n
0x0
0x0
FCNnMmDAT2H
Message buffer register a (Half word data)
0x9008
16
read-write
n
0x0
0x0
FCNnMmDAT3B
Message buffer register a (Byte data)
0x100C
8
read-write
n
0x0
0x0
FCNnMmDAT4B
Message buffer register a (Byte data)
0x1010
8
read-write
n
0x0
0x0
FCNnMmDAT4H
Message buffer register a (Half word data)
0x9010
16
read-write
n
0x0
0x0
FCNnMmDAT4W
Message buffer register a (Word data)
0x11010
32
read-write
n
0x0
0x0
FCNnMmDAT5B
Message buffer register a (Byte data)
0x1014
8
read-write
n
0x0
0x0
FCNnMmDAT6B
Message buffer register a (Byte data)
0x1018
8
read-write
n
0x0
0x0
FCNnMmDAT6H
Message buffer register a (Half word data)
0x9018
16
read-write
n
0x0
0x0
FCNnMmDAT7B
Message buffer register a (Byte data)
0x101C
8
read-write
n
0x0
0x0
FCNnMmDTLGB
Message data length register
0x1020
8
read-write
n
0x0
0x0
FCNnMmMID0H
Message ID register a (Half word data)
0x9028
16
read-write
n
0x0
0x0
FCNnMmMID0W
Message ID register 0 (Word data)
0x11028
32
read-write
n
0x0
0x0
FCNnMmMID1H
Message ID register a (Half word data)
0x9030
16
read-write
n
0x0
0x0
FCNnMmSTRB
Message configuration register
0x1024
8
read-write
n
0x0
0x0
CC_Link
CC-Link
CC_Link
0x0
0x0
0x50
registers
n
CCSIRZ
CC-Link IRZ interrupt
116
CCSREFSTB
CC-Link REFSTB interrupt
117
CCSMON3
CC-Link MON3 interrupt
118
CC_Link_BR
CC-Link BUS Control
CC_Link_BR
0x0
0x0
0x400
registers
n
CCBSC
Bus Size Control register
0x4
32
read-write
n
0x0
0x0
CCSMC0
CC-Link BUS Control register 0
0x8
32
read-write
n
0x0
0x0
CCSMC1
CC-Link BUS Control register 1
0xC
32
read-write
n
0x0
0x0
CC_Link_IEF_BR
CC-Link IE Field BUS Control
CC_Link_IEF_BR
0x0
0x0
0x400
registers
n
CIEBSC
CC-Link IE Bus Size Control register
0x4
32
read-write
n
0x0
0x0
CIESMC
CC-Link IE BUS Bridge Control register
0x8
32
read-write
n
0x0
0x0
CC_Link_RMT
CC-Link Remote Device Station
CC_Link_RMT
0x0
0x0
0x400
registers
n
CCS_M3ERR1_ERR2
Error information register
0x4
16
read-only
n
0x0
0x0
CCS_M3HOLDCLR
HOLD/CLR Information Setting register
0xBA
16
read-write
n
0x0
0x0
CCS_M3MODELCODE_VERSION
Model code and version register
0x84
16
read-write
n
0x0
0x0
CCS_M3MRRWW0
M-R RWw0 register
0x1A
16
read-only
n
0x0
0x0
CCS_M3MRRWW1
M-R RWw1 register
0x1C
16
read-only
n
0x0
0x0
CCS_M3MRRWW10
M-R RWw10 register
0x2E
16
read-only
n
0x0
0x0
CCS_M3MRRWW11
M-R RWw11 register
0x30
16
read-only
n
0x0
0x0
CCS_M3MRRWW12
M-R RWw12 register
0x32
16
read-only
n
0x0
0x0
CCS_M3MRRWW13
M-R RWw13 register
0x34
16
read-only
n
0x0
0x0
CCS_M3MRRWW14
M-R RWw14 register
0x36
16
read-only
n
0x0
0x0
CCS_M3MRRWW15
M-R RWw15 register
0x38
16
read-only
n
0x0
0x0
CCS_M3MRRWW2
M-R RWw2 register
0x1E
16
read-only
n
0x0
0x0
CCS_M3MRRWW3
M-R RWw3 register
0x20
16
read-only
n
0x0
0x0
CCS_M3MRRWW4
M-R RWw4 register
0x22
16
read-only
n
0x0
0x0
CCS_M3MRRWW5
M-R RWw5 register
0x24
16
read-only
n
0x0
0x0
CCS_M3MRRWW6
M-R RWw6 register
0x26
16
read-only
n
0x0
0x0
CCS_M3MRRWW7
M-R RWw7 register
0x28
16
read-only
n
0x0
0x0
CCS_M3MRRWW8
M-R RWw8 register
0x2A
16
read-only
n
0x0
0x0
CCS_M3MRRWW9
M-R RWw9 register
0x2C
16
read-only
n
0x0
0x0
CCS_M3MRRY00_0F
M-R RY00-0F register
0xA
16
read-only
n
0x0
0x0
CCS_M3MRRY10_1F
M-R RY10-1F register
0xC
16
read-only
n
0x0
0x0
CCS_M3MRRY20_2F
M-R RY20-2F register
0xE
16
read-only
n
0x0
0x0
CCS_M3MRRY30_3F
M-R RY30-3F register
0x10
16
read-only
n
0x0
0x0
CCS_M3MRRY40_4F
M-R RY40-4F register
0x12
16
read-only
n
0x0
0x0
CCS_M3MRRY50_5F
M-R RY50-5F register
0x14
16
read-only
n
0x0
0x0
CCS_M3MRRY60_6F
M-R RY60-6F register
0x16
16
read-only
n
0x0
0x0
CCS_M3MRRY70_7F
M-R RY70-7F register
0x18
16
read-only
n
0x0
0x0
CCS_M3MRST1_ST2
M-R status information register
0x8
16
read-only
n
0x0
0x0
CCS_M3RMRWR0
M-R RWr0 register
0x9A
16
read-write
n
0x0
0x0
CCS_M3RMRWR1
M-R RWr1 register
0x9C
16
read-write
n
0x0
0x0
CCS_M3RMRWR10
M-R RWr10 register
0xAE
16
read-write
n
0x0
0x0
CCS_M3RMRWR11
M-R RWr11 register
0xB0
16
read-write
n
0x0
0x0
CCS_M3RMRWR12
M-R RWr12 register
0xB2
16
read-write
n
0x0
0x0
CCS_M3RMRWR13
M-R RWr13 register
0xB4
16
read-write
n
0x0
0x0
CCS_M3RMRWR14
M-R RWr14 register
0xB6
16
read-write
n
0x0
0x0
CCS_M3RMRWR15
M-R RWr15 register
0xB8
16
read-write
n
0x0
0x0
CCS_M3RMRWR2
M-R RWr2 register
0x9E
16
read-write
n
0x0
0x0
CCS_M3RMRWR3
M-R RWr3 register
0xA0
16
read-write
n
0x0
0x0
CCS_M3RMRWR4
M-R RWr4 register
0xA2
16
read-write
n
0x0
0x0
CCS_M3RMRWR5
M-R RWr5 register
0xA4
16
read-write
n
0x0
0x0
CCS_M3RMRWR6
M-R RWr6 register
0xA6
16
read-write
n
0x0
0x0
CCS_M3RMRWR7
M-R RWr7 register
0xA8
16
read-write
n
0x0
0x0
CCS_M3RMRWR8
M-R RWr8 register
0xAA
16
read-write
n
0x0
0x0
CCS_M3RMRWR9
M-R RWr9 register
0xAC
16
read-write
n
0x0
0x0
CCS_M3RMRX00_0F
R-M RX00-0F register
0x8A
16
read-write
n
0x0
0x0
CCS_M3RMRX10_1F
R-M RX10-1F register
0x8C
16
read-write
n
0x0
0x0
CCS_M3RMRX20_2F
R-M RX20-2F register
0x8E
16
read-write
n
0x0
0x0
CCS_M3RMRX30_3F
R-M RX30-3F register
0x90
16
read-write
n
0x0
0x0
CCS_M3RMRX40_4F
R-M RX40-4F register
0x92
16
read-write
n
0x0
0x0
CCS_M3RMRX50_5F
R-M RX50-5F register
0x94
16
read-write
n
0x0
0x0
CCS_M3RMRX60_6F
R-M RX60-6F register
0x96
16
read-write
n
0x0
0x0
CCS_M3RMRX70_7F
R-M RX70-7F register
0x98
16
read-write
n
0x0
0x0
CCS_M3RMST1_ST2
Cyclic Communication register
0x88
16
read-write
n
0x0
0x0
CCS_M3SDLED_TOVER
SDLED illumination time setting and Timeout time setting register
0x86
16
read-write
n
0x0
0x0
CCS_M3SDOK_RDRQ
Send data write complete flag and Receive data read request register
0x80
16
read-write
n
0x0
0x0
CCS_M3STNO_BSW_KYOKU
Station number and Baud rate switch information register
0x2
16
read-only
n
0x0
0x0
CCS_M3VENDORCODE
Vendor code register
0x82
16
read-write
n
0x0
0x0
CCS_MWRENL_RCEX
Send data write enable information register
0x0
16
read-only
n
0x0
0x0
CSI0
CSI
CSI
0x0
0x0
0x100
registers
n
CSIH0IC
CSIH0 communication status interrupt
8
CSIH0IR
CSIH0 reception status interrupt
9
CSIH0IJC
CSIH0 job completion interrupt
10
CSIH0IRE
CSIH0 communication error interrupt
84
CSIHnCFG0
Configuration register 0
0xC4
32
read-write
n
0x0
0x0
CSIHnCFG1
Configuration register 1
0xC8
32
read-write
n
0x0
0x0
CSIHnCTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
CSIHnCTL1
Control register 1
0x10
32
read-write
n
0x0
0x0
CSIHnCTL2
Control register 2
0x14
32
read-write
n
0x0
0x0
CSIHnMCTL0
Memory control register 0
0xC0
32
read-write
n
0x0
0x0
CSIHnMCTL1
Memory control register 1
0x80
32
read-write
n
0x0
0x0
CSIHnMCTL2
Memory control register 2
0x84
32
read-write
n
0x0
0x0
CSIHnMRWP0
Memory read/write pointerregister 0
0x98
32
read-write
n
0x0
0x0
CSIHnRX0H
Receive data register 0 for half word access
0x94
32
read-only
n
0x0
0x0
CSIHnRX0W
Receive data register 0 for word access
0x90
32
read-only
n
0x0
0x0
CSIHnSTCR0
Status clear register 0
0x8
32
write-only
n
0x0
0x0
CSIHnSTR0
Status register 0
0x4
32
read-only
n
0x0
0x0
CSIHnTX0H
Transmit data register 0 for half word access
0x8C
32
read-write
n
0x0
0x0
CSIHnTX0W
Transmit data register 0 for word access
0x88
32
read-write
n
0x0
0x0
CSI1
CSI
CSI
0x0
0x0
0x100
registers
n
CSIH1IC
CSIH1 communication status interrupt
11
CSIH1IR
CSIH1 reception status interrupt
12
CSIH1IJC
CSIH1 job completion interrupt
13
CSIH1IRE
CSIH1 communication error interrupt
85
CSIHnCFG0
Configuration register 0
0xC4
32
read-write
n
0x0
0x0
CSIHnCFG1
Configuration register 1
0xC8
32
read-write
n
0x0
0x0
CSIHnCTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
CSIHnCTL1
Control register 1
0x10
32
read-write
n
0x0
0x0
CSIHnCTL2
Control register 2
0x14
32
read-write
n
0x0
0x0
CSIHnMCTL0
Memory control register 0
0xC0
32
read-write
n
0x0
0x0
CSIHnMCTL1
Memory control register 1
0x80
32
read-write
n
0x0
0x0
CSIHnMCTL2
Memory control register 2
0x84
32
read-write
n
0x0
0x0
CSIHnMRWP0
Memory read/write pointerregister 0
0x98
32
read-write
n
0x0
0x0
CSIHnRX0H
Receive data register 0 for half word access
0x94
32
read-only
n
0x0
0x0
CSIHnRX0W
Receive data register 0 for word access
0x90
32
read-only
n
0x0
0x0
CSIHnSTCR0
Status clear register 0
0x8
32
write-only
n
0x0
0x0
CSIHnSTR0
Status register 0
0x4
32
read-only
n
0x0
0x0
CSIHnTX0H
Transmit data register 0 for half word access
0x8C
32
read-write
n
0x0
0x0
CSIHnTX0W
Transmit data register 0 for word access
0x88
32
read-write
n
0x0
0x0
DCTL
DMA control
DMACCTL
0x0
0x0
0x24
registers
n
DCTRL
DMAC control register
0x0
32
read-write
n
0x0
0x0
DSCITVL
DMAC descriptor interval register
0x4
32
read-write
n
0x0
0x0
DSTEN
DMAC enable status register
0x10
32
read-only
n
0x0
0x0
DSTEND
DMAC end status register
0x18
32
read-only
n
0x0
0x0
DSTER
DMAC error status register
0x14
32
read-only
n
0x0
0x0
DSTSUS
DMAC suspend status register
0x20
32
read-only
n
0x0
0x0
DSTTC
DMAC terminal count status register
0x1C
32
read-only
n
0x0
0x0
DMAC0
DMA controller
DMAC
0x0
0x0
0x40
registers
n
DMA00
General DMAC channel 0 transfer completion interrupt
22
DERR0
General DMAC error response interrupt
88
CHCFGn
Channel configulation register
0x2C
32
read-write
n
0x0
0x0
CHCTRLn
Channel control register
0x28
32
write-only
n
0x0
0x0
CHITVLn
Channel intereval register
0x30
32
read-write
n
0x0
0x0
CHSTATn
Channel status register
0x24
32
read-only
n
0x0
0x0
CRDAn
Destination address register [Current]
0x1C
32
read-only
n
0x0
0x0
CRLAn
Link address register [Current]
0x3C
32
read-only
n
0x0
0x0
CRSAn
Source address register [Current]
0x18
32
read-only
n
0x0
0x0
CRTBn
Transaction byte register [Current]
0x20
32
read-only
n
0x0
0x0
N0DAn
Destination address register [Next0]
0x4
32
read-write
n
0x0
0x0
N0SAn
Source address register [Next0]
0x0
32
read-write
n
0x0
0x0
N0TBn
Transaction byte register [Next0]
0x8
32
read-write
n
0x0
0x0
N1DAn
Destination address register [Next1]
0x10
32
read-write
n
0x0
0x0
N1SAn
Source address register [Next1]
0xC
32
read-write
n
0x0
0x0
N1TBn
Transaction byte register [Next1]
0x14
32
read-write
n
0x0
0x0
NXLAn
Link address register [Next]
0x38
32
read-write
n
0x0
0x0
DMAC1
DMA controller
DMAC
0x0
0x0
0x40
registers
n
DMA01
General DMAC channel 1 transfer completion interrupt
23
CHCFGn
Channel configulation register
0x2C
32
read-write
n
0x0
0x0
CHCTRLn
Channel control register
0x28
32
write-only
n
0x0
0x0
CHITVLn
Channel intereval register
0x30
32
read-write
n
0x0
0x0
CHSTATn
Channel status register
0x24
32
read-only
n
0x0
0x0
CRDAn
Destination address register [Current]
0x1C
32
read-only
n
0x0
0x0
CRLAn
Link address register [Current]
0x3C
32
read-only
n
0x0
0x0
CRSAn
Source address register [Current]
0x18
32
read-only
n
0x0
0x0
CRTBn
Transaction byte register [Current]
0x20
32
read-only
n
0x0
0x0
N0DAn
Destination address register [Next0]
0x4
32
read-write
n
0x0
0x0
N0SAn
Source address register [Next0]
0x0
32
read-write
n
0x0
0x0
N0TBn
Transaction byte register [Next0]
0x8
32
read-write
n
0x0
0x0
N1DAn
Destination address register [Next1]
0x10
32
read-write
n
0x0
0x0
N1SAn
Source address register [Next1]
0xC
32
read-write
n
0x0
0x0
N1TBn
Transaction byte register [Next1]
0x14
32
read-write
n
0x0
0x0
NXLAn
Link address register [Next]
0x38
32
read-write
n
0x0
0x0
DMAC2
DMA controller
DMAC
0x0
0x0
0x40
registers
n
DMA02
General DMAC channel 2 transfer completion interrupt
24
CHCFGn
Channel configulation register
0x2C
32
read-write
n
0x0
0x0
CHCTRLn
Channel control register
0x28
32
write-only
n
0x0
0x0
CHITVLn
Channel intereval register
0x30
32
read-write
n
0x0
0x0
CHSTATn
Channel status register
0x24
32
read-only
n
0x0
0x0
CRDAn
Destination address register [Current]
0x1C
32
read-only
n
0x0
0x0
CRLAn
Link address register [Current]
0x3C
32
read-only
n
0x0
0x0
CRSAn
Source address register [Current]
0x18
32
read-only
n
0x0
0x0
CRTBn
Transaction byte register [Current]
0x20
32
read-only
n
0x0
0x0
N0DAn
Destination address register [Next0]
0x4
32
read-write
n
0x0
0x0
N0SAn
Source address register [Next0]
0x0
32
read-write
n
0x0
0x0
N0TBn
Transaction byte register [Next0]
0x8
32
read-write
n
0x0
0x0
N1DAn
Destination address register [Next1]
0x10
32
read-write
n
0x0
0x0
N1SAn
Source address register [Next1]
0xC
32
read-write
n
0x0
0x0
N1TBn
Transaction byte register [Next1]
0x14
32
read-write
n
0x0
0x0
NXLAn
Link address register [Next]
0x38
32
read-write
n
0x0
0x0
DMAC3
DMA controller
DMAC
0x0
0x0
0x40
registers
n
DMA03
General DMAC channel 3 transfer completion interrupt
25
CHCFGn
Channel configulation register
0x2C
32
read-write
n
0x0
0x0
CHCTRLn
Channel control register
0x28
32
write-only
n
0x0
0x0
CHITVLn
Channel intereval register
0x30
32
read-write
n
0x0
0x0
CHSTATn
Channel status register
0x24
32
read-only
n
0x0
0x0
CRDAn
Destination address register [Current]
0x1C
32
read-only
n
0x0
0x0
CRLAn
Link address register [Current]
0x3C
32
read-only
n
0x0
0x0
CRSAn
Source address register [Current]
0x18
32
read-only
n
0x0
0x0
CRTBn
Transaction byte register [Current]
0x20
32
read-only
n
0x0
0x0
N0DAn
Destination address register [Next0]
0x4
32
read-write
n
0x0
0x0
N0SAn
Source address register [Next0]
0x0
32
read-write
n
0x0
0x0
N0TBn
Transaction byte register [Next0]
0x8
32
read-write
n
0x0
0x0
N1DAn
Destination address register [Next1]
0x10
32
read-write
n
0x0
0x0
N1SAn
Source address register [Next1]
0xC
32
read-write
n
0x0
0x0
N1TBn
Transaction byte register [Next1]
0x14
32
read-write
n
0x0
0x0
NXLAn
Link address register [Next]
0x38
32
read-write
n
0x0
0x0
DSS0
DMAC space source size
DMACSS
0x0
0x0
0x20
registers
n
DCNTn
Continuous space destination size register
0x8
32
read-write
n
0x0
0x0
DSKPn
Skip space destination size register
0xC
32
read-write
n
0x0
0x0
SCNTn
Continuous space source size register
0x0
32
read-write
n
0x0
0x0
SSKPn
Skip space source size register
0x4
32
read-write
n
0x0
0x0
DSS1
DMAC space source size
DMACSS
0x0
0x0
0x20
registers
n
DCNTn
Continuous space destination size register
0x8
32
read-write
n
0x0
0x0
DSKPn
Skip space destination size register
0xC
32
read-write
n
0x0
0x0
SCNTn
Continuous space source size register
0x0
32
read-write
n
0x0
0x0
SSKPn
Skip space source size register
0x4
32
read-write
n
0x0
0x0
DSS2
DMAC space source size
DMACSS
0x0
0x0
0x20
registers
n
DCNTn
Continuous space destination size register
0x8
32
read-write
n
0x0
0x0
DSKPn
Skip space destination size register
0xC
32
read-write
n
0x0
0x0
SCNTn
Continuous space source size register
0x0
32
read-write
n
0x0
0x0
SSKPn
Skip space source size register
0x4
32
read-write
n
0x0
0x0
DSS3
DMAC space source size
DMACSS
0x0
0x0
0x20
registers
n
DCNTn
Continuous space destination size register
0x8
32
read-write
n
0x0
0x0
DSKPn
Skip space destination size register
0xC
32
read-write
n
0x0
0x0
SCNTn
Continuous space source size register
0x0
32
read-write
n
0x0
0x0
SSKPn
Skip space source size register
0x4
32
read-write
n
0x0
0x0
ETH
Ethernet MAC
ETH
0x0
0x0
0x1000
registers
n
ETHPHY0
Gigabit Ethernet PHY Port0 interrupt
33
ETHPHY1
Gigabit Ethernet PHY Port1 interrupt
34
ETHMIICMP
Ethernet MII management access completion interrupt
35
ETHPAUSECMP
Ethernet pause packet transmission completion interrupt
36
ETHTXCMP
Ethernet transmission completion interrupt
37
ETHRXFIFO
RX FIFO overflow interrupt
41
ETHTXFIFO
TX FIFO underflow interrupt
42
ETHRXDMA
Ethernet MACDMA reception completion interrupt
43
ETHTXDMA
Ethernet MACDMA transmission completion interrupt
44
MACDMARXFRM
Receive frame successful interrupt
45
ETHTXFIFOERR
Ethernet TX-FIFO error interrupt
90
ETHRXERR
Ethernet reception frame error interrupt
91
ETHRXDERR
MACDMA reception error interrupt
92
ETHTXDERR
MACDMA transmission error interrupt
93
BUFDMAERR
Internal buffer DMA error interrupt
94
LED0PHY0
Gigabit Ethernet PHY LED0_PHY0 input interrupt
95
LED0PHY1
Gigabit Ethernet PHY LED0_PHY1 input interrupt
96
GBEPHYFLF
Gigabit Ethernet PHY FASTLINK_FAIL interrupt
121
LED1PHY0
Gigabit Ethernet PHY LED1_PHY0 input interrupt
122
LED1PHY1
Gigabit Ethernet PHY LED1_PHY1 input interrupt
123
LED2PHY0
Gigabit Ethernet PHY LED2_PHY0 input interrupt
124
LED2PHY1
Gigabit Ethernet PHY LED2_PHY1 input interrupt
125
GMAC_ACC
TCPIP Acc
0x208
32
read-write
n
0x0
0x0
GMAC_ADR0A
MAC Address 0A
0x100
32
read-write
n
0x0
0x0
GMAC_ADR0B
MAC Address 0B
0x104
32
read-write
n
0x0
0x0
GMAC_ADR10A
MAC Address 10A
0x150
32
read-write
n
0x0
0x0
GMAC_ADR10B
MAC Address 10B
0x154
32
read-write
n
0x0
0x0
GMAC_ADR11A
MAC Address 11A
0x158
32
read-write
n
0x0
0x0
GMAC_ADR11B
MAC Address 11B
0x15C
32
read-write
n
0x0
0x0
GMAC_ADR12A
MAC Address 12A
0x160
32
read-write
n
0x0
0x0
GMAC_ADR12B
MAC Address 12B
0x164
32
read-write
n
0x0
0x0
GMAC_ADR13A
MAC Address 13A
0x168
32
read-write
n
0x0
0x0
GMAC_ADR13B
MAC Address 13B
0x16C
32
read-write
n
0x0
0x0
GMAC_ADR14A
MAC Address 14A
0x170
32
read-write
n
0x0
0x0
GMAC_ADR14B
MAC Address 14B
0x174
32
read-write
n
0x0
0x0
GMAC_ADR15A
MAC Address 15A
0x178
32
read-write
n
0x0
0x0
GMAC_ADR15B
MAC Address 15B
0x17C
32
read-write
n
0x0
0x0
GMAC_ADR1A
MAC Address 1A
0x108
32
read-write
n
0x0
0x0
GMAC_ADR1B
MAC Address 1B
0x10C
32
read-write
n
0x0
0x0
GMAC_ADR2A
MAC Address 2A
0x110
32
read-write
n
0x0
0x0
GMAC_ADR2B
MAC Address 2B
0x114
32
read-write
n
0x0
0x0
GMAC_ADR3A
MAC Address 3A
0x118
32
read-write
n
0x0
0x0
GMAC_ADR3B
MAC Address 3B
0x11C
32
read-write
n
0x0
0x0
GMAC_ADR4A
MAC Address 4A
0x120
32
read-write
n
0x0
0x0
GMAC_ADR4B
MAC Address 4B
0x124
32
read-write
n
0x0
0x0
GMAC_ADR5A
MAC Address 5A
0x128
32
read-write
n
0x0
0x0
GMAC_ADR5B
MAC Address 5B
0x12C
32
read-write
n
0x0
0x0
GMAC_ADR6A
MAC Address 6A
0x130
32
read-write
n
0x0
0x0
GMAC_ADR6B
MAC Address 6B
0x134
32
read-write
n
0x0
0x0
GMAC_ADR7A
MAC Address 7A
0x138
32
read-write
n
0x0
0x0
GMAC_ADR7B
MAC Address 7B
0x13C
32
read-write
n
0x0
0x0
GMAC_ADR8A
MAC Address 8A
0x140
32
read-write
n
0x0
0x0
GMAC_ADR8B
MAC Address 8B
0x144
32
read-write
n
0x0
0x0
GMAC_ADR9A
MAC Address 9A
0x148
32
read-write
n
0x0
0x0
GMAC_ADR9B
MAC Address 9B
0x14C
32
read-write
n
0x0
0x0
GMAC_FLWCTL
RX Flow Control
0x98
32
read-write
n
0x0
0x0
GMAC_LPI_MODE
LPI Mode
0x224
32
read-write
n
0x0
0x0
GMAC_LPI_TIMING
LPI Timing
0x228
32
read-write
n
0x0
0x0
GMAC_MIIM
MIIM
0xA0
32
read-write
n
0x0
0x0
GMAC_MODE
MODE
0x20
32
read-write
n
0x0
0x0
GMAC_PAUSE1
Pause Packet 1
0x80
32
read-write
n
0x0
0x0
GMAC_PAUSE2
Pause Packet 2
0x84
32
read-write
n
0x0
0x0
GMAC_PAUSE3
Pause Packet 3
0x88
32
read-write
n
0x0
0x0
GMAC_PAUSE4
Pause Packet 4
0x8C
32
read-write
n
0x0
0x0
GMAC_PAUSE5
Pause Packet 5
0x90
32
read-write
n
0x0
0x0
GMAC_PAUSPKT
Pause PKT
0x9C
32
read-write
n
0x0
0x0
GMAC_RESET
RESET
0x30
32
write-only
n
0x0
0x0
GMAC_RXFIFO
RX FIFO
0x200
32
read-only
n
0x0
0x0
GMAC_RXMAC_ENA
RXMAC Enable
0x220
32
read-write
n
0x0
0x0
GMAC_RXMODE
RX MODE
0x24
32
read-write
n
0x0
0x0
GMAC_TXFIFO
TX FIFO
0x204
32
read-only
n
0x0
0x0
GMAC_TXID
TXID
0xC
32
read-only
n
0x0
0x0
GMAC_TXMODE
TX MODE
0x28
32
read-write
n
0x0
0x0
GMAC_TXRESULT
TX Result
0x10
32
read-only
n
0x0
0x0
ETHSW
Ethernet Switch
ETHSW
0x0
0x0
0x10000
registers
n
ETHSW
Ethernet SWITCH interrupt
38
ETHSWDLR
Ethernet SWITCH DLR interrupt
39
ETHSWSYNC
Ethernet SWITCH SYNC interrupt
40
aAlignmentErrors_0
Counts when mii_rx_dv deasserted but no SFD (0xd5) was
0x8108
32
read-only
n
0x0
0x0
aAlignmentErrors_1
Counts when mii_rx_dv deasserted but no SFD (0xd5) was
0xA108
32
read-only
n
0x0
0x0
aExcessCollisions_0
aExcessCollisions Frames dropped due to excessive collisions
0x81F8
32
read-only
n
0x0
0x0
aExcessCollisions_1
aExcessCollisions Frames dropped due to excessive collisions
0xA1F8
32
read-only
n
0x0
0x0
aFrameTooLong_0
total frames exceeding FRAME_LENGTH, good and bad
0x8164
32
read-only
n
0x0
0x0
aFrameTooLong_1
total frames exceeding FRAME_LENGTH, good and bad
0xA164
32
read-only
n
0x0
0x0
aLateCollisions_0
Frames transmitted in error due to late collisions
0x81F4
32
read-only
n
0x0
0x0
aLateCollisions_1
Frames transmitted in error due to late collisions
0xA1F4
32
read-only
n
0x0
0x0
aMACControlFramesReceived_0
Good Frames with type 0x8808 (incl. Pause)
0x8160
32
read-only
n
0x0
0x0
aMACControlFramesReceived_1
Good Frames with type 0x8808 (incl. Pause)
0xA160
32
read-only
n
0x0
0x0
aMACControlFrames_0
Good frames with type 0x8808 (incl. Pause)
0x81E0
32
read-only
n
0x0
0x0
aMACControlFrames_1
Good frames with type 0x8808 (incl. Pause)
0xA1E0
32
read-only
n
0x0
0x0
aMultipleCollisions_0
Successful transmissions after multiple collisions
0x81EC
32
read-only
n
0x0
0x0
aMultipleCollisions_1
Successful transmissions after multiple collisions
0xA1EC
32
read-only
n
0x0
0x0
aPAUSEMACCtrlFrames_0
PAUSEMACCtrlFrames good pause frames received
0x810C
32
read-only
n
0x0
0x0
aPAUSEMACCtrlFrames_1
PAUSEMACCtrlFrames good pause frames received
0xA10C
32
read-only
n
0x0
0x0
aSingleCollisions_0
Successful transmissions after one collisions
0x81F0
32
read-only
n
0x0
0x0
aSingleCollisions_1
Successful transmissions after one collisions
0xA1F0
32
read-only
n
0x0
0x0
ATIME
TSM Time value
0xC124
32
read-write
n
0x0
0x0
ATIME_CORR
TSM correction value
0xC130
32
read-write
n
0x0
0x0
ATIME_CTRL
TSM Time control
0xC120
32
read-write
n
0x0
0x0
ATIME_EVT_PERIOD
TSM periodic events
0xC12C
32
read-write
n
0x0
0x0
ATIME_INC
TSM correction increment value
0xC134
32
read-write
n
0x0
0x0
ATIME_OFFSET
TSM offset corrections
0xC128
32
read-write
n
0x0
0x0
ATIME_OFFS_CORR
TSM offset correction counter
0xC13C
32
read-write
n
0x0
0x0
ATIME_SEC
TSM second time value
0xC138
32
read-write
n
0x0
0x0
BCAST_DEFAULT_MASK
Default broadcast resolution
0x14
32
read-write
n
0x0
0x0
BEC_INTRVL
Beacon interval
0xE030
32
read-only
n
0x0
0x0
BEC_TMOUT
Beacon timeout timer value
0xE02C
32
read-only
n
0x0
0x0
COMMAND_CONFIG0
Command Register
0x8008
32
read-write
n
0x0
0x0
COMMAND_CONFIG1
Command Register
0xA008
32
read-write
n
0x0
0x0
CRCErrors_0
wrong CRC but good length (64..MTU)
0x8114
32
read-only
n
0x0
0x0
CRCErrors_1
wrong CRC but good length (64..MTU)
0xA114
32
read-only
n
0x0
0x0
DLR_CONTROL
DLR Control register
0xE000
32
read-write
n
0x0
0x0
DLR_ETH_TYP
Ethernet Type to compare for DLR frame
0xE008
32
read-write
n
0x0
0x0
DLR_IRQ_CTRL
Interrupt Control
0xE00C
32
read-write
n
0x0
0x0
DLR_IRQ_STAT_ACK
Interrupt Status Acknowledgement
0xE010
32
read-write
n
0x0
0x0
DLR_STATUS
DLR Status register
0xE004
32
read-only
n
0x0
0x0
etherStatsDropEvents_0
Increments when frames are dropped
0x812C
32
read-only
n
0x0
0x0
etherStatsDropEvents_1
Increments when frames are dropped
0xA12C
32
read-only
n
0x0
0x0
etherStatsFragments_0
rames with length less 64 and bad CRC
0x815C
32
read-only
n
0x0
0x0
etherStatsFragments_1
rames with length less 64 and bad CRC
0xA15C
32
read-only
n
0x0
0x0
etherStatsJabbers_0
frames with length exceeding FRM_LENGTH, bad CRC
0x8158
32
read-only
n
0x0
0x0
etherStatsJabbers_1
frames with length exceeding FRM_LENGTH, bad CRC
0xA158
32
read-only
n
0x0
0x0
etherStatsOctets_0
total octets, good and bad frames
0x8100
32
read-only
n
0x0
0x0
etherStatsOctets_1
total octets, good and bad frames
0xA100
32
read-only
n
0x0
0x0
etherStatsOversizePkts_0
frames with length exceeding FRM_LENGTH, good CRC
0x8154
32
read-only
n
0x0
0x0
etherStatsOversizePkts_1
frames with length exceeding FRM_LENGTH, good CRC
0xA154
32
read-only
n
0x0
0x0
etherStatsPkts1024to1518Octets_0
frames with length from 1024 .. 1518 bytes
0x814C
32
read-only
n
0x0
0x0
etherStatsPkts1024to1518Octets_1
frames with length from 1024 .. 1518 bytes
0xA14C
32
read-only
n
0x0
0x0
etherStatsPkts128to255Octets_0
frames with length from 128 .. 255 bytes
0x8140
32
read-only
n
0x0
0x0
etherStatsPkts128to255Octets_1
frames with length from 128 .. 255 bytes
0xA140
32
read-only
n
0x0
0x0
etherStatsPkts1519toMax_0
frames with length from 1519 .. value in FRM_LENGTH register
0x8150
32
read-only
n
0x0
0x0
etherStatsPkts1519toMax_1
frames with length from 1519 .. value in FRM_LENGTH register
0xA150
32
read-only
n
0x0
0x0
etherStatsPkts256to511Octets_0
frames with length from 256 .. 511 bytes
0x8144
32
read-only
n
0x0
0x0
etherStatsPkts256to511Octets_1
frames with length from 256 .. 511 bytes
0xA144
32
read-only
n
0x0
0x0
etherStatsPkts512to1023Octets_0
frames with length from 512 .. 1023 bytes
0x8148
32
read-only
n
0x0
0x0
etherStatsPkts512to1023Octets_1
frames with length from 512 .. 1023 bytes
0xA148
32
read-only
n
0x0
0x0
etherStatsPkts64Octets_0
frames with length of 64 bytes
0x8138
32
read-only
n
0x0
0x0
etherStatsPkts64Octets_1
frames with length of 64 bytes
0xA138
32
read-only
n
0x0
0x0
etherStatsPkts65to127Octets_0
frames with length from 65 .. 127 bytes
0x813C
32
read-only
n
0x0
0x0
etherStatsPkts65to127Octets_1
frames with length from 65 .. 127 bytes
0xA13C
32
read-only
n
0x0
0x0
etherStatsPkts_0
total frames, good and bad
0x8130
32
read-only
n
0x0
0x0
etherStatsPkts_1
total frames, good and bad
0xA130
32
read-only
n
0x0
0x0
etherStatsUndersizePkts_0
frames with length less 64 bytes and good CRC
0x8134
32
read-only
n
0x0
0x0
etherStatsUndersizePkts_1
frames with length less 64 bytes and good CRC
0xA134
32
read-only
n
0x0
0x0
ETH_STYP_VER
DLR Ring Ether sub Type and Protocol Version
0xE038
32
read-only
n
0x0
0x0
FramesOK_0
good frames received
0x8110
32
read-only
n
0x0
0x0
FramesOK_1
good frames received
0xA110
32
read-only
n
0x0
0x0
FRM_LENGTH0
Max frame length
0x8014
32
read-write
n
0x0
0x0
FRM_LENGTH1
Max frame length
0xA014
32
read-write
n
0x0
0x0
HUB_CONTROL
HUB Control register
0x1C0
32
read-write
n
0x0
0x0
HUB_FLT_MAC0hi
last 2 octets of MAC address n
0x1CC
32
read-write
n
0x0
0x0
HUB_FLT_MAC0lo
first 4 octets of MAC address n
0x1C8
32
read-write
n
0x0
0x0
HUB_FLT_MAC1hi
last 2 octets of MAC address n
0x1D4
32
read-write
n
0x0
0x0
HUB_FLT_MAC1lo
first 4 octets of MAC address n
0x1D0
32
read-write
n
0x0
0x0
HUB_FLT_MAC2hi
last 2 octets of MAC address n
0x1DC
32
read-write
n
0x0
0x0
HUB_FLT_MAC2lo
first 4 octets of MAC address n
0x1D8
32
read-write
n
0x0
0x0
HUB_FLT_MAC3hi
last 2 octets of MAC address n
0x1E4
32
read-write
n
0x0
0x0
HUB_FLT_MAC3lo
first 4 octets of MAC address n
0x1E0
32
read-write
n
0x0
0x0
HUB_FLT_MAC4hi
last 2 octets of MAC address n
0x1EC
32
read-write
n
0x0
0x0
HUB_FLT_MAC4lo
first 4 octets of MAC address n
0x1E8
32
read-write
n
0x0
0x0
HUB_FLT_MAC5hi
last 2 octets of MAC address n
0x1F4
32
read-write
n
0x0
0x0
HUB_FLT_MAC5lo
first 4 octets of MAC address n
0x1F0
32
read-write
n
0x0
0x0
HUB_FLT_MAC6hi
last 2 octets of MAC address 6
0x1FC
32
read-write
n
0x0
0x0
HUB_FLT_MAC6lo
first 4 octets of MAC address 6
0x1F8
32
read-write
n
0x0
0x0
HUB_STATS
HUB status
0x1C4
32
read-only
n
0x0
0x0
IDISC_BLOCKED0
Port n incoming frames discarded
0x314
32
read-only
n
0x0
0x0
IDISC_BLOCKED1
Port n incoming frames discarded
0x31C
32
read-only
n
0x0
0x0
IDISC_BLOCKED2
Port n incoming frames discarded
0x324
32
read-only
n
0x0
0x0
ifBroadcastPkts_0
Good Broadcast
0x81A8
32
read-only
n
0x0
0x0
ifBroadcastPkts_1
Good Broadcast
0xA1A8
32
read-only
n
0x0
0x0
ifInBroadcastPkts_0
Good Broadcast
0x8128
32
read-only
n
0x0
0x0
ifInBroadcastPkts_1
Good Broadcast
0xA128
32
read-only
n
0x0
0x0
ifInErrors_0
Counts for any receive errors
0x811C
32
read-only
n
0x0
0x0
ifInErrors_1
Counts for any receive errors
0xA11C
32
read-only
n
0x0
0x0
ifInMulticastPkts_0
Good Multicast
0x8124
32
read-only
n
0x0
0x0
ifInMulticastPkts_1
Good Multicast
0xA124
32
read-only
n
0x0
0x0
ifInUcastPkts_0
ifInUcastPkts Good Unicast
0x8120
32
read-only
n
0x0
0x0
ifInUcastPkts_1
ifInUcastPkts Good Unicast
0xA120
32
read-only
n
0x0
0x0
ifMulticastPkts_0
Good Multicast
0x81A4
32
read-only
n
0x0
0x0
ifMulticastPkts_1
Good Multicast
0xA1A4
32
read-only
n
0x0
0x0
ifOutErrors_0
any error (ff_tx_err, toolong, but not counting undersized)
0x819C
32
read-only
n
0x0
0x0
ifOutErrors_1
any error (ff_tx_err, toolong, but not counting undersized)
0xA19C
32
read-only
n
0x0
0x0
ifUcastPkts_0
Good Unicast
0x81A0
32
read-only
n
0x0
0x0
ifUcastPkts_1
Good Unicast
0xA1A0
32
read-only
n
0x0
0x0
INPUT_LEARN_BLOCK
Define port in blocking state and enable or disable learning
0x1C
32
read-write
n
0x0
0x0
INV_TMOUT
Last out of range Beacon timeout timer value
0xE03C
32
read-only
n
0x0
0x0
IP_PRIORITY0
IPv4 priority resolution
0x140
32
read-write
n
0x0
0x0
IP_PRIORITY1
IPv4 priority resolution
0x144
32
read-write
n
0x0
0x0
IP_PRIORITY2
IPv4 priority resolution
0x148
32
read-write
n
0x0
0x0
LOC_MAChi
Local MAC address
0xE018
32
read-write
n
0x0
0x0
LOC_MAClo
Local MAC address
0xE014
32
read-write
n
0x0
0x0
LRN_REC_A
Learning Records A
0x500
32
read-only
n
0x0
0x0
LRN_REC_B
Learning Records B
0x504
32
read-only
n
0x0
0x0
LRN_STATUS
Learning data available status
0x508
32
read-only
n
0x0
0x0
MAC_STATUS0
informal status info for both MACs
0x8058
32
read-only
n
0x0
0x0
MAC_STATUS1
informal status info for both MACs
0xA058
32
read-only
n
0x0
0x0
MCAST_DEFAULT_MASK
Default multicast resolution
0x18
32
read-write
n
0x0
0x0
MGMT_CONFIG
Bridge Management Port Config
0x20
32
read-write
n
0x0
0x0
MODE_CONFIG
Define global config settings
0x24
32
read-write
n
0x0
0x0
OctetsOK_0
total octets, good frames only
0x8104
32
read-only
n
0x0
0x0
OctetsOK_1
total octets, good frames only
0xA104
32
read-only
n
0x0
0x0
ODISC0
Port n outgoing frames discarded
0x310
32
read-only
n
0x0
0x0
ODISC1
Port n outgoing frames discarded
0x318
32
read-only
n
0x0
0x0
ODISC2
Port n outgoing frames discarded
0x320
32
read-only
n
0x0
0x0
OQMGR_STATUS
OQMGR status info
0x80
32
read-write
n
0x0
0x0
PORT0_CTRL
TSM Port n timestamp control/status
0xC020
32
read-write
n
0x0
0x0
PORT0_TIME
TSM Port n memorized timestamp
0xC024
32
read-only
n
0x0
0x0
PORT1_CTRL
TSM Port n timestamp control/status
0xC028
32
read-write
n
0x0
0x0
PORT1_TIME
TSM Port n memorized timestamp
0xC02C
32
read-only
n
0x0
0x0
PORT_ENA
Port Enable Bits
0x8
32
read-write
n
0x0
0x0
PRIORITY_CFG0
priority resolution config
0x180
32
read-write
n
0x0
0x0
PRIORITY_CFG1
priority resolution config
0x184
32
read-write
n
0x0
0x0
PRIORITY_CFG2
priority resolution config
0x188
32
read-write
n
0x0
0x0
QMGR_CGS_STAT
OQMGR Congestion Status
0x8C
32
read-only
n
0x0
0x0
QMGR_IFACE_STAT
OQMGR Internal I/F handshaking
0x90
32
read-only
n
0x0
0x0
QMGR_MINCELLS
OQMGR Low memory threshold
0x84
32
read-write
n
0x0
0x0
QMGR_ST_MINCELLS
OQMGR Statistic lowest free cells
0x88
32
read-write
n
0x0
0x0
QMGR_WEIGHTS
OQMGR weights
0x94
32
read-write
n
0x0
0x0
RX_ALMOST_EMPTY0
receive FIFO almost empty threshold
0x802C
32
read-only
n
0x0
0x0
RX_ALMOST_EMPTY1
receive FIFO almost empty threshold
0xA02C
32
read-only
n
0x0
0x0
RX_ALMOST_FULL0
receive FIFO almost full threshold
0x8030
32
read-only
n
0x0
0x0
RX_ALMOST_FULL1
receive FIFO almost full threshold
0xA030
32
read-only
n
0x0
0x0
RX_ERR_STAT0
Number of Beacon frames received with crc error on port n
0xE064
32
read-only
n
0x0
0x0
RX_ERR_STAT1
Number of Beacon frames received with crc error on port n
0xE074
32
read-only
n
0x0
0x0
RX_SECTION_EMPTY0
receive FIFO section empty threshold
0x801C
32
read-only
n
0x0
0x0
RX_SECTION_EMPTY1
receive FIFO section empty threshold
0xA01C
32
read-only
n
0x0
0x0
RX_SECTION_FULL0
receive FIFO section full threshold
0x8020
32
read-write
n
0x0
0x0
RX_SECTION_FULL1
receive FIFO section full threshold
0xA020
32
read-write
n
0x0
0x0
RX_STAT0
Number of Beacon frames received on port n
0xE060
32
read-only
n
0x0
0x0
RX_STAT1
Number of Beacon frames received on port n
0xE070
32
read-only
n
0x0
0x0
SEQ_ID
Sequence ID of the last Beacon frame
0xE040
32
read-only
n
0x0
0x0
StackedVLANOK_0
Good with stacked VLAN (two VLAN tags)
0x816C
32
read-only
n
0x0
0x0
StackedVLANOK_1
Good with stacked VLAN (two VLAN tags)
0xA16C
32
read-only
n
0x0
0x0
STATE_VLAN
DLR Ring state
0xE028
32
read-only
n
0x0
0x0
SUPR_IPADR
Ring supervisor's IP address
0xE034
32
read-only
n
0x0
0x0
SUPR_MAChi
Active ring supervisor's MAC address
0xE024
32
read-only
n
0x0
0x0
SUPR_MAClo
Active ring supervisor's MAC address
0xE020
32
read-only
n
0x0
0x0
TOTAL_BYT_DISC
Sum of bytes of frames in TOTAL_DISC
0x304
32
read-only
n
0x0
0x0
TOTAL_BYT_FRM
Sum of bytes of frames in TOTAL_FRM
0x300
32
read-only
n
0x0
0x0
TOTAL_DISC
Total number of incoming frames discarded in SW
0x30C
32
read-only
n
0x0
0x0
TOTAL_FRM
Total number of incoming frames
0x308
32
read-only
n
0x0
0x0
TSM_CONFIG
TSM Module config
0xC004
32
read-write
n
0x0
0x0
TSM_IRQ_STAT_ACK
TSM Interrupt Status/Ack
0xC008
32
read-write
n
0x0
0x0
TXaFrameTooLong_0
total frames exceeding FRAME_LENGTH, good and bad
0x81E4
32
read-only
n
0x0
0x0
TXaFrameTooLong_1
total frames exceeding FRAME_LENGTH, good and bad
0xA1E4
32
read-only
n
0x0
0x0
TXaPAUSEMACCtrlFrames_0
good pause transmitted
0x818C
32
read-only
n
0x0
0x0
TXaPAUSEMACCtrlFrames_1
good pause transmitted
0xA18C
32
read-only
n
0x0
0x0
TxCRCErrors_0
transmitted with error but good length (ff_tx_err)
0x8194
32
read-only
n
0x0
0x0
TxCRCErrors_1
transmitted with error but good length (ff_tx_err)
0xA194
32
read-only
n
0x0
0x0
TXetherStatsDropEvents_0
Counts undersized frames transmitted
0x81AC
32
read-only
n
0x0
0x0
TXetherStatsDropEvents_1
Counts undersized frames transmitted
0xA1AC
32
read-only
n
0x0
0x0
TXetherStatsFragments_0
frames with length less 64 bytes and marked erronenousyte
0x81DC
32
read-only
n
0x0
0x0
TXetherStatsFragments_1
frames with length less 64 bytes and marked erronenousyte
0xA1DC
32
read-only
n
0x0
0x0
TXetherStatsJabbers_0
frames with length exceeding FRM_LENGTH, bad
0x81D8
32
read-only
n
0x0
0x0
TXetherStatsJabbers_1
frames with length exceeding FRM_LENGTH, bad
0xA1D8
32
read-only
n
0x0
0x0
TXetherStatsOctets_0
total octets, good and bad frames
0x8180
32
read-only
n
0x0
0x0
TXetherStatsOctets_1
total octets, good and bad frames
0xA180
32
read-only
n
0x0
0x0
TXetherStatsOversizePkts_0
frames with length exceeding FRM_LENGTH, good
0x81D4
32
read-only
n
0x0
0x0
TXetherStatsOversizePkts_1
frames with length exceeding FRM_LENGTH, good
0xA1D4
32
read-only
n
0x0
0x0
TXetherStatsPkts1024to1518Octets_0
frames with length from 1024 .. 1518 byte
0x81CC
32
read-only
n
0x0
0x0
TXetherStatsPkts1024to1518Octets_1
frames with length from 1024 .. 1518 byte
0xA1CC
32
read-only
n
0x0
0x0
TXetherStatsPkts128to255Octets_0
frames with length from 128 .. 255 byte
0x81C0
32
read-only
n
0x0
0x0
TXetherStatsPkts128to255Octets_1
frames with length from 128 .. 255 byte
0xA1C0
32
read-only
n
0x0
0x0
TXetherStatsPkts1519toMax_0
frames with length from 1519 .. value in FRM_LENGTH register
0x81D0
32
read-only
n
0x0
0x0
TXetherStatsPkts1519toMax_1
frames with length from 1519 .. value in FRM_LENGTH register
0xA1D0
32
read-only
n
0x0
0x0
TXetherStatsPkts256to511Octets_0
frames with length from 256 .. 511 byte
0x81C4
32
read-only
n
0x0
0x0
TXetherStatsPkts256to511Octets_1
frames with length from 256 .. 511 byte
0xA1C4
32
read-only
n
0x0
0x0
TXetherStatsPkts512to1023Octets_0
frames with length from 512 .. 1023 byte
0x81C8
32
read-only
n
0x0
0x0
TXetherStatsPkts512to1023Octets_1
frames with length from 512 .. 1023 byte
0xA1C8
32
read-only
n
0x0
0x0
TXetherStatsPkts64Octets_0
frames with length of 64 bytes
0x81B8
32
read-only
n
0x0
0x0
TXetherStatsPkts64Octets_1
frames with length of 64 bytes
0xA1B8
32
read-only
n
0x0
0x0
TXetherStatsPkts65to127Octets_0
frames with length from 65 .. 127 bytes
0x81BC
32
read-only
n
0x0
0x0
TXetherStatsPkts65to127Octets_1
frames with length from 65 .. 127 bytes
0xA1BC
32
read-only
n
0x0
0x0
TXetherStatsPkts_0
total frames, good and bad
0x81B0
32
read-only
n
0x0
0x0
TXetherStatsPkts_1
total frames, good and bad
0xA1B0
32
read-only
n
0x0
0x0
TXetherStatsUndersizePkts_0
frames with length less 64 bytes and good CRC
0x81B4
32
read-only
n
0x0
0x0
TXetherStatsUndersizePkts_1
frames with length less 64 bytes and good CRC
0xA1B4
32
read-only
n
0x0
0x0
TxFramesOK_0
good transmitted
0x8190
32
read-only
n
0x0
0x0
TxFramesOK_1
good transmitted
0xA190
32
read-only
n
0x0
0x0
TxOctetsOK_0
total octets, good frames only
0x8184
32
read-only
n
0x0
0x0
TxOctetsOK_1
total octets, good frames only
0xA184
32
read-only
n
0x0
0x0
TxVLANOK_0
good,VLAN tagged
0x8198
32
read-only
n
0x0
0x0
TxVLANOK_1
good,VLAN tagged
0xA198
32
read-only
n
0x0
0x0
TX_ALMOST_EMPTY0
transmit FIFO almost empty threshold
0x8034
32
read-only
n
0x0
0x0
TX_ALMOST_EMPTY1
transmit FIFO almost empty threshold
0xA034
32
read-only
n
0x0
0x0
TX_ALMOST_FULL0
transmit FIFO almost full threshold
0x8038
32
read-only
n
0x0
0x0
TX_ALMOST_FULL1
transmit FIFO almost full threshold
0xA038
32
read-only
n
0x0
0x0
TX_IPG_LENGTH0
Programmable Inter-Packet Gap
0x805C
32
read-write
n
0x0
0x0
TX_IPG_LENGTH1
Programmable Inter-Packet Gap
0xA05C
32
read-write
n
0x0
0x0
TX_SECTION_EMPTY0
transmit FIFO section empty threshold
0x8024
32
read-write
n
0x0
0x0
TX_SECTION_EMPTY1
transmit FIFO section empty threshold
0xA024
32
read-write
n
0x0
0x0
TX_SECTION_FULL0
transmit FIFO section full threshold
0x8028
32
read-write
n
0x0
0x0
TX_SECTION_FULL1
transmit FIFO section full threshold
0xA028
32
read-write
n
0x0
0x0
TX_STAT0
Number of Beacon frames forwarded through the HUB from port n to port m
0xE068
32
read-only
n
0x0
0x0
TX_STAT1
Number of Beacon frames forwarded through the HUB from port n to port m
0xE078
32
read-only
n
0x0
0x0
UCAST_DEFAULT_MASK
Default unicast flooding resolution
0xC
32
read-write
n
0x0
0x0
VLANOK_0
good,VLAN tagged
0x8118
32
read-only
n
0x0
0x0
VLANOK_1
good,VLAN tagged
0xA118
32
read-only
n
0x0
0x0
VLAN_PRIORITY0
VLAN priority resolution map
0x100
32
read-write
n
0x0
0x0
VLAN_PRIORITY1
VLAN priority resolution map
0x104
32
read-write
n
0x0
0x0
VLAN_PRIORITY2
VLAN priority resolution map
0x108
32
read-write
n
0x0
0x0
VLAN_TAG_ID
VLAN type field value
0x34
32
read-write
n
0x0
0x0
EXTPORT
Port (EXTPORT)
EXTPORT
0x0
0x0
0x400
registers
n
EXTP0B
EXT Port register 0 ( 8 bit)
EXTP0W
0x0
8
read-write
n
0x0
0x0
EXTP0H
EXT Port register 0 ( 16 bit)
EXTP0W
0x0
16
read-write
n
0x0
0x0
EXTP0W
EXT Port register 0 ( 32 bit)
0x0
32
read-write
n
0x0
0x0
EXTP1B
EXT Port register 1 ( 8 bit)
EXTP0W
0x1
8
read-write
n
0x0
0x0
EXTPFC0B
EXT function control register 0 ( 8 bit)
EXTPFC0W
0x30
8
read-write
n
0x0
0x0
EXTPFC0H
EXT Port function control register 0 ( 16 bit)
EXTPFC0W
0x30
16
read-write
n
0x0
0x0
EXTPFC0W
EXT Port function control register 0 ( 32 bit)
0x30
32
read-write
n
0x0
0x0
EXTPFC1B
EXT function control register 1 ( 8 bit)
EXTPFC0W
0x31
8
read-write
n
0x0
0x0
EXTPFCE0B
EXT function control expregister 0 ( 8 bit)
EXTPFCE0W
0x40
8
read-write
n
0x0
0x0
EXTPFCE0H
EXT Port function control ext.register 0 ( 16 bit)
EXTPFCE0W
0x40
16
read-write
n
0x0
0x0
EXTPFCE0W
EXT Port function control ext.register 0 ( 32 bit)
0x40
32
read-write
n
0x0
0x0
EXTPFCE1B
EXT function control expregister 1 ( 8 bit)
EXTPFCE0W
0x41
8
read-write
n
0x0
0x0
EXTPIN0B
EXT Port input register 0 ( 8 bit)
EXTPIN0W
0x50
8
read-only
n
0x0
0x0
EXTPIN0H
EXT Port input register 0 ( 16 bit)
EXTPIN0W
0x50
16
read-only
n
0x0
0x0
EXTPIN0W
EXT Port input register 0 ( 32 bit)
0x50
32
read-only
n
0x0
0x0
EXTPIN1B
EXT Port input register 0 ( 8 bit)
EXTPIN0W
0x51
8
read-only
n
0x0
0x0
EXTPM0B
EXT Port Mode register 0 ( 8 bit)
EXTPM0W
0x10
8
read-write
n
0x0
0x0
EXTPM0H
EXT Port mode register 0 ( 16 bit)
EXTPM0W
0x10
16
read-write
n
0x0
0x0
EXTPM0W
EXT Port mode register 0 ( 32 bit)
0x10
32
read-write
n
0x0
0x0
EXTPM1B
EXT Port Mode register 1 ( 8 bit)
EXTPM0W
0x11
8
read-write
n
0x0
0x0
EXTPMC0B
EXT Port mode control register 0 ( 8 bit)
EXTPMC0W
0x20
8
read-write
n
0x0
0x0
EXTPMC0H
EXT Port mode control register 0 ( 16 bit)
EXTPMC0W
0x20
16
read-write
n
0x0
0x0
EXTPMC0W
EXT Port mode control register 0 ( 32 bit)
0x20
32
read-write
n
0x0
0x0
EXTPMC1B
EXT Port mode control register 1 ( 8 bit)
EXTPMC0W
0x21
8
read-write
n
0x0
0x0
GPIO
Port (GPIO)
GPIO
0x0
0x0
0x400
registers
n
INTPZ0
INTPZ0 input
47
INTPZ1
INTPZ1 input
48
INTPZ2
INTPZ2 input
49
INTPZ3
INTPZ3 input
50
INTPZ4
INTPZ4 input
51
INTPZ5
INTPZ5 input
52
INTPZ6
INTPZ6 input
53
INTPZ7
INTPZ7 input
54
INTPZ8
INTPZ8 input
55
INTPZ9
INTPZ9 input
56
INTPZ10
INTPZ10 input
57
INTPZ11
INTPZ11 input / TAUD channel 5 interrupt
58
INTPZ12
INTPZ12 input / TAUD channel 6 interrupt
59
INTPZ13
INTPZ13 input / TAUD channel 7 interrupt
60
INTPZ14
INTPZ14 input / TAUD channel 8 interrupt
61
INTPZ15
INTPZ15 input / TAUD channel 9 interrupt
62
INTPZ16
INTPZ16 input / TAUD channel 10 interrupt
63
INTPZ17
INTPZ17 input / TAUD channel 11 interrupt
64
INTPZ18
INTPZ18 input / TAUD channel 12 interrupt
65
INTPZ19
INTPZ19 input / TAUD channel 13 interrupt
66
INTPZ20
INTPZ20 input / TAUD channel 14 interrupt
67
INTPZ21
INTPZ21 input / TAUD channel 15 interrupt
68
INTPZ22
INTPZ22 input / peak interrupt (TAPA)
69
INTPZ23
INTPZ23 input / trough interrupt (TAPA)
70
INTPZ24
INTPZ24 input
71
INTPZ25
INTPZ25 input
72
INTPZ26
INTPZ26 input
73
INTPZ27
INTPZ27 input
74
INTPZ28
INTPZ28 input
75
P0B
Port register 0 ( 8 bit)
P0W
0x0
8
read-write
n
0x0
0x0
P0H
Port register 0 ( 16 bit)
P0W
0x0
16
read-write
n
0x0
0x0
P0W
Port register 0 ( 32 bit)
0x0
32
read-write
n
0x0
0x0
P1B
Port register 1 ( 8 bit)
P0W
0x1
8
read-write
n
0x0
0x0
P2B
Port register 2 ( 8 bit)
P0W
0x2
8
read-write
n
0x0
0x0
P2H
Port register 2 ( 16 bit)
P0W
0x2
16
read-write
n
0x0
0x0
P3B
Port register 3 ( 8 bit)
P0W
0x3
8
read-write
n
0x0
0x0
P4B
Port register 4 ( 8 bit)
P4W
0x4
8
read-write
n
0x0
0x0
P4H
Port register 4 ( 16 bit)
P4W
0x4
16
read-write
n
0x0
0x0
P4W
Port register 4 ( 32 bit)
0x4
32
read-write
n
0x0
0x0
P5B
Port register 5 ( 8 bit)
P4W
0x5
8
read-write
n
0x0
0x0
P6B
Port register 6 ( 8 bit)
P4W
0x6
8
read-write
n
0x0
0x0
P6H
Port register 6 ( 16 bit)
P4W
0x6
16
read-write
n
0x0
0x0
P7B
Port register 7 ( 8 bit)
P4W
0x7
8
read-write
n
0x0
0x0
PFC0B
Port function control register 0 ( 8 bit)
PFC0W
0x30
8
read-write
n
0x0
0x0
PFC0H
Port function control register 0 ( 16 bit)
PFC0W
0x30
16
read-write
n
0x0
0x0
PFC0W
Port function control register 0 ( 32 bit)
0x30
32
read-write
n
0x0
0x0
PFC1B
Port function control register 1 ( 8 bit)
PFC0W
0x31
8
read-write
n
0x0
0x0
PFC2B
Port function control register 2 ( 8 bit)
PFC0W
0x32
8
read-write
n
0x0
0x0
PFC2H
Port function control register 2 ( 16 bit)
PFC0W
0x32
16
read-write
n
0x0
0x0
PFC3B
Port function control register 3 ( 8 bit)
PFC0W
0x33
8
read-write
n
0x0
0x0
PFC4B
Port function control register 4 ( 8 bit)
PFC4W
0x34
8
read-write
n
0x0
0x0
PFC4H
Port function control register 4 ( 16 bit)
PFC4W
0x34
16
read-write
n
0x0
0x0
PFC4W
Port function control register 4 ( 32 bit)
0x34
32
read-write
n
0x0
0x0
PFC5B
Port function control register 5 ( 8 bit)
PFC4W
0x35
8
read-write
n
0x0
0x0
PFC6B
Port function control register 6 ( 8 bit)
PFC4W
0x36
8
read-write
n
0x0
0x0
PFC6H
Port function control register 6 ( 16 bit)
PFC4W
0x36
16
read-write
n
0x0
0x0
PFC7B
Port function control register 7 ( 8 bit)
PFC4W
0x37
8
read-write
n
0x0
0x0
PFCE0B
Port function control ext.register 0 ( 8 bit)
PFCE0W
0x40
8
read-write
n
0x0
0x0
PFCE0H
Port function control ext.register 0 ( 16 bit)
PFCE0W
0x40
16
read-write
n
0x0
0x0
PFCE0W
Port function control ext.register 0 ( 32 bit)
0x40
32
read-write
n
0x0
0x0
PFCE1B
Port function control ext.register 1 ( 8 bit)
PFCE0W
0x41
8
read-write
n
0x0
0x0
PFCE2B
Port function control ext.register 2 ( 8 bit)
PFCE0W
0x42
8
read-write
n
0x0
0x0
PFCE2H
Port function control ext.register 2 ( 16 bit)
PFCE0W
0x42
16
read-write
n
0x0
0x0
PFCE3B
Port function control ext.register 3 ( 8 bit)
PFCE0W
0x43
8
read-write
n
0x0
0x0
PFCE4B
Port function control ext.register 4 ( 8 bit)
PFCE4W
0x44
8
read-write
n
0x0
0x0
PFCE4H
Port function control ext.register 4 ( 16 bit)
PFCE4W
0x44
16
read-write
n
0x0
0x0
PFCE4W
Port function control ext.register 4 ( 32 bit)
0x44
32
read-write
n
0x0
0x0
PFCE5B
Port function control ext.register 5 ( 8 bit)
PFCE4W
0x45
8
read-write
n
0x0
0x0
PFCE6B
Port function control ext.register 6 ( 8 bit)
PFCE4W
0x46
8
read-write
n
0x0
0x0
PFCE6H
Port function control ext.register 6 ( 16 bit)
PFCE4W
0x46
16
read-write
n
0x0
0x0
PFCE7B
Port function control ext.register 7 ( 8 bit)
PFCE4W
0x47
8
read-write
n
0x0
0x0
PIN0B
Port input level register 0 ( 8 bit)
PIN0W
0x50
8
read-only
n
0x0
0x0
PIN0H
Port input level register 0 ( 16 bit)
PIN0W
0x50
16
read-only
n
0x0
0x0
PIN0W
Port input level register 0 ( 32 bit)
0x50
32
read-only
n
0x0
0x0
PIN1B
Port input level register 1 ( 8 bit)
PIN0W
0x51
8
read-only
n
0x0
0x0
PIN2B
Port input level register 2 ( 8 bit)
PIN0W
0x52
8
read-only
n
0x0
0x0
PIN2H
Port input level register 2 ( 16 bit)
PIN0W
0x52
16
read-only
n
0x0
0x0
PIN3B
Port input level register 3 ( 8 bit)
PIN0W
0x53
8
read-only
n
0x0
0x0
PIN4B
Port input level register 4 ( 8 bit)
PIN4W
0x54
8
read-only
n
0x0
0x0
PIN4H
Port input level register 4 ( 16 bit)
PIN4W
0x54
16
read-only
n
0x0
0x0
PIN4W
Port input level register 4 ( 32 bit)
0x54
32
read-only
n
0x0
0x0
PIN5B
Port input level register 5 ( 8 bit)
PIN4W
0x55
8
read-only
n
0x0
0x0
PIN6B
Port input level register 6 ( 8 bit)
PIN4W
0x56
8
read-only
n
0x0
0x0
PIN6H
Port input level register 6 ( 16 bit)
PIN4W
0x56
16
read-only
n
0x0
0x0
PIN7B
Port input level register 7 ( 8 bit)
PIN4W
0x57
8
read-only
n
0x0
0x0
PM0B
Port mode register 0 ( 8 bit)
PM0W
0x10
8
read-write
n
0x0
0x0
PM0H
Port mode register 0 ( 16 bit)
PM0W
0x10
16
read-write
n
0x0
0x0
PM0W
Port mode register 0 ( 32 bit)
0x10
32
read-write
n
0x0
0x0
PM1B
Port mode register 1 ( 8 bit)
PM0W
0x11
8
read-write
n
0x0
0x0
PM2B
Port mode register 2 ( 8 bit)
PM0W
0x12
8
read-write
n
0x0
0x0
PM2H
Port mode register 2 ( 16 bit)
PM0W
0x12
16
read-write
n
0x0
0x0
PM3B
Port mode register 3 ( 8 bit)
PM0W
0x13
8
read-write
n
0x0
0x0
PM4B
Port mode register 4 ( 8 bit)
PM4W
0x14
8
read-write
n
0x0
0x0
PM4H
Port mode register 4 ( 16 bit)
PM4W
0x14
16
read-write
n
0x0
0x0
PM4W
Port mode register 4 ( 32 bit)
0x14
32
read-write
n
0x0
0x0
PM5B
Port mode register 5 ( 8 bit)
PM4W
0x15
8
read-write
n
0x0
0x0
PM6B
Port mode register 6 ( 8 bit)
PM4W
0x16
8
read-write
n
0x0
0x0
PM6H
Port mode register 6 ( 16 bit)
PM4W
0x16
16
read-write
n
0x0
0x0
PM7B
Port mode register 7 ( 8 bit)
PM4W
0x17
8
read-write
n
0x0
0x0
PMC0B
Port mode control register 0 ( 8 bit)
PMC0W
0x20
8
read-write
n
0x0
0x0
PMC0H
Port mode control register 0 ( 16 bit)
PMC0W
0x20
16
read-write
n
0x0
0x0
PMC0W
Port mode control register 0 ( 32 bit)
0x20
32
read-write
n
0x0
0x0
PMC1B
Port mode control register 1 ( 8 bit)
PMC0W
0x21
8
read-write
n
0x0
0x0
PMC2B
Port mode control register 2 ( 8 bit)
PMC0W
0x22
8
read-write
n
0x0
0x0
PMC2H
Port mode control register 2 ( 16 bit)
PMC0W
0x22
16
read-write
n
0x0
0x0
PMC3B
Port mode control register 3 ( 8 bit)
PMC0W
0x23
8
read-write
n
0x0
0x0
PMC4B
Port mode control register 4 ( 8 bit)
PMC4W
0x24
8
read-write
n
0x0
0x0
PMC4H
Port mode control register 4 ( 16 bit)
PMC4W
0x24
16
read-write
n
0x0
0x0
PMC4W
Port mode control register 4 ( 32 bit)
0x24
32
read-write
n
0x0
0x0
PMC5B
Port mode control register 5 ( 8 bit)
PMC4W
0x25
8
read-write
n
0x0
0x0
PMC6B
Port mode control register 6 ( 8 bit)
PMC4W
0x26
8
read-write
n
0x0
0x0
PMC6H
Port mode control register 6 ( 16 bit)
PMC4W
0x26
16
read-write
n
0x0
0x0
PMC7B
Port mode control register 7 ( 8 bit)
PMC4W
0x27
8
read-write
n
0x0
0x0
HWOS
Hardware Real Time OS
HWOS
0x0
0x0
0x10000
registers
n
BUFDMA
Inter-buffer DMA transfer completion interrupt
32
HWRTOS
HW-RTOS interrupt
76
BRAMERR
Buffer RAM area access error interrupt
77
CMD
CPU I/F R7
0xF014
32
read-write
n
0x0
0x0
R0_
CPU I/F R0
0xF020
32
read-write
n
0x0
0x0
R1_
CPU I/F R1
0xF024
32
read-write
n
0x0
0x0
R4_
CPU I/F R4
0xF004
32
read-write
n
0x0
0x0
R5_
CPU I/F R5
0xF008
32
read-write
n
0x0
0x0
R6_
CPU I/F R6
0xF00C
32
read-write
n
0x0
0x0
R7_
CPU I/F R7
0xF010
32
read-write
n
0x0
0x0
SYSC
CPU I/F SYSC
0xF000
32
read-write
n
0x0
0x0
IIC0
IIC
IIC
0x0
0x0
0x100
registers
n
IICB0TIA
IICB0 data transmission/reception interrupt
14
IICB0TIS
IICB0 status interrupt
78
IICBnCTL0
Control Register 0
0x8
8
read-write
n
0x0
0x0
IICBnCTL1
Control Register 1
0x20
8
read-write
n
0x0
0x0
IICBnDAT
Data register
0x0
8
read-write
n
0x0
0x0
IICBnSTR0
Status Register 0
0x10
16
read-only
n
0x0
0x0
IICBnSTR1
Status Register 1
0x14
8
read-only
n
0x0
0x0
IICBnSTRC
Status clear register
0x18
8
read-write
n
0x0
0x0
IICBnSVA
Slave address register
0x4
8
read-write
n
0x0
0x0
IICBnTRG
Trigger register
0xC
8
read-write
n
0x0
0x0
IICBnWH
High level width setting register
0x28
16
read-write
n
0x0
0x0
IICBnWL
Low level width setting register
0x24
16
read-write
n
0x0
0x0
IIC1
IIC
IIC
0x0
0x0
0x100
registers
n
IICB1TIA
IICB1 data transmission/reception interrupt
15
IICB1TIS
IICB1 status interrupt
79
IICBnCTL0
Control Register 0
0x8
8
read-write
n
0x0
0x0
IICBnCTL1
Control Register 1
0x20
8
read-write
n
0x0
0x0
IICBnDAT
Data register
0x0
8
read-write
n
0x0
0x0
IICBnSTR0
Status Register 0
0x10
16
read-only
n
0x0
0x0
IICBnSTR1
Status Register 1
0x14
8
read-only
n
0x0
0x0
IICBnSTRC
Status clear register
0x18
8
read-write
n
0x0
0x0
IICBnSVA
Slave address register
0x4
8
read-write
n
0x0
0x0
IICBnTRG
Trigger register
0xC
8
read-write
n
0x0
0x0
IICBnWH
High level width setting register
0x28
16
read-write
n
0x0
0x0
IICBnWL
Low level width setting register
0x24
16
read-write
n
0x0
0x0
MEMC
Memory controller (ROM/SRAM)
MEMC
0x0
0x0
0x400
registers
n
BSC
Bus Size Control register
0x4
32
read-write
n
0x0
0x0
PRC
Page Rom Control register
0x18
32
read-write
n
0x0
0x0
SMC0
Static Memory Control register 0
0x8
32
read-write
n
0x0
0x0
SMC1
Static Memory Control register 1
0xC
32
read-write
n
0x0
0x0
SMC2
Static Memory Control register 2
0x10
32
read-write
n
0x0
0x0
SMC3
Static Memory Control register 3
0x14
32
read-write
n
0x0
0x0
PIC
Peripheral Inter Connection
PIC
0x0
0x0
0x100
registers
n
PICADTEN400
A/D Conversion Trigger Output Control Register 400
0x90
16
read-write
n
0x0
0x0
PICADTEN401
A/D Conversion Trigger Output Control Register 401
0x94
16
read-write
n
0x0
0x0
PICADTEN402
A/D Conversion Trigger Output Control Register 402
0x98
16
read-write
n
0x0
0x0
PICHIZCEN0
Hi-Z Output Control Register 0
0x80
8
read-write
n
0x0
0x0
PICREG200
Timmer I/O Control Register 200
0xC0
32
read-write
n
0x0
0x0
PICREG201
Timmer I/O Control Register 201
0xC4
32
read-write
n
0x0
0x0
PICREG202
Timmer I/O Control Register 202
0xC8
32
read-write
n
0x0
0x0
PICREG203
Timmer I/O Control Register 203
0xCC
32
read-write
n
0x0
0x0
PICSSER0
Concurrency Start Control Register 0
0x10
16
read-write
n
0x0
0x0
PICSSER2
Concurrency Start Control Register 2
0x18
16
read-write
n
0x0
0x0
PICSST
Concurrency Start Trigger Control Register
0x4
8
write-only
n
0x0
0x0
QINT_BUFID
Receive Buffer Information
QINT_BUFID
0x0
0x0
0x1000
registers
n
BUFID
BUFID
0x100
32
read-write
n
0x0
0x0
RTDCTL
DMA control
DMACCTL
0x0
0x0
0x24
registers
n
DCTRL
DMAC control register
0x0
32
read-write
n
0x0
0x0
DSCITVL
DMAC descriptor interval register
0x4
32
read-write
n
0x0
0x0
DSTEN
DMAC enable status register
0x10
32
read-only
n
0x0
0x0
DSTEND
DMAC end status register
0x18
32
read-only
n
0x0
0x0
DSTER
DMAC error status register
0x14
32
read-only
n
0x0
0x0
DSTSUS
DMAC suspend status register
0x20
32
read-only
n
0x0
0x0
DSTTC
DMAC terminal count status register
0x1C
32
read-only
n
0x0
0x0
RTDMAC
DMA controller
DMAC
0x0
0x0
0x40
registers
n
RTDMA
Real-time port DMAC transfer completion interrupt
26
DERR1
Real-time port DMAC error response interrupt
89
CHCFGn
Channel configulation register
0x2C
32
read-write
n
0x0
0x0
CHCTRLn
Channel control register
0x28
32
write-only
n
0x0
0x0
CHITVLn
Channel intereval register
0x30
32
read-write
n
0x0
0x0
CHSTATn
Channel status register
0x24
32
read-only
n
0x0
0x0
CRDAn
Destination address register [Current]
0x1C
32
read-only
n
0x0
0x0
CRLAn
Link address register [Current]
0x3C
32
read-only
n
0x0
0x0
CRSAn
Source address register [Current]
0x18
32
read-only
n
0x0
0x0
CRTBn
Transaction byte register [Current]
0x20
32
read-only
n
0x0
0x0
N0DAn
Destination address register [Next0]
0x4
32
read-write
n
0x0
0x0
N0SAn
Source address register [Next0]
0x0
32
read-write
n
0x0
0x0
N0TBn
Transaction byte register [Next0]
0x8
32
read-write
n
0x0
0x0
N1DAn
Destination address register [Next1]
0x10
32
read-write
n
0x0
0x0
N1SAn
Source address register [Next1]
0xC
32
read-write
n
0x0
0x0
N1TBn
Transaction byte register [Next1]
0x14
32
read-write
n
0x0
0x0
NXLAn
Link address register [Next]
0x38
32
read-write
n
0x0
0x0
RTDSS
DMAC space source size
DMACSS
0x0
0x0
0x20
registers
n
DCNTn
Continuous space destination size register
0x8
32
read-write
n
0x0
0x0
DSKPn
Skip space destination size register
0xC
32
read-write
n
0x0
0x0
SCNTn
Continuous space source size register
0x0
32
read-write
n
0x0
0x0
SSKPn
Skip space source size register
0x4
32
read-write
n
0x0
0x0
RTPORT
Port (RTPORT)
RTPORT
0x0
0x0
0x400
registers
n
RP0B
RT Port register 0 ( 8 bit)
RP0W
0x0
8
read-write
n
0x0
0x0
RP0H
RT Port register 0 ( 16 bit)
RP0W
0x0
16
read-write
n
0x0
0x0
RP0W
RT Port register 0 ( 32 bit)
0x0
32
read-write
n
0x0
0x0
RP1B
RT Port register 1 ( 8 bit)
RP0W
0x1
8
read-write
n
0x0
0x0
RP2B
RT Port register 2 ( 8 bit)
RP0W
0x2
8
read-write
n
0x0
0x0
RP2H
RT Port register 2 ( 16 bit)
RP0W
0x2
16
read-write
n
0x0
0x0
RP3B
RT Port register 3 ( 8 bit)
RP0W
0x3
8
read-write
n
0x0
0x0
RPFC0B
RT Port function control register 0 ( 8 bit)
RPFC0W
0x30
8
read-write
n
0x0
0x0
RPFC0H
RT Port function control register 0 ( 16 bit)
RPFC0W
0x30
16
read-write
n
0x0
0x0
RPFC0W
RT Port function control register 0 ( 32 bit)
0x30
32
read-write
n
0x0
0x0
RPFC1B
RT Port function control register 1 ( 8 bit)
RPFC0W
0x31
8
read-write
n
0x0
0x0
RPFC2B
RT Port function control register 2 ( 8 bit)
RPFC0W
0x32
8
read-write
n
0x0
0x0
RPFC2H
RT Port function control register 2 ( 16 bit)
RPFC0W
0x32
16
read-write
n
0x0
0x0
RPFC3B
RT Port function control register 3 ( 8 bit)
RPFC0W
0x33
8
read-write
n
0x0
0x0
RPFCE0B
RT Port function control ext.register 0 ( 8 bit)
RPFCE0W
0x40
8
read-write
n
0x0
0x0
RPFCE0H
RT Port function control ext.register 0 ( 16 bit)
RPFCE0W
0x40
16
read-write
n
0x0
0x0
RPFCE0W
RT Port function control ext.register 0 ( 32 bit)
0x40
32
read-write
n
0x0
0x0
RPFCE1B
RT Port function control ext.register 1 ( 8 bit)
RPFCE0W
0x41
8
read-write
n
0x0
0x0
RPFCE2B
RT Port function control ext.register 2 ( 8 bit)
RPFCE0W
0x42
8
read-write
n
0x0
0x0
RPFCE2H
RT Port function control ext.register 2 ( 16 bit)
RPFCE0W
0x42
16
read-write
n
0x0
0x0
RPFCE3B
RT Port function control ext.register 3 ( 8 bit)
RPFCE0W
0x43
8
read-write
n
0x0
0x0
RPIN0B
RT Port input level register 0 ( 8 bit)
RPIN0W
0x50
8
read-only
n
0x0
0x0
RPIN0H
RT Port input level register 0 ( 16 bit)
RPIN0W
0x50
16
read-only
n
0x0
0x0
RPIN0W
RT Port input level register 0 ( 32 bit)
0x50
32
read-only
n
0x0
0x0
RPIN1B
RT Port input level register 1 ( 8 bit)
RPIN0W
0x51
8
read-only
n
0x0
0x0
RPIN2B
RT Port input level register 2 ( 8 bit)
RPIN0W
0x52
8
read-only
n
0x0
0x0
RPIN2H
RT Port input level register 2 ( 16 bit)
RPIN0W
0x52
16
read-only
n
0x0
0x0
RPIN3B
RT Port input level register 3 ( 8 bit)
RPIN0W
0x53
8
read-only
n
0x0
0x0
RPM0B
RT Port mode register 0 ( 8 bit)
RPM0W
0x10
8
read-write
n
0x0
0x0
RPM0H
RT Port mode register 0 ( 16 bit)
RPM0W
0x10
16
read-write
n
0x0
0x0
RPM0W
RT Port mode register 0 ( 32 bit)
0x10
32
read-write
n
0x0
0x0
RPM1B
RT Port mode register 1 ( 8 bit)
RPM0W
0x11
8
read-write
n
0x0
0x0
RPM2B
RT Port mode register 2 ( 8 bit)
RPM0W
0x12
8
read-write
n
0x0
0x0
RPM2H
RT Port mode register 2 ( 16 bit)
RPM0W
0x12
16
read-write
n
0x0
0x0
RPM3B
RT Port mode register 3 ( 8 bit)
RPM0W
0x13
8
read-write
n
0x0
0x0
RPMC0B
RT Port mode control register 0 ( 8 bit)
RPMC0W
0x20
8
read-write
n
0x0
0x0
RPMC0H
RT Port mode control register 0 ( 16 bit)
RPMC0W
0x20
16
read-write
n
0x0
0x0
RPMC0W
RT Port mode control register 0 ( 32 bit)
0x20
32
read-write
n
0x0
0x0
RPMC1B
RT Port mode control register 1 ( 8 bit)
RPMC0W
0x21
8
read-write
n
0x0
0x0
RPMC2B
RT Port mode control register 2 ( 8 bit)
RPMC0W
0x22
8
read-write
n
0x0
0x0
RPMC2H
RT Port mode control register 2 ( 16 bit)
RPMC0W
0x22
16
read-write
n
0x0
0x0
RPMC3B
RT Port mode control register 3 ( 8 bit)
RPMC0W
0x23
8
read-write
n
0x0
0x0
SMC
Burst memory controller
SMC
0x0
0x0
0x200
registers
n
DIRECT_CMD
Direct Command Register
0x10
32
write-only
n
0x0
0x0
OPMODE0_0
CS0 mode register
0x104
32
read-only
n
0x0
0x0
OPMODE0_1
CS1 mode register
0x124
32
read-only
n
0x0
0x0
OPMODE0_2
CS2 mode register
0x144
32
read-only
n
0x0
0x0
OPMODE0_3
CS3 mode register
0x164
32
read-only
n
0x0
0x0
REF_PERIOD0
Refresh Period 0 Register
0x20
32
read-write
n
0x0
0x0
SET_CYCLES
Set Cycles Register
0x14
32
write-only
n
0x0
0x0
SET_OPMODE
Set Operating Mode Register
0x18
32
write-only
n
0x0
0x0
SRAM_CYCLES0_0
CS0 cycle setting register
0x100
32
read-only
n
0x0
0x0
SRAM_CYCLES0_1
CS1 cycle setting register
0x120
32
read-only
n
0x0
0x0
SRAM_CYCLES0_2
CS2 cycle setting register
0x140
32
read-only
n
0x0
0x0
SRAM_CYCLES0_3
CS3 cycle setting register
0x160
32
read-only
n
0x0
0x0
SROM
Serial flash ROM memory controller
SROM
0x0
0x0
0x100
registers
n
SFLASH
Serial flash ROM controller error interrupt
81
SFMCMD
Communication mode control register
0x14
32
read-write
n
0x0
0x0
SFMCOM
Communication port register
0x10
32
read-write
n
0x0
0x0
SFMCST
Communication status register
0x18
32
read-write
n
0x0
0x0
SFMDTC
Data Input Timing register
0x38
32
read-write
n
0x0
0x0
SFMPMD
Port mode control register
0x34
32
read-write
n
0x0
0x0
SFMSAC
Address mode control register
0x24
32
read-write
n
0x0
0x0
SFMSDC
Dummy Cycle control register
0x28
32
read-write
n
0x0
0x0
SFMSIC
Command code register
0x20
32
read-write
n
0x0
0x0
SFMSKC
Clock control register
0x8
32
read-write
n
0x0
0x0
SFMSMD
Transfer mode control register
0x0
32
read-write
n
0x0
0x0
SFMSPC
SPI Protocol control register
0x30
32
read-write
n
0x0
0x0
SFMSSC
Chip select control register
0x4
32
read-write
n
0x0
0x0
SFMSST
Status register
0xC
32
read-only
n
0x0
0x0
SFMVER
Version register
0x4C
32
read-write
n
0x0
0x0
SYS
System
SYS
0x0
0x0
0x10000
registers
n
BCLKSEL
BUSCLK devide
0x120
32
read-write
n
0x0
0x0
CCRES
CC-Link reset register
0x814
32
read-write
n
0x0
0x0
CCSINTMD
CC-Link slave REFSTB interrupt detection mode
0x824
32
read-write
n
0x0
0x0
CCSMD
CC-Link mode register
0x818
32
read-write
n
0x0
0x0
CCSMON
CC-Link slave monitor
0x80C
32
read-only
n
0x0
0x0
CCSREFMON
CC-Link slave REFSTB monitor
0x828
32
read-write
n
0x0
0x0
CCSRUN
CC-Link slave RUN LED control
0x810
32
read-write
n
0x0
0x0
CIECLKGTD
CC-Link IE Clock Gate register
0x938
32
read-write
n
0x0
0x0
CLKGTD0
Clock control 0
0x1A0
32
read-write
n
0x0
0x0
CLKGTD1
Clock control 1
0x1A4
32
read-write
n
0x0
0x0
CPURESET
CPU reset
0x210
32
read-write
n
0x0
0x0
DMAIFC0
DMA transfer interface signal 0
0x720
32
read-write
n
0x0
0x0
DMAIFC1
DMA transfer interface signal 1
0x724
32
read-write
n
0x0
0x0
DRCTLEXTP0H
EXT Port 0 buffer select Hi
0x284
32
read-write
n
0x0
0x0
DRCTLEXTP0L
EXT Port 0 buffer select Lo
0x280
32
read-write
n
0x0
0x0
DRCTLEXTP1L
EXT Port 1 buffer select Lo
0x288
32
read-write
n
0x0
0x0
DRCTLP0H
Port 0 buffer select Hi
0x224
32
read-write
n
0x0
0x0
DRCTLP0L
Port 0 buffer select Lo
0x220
32
read-write
n
0x0
0x0
DRCTLP1H
Port 1 buffer select Hi
0x22C
32
read-write
n
0x0
0x0
DRCTLP1L
Port 1 buffer select Lo
0x228
32
read-write
n
0x0
0x0
DRCTLP2H
Port 2 buffer select Hi
0x234
32
read-write
n
0x0
0x0
DRCTLP2L
Port 2 buffer select Lo
0x230
32
read-write
n
0x0
0x0
DRCTLP3H
Port 3 buffer select Hi
0x23C
32
read-write
n
0x0
0x0
DRCTLP3L
Port 3 buffer select Lo
0x238
32
read-write
n
0x0
0x0
DRCTLP4H
Port 4 buffer select Hi
0x244
32
read-write
n
0x0
0x0
DRCTLP4L
Port 4 buffer select Lo
0x240
32
read-write
n
0x0
0x0
DRCTLP5H
Port 5 buffer select Hi
0x24C
32
read-write
n
0x0
0x0
DRCTLP5L
Port 5 buffer select Lo
0x248
32
read-write
n
0x0
0x0
DRCTLP6H
Port 6 buffer select Hi
0x254
32
read-write
n
0x0
0x0
DRCTLP6L
Port 6 buffer select Lo
0x250
32
read-write
n
0x0
0x0
DRCTLP7H
Port 7 buffer select Hi
0x25C
32
read-write
n
0x0
0x0
DRCTLP7L
Port 7 buffer select Lo
0x258
32
read-write
n
0x0
0x0
DRCTLRP0H
Realtime Port n buffer select Hi
0x264
32
read-write
n
0x0
0x0
DRCTLRP0L
Realtime Port n buffer select Lo
0x260
32
read-write
n
0x0
0x0
DRCTLRP1H
Realtime Port n buffer select Hi
0x26C
32
read-write
n
0x0
0x0
DRCTLRP1L
Realtime Port n buffer select Lo
0x268
32
read-write
n
0x0
0x0
DRCTLRP2H
Realtime Port n buffer select Hi
0x274
32
read-write
n
0x0
0x0
DRCTLRP2L
Realtime Port n buffer select Lo
0x270
32
read-write
n
0x0
0x0
DRCTLRP3H
Realtime Port n buffer select Hi
0x27C
32
read-write
n
0x0
0x0
DRCTLRP3L
Realtime Port n buffer select Lo
0x278
32
read-write
n
0x0
0x0
DTFR0
DMA trigger factor n
0x730
32
read-write
n
0x0
0x0
DTFR1
DMA trigger factor n
0x734
32
read-write
n
0x0
0x0
DTFR2
DMA trigger factor n
0x738
32
read-write
n
0x0
0x0
DTFR3
DMA trigger factor n
0x73C
32
read-write
n
0x0
0x0
ERRDETSEL0
Error detection signal select 0
0x1268
32
read-write
n
0x0
0x0
ERRDETSEL1
Error detection signal select 1
0x126C
32
read-write
n
0x0
0x0
ETHSWMD
EtherSW mode control
0x684
32
read-write
n
0x0
0x0
ETHSWMTC
EtherSW management TAG
0x680
32
read-write
n
0x0
0x0
IDCODE
ID code register
0x4
32
read-only
n
0x0
0x0
INTM0
External interrupt mode 0
0x710
32
read-write
n
0x0
0x0
INTM1
External interrupt mode 1
0x714
32
read-write
n
0x0
0x0
INTM2
External interrupt mode 2
0x718
32
read-write
n
0x0
0x0
INTSEL
INTPZ/Timer interrupt select
0x1244
32
read-write
n
0x0
0x0
MACSEL
MAC select
0x600
32
read-write
n
0x0
0x0
MDCCFG
MDC clock select
0x604
32
read-write
n
0x0
0x0
MDIOSEL
GMII/MII management I/F select
0xE00
32
read-write
n
0x0
0x0
MDMNT
Mode monitor register
0x0
32
read-only
n
0x0
0x0
NFC0
Noise filter control n
0x700
32
read-write
n
0x0
0x0
NFC1
Noise filter control n
0x704
32
read-write
n
0x0
0x0
NFC2
Noise filter control n
0x708
32
read-write
n
0x0
0x0
NFC3
Noise filter control n
0x70C
32
read-write
n
0x0
0x0
NFC4
Noise filter control 4
0x1250
32
read-write
n
0x0
0x0
PHYRST
PHY reset
0x1220
32
read-write
n
0x0
0x0
PHYRSTCH
PHY reset select
0x1224
32
read-write
n
0x0
0x0
RINVER
Version register
0x8
32
read-only
n
0x0
0x0
RP0TFR
Trigger sync port factor n
0xA30
32
read-write
n
0x0
0x0
RP1TFR
Trigger sync port factor n
0xA34
32
read-write
n
0x0
0x0
RP2TFR
Trigger sync port factor n
0xA38
32
read-write
n
0x0
0x0
RP3TFR
Trigger sync port factor n
0xA3C
32
read-write
n
0x0
0x0
RPTRGMD
Trigger sync port control
0xA00
32
read-write
n
0x0
0x0
RTDMAIFC
DMA transfer interface signal RT
0x728
32
read-write
n
0x0
0x0
RTDTFR
DMA trigger factor RT
0x740
32
read-write
n
0x0
0x0
RTOS_SOFTRST
HW-RTOS reset register
0x400
32
read-write
n
0x0
0x0
SCRATCH0
Scratch n
0x900
32
read-write
n
0x0
0x0
SCRATCH1
Scratch n
0x904
32
read-write
n
0x0
0x0
SCRATCH2
Scratch n
0x908
32
read-write
n
0x0
0x0
SCRATCH3
Scratch n
0x90C
32
read-write
n
0x0
0x0
SCRATCH4
Scratch n
0x910
32
read-write
n
0x0
0x0
SCRATCH5
Scratch n
0x914
32
read-write
n
0x0
0x0
SCRATCH6
Scratch n
0x918
32
read-write
n
0x0
0x0
SCRATCH7
Scratch n
0x91C
32
read-write
n
0x0
0x0
SCRATCH8
Scratch n
0x920
32
read-write
n
0x0
0x0
SCRATCH9
Scratch n
0x924
32
read-write
n
0x0
0x0
SCRATCHA
Scratch n
0x928
32
read-write
n
0x0
0x0
SCRATCHB
Scratch n
0x92C
32
read-write
n
0x0
0x0
SCRATCHC
Scratch n
0x930
32
read-write
n
0x0
0x0
SELCNT
Timer input select
0x500
32
read-write
n
0x0
0x0
SELCNTD
Timer input select (TAUD)
0x504
32
read-write
n
0x0
0x0
SMADSEL0
External memory I/F select 0
0x110
32
read-write
n
0x0
0x0
SMADSEL1
External memory I/F select 1
0x114
32
read-write
n
0x0
0x0
SMADSEL2
External memory I/F select 2
0x118
32
read-write
n
0x0
0x0
SMADSEL3
External memory I/F select 3
0x11C
32
read-write
n
0x0
0x0
SMC352MD
SMC mode
0x124
32
read-write
n
0x0
0x0
SMCBUFMD
SMC352 buffer control
0x128
32
read-write
n
0x0
0x0
SRAMBRSEL
SRAM bridge select
0x804
32
read-write
n
0x0
0x0
STOP_TOUTD
TOUTD output control
0x1260
32
read-write
n
0x0
0x0
SWTMEN
Ether switch timer output control
0x1100
32
read-write
n
0x0
0x0
SWTMLATNS
Ether switch timer latch setting (ns)
0x1144
32
read-write
n
0x0
0x0
SWTMLATSEC
Ether switch timer latch setting (sec)
0x1140
32
read-write
n
0x0
0x0
SWTMMAXPH
Ether switch timer max count setting 1
0x1138
32
read-write
n
0x0
0x0
SWTMMAXPL
Ether switch timer max count setting 0
0x1134
32
read-write
n
0x0
0x0
SWTMPNSH
Ether switch timer period setting (ns) 1
0x112C
32
read-write
n
0x0
0x0
SWTMPNSL
Ether switch timer period setting (ns) 0
0x1128
32
read-write
n
0x0
0x0
SWTMPSECH
Ether switch timer period setting (sec) 1
0x1124
32
read-write
n
0x0
0x0
SWTMPSECL
Ether switch timer period setting (sec) 0
0x1120
32
read-write
n
0x0
0x0
SWTMSTNSH
Ether switch timer start setting (ns) 1
0x111C
32
read-write
n
0x0
0x0
SWTMSTNSL
Ether switch timer start setting (ns) 0
0x1118
32
read-write
n
0x0
0x0
SWTMSTSECH
Ether switch timer start setting (sec) 1
0x1114
32
read-write
n
0x0
0x0
SWTMSTSECL
Ether switch timer start setting (sec) 0
0x1110
32
read-write
n
0x0
0x0
SWTMWTH
Ether switch timer pulse width setting
0x1130
32
read-write
n
0x0
0x0
SYSPCMD
System protect command
0x300
32
read-write
n
0x0
0x0
SYSRESET
System reset register
0x1C0
16
read-write
n
0x0
0x0
TMDTFR0
Timer trigger factor m (TAUD)
0xD00
32
read-write
n
0x0
0x0
TMDTFR1
Timer trigger factor m (TAUD)
0xD04
32
read-write
n
0x0
0x0
TMDTFR2
Timer trigger factor m (TAUD)
0xD08
32
read-write
n
0x0
0x0
TMDTFR3
Timer trigger factor m (TAUD)
0xD0C
32
read-write
n
0x0
0x0
TMDTFR4
Timer trigger factor m (TAUD)
0xD10
32
read-write
n
0x0
0x0
TMDTFR5
Timer trigger factor m (TAUD)
0xD14
32
read-write
n
0x0
0x0
TMDTFR6
Timer trigger factor m (TAUD)
0xD18
32
read-write
n
0x0
0x0
TMDTFR7
Timer trigger factor m (TAUD)
0xD1C
32
read-write
n
0x0
0x0
TMISEL
Timer I/F select
0x1240
32
read-write
n
0x0
0x0
TMTFR0
Timer trigger factor n
0x530
32
read-write
n
0x0
0x0
TMTFR1
Timer trigger factor n
0x534
32
read-write
n
0x0
0x0
TMTFR2
Timer trigger factor n
0x538
32
read-write
n
0x0
0x0
TMTFR3
Timer trigger factor n
0x53C
32
read-write
n
0x0
0x0
TOUTD_SEL
TOUTD output select
0x1264
32
read-write
n
0x0
0x0
WAITZSEL
WAITZ select
0x108
32
read-write
n
0x0
0x0
WDTCLKCFG
WDT input clock selection register
0x180
32
read-write
n
0x0
0x0
WDTISEL
WDT input filter select
0x1230
32
read-write
n
0x0
0x0
WREN
Write enable register
0x100
32
read-write
n
0x0
0x0
TAPA
motor control unit
TAPA
0x0
0x0
0x40
registers
n
INTPZ22
INTPZ22 input / peak interrupt (TAPA)
69
INTPZ23
INTPZ23 input / trough interrupt (TAPA)
70
TAPAACTS
Asynchronous Hi-Z Stop Trigger Register
0x8
8
write-only
n
0x0
0x0
TAPAACTT
Asynchronous Hi-Z Stop Trigger Register
0xC
8
write-only
n
0x0
0x0
TAPAACWE
Asynchronous Hi-Z Start Trigger Register
0x4
8
read-write
n
0x0
0x0
TAPACTL1
Control Register 1
0x24
8
read-write
n
0x0
0x0
TAPACTLO
Control Register 0
0x20
16
read-write
n
0x0
0x0
TAPAEMU
Emulation Register
0x28
8
read-write
n
0x0
0x0
TAPAFLG
TAPA FLAG Register
0x0
16
read-only
n
0x0
0x0
TAPAOPHS
Hi-Z Start Trigger Register
0x14
8
write-only
n
0x0
0x0
TAPAOPHT
Hi-Z Stop Trigger Register
0x18
8
write-only
n
0x0
0x0
TAUD
Timer Array Unit D
TAUD
0x0
0x0
0x400
registers
n
TAUDI0
TAUD channel 0 interrupt
27
TAUDI1
TAUD channel 1 interrupt
28
TAUDI2
TAUD channel 2 interrupt
29
TAUDI3
TAUD channel 3 interrupt
30
TAUDI4
TAUD channel 4 interrupt
31
INTPZ11
INTPZ11 input / TAUD channel 5 interrupt
58
INTPZ12
INTPZ12 input / TAUD channel 6 interrupt
59
INTPZ13
INTPZ13 input / TAUD channel 7 interrupt
60
INTPZ14
INTPZ14 input / TAUD channel 8 interrupt
61
INTPZ15
INTPZ15 input / TAUD channel 9 interrupt
62
INTPZ16
INTPZ16 input / TAUD channel 10 interrupt
63
INTPZ17
INTPZ17 input / TAUD channel 11 interrupt
64
INTPZ18
INTPZ18 input / TAUD channel 12 interrupt
65
INTPZ19
INTPZ19 input / TAUD channel 13 interrupt
66
INTPZ20
INTPZ20 input / TAUD channel 14 interrupt
67
INTPZ21
INTPZ21 input / TAUD channel 15 interrupt
68
TAUDBRS
Prescaler Baudrate setting Register
0x244
8
read-write
n
0x0
0x0
TAUDCDR0
Channel Data Register m
0x0
16
read-write
n
0x0
0x0
TAUDCDR1
Channel Data Register m
0x4
16
read-write
n
0x0
0x0
TAUDCDR10
Channel Data Register m
0x28
16
read-write
n
0x0
0x0
TAUDCDR11
Channel Data Register m
0x2C
16
read-write
n
0x0
0x0
TAUDCDR12
Channel Data Register m
0x30
16
read-write
n
0x0
0x0
TAUDCDR13
Channel Data Register m
0x34
16
read-write
n
0x0
0x0
TAUDCDR14
Channel Data Register m
0x38
16
read-write
n
0x0
0x0
TAUDCDR15
Channel Data Register m
0x3C
16
read-write
n
0x0
0x0
TAUDCDR2
Channel Data Register m
0x8
16
read-write
n
0x0
0x0
TAUDCDR3
Channel Data Register m
0xC
16
read-write
n
0x0
0x0
TAUDCDR4
Channel Data Register m
0x10
16
read-write
n
0x0
0x0
TAUDCDR5
Channel Data Register m
0x14
16
read-write
n
0x0
0x0
TAUDCDR6
Channel Data Register m
0x18
16
read-write
n
0x0
0x0
TAUDCDR7
Channel Data Register m
0x1C
16
read-write
n
0x0
0x0
TAUDCDR8
Channel Data Register m
0x20
16
read-write
n
0x0
0x0
TAUDCDR9
Channel Data Register m
0x24
16
read-write
n
0x0
0x0
TAUDCMOR0
Channel Mode OS Register m
0x200
16
read-write
n
0x0
0x0
TAUDCMOR1
Channel Mode OS Register m
0x204
16
read-write
n
0x0
0x0
TAUDCMOR10
Channel Mode OS Register m
0x228
16
read-write
n
0x0
0x0
TAUDCMOR11
Channel Mode OS Register m
0x22C
16
read-write
n
0x0
0x0
TAUDCMOR12
Channel Mode OS Register m
0x230
16
read-write
n
0x0
0x0
TAUDCMOR13
Channel Mode OS Register m
0x234
16
read-write
n
0x0
0x0
TAUDCMOR14
Channel Mode OS Register m
0x238
16
read-write
n
0x0
0x0
TAUDCMOR15
Channel Mode OS Register m
0x23C
16
read-write
n
0x0
0x0
TAUDCMOR2
Channel Mode OS Register m
0x208
16
read-write
n
0x0
0x0
TAUDCMOR3
Channel Mode OS Register m
0x20C
16
read-write
n
0x0
0x0
TAUDCMOR4
Channel Mode OS Register m
0x210
16
read-write
n
0x0
0x0
TAUDCMOR5
Channel Mode OS Register m
0x214
16
read-write
n
0x0
0x0
TAUDCMOR6
Channel Mode OS Register m
0x218
16
read-write
n
0x0
0x0
TAUDCMOR7
Channel Mode OS Register m
0x21C
16
read-write
n
0x0
0x0
TAUDCMOR8
Channel Mode OS Register m
0x220
16
read-write
n
0x0
0x0
TAUDCMOR9
Channel Mode OS Register m
0x224
16
read-write
n
0x0
0x0
TAUDCMUR0
Channel Mode User Register m
0xC0
8
read-write
n
0x0
0x0
TAUDCMUR1
Channel Mode User Register m
0xC4
8
read-write
n
0x0
0x0
TAUDCMUR10
Channel Mode User Register m
0xE8
8
read-write
n
0x0
0x0
TAUDCMUR11
Channel Mode User Register m
0xEC
8
read-write
n
0x0
0x0
TAUDCMUR12
Channel Mode User Register m
0xF0
8
read-write
n
0x0
0x0
TAUDCMUR13
Channel Mode User Register m
0xF4
8
read-write
n
0x0
0x0
TAUDCMUR14
Channel Mode User Register m
0xF8
8
read-write
n
0x0
0x0
TAUDCMUR15
Channel Mode User Register m
0xFC
8
read-write
n
0x0
0x0
TAUDCMUR2
Channel Mode User Register m
0xC8
8
read-write
n
0x0
0x0
TAUDCMUR3
Channel Mode User Register m
0xCC
8
read-write
n
0x0
0x0
TAUDCMUR4
Channel Mode User Register m
0xD0
8
read-write
n
0x0
0x0
TAUDCMUR5
Channel Mode User Register m
0xD4
8
read-write
n
0x0
0x0
TAUDCMUR6
Channel Mode User Register m
0xD8
8
read-write
n
0x0
0x0
TAUDCMUR7
Channel Mode User Register m
0xDC
8
read-write
n
0x0
0x0
TAUDCMUR8
Channel Mode User Register m
0xE0
8
read-write
n
0x0
0x0
TAUDCMUR9
Channel Mode User Register m
0xE4
8
read-write
n
0x0
0x0
TAUDCNT0
Channel Counter Register m
0x80
16
read-only
n
0x0
0x0
TAUDCNT1
Channel Counter Register m
0x84
16
read-only
n
0x0
0x0
TAUDCNT10
Channel Counter Register m
0xA8
16
read-only
n
0x0
0x0
TAUDCNT11
Channel Counter Register m
0xAC
16
read-only
n
0x0
0x0
TAUDCNT12
Channel Counter Register m
0xB0
16
read-only
n
0x0
0x0
TAUDCNT13
Channel Counter Register m
0xB4
16
read-only
n
0x0
0x0
TAUDCNT14
Channel Counter Register m
0xB8
16
read-only
n
0x0
0x0
TAUDCNT15
Channel Counter Register m
0xBC
16
read-only
n
0x0
0x0
TAUDCNT2
Channel Counter Register m
0x88
16
read-only
n
0x0
0x0
TAUDCNT3
Channel Counter Register m
0x8C
16
read-only
n
0x0
0x0
TAUDCNT4
Channel Counter Register m
0x90
16
read-only
n
0x0
0x0
TAUDCNT5
Channel Counter Register m
0x94
16
read-only
n
0x0
0x0
TAUDCNT6
Channel Counter Register m
0x98
16
read-only
n
0x0
0x0
TAUDCNT7
Channel Counter Register m
0x9C
16
read-only
n
0x0
0x0
TAUDCNT8
Channel Counter Register m
0xA0
16
read-only
n
0x0
0x0
TAUDCNT9
Channel Counter Register m
0xA4
16
read-only
n
0x0
0x0
TAUDCSC0
Channel Status Clear Trigger Register m
0x180
8
write-only
n
0x0
0x0
TAUDCSC1
Channel Status Clear Trigger Register m
0x184
8
write-only
n
0x0
0x0
TAUDCSC10
Channel Status Clear Trigger Register m
0x1A8
8
write-only
n
0x0
0x0
TAUDCSC11
Channel Status Clear Trigger Register m
0x1AC
8
write-only
n
0x0
0x0
TAUDCSC12
Channel Status Clear Trigger Register m
0x1B0
8
write-only
n
0x0
0x0
TAUDCSC13
Channel Status Clear Trigger Register m
0x1B4
8
write-only
n
0x0
0x0
TAUDCSC14
Channel Status Clear Trigger Register m
0x1B8
8
write-only
n
0x0
0x0
TAUDCSC15
Channel Status Clear Trigger Register m
0x1BC
8
write-only
n
0x0
0x0
TAUDCSC2
Channel Status Clear Trigger Register m
0x188
8
write-only
n
0x0
0x0
TAUDCSC3
Channel Status Clear Trigger Register m
0x18C
8
write-only
n
0x0
0x0
TAUDCSC4
Channel Status Clear Trigger Register m
0x190
8
write-only
n
0x0
0x0
TAUDCSC5
Channel Status Clear Trigger Register m
0x194
8
write-only
n
0x0
0x0
TAUDCSC6
Channel Status Clear Trigger Register m
0x198
8
write-only
n
0x0
0x0
TAUDCSC7
Channel Status Clear Trigger Register m
0x19C
8
write-only
n
0x0
0x0
TAUDCSC8
Channel Status Clear Trigger Register m
0x1A0
8
write-only
n
0x0
0x0
TAUDCSC9
Channel Status Clear Trigger Register m
0x1A4
8
write-only
n
0x0
0x0
TAUDCSR0
Channel Status Register m
0x140
8
read-only
n
0x0
0x0
TAUDCSR1
Channel Status Register m
0x144
8
read-only
n
0x0
0x0
TAUDCSR10
Channel Status Register m
0x168
8
read-only
n
0x0
0x0
TAUDCSR11
Channel Status Register m
0x16C
8
read-only
n
0x0
0x0
TAUDCSR12
Channel Status Register m
0x170
8
read-only
n
0x0
0x0
TAUDCSR13
Channel Status Register m
0x174
8
read-only
n
0x0
0x0
TAUDCSR14
Channel Status Register m
0x178
8
read-only
n
0x0
0x0
TAUDCSR15
Channel Status Register m
0x17C
8
read-only
n
0x0
0x0
TAUDCSR2
Channel Status Register m
0x148
8
read-only
n
0x0
0x0
TAUDCSR3
Channel Status Register m
0x14C
8
read-only
n
0x0
0x0
TAUDCSR4
Channel Status Register m
0x150
8
read-only
n
0x0
0x0
TAUDCSR5
Channel Status Register m
0x154
8
read-only
n
0x0
0x0
TAUDCSR6
Channel Status Register m
0x158
8
read-only
n
0x0
0x0
TAUDCSR7
Channel Status Register m
0x15C
8
read-only
n
0x0
0x0
TAUDCSR8
Channel Status Register m
0x160
8
read-only
n
0x0
0x0
TAUDCSR9
Channel Status Register m
0x164
8
read-only
n
0x0
0x0
TAUDEMU
Emulation Register
0x290
8
read-write
n
0x0
0x0
TAUDRDC
Channel Reload data Control Register
0x26C
16
read-write
n
0x0
0x0
TAUDRDE
Channel Reload data Authorized Register
0x260
16
read-write
n
0x0
0x0
TAUDRDM
Channel Reload data Mode Register
0x264
16
read-write
n
0x0
0x0
TAUDRDS
Channel Reload data Control CH Selected Register
0x268
16
read-write
n
0x0
0x0
TAUDRDT
Channel Reload data Trigger Register
0x44
16
write-only
n
0x0
0x0
TAUDRSF
Channel Reload Status Register
0x48
16
read-only
n
0x0
0x0
TAUDTDE
Channel Dead Time Output Authorized Register
0x250
16
read-write
n
0x0
0x0
TAUDTDL
Channel Dead Time Output Level Register
0x54
16
read-write
n
0x0
0x0
TAUDTDM
Channel Dead Time Output Mode Register
0x254
16
read-write
n
0x0
0x0
TAUDTE
Channel Authorized Status Register
0x1C0
16
read-only
n
0x0
0x0
TAUDTME
Channel Modulation Output Authorized Register
0x50
16
read-write
n
0x0
0x0
TAUDTO
Channel Output Register
0x58
16
read-write
n
0x0
0x0
TAUDTOC
Channel Output Configuration Register
0x24C
16
read-write
n
0x0
0x0
TAUDTOE
Channel Output Authorized Register
0x5C
16
read-write
n
0x0
0x0
TAUDTOL
Channel Output Active Level Register
0x40
16
read-write
n
0x0
0x0
TAUDTOM
Channel Output Mode Register
0x248
16
read-write
n
0x0
0x0
TAUDTPS
Prescaler Clock Selected Register
0x240
16
read-write
n
0x0
0x0
TAUDTRC
Channel Real Time Output Control Register
0x25C
16
read-write
n
0x0
0x0
TAUDTRE
Channel Real Time Output Authorized Register
0x258
16
read-write
n
0x0
0x0
TAUDTRO
Channel Real Time Output Register
0x4C
16
read-write
n
0x0
0x0
TAUDTS
Channel Start Trigger Register
0x1C4
16
write-only
n
0x0
0x0
TAUDTT
Channel Stop Trigger Register
0x1C8
16
write-only
n
0x0
0x0
TAUJ2
Timer array unit(TAUJ2)
Timer0
0x0
0x0
0x100
registers
n
TAUJ2I0
TAUJ2 channel 0 interrupt
0
TAUJ2I1
TAUJ2 channel 1 interrupt
1
TAUJ2I2
TAUJ2 channel 2 interrupt
2
TAUJ2I3
TAUJ2 channel 3 interrupt
3
TAUJ2BRS
prescaler baud rate setting register
0x94
8
read-write
n
0x0
0x0
TAUJ2CDR0
channel data register m
0x0
32
read-write
n
0x0
0x0
TAUJ2CDR1
channel data register m
0x4
32
read-write
n
0x0
0x0
TAUJ2CDR2
channel data register m
0x8
32
read-write
n
0x0
0x0
TAUJ2CDR3
channel data register m
0xC
32
read-write
n
0x0
0x0
TAUJ2CMOR0
channel mode OS register m
0x80
16
read-write
n
0x0
0x0
TAUJ2CMOR1
channel mode OS register m
0x84
16
read-write
n
0x0
0x0
TAUJ2CMOR2
channel mode OS register m
0x88
16
read-write
n
0x0
0x0
TAUJ2CMOR3
channel mode OS register m
0x8C
16
read-write
n
0x0
0x0
TAUJ2CMUR0
channel mode user register m
0x20
8
read-write
n
0x0
0x0
TAUJ2CMUR1
channel mode user register m
0x24
8
read-write
n
0x0
0x0
TAUJ2CMUR2
channel mode user register m
0x28
8
read-write
n
0x0
0x0
TAUJ2CMUR3
channel mode user register m
0x2C
8
read-write
n
0x0
0x0
TAUJ2CNT0
channel counter register m
0x10
32
read-only
n
0x0
0x0
TAUJ2CNT1
channel counter register m
0x14
32
read-only
n
0x0
0x0
TAUJ2CNT2
channel counter register m
0x18
32
read-only
n
0x0
0x0
TAUJ2CNT3
channel counter register m
0x1C
32
read-only
n
0x0
0x0
TAUJ2CSC0
channel status clear trigger register m
0x40
8
write-only
n
0x0
0x0
TAUJ2CSC1
channel status clear trigger register m
0x44
8
write-only
n
0x0
0x0
TAUJ2CSC2
channel status clear trigger register m
0x48
8
write-only
n
0x0
0x0
TAUJ2CSC3
channel status clear trigger register m
0x4C
8
write-only
n
0x0
0x0
TAUJ2CSR0
channel status register m
0x30
8
read-only
n
0x0
0x0
TAUJ2CSR1
channel status register m
0x34
8
read-only
n
0x0
0x0
TAUJ2CSR2
channel status register m
0x38
8
read-only
n
0x0
0x0
TAUJ2CSR3
channel status register m
0x3C
8
read-only
n
0x0
0x0
TAUJ2RDE
channel reload data enable register
0xA0
8
read-write
n
0x0
0x0
TAUJ2RDM
channel reload data mode register
0xA4
8
read-write
n
0x0
0x0
TAUJ2RDT
channel reload data trigger register
0x68
8
write-only
n
0x0
0x0
TAUJ2RSF
channel reload status register
0x6C
8
read-only
n
0x0
0x0
TAUJ2TE
channel enable status register
0x50
8
read-only
n
0x0
0x0
TAUJ2TO
channel output register
0x5C
8
read-write
n
0x0
0x0
TAUJ2TOC
channel output configuration register
0x9C
8
read-write
n
0x0
0x0
TAUJ2TOE
channel output enable register
0x60
8
read-write
n
0x0
0x0
TAUJ2TOL
channel output active level register
0x64
8
read-write
n
0x0
0x0
TAUJ2TOM
channel output mode register
0x98
8
read-write
n
0x0
0x0
TAUJ2TPS
prescaler clock select register
0x90
16
read-write
n
0x0
0x0
TAUJ2TS
channel start trigger register
0x54
8
write-only
n
0x0
0x0
TAUJ2TT
channel stop trigger register
0x58
8
write-only
n
0x0
0x0
UART0
UART
UART
0x0
0x0
0x100
registers
n
UAJ0TIT
UARTJ0 transmission interrupt
4
UAJ0TIR
UARTJ0 reception interrupt
5
UAJ0TIS
UARTJ0 status interrupt
82
URTJnCTL0
Control Register 0
0x0
32
read-write
n
0x0
0x0
URTJnCTL1
Control Register 1
0x20
32
read-write
n
0x0
0x0
URTJnCTL2
Control Register 2
0x24
32
read-write
n
0x0
0x0
URTJnFCTL0
FIFO Control Register 0
0x80
32
read-write
n
0x0
0x0
URTJnFCTL1
FIFO Control Register 1
0xA0
32
read-write
n
0x0
0x0
URTJnFRX
FIFO Recieve Data Register
0x90
32
read-only
n
0x0
0x0
URTJnFSTC
FIFO Status Clear Register
0x8C
32
read-write
n
0x0
0x0
URTJnFSTR0
FIFO Status Register 0
0x84
32
read-only
n
0x0
0x0
URTJnFSTR1
FIFO Status Register 1
0x88
32
read-only
n
0x0
0x0
URTJnFTX
FIFO Transmit Data Register
0x94
8
read-write
n
0x0
0x0
URTJnSTC
Status Clear Register
0x10
32
read-write
n
0x0
0x0
URTJnSTR0
Status Register 0
0x8
32
read-only
n
0x0
0x0
URTJnSTR1
Status Register 1
0xC
32
read-only
n
0x0
0x0
URTJnTRG
Triger Register
0x4
32
read-write
n
0x0
0x0
UART1
UART
UART
0x0
0x0
0x100
registers
n
UAJ1TIT
UARTJ1 transmission interrupt
6
UAJ1TIR
UARTJ1 reception interrupt
7
UAJ1TIS
UARTJ1 status interrupt
83
URTJnCTL0
Control Register 0
0x0
32
read-write
n
0x0
0x0
URTJnCTL1
Control Register 1
0x20
32
read-write
n
0x0
0x0
URTJnCTL2
Control Register 2
0x24
32
read-write
n
0x0
0x0
URTJnFCTL0
FIFO Control Register 0
0x80
32
read-write
n
0x0
0x0
URTJnFCTL1
FIFO Control Register 1
0xA0
32
read-write
n
0x0
0x0
URTJnFRX
FIFO Recieve Data Register
0x90
32
read-only
n
0x0
0x0
URTJnFSTC
FIFO Status Clear Register
0x8C
32
read-write
n
0x0
0x0
URTJnFSTR0
FIFO Status Register 0
0x84
32
read-only
n
0x0
0x0
URTJnFSTR1
FIFO Status Register 1
0x88
32
read-only
n
0x0
0x0
URTJnFTX
FIFO Transmit Data Register
0x94
8
read-write
n
0x0
0x0
URTJnSTC
Status Clear Register
0x10
32
read-write
n
0x0
0x0
URTJnSTR0
Status Register 0
0x8
32
read-only
n
0x0
0x0
URTJnSTR1
Status Register 1
0xC
32
read-only
n
0x0
0x0
URTJnTRG
Triger Register
0x4
32
read-write
n
0x0
0x0
WDT
Watchdog Timer
WDT
0x0
0x0
0x10
registers
n
WDTA
WDT alarm interrupt
80
WDTA0MD
Watchdog Timer Mode register
0xC
8
read-write
n
0x0
0x0
WDTA0WDTE
Watchdog Timer Enable register
0x0
8
read-write
n
0x0
0x0