SONIX SN32F100 2025.04.30 ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 50MHz, etc. CM0 r0p0 little 2 false 8 32 SN_ADC Codec ADC Control Registers ADC 0x40064000 0x0 0x1000 registers n SET1 Offset:0x540 ADC Setting 1 Register 0x540 32 read-write n 0x40 0xFF LB_H AGC Control Low bound setting : High byte 0 8 read-write SET10 Offset:0x5D0 ADC Setting 10 Register 0x5D0 32 read-write n 0x0 0xFF MUTE_TH_L AGC Control Threshold for inactivating : Low byte 0 8 read-write SET11 Offset:0x5E0 ADC Setting 11 Register 0x5E0 32 read-write n 0x9 0xF MUTE_CAL_POD AGC Control Period for inactivating 0 4 read-write 256/Fs x 2^0 None 0 256/Fs x 2^1 None 1 256/Fs x 2^10 None 10 256/Fs x 2^11 None 11 256/Fs x 2^12 None 12 256/Fs x 2^13 None 13 256/Fs x 2^14 None 14 256/Fs x 2^15 None 15 256/Fs x 2^2 None 2 256/Fs x 2^3 None 3 256/Fs x 2^4 None 4 256/Fs x 2^5 None 5 256/Fs x 2^6 None 6 256/Fs x 2^7 None 7 256/Fs x 2^8 None 8 256/Fs x 2^9 None 9 SET12 Offset:0x5F0 ADC Setting 12 Register 0x5F0 32 read-write n 0x3 0xF SAT_TH AGC Control Threshold for ADC saturation 0 4 read-write SET13 Offset:0x600 ADC Setting 13 Register 0x600 32 read-write n 0xA 0xF SAT_POD AGC Control Period for ADC saturation 0 4 read-write 1/Fs x 2^0 None 0 1/Fs x 2^1 None 1 1/Fs x 2^10 None 10 1/Fs x 2^11 None 11 1/Fs x 2^12 None 12 1/Fs x 2^13 None 13 1/Fs x 2^14 None 14 1/Fs x 2^15 None 15 1/Fs x 2^2 None 2 1/Fs x 2^3 None 3 1/Fs x 2^4 None 4 1/Fs x 2^5 None 5 1/Fs x 2^6 None 6 1/Fs x 2^7 None 7 1/Fs x 2^8 None 8 1/Fs x 2^9 None 9 SET14 Offset:0x610 ADC Setting 14 Register 0x610 32 read-write n 0xF0 0xFF AGC_OFF AGC Control function 7 8 read-write Enable None 0 Disable None 1 BOOST_SET_VAL AGC Control Boost setting value at normal mode 5 7 read-write +0dB None 0 +12dB None 1 +20dB None 2 +30dB None 3 PGA_SET_VAL AGC Control PGA setting value at normal mode(1.5dB/step) 0 5 read-write SET15 Offset:0x620 ADC Setting 15 Register 0x620 32 read-write n 0x7 0x7 ACTIVE Digital Audio Interface Control 2 3 read-write Disable None 0 Enable None 1 IWL World length of DAI 0 2 read-write 16-bits None 0 18-bits None 1 20-bits None 2 24-bits None 3 SET16 Offset:0x630 ADC Setting 16 Register 0x630 32 read-write n 0x9 0x7F BOOST Boost setting value 5 7 read-write +0dB None 0 +12dB None 1 +20dB None 2 +30dB None 3 PGA PGA setting value(1.5dB/step) 0 5 read-write SET18 Offset:0x650 ADC Setting 18 Register 0x650 32 read-write n 0x0 0xFF MUTE_CTRL Digital volume attenuation control at mute mode 0 4 read-write 0dB None 0 -3dB None 1 -30dB None 10 -36dB None 11 -42dB None 12 -48dB None 13 -54dB None 14 -78dB None 15 -6dB None 2 -9dB None 3 -12dB None 4 -15dB None 5 -18dB None 6 -21dB None 7 -24dB None 8 -27dB None 9 VOL_CTRL Digital volume attenuation control at normal mode 4 8 read-write 0dB None 0 -3dB None 1 -30dB None 10 -36dB None 11 -42dB None 12 -48dB None 13 -54dB None 14 -78dB None 15 -6dB None 2 -9dB None 3 -12dB None 4 -15dB None 5 -18dB None 6 -21dB None 7 -24dB None 8 -27dB None 9 SET19 Offset:0x660 ADC Setting 19 Register 0x660 32 read-write n 0x70 0x7F BOOST_MUTE_VAL Boost setting value at mute mode 5 7 read-write +0dB None 0 +12dB None 1 +20dB None 2 +30dB None 3 PGA_MUTE_VAL PGA setting value at mute mode(1.5dB/step) 0 5 read-write SET2 Offset:0x550 ADC Setting 2 Register 0x550 32 read-write n 0x0 0xFF LB_L AGC Control Low bound setting : Low byte 0 8 read-write SET20 Offset:0x670 ADC Setting 20 Register 0x670 32 read-write n 0x12 0xFF VOL_MUTE_POD_H Period for Digital volume attenuation at normal mode 4 8 read-write 1/Fs x 2^0 None 0 1/Fs x 2^1 None 1 1/Fs x 2^10 None 10 1/Fs x 2^11 None 11 1/Fs x 2^12 None 12 1/Fs x 2^13 None 13 1/Fs x 2^14 None 14 1/Fs x 2^15 None 15 1/Fs x 2^2 None 2 1/Fs x 2^3 None 3 1/Fs x 2^4 None 4 1/Fs x 2^5 None 5 1/Fs x 2^6 None 6 1/Fs x 2^7 None 7 1/Fs x 2^8 None 8 1/Fs x 2^9 None 9 VOL_MUTE_POD_L Period for Digital volume attenuation at mute mode 0 4 read-write 1/Fs x 2^0 None 0 1/Fs x 2^1 None 1 1/Fs x 2^10 None 10 1/Fs x 2^11 None 11 1/Fs x 2^12 None 12 1/Fs x 2^13 None 13 1/Fs x 2^14 None 14 1/Fs x 2^15 None 15 1/Fs x 2^2 None 2 1/Fs x 2^3 None 3 1/Fs x 2^4 None 4 1/Fs x 2^5 None 5 1/Fs x 2^6 None 6 1/Fs x 2^7 None 7 1/Fs x 2^8 None 8 1/Fs x 2^9 None 9 SET21 Offset:0x6B0 ADC Setting 21 Register 0x6B0 32 read-write n 0x1 0xFF ADC_EN ADC power-on enable 7 8 read-write Disable None 0 Enable None 1 MICBT_EN MICBOOST power-on enable 5 6 read-write Disable None 0 Enable None 1 PGA_EN PGA power-on enable 4 5 read-write Disable None 0 Enable None 1 SET22 Offset:0x6C0 ADC Setting 22 Register 0x6C0 32 read-write n 0x0 0x1F CK_EN CKGEN enable 0 1 read-write Disable None 0 Enable None 1 IREF_EN IREF circuit enable 3 4 read-write Disable None 0 Enable None 1 MICB_EN Microphone bias enable 1 2 read-write Disable None 0 Enable None 1 VREF_EN VREF circuit enable 2 3 read-write Disable None 0 Enable None 1 SET23 Offset:0x6D0 ADC Setting 23 Register 0x6D0 32 read-write n 0x1 0x7F SEL_MIC P1.7/MIC_P and P1.8/MIC_N function selection 2 3 read-write General purpose IO None 0 Microphone Differential input None 1 SEL_MICB Microphone Bias Output select 4 5 read-write 0.8*VA None 0 0.9*VA None 1 SEL_MIX_MIC Microphone input path to mixer enable 0 1 read-write Disable None 0 Enable None 1 SET24 Offset:0x6E0 ADC Setting 24 Register 0x6E0 32 read-only n 0x0 0x7F BOOST_AGC Boost setting value when AGC is on 5 7 read-only PGA_AGC PGA setting value when AGC is on 0 5 read-only SET3 Offset:0x560 ADC Setting 3 Register 0x560 32 read-write n 0x60 0xFF HB_H AGC Control High bound setting : High byte 0 8 read-write SET4 Offset:0x570 ADC Setting 4 Register 0x570 32 read-write n 0x0 0xFF HB_L AGC Control High bound setting : Low byte 0 8 read-write SET5 Offset:0x580 ADC Setting 5 Register 0x580 32 read-write n 0x5 0xF NOR_POD AGC Control Gain update period at normal mode 0 4 read-write 1/Fs x 2^0 None 0 1/Fs x 2^1 None 1 1/Fs x 2^10 None 10 1/Fs x 2^11 None 11 1/Fs x 2^12 None 12 1/Fs x 2^13 None 13 1/Fs x 2^14 None 14 1/Fs x 2^15 None 15 1/Fs x 2^2 None 2 1/Fs x 2^3 None 3 1/Fs x 2^4 None 4 1/Fs x 2^5 None 5 1/Fs x 2^6 None 6 1/Fs x 2^7 None 7 1/Fs x 2^8 None 8 1/Fs x 2^9 None 9 SET6 Offset:0x590 ADC Setting 6 Register 0x590 32 read-write n 0xB 0xF MUTE_POD AGC Control Gain update period at mute mode 0 4 read-write 1/Fs x 2^0 None 0 1/Fs x 2^1 None 1 1/Fs x 2^10 None 10 1/Fs x 2^11 None 11 1/Fs x 2^12 None 12 1/Fs x 2^13 None 13 1/Fs x 2^14 None 14 1/Fs x 2^15 None 15 1/Fs x 2^2 None 2 1/Fs x 2^3 None 3 1/Fs x 2^4 None 4 1/Fs x 2^5 None 5 1/Fs x 2^6 None 6 1/Fs x 2^7 None 7 1/Fs x 2^8 None 8 1/Fs x 2^9 None 9 SET7 Offset:0x5A0 ADC Setting 7 Register 0x5A0 32 read-write n 0x3 0xFF SEARCH_TH_H AGC Control Threshold for activating : High byte 0 8 read-write SET8 Offset:0x5B0 ADC Setting 8 Register 0x5B0 32 read-write n 0x0 0xFF SEARCH_TH_L AGC Control Threshold for activating : Low byte 0 8 read-write SET9 Offset:0x5C0 ADC Setting 9 Register 0x5C0 32 read-write n 0x10 0xFF MUTE_TH_H AGC Control Threshold for inactivating : High byte 0 8 read-write SN_CMP Comparator Control Register CMP 0x40066000 0x0 0x2000 registers n CMP 17 CMPM Offset:0x00 Comparator Control register 0x0 32 read-write n 0x4000 0x8078FF7F CMCH Comparator negative input pin control bit (CMPEN must be 1 ) 0 5 read-write CM0 Comparator negative input pin is P2.0 0 CM1 Comparator negative input pin is P2.1 1 CM10 Comparator negative input pin is P2.10 10 CM11 Comparator negative input pin is P2.11 11 CM12 Comparator negative input pin is P2.12 12 CM13 Comparator negative input pin is P2.13 13 CM14 Comparator negative input pin is P2.14 14 CM15 Comparator negative input pin is P2.15 15 CM16 Comparator negative input pin is P3.0 16 CM17 Comparator negative input pin is P3.1 17 CM18 Comparator negative input pin is P3.2 18 CM19 Comparator negative input pin is P3.3 19 CM2 Comparator negative input pin is P2.2 2 CM20 Comparator negative input pin is P3.4 20 CM21 Comparator negative input pin is P3.5 21 CM22 Comparator negative input pin is P3.6 22 CM23 Comparator negative input pin is P3.7 23 CM3 Comparator negative input pin is P2.3 3 CM4 Comparator negative input pin is P2.4 4 CM5 Comparator negative input pin is P2.5 5 CM6 Comparator negative input pin is P2.6 6 CM7 Comparator negative input pin is P2.7 7 CM8 Comparator negative input pin is P2.8 8 CM9 Comparator negative input pin is P2.9 9 CMDB Comparator output debounce time select bit(TCHEN=1 is HCLK, TCHEN=0 is CMP_PCLK) 10 12 read-write 1*CMP_PCLK Comparator output debounce time = 1*CMP_PCLK 0 2*CMP_PCLK Comparator output debounce time = 2*CMP_PCLK 01 3*CMP_PCLK Comparator output debounce time = 3*CMP_PCLK 2 No-debounce Comparator output debounce time = 0 3 CMPEN Comparator control bit 31 32 read-write Disable P2[15:0], P3[7:0] are GPIO mode 0 Enable Comparator negative input pins are controlled by CMCH[4:0] bits 1 CMPG Comparator interrupt trigger direction control bit 8 9 read-write Rising edge Rising edge trigger (CMPP larger than CMPN or comparator internal reference voltage) 0 Falling edge Falling edge trigger (CMPP less than CMPN or comparator internal reference voltage) 1 CMPOEN Comparator output pin control bit 9 10 read-write Disable CMO pin is GPIO mode 0 Enable Enable comparator output pin (P3.8 pin exchanges to comparator output pin and GPIO function is isolated) 1 CMPOUT Comparator output flag bit (The comparator output status is 1 as comparator disable) 14 15 read-write Comparator internal reference voltage is less than CMPN voltage None 0 Comparator internal reference voltage is larger than CMPN voltage None 1 CMPS Comparator positive input voltage control bit 5 7 read-write 1/4*Vdd Internal 1/4*Vdd and enable internal reference voltage generato 0 1/2*Vdd Internal 1/2*Vdd and enable internal reference voltage generator 1 3/4*Vdd Internal 3/4*Vdd and enable internal reference voltage generator 3 3/4*Vdd Internal 3/4*Vdd and enable internal reference voltage generator 3 CMP_IC Offset:0x18 Comparator Interrupt Clear register 0x18 32 write-only n 0x0 0x3 CMPGIC Comparator CMPGIF interrupt flag clear 0 1 write-only No effect None 0 Clear Clear CMPGIF bit 1 CMP_IE Offset:0x10 Comparator Interrupt Enable register 0x10 32 read-write n 0x0 0x3 CMPGIE Comparator edge trigger interrupt enable (Comparator interrupt trigger direction refer to CMPG) 0 1 read-write Disable None 0 Enable None 1 CMP_RIS Offset:0x14 Comparator Interrupt Status register 0x14 32 read-only n 0x0 0x3 CMPGIF Comparator edge trigger interrupt flag 0 1 read-only No interrupt Comparator edge trigger doesn't occur 0 Met interrupt requirements Comparator edge trigger occurs 1 SN_CT16B0 16-bit Timer 0 with Capture function TIMER 0x40000000 0x0 0x2000 registers n CT16B0 18 CAP0 Offset:0x2C CT16Bn CAP0 Register 0x2C 32 read-only n 0x0 0xFFFF CAP0 Timer counter capture value 0 16 read-only CAPCTRL Offset:0x28 CT16Bn Capture Control Register 0x28 32 read-write n 0x0 0x7F CAP0EN CAP0 function enable 5 7 read-write Disable Disable 0 Enable Enable CAP0 function for external Capture pin 1 CAP0FE Capture/Reset on CT16Bn_CAP0 signal falling edge 2 4 read-write Disable Disable 0 Enable A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CAP0IE Interrupt on CT16Bn_CAP0 signal event: a CAP0 load due to a CT16Bn_CAP0 signal event will generate an interrupt. 4 5 read-write Disable Disable 0 Enable A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt. 1 CAP0RE Capture/Reset on CT16Bn_CAP0 signal rising edge 0 2 read-write Disable Disable 0 Enable A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CNTCTRL Offset:0x10 CT16Bn Counter Control Register 0x10 32 read-write n 0x0 0xF CIS Counter Input Select 2 4 read-write CT16Bn_CAP0 CT16Bn_CAP0 0 CTM Counter/Timer Mode 0 2 read-write Timer Mode Every rising PCLK edge 0 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 EM Offset:0x30 CT16Bn External Match Register 0x30 32 read-write n 0x0 0x31 EM0 When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. 0 1 read-write EMC0 CT16Bn_PWM0 functionality 4 6 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM0 pin is LOW 1 High CT16Bn_PWM0 pin is HIGH 2 Toggle Toggle CT16Bn_PWM0 pin 3 IC Offset:0x3C CT16Bn Interrupt Clear Register 0x3C 32 write-only n 0x0 0x1F CAP0IC CAP0IF clear bit 4 5 write-only No effect No effect 0 Clear Clear CAP0IF 1 MR0IC MR0IF clear bit 0 1 write-only No effect No effect 0 Clear Clear MR0IF 1 MR1IC MR1IF clear bit 1 2 write-only No effect No effect 0 Clear Clear MR1IF 1 MR2IC MR2IF clear bit 2 3 write-only No effect No effect 0 Clear Clear MR2IF 1 MR3IC MR3IF clear bit 3 4 write-only No effect No effect 0 Clear Clear MR3IF 1 MCTRL Offset:0x14 CT16Bn Match Control Register 0x14 32 read-write n 0x0 0xFFF MR0IE Enable generating an interrupt when MR0 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR0 matches TC 1 MR0RST Enable reset TC when MR0 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR0 matches TC 1 MR0STOP Stop TC and PC and clear CEN bit when MR0 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR0 matches TC 1 MR1IE Enable generating an interrupt when MR1 matches TC 3 4 read-write Disable Disable 0 Enable Generating an interrupt when MR1 matches TC 1 MR1RST Enable reset TC when MR1 matches TC 4 5 read-write Disable Disable 0 Enable Reset TC when MR1 matches TC 1 MR1STOP Stop TC and PC and clear CEN bit when MR1 matches TC 5 6 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR1 matches TC 1 MR2IE Enable generating an interrupt when MR2 matches TC 6 7 read-write Disable Disable 0 Enable Generating an interrupt when MR2 matches TC 1 MR2RST Enable reset TC when MR2 matches TC 7 8 read-write Disable Disable 0 Enable Reset TC when MR2 matches TC 1 MR2STOP Stop TC and PC and clear CEN bit when MR2 matches TC 8 9 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR2 matches TC 1 MR3IE Enable generating an interrupt when MR3 matches TC 9 10 read-write Disable Disable 0 Enable Generating an interrupt when MR3 matches TC 1 MR3RST Enable reset TC when MR3 matches TC 10 11 read-write Disable Disable 0 Enable Reset TC when MR3 matches TC 1 MR3STOP Stop TC and PC and clear CEN bit when MR3 matches TC 11 12 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR3 matches TC 1 MR0 Offset:0x18 CT16Bn MR0 Register 0x18 32 read-write n 0x0 0xFFFF MR1 Offset:0x1C CT16Bn MR1 Register 0x1C 32 read-write n 0x0 0xFFFF MR2 Offset:0x20 CT16Bn MR2 Register 0x20 32 read-write n 0x0 0xFFFF MR3 Offset:0x24 CT16Bn MR3 Register 0x24 32 read-write n 0x0 0xFFFF PC Offset:0x0C CT16Bn Prescale Counter Register 0xC 32 read-write n 0x0 0xFFFF PC Prescaler Counter 0 16 read-write PRE Offset:0x08 CT16Bn Prescale Register 0x8 32 read-write n 0x0 0xFFFF PR Prescaler 0 16 read-write PWMCTRL Offset:0x34 CT16Bn PWM Control Register 0x34 32 read-write n 0x0 0x100001 PWM0EN PWM0 enable 0 1 read-write Disable CT16Bn_PWM0 is controlled by EM0 0 Enable Enable PWM mode for CT16Bn_PWM0 1 PWM0IOEN CT16Bn_PWM0/GPIO selection 20 21 read-write Disable CT16Bn_PWM0 pin is act as GPIO 0 Enable CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit 1 RIS Offset:0x38 CT16Bn Raw Interrupt Status Register 0x38 32 read-only n 0x0 0x1F CAP0IF Capture channel 0 interrupt flag 4 5 read-only No No interrupt on CAP0 0 Met interrupt requirements Interrupt requirements met on CAP0 1 MR0IF Match channel 0 interrupt flag 0 1 read-only No interrupt No interrupt on match channel 0 0 Met interrupt requirements Interrupt requirements met on match channel 0 1 MR1IF Match channel 1 interrupt flag 1 2 read-only No No interrupt on match channel 1 0 Met interrupt requirements Interrupt requirements met on match channel 1 1 MR2IF Match channel 2 interrupt flag 2 3 read-only No No interrupt on match channel 2 0 Met interrupt requirements Interrupt requirements met on match channel 2 1 MR3IF Match channel 3 interrupt flag 3 4 read-only No No interrupt on match channel 3 0 Met interrupt requirements Interrupt requirements met on match channel 3 1 TC Offset:0x04 CT16Bn Timer Counter Register 0x4 32 read-write n 0x0 0xFFFF TC Timer Counter 0 16 read-write TMRCTRL Offset:0x00 CT16Bn Timer Control Register 0x0 32 read-write n 0x0 0x3 CEN Counter enable 0 1 read-write Disable Disable counter 0 Enable Enable Timer Counter and Prescale Counter for counting 1 CRST Counter Reset 1 2 read-write Disable Disable 0 Reset Counter Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK 1 SN_CT16B1 16-bit Timer 0 with Capture function TIMER 0x40002000 0x0 0x2000 registers n CT16B1 19 CAP0 Offset:0x2C CT16Bn CAP0 Register 0x2C 32 read-only n 0x0 0xFFFF CAP0 Timer counter capture value 0 16 read-only CAPCTRL Offset:0x28 CT16Bn Capture Control Register 0x28 32 read-write n 0x0 0x7F CAP0EN CAP0 function enable 5 7 read-write Disable Disable 0 Enable Enable CAP0 function for external Capture pin 1 CAP0FE Capture/Reset on CT16Bn_CAP0 signal falling edge 2 4 read-write Disable Disable 0 Enable A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CAP0IE Interrupt on CT16Bn_CAP0 signal event: a CAP0 load due to a CT16Bn_CAP0 signal event will generate an interrupt. 4 5 read-write Disable Disable 0 Enable A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt. 1 CAP0RE Capture/Reset on CT16Bn_CAP0 signal rising edge 0 2 read-write Disable Disable 0 Enable A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CNTCTRL Offset:0x10 CT16Bn Counter Control Register 0x10 32 read-write n 0x0 0xF CIS Counter Input Select 2 4 read-write CT16Bn_CAP0 CT16Bn_CAP0 0 CTM Counter/Timer Mode 0 2 read-write Timer Mode Every rising PCLK edge 0 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 EM Offset:0x30 CT16Bn External Match Register 0x30 32 read-write n 0x0 0x31 EM0 When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. 0 1 read-write EMC0 CT16Bn_PWM0 functionality 4 6 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM0 pin is LOW 1 High CT16Bn_PWM0 pin is HIGH 2 Toggle Toggle CT16Bn_PWM0 pin 3 IC Offset:0x3C CT16Bn Interrupt Clear Register 0x3C 32 write-only n 0x0 0x1F CAP0IC CAP0IF clear bit 4 5 write-only No effect No effect 0 Clear Clear CAP0IF 1 MR0IC MR0IF clear bit 0 1 write-only No effect No effect 0 Clear Clear MR0IF 1 MR1IC MR1IF clear bit 1 2 write-only No effect No effect 0 Clear Clear MR1IF 1 MR2IC MR2IF clear bit 2 3 write-only No effect No effect 0 Clear Clear MR2IF 1 MR3IC MR3IF clear bit 3 4 write-only No effect No effect 0 Clear Clear MR3IF 1 MCTRL Offset:0x14 CT16Bn Match Control Register 0x14 32 read-write n 0x0 0xFFF MR0IE Enable generating an interrupt when MR0 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR0 matches TC 1 MR0RST Enable reset TC when MR0 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR0 matches TC 1 MR0STOP Stop TC and PC and clear CEN bit when MR0 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR0 matches TC 1 MR1IE Enable generating an interrupt when MR1 matches TC 3 4 read-write Disable Disable 0 Enable Generating an interrupt when MR1 matches TC 1 MR1RST Enable reset TC when MR1 matches TC 4 5 read-write Disable Disable 0 Enable Reset TC when MR1 matches TC 1 MR1STOP Stop TC and PC and clear CEN bit when MR1 matches TC 5 6 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR1 matches TC 1 MR2IE Enable generating an interrupt when MR2 matches TC 6 7 read-write Disable Disable 0 Enable Generating an interrupt when MR2 matches TC 1 MR2RST Enable reset TC when MR2 matches TC 7 8 read-write Disable Disable 0 Enable Reset TC when MR2 matches TC 1 MR2STOP Stop TC and PC and clear CEN bit when MR2 matches TC 8 9 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR2 matches TC 1 MR3IE Enable generating an interrupt when MR3 matches TC 9 10 read-write Disable Disable 0 Enable Generating an interrupt when MR3 matches TC 1 MR3RST Enable reset TC when MR3 matches TC 10 11 read-write Disable Disable 0 Enable Reset TC when MR3 matches TC 1 MR3STOP Stop TC and PC and clear CEN bit when MR3 matches TC 11 12 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR3 matches TC 1 MR0 Offset:0x18 CT16Bn MR0 Register 0x18 32 read-write n 0x0 0xFFFF MR1 Offset:0x1C CT16Bn MR1 Register 0x1C 32 read-write n 0x0 0xFFFF MR2 Offset:0x20 CT16Bn MR2 Register 0x20 32 read-write n 0x0 0xFFFF MR3 Offset:0x24 CT16Bn MR3 Register 0x24 32 read-write n 0x0 0xFFFF PC Offset:0x0C CT16Bn Prescale Counter Register 0xC 32 read-write n 0x0 0xFFFF PC Prescaler Counter 0 16 read-write PRE Offset:0x08 CT16Bn Prescale Register 0x8 32 read-write n 0x0 0xFFFF PR Prescaler 0 16 read-write PWMCTRL Offset:0x34 CT16Bn PWM Control Register 0x34 32 read-write n 0x0 0x100001 PWM0EN PWM0 enable 0 1 read-write Disable CT16Bn_PWM0 is controlled by EM0 0 Enable Enable PWM mode for CT16Bn_PWM0 1 PWM0IOEN CT16Bn_PWM0/GPIO selection 20 21 read-write Disable CT16Bn_PWM0 pin is act as GPIO 0 Enable CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit 1 RIS Offset:0x38 CT16Bn Raw Interrupt Status Register 0x38 32 read-only n 0x0 0x1F CAP0IF Capture channel 0 interrupt flag 4 5 read-only No No interrupt on CAP0 0 Met interrupt requirements Interrupt requirements met on CAP0 1 MR0IF Match channel 0 interrupt flag 0 1 read-only No interrupt No interrupt on match channel 0 0 Met interrupt requirements Interrupt requirements met on match channel 0 1 MR1IF Match channel 1 interrupt flag 1 2 read-only No No interrupt on match channel 1 0 Met interrupt requirements Interrupt requirements met on match channel 1 1 MR2IF Match channel 2 interrupt flag 2 3 read-only No No interrupt on match channel 2 0 Met interrupt requirements Interrupt requirements met on match channel 2 1 MR3IF Match channel 3 interrupt flag 3 4 read-only No No interrupt on match channel 3 0 Met interrupt requirements Interrupt requirements met on match channel 3 1 TC Offset:0x04 CT16Bn Timer Counter Register 0x4 32 read-write n 0x0 0xFFFF TC Timer Counter 0 16 read-write TMRCTRL Offset:0x00 CT16Bn Timer Control Register 0x0 32 read-write n 0x0 0x3 CEN Counter enable 0 1 read-write Disable Disable counter 0 Enable Enable Timer Counter and Prescale Counter for counting 1 CRST Counter Reset 1 2 read-write Disable Disable 0 Reset Counter Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK 1 SN_CT32B0 32-bit Timer 0 with Capture function TIMER 0x40004000 0x0 0x2000 registers n CT32B0 20 CAP0 Offset:0x2C CT32Bn CAP0 Register 0x2C 32 read-only n 0x0 0xFFFFFFFF CAPCTRL Offset:0x28 CT32Bn Capture Control Register 0x28 32 read-write n 0x0 0x7F CAP0EN CAP0 function enable 5 7 read-write Disable Disable 0 Enable Enable CAP0 function for external Capture pin 1 CAP0FE Capture/Reset on CT32Bn_CAP0 signal falling edge. 2 4 read-write Disable Disable 0 Enable A sequence of 1 then 0 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 1 then 0 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CAP0IE Interrupt on CT32Bn_CAP0 signal event 4 5 read-write Disable Disable 0 Enable A CAP0 load due to a CT32Bn_CAP0 event will generate an interrupt. 1 CAP0RE Capture/Reset on CT32Bn_CAP0 signal rising edge. 0 2 read-write Disable Disable 0 Enable A sequence of 0 then 1 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 0 then 1 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CNTCTRL Offset:0x10 CT32Bn Counter Control Register 0x10 32 read-write n 0x0 0xF CIS Counter Input Select 2 4 read-write CT32Bn_CAP0 Counter input from CT32Bn_CAP0 0 CTM Counter/Timer Mode 0 2 read-write Timer Mode Every rising PCLK edge 0 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 EM Offset:0x30 CT32Bn External Match Register 0x30 32 read-write n 0x0 0xF3 EM0 When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT32Bn_PWM0 output. 0 1 read-write EM1 When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT32Bn_PWM1 output. 1 2 read-write EMC0 CT32Bn_PWM0 functionality 4 6 read-write Do Nothing Do Nothing 0 Low CT32Bn_PWM0 pin is LOW 1 High CT32Bn_PWM0 pin is HIGH 2 Toggle Toggle CT32Bn_PWM0 pin 3 EMC1 CT32Bn_PWM1 functionality 6 8 read-write Do Nothing Do Nothing 0 Low CT32Bn_PWM1 pin is LOW 1 High CT32Bn_PWM1 pin is HIGH 2 Toggle Toggle CT32Bn_PWM1 pin 3 IC Offset:0x3C CT32Bn Interrupt Clear Register 0x3C 32 write-only n 0x0 0x1F CAP0IC CAP0IF clear bit 4 5 write-only No effect No effect 0 Clear Clear CAP0IF 1 MR0IC MR0IF clear bit 0 1 write-only No effect No effect 0 Clear Clear MR0IF 1 MR1IC MR1IF clear bit 1 2 write-only No effect No effect 0 Clear Clear MR1IF 1 MR2IC MR2IF clear bit 2 3 write-only No effect No effect 0 Clear Clear MR2IF 1 MR3IC MR3IF clear bit 3 4 write-only No effect No effect 0 Clear Clear MR3IF 1 MCTRL Offset:0x14 CT32Bn Match Control Register 0x14 32 read-write n 0x0 0xFFF MR0IE Enable generating an interrupt when MR0 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR0 matches TC 1 MR0RST Enable reset TC when MR0 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR0 matches TC 1 MR0STOP Stop TC and PC and clear CEN bit when MR0 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR0 matches TC 1 MR1IE Enable generating an interrupt when MR1 matches TC 3 4 read-write Disable Disable 0 Enable Generating an interrupt when MR1 matches TC 1 MR1RST Enable reset TC when MR1 matches TC 4 5 read-write Disable Disable 0 Enable Reset TC when MR1 matches TC 1 MR1STOP Stop TC and PC and clear CEN bit when MR1 matches TC 5 6 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR1 matches TC 1 MR2IE Enable generating an interrupt when MR2 matches TC 6 7 read-write Disable Disable 0 Enable Generating an interrupt when MR2 matches TC 1 MR2RST Enable reset TC when MR2 matches TC 7 8 read-write Disable Disable 0 Enable Reset TC when MR2 matches TC 1 MR2STOP Stop TC and PC and clear CEN bit when MR2 matches TC 8 9 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR2 matches TC 1 MR3IE Enable generating an interrupt when MR3 matches TC 9 10 read-write Disable Disable 0 Enable Generating an interrupt when MR3 matches TC 1 MR3RST Enable reset TC when MR3 matches TC 10 11 read-write Disable Disable 0 Enable Reset TC when MR3 matches TC 1 MR3STOP Stop TC and PC and clear CEN bit when MR3 matches TC 11 12 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR3 matches TC 1 MR0 Offset:0x18 CT32Bn MR0 Register 0x18 32 read-write n 0x0 0xFFFFFFFF MR1 Offset:0x1C CT32Bn MR1 Register 0x1C 32 read-write n 0x0 0xFFFFFFFF MR2 Offset:0x20 CT32Bn MR2 Register 0x20 32 read-write n 0x0 0xFFFFFFFF MR3 Offset:0x24 CT32Bn MR3 Register 0x24 32 read-write n 0x0 0xFFFFFFFF PC Offset:0x0C CT32Bn Prescale Counter Register 0xC 32 read-write n 0x0 0xFFFFFFFF PRE Offset:0x08 CT32Bn Prescale Register 0x8 32 read-write n 0x0 0xFFFFFFFF PWMCTRL Offset:0x34 CT32Bn PWM Control Register 0x34 32 read-write n 0x0 0x300003 PWM0EN PWM0 enable 0 1 read-write Disable CT32Bn_PWM0 is controlled by EM0 0 Enable Enable PWM mode for CT32Bn_PWM0 1 PWM0IOEN CT32Bn_PWM0/GPIO selection 20 21 read-write Disable CT32Bn_PWM0 pin is act as GPIO 0 Enable CT32Bn_PWM0 pin act as match output, and output depends on PWM0EN bit 1 PWM1EN PWM1 enable 1 2 read-write Disable CT32Bn_PWM1 is controlled by EM1 0 Enable Enable PWM mode for CT32Bn_PWM1 1 PWM1IOEN CT16Bn_PWM1/GPIO selection 21 22 read-write Disable CT32Bn_PWM1 pin is act as GPIO 0 Enable CT32Bn_PWM1 pin act as match output, and output depends on PWM1EN bit 1 RIS Offset:0x38 CT32Bn Raw Interrupt Status Register 0x38 32 read-only n 0x0 0x1F CAP0IF Capture channel 0 interrupt flag 4 5 read-only No No interrupt on CAP0 0 Met interrupt requirements Interrupt requirements met on CAP0 1 MR0IF Match channel 0 interrupt flag 0 1 read-only No No interrupt on match channel 0 0 Met interrupt requirements Interrupt requirements met on match channel 0 1 MR1IF Match channel 1 interrupt flag 1 2 read-only No No interrupt on match channel 1 0 Met interrupt requirements Interrupt requirements met on match channel 1 1 MR2IF Match channel 2 interrupt flag 2 3 read-only No No interrupt on match channel 2 0 Met interrupt requirements Interrupt requirements met on match channel 2 1 MR3IF Match channel 3 interrupt flag 3 4 read-only No No interrupt on match channel 3 0 Met interrupt requirements Interrupt requirements met on match channel 3 1 TC Offset:0x04 CT32Bn Timer Counter Register 0x4 32 read-write n 0x0 0xFFFFFFFF TMRCTRL Offset:0x00 CT32Bn Timer Control Register 0x0 32 read-write n 0x0 0x3 CEN Counter Enable 0 1 read-write Disable Disable 0 Enable Enable Timer Counter and Prescale Counter for counting 1 CRST Counter Reset 1 2 read-write Disable Disable 0 Reset Counter Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. This is cleared by HW when the counter reset operation finishes. 1 SN_CT32B1 32-bit Timer 0 with Capture function TIMER 0x40006000 0x0 0x2000 registers n CT32B1 21 CAP0 Offset:0x2C CT32Bn CAP0 Register 0x2C 32 read-only n 0x0 0xFFFFFFFF CAPCTRL Offset:0x28 CT32Bn Capture Control Register 0x28 32 read-write n 0x0 0x7F CAP0EN CAP0 function enable 5 7 read-write Disable Disable 0 Enable Enable CAP0 function for external Capture pin 1 CAP0FE Capture/Reset on CT32Bn_CAP0 signal falling edge. 2 4 read-write Disable Disable 0 Enable A sequence of 1 then 0 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 1 then 0 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CAP0IE Interrupt on CT32Bn_CAP0 signal event 4 5 read-write Disable Disable 0 Enable A CAP0 load due to a CT32Bn_CAP0 event will generate an interrupt. 1 CAP0RE Capture/Reset on CT32Bn_CAP0 signal rising edge. 0 2 read-write Disable Disable 0 Enable A sequence of 0 then 1 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 Enable A sequence of 0 then 1 on CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CNTCTRL Offset:0x10 CT32Bn Counter Control Register 0x10 32 read-write n 0x0 0xF CIS Counter Input Select 2 4 read-write CT32Bn_CAP0 Counter input from CT32Bn_CAP0 0 CTM Counter/Timer Mode 0 2 read-write Timer Mode Every rising PCLK edge 0 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 EM Offset:0x30 CT32Bn External Match Register 0x30 32 read-write n 0x0 0xF3 EM0 When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT32Bn_PWM0 output. 0 1 read-write EM1 When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT32Bn_PWM1 output. 1 2 read-write EMC0 CT32Bn_PWM0 functionality 4 6 read-write Do Nothing Do Nothing 0 Low CT32Bn_PWM0 pin is LOW 1 High CT32Bn_PWM0 pin is HIGH 2 Toggle Toggle CT32Bn_PWM0 pin 3 EMC1 CT32Bn_PWM1 functionality 6 8 read-write Do Nothing Do Nothing 0 Low CT32Bn_PWM1 pin is LOW 1 High CT32Bn_PWM1 pin is HIGH 2 Toggle Toggle CT32Bn_PWM1 pin 3 IC Offset:0x3C CT32Bn Interrupt Clear Register 0x3C 32 write-only n 0x0 0x1F CAP0IC CAP0IF clear bit 4 5 write-only No effect No effect 0 Clear Clear CAP0IF 1 MR0IC MR0IF clear bit 0 1 write-only No effect No effect 0 Clear Clear MR0IF 1 MR1IC MR1IF clear bit 1 2 write-only No effect No effect 0 Clear Clear MR1IF 1 MR2IC MR2IF clear bit 2 3 write-only No effect No effect 0 Clear Clear MR2IF 1 MR3IC MR3IF clear bit 3 4 write-only No effect No effect 0 Clear Clear MR3IF 1 MCTRL Offset:0x14 CT32Bn Match Control Register 0x14 32 read-write n 0x0 0xFFF MR0IE Enable generating an interrupt when MR0 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR0 matches TC 1 MR0RST Enable reset TC when MR0 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR0 matches TC 1 MR0STOP Stop TC and PC and clear CEN bit when MR0 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR0 matches TC 1 MR1IE Enable generating an interrupt when MR1 matches TC 3 4 read-write Disable Disable 0 Enable Generating an interrupt when MR1 matches TC 1 MR1RST Enable reset TC when MR1 matches TC 4 5 read-write Disable Disable 0 Enable Reset TC when MR1 matches TC 1 MR1STOP Stop TC and PC and clear CEN bit when MR1 matches TC 5 6 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR1 matches TC 1 MR2IE Enable generating an interrupt when MR2 matches TC 6 7 read-write Disable Disable 0 Enable Generating an interrupt when MR2 matches TC 1 MR2RST Enable reset TC when MR2 matches TC 7 8 read-write Disable Disable 0 Enable Reset TC when MR2 matches TC 1 MR2STOP Stop TC and PC and clear CEN bit when MR2 matches TC 8 9 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR2 matches TC 1 MR3IE Enable generating an interrupt when MR3 matches TC 9 10 read-write Disable Disable 0 Enable Generating an interrupt when MR3 matches TC 1 MR3RST Enable reset TC when MR3 matches TC 10 11 read-write Disable Disable 0 Enable Reset TC when MR3 matches TC 1 MR3STOP Stop TC and PC and clear CEN bit when MR3 matches TC 11 12 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR3 matches TC 1 MR0 Offset:0x18 CT32Bn MR0 Register 0x18 32 read-write n 0x0 0xFFFFFFFF MR1 Offset:0x1C CT32Bn MR1 Register 0x1C 32 read-write n 0x0 0xFFFFFFFF MR2 Offset:0x20 CT32Bn MR2 Register 0x20 32 read-write n 0x0 0xFFFFFFFF MR3 Offset:0x24 CT32Bn MR3 Register 0x24 32 read-write n 0x0 0xFFFFFFFF PC Offset:0x0C CT32Bn Prescale Counter Register 0xC 32 read-write n 0x0 0xFFFFFFFF PRE Offset:0x08 CT32Bn Prescale Register 0x8 32 read-write n 0x0 0xFFFFFFFF PWMCTRL Offset:0x34 CT32Bn PWM Control Register 0x34 32 read-write n 0x0 0x300003 PWM0EN PWM0 enable 0 1 read-write Disable CT32Bn_PWM0 is controlled by EM0 0 Enable Enable PWM mode for CT32Bn_PWM0 1 PWM0IOEN CT32Bn_PWM0/GPIO selection 20 21 read-write Disable CT32Bn_PWM0 pin is act as GPIO 0 Enable CT32Bn_PWM0 pin act as match output, and output depends on PWM0EN bit 1 PWM1EN PWM1 enable 1 2 read-write Disable CT32Bn_PWM1 is controlled by EM1 0 Enable Enable PWM mode for CT32Bn_PWM1 1 PWM1IOEN CT16Bn_PWM1/GPIO selection 21 22 read-write Disable CT32Bn_PWM1 pin is act as GPIO 0 Enable CT32Bn_PWM1 pin act as match output, and output depends on PWM1EN bit 1 RIS Offset:0x38 CT32Bn Raw Interrupt Status Register 0x38 32 read-only n 0x0 0x1F CAP0IF Capture channel 0 interrupt flag 4 5 read-only No No interrupt on CAP0 0 Met interrupt requirements Interrupt requirements met on CAP0 1 MR0IF Match channel 0 interrupt flag 0 1 read-only No No interrupt on match channel 0 0 Met interrupt requirements Interrupt requirements met on match channel 0 1 MR1IF Match channel 1 interrupt flag 1 2 read-only No No interrupt on match channel 1 0 Met interrupt requirements Interrupt requirements met on match channel 1 1 MR2IF Match channel 2 interrupt flag 2 3 read-only No No interrupt on match channel 2 0 Met interrupt requirements Interrupt requirements met on match channel 2 1 MR3IF Match channel 3 interrupt flag 3 4 read-only No No interrupt on match channel 3 0 Met interrupt requirements Interrupt requirements met on match channel 3 1 TC Offset:0x04 CT32Bn Timer Counter Register 0x4 32 read-write n 0x0 0xFFFFFFFF TMRCTRL Offset:0x00 CT32Bn Timer Control Register 0x0 32 read-write n 0x0 0x3 CEN Counter Enable 0 1 read-write Disable Disable 0 Enable Enable Timer Counter and Prescale Counter for counting 1 CRST Counter Reset 1 2 read-write Disable Disable 0 Reset Counter Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. This is cleared by HW when the counter reset operation finishes. 1 SN_DAC Codec DAC Control Registers DAC 0x40065000 0x0 0x1000 registers n SET1 Offset:0x000 DAC Setting 1 Register 0x0 32 read-write n 0xED 0xFF PD_CLK CKGEN Power-down enable 6 7 read-write Disable None 0 Enable None 1 PD_DAC DAC Power-down enable 7 8 read-write Disable None 0 Enable None 1 PD_IREF IREF Circuit Power-down enable 5 6 read-write Disable None 0 Enable None 1 PD_VREF VREF Circuit Power-down enable 2 3 read-write Disable None 0 Enable None 1 VMIDSEL Normal mode/Fast Start-up select 1 2 read-write Normal mode None 0 Fast Start-up mode None 1 SET2 Offset:0x010 DAC Setting 2 Register 0x10 32 read-write n 0x25 0xFF DAC_EN_IN DAC Enable 1 2 read-write Disable None 0 Enable None 1 MUTX Mute ON/OFF 2 3 read-write Mute off None 0 Mute on None 1 RMP Attenuation ramp rate 6 8 read-write 1*LRCK None 0 2*LRCK None 1 4*LRCK None 2 8*LRCK None 3 SOFT_RSTN Software reset digital circuit(one MCLK pulse trigger) 0 1 read-write Reset None 0 Not Reset None 1 SET3 Offset:0x020 DAC Setting 3 Register 0x20 32 read-write n 0x0 0xFF VOL DAC VOL setting 0 8 read-write SET4 Offset:0x030 DAC Setting 4 Register 0x30 32 read-write n 0x80 0x87 DEMS Select the DAC de-emphasis response curve 1 3 read-write De-emphasis for 48KHz None 1 De-emphasis for 44.1KHz None 2 De-emphasis for 32KHz None 3 INI_RAM_EN Initialize RAM enable 0 1 read-write Disable None 0 Enable None 1 PD_DRV Driver Power-down enable 7 8 read-write Disable None 0 Enable None 1 STATUS Offset:0x040 DAC Status Register 0x40 32 read-only n 0x0 0x1 Ini_RAM_Ready Initialize RAM ready 0 1 read-only Not ready None 0 Ready None 1 SN_FLASH FLASH Memory Control Registers FLASH 0x40062000 0x0 0x2000 registers n ADDR Offset:0x10 Flash Address Register 0x10 32 read-write n 0x0 0xFFFFFFFF CHKSUM Offset:0x14 Flash Checksum Register 0x14 32 read-only n 0x0 0xFFFF CTRL Offset:0x08 Flash Control Register 0x8 32 read-write n 0x0 0xC3 CHK Checksum calculation choosen 7 8 read-write Disable None 0 Enable Trigger checksum calculation 1 PER Page erase choosen 1 2 read-write Not chosen Not choose page erase operation. 0 Choose page erase operation Choose page erase operation. 1 PG Flash program choosen 0 1 read-write Not chosen Not choose Flash program operation. 0 Choose Flash program operation Choose Flash program operation. 1 STARTE Start erase operation 6 7 read-write Stop/Finish Erase operation is finished. 0 Start Start erase operation 1 DATA Offset:0x0C Flash Data Register 0xC 32 read-write n 0x0 0xFFFFFFFF STATUS Offset:0x04 Flash Status Register 0x4 32 read-write n 0x20 0x25 BUSY Busy flag 0 1 read-only Idle Flash operation is stopped. 0 Busy Flash operation is in process 1 EOP End of process flag 5 6 read-write Busy Flash operation is not completed 0 End Flash operation is completed 1 PGERR Program error flag 2 3 read-write No error No error 0 Program error The address to be programmed contains a value different from 0xFFFF 1 SN_GPIO0 General Purpose I/O GPIO 0x40044000 0x0 0x2000 registers n P0 0 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0xFFFF BCLR0 Clear Pn.0 0 1 write-only No effect No effect 0 Clear Clear Pn.0 1 BCLR1 Clear Pn.1 1 2 write-only No effect No effect 0 Clear Clear Pn.1 1 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR12 Clear Pn.12 12 13 write-only No effect No effect 0 Clear Clear Pn.12 1 BCLR13 Clear Pn.13 13 14 write-only No effect No effect 0 Clear Clear Pn.13 1 BCLR14 Clear Pn.14 14 15 write-only No effect No effect 0 Clear Clear Pn.14 1 BCLR15 Clear Pn.15 15 16 write-only No effect No effect 0 Clear Clear Pn.15 1 BCLR2 Clear Pn.2 2 3 write-only No effect No effect 0 Clear Clear Pn.2 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0xFFFF BSET0 Set Pn.0 0 1 write-only No effect No effect 0 Set Set Pn.0 to 1 1 BSET1 Set Pn.1 1 2 write-only No effect No effect 0 Set Set Pn.1 to 1 1 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET12 Set Pn.12 12 13 write-only No effect No effect 0 Set Set Pn.12 to 1 1 BSET13 Set Pn.13 13 14 write-only No effect No effect 0 Set Set Pn.13 to 1 1 BSET14 Set Pn.14 14 15 write-only No effect No effect 0 Set Set Pn.14 to 1 1 BSET15 Set Pn.15 15 16 write-only No effect No effect 0 Set Set Pn.15 to 1 1 BSET2 Set Pn.2 2 3 write-only No effect No effect 0 Set Set Pn.2 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0xAAAAAAAA 0xFFFFFFFF CFG0 Configuration of Pn.0 0 2 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG1 Configuration of Pn.1 2 4 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG10 Configuration of Pn.10 20 22 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG11 Configuration of Pn.11 22 24 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG12 Configuration of Pn.12 24 26 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG13 Configuration of Pn.13 26 28 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG14 Configuration of Pn.14 28 30 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG15 Configuration of Pn.15 30 32 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG2 Configuration of Pn.2 4 6 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG3 Configuration of Pn.3 6 8 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG4 Configuration of Pn.4 8 10 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG5 Configuration of Pn.5 10 12 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG6 Configuration of Pn.6 12 14 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG7 Configuration of Pn.7 14 16 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG8 Configuration of Pn.8 16 18 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG9 Configuration of Pn.9 18 20 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0xFFFF DATA0 Data of Pn.0 0 1 read-write 0 Pn.0 is 0 0 1 Pn.0 is 1 1 DATA1 Data of Pn.1 1 2 read-write 0 Pn.1 is 0 0 1 Pn.1 is 1 1 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA12 Data of Pn.12 12 13 read-write 0 Pn.12 is 0 0 1 Pn.12 is 1 1 DATA13 Data of Pn.13 13 14 read-write 0 Pn.13 is 0 0 1 Pn.13 is 1 1 DATA14 Data of Pn.14 14 15 read-write 0 Pn.14 is 0 0 1 Pn.14 is 1 1 DATA15 Data of Pn.15 15 16 read-write 0 Pn.15 is 0 0 1 Pn.15 is 1 1 DATA2 Data of Pn.2 2 3 read-write 0 Pn.2 is 0 0 1 Pn.2 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0xFFFF IBS0 Interrupt on Pn.0 is triggered ob both edges 0 1 read-write IEV Interrupt on Pn.0 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.0 trigger an interrupt 1 IBS1 Interrupt on Pn.1 is triggered ob both edges 1 2 read-write IEV Interrupt on Pn.1 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.1 trigger an interrupt 1 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS12 Interrupt on Pn.12 is triggered ob both edges 12 13 read-write IEV Interrupt on Pn.12 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.12 trigger an interrupt 1 IBS13 Interrupt on Pn.13 is triggered ob both edges 13 14 read-write IEV Interrupt on Pn.13 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.13 trigger an interrupt 1 IBS14 Interrupt on Pn.14 is triggered ob both edges 14 15 read-write IEV Interrupt on Pn.14 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.14 trigger an interrupt 1 IBS15 Interrupt on Pn.15 is triggered ob both edges 15 16 read-write IEV Interrupt on Pn.15 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.15 trigger an interrupt 1 IBS2 Interrupt on Pn.2 is triggered ob both edges 2 3 read-write IEV Interrupt on Pn.2 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.2 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0xFFFF IC0 Pn.0 interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.0 1 IC1 Pn.1 interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.1 1 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC12 Pn.12 interrupt flag clear 12 13 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.12 1 IC13 Pn.13 interrupt flag clear 13 14 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.13 1 IC14 Pn.14 interrupt flag clear 14 15 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.14 1 IC15 Pn.15 interrupt flag clear 15 16 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.15 1 IC2 Pn.2 interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.2 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0xFFFF IE0 Interrupt on Pn.0 enable 0 1 read-write Disable Disable interrupt on Pn.0 0 Enable Enable interrupt on Pn.0 1 IE1 Interrupt on Pn.1 enable 1 2 read-write Disable Disable interrupt on Pn.1 0 Enable Enable interrupt on Pn.1 1 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE12 Interrupt on Pn.11 enable 12 13 read-write Disable Disable interrupt on Pn.12 0 Enable Enable interrupt on Pn.12 1 IE13 Interrupt on Pn.13 enable 13 14 read-write Disable Disable interrupt on Pn.13 0 Enable Enable interrupt on Pn.13 1 IE14 Interrupt on Pn.14 enable 14 15 read-write Disable Disable interrupt on Pn.14 0 Enable Enable interrupt on Pn.14 1 IE15 Interrupt on Pn.15 enable 15 16 read-write Disable Disable interrupt on Pn.15 0 Enable Enable interrupt on Pn.15 1 IE2 Interrupt on Pn.2 enable 2 3 read-write Disable Disable interrupt on Pn.2 0 Enable Enable interrupt on Pn.2 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0xFFFF IEV0 Interrupt trigged evnet on Pn.0 0 1 read-write 0 Rising edge or High level on Pn.0 triggers an interrupt 0 1 Falling edge or Low level on Pn.0 triggers an interrupt 1 IEV1 Interrupt trigged evnet on Pn.1 1 2 read-write 0 Rising edge or High level on Pn.1 triggers an interrupt 0 1 Falling edge or Low level on Pn.1 triggers an interrupt 1 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV12 Interrupt trigged evnet on Pn.12 12 13 read-write 0 Rising edge or High level on Pn.12 triggers an interrupt 0 1 Falling edge or Low level on Pn.12 triggers an interrupt 1 IEV13 Interrupt trigged evnet on Pn.13 13 14 read-write 0 Rising edge or High level on Pn.13 triggers an interrupt 0 1 Falling edge or Low level on Pn.13 triggers an interrupt 1 IEV14 Interrupt trigged evnet on Pn.14 14 15 read-write 0 Rising edge or High level on Pn.14 triggers an interrupt 0 1 Falling edge or Low level on Pn.14 triggers an interrupt 1 IEV15 Interrupt trigged evnet on Pn.15 15 16 read-write 0 Rising edge or High level on Pn.15 triggers an interrupt 0 1 Falling edge or Low level on Pn.15 triggers an interrupt 1 IEV2 Interrupt trigged evnet on Pn.2 2 3 read-write 0 Rising edge or High level on Pn.2 triggers an interrupt 0 1 Falling edge or Low level on Pn.2 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0xFFFF IS0 Interrupt on Pn.0 is event or edge sensitive 0 1 read-write Edge Interrupt on Pn.0 is edge sensitive 0 Event Interrupt on Pn.0 is event sensitive 1 IS1 Interrupt on Pn.1 is event or edge sensitive 1 2 read-write Edge Interrupt on Pn.1 is edge sensitive 0 Event Interrupt on Pn.1 is event sensitive 1 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS12 Interrupt on Pn.12 is event or edge sensitive 12 13 read-write Edge Interrupt on Pn.12 is edge sensitive 0 Event Interrupt on Pn.12 is event sensitive 1 IS13 Interrupt on Pn.13 is event or edge sensitive 13 14 read-write Edge Interrupt on Pn.13 is edge sensitive 0 Event Interrupt on Pn.13 is event sensitive 1 IS14 Interrupt on Pn.14 is event or edge sensitive 14 15 read-write Edge Interrupt on Pn.14 is edge sensitive 0 Event Interrupt on Pn.14 is event sensitive 1 IS15 Interrupt on Pn.15 is event or edge sensitive 15 16 read-write Edge Interrupt on Pn.15 is edge sensitive 0 Event Interrupt on Pn.15 is event sensitive 1 IS2 Interrupt on Pn.2 is event or edge sensitive 2 3 read-write Edge Interrupt on Pn.2 is edge sensitive 0 Event Interrupt on Pn.2 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0xFFFF MODE0 Mode of Pn.0 0 1 read-write I Pn.0 is Input pin 0 O Pn.0 is Output pin 1 MODE1 Mode of Pn.1 1 2 read-write I Pn.1 is Input pin 0 O Pn.1 is Output pin 1 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE12 Mode of Pn.12 12 13 read-write I Pn.12 is Input pin 0 O Pn.12 is Output pin 1 MODE13 Mode of Pn.13 13 14 read-write I Pn.13 is Input pin 0 O Pn.13 is Output pin 1 MODE14 Mode of Pn.14 14 15 read-write I Pn.14 is Input pin 0 O Pn.14 is Output pin 1 MODE15 Mode of Pn.15 15 16 read-write I Pn.15 is Input pin 0 O Pn.15 is Output pin 1 MODE2 Mode of Pn.2 2 3 read-write I Pn.2 is Input pin 0 O Pn.2 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 ODCTRL Offset:0x2C GPIO Port n Open-drain Control Register 0x2C 32 read-write n 0x0 0xF Pn0OC Pn.0 open-drain control 0 1 read-write Disable Disable 0 Enable Enable 1 Pn12OC Pn.12 open-drain control 12 13 read-write Disable Disable 0 Enable Enable 1 Pn13OC Pn.13 open-drain control 13 14 read-write Disable Disable 0 Enable Enable 1 Pn14OC Pn.14 open-drain control 14 15 read-write Disable Disable 0 Enable Enable 1 Pn15OC Pn.15 open-drain control 15 16 read-write Disable Disable 0 Enable Enable 1 Pn1OC Pn.1 open-drain control 1 2 read-write Disable Disable 0 Enable Enable 1 Pn2OC Pn.2 open-drain control 2 3 read-write Disable Disable 0 Enable Enable 1 Pn3OC Pn.3 open-drain control 3 4 read-write Disable Disable 0 Enable Enable 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0xFFFF IF0 Pn.0 raw interrupt flag 0 1 read-only 0 No interrupt on Pn.0 0 1 Interrupt requirements met on Pn.0 1 IF1 Pn.1 raw interrupt flag 1 2 read-only 0 No interrupt on Pn.1 0 1 Interrupt requirements met on Pn.1 1 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF12 Pn.12 raw interrupt flag 12 13 read-only 0 No interrupt on Pn.12 0 1 Interrupt requirements met on Pn.12 1 IF13 Pn.13 raw interrupt flag 13 14 read-only 0 No interrupt on Pn.13 0 1 Interrupt requirements met on Pn.13 1 IF14 Pn.14 raw interrupt flag 14 15 read-only 0 No interrupt on Pn.14 0 1 Interrupt requirements met on Pn.14 1 IF15 Pn.15 raw interrupt flag 15 16 read-only 0 No interrupt on Pn.15 0 1 Interrupt requirements met on Pn.15 1 IF2 Pn.2 raw interrupt flag 2 3 read-only 0 No interrupt on Pn.2 0 1 Interrupt requirements met on Pn.2 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_GPIO1 General Purpose I/O GPIO 0x40046000 0x0 0x2000 registers n P1 1 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0xFFFF BCLR0 Clear Pn.0 0 1 write-only No effect No effect 0 Clear Clear Pn.0 1 BCLR1 Clear Pn.1 1 2 write-only No effect No effect 0 Clear Clear Pn.1 1 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR12 Clear Pn.12 12 13 write-only No effect No effect 0 Clear Clear Pn.12 1 BCLR13 Clear Pn.13 13 14 write-only No effect No effect 0 Clear Clear Pn.13 1 BCLR14 Clear Pn.14 14 15 write-only No effect No effect 0 Clear Clear Pn.14 1 BCLR15 Clear Pn.15 15 16 write-only No effect No effect 0 Clear Clear Pn.15 1 BCLR2 Clear Pn.2 2 3 write-only No effect No effect 0 Clear Clear Pn.2 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0xFFFF BSET0 Set Pn.0 0 1 write-only No effect No effect 0 Set Set Pn.0 to 1 1 BSET1 Set Pn.1 1 2 write-only No effect No effect 0 Set Set Pn.1 to 1 1 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET12 Set Pn.12 12 13 write-only No effect No effect 0 Set Set Pn.12 to 1 1 BSET13 Set Pn.13 13 14 write-only No effect No effect 0 Set Set Pn.13 to 1 1 BSET14 Set Pn.14 14 15 write-only No effect No effect 0 Set Set Pn.14 to 1 1 BSET15 Set Pn.15 15 16 write-only No effect No effect 0 Set Set Pn.15 to 1 1 BSET2 Set Pn.2 2 3 write-only No effect No effect 0 Set Set Pn.2 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0xAAAAAAAA 0xFFFFFFFF CFG0 Configuration of Pn.0 0 2 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG1 Configuration of Pn.1 2 4 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG10 Configuration of Pn.10 20 22 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG11 Configuration of Pn.11 22 24 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG12 Configuration of Pn.12 24 26 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG13 Configuration of Pn.13 26 28 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG14 Configuration of Pn.14 28 30 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG15 Configuration of Pn.15 30 32 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG2 Configuration of Pn.2 4 6 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG3 Configuration of Pn.3 6 8 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG4 Configuration of Pn.4 8 10 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG5 Configuration of Pn.5 10 12 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG6 Configuration of Pn.6 12 14 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG7 Configuration of Pn.7 14 16 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG8 Configuration of Pn.8 16 18 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG9 Configuration of Pn.9 18 20 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0xFFFF DATA0 Data of Pn.0 0 1 read-write 0 Pn.0 is 0 0 1 Pn.0 is 1 1 DATA1 Data of Pn.1 1 2 read-write 0 Pn.1 is 0 0 1 Pn.1 is 1 1 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA12 Data of Pn.12 12 13 read-write 0 Pn.12 is 0 0 1 Pn.12 is 1 1 DATA13 Data of Pn.13 13 14 read-write 0 Pn.13 is 0 0 1 Pn.13 is 1 1 DATA14 Data of Pn.14 14 15 read-write 0 Pn.14 is 0 0 1 Pn.14 is 1 1 DATA15 Data of Pn.15 15 16 read-write 0 Pn.15 is 0 0 1 Pn.15 is 1 1 DATA2 Data of Pn.2 2 3 read-write 0 Pn.2 is 0 0 1 Pn.2 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0xFFFF IBS0 Interrupt on Pn.0 is triggered ob both edges 0 1 read-write IEV Interrupt on Pn.0 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.0 trigger an interrupt 1 IBS1 Interrupt on Pn.1 is triggered ob both edges 1 2 read-write IEV Interrupt on Pn.1 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.1 trigger an interrupt 1 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS12 Interrupt on Pn.12 is triggered ob both edges 12 13 read-write IEV Interrupt on Pn.12 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.12 trigger an interrupt 1 IBS13 Interrupt on Pn.13 is triggered ob both edges 13 14 read-write IEV Interrupt on Pn.13 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.13 trigger an interrupt 1 IBS14 Interrupt on Pn.14 is triggered ob both edges 14 15 read-write IEV Interrupt on Pn.14 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.14 trigger an interrupt 1 IBS15 Interrupt on Pn.15 is triggered ob both edges 15 16 read-write IEV Interrupt on Pn.15 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.15 trigger an interrupt 1 IBS2 Interrupt on Pn.2 is triggered ob both edges 2 3 read-write IEV Interrupt on Pn.2 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.2 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0xFFFF IC0 Pn.0 interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.0 1 IC1 Pn.1 interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.1 1 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC12 Pn.12 interrupt flag clear 12 13 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.12 1 IC13 Pn.13 interrupt flag clear 13 14 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.13 1 IC14 Pn.14 interrupt flag clear 14 15 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.14 1 IC15 Pn.15 interrupt flag clear 15 16 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.15 1 IC2 Pn.2 interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.2 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0xFFFF IE0 Interrupt on Pn.0 enable 0 1 read-write Disable Disable interrupt on Pn.0 0 Enable Enable interrupt on Pn.0 1 IE1 Interrupt on Pn.1 enable 1 2 read-write Disable Disable interrupt on Pn.1 0 Enable Enable interrupt on Pn.1 1 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE12 Interrupt on Pn.11 enable 12 13 read-write Disable Disable interrupt on Pn.12 0 Enable Enable interrupt on Pn.12 1 IE13 Interrupt on Pn.13 enable 13 14 read-write Disable Disable interrupt on Pn.13 0 Enable Enable interrupt on Pn.13 1 IE14 Interrupt on Pn.14 enable 14 15 read-write Disable Disable interrupt on Pn.14 0 Enable Enable interrupt on Pn.14 1 IE15 Interrupt on Pn.15 enable 15 16 read-write Disable Disable interrupt on Pn.15 0 Enable Enable interrupt on Pn.15 1 IE2 Interrupt on Pn.2 enable 2 3 read-write Disable Disable interrupt on Pn.2 0 Enable Enable interrupt on Pn.2 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0xFFFF IEV0 Interrupt trigged evnet on Pn.0 0 1 read-write 0 Rising edge or High level on Pn.0 triggers an interrupt 0 1 Falling edge or Low level on Pn.0 triggers an interrupt 1 IEV1 Interrupt trigged evnet on Pn.1 1 2 read-write 0 Rising edge or High level on Pn.1 triggers an interrupt 0 1 Falling edge or Low level on Pn.1 triggers an interrupt 1 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV12 Interrupt trigged evnet on Pn.12 12 13 read-write 0 Rising edge or High level on Pn.12 triggers an interrupt 0 1 Falling edge or Low level on Pn.12 triggers an interrupt 1 IEV13 Interrupt trigged evnet on Pn.13 13 14 read-write 0 Rising edge or High level on Pn.13 triggers an interrupt 0 1 Falling edge or Low level on Pn.13 triggers an interrupt 1 IEV14 Interrupt trigged evnet on Pn.14 14 15 read-write 0 Rising edge or High level on Pn.14 triggers an interrupt 0 1 Falling edge or Low level on Pn.14 triggers an interrupt 1 IEV15 Interrupt trigged evnet on Pn.15 15 16 read-write 0 Rising edge or High level on Pn.15 triggers an interrupt 0 1 Falling edge or Low level on Pn.15 triggers an interrupt 1 IEV2 Interrupt trigged evnet on Pn.2 2 3 read-write 0 Rising edge or High level on Pn.2 triggers an interrupt 0 1 Falling edge or Low level on Pn.2 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0xFFFF IS0 Interrupt on Pn.0 is event or edge sensitive 0 1 read-write Edge Interrupt on Pn.0 is edge sensitive 0 Event Interrupt on Pn.0 is event sensitive 1 IS1 Interrupt on Pn.1 is event or edge sensitive 1 2 read-write Edge Interrupt on Pn.1 is edge sensitive 0 Event Interrupt on Pn.1 is event sensitive 1 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS12 Interrupt on Pn.12 is event or edge sensitive 12 13 read-write Edge Interrupt on Pn.12 is edge sensitive 0 Event Interrupt on Pn.12 is event sensitive 1 IS13 Interrupt on Pn.13 is event or edge sensitive 13 14 read-write Edge Interrupt on Pn.13 is edge sensitive 0 Event Interrupt on Pn.13 is event sensitive 1 IS14 Interrupt on Pn.14 is event or edge sensitive 14 15 read-write Edge Interrupt on Pn.14 is edge sensitive 0 Event Interrupt on Pn.14 is event sensitive 1 IS15 Interrupt on Pn.15 is event or edge sensitive 15 16 read-write Edge Interrupt on Pn.15 is edge sensitive 0 Event Interrupt on Pn.15 is event sensitive 1 IS2 Interrupt on Pn.2 is event or edge sensitive 2 3 read-write Edge Interrupt on Pn.2 is edge sensitive 0 Event Interrupt on Pn.2 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0xFFFF MODE0 Mode of Pn.0 0 1 read-write I Pn.0 is Input pin 0 O Pn.0 is Output pin 1 MODE1 Mode of Pn.1 1 2 read-write I Pn.1 is Input pin 0 O Pn.1 is Output pin 1 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE12 Mode of Pn.12 12 13 read-write I Pn.12 is Input pin 0 O Pn.12 is Output pin 1 MODE13 Mode of Pn.13 13 14 read-write I Pn.13 is Input pin 0 O Pn.13 is Output pin 1 MODE14 Mode of Pn.14 14 15 read-write I Pn.14 is Input pin 0 O Pn.14 is Output pin 1 MODE15 Mode of Pn.15 15 16 read-write I Pn.15 is Input pin 0 O Pn.15 is Output pin 1 MODE2 Mode of Pn.2 2 3 read-write I Pn.2 is Input pin 0 O Pn.2 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 ODCTRL Offset:0x2C GPIO Port n Open-drain Control Register 0x2C 32 read-write n 0x0 0xF Pn0OC Pn.0 open-drain control 0 1 read-write Disable Disable 0 Enable Enable 1 Pn12OC Pn.12 open-drain control 12 13 read-write Disable Disable 0 Enable Enable 1 Pn13OC Pn.13 open-drain control 13 14 read-write Disable Disable 0 Enable Enable 1 Pn14OC Pn.14 open-drain control 14 15 read-write Disable Disable 0 Enable Enable 1 Pn15OC Pn.15 open-drain control 15 16 read-write Disable Disable 0 Enable Enable 1 Pn1OC Pn.1 open-drain control 1 2 read-write Disable Disable 0 Enable Enable 1 Pn2OC Pn.2 open-drain control 2 3 read-write Disable Disable 0 Enable Enable 1 Pn3OC Pn.3 open-drain control 3 4 read-write Disable Disable 0 Enable Enable 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0xFFFF IF0 Pn.0 raw interrupt flag 0 1 read-only 0 No interrupt on Pn.0 0 1 Interrupt requirements met on Pn.0 1 IF1 Pn.1 raw interrupt flag 1 2 read-only 0 No interrupt on Pn.1 0 1 Interrupt requirements met on Pn.1 1 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF12 Pn.12 raw interrupt flag 12 13 read-only 0 No interrupt on Pn.12 0 1 Interrupt requirements met on Pn.12 1 IF13 Pn.13 raw interrupt flag 13 14 read-only 0 No interrupt on Pn.13 0 1 Interrupt requirements met on Pn.13 1 IF14 Pn.14 raw interrupt flag 14 15 read-only 0 No interrupt on Pn.14 0 1 Interrupt requirements met on Pn.14 1 IF15 Pn.15 raw interrupt flag 15 16 read-only 0 No interrupt on Pn.15 0 1 Interrupt requirements met on Pn.15 1 IF2 Pn.2 raw interrupt flag 2 3 read-only 0 No interrupt on Pn.2 0 1 Interrupt requirements met on Pn.2 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_GPIO2 General Purpose I/O GPIO 0x40048000 0x0 0x2000 registers n P2 2 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0xFFFF BCLR0 Clear Pn.0 0 1 write-only No effect No effect 0 Clear Clear Pn.0 1 BCLR1 Clear Pn.1 1 2 write-only No effect No effect 0 Clear Clear Pn.1 1 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR12 Clear Pn.12 12 13 write-only No effect No effect 0 Clear Clear Pn.12 1 BCLR13 Clear Pn.13 13 14 write-only No effect No effect 0 Clear Clear Pn.13 1 BCLR14 Clear Pn.14 14 15 write-only No effect No effect 0 Clear Clear Pn.14 1 BCLR15 Clear Pn.15 15 16 write-only No effect No effect 0 Clear Clear Pn.15 1 BCLR2 Clear Pn.2 2 3 write-only No effect No effect 0 Clear Clear Pn.2 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0xFFFF BSET0 Set Pn.0 0 1 write-only No effect No effect 0 Set Set Pn.0 to 1 1 BSET1 Set Pn.1 1 2 write-only No effect No effect 0 Set Set Pn.1 to 1 1 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET12 Set Pn.12 12 13 write-only No effect No effect 0 Set Set Pn.12 to 1 1 BSET13 Set Pn.13 13 14 write-only No effect No effect 0 Set Set Pn.13 to 1 1 BSET14 Set Pn.14 14 15 write-only No effect No effect 0 Set Set Pn.14 to 1 1 BSET15 Set Pn.15 15 16 write-only No effect No effect 0 Set Set Pn.15 to 1 1 BSET2 Set Pn.2 2 3 write-only No effect No effect 0 Set Set Pn.2 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0xAAAAAAAA 0xFFFFFFFF CFG0 Configuration of Pn.0 0 2 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG1 Configuration of Pn.1 2 4 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG10 Configuration of Pn.10 20 22 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG11 Configuration of Pn.11 22 24 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG12 Configuration of Pn.12 24 26 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG13 Configuration of Pn.13 26 28 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG14 Configuration of Pn.14 28 30 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG15 Configuration of Pn.15 30 32 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG2 Configuration of Pn.2 4 6 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG3 Configuration of Pn.3 6 8 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG4 Configuration of Pn.4 8 10 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG5 Configuration of Pn.5 10 12 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG6 Configuration of Pn.6 12 14 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG7 Configuration of Pn.7 14 16 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG8 Configuration of Pn.8 16 18 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG9 Configuration of Pn.9 18 20 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0xFFFF DATA0 Data of Pn.0 0 1 read-write 0 Pn.0 is 0 0 1 Pn.0 is 1 1 DATA1 Data of Pn.1 1 2 read-write 0 Pn.1 is 0 0 1 Pn.1 is 1 1 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA12 Data of Pn.12 12 13 read-write 0 Pn.12 is 0 0 1 Pn.12 is 1 1 DATA13 Data of Pn.13 13 14 read-write 0 Pn.13 is 0 0 1 Pn.13 is 1 1 DATA14 Data of Pn.14 14 15 read-write 0 Pn.14 is 0 0 1 Pn.14 is 1 1 DATA15 Data of Pn.15 15 16 read-write 0 Pn.15 is 0 0 1 Pn.15 is 1 1 DATA2 Data of Pn.2 2 3 read-write 0 Pn.2 is 0 0 1 Pn.2 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0xFFFF IBS0 Interrupt on Pn.0 is triggered ob both edges 0 1 read-write IEV Interrupt on Pn.0 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.0 trigger an interrupt 1 IBS1 Interrupt on Pn.1 is triggered ob both edges 1 2 read-write IEV Interrupt on Pn.1 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.1 trigger an interrupt 1 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS12 Interrupt on Pn.12 is triggered ob both edges 12 13 read-write IEV Interrupt on Pn.12 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.12 trigger an interrupt 1 IBS13 Interrupt on Pn.13 is triggered ob both edges 13 14 read-write IEV Interrupt on Pn.13 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.13 trigger an interrupt 1 IBS14 Interrupt on Pn.14 is triggered ob both edges 14 15 read-write IEV Interrupt on Pn.14 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.14 trigger an interrupt 1 IBS15 Interrupt on Pn.15 is triggered ob both edges 15 16 read-write IEV Interrupt on Pn.15 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.15 trigger an interrupt 1 IBS2 Interrupt on Pn.2 is triggered ob both edges 2 3 read-write IEV Interrupt on Pn.2 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.2 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0xFFFF IC0 Pn.0 interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.0 1 IC1 Pn.1 interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.1 1 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC12 Pn.12 interrupt flag clear 12 13 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.12 1 IC13 Pn.13 interrupt flag clear 13 14 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.13 1 IC14 Pn.14 interrupt flag clear 14 15 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.14 1 IC15 Pn.15 interrupt flag clear 15 16 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.15 1 IC2 Pn.2 interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.2 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0xFFFF IE0 Interrupt on Pn.0 enable 0 1 read-write Disable Disable interrupt on Pn.0 0 Enable Enable interrupt on Pn.0 1 IE1 Interrupt on Pn.1 enable 1 2 read-write Disable Disable interrupt on Pn.1 0 Enable Enable interrupt on Pn.1 1 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE12 Interrupt on Pn.11 enable 12 13 read-write Disable Disable interrupt on Pn.12 0 Enable Enable interrupt on Pn.12 1 IE13 Interrupt on Pn.13 enable 13 14 read-write Disable Disable interrupt on Pn.13 0 Enable Enable interrupt on Pn.13 1 IE14 Interrupt on Pn.14 enable 14 15 read-write Disable Disable interrupt on Pn.14 0 Enable Enable interrupt on Pn.14 1 IE15 Interrupt on Pn.15 enable 15 16 read-write Disable Disable interrupt on Pn.15 0 Enable Enable interrupt on Pn.15 1 IE2 Interrupt on Pn.2 enable 2 3 read-write Disable Disable interrupt on Pn.2 0 Enable Enable interrupt on Pn.2 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0xFFFF IEV0 Interrupt trigged evnet on Pn.0 0 1 read-write 0 Rising edge or High level on Pn.0 triggers an interrupt 0 1 Falling edge or Low level on Pn.0 triggers an interrupt 1 IEV1 Interrupt trigged evnet on Pn.1 1 2 read-write 0 Rising edge or High level on Pn.1 triggers an interrupt 0 1 Falling edge or Low level on Pn.1 triggers an interrupt 1 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV12 Interrupt trigged evnet on Pn.12 12 13 read-write 0 Rising edge or High level on Pn.12 triggers an interrupt 0 1 Falling edge or Low level on Pn.12 triggers an interrupt 1 IEV13 Interrupt trigged evnet on Pn.13 13 14 read-write 0 Rising edge or High level on Pn.13 triggers an interrupt 0 1 Falling edge or Low level on Pn.13 triggers an interrupt 1 IEV14 Interrupt trigged evnet on Pn.14 14 15 read-write 0 Rising edge or High level on Pn.14 triggers an interrupt 0 1 Falling edge or Low level on Pn.14 triggers an interrupt 1 IEV15 Interrupt trigged evnet on Pn.15 15 16 read-write 0 Rising edge or High level on Pn.15 triggers an interrupt 0 1 Falling edge or Low level on Pn.15 triggers an interrupt 1 IEV2 Interrupt trigged evnet on Pn.2 2 3 read-write 0 Rising edge or High level on Pn.2 triggers an interrupt 0 1 Falling edge or Low level on Pn.2 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0xFFFF IS0 Interrupt on Pn.0 is event or edge sensitive 0 1 read-write Edge Interrupt on Pn.0 is edge sensitive 0 Event Interrupt on Pn.0 is event sensitive 1 IS1 Interrupt on Pn.1 is event or edge sensitive 1 2 read-write Edge Interrupt on Pn.1 is edge sensitive 0 Event Interrupt on Pn.1 is event sensitive 1 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS12 Interrupt on Pn.12 is event or edge sensitive 12 13 read-write Edge Interrupt on Pn.12 is edge sensitive 0 Event Interrupt on Pn.12 is event sensitive 1 IS13 Interrupt on Pn.13 is event or edge sensitive 13 14 read-write Edge Interrupt on Pn.13 is edge sensitive 0 Event Interrupt on Pn.13 is event sensitive 1 IS14 Interrupt on Pn.14 is event or edge sensitive 14 15 read-write Edge Interrupt on Pn.14 is edge sensitive 0 Event Interrupt on Pn.14 is event sensitive 1 IS15 Interrupt on Pn.15 is event or edge sensitive 15 16 read-write Edge Interrupt on Pn.15 is edge sensitive 0 Event Interrupt on Pn.15 is event sensitive 1 IS2 Interrupt on Pn.2 is event or edge sensitive 2 3 read-write Edge Interrupt on Pn.2 is edge sensitive 0 Event Interrupt on Pn.2 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0xFFFF MODE0 Mode of Pn.0 0 1 read-write I Pn.0 is Input pin 0 O Pn.0 is Output pin 1 MODE1 Mode of Pn.1 1 2 read-write I Pn.1 is Input pin 0 O Pn.1 is Output pin 1 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE12 Mode of Pn.12 12 13 read-write I Pn.12 is Input pin 0 O Pn.12 is Output pin 1 MODE13 Mode of Pn.13 13 14 read-write I Pn.13 is Input pin 0 O Pn.13 is Output pin 1 MODE14 Mode of Pn.14 14 15 read-write I Pn.14 is Input pin 0 O Pn.14 is Output pin 1 MODE15 Mode of Pn.15 15 16 read-write I Pn.15 is Input pin 0 O Pn.15 is Output pin 1 MODE2 Mode of Pn.2 2 3 read-write I Pn.2 is Input pin 0 O Pn.2 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 ODCTRL Offset:0x2C GPIO Port n Open-drain Control Register 0x2C 32 read-write n 0x0 0xF Pn0OC Pn.0 open-drain control 0 1 read-write Disable Disable 0 Enable Enable 1 Pn12OC Pn.12 open-drain control 12 13 read-write Disable Disable 0 Enable Enable 1 Pn13OC Pn.13 open-drain control 13 14 read-write Disable Disable 0 Enable Enable 1 Pn14OC Pn.14 open-drain control 14 15 read-write Disable Disable 0 Enable Enable 1 Pn15OC Pn.15 open-drain control 15 16 read-write Disable Disable 0 Enable Enable 1 Pn1OC Pn.1 open-drain control 1 2 read-write Disable Disable 0 Enable Enable 1 Pn2OC Pn.2 open-drain control 2 3 read-write Disable Disable 0 Enable Enable 1 Pn3OC Pn.3 open-drain control 3 4 read-write Disable Disable 0 Enable Enable 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0xFFFF IF0 Pn.0 raw interrupt flag 0 1 read-only 0 No interrupt on Pn.0 0 1 Interrupt requirements met on Pn.0 1 IF1 Pn.1 raw interrupt flag 1 2 read-only 0 No interrupt on Pn.1 0 1 Interrupt requirements met on Pn.1 1 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF12 Pn.12 raw interrupt flag 12 13 read-only 0 No interrupt on Pn.12 0 1 Interrupt requirements met on Pn.12 1 IF13 Pn.13 raw interrupt flag 13 14 read-only 0 No interrupt on Pn.13 0 1 Interrupt requirements met on Pn.13 1 IF14 Pn.14 raw interrupt flag 14 15 read-only 0 No interrupt on Pn.14 0 1 Interrupt requirements met on Pn.14 1 IF15 Pn.15 raw interrupt flag 15 16 read-only 0 No interrupt on Pn.15 0 1 Interrupt requirements met on Pn.15 1 IF2 Pn.2 raw interrupt flag 2 3 read-only 0 No interrupt on Pn.2 0 1 Interrupt requirements met on Pn.2 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_GPIO3 General Purpose I/O GPIO 0x4004A000 0x0 0x2000 registers n P3 3 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0xFFFF BCLR0 Clear Pn.0 0 1 write-only No effect No effect 0 Clear Clear Pn.0 1 BCLR1 Clear Pn.1 1 2 write-only No effect No effect 0 Clear Clear Pn.1 1 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR12 Clear Pn.12 12 13 write-only No effect No effect 0 Clear Clear Pn.12 1 BCLR13 Clear Pn.13 13 14 write-only No effect No effect 0 Clear Clear Pn.13 1 BCLR14 Clear Pn.14 14 15 write-only No effect No effect 0 Clear Clear Pn.14 1 BCLR15 Clear Pn.15 15 16 write-only No effect No effect 0 Clear Clear Pn.15 1 BCLR2 Clear Pn.2 2 3 write-only No effect No effect 0 Clear Clear Pn.2 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0xFFFF BSET0 Set Pn.0 0 1 write-only No effect No effect 0 Set Set Pn.0 to 1 1 BSET1 Set Pn.1 1 2 write-only No effect No effect 0 Set Set Pn.1 to 1 1 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET12 Set Pn.12 12 13 write-only No effect No effect 0 Set Set Pn.12 to 1 1 BSET13 Set Pn.13 13 14 write-only No effect No effect 0 Set Set Pn.13 to 1 1 BSET14 Set Pn.14 14 15 write-only No effect No effect 0 Set Set Pn.14 to 1 1 BSET15 Set Pn.15 15 16 write-only No effect No effect 0 Set Set Pn.15 to 1 1 BSET2 Set Pn.2 2 3 write-only No effect No effect 0 Set Set Pn.2 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0xAAAAAAAA 0xFFFFFFFF CFG0 Configuration of Pn.0 0 2 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG1 Configuration of Pn.1 2 4 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG10 Configuration of Pn.10 20 22 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG11 Configuration of Pn.11 22 24 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG12 Configuration of Pn.12 24 26 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG13 Configuration of Pn.13 26 28 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG14 Configuration of Pn.14 28 30 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG15 Configuration of Pn.15 30 32 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG2 Configuration of Pn.2 4 6 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG3 Configuration of Pn.3 6 8 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG4 Configuration of Pn.4 8 10 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG5 Configuration of Pn.5 10 12 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG6 Configuration of Pn.6 12 14 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG7 Configuration of Pn.7 14 16 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG8 Configuration of Pn.8 16 18 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 CFG9 Configuration of Pn.9 18 20 read-write 00b Enable pull-up resistor 0 01b Enable pull-down resistor 1 10b No pull-up/pull-down resistor enabled 2 11b Repeater mode 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0xFFFF DATA0 Data of Pn.0 0 1 read-write 0 Pn.0 is 0 0 1 Pn.0 is 1 1 DATA1 Data of Pn.1 1 2 read-write 0 Pn.1 is 0 0 1 Pn.1 is 1 1 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA12 Data of Pn.12 12 13 read-write 0 Pn.12 is 0 0 1 Pn.12 is 1 1 DATA13 Data of Pn.13 13 14 read-write 0 Pn.13 is 0 0 1 Pn.13 is 1 1 DATA14 Data of Pn.14 14 15 read-write 0 Pn.14 is 0 0 1 Pn.14 is 1 1 DATA15 Data of Pn.15 15 16 read-write 0 Pn.15 is 0 0 1 Pn.15 is 1 1 DATA2 Data of Pn.2 2 3 read-write 0 Pn.2 is 0 0 1 Pn.2 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0xFFFF IBS0 Interrupt on Pn.0 is triggered ob both edges 0 1 read-write IEV Interrupt on Pn.0 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.0 trigger an interrupt 1 IBS1 Interrupt on Pn.1 is triggered ob both edges 1 2 read-write IEV Interrupt on Pn.1 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.1 trigger an interrupt 1 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS12 Interrupt on Pn.12 is triggered ob both edges 12 13 read-write IEV Interrupt on Pn.12 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.12 trigger an interrupt 1 IBS13 Interrupt on Pn.13 is triggered ob both edges 13 14 read-write IEV Interrupt on Pn.13 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.13 trigger an interrupt 1 IBS14 Interrupt on Pn.14 is triggered ob both edges 14 15 read-write IEV Interrupt on Pn.14 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.14 trigger an interrupt 1 IBS15 Interrupt on Pn.15 is triggered ob both edges 15 16 read-write IEV Interrupt on Pn.15 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.15 trigger an interrupt 1 IBS2 Interrupt on Pn.2 is triggered ob both edges 2 3 read-write IEV Interrupt on Pn.2 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.2 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0xFFFF IC0 Pn.0 interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.0 1 IC1 Pn.1 interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.1 1 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC12 Pn.12 interrupt flag clear 12 13 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.12 1 IC13 Pn.13 interrupt flag clear 13 14 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.13 1 IC14 Pn.14 interrupt flag clear 14 15 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.14 1 IC15 Pn.15 interrupt flag clear 15 16 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.15 1 IC2 Pn.2 interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.2 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0xFFFF IE0 Interrupt on Pn.0 enable 0 1 read-write Disable Disable interrupt on Pn.0 0 Enable Enable interrupt on Pn.0 1 IE1 Interrupt on Pn.1 enable 1 2 read-write Disable Disable interrupt on Pn.1 0 Enable Enable interrupt on Pn.1 1 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE12 Interrupt on Pn.11 enable 12 13 read-write Disable Disable interrupt on Pn.12 0 Enable Enable interrupt on Pn.12 1 IE13 Interrupt on Pn.13 enable 13 14 read-write Disable Disable interrupt on Pn.13 0 Enable Enable interrupt on Pn.13 1 IE14 Interrupt on Pn.14 enable 14 15 read-write Disable Disable interrupt on Pn.14 0 Enable Enable interrupt on Pn.14 1 IE15 Interrupt on Pn.15 enable 15 16 read-write Disable Disable interrupt on Pn.15 0 Enable Enable interrupt on Pn.15 1 IE2 Interrupt on Pn.2 enable 2 3 read-write Disable Disable interrupt on Pn.2 0 Enable Enable interrupt on Pn.2 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0xFFFF IEV0 Interrupt trigged evnet on Pn.0 0 1 read-write 0 Rising edge or High level on Pn.0 triggers an interrupt 0 1 Falling edge or Low level on Pn.0 triggers an interrupt 1 IEV1 Interrupt trigged evnet on Pn.1 1 2 read-write 0 Rising edge or High level on Pn.1 triggers an interrupt 0 1 Falling edge or Low level on Pn.1 triggers an interrupt 1 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV12 Interrupt trigged evnet on Pn.12 12 13 read-write 0 Rising edge or High level on Pn.12 triggers an interrupt 0 1 Falling edge or Low level on Pn.12 triggers an interrupt 1 IEV13 Interrupt trigged evnet on Pn.13 13 14 read-write 0 Rising edge or High level on Pn.13 triggers an interrupt 0 1 Falling edge or Low level on Pn.13 triggers an interrupt 1 IEV14 Interrupt trigged evnet on Pn.14 14 15 read-write 0 Rising edge or High level on Pn.14 triggers an interrupt 0 1 Falling edge or Low level on Pn.14 triggers an interrupt 1 IEV15 Interrupt trigged evnet on Pn.15 15 16 read-write 0 Rising edge or High level on Pn.15 triggers an interrupt 0 1 Falling edge or Low level on Pn.15 triggers an interrupt 1 IEV2 Interrupt trigged evnet on Pn.2 2 3 read-write 0 Rising edge or High level on Pn.2 triggers an interrupt 0 1 Falling edge or Low level on Pn.2 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0xFFFF IS0 Interrupt on Pn.0 is event or edge sensitive 0 1 read-write Edge Interrupt on Pn.0 is edge sensitive 0 Event Interrupt on Pn.0 is event sensitive 1 IS1 Interrupt on Pn.1 is event or edge sensitive 1 2 read-write Edge Interrupt on Pn.1 is edge sensitive 0 Event Interrupt on Pn.1 is event sensitive 1 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS12 Interrupt on Pn.12 is event or edge sensitive 12 13 read-write Edge Interrupt on Pn.12 is edge sensitive 0 Event Interrupt on Pn.12 is event sensitive 1 IS13 Interrupt on Pn.13 is event or edge sensitive 13 14 read-write Edge Interrupt on Pn.13 is edge sensitive 0 Event Interrupt on Pn.13 is event sensitive 1 IS14 Interrupt on Pn.14 is event or edge sensitive 14 15 read-write Edge Interrupt on Pn.14 is edge sensitive 0 Event Interrupt on Pn.14 is event sensitive 1 IS15 Interrupt on Pn.15 is event or edge sensitive 15 16 read-write Edge Interrupt on Pn.15 is edge sensitive 0 Event Interrupt on Pn.15 is event sensitive 1 IS2 Interrupt on Pn.2 is event or edge sensitive 2 3 read-write Edge Interrupt on Pn.2 is edge sensitive 0 Event Interrupt on Pn.2 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0xFFFF MODE0 Mode of Pn.0 0 1 read-write I Pn.0 is Input pin 0 O Pn.0 is Output pin 1 MODE1 Mode of Pn.1 1 2 read-write I Pn.1 is Input pin 0 O Pn.1 is Output pin 1 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE12 Mode of Pn.12 12 13 read-write I Pn.12 is Input pin 0 O Pn.12 is Output pin 1 MODE13 Mode of Pn.13 13 14 read-write I Pn.13 is Input pin 0 O Pn.13 is Output pin 1 MODE14 Mode of Pn.14 14 15 read-write I Pn.14 is Input pin 0 O Pn.14 is Output pin 1 MODE15 Mode of Pn.15 15 16 read-write I Pn.15 is Input pin 0 O Pn.15 is Output pin 1 MODE2 Mode of Pn.2 2 3 read-write I Pn.2 is Input pin 0 O Pn.2 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 ODCTRL Offset:0x2C GPIO Port n Open-drain Control Register 0x2C 32 read-write n 0x0 0xF Pn0OC Pn.0 open-drain control 0 1 read-write Disable Disable 0 Enable Enable 1 Pn12OC Pn.12 open-drain control 12 13 read-write Disable Disable 0 Enable Enable 1 Pn13OC Pn.13 open-drain control 13 14 read-write Disable Disable 0 Enable Enable 1 Pn14OC Pn.14 open-drain control 14 15 read-write Disable Disable 0 Enable Enable 1 Pn15OC Pn.15 open-drain control 15 16 read-write Disable Disable 0 Enable Enable 1 Pn1OC Pn.1 open-drain control 1 2 read-write Disable Disable 0 Enable Enable 1 Pn2OC Pn.2 open-drain control 2 3 read-write Disable Disable 0 Enable Enable 1 Pn3OC Pn.3 open-drain control 3 4 read-write Disable Disable 0 Enable Enable 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0xFFFF IF0 Pn.0 raw interrupt flag 0 1 read-only 0 No interrupt on Pn.0 0 1 Interrupt requirements met on Pn.0 1 IF1 Pn.1 raw interrupt flag 1 2 read-only 0 No interrupt on Pn.1 0 1 Interrupt requirements met on Pn.1 1 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF12 Pn.12 raw interrupt flag 12 13 read-only 0 No interrupt on Pn.12 0 1 Interrupt requirements met on Pn.12 1 IF13 Pn.13 raw interrupt flag 13 14 read-only 0 No interrupt on Pn.13 0 1 Interrupt requirements met on Pn.13 1 IF14 Pn.14 raw interrupt flag 14 15 read-only 0 No interrupt on Pn.14 0 1 Interrupt requirements met on Pn.14 1 IF15 Pn.15 raw interrupt flag 15 16 read-only 0 No interrupt on Pn.15 0 1 Interrupt requirements met on Pn.15 1 IF2 Pn.2 raw interrupt flag 2 3 read-only 0 No interrupt on Pn.2 0 1 Interrupt requirements met on Pn.2 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_I2C0 I2C0 I2C 0x40018000 0x0 0x2000 registers n I2C0 27 CTRL Offset:0x00 I2Cn Control Register 0x0 32 read-write n 0x0 0x1B6 ACK ACK assert flag 2 3 read-write No Master: No action/Slave: Assert NACK after receiving 0 Assert Assert ACK during the acknowledge clock pulse on SCLn 1 I2CEN I2Cn interface enable 8 9 read-write Disable Disable I2C 0 Enable Enable I2C 1 NACK NACK assert flag 1 2 read-write No action No action 0 Assert Assert NACK during the acknowledge clock pulse on SCLn 1 STA START assert flag 5 6 read-write No action No START condition or Repeated START condition will be generated 0 Assert Enter master mode and transmit a START or Repeated START condition 1 STO STOP assert flag 4 5 read-write Idle STOP condition idle 0 Assert Transmit a STOP condition in master mode, or recover from an error condition in slave mode 1 MMCTRL Offset:0x30 I2Cn Monitor Mode Control Register 0x30 32 read-write n 0x0 0x7 MATCH_ALL Match address selection 2 3 read-write I2Cn_SLVADDR0~3 Interrupt will only be generated when the address matches one of the I2Cn_SLVADDR0~3 register 0 All Interrupt will be generated on ANY address received if in monitor mode 1 MMEN Monitor mode enable 0 1 read-write Disable Disable monitor mode 0 Enable Enable monitor mode 1 SCLOEN SCLn output enable 1 2 read-write Disable Disable SCLn output, SCLn is forced High 0 Enable I2C module may hold the SCLn Low until it has time to respond to an I2C interrupt 1 RXDATA Offset:0x0C I2Cn RX Data Register 0xC 32 read-only n 0x0 0xFF Data RX Data received when RX_DN=1 0 8 read-only SCLHT Offset:0x20 I2Cn SCL High Time Register 0x20 32 read-write n 0x4 0xFF SCLH SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle 0 8 read-write SCLLT Offset:0x24 I2Cn SCL Low Time Register 0x24 32 read-write n 0x4 0xFF SCLL SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle 0 8 read-write SLVADDR0 Offset:0x10 I2Cn Slave Address 0 Register 0x10 32 read-write n 0x0 0xC00003FF ADDR I2Cn slave address 0 0 10 read-write ADD_MODE Slave address mode 31 32 read-write 0 7-bit slave address mode 0 1 10-bit slave address mode 1 GCEN General call address enable 30 31 read-write Disable Disable general call address 0 Enable Enable general call address (0x0) 1 SLVADDR1 Offset:0x14 I2Cn Slave Address 1 Register 0x14 32 read-write n 0x0 0x3FF ADDR I2Cn slave address 1 0 10 read-write SLVADDR2 Offset:0x18 I2Cn Slave Address 2 Register 0x18 32 read-write n 0x0 0x3FF ADDR I2Cn slave address 2 0 10 read-write SLVADDR3 Offset:0x1C I2Cn Slave Address 3 Register 0x1C 32 read-write n 0x0 0x3FF ADDR I2Cn slave address 3 0 10 read-write STAT Offset:0x04 I2Cn Status Register 0x4 32 read-write n 0x0 0x83FF ACK_STAT ACK done status 1 2 read-only No No ACK received 0 Done Receive an ACK 1 I2CIF I2C interrupt flag 15 16 read-write 0 I2C status doesn't change 0 1 I2C status changes 1 LOST_ARB Lost arbitration status 8 9 read-only 0 Not lost arbitration 0 1 Lost arbitration 1 MST I2C master/slave status 5 6 read-only Slave Act as Slave 0 Master Act as Master 1 NACK_STAT NACK done status 2 3 read-only No No NACK received 0 Done Receive a NACK 1 RX_DN RX done status 0 1 read-only Not done No RX with ACK/NACK transfer 0 Done 8-bit RX with ACK/NACK transfer 1 SLV_RX_HIT Slave RX address hit flag 6 7 read-only 0 No matched slave address 0 1 Slave address hit, and is called for RX 1 SLV_TX_HIT Slave TX address hit flag 7 8 read-only 0 No matched slave address 0 1 Slave address hit, and is called for TX 1 START_DN START done status 4 5 read-only No No START condition 0 Assert Transmit or receive a START condition 1 STOP_DN STOP done status 3 4 read-only No No STOP condition 0 Done Transmit or receive a STOP condition 1 TIMEOUT Time-out status 9 10 read-only 0 No timeout 0 1 Timeout 1 TOCTRL Offset:0x2C I2Cn Timeout Control Register 0x2C 32 read-write n 0x0 0xFFFF TO Timeout period time = TO*32*I2Cn_PCLK cycle 0 16 read-write TXDATA Offset:0x08 I2Cn TX Data Register 0x8 32 read-write n 0x0 0xFF Data TX Data 0 8 read-write SN_I2C1 I2C0 I2C 0x4005A000 0x0 0x2000 registers n I2C1 28 CTRL Offset:0x00 I2Cn Control Register 0x0 32 read-write n 0x0 0x1B6 ACK ACK assert flag 2 3 read-write No Master: No action/Slave: Assert NACK after receiving 0 Assert Assert ACK during the acknowledge clock pulse on SCLn 1 I2CEN I2Cn interface enable 8 9 read-write Disable Disable I2C 0 Enable Enable I2C 1 NACK NACK assert flag 1 2 read-write No action No action 0 Assert Assert NACK during the acknowledge clock pulse on SCLn 1 STA START assert flag 5 6 read-write No action No START condition or Repeated START condition will be generated 0 Assert Enter master mode and transmit a START or Repeated START condition 1 STO STOP assert flag 4 5 read-write Idle STOP condition idle 0 Assert Transmit a STOP condition in master mode, or recover from an error condition in slave mode 1 MMCTRL Offset:0x30 I2Cn Monitor Mode Control Register 0x30 32 read-write n 0x0 0x7 MATCH_ALL Match address selection 2 3 read-write I2Cn_SLVADDR0~3 Interrupt will only be generated when the address matches one of the I2Cn_SLVADDR0~3 register 0 All Interrupt will be generated on ANY address received if in monitor mode 1 MMEN Monitor mode enable 0 1 read-write Disable Disable monitor mode 0 Enable Enable monitor mode 1 SCLOEN SCLn output enable 1 2 read-write Disable Disable SCLn output, SCLn is forced High 0 Enable I2C module may hold the SCLn Low until it has time to respond to an I2C interrupt 1 RXDATA Offset:0x0C I2Cn RX Data Register 0xC 32 read-only n 0x0 0xFF Data RX Data received when RX_DN=1 0 8 read-only SCLHT Offset:0x20 I2Cn SCL High Time Register 0x20 32 read-write n 0x4 0xFF SCLH SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle 0 8 read-write SCLLT Offset:0x24 I2Cn SCL Low Time Register 0x24 32 read-write n 0x4 0xFF SCLL SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle 0 8 read-write SLVADDR0 Offset:0x10 I2Cn Slave Address 0 Register 0x10 32 read-write n 0x0 0xC00003FF ADDR I2Cn slave address 0 0 10 read-write ADD_MODE Slave address mode 31 32 read-write 0 7-bit slave address mode 0 1 10-bit slave address mode 1 GCEN General call address enable 30 31 read-write Disable Disable general call address 0 Enable Enable general call address (0x0) 1 SLVADDR1 Offset:0x14 I2Cn Slave Address 1 Register 0x14 32 read-write n 0x0 0x3FF ADDR I2Cn slave address 1 0 10 read-write SLVADDR2 Offset:0x18 I2Cn Slave Address 2 Register 0x18 32 read-write n 0x0 0x3FF ADDR I2Cn slave address 2 0 10 read-write SLVADDR3 Offset:0x1C I2Cn Slave Address 3 Register 0x1C 32 read-write n 0x0 0x3FF ADDR I2Cn slave address 3 0 10 read-write STAT Offset:0x04 I2Cn Status Register 0x4 32 read-write n 0x0 0x83FF ACK_STAT ACK done status 1 2 read-only No No ACK received 0 Done Receive an ACK 1 I2CIF I2C interrupt flag 15 16 read-write 0 I2C status doesn't change 0 1 I2C status changes 1 LOST_ARB Lost arbitration status 8 9 read-only 0 Not lost arbitration 0 1 Lost arbitration 1 MST I2C master/slave status 5 6 read-only Slave Act as Slave 0 Master Act as Master 1 NACK_STAT NACK done status 2 3 read-only No No NACK received 0 Done Receive a NACK 1 RX_DN RX done status 0 1 read-only Not done No RX with ACK/NACK transfer 0 Done 8-bit RX with ACK/NACK transfer 1 SLV_RX_HIT Slave RX address hit flag 6 7 read-only 0 No matched slave address 0 1 Slave address hit, and is called for RX 1 SLV_TX_HIT Slave TX address hit flag 7 8 read-only 0 No matched slave address 0 1 Slave address hit, and is called for TX 1 START_DN START done status 4 5 read-only No No START condition 0 Assert Transmit or receive a START condition 1 STOP_DN STOP done status 3 4 read-only No No STOP condition 0 Done Transmit or receive a STOP condition 1 TIMEOUT Time-out status 9 10 read-only 0 No timeout 0 1 Timeout 1 TOCTRL Offset:0x2C I2Cn Timeout Control Register 0x2C 32 read-write n 0x0 0xFFFF TO Timeout period time = TO*32*I2Cn_PCLK cycle 0 16 read-write TXDATA Offset:0x08 I2Cn TX Data Register 0x8 32 read-write n 0x0 0xFF Data TX Data 0 8 read-write SN_I2S I2S I2S 0x4001A000 0x0 0x2000 registers n I2S 22 CLK Offset:0x04 I2S Clock Register 0x4 32 read-write n 0x100 0xFF1F BCLKDIV BCLK divider 8 16 read-write MCLKDIV MCLK divider 0 3 read-write 0 MCLK=MCLK source 0 1 MCLK=MCLK source/2 1 2 MCLK=MCLK source/4 2 3 MCLK=MCLK source/6 3 4 MCLK=MCLK source/8 4 5 MCLK=MCLK source/10 5 6 MCLK=MCLK source/12 6 7 MCLK=MCLK source/14 7 MCLKOEN MLCK output enable 3 4 read-write Disable Disable MCLK output 0 Enable Enable MCLK output 1 MCLKSEL MLCK source selection 4 5 read-write I2S_PCLK MCLK source of master is from I2S_PCLK 0 Audio external high-speed X'tal MCLK source of master is from external high-speed X'tal for Audio and Audio clock prescaler out 1 CTRL Offset:0x00 I2S Control Register 0x0 32 read-write n 0x1F33400 0xC1F77FFF CHLENGTH Bit number of single channel 20 25 read-write 10 11 bits 10 11 12 bits 11 12 13 bits 12 13 14 bits 13 14 15 bits 14 15 16 bits 15 16 17 bits 16 17 18 bits 17 18 19 bits 18 19 20 bits 19 20 21 bits 20 21 22 bits 21 22 23 bits 22 23 24 bits 23 24 25 bits 24 25 26 bits 25 26 27 bits 26 27 28 bits 27 28 29 bits 28 29 30 bits 29 30 31 bits 30 31 32 bits (Max) 31 7 8 bits 7 8 9 bits 8 9 10 bits 9 CLRRXFIFO Clear I2S RX FIFO 9 10 write-only No effect None 0 Reset Rx FIFO None 1 CLRTXFIFO Clear I2S TX FIFO 8 9 write-only No effect No effect 0 Reset TX FIFO None 1 DL Data length 10 12 read-write 8 Data length=8 bits 0 16 Data length=16 bits 1 24 Data length=24 bits 2 32 Data length=32 bits 3 FORMAT I2S operation format 4 6 read-write 00b Standard I2S format 0 01b Left-justified format 1 10b Right(MSB)-justified format 2 11b DSP mode format 3 I2SEN I2S enable 31 32 read-write Disable Disable I2S 0 Enable Enable I2S 1 I2SMOD I2S mode select bit 30 31 read-write I2S mode I2S mode for external I2S interface 0 Codec mode Codec mode for internal I2S interface connected to ADC and DAC 1 MONO Mono/stereo selection 2 3 read-write Stereo Stereo mode 0 Mono Mono mode 1 MS Master/Slave selection bit 3 4 read-write Transmitter Act as Master using internally generated BCLK and WS signals. 0 Receiver Act as Slave using externally BCLK and WS signals. 1 MUTE Mute enable 1 2 read-write Disable Disable mute 0 Enable Enable mute (I2SSDA output is 0) 1 RXEN Receiver enable bit 7 8 write-only Disable None 0 Enable None 1 RXFIFOTH Rx FIFO threshold level 16 19 read-write 0 Rx FIFO threshold level=0 0 1 Rx FIFO threshold level=1 1 2 Rx FIFO threshold level=2 2 3 Rx FIFO threshold level=3 3 4 Rx FIFO threshold level=4 4 5 Rx FIFO threshold level=5 5 6 Rx FIFO threshold level=6 6 7 Rx FIFO threshold level=7 7 START Start Transmit/Receive 0 1 read-write Stop Stop transmit/receive 0 Start Start transmit/receive 1 TXEN Transmit enable bit 6 7 read-write Disable None 0 Enable None 1 TXFIFOTH Tx FIFO threshold level 12 15 read-write 0 Tx FIFO threshold level=0 0 1 Tx FIFO threshold level=1 1 2 Tx FIFO threshold level=2 2 3 Tx FIFO threshold level=3 3 4 Tx FIFO threshold level=4 4 5 Tx FIFO threshold level=5 5 6 Tx FIFO threshold level=6 6 7 Tx FIFO threshold level=7 7 IC Offset:0x14 I2S Interrupt Clear Register 0x14 32 write-only n 0x0 0xF0 RXFIFOTHIC RX FIFO threshold interrupt clear 7 8 write-only No effect No effect 0 Clear Clear RXFIFOTHIF bit 1 RXFIFOUDIC RX FIFO underflow interrupt clear 5 6 write-only No effect No effect 0 Clear Clear RXFIFOUDIF bit 1 TXFIFOOVIC TX FIFO overflow interrupt clear 4 5 write-only No effect No effect 0 Clear Clear TXFIFOOVIF bit 1 TXFIFOTHIC TX FIFO threshold interrupt clear 6 7 write-only No effect No effect 0 Clear Clear TXFIFOTHIF bit 1 IE Offset:0x0C I2S Interrupt Enable Register 0xC 32 read-write n 0x0 0xF0 RXFIFOTHIEN RX FIFO threshold interrupt enable 7 8 read-write Disable Disable RX FIFO threshold interrupt 0 Enable Enable RX FIFO threshold interrupt 1 RXFIFOUDFIEN RX FIFO underflow interrupt enable 5 6 read-write Disable Disable RX FIFO underflow interrupt 0 Enable Enable RX FIFO underflow interrupt 1 TXFIFOOVFIEN TX FIFO overflow interrupt enable 4 5 read-write Disable Disable TX FIFO overflow interrupt 0 Enable Enable TX FIFO overflow interrupt 1 TXFIFOTHIEN TX FIFO threshold interrupt enable 6 7 read-write Disable Disable TX FIFO threshold interrupt 0 Enable Enable TX FIFO threshold interrupt 1 RIS Offset:0x10 I2S Raw Interrupt Status Register 0x10 32 read-only n 0x0 0xF0 RXFIFOTHIF RX FIFO threshold interrupt flag 7 8 read-only No RX FIFO threshold interrupt None 0 RX FIFO threshold triggered None 1 RXFIFOUDIF RX FIFO underflow interrupt flag 5 6 read-only No RX FIFO underflow None 0 RX FIFO underflow None 1 TXFIFOOVIF TX FIFO overflow interrupt flag 4 5 read-only No TX FIFO overflow None 0 TX FIFO overflow None 1 TXFIFOTHIF TX FIFO threshold interrupt flag 6 7 read-only No TX FIFO threshold interrupt None 0 TX FIFO threshold triggered None 1 RXFIFO Offset:0x18 UARTn RX FIFO Register 0x18 32 read-only n 0x0 0xFFFFFFFF STATUS Offset:0x08 I2S Status Register 0x8 32 read-only n 0x2 0x1EFFC3 I2SINT I2S interrupt flag 0 1 read-only No No I2S interrupt 0 I2S interrupt occurs I2S interrupt occurs 1 RIGHTCH Current channel status 1 2 read-only Left Current channel is left channel 0 Right Current channel is right channel 1 RXFIFOEMPTY RX FIFO empty flag 11 12 read-only Not empty RX FIFO is not empty 0 Empty RX FIFO is empty 1 RXFIFOFULL RX FIFO full flag 9 10 read-only Not full RX FIFO is not full 0 Full RX FIFO is full 1 RXFIFOLV RX FIFO used level 17 21 read-only 0 0/8 RX FIFO is used (Empty) 0 1 1/8 RX FIFO is used 1 2 2/8 RX FIFO is used 2 3 3/8 RX FIFO is used 3 4 4/8 RX FIFO is used 4 5 5/8 RX FIFO is used 5 6 6/8 RX FIFO is used 6 7 7/8 RX FIFO is used 7 8 8/8 RX FIFO is used (Full) 8 RXFIFOTHF RX FIFO threshold flag 7 8 read-only 0 RXFIFOLV is less equal than RXFIFOTH 0 1 RXFIFOLV is larger than RXFIFOTH 1 TXFIFOEMPTY TX FIFO empty flag 10 11 read-only Not empty TX FIFO is not empty 0 Empty TX FIFO is empty 1 TXFIFOFULL TX FIFO full flag 8 9 read-only Not full TX FIFO is not full 0 Full TX FIFO is full 1 TXFIFOLV TX FIFO used level 12 16 read-only 0 0/8 TX FIFO is used (Empty) 0 1 1/8 TX FIFO is used 1 2 2/8 TX FIFO is used 2 3 3/8 TX FIFO is used 3 4 4/8 TX FIFO is used 4 5 5/8 TX FIFO is used 5 6 6/8 TX FIFO is used 6 7 7/8 TX FIFO is used 7 8 8/8 TX FIFO is used (Full) 8 TXFIFOTHF TX FIFO threshold flag 6 7 read-only 0 TXFIFOLV is larger equal than TXFIFOTH 0 1 TXFIFOLV is less than TXFIFOTH 1 TXFIFO Offset:0x1C UARTn TX FIFO Register 0x1C 32 write-only n 0x0 0xFFFFFFFF SN_PMU Power Management Unit PMU 0x40032000 0x0 0x2000 registers n BKP0 Offset:0x00 PMU Backup Register 0 0x0 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP1 Offset:0x04 PMU Backup Register 1 0x4 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP10 Offset:0x28 PMU Backup Register 10 0x28 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP11 Offset:0x2C PMU Backup Register 11 0x2C 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP12 Offset:0x30 PMU Backup Register 12 0x30 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP13 Offset:0x34 PMU Backup Register 13 0x34 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP14 Offset:0x38 PMU Backup Register 14 0x38 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP15 Offset:0x3C PMU Backup Register 15 0x3C 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP2 Offset:0x08 PMU Backup Register 2 0x8 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP3 Offset:0x0C PMU Backup Register 3 0xC 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP4 Offset:0x10 PMU Backup Register 4 0x10 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP5 Offset:0x14 PMU Backup Register 5 0x14 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP6 Offset:0x18 PMU Backup Register 6 0x18 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP7 Offset:0x1C PMU Backup Register 7 0x1C 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP8 Offset:0x20 PMU Backup Register 8 0x20 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write BKP9 Offset:0x24 PMU Backup Register 9 0x24 32 read-write n 0x0 0xFF BACKUPDATA Data retained during Deep power-down mode 0 8 read-write CTRL Offset:0x40 PMU Control Register 0x40 32 read-write n 0x0 0x7 DPDEN Deep Power-down mode Enable 0 1 read-write Disable No effect 0 Enable WFI instruction will make MCU enter Deep Power-down mode 1 DSLEEPEN Deep Sleep mode Enable 1 2 read-write Disable No effect 0 Enable WFI instruction will make MCU enter Deep-sleep mode 1 SLEEPEN Sleep mode Enable 2 3 read-write Disable No effect 0 Enable WFI instruction will make MCU enter Sleep mode 1 SN_RTC Real-time Clock RTC 0x40012000 0x0 0x2000 registers n RTC 31 ALMCNT Offset:0x20 RTC Alarm Counter Register 0x20 32 read-only n 0x0 0xFFFFFFFF ALMCNTV Offset:0x1C RTC Alarm Counter Reload Value Register 0x1C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF CLKS Offset:0x04 RTC Clock Source Register 0x4 32 read-write n 0x0 0x3 CLKSEL RTC clock source 0 2 read-write ILRC ILRC is RTC clock source 0 ELS XTAL ELS Xtal is RTC clock source 1 EHS XTAL clock/128 EHS Xtal/128 is RTC clock source 3 CTRL Offset:0x00 RTC Control Register 0x0 32 read-write n 0x0 0x1 RTCEN RTC enable 0 1 read-write Disable Disable RTC 0 Enable Enable RTC 1 IC Offset:0x10 RTC Interrupt Clear Register 0x10 32 write-only n 0x0 0x7 ALMIC Alarm interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear alarm interrupt flag 1 OVFIC Overflow interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear overflow interrupt flag 1 SECIC Second interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear second interrupt flag 1 IE Offset:0x08 RTC Interrupt Enable Register 0x8 32 read-write n 0x0 0x7 ALMIE Alarm interrupt enable 1 2 read-write Disable Disable alarm interrupt 0 Enable Enable alarm interrupt 1 OVFIE Overflow interrupt enable 2 3 read-write Disable Disable overflow interrupt 0 Enable Enable overflow interrupt 1 SECIE Second interrupt enable 0 1 read-write Disable Disable second interrupt 0 Enable Enable second interrupt 1 RIS Offset:0x0C RTC Raw Interrupt Status Register 0xC 32 read-only n 0x0 0x7 ALMIF Alarm interrupt flag 1 2 read-only No No alarm interrupt 0 Met alarm interrupt requirements Alarm interrupt is triggered when ALMIE=1 1 OVFIF Overflow interrupt flag 2 3 read-only No No overflow interrupt 0 Met overflow interrupt requirements Overflow interrupt is triggered when OVFIE=1 1 SECIF Second interrupt flag 0 1 read-only No No second interrupt 0 Met second interrupt requirements Second interrupt is triggered when SECIE=1 1 SECCNT Offset:0x18 RTC Second Counter Register 0x18 32 read-only n 0x0 0xFFFFFFFF SECCNTV Offset:0x14 RTC Second Counter Reload Value Register 0x14 32 read-write n 0x8000 0xFFFFF SN_SSP0 SSP0 SSP 0x4001C000 0x0 0x2000 registers n SSP0 23 CLKDIV Offset:0x08 SSPn Clock Divider Register 0x8 32 read-write n 0x0 0xFF DIV SSPn SCK=SSPn_PCLK/(2*DIV+2) 0 8 read-write CTRL0 Offset:0x00 SSPn Control Register 0 0x0 32 read-write n 0xF00 0xFFFDF DL Data length = DL[3:0]+1 8 12 read-write 1010b Data length=11 10 1011b Data length=12 11 1100b Data length=13 12 1101b Data length=14 13 1110b Data length=15 14 1111b Data length=16 15 0010b Data length=3 2 0011b Data length=4 3 0100b Data length=5 4 0101b Data length=6 5 0110b Data length=7 6 0111b Data length=8 7 1000b Data length=9 8 1001b Data length=10 9 FORMAT Interface format 4 5 read-write SPI SPI 0 SSI SSI 1 FRESET SSP FSM and FIFO Reset 6 8 write-only 00b No effect 0 11b Reset FSM and FIFO 3 LOOPBACK Loopback mode enable 1 2 read-write Disable Disable loopback mode 0 Enable Enable loopback mode 1 MS Master/Slave selection 3 4 read-write Master Act as Master 0 Slave Act as Slave 1 RXFIFOTH Rx FIFO Threshold level 15 18 read-write 000b Rx FIFO threshold level is 0 0 001b Rx FIFO threshold level is 1 1 010b Rx FIFO threshold level is 2 2 011b Rx FIFO threshold level is 3 3 100b Rx FIFO threshold level is 4 4 101b Rx FIFO threshold level is 5 5 110b Rx FIFO threshold level is 6 6 111b Rx FIFO threshold level is 7 7 SDODIS Slave data out disable 2 3 read-write Enable Enable slave data out 0 Disble Diable slave data out (MISO=0) 1 SELCTRL Source for SEL pin 19 20 read-write SEL-Low SEL pin is low level. 0 SEL-High SEL pin is high level. 1 SELDIS Auto-SEL disable bit 18 19 read-write Enable Auto-SEL Enable Auto-SEL flow control 0 Disable Auto-SEL Disable Auto-SEL flow control 1 SSPEN SSP enable 0 1 read-write Disable Disable SSP 0 Enable Enable SSP 1 TXFIFOTH TX FIFO Threshold level 12 15 read-write 000b TX FIFO threshold level is 0 0 001b TX FIFO threshold level is 1 1 010b TX FIFO threshold level is 2 2 011b TX FIFO threshold level is 3 3 100b TX FIFO threshold level is 4 4 101b TX FIFO threshold level is 5 5 110b TX FIFO threshold level is 6 6 111b TX FIFO threshold level is 7 7 CTRL1 Offset:0x04 SSPn Control Register 1 0x4 32 read-write n 0x0 0x7 CPHA Clock phase of edge sampling 2 3 read-write CPHA0 The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data 0 CPHA1 SCK 1st edge is for data transition, and receive/transmit data at 2nd edge 1 CPOL Clock priority selection 1 2 read-write Low SCK idles at low level 0 High SCK idles at high level 1 MLSB MSB/LSB seletion 0 1 read-write MSB MSB transmit first 0 LSB LSB transmit first 1 DATA Offset:0x1C SSPn Data Register 0x1C 32 read-write n 0x0 0xFFFF Data Data 0 16 read-write DF Offset:0x20 SPIn Data Fetch Register 0x20 32 read-write n 0x0 0x1 DF SPI data fetch control bit 0 1 read-write Disable Disable 0 Enable Enable when SCKn frequency is higher than 6MHz 1 IC Offset:0x18 SSPn Interrupt Clear Register 0x18 32 write-only n 0x0 0xF RXFIFOTHIC RX Interrupt flag Clear 2 3 write-only No effect No effect 0 Clear Clear RXFIFOTH flag 1 RXOVFIC RX FIFO overflow flag clear 0 1 write-only No effect No effect 0 Clear Clear RXOVF flag 1 RXTOIC RX time-out interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear RXTO flag 1 TXFIFOTHIC TX Interrupt flag Clear 3 4 write-only No effect No effect 0 Clear Clear TXFIFOTH flag 1 IE Offset:0x10 SSPn Interrupt Enable Register 0x10 32 read-write n 0x0 0xF RXFIFOTHIE RX FIFO threshold interrupt enable 2 3 read-write Disable None 0 Enable None 1 RXOVFIE RX FIFO overflow interrupt enable 0 1 read-write Disable Disable RX FIFO overflow interrupt 0 Enable Enable RX FIFO overflow interrupt 1 RXTOIE RX time-out interrupt enable 1 2 read-write Disable Disable RX time-out interrupt 0 Enable Enable RX time-out interrupt 1 TXFIFOTHIE TX FIFO threshold interrupt enable 3 4 read-write Disable None 0 Enable None 1 RIS Offset:0x14 SSPn Raw Interrupt Status Register 0x14 32 read-only n 0x0 0xF RXFIFOTHIF RX FIFO threshold interrupt flag 2 3 read-only No No RXFIFOTH interrupt 0 Met RXFIFOTH interrupt requirements RX FIFO threshold is triggered when RXFIFOTHIE=1 1 RXOVFIF RX FIFO overflow interrupt flag 0 1 read-only No RXOVF interrupt No RXOVF interrupt 0 Met RXOVF interrupt requirements RXOVF interrupt is triggered when RXOVFIE=1 1 RXTOIF RX time-out interrupt flag 1 2 read-only No RXTO interrupt No RXTO interrupt 0 Met RXTO interrupt requirements RXTO interrupt is triggered when RXTOIE=1 1 TXFIFOTHIF TX FIFO threshold interrupt flag 3 4 read-only No TXFIFOTH interrupt None 0 Met TXFIFOTH interrupt requirements TX FIFO threshold is triggered when TXFIFOTHIE=1 1 STAT Offset:0x0C SSPn Status Register 0xC 32 read-only n 0x25 0x7F BUSY Busy flag 4 5 read-only Idle SSPn is idle 0 Busy SSPn is transfering 1 RXFIFOTHF RX FIFO threshold flag 6 7 read-only RX FIFO is less equal than RXFIFOTH Data in RX FIFO is less equal than RXFIFOTH 0 RX FIFO is larger than RXFIFOTH Data in RX FIFO is larger than RXFIFOTH 1 RX_EMPTY RX FIFO empty flag 2 3 read-only 0 RX FIFO is not empty 0 1 RX FIFO is empty 1 RX_FULL RX FIFO full flag 3 4 read-only 0 RX FIFO is not full 0 1 RX FIFO is full 1 TXFIFOTHF TX FIFO threshold flag 5 6 read-only TX FIFO is larger than TXFIFOTH Data in TX FIFO is larger than TXFIFOTH 0 TX FIFO is less equal than TXFIFOTH Data in TX FIFO is less equal than TXFIFOTH 1 TX_EMPTY TX FIFO empty flag 0 1 read-only 0 TX FIFO is not empty 0 1 TX FIFO is empty 1 TX_FULL TX FIFO full flag 1 2 read-only 0 TX FIFO is not full 0 1 TX FIFO is full 1 SN_SSP1 SSP0 SSP 0x40058000 0x0 0x2000 registers n SSP1 24 CLKDIV Offset:0x08 SSPn Clock Divider Register 0x8 32 read-write n 0x0 0xFF DIV SSPn SCK=SSPn_PCLK/(2*DIV+2) 0 8 read-write CTRL0 Offset:0x00 SSPn Control Register 0 0x0 32 read-write n 0xF00 0xFFFDF DL Data length = DL[3:0]+1 8 12 read-write 1010b Data length=11 10 1011b Data length=12 11 1100b Data length=13 12 1101b Data length=14 13 1110b Data length=15 14 1111b Data length=16 15 0010b Data length=3 2 0011b Data length=4 3 0100b Data length=5 4 0101b Data length=6 5 0110b Data length=7 6 0111b Data length=8 7 1000b Data length=9 8 1001b Data length=10 9 FORMAT Interface format 4 5 read-write SPI SPI 0 SSI SSI 1 FRESET SSP FSM and FIFO Reset 6 8 write-only 00b No effect 0 11b Reset FSM and FIFO 3 LOOPBACK Loopback mode enable 1 2 read-write Disable Disable loopback mode 0 Enable Enable loopback mode 1 MS Master/Slave selection 3 4 read-write Master Act as Master 0 Slave Act as Slave 1 RXFIFOTH Rx FIFO Threshold level 15 18 read-write 000b Rx FIFO threshold level is 0 0 001b Rx FIFO threshold level is 1 1 010b Rx FIFO threshold level is 2 2 011b Rx FIFO threshold level is 3 3 100b Rx FIFO threshold level is 4 4 101b Rx FIFO threshold level is 5 5 110b Rx FIFO threshold level is 6 6 111b Rx FIFO threshold level is 7 7 SDODIS Slave data out disable 2 3 read-write Enable Enable slave data out 0 Disble Diable slave data out (MISO=0) 1 SELCTRL Source for SEL pin 19 20 read-write SEL-Low SEL pin is low level. 0 SEL-High SEL pin is high level. 1 SELDIS Auto-SEL disable bit 18 19 read-write Enable Auto-SEL Enable Auto-SEL flow control 0 Disable Auto-SEL Disable Auto-SEL flow control 1 SSPEN SSP enable 0 1 read-write Disable Disable SSP 0 Enable Enable SSP 1 TXFIFOTH TX FIFO Threshold level 12 15 read-write 000b TX FIFO threshold level is 0 0 001b TX FIFO threshold level is 1 1 010b TX FIFO threshold level is 2 2 011b TX FIFO threshold level is 3 3 100b TX FIFO threshold level is 4 4 101b TX FIFO threshold level is 5 5 110b TX FIFO threshold level is 6 6 111b TX FIFO threshold level is 7 7 CTRL1 Offset:0x04 SSPn Control Register 1 0x4 32 read-write n 0x0 0x7 CPHA Clock phase of edge sampling 2 3 read-write CPHA0 The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data 0 CPHA1 SCK 1st edge is for data transition, and receive/transmit data at 2nd edge 1 CPOL Clock priority selection 1 2 read-write Low SCK idles at low level 0 High SCK idles at high level 1 MLSB MSB/LSB seletion 0 1 read-write MSB MSB transmit first 0 LSB LSB transmit first 1 DATA Offset:0x1C SSPn Data Register 0x1C 32 read-write n 0x0 0xFFFF Data Data 0 16 read-write DF Offset:0x20 SPIn Data Fetch Register 0x20 32 read-write n 0x0 0x1 DF SPI data fetch control bit 0 1 read-write Disable Disable 0 Enable Enable when SCKn frequency is higher than 6MHz 1 IC Offset:0x18 SSPn Interrupt Clear Register 0x18 32 write-only n 0x0 0xF RXFIFOTHIC RX Interrupt flag Clear 2 3 write-only No effect No effect 0 Clear Clear RXFIFOTH flag 1 RXOVFIC RX FIFO overflow flag clear 0 1 write-only No effect No effect 0 Clear Clear RXOVF flag 1 RXTOIC RX time-out interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear RXTO flag 1 TXFIFOTHIC TX Interrupt flag Clear 3 4 write-only No effect No effect 0 Clear Clear TXFIFOTH flag 1 IE Offset:0x10 SSPn Interrupt Enable Register 0x10 32 read-write n 0x0 0xF RXFIFOTHIE RX FIFO threshold interrupt enable 2 3 read-write Disable None 0 Enable None 1 RXOVFIE RX FIFO overflow interrupt enable 0 1 read-write Disable Disable RX FIFO overflow interrupt 0 Enable Enable RX FIFO overflow interrupt 1 RXTOIE RX time-out interrupt enable 1 2 read-write Disable Disable RX time-out interrupt 0 Enable Enable RX time-out interrupt 1 TXFIFOTHIE TX FIFO threshold interrupt enable 3 4 read-write Disable None 0 Enable None 1 RIS Offset:0x14 SSPn Raw Interrupt Status Register 0x14 32 read-only n 0x0 0xF RXFIFOTHIF RX FIFO threshold interrupt flag 2 3 read-only No No RXFIFOTH interrupt 0 Met RXFIFOTH interrupt requirements RX FIFO threshold is triggered when RXFIFOTHIE=1 1 RXOVFIF RX FIFO overflow interrupt flag 0 1 read-only No RXOVF interrupt No RXOVF interrupt 0 Met RXOVF interrupt requirements RXOVF interrupt is triggered when RXOVFIE=1 1 RXTOIF RX time-out interrupt flag 1 2 read-only No RXTO interrupt No RXTO interrupt 0 Met RXTO interrupt requirements RXTO interrupt is triggered when RXTOIE=1 1 TXFIFOTHIF TX FIFO threshold interrupt flag 3 4 read-only No TXFIFOTH interrupt None 0 Met TXFIFOTH interrupt requirements TX FIFO threshold is triggered when TXFIFOTHIE=1 1 STAT Offset:0x0C SSPn Status Register 0xC 32 read-only n 0x25 0x7F BUSY Busy flag 4 5 read-only Idle SSPn is idle 0 Busy SSPn is transfering 1 RXFIFOTHF RX FIFO threshold flag 6 7 read-only RX FIFO is less equal than RXFIFOTH Data in RX FIFO is less equal than RXFIFOTH 0 RX FIFO is larger than RXFIFOTH Data in RX FIFO is larger than RXFIFOTH 1 RX_EMPTY RX FIFO empty flag 2 3 read-only 0 RX FIFO is not empty 0 1 RX FIFO is empty 1 RX_FULL RX FIFO full flag 3 4 read-only 0 RX FIFO is not full 0 1 RX FIFO is full 1 TXFIFOTHF TX FIFO threshold flag 5 6 read-only TX FIFO is larger than TXFIFOTH Data in TX FIFO is larger than TXFIFOTH 0 TX FIFO is less equal than TXFIFOTH Data in TX FIFO is less equal than TXFIFOTH 1 TX_EMPTY TX FIFO empty flag 0 1 read-only 0 TX FIFO is not empty 0 1 TX FIFO is empty 1 TX_FULL TX FIFO full flag 1 2 read-only 0 TX FIFO is not full 0 1 TX FIFO is full 1 SN_SYS0 System Control Registers SYSTEM 0x40060000 0x0 0x2000 registers n LVD 30 AHBCP Offset:0x10 AHB Clock Prescale Register 0x10 32 read-write n 0x0 0xF AHBPRE AHB clock source prescaler 0 4 read-write 0000b FAHB=FSYSCLK/1 0 0001b FAHB=FSYSCLK/2 1 0010b FAHB=FSYSCLK/4 2 0011b FAHB=FSYSCLK/8 3 0100b FAHB=FSYSCLK/16 4 0101b FAHB=FSYSCLK/32 5 0110b FAHB=FSYSCLK/64 6 0111b FAHB=FSYSCLK/128 7 1000b FAHB=FSYSCLK/256 8 1001b FAHB=FSYSCLK/512 9 ANBCTRL Offset:0x00 Analog Block Control Register 0x0 32 read-write n 0x1 0x3F5 AUEHSEN Audio external high-speed clock enable 8 9 read-write Disable Disable AUEHS X'TAL 0 Enable Enable AUEHS X'TAL 1 AUEHSFREQ AUEHS X'TAL Frequency range 9 10 read-write AUEHS X'TAL less equal than 12MHz None 0 AUEHS X'TAL less equal than 12MHz 0 AUEHS X'TAL more than 12MHz None 1 AUEHS X'TAL more than 12MHz 1 EHSEN EHS XTAL enable 4 5 read-write Disable Disable EHS Xtal 0 Enable Enable EHS Xtal 1 EHSFREQ EHS XTAL frequency range 5 6 read-write Low Less equal than 12MHz 0 High Greater than 12MHz 1 ELSEN ELS XTAL enable 2 3 read-write Disable Disable ELS Xtal 0 Enable Enable ELS Xtal 1 IHRCEN IHRC enable 0 1 read-write Disable Disable IHRC 0 Enable Enable IHRC 1 CLKCFG Offset:0x0C System Clock Configuration Register 0xC 32 read-write n 0x0 0x77 SYSCLKSEL System clock source selection 0 3 read-write IHRC IHRC is system clock 0 ILRC ILRC is system clock 1 EHS XTAL EHS Xtal is system clock 2 ELS XTAL ELS Xtal is system clock 3 PLL Output PLL is system clock 4 SYSCLKST System clock switch status 4 7 read-only IHRC IHRC is used as system clock 0 ILRC ILRC is used as system clock 1 EHS XTAL EHS XTAL is used as system clock 2 ELS XTAL ELS XTAL is used as system clock 3 PLL PLL output is used as system clock 4 CSST Offset:0x08 Clock Source Status Register 0x8 32 read-only n 0x1 0x155 AUEHSRDY Audio external high-speed clock ready flag 8 9 read-only AUEHS not ready None 0 AUEHS ready None 1 EHSRDY EHS XTAL ready flag 4 5 read-only 0 EHS Xtal is Not Ready 0 1 EHS Xtal is Ready 1 ELSRDY ELS XTAL ready flag 2 3 read-only 0 ELS Xtal is Not Ready 0 1 ELS Xtal is Ready 1 IHRCRDY IHRC ready flag 0 1 read-only 0 IHRC is Not Ready 0 1 IHRC is Ready 1 PLLRDY PLL ready flag 6 7 read-only 0 PLL is Not locked 0 1 PLL is locked 1 EXRSTCTRL Offset:0x1C External Reset Pin Control Register 0x1C 32 read-write n 0x0 0x1 RESETDIS External reset pin disable 0 1 read-write Enable P0.15 acts as External Reset pin 0 Disable P0.15 acts as GPIO pin 1 LVDCTRL Offset:0x18 LVD Control Register 0x18 32 read-write n 0x0 0xC033 LVDEN LVD enable 15 16 read-write Diable Disable LVD 0 Enable Enable LVD 1 LVDINTLVL LVD interrupt level 4 6 read-write 2.00V LVD interrupt threshold is 2.00V 0 2.40V LVD interrupt threshold is 2.40V 1 2.70V LVD interrupt threshold is 2.70V 2 3.00V LVD interrupt threshold is 3.00V 3 LVDRSTEN LVD Reset enable 14 15 read-write Diable Disable LVD reset 0 Enable Enable LVD reset 1 LVDRSTLVL LVD reset level 0 2 read-write 2.00V LVD reset threshold is 2.00V 0 2.40V LVD reset threshold is 2.40V 1 2.70V LVD reset threshold is 2.70V 2 PLLCTRL Offset:0x04 PLL Control Register 0x4 32 read-write n 0x63 0xB1FF FSEL F=POWER(2, FSEL) 8 9 read-write F=1 F=1 0 F=2 F=2 1 MSEL M: 3~31 0 5 read-write PLLCLKSEL PLL clock source 12 14 read-write IHRC 12MHz 0 EHS XTAL 10MHz~25MHz 1 PLLEN PLL enable 15 16 read-write Disable Disable PLL 0 Enable Enable PLL 1 PSEL P=PSEL*2 5 8 read-write 011b P=6 3 100b P=8 4 101b P=10 5 110b P=12 6 111b P=14 7 RSTST Offset:0x14 System Reset Status Register 0x14 32 read-write n 0x10 0x1F EXTRSTF External reset flag 3 4 read-write 0 No Extenral reset occurred 0 1 External reset occurred 1 LVDRSTF LVD reset flag 2 3 read-write 0 No LVD reset occurred 0 1 LVD reset occurred 1 PORRSTF POR reset flag 4 5 read-write 0 No POR occurred 0 1 POR occurred 1 SWRSTF Software reset flag 0 1 read-write 0 No SW reset occurred 0 1 SW reset occurred 1 WDTRSTF WDT reset flag 1 2 read-write 0 No WDT reset occurred 0 1 WDT reset occurred 1 SWDCTRL Offset:0x20 SWD Pin Control Register 0x20 32 read-write n 0x0 0x1 SWDDIS SWD pin disable 0 1 read-write Enable Enable SWD pins 0 Disable Disable SWD pins 1 SN_SYS1 System Control Registers SYSTEM 0x4005E000 0x0 0x2000 registers n AHBCLKEN Offset:0x00 AHB Clock Enable Register 0x0 32 read-write n 0x1000008 0x71F33BC8 CLKOUTSEL Clock output source selection 28 31 read-write 000b Disable 0 001b HCLK clock output 1 010b PLL clock output 2 011b ILRC clock output 3 100b IHRC clock output 4 101b ELS clock output 5 110b EHS XTAL 6 111b AUEHS XTAL 7 CMPCLKEN Enable AHB clock for Comparator 11 12 read-write Disable Disable 0 Enable Enable 1 CT16B0CLKEN Enable AHB clock for CT16B0 6 7 read-write Disable Disable 0 Enable Enable 1 CT16B1CLKEN Enable AHB clock for CT16B1 7 8 read-write Disable Disable 0 Enable Enable 1 CT32B0CLKEN Enable AHB clock for CT32B0 8 9 read-write Disable Disable 0 Enable Enable 1 CT32B1CLKEN Enable AHB clock for CT32B1 9 10 read-write Disable Disable 0 Enable Enable 1 GPIOCLKEN Enable AHB clock for GPIO 3 4 read-write Disable Disable 0 Enable Enable 1 I2C0CLKEN Enable AHB clock for I2C0 21 22 read-write Disable Disable 0 Enable Enable 1 I2C1CLKEN Enable AHB clock for I2C1 20 21 read-write Disable Disable 0 Enable Enable 1 I2SCLKEN Enable AHB clock for I2S 22 23 read-write Disable Disable 0 Enable Enable 1 RTCCLKEN Enable AHB clock for RTC 23 24 read-write Disable Disable 0 Enable Enable 1 SSP0CLKEN Enable AHB clock for SSP0 12 13 read-write Disable Disable 0 Enable Enable 1 SSP1CLKEN Enable AHB clock for SSP1 13 14 read-write Disable Disable 0 Enable Enable 1 UART0CLKEN Enable AHB clock for UART0 16 17 read-write Disable Disable 0 Enable Enable 1 UART1CLKEN Enable AHB clock for UART1 17 18 read-write Disable Disable 0 Enable Enable 1 WDTCLKEN Enable AHB clock for WDT 24 25 read-write Disable Disable 0 Enable Enable 1 APBCP0 Offset:0x04 APB Clock Prescale Register 0 0x4 32 read-write n 0x0 0x77777777 AUEHSPRE Audio external high clock source prescaler 28 31 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 AUEHSPRE Audio external high clock source prescaler 28 31 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 CMPPRE Comparator clock source prescaler 16 19 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 CT16B0PRE CT16B0 APB clock source prescaler 0 3 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 CT16B1PRE CT16B1 APB clock source prescaler 4 7 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011 HCLK/8 3 100 HCLK/16 4 CT32B0PRE CT32B0 APB clock source prescaler 8 11 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 CT32B1PRE CT32B1 APB clock source prescaler 12 15 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 SSP0PRE SSP0 APB clock source prescaler 20 23 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 SSP1PRE SSP1 APB clock source prescaler 24 27 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 APBCP1 Offset:0x08 APB Clock Prescale Register 1 0x8 32 read-write n 0x0 0xF7737777 CLKOUTPRE CLKOUT APB clock source prescaler 28 32 read-write 0000b FCLKOUT/1 0 0001b FCLKOUT/2 1 0010b FCLKOUT/4 2 0011b FCLKOUT/8 3 0100b FCLKOUT/16 4 0101b FCLKOUT/32 5 0110b FCLKOUT/64 6 0111b FCLKOUT/128 7 1000b FCLKOUT/256 8 1001b FCLKOUT/512 9 I2C0PRE I2C0 APB clock source prescaler 8 11 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 I2C1PRE I2C1 APB clock source prescaler 24 27 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 I2SPRE I2S APB clock source prescaler 12 15 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 UART0PRE UART0 APB clock source prescaler 0 3 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 UART1PRE UART1 APB clock source prescaler 4 7 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 WDTPRE WDT APB clock source prescaler 20 23 read-write 000b HCLK/1 0 001b HCLK/2 1 010b HCLK/4 2 011b HCLK/8 3 100b HCLK/16 4 101b HCLK/32 5 PRST Offset:0x0C Peripheral Reset Register 0xC 32 read-write n 0x0 0x7F33BCF CMPRST Comparator Reset 11 12 read-write 0 No effect 0 1 Reset CMP 1 CODECADRST Codec ADC reset 26 27 read-write No effect None 0 Reset WDT None 1 CODECDARST Codec DAC reset 25 26 read-write No effect None 0 Reset WDT None 1 CT16B0RST CT16B0 Reset 6 7 read-write 0 No effect 0 1 Reset CT16B0 1 CT16B1RST CT16B1 Reset 7 8 read-write 0 No effect 0 1 Reset CT16B1 1 CT32B0RST CT32B0 Reset 8 9 read-write 0 No effect 0 1 Reset CT32B0 1 CT32B1RST CT32B1 Reset 9 10 read-write 0 No effect 0 1 Reset CT32B1 1 GPIO0RST GPIO0 Reset 0 1 read-write 0 No effect 0 1 Reset GPIO0 1 GPIO1RST GPIO1 Reset 1 2 read-write 0 No effect 0 1 Reset GPIO1 1 GPIO2RST GPIO2 Reset 2 3 read-write 0 No effect 0 1 Reset GPIO2 1 GPIO3RST GPIO3 Reset 3 4 read-write 0 No effect 0 1 Reset GPIO3 1 I2C0RST I2C0 Reset 21 22 read-write 0 No effect 0 1 Reset I2C0 1 I2C1RST I2C1 Reset 20 21 read-write 0 No effect 0 1 Reset I2C1 1 I2SRST I2S Reset 22 23 read-write 0 No effect 0 1 Reset I2S 1 RTCRST RTC Reset 23 24 read-write 0 No effect 0 1 Reset RTC 1 SSP0RST SSP0 Reset 12 13 read-write 0 No effect 0 1 Reset SSP0 1 SSP1RST SSP1 Reset 13 14 read-write 0 No effect 0 1 Reset SSP1 1 UART0RST UART0 Reset 16 17 read-write 0 No effect 0 1 Reset UART0 1 UART1RST UART1 Reset 17 18 read-write 0 No effect 0 1 Reset UART1 1 WDTRST WDT Reset 24 25 read-write 0 No effect 0 1 Reset WDT 1 SN_UART0 UART0 UART 0x40016000 0x0 0x2000 registers n UART0 25 ABCTRL Offset:0x20 UARTn Auto-baud Control Register 0x20 32 read-write n 0x0 0x307 ABEOIFC Clear ABEOIF flag 8 9 write-only No effect No effect 0 Clear Clear ABEOIF bit 1 ABTOIFC Clear ABTOIF flag 9 10 write-only No effect No effect 0 Clear Clear ABTOIF bit 1 AUTORESTART Restart mode selection 2 3 read-write No restart No restart 0 Restart Auto restart in case of timeout 1 MODE Auto-baud mode selection 1 2 read-write Mode 0 Auto-baud mode 0 0 Mode 1 Auto-baud mode 1 1 START Auto-baud run bit 0 1 read-write Stop Auto-baud is not running 0 Start Auto-baud ids running 1 CTRL Offset:0x30 UARTn Control Register 0x30 32 read-write n 0xC0 0xC1 RXEN RX enable 6 7 read-write Disable Disable RX 0 Enable Enable RX 1 TXEN TX enable 7 8 read-write Disable Disable TX 0 Enable Enable TX 1 UARTEN UART enable 0 1 read-write Disable Disable UART 0 Enable Enable UART 1 DLL Offset:0x00 UARTn Divisor Latch LSB Register RB 0x0 32 read-write n 0x0 0xFF DLL DLL and DLM register determines the baud rate of UARTn 0 8 read-write DLM Offset:0x04 UARTn Divisor Latch MSB Register 0x4 32 read-write n 0x0 0xFF DLM DLL and DLM register determines the baud rate of UARTn 0 8 read-write FD Offset:0x28 UARTn Fractional Divider Register 0x28 32 read-write n 0x0 0x1FF DIVADDVAL Baud rate generation prescaler divisor value 0 4 read-write MULVAL Baud rate generation prescaler multiplier value 4 8 read-write 0000b Baud rate prescaler multiplier value is 1 0 0001b Baud rate prescaler multiplier value is 2 1 1010b Baud rate prescaler multiplier value is 11 10 1011b Baud rate prescaler multiplier value is 12 11 1100b Baud rate prescaler multiplier value is 13 12 1101b Baud rate prescaler multiplier value is 14 13 1110b Baud rate prescaler multiplier value is 15 14 1111b Baud rate prescaler multiplier value is 16 15 0010b Baud rate prescaler multiplier value is 3 2 0011b Baud rate prescaler multiplier value is 4 3 0100b Baud rate prescaler multiplier value is 5 4 0101b Baud rate prescaler multiplier value is 6 5 0110b Baud rate prescaler multiplier value is 7 6 0111b Baud rate prescaler multiplier value is 8 7 1000b Baud rate prescaler multiplier value is 9 8 1001b Baud rate prescaler multiplier value is 10 9 OVER8 Oversampling value 8 9 read-write 16 Oversampling by 16 0 8 Oversampling by 8 1 FIFOCTRL Offset:0x08 UARTn FIFO Control Register 0x8 32 write-only n 0x1 0xC7 FIFOEN FIFO enable 0 1 write-only No effect No effect 0 Enable Enable FIFO 1 RXFIFORST RX FIFO reset 1 2 write-only No impact No impact 0 Reset Reset the pointer logic in RX FIFO 1 RXTL RX trigger level 6 8 write-only Trigger level 0 1 character 0 Trigger level 1 4 character 1 Trigger level 2 8 character 2 Trigger level 3 14 character 3 TXFIFORST TX FIFO reset 2 3 write-only No impact No impact 0 Reset Reset the pointer logic in TX FIFO 1 HDEN Offset:0x34 UARTn Control Register 0x34 32 read-write n 0x0 0x1 HDEN Half-duplex mode enable 0 1 read-write Disable Disable half-duplex mode 0 Enable Enable UART 1 IE Offset:0x04 UARTn Interrupt Enable Register DLM 0x4 32 read-write n 0x0 0x317 ABEOIE ABE0 interrupt enable 8 9 read-write Disable Disable ABEO interrupt 0 Enable Enable ABEO interrupt 1 ABTOIE ABT0 interrupt enable 9 10 read-write Disable Disable ABTO interrupt 0 Enable Enable ABTO interrupt 1 RDAIE RDA interrupt enable 0 1 read-write Disable Disable RDA interrupt 0 Enable Enable RDA interrupt 1 RLSIE RLS interrupt enable 2 3 read-write Disable Disable RLS interrupt 0 Enable Enable RLS interrupt 1 TEMTIE TEMT interrupt enable 4 5 read-write Disable Disable TEMT interrupt 0 Enable Enable TEMT interrupt 1 THREIE THRE interrupt enable 1 2 read-write Disable Disable THRE interrupt 0 Enable Enable THRE interrupt 1 II Offset:0x08 UARTn Interrupt Identification Register 0x8 32 read-only n 0x41 0x3CF ABEOIF ABEO interrupt flag 8 9 read-only Not end Auto-baud has not finished 0 End Auto-baud has finished and interrupt is enabled 1 ABTOIF ABTO interrupt flag 9 10 read-only Not Time-out Auto-baud has not timed out 0 Time-out Auto-baud has timed out and interrupt is enabled 1 FIFOEN Equal to FIFOEN bits in UARTn_FIFOCTRL register 6 8 read-only INTID Interrupt ID of RX FIFO 1 4 read-only 3a THRE interrupt 1 2a RDA (Receive Data Available) 2 1 RLS (Receive Line Status) 3 2b CTI (Character Time-out Indicator) 6 3b TEMT interrupt 7 INTSTATUS Interrupt status 0 1 read-only Pending As least 1 interrupt is pending 0 No interrupt No interrupt 1 LC Offset:0x0C UARTn Line Control Register 0xC 32 read-write n 0x0 0xFF BC Break control 6 7 read-write Disable Disable break transmission 0 Enable Enable break transmission 1 DLAB Divisor Latch access 7 8 read-write Disable Disable access to Divisor Latch 0 Enable Enable access to Divisor Latch 1 PE Parity enable 3 4 read-write Disable Disable parity generation and checking 0 Enable Enable parity generation and checking 1 PS Parity selection 4 6 read-write 0 Odd parity 0 1 Even parity 1 2 Forced 1 sticky parity 2 3 Forced 0 sticky parity 3 SBS Stop bit selection 2 3 read-write 1 stop bit 1 stop bit 0 2 stop bit 2 stop bit (1.5 stop bit if WLS=0) 1 WLS Word length selection 0 2 read-write 5-bit 5-bit character 0 6-bit 6-bit character 1 7-bit 7-bit character 2 8-bit 8-bit character 3 LS Offset:0x14 UARTn Line Status Register 0x14 32 read-only n 0x60 0xFF BI Break interrupt flag 4 5 read-only No break interrupt No break interrupt 0 Break interrupt Break interrupt status is active 1 FE Framing error flag 3 4 read-only No framing error No framing error 0 Framing error Framing error status is active 1 OE Overrun error flag 1 2 read-only No overrun error No overrun error 0 Overrun error Overrun error status is active 1 PE Parity error flag 2 3 read-only No parity error No parity error 0 Parity error Parity error status is active 1 RDR Receiver data ready flag 0 1 read-only Not ready UARTn_RB FIFO is empty 0 Ready UARTn_RB FIFO contains valid data 1 RXFE Receiver FIFO error flag 7 8 read-only No RX FIFO error UARTn_RB contains no UART RX errors 0 RX FIFO error UARTn_RB contains at least 1 UART RX error 1 TEMT Transmitter empty flag 6 7 read-only Not empty THR and/or TSR contains valid data 0 Empty THR and TSR are both empty 1 THRE THR empty flag 5 6 read-only Not empty THR contains valid data 0 Empty THR (TX FIFO) is empty 1 RB Offset:0x00 UARTn Receiver Buffer Register 0x0 32 read-only n 0x0 0xFF RB The oldest received byte in UART RX FIFO 0 8 read-only SP Offset:0x1C UARTn Scratch Pad Register 0x1C 32 read-write n 0x0 0xFF PAD Pad informaton 0 8 read-write TH Offset:0x00 UARTn Transmit Holding Register RB 0x0 32 write-only n 0x0 0xFF TH The oldest byte to be transmitted in UART TX FIFO when transmitter is available 0 8 write-only SN_UART1 UART0 UART 0x40056000 0x0 0x2000 registers n UART1 26 ABCTRL Offset:0x20 UARTn Auto-baud Control Register 0x20 32 read-write n 0x0 0x307 ABEOIFC Clear ABEOIF flag 8 9 write-only No effect No effect 0 Clear Clear ABEOIF bit 1 ABTOIFC Clear ABTOIF flag 9 10 write-only No effect No effect 0 Clear Clear ABTOIF bit 1 AUTORESTART Restart mode selection 2 3 read-write No restart No restart 0 Restart Auto restart in case of timeout 1 MODE Auto-baud mode selection 1 2 read-write Mode 0 Auto-baud mode 0 0 Mode 1 Auto-baud mode 1 1 START Auto-baud run bit 0 1 read-write Stop Auto-baud is not running 0 Start Auto-baud ids running 1 CTRL Offset:0x30 UARTn Control Register 0x30 32 read-write n 0xC0 0xC1 RXEN RX enable 6 7 read-write Disable Disable RX 0 Enable Enable RX 1 TXEN TX enable 7 8 read-write Disable Disable TX 0 Enable Enable TX 1 UARTEN UART enable 0 1 read-write Disable Disable UART 0 Enable Enable UART 1 DLL Offset:0x00 UARTn Divisor Latch LSB Register RB 0x0 32 read-write n 0x0 0xFF DLL DLL and DLM register determines the baud rate of UARTn 0 8 read-write DLM Offset:0x04 UARTn Divisor Latch MSB Register 0x4 32 read-write n 0x0 0xFF DLM DLL and DLM register determines the baud rate of UARTn 0 8 read-write FD Offset:0x28 UARTn Fractional Divider Register 0x28 32 read-write n 0x0 0x1FF DIVADDVAL Baud rate generation prescaler divisor value 0 4 read-write MULVAL Baud rate generation prescaler multiplier value 4 8 read-write 0000b Baud rate prescaler multiplier value is 1 0 0001b Baud rate prescaler multiplier value is 2 1 1010b Baud rate prescaler multiplier value is 11 10 1011b Baud rate prescaler multiplier value is 12 11 1100b Baud rate prescaler multiplier value is 13 12 1101b Baud rate prescaler multiplier value is 14 13 1110b Baud rate prescaler multiplier value is 15 14 1111b Baud rate prescaler multiplier value is 16 15 0010b Baud rate prescaler multiplier value is 3 2 0011b Baud rate prescaler multiplier value is 4 3 0100b Baud rate prescaler multiplier value is 5 4 0101b Baud rate prescaler multiplier value is 6 5 0110b Baud rate prescaler multiplier value is 7 6 0111b Baud rate prescaler multiplier value is 8 7 1000b Baud rate prescaler multiplier value is 9 8 1001b Baud rate prescaler multiplier value is 10 9 OVER8 Oversampling value 8 9 read-write 16 Oversampling by 16 0 8 Oversampling by 8 1 FIFOCTRL Offset:0x08 UARTn FIFO Control Register 0x8 32 write-only n 0x1 0xC7 FIFOEN FIFO enable 0 1 write-only No effect No effect 0 Enable Enable FIFO 1 RXFIFORST RX FIFO reset 1 2 write-only No impact No impact 0 Reset Reset the pointer logic in RX FIFO 1 RXTL RX trigger level 6 8 write-only Trigger level 0 1 character 0 Trigger level 1 4 character 1 Trigger level 2 8 character 2 Trigger level 3 14 character 3 TXFIFORST TX FIFO reset 2 3 write-only No impact No impact 0 Reset Reset the pointer logic in TX FIFO 1 HDEN Offset:0x34 UARTn Control Register 0x34 32 read-write n 0x0 0x1 HDEN Half-duplex mode enable 0 1 read-write Disable Disable half-duplex mode 0 Enable Enable UART 1 IE Offset:0x04 UARTn Interrupt Enable Register DLM 0x4 32 read-write n 0x0 0x317 ABEOIE ABE0 interrupt enable 8 9 read-write Disable Disable ABEO interrupt 0 Enable Enable ABEO interrupt 1 ABTOIE ABT0 interrupt enable 9 10 read-write Disable Disable ABTO interrupt 0 Enable Enable ABTO interrupt 1 RDAIE RDA interrupt enable 0 1 read-write Disable Disable RDA interrupt 0 Enable Enable RDA interrupt 1 RLSIE RLS interrupt enable 2 3 read-write Disable Disable RLS interrupt 0 Enable Enable RLS interrupt 1 TEMTIE TEMT interrupt enable 4 5 read-write Disable Disable TEMT interrupt 0 Enable Enable TEMT interrupt 1 THREIE THRE interrupt enable 1 2 read-write Disable Disable THRE interrupt 0 Enable Enable THRE interrupt 1 II Offset:0x08 UARTn Interrupt Identification Register 0x8 32 read-only n 0x41 0x3CF ABEOIF ABEO interrupt flag 8 9 read-only Not end Auto-baud has not finished 0 End Auto-baud has finished and interrupt is enabled 1 ABTOIF ABTO interrupt flag 9 10 read-only Not Time-out Auto-baud has not timed out 0 Time-out Auto-baud has timed out and interrupt is enabled 1 FIFOEN Equal to FIFOEN bits in UARTn_FIFOCTRL register 6 8 read-only INTID Interrupt ID of RX FIFO 1 4 read-only 3a THRE interrupt 1 2a RDA (Receive Data Available) 2 1 RLS (Receive Line Status) 3 2b CTI (Character Time-out Indicator) 6 3b TEMT interrupt 7 INTSTATUS Interrupt status 0 1 read-only Pending As least 1 interrupt is pending 0 No interrupt No interrupt 1 LC Offset:0x0C UARTn Line Control Register 0xC 32 read-write n 0x0 0xFF BC Break control 6 7 read-write Disable Disable break transmission 0 Enable Enable break transmission 1 DLAB Divisor Latch access 7 8 read-write Disable Disable access to Divisor Latch 0 Enable Enable access to Divisor Latch 1 PE Parity enable 3 4 read-write Disable Disable parity generation and checking 0 Enable Enable parity generation and checking 1 PS Parity selection 4 6 read-write 0 Odd parity 0 1 Even parity 1 2 Forced 1 sticky parity 2 3 Forced 0 sticky parity 3 SBS Stop bit selection 2 3 read-write 1 stop bit 1 stop bit 0 2 stop bit 2 stop bit (1.5 stop bit if WLS=0) 1 WLS Word length selection 0 2 read-write 5-bit 5-bit character 0 6-bit 6-bit character 1 7-bit 7-bit character 2 8-bit 8-bit character 3 LS Offset:0x14 UARTn Line Status Register 0x14 32 read-only n 0x60 0xFF BI Break interrupt flag 4 5 read-only No break interrupt No break interrupt 0 Break interrupt Break interrupt status is active 1 FE Framing error flag 3 4 read-only No framing error No framing error 0 Framing error Framing error status is active 1 OE Overrun error flag 1 2 read-only No overrun error No overrun error 0 Overrun error Overrun error status is active 1 PE Parity error flag 2 3 read-only No parity error No parity error 0 Parity error Parity error status is active 1 RDR Receiver data ready flag 0 1 read-only Not ready UARTn_RB FIFO is empty 0 Ready UARTn_RB FIFO contains valid data 1 RXFE Receiver FIFO error flag 7 8 read-only No RX FIFO error UARTn_RB contains no UART RX errors 0 RX FIFO error UARTn_RB contains at least 1 UART RX error 1 TEMT Transmitter empty flag 6 7 read-only Not empty THR and/or TSR contains valid data 0 Empty THR and TSR are both empty 1 THRE THR empty flag 5 6 read-only Not empty THR contains valid data 0 Empty THR (TX FIFO) is empty 1 RB Offset:0x00 UARTn Receiver Buffer Register 0x0 32 read-only n 0x0 0xFF RB The oldest received byte in UART RX FIFO 0 8 read-only SP Offset:0x1C UARTn Scratch Pad Register 0x1C 32 read-write n 0x0 0xFF PAD Pad informaton 0 8 read-write TH Offset:0x00 UARTn Transmit Holding Register RB 0x0 32 write-only n 0x0 0xFF TH The oldest byte to be transmitted in UART TX FIFO when transmitter is available 0 8 write-only SN_WDT Watchdog Timer WDT 0x40010000 0x0 0x2000 registers n WDT 29 CFG Offset:0x00 WDT Configuration Register 0x0 32 read-write n 0x0 0xFFFF0007 WDKEY Watchdog register key 16 32 write-only WDTEN WDT enable 0 1 read-write Disable Disable WDT 0 Enable Enable WDT 1 WDTIE WDT interrupt enable 1 2 read-write Disable WDT reset when WDT time-out 0 Enable Enable WDT interrupt 1 WDTINT WDT interrupt flag 2 3 read-write No No WDT time-out 0 WDT time-out WDT interrupt is triggered if WDTIE=1 1 CLKSOURCE Offset:0x04 WDT Clock Source Register 0x4 32 read-write n 0x0 0xFFFF0003 CLKSOURCE WDT clock source 0 2 read-write IHRC WDT clock source=IHRC 0 HCLK WDT clock source=HCLK 1 ILRC WDT clock source=ILRC 2 ELS XTAL WDT clock source=ELS XTAL 3 WDKEY Watchdog register key 16 32 write-only FEED Offset:0x0C WDT Feed Register 0xC 32 write-only n 0x0 0xFFFFFFFF FV Watchdog feed value 0 16 write-only WDKEY Watchdog register key 16 32 write-only TC Offset:0x08 WDT Timer Constant Register 0x8 32 read-write n 0xFF 0xFFFF00FF TC Watchdog timer constant reload value 0 8 read-write WDKEY Watchdog register key 16 32 write-only