SONIX SN32F240B 2024.04.25 ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 48MHz, etc. CM0 r0p0 little 2 false 8 32 SN_ADC ADC ADC 0x0 0x0 0x2000 registers n ADC 24 ADB Offset:0x04 ADC Data Register 0x4 32 read-only n 0x0 0x0 ADM Offset:0x00 ADC Management Register 0x0 32 read-write n 0x0 0x0 ADCKS ADC clock source divider 8 11 read-write 000 ADC_PCLK/1 0 001 ADC_PCLK/2 1 010 ADC_PCLK/4 2 011 ADC_PCLK/8 3 101 ADC_PCLK/16 5 110 ADC_PCLK/32 6 ADENB ADC enable 11 12 read-write Disable Disable ADC 0 Enable Enable ADC 1 ADLEN ADC resolution 7 8 read-write 0 8-bit ADB 0 1 12-bit ADB 1 ADS ADC start control 6 7 read-write Stop ADC stopped 0 Start Start ADC conversion 1 AVREFHSEL ADC high reference voltage source 12 13 read-write Interal VDD P2.0 acts as GPIO or AIN0 pin 0 External reference voltage P2.0 acts as AVREFH pin 1 CHS ADC input channel 0 5 read-write 0 AIN0 0 1 AIN1 1 10 AIN10 10 11 AIN11 11 12 AIN12 12 13 AIN13 13 14 AIN14 14 15 AIN15 15 16 AIN16(Internal reference voltage 4.5V/3V/2V) 16 17 AIN17(VDD) 17 18 AIN18(VSS) 18 2 AIN2 2 3 AIN3 3 4 AIN4 4 5 AIN5 5 6 AIN6 6 7 AIN7 7 8 AIN8 8 9 AIN9 9 EOC ADC status 5 6 read-write Busy ADC processing 0 End End of conversion 1 GCHS ADC global channel enable 16 17 read-write Disable Disable AIN channel 0 Enable Enable AIN channel 1 VHS Internal Ref. voltage source 13 16 read-write 000b Internal 2.0V as ADC internal reference high voltage 0 001b Internal 3.0V as ADC internal reference high voltage 1 010b Internal 4.5V as ADC internal reference high voltage 2 100b VDD as ADC internal reference high voltage, Internal 2.0V as AIN10 4 101b VDD as ADC internal reference high voltage, Internal 3.0V as AIN10 5 110b VDD as ADC internal reference high voltage, Internal 4.5V as AIN10 6 111b VDD as ADC internal reference high voltage 7 IE Offset:0x0C ADC Interrupt Enable Register 0xC 32 read-write n 0x0 0x0 IE0 AIN0 interrupt enable 0 1 read-write Disable Disable AIN0 interrupt 0 Enable ADC interrupt is triggered when AIN0 completes ADC conversion 1 IE1 AIN1 interrupt enable 1 2 read-write Disable Disable AIN1 interrupt 0 Enable ADC interrupt is triggered when AIN1 completes ADC conversion 1 IE10 AIN10 interrupt enable 10 11 read-write Disable Disable AIN10 interrupt 0 Enable ADC interrupt is triggered when AIN10 completes ADC conversion 1 IE11 AIN11 interrupt enable 11 12 read-write Disable Disable AIN11 interrupt 0 Enable ADC interrupt is triggered when AIN11 completes ADC conversion 1 IE12 AIN12 interrupt enable 12 13 read-write Disable Disable AIN12 interrupt 0 Enable ADC interrupt is triggered when AIN12 completes ADC conversion 1 IE13 AIN13 interrupt enable 13 14 read-write Disable Disable AIN13 interrupt 0 Enable ADC interrupt is triggered when AIN13 completes ADC conversion 1 IE14 AIN14 interrupt enable 14 15 read-write Disable Disable AIN14 interrupt 0 Enable ADC interrupt is triggered when AIN14 completes ADC conversion 1 IE15 AIN15 interrupt enable 15 16 read-write Disable Disable AIN15 interrupt 0 Enable ADC interrupt is triggered when AIN15 completes ADC conversion 1 IE16 AIN16 interrupt enable 16 17 read-write Disable Disable AIN16 interrupt 0 Enable ADC interrupt is triggered when AIN16 completes ADC conversion 1 IE17 AIN17 interrupt enable 17 18 read-write Disable Disable AIN17 interrupt 0 Enable ADC interrupt is triggered when AIN17 completes ADC conversion 1 IE18 AIN18 interrupt enable 18 19 read-write Disable Disable AIN18 interrupt 0 Enable ADC interrupt is triggered when AIN18 completes ADC conversion 1 IE2 AIN2 interrupt enable 2 3 read-write Disable Disable AIN2 interrupt 0 Enable ADC interrupt is triggered when AIN2 completes ADC conversion 1 IE3 AIN3 interrupt enable 3 4 read-write Disable Disable AIN3 interrupt 0 Enable ADC interrupt is triggered when AIN3 completes ADC conversion 1 IE4 AIN4 interrupt enable 4 5 read-write Disable Disable AIN4 interrupt 0 Enable ADC interrupt is triggered when AIN4 completes ADC conversion 1 IE5 AIN5 interrupt enable 5 6 read-write Disable Disable AIN5 interrupt 0 Enable ADC interrupt is triggered when AIN5 completes ADC conversion 1 IE6 AIN6 interrupt enable 6 7 read-write Disable Disable AIN6 interrupt 0 Enable ADC interrupt is triggered when AIN6 completes ADC conversion 1 IE7 AIN7 interrupt enable 7 8 read-write Disable Disable AIN7 interrupt 0 Enable ADC interrupt is triggered when AIN7 completes ADC conversion 1 IE8 AIN8 interrupt enable 8 9 read-write Disable Disable AIN8 interrupt 0 Enable ADC interrupt is triggered when AIN8 completes ADC conversion 1 IE9 AIN9 interrupt enable 9 10 read-write Disable Disable AIN9 interrupt 0 Enable ADC interrupt is triggered when AIN9 completes ADC conversion 1 RIS Offset:0x10 ADC Raw Interrupt Status Register 0x10 32 read-write n 0x0 0x0 SN_CT16B0 16-bit Timer 0 with Capture function TIMER 0x0 0x0 0x2000 registers n CT16B0 15 CAP0 Offset:0x84 CT16Bn CAP0 Register 0x84 32 read-only n 0x0 0x0 CAP0 Timer counter capture value 0 16 read-only CAPCTRL Offset:0x80 CT16Bn Capture Control Register 0x80 32 read-write n 0x0 0x0 CAP0EN CAP0 function enable 3 4 read-write Disable Disable 0 Enable Enable CAP0 function 1 CAP0FE Capture on CT16Bn_CAP0 falling edge 1 2 read-write Disable Disable 0 Enable A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CAP0IE Interrupt on CT16Bn_CAP0 event 2 3 read-write Disable Disable 0 Enable A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt. 1 CAP0RE Capture on CT16Bn_CAP0 rising edge 0 1 read-write Disable Disable 0 Enable A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 1 CNTCTRL Offset:0x10 CT16Bn Counter Control Register 0x10 32 read-write n 0x0 0x0 CIS Counter Input Select 2 4 read-write CT16Bn_CAP0 CT16Bn_CAP0 0 CTM Counter/Timer Mode 0 2 read-write Timer Mode Every rising PCLK edge 0 Counter Mode TC is incremented on rising edges on the CAP0 input selected by CIS bits. 1 Counter Mode TC is incremented on falling edges on the CAP0 input selected by CIS bits. 2 Counter Mode TC is incremented on both edges on the CAP0 input selected by CIS bits. 3 IC Offset:0xA8 CT16Bn Interrupt Clear Register 0xA8 32 write-only n 0x0 0x0 CAP0IC CAP0IF clear bit 25 26 write-only No effect No effect 0 Clear Clear CAP0IF 1 MR0IC MR0IF clear bit 0 1 write-only No effect No effect 0 Clear Clear MR0IF 1 MCTRL Offset:0x14 CT16Bn Match Control Register 0x14 32 read-write n 0x0 0x0 MR0IE Enable generating an interrupt when MR0 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR0 matches TC 1 MR0RST Enable reset TC when MR0 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR0 matches TC 1 MR0STOP Stop TC and PC and clear CEN bit when MR0 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR0 matches TC 1 MR0 Offset:0x20 CT16Bn MR0 Register 0x20 32 read-write n 0x0 0x0 PC Offset:0x0C CT16Bn Prescale Counter Register 0xC 32 read-write n 0x0 0x0 PC Prescaler Counter 0 8 read-write PRE Offset:0x08 CT16Bn Prescale Register 0x8 32 read-write n 0x0 0x0 PRE Prescaler 0 8 read-write RIS Offset:0xA4 CT16Bn Raw Interrupt Status Register 0xA4 32 read-only n 0x0 0x0 CAP0IF Interrupt flag for capture channel 0 25 26 read-only No No interrupt on CAP0 0 Met interrupt requirements Interrupt requirements met on CAP0 1 MR0IF Match channel 0 interrupt flag 0 1 read-only No interrupt No interrupt on match channel 0 0 Met interrupt requirements Interrupt requirements met on match channel 0 1 TC Offset:0x04 CT16Bn Timer Counter Register 0x4 32 read-write n 0x0 0x0 TC Timer Counter 0 16 read-write TMRCTRL Offset:0x00 CT16Bn Timer Control Register 0x0 32 read-write n 0x0 0x0 CEN Counter enable 0 1 read-write Disable Disable counter 0 Enable Enable Timer Counter and Prescale Counter for counting 1 CRST Counter Reset 1 2 read-write Disable Disable 0 Reset Counter Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK 1 SN_CT16B1 16-bit Timer 0 with Capture function TIMER 0x0 0x0 0x2000 registers n CT16B1 16 EM Offset:0x88 CT16Bn External Match Register 0x88 32 read-write n 0x0 0x0 EM0 When the TC doesn't match MR0 and EMC0 is not 0, this bit will drive the state of CT16Bn_PWM0 output. 0 1 read-write EM1 When the TC doesn't match MR1 and EMC1 is not 0, this bit will drive the state of CT16Bn_PWM1 output. 1 2 read-write EM10 When the TC doesn't match MR10 and EMC10 is not 0, this bit will drive the state of CT16Bn_PWM10 output. 10 11 read-write EM11 When the TC doesn't match MR11 and EMC11 is not 0, this bit will drive the state of CT16Bn_PWM11 output. 11 12 read-write EM12 When the TC doesn't match MR12 and EMC12 is not 0, this bit will drive the state of CT16Bn_PWM12 output. 12 13 read-write EM13 When the TC doesn't match MR13 and EMC13 is not 0, this bit will drive the state of CT16Bn_PWM13 output. 13 14 read-write EM14 When the TC doesn't match MR14 and EMC14 is not 0, this bit will drive the state of CT16Bn_PWM14 output. 14 15 read-write EM15 When the TC doesn't match MR15 and EMC15 is not 0, this bit will drive the state of CT16Bn_PWM15 output. 15 16 read-write EM16 When the TC doesn't match MR16 and EMC16 is not 0, this bit will drive the state of CT16Bn_PWM16 output. 16 17 read-write EM17 When the TC doesn't match MR17 and EMC17 is not 0, this bit will drive the state of CT16Bn_PWM17 output. 17 18 read-write EM18 When the TC doesn't match MR18 and EMC18 is not 0, this bit will drive the state of CT16Bn_PWM18 output. 18 19 read-write EM19 When the TC doesn't match MR19 and EMC19 is not 0, this bit will drive the state of CT16Bn_PWM19 output. 19 20 read-write EM2 When the TC doesn't match MR2 and EMC2 is not 0, this bit will drive the state of CT16Bn_PWM2 output. 2 3 read-write EM20 When the TC doesn't match MR20 and EMC20 is not 0, this bit will drive the state of CT16Bn_PWM20 output. 20 21 read-write EM21 When the TC doesn't match MR21 and EMC21 is not 0, this bit will drive the state of CT16Bn_PWM21 output. 21 22 read-write EM22 When the TC doesn't match MR22 and EMC22 is not 0, this bit will drive the state of CT16Bn_PWM22 output. 22 23 read-write EM23 When the TC doesn't match MR23 and EMC23 is not 0, this bit will drive the state of CT16Bn_PWM23 output. 23 24 read-write EM3 When the TC doesn't match MR3 and EMC3 is not 0, this bit will drive the state of CT16Bn_PWM3 output. 3 4 read-write EM4 When the TC doesn't match MR4 and EMC4 is not 0, this bit will drive the state of CT16Bn_PWM4 output. 4 5 read-write EM5 When the TC doesn't match MR5 and EMC5 is not 0, this bit will drive the state of CT16Bn_PWM5 output. 5 6 read-write EM6 When the TC doesn't match MR6 and EMC6 is not 0, this bit will drive the state of CT16Bn_PWM6 output. 6 7 read-write EM7 When the TC doesn't match MR7 and EMC7 is not 0, this bit will drive the state of CT16Bn_PWM7 output. 7 8 read-write EM8 When the TC doesn't match MR8 and EMC8 is not 0, this bit will drive the state of CT16Bn_PWM8 output. 8 9 read-write EM9 When the TC doesn't match MR9 and EMC9 is not 0, this bit will drive the state of CT16Bn_PWM9 output. 9 10 read-write EMC Offset:0x8C CT16Bn External Match Control register 0x8C 32 read-write n 0x0 0x0 EMC0 CT16Bn_PWM0 functionality when the TC matches MR0 0 2 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM0 pin is LOW 1 High CT16Bn_PWM0 pin is HIGH 2 Toggle Toggle CT16Bn_PWM0 pin 3 EMC1 CT16Bn_PWM1 functionality when the TC matches MR1 2 4 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM1 pin is LOW 1 High CT16Bn_PWM1 pin is HIGH 2 Toggle Toggle CT16Bn_PWM1 pin 3 EMC10 CT16Bn_PWM10 functionality when the TC matches MR10 20 22 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM10 pin is LOW 1 High CT16Bn_PWM10 pin is HIGH 2 Toggle Toggle CT16Bn_PWM10 pin 3 EMC11 CT16Bn_PWM11 functionality when the TC matches MR11 22 24 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM11 pin is LOW 1 High CT16Bn_PWM11 pin is HIGH 2 Toggle Toggle CT16Bn_PWM11 pin 3 EMC12 CT16Bn_PWM12 functionality when the TC matches MR12 24 26 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM12 pin is LOW 1 High CT16Bn_PWM12 pin is HIGH 2 Toggle Toggle CT16Bn_PWM12 pin 3 EMC13 CT16Bn_PWM13 functionality when the TC matches MR13 26 28 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM13 pin is LOW 1 High CT16Bn_PWM13 pin is HIGH 2 Toggle Toggle CT16Bn_PWM13 pin 3 EMC14 CT16Bn_PWM14 functionality when the TC matches MR14 28 30 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM14 pin is LOW 1 High CT16Bn_PWM14 pin is HIGH 2 Toggle Toggle CT16Bn_PWM14 pin 3 EMC15 CT16Bn_PWM15 functionality when the TC matches MR15 30 32 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM15 pin is LOW 1 High CT16Bn_PWM15 pin is HIGH 2 Toggle Toggle CT16Bn_PWM15 pin 3 EMC2 CT16Bn_PWM2 functionality when the TC matches MR2 4 6 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM2 pin is LOW 1 High CT16Bn_PWM2 pin is HIGH 2 Toggle Toggle CT16Bn_PWM2 pin 3 EMC3 CT16Bn_PWM3 functionality when the TC matches MR3 6 8 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM3 pin is LOW 1 High CT16Bn_PWM3 pin is HIGH 2 Toggle Toggle CT16Bn_PWM3 pin 3 EMC4 CT16Bn_PWM4 functionality when the TC matches MR4 8 10 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM4 pin is LOW 1 High CT16Bn_PWM4 pin is HIGH 2 Toggle Toggle CT16Bn_PWM4 pin 3 EMC5 CT16Bn_PWM5 functionality when the TC matches MR5 10 12 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM5 pin is LOW 1 High CT16Bn_PWM5 pin is HIGH 2 Toggle Toggle CT16Bn_PWM5 pin 3 EMC6 CT16Bn_PWM6 functionality when the TC matches MR6 12 14 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM6 pin is LOW 1 High CT16Bn_PWM6 pin is HIGH 2 Toggle Toggle CT16Bn_PWM6 pin 3 EMC7 CT16Bn_PWM7 functionality when the TC matches MR7 14 16 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM7 pin is LOW 1 High CT16Bn_PWM7 pin is HIGH 2 Toggle Toggle CT16Bn_PWM7 pin 3 EMC8 CT16Bn_PWM8 functionality when the TC matches MR8 16 18 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM8 pin is LOW 1 High CT16Bn_PWM8 pin is HIGH 2 Toggle Toggle CT16Bn_PWM8 pin 3 EMC9 CT16Bn_PWM9 functionality when the TC matches MR9 18 20 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM9 pin is LOW 1 High CT16Bn_PWM9 pin is HIGH 2 Toggle Toggle CT16Bn_PWM9 pin 3 EMC2 Offset:0x90 CT16Bn External Match Control register 2 0x90 32 read-write n 0x0 0x0 EMC16 CT16Bn_PWM16 functionality when the TC matches MR16 0 2 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM16 pin is LOW 1 High CT16Bn_PWM16 pin is HIGH 2 Toggle Toggle CT16Bn_PWM16 pin 3 EMC17 CT16Bn_PWM17 functionality when the TC matches MR17 2 4 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM17 pin is LOW 1 High CT16Bn_PWM17 pin is HIGH 2 Toggle Toggle CT16Bn_PWM17 pin 3 EMC18 CT16Bn_PWM18 functionality when the TC matches MR18 4 6 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM18 pin is LOW 1 High CT16Bn_PWM18 pin is HIGH 2 Toggle Toggle CT16Bn_PWM18 pin 3 EMC19 CT16Bn_PWM19 functionality when the TC matches MR19 6 8 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM19 pin is LOW 1 High CT16Bn_PWM19 pin is HIGH 2 Toggle Toggle CT16Bn_PWM19 pin 3 EMC20 CT16Bn_PWM20 functionality when the TC matches MR20 8 10 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM20 pin is LOW 1 High CT16Bn_PWM20 pin is HIGH 2 Toggle Toggle CT16Bn_PWM20 pin 3 EMC21 CT16Bn_PWM21 functionality when the TC matches MR21 10 12 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM21 pin is LOW 1 High CT16Bn_PWM21 pin is HIGH 2 Toggle Toggle CT16Bn_PWM21 pin 3 EMC22 CT16Bn_PWM22 functionality when the TC matches MR22 12 14 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM22 pin is LOW 1 High CT16Bn_PWM22 pin is HIGH 2 Toggle Toggle CT16Bn_PWM22 pin 3 EMC23 CT16Bn_PWM23 functionality when the TC matches MR23 14 16 read-write Do Nothing Do nothing 0 Low CT16Bn_PWM23 pin is LOW 1 High CT16Bn_PWM23 pin is HIGH 2 Toggle Toggle CT16Bn_PWM23 pin 3 IC Offset:0xA8 CT16Bn Interrupt Clear Register 0xA8 32 write-only n 0x0 0x0 MR0IC MR0IF clear bit 0 1 write-only No effect No effect 0 Clear Clear MR0IF 1 MR10IC MR10IF clear bit 10 11 write-only No effect No effect 0 Clear Clear MR10IF 1 MR11IC MR11IF clear bit 11 12 write-only No effect No effect 0 Clear Clear MR11IF 1 MR12IC MR12IF clear bit 12 13 write-only No effect No effect 0 Clear Clear MR12IF 1 MR13IC MR13IF clear bit 13 14 write-only No effect No effect 0 Clear Clear MR13IF 1 MR14IC MR14IF clear bit 14 15 write-only No effect No effect 0 Clear Clear MR14IF 1 MR15IC MR15IF clear bit 15 16 write-only No effect No effect 0 Clear Clear MR15IF 1 MR16IC MR16IF clear bit 16 17 write-only No effect No effect 0 Clear Clear MR16IF 1 MR17IC MR17IF clear bit 17 18 write-only No effect No effect 0 Clear Clear MR17IF 1 MR18IC MR18IF clear bit 18 19 write-only No effect No effect 0 Clear Clear MR18IF 1 MR19IC MR19IF clear bit 19 20 write-only No effect No effect 0 Clear Clear MR19IF 1 MR1IC MR1IF clear bit 1 2 write-only No effect No effect 0 Clear Clear MR1IF 1 MR20IC MR20IF clear bit 20 21 write-only No effect No effect 0 Clear Clear MR20IF 1 MR21IC MR21IF clear bit 21 22 write-only No effect No effect 0 Clear Clear MR21IF 1 MR22IC MR22IF clear bit 22 23 write-only No effect No effect 0 Clear Clear MR22IF 1 MR23IC MR23IF clear bit 23 24 write-only No effect No effect 0 Clear Clear MR23IF 1 MR24IC MR24IF clear bit 24 25 write-only No effect No effect 0 Clear Clear MR24IF 1 MR2IC MR2IF clear bit 2 3 write-only No effect No effect 0 Clear Clear MR2IF 1 MR3IC MR3IF clear bit 3 4 write-only No effect No effect 0 Clear Clear MR3IF 1 MR4IC MR4IF clear bit 4 5 write-only No effect No effect 0 Clear Clear MR4IF 1 MR5IC MR5IF clear bit 5 6 write-only No effect No effect 0 Clear Clear MR5IF 1 MR6IC MR6IF clear bit 6 7 write-only No effect No effect 0 Clear Clear MR6IF 1 MR7IC MR7IF clear bit 7 8 write-only No effect No effect 0 Clear Clear MR7IF 1 MR8IC MR8IF clear bit 8 9 write-only No effect No effect 0 Clear Clear MR8IF 1 MR9IC MR9IF clear bit 9 10 write-only No effect No effect 0 Clear Clear MR9IF 1 MCTRL Offset:0x14 CT16Bn Match Control Register 0x14 32 read-write n 0x0 0x0 MR0IE Enable generating an interrupt when MR0 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR0 matches TC 1 MR0RST Enable reset TC when MR0 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR0 matches TC 1 MR0STOP Stop TC and PC and clear CEN bit when MR0 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR0 matches TC 1 MR1IE Enable generating an interrupt when MR1 matches TC 3 4 read-write Disable Disable 0 Enable Generating an interrupt when MR1 matches TC 1 MR1RST Enable reset TC when MR1 matches TC 4 5 read-write Disable Disable 0 Enable Reset TC when MR1 matches TC 1 MR1STOP Stop TC and PC and clear CEN bit when MR1 matches TC 5 6 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR1 matches TC 1 MR2IE Enable generating an interrupt when MR2 matches TC 6 7 read-write Disable Disable 0 Enable Generating an interrupt when MR2 matches TC 1 MR2RST Enable reset TC when MR2 matches TC 7 8 read-write Disable Disable 0 Enable Reset TC when MR2 matches TC 1 MR2STOP Stop TC and PC and clear CEN bit when MR2 matches TC 8 9 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR2 matches TC 1 MR3IE Enable generating an interrupt when MR3 matches TC 9 10 read-write Disable Disable 0 Enable Generating an interrupt when MR3 matches TC 1 MR3RST Enable reset TC when MR3 matches TC 10 11 read-write Disable Disable 0 Enable Reset TC when MR3 matches TC 1 MR3STOP Stop TC and PC and clear CEN bit when MR3 matches TC 11 12 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR3 matches TC 1 MR4IE Enable generating an interrupt when MR4 matches TC 12 13 read-write Disable Disable 0 Enable Generating an interrupt when MR4 matches TC 1 MR4RST Enable reset TC when MR4 matches TC 13 14 read-write Disable Disable 0 Enable Reset TC when MR4 matches TC 1 MR4STOP Stop TC and PC and clear CEN bit when MR4 matches TC 14 15 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR4 matches TC 1 MR5IE Enable generating an interrupt when MR5 matches TC 15 16 read-write Disable Disable 0 Enable Generating an interrupt when MR5 matches TC 1 MR5RST Enable reset TC when MR5 matches TC 16 17 read-write Disable Disable 0 Enable Reset TC when MR5 matches TC 1 MR5STOP Stop TC and PC and clear CEN bit when MR5 matches TC 17 18 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR5 matches TC 1 MR6IE Enable generating an interrupt when MR6 matches TC 18 19 read-write Disable Disable 0 Enable Generating an interrupt when MR6 matches TC 1 MR6RST Enable reset TC when MR6 matches TC 19 20 read-write Disable Disable 0 Enable Reset TC when MR6 matches TC 1 MR6STOP Stop TC and PC and clear CEN bit when MR6 matches TC 20 21 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR6 matches TC 1 MR7IE Enable generating an interrupt when MR7 matches TC 21 22 read-write Disable Disable 0 Enable Generating an interrupt when MR7 matches TC 1 MR7RST Enable reset TC when MR7 matches TC 22 23 read-write Disable Disable 0 Enable Reset TC when MR7 matches TC 1 MR7STOP Stop TC and PC and clear CEN bit when MR7 matches TC 23 24 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR7 matches TC 1 MR8IE Enable generating an interrupt when MR8 matches TC 24 25 read-write Disable Disable 0 Enable Generating an interrupt when MR8 matches TC 1 MR8RST Enable reset TC when MR8 matches TC 25 26 read-write Disable Disable 0 Enable Reset TC when MR8 matches TC 1 MR8STOP Stop TC and PC and clear CEN bit when MR8 matches TC 26 27 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR8 matches TC 1 MR9IE Enable generating an interrupt when MR9 matches TC 27 28 read-write Disable Disable 0 Enable Generating an interrupt when MR9 matches TC 1 MR9RST Enable reset TC when MR9 matches TC 28 29 read-write Disable Disable 0 Enable Reset TC when MR9 matches TC 1 MR9STOP Stop TC and PC and clear CEN bit when MR9 matches TC 29 30 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR9 matches TC 1 MCTRL2 Offset:0x18 CT16Bn Match Control Register 2 0x18 32 read-write n 0x0 0x0 MR10IE Enable generating an interrupt when MR10 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR10 matches TC 1 MR10RST Enable reset TC when MR10 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR10 matches TC 1 MR10STOP Stop TC and PC and clear CEN bit when MR10 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR10 matches TC 1 MR11IE Enable generating an interrupt when MR11 matches TC 3 4 read-write Disable Disable 0 Enable Generating an interrupt when MR11 matches TC 1 MR11RST Enable reset TC when MR11 matches TC 4 5 read-write Disable Disable 0 Enable Reset TC when MR11 matches TC 1 MR11STOP Stop TC and PC and clear CEN bit when MR11 matches TC 5 6 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR11 matches TC 1 MR12IE Enable generating an interrupt when MR12 matches TC 6 7 read-write Disable Disable 0 Enable Generating an interrupt when MR12 matches TC 1 MR12RST Enable reset TC when MR12 matches TC 7 8 read-write Disable Disable 0 Enable Reset TC when MR12 matches TC 1 MR12STOP Stop TC and PC and clear CEN bit when MR12 matches TC 8 9 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR12 matches TC 1 MR13IE Enable generating an interrupt when MR13 matches TC 9 10 read-write Disable Disable 0 Enable Generating an interrupt when MR13 matches TC 1 MR13RST Enable reset TC when MR13 matches TC 10 11 read-write Disable Disable 0 Enable Reset TC when MR13 matches TC 1 MR13STOP Stop TC and PC and clear CEN bit when MR13 matches TC 11 12 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR13 matches TC 1 MR14IE Enable generating an interrupt when MR14 matches TC 12 13 read-write Disable Disable 0 Enable Generating an interrupt when MR14 matches TC 1 MR14RST Enable reset TC when MR14 matches TC 13 14 read-write Disable Disable 0 Enable Reset TC when MR14 matches TC 1 MR14STOP Stop TC and PC and clear CEN bit when MR14 matches TC 14 15 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR14 matches TC 1 MR15IE Enable generating an interrupt when MR15 matches TC 15 16 read-write Disable Disable 0 Enable Generating an interrupt when MR15 matches TC 1 MR15RST Enable reset TC when MR15 matches TC 16 17 read-write Disable Disable 0 Enable Reset TC when MR15 matches TC 1 MR15STOP Stop TC and PC and clear CEN bit when MR15 matches TC 17 18 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR15 matches TC 1 MR16IE Enable generating an interrupt when MR16 matches TC 18 19 read-write Disable Disable 0 Enable Generating an interrupt when MR16 matches TC 1 MR16RST Enable reset TC when MR16 matches TC 19 20 read-write Disable Disable 0 Enable Reset TC when MR16 matches TC 1 MR16STOP Stop TC and PC and clear CEN bit when MR16 matches TC 20 21 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR16 matches TC 1 MR17IE Enable generating an interrupt when MR17 matches TC 21 22 read-write Disable Disable 0 Enable Generating an interrupt when MR17 matches TC 1 MR17RST Enable reset TC when MR17 matches TC 22 23 read-write Disable Disable 0 Enable Reset TC when MR17 matches TC 1 MR17STOP Stop TC and PC and clear CEN bit when MR17 matches TC 23 24 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR17 matches TC 1 MR18IE Enable generating an interrupt when MR18 matches TC 24 25 read-write Disable Disable 0 Enable Generating an interrupt when MR18 matches TC 1 MR18RST Enable reset TC when MR18 matches TC 25 26 read-write Disable Disable 0 Enable Reset TC when MR18 matches TC 1 MR18STOP Stop TC and PC and clear CEN bit when MR18 matches TC 26 27 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR18 matches TC 1 MR19IE Enable generating an interrupt when MR19 matches TC 27 28 read-write Disable Disable 0 Enable Generating an interrupt when MR19 matches TC 1 MR19RST Enable reset TC when MR19 matches TC 28 29 read-write Disable Disable 0 Enable Reset TC when MR19 matches TC 1 MR19STOP Stop TC and PC and clear CEN bit when MR19 matches TC 29 30 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR19 matches TC 1 MCTRL3 Offset:0x1C CT16Bn Match Control Register 3 0x1C 32 read-write n 0x0 0x0 MR20IE Enable generating an interrupt when MR20 matches TC 0 1 read-write Disable Disable 0 Enable Generating an interrupt when MR20 matches TC 1 MR20RST Enable reset TC when MR20 matches TC 1 2 read-write Disable Disable 0 Enable Reset TC when MR20 matches TC 1 MR20STOP Stop TC and PC and clear CEN bit when MR20 matches TC 2 3 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR20 matches TC 1 MR21IE Enable generating an interrupt when MR21 matches TC 3 4 read-write Disable Disable 0 Enable Generating an interrupt when MR21 matches TC 1 MR21RST Enable reset TC when MR21 matches TC 4 5 read-write Disable Disable 0 Enable Reset TC when MR21 matches TC 1 MR21STOP Stop TC and PC and clear CEN bit when MR21 matches TC 5 6 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR21 matches TC 1 MR22IE Enable generating an interrupt when MR22 matches TC 6 7 read-write Disable Disable 0 Enable Generating an interrupt when MR22 matches TC 1 MR22RST Enable reset TC when MR22 matches TC 7 8 read-write Disable Disable 0 Enable Reset TC when MR22 matches TC 1 MR22STOP Stop TC and PC and clear CEN bit when MR22 matches TC 8 9 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR22 matches TC 1 MR23IE Enable generating an interrupt when MR23 matches TC 9 10 read-write Disable Disable 0 Enable Generating an interrupt when MR23 matches TC 1 MR23RST Enable reset TC when MR23 matches TC 10 11 read-write Disable Disable 0 Enable Reset TC when MR23 matches TC 1 MR23STOP Stop TC and PC and clear CEN bit when MR23 matches TC 11 12 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR23 matches TC 1 MR24IE Enable generating an interrupt when MR24 matches TC 12 13 read-write Disable Disable 0 Enable Generating an interrupt when MR24 matches TC 1 MR24RST Enable reset TC when MR24 matches TC 13 14 read-write Disable Disable 0 Enable Reset TC when MR24 matches TC 1 MR24STOP Stop TC and PC and clear CEN bit when MR24 matches TC 14 15 read-write Disable Disable 0 Enable Stop TC and PC and clear CEN bit when MR24 matches TC 1 MR0 Offset:0x20 CT16Bn MR0 Register 0x20 32 read-write n 0x0 0x0 MR1 Offset:0x24 CT16Bn MR1 Register 0x24 32 read-write n 0x0 0x0 MR10 Offset:0x48 CT16Bn MR10 Register 0x48 32 read-write n 0x0 0x0 MR11 Offset:0x4C CT16Bn MR11 Register 0x4C 32 read-write n 0x0 0x0 MR12 Offset:0x50 CT16Bn MR12 Register 0x50 32 read-write n 0x0 0x0 MR13 Offset:0x54 CT16Bn MR13 Register 0x54 32 read-write n 0x0 0x0 MR14 Offset:0x58 CT16Bn MR14 Register 0x58 32 read-write n 0x0 0x0 MR15 Offset:0x5C CT16Bn MR15 Register 0x5C 32 read-write n 0x0 0x0 MR16 Offset:0x60 CT16Bn MR16 Register 0x60 32 read-write n 0x0 0x0 MR17 Offset:0x64 CT16Bn MR17 Register 0x64 32 read-write n 0x0 0x0 MR18 Offset:0x68 CT16Bn MR18 Register 0x68 32 read-write n 0x0 0x0 MR19 Offset:0x6C CT16Bn MR19 Register 0x6C 32 read-write n 0x0 0x0 MR2 Offset:0x28 CT16Bn MR2 Register 0x28 32 read-write n 0x0 0x0 MR20 Offset:0x70 CT16Bn MR20 Register 0x70 32 read-write n 0x0 0x0 MR21 Offset:0x74 CT16Bn MR21 Register 0x74 32 read-write n 0x0 0x0 MR22 Offset:0x78 CT16Bn MR22 Register 0x78 32 read-write n 0x0 0x0 MR23 Offset:0x7C CT16Bn MR23 Register 0x7C 32 read-write n 0x0 0x0 MR24 Offset:0x80 CT16Bn MR24 Register 0x80 32 read-write n 0x0 0x0 MR3 Offset:0x2C CT16Bn MR3 Register 0x2C 32 read-write n 0x0 0x0 MR4 Offset:0x30 CT16Bn MR4 Register 0x30 32 read-write n 0x0 0x0 MR5 Offset:0x34 CT16Bn MR5 Register 0x34 32 read-write n 0x0 0x0 MR6 Offset:0x38 CT16Bn MR6 Register 0x38 32 read-write n 0x0 0x0 MR7 Offset:0x3C CT16Bn MR7 Register 0x3C 32 read-write n 0x0 0x0 MR8 Offset:0x40 CT16Bn MR8 Register 0x40 32 read-write n 0x0 0x0 MR9 Offset:0x44 CT16Bn MR9 Register 0x44 32 read-write n 0x0 0x0 PC Offset:0x0C CT16Bn Prescale Counter Register 0xC 32 read-write n 0x0 0x0 PC Prescaler Counter 0 8 read-write PRE Offset:0x08 CT16Bn Prescale Register 0x8 32 read-write n 0x0 0x0 PRE Prescaler 0 8 read-write PWMCTRL Offset:0x94 CT16Bn PWM Control Register 0x94 32 read-write n 0x0 0x0 PWM0MODE PWM0 output mode 0 2 read-write PWM mode 1 During up-counting, PWM0 is 0 when TC is less than MR0. During down-counting, PWM0 is 1 when TC is larger/equal than MR0 0 PWM mode 2 During up-counting, PWM0 is 1 when TC is less than MR0. During down-counting, PWM0 is 0 when TC is larger/equal than MR0 1 Force 0 PWM0 is forced to 0 2 Force 1 PWM0 is forced to 1 3 PWM10MODE PWM10 output mode 20 22 read-write PWM mode 1 During up-counting, PWM10 is 0 when TC is less than MR10. During down-counting, PWM10 is 1 when TC is larger/equal than MR10 0 PWM mode 2 During up-counting, PWM10 is 1 when TC is less than MR10. During down-counting, PWM10 is 0 when TC is larger/equal than MR10 1 Force 0 PWM10 is forced to 0 2 Force 1 PWM10 is forced to 1 3 PWM11MODE PWM11 output mode 22 24 read-write PWM mode 1 During up-counting, PWM11 is 0 when TC is less than MR11. During down-counting, PWM11 is 1 when TC is larger/equal than MR11 0 PWM mode 2 During up-counting, PWM11 is 1 when TC is less than MR11. During down-counting, PWM11 is 0 when TC is larger/equal than MR11 1 Force 0 PWM11 is forced to 0 2 Force 1 PWM11 is forced to 1 3 PWM12MODE PWM12 output mode 24 26 read-write PWM mode 1 During up-counting, PWM12 is 0 when TC is less than MR12. During down-counting, PWM12 is 1 when TC is larger/equal than MR12 0 PWM mode 2 During up-counting, PWM12 is 1 when TC is less than MR12. During down-counting, PWM12 is 0 when TC is larger/equal than MR12 1 Force 0 PWM12 is forced to 0 2 Force 1 PWM12 is forced to 1 3 PWM13MODE PWM13 output mode 26 28 read-write PWM mode 1 During up-counting, PWM13 is 0 when TC is less than MR13. During down-counting, PWM13 is 1 when TC is larger/equal than MR13 0 PWM mode 2 During up-counting, PWM13 is 1 when TC is less than MR13. During down-counting, PWM13 is 0 when TC is larger/equal than MR13 1 Force 0 PWM13 is forced to 0 2 Force 1 PWM13 is forced to 1 3 PWM14MODE PWM14 output mode 28 30 read-write PWM mode 1 During up-counting, PWM14 is 0 when TC is less than MR14. During down-counting, PWM14 is 1 when TC is larger/equal than MR14 0 PWM mode 2 During up-counting, PWM14 is 1 when TC is less than MR14. During down-counting, PWM14 is 0 when TC is larger/equal than MR14 1 Force 0 PWM14 is forced to 0 2 Force 1 PWM14 is forced to 1 3 PWM15MODE PWM15 output mode 30 32 read-write PWM mode 1 During up-counting, PWM15 is 0 when TC is less than MR15. During down-counting, PWM15 is 1 when TC is larger/equal than MR15 0 PWM mode 2 During up-counting, PWM15 is 1 when TC is less than MR15. During down-counting, PWM15 is 0 when TC is larger/equal than MR15 1 Force 0 PWM15 is forced to 0 2 Force 1 PWM15 is forced to 1 3 PWM1MODE PWM1 output mode 2 4 read-write PWM mode 1 During up-counting, PWM1 is 0 when TC is less than MR1. During down-counting, PWM1 is 1 when TC is larger/equal than MR1 0 PWM mode 2 During up-counting, PWM1 is 1 when TC is less than MR1. During down-counting, PWM1 is 0 when TC is larger/equal than MR1 1 Force 0 PWM1 is forced to 0 2 Force 1 PWM1 is forced to 1 3 PWM2MODE PWM2 output mode 4 6 read-write PWM mode 1 During up-counting, PWM2 is 0 when TC is less than MR2. During down-counting, PWM2 is 1 when TC is larger/equal than MR2 0 PWM mode 2 During up-counting, PWM2 is 1 when TC is less than MR2. During down-counting, PWM2 is 0 when TC is larger/equal than MR2 1 Force 0 PWM2 is forced to 0 2 Force 1 PWM2 is forced to 1 3 PWM3MODE PWM3 output mode 6 8 read-write PWM mode 1 During up-counting, PWM3 is 0 when TC is less than MR3. During down-counting, PWM3 is 1 when TC is larger/equal than MR3 0 PWM mode 2 During up-counting, PWM3 is 1 when TC is less than MR3. During down-counting, PWM3 is 0 when TC is larger/equal than MR3 1 Force 0 PWM3 is forced to 0 2 Force 1 PWM3 is forced to 1 3 PWM4MODE PWM4 output mode 8 10 read-write PWM mode 1 During up-counting, PWM4 is 0 when TC is less than MR4. During down-counting, PWM4 is 1 when TC is larger/equal than MR4 0 PWM mode 2 During up-counting, PWM4 is 1 when TC is less than MR4. During down-counting, PWM4 is 0 when TC is larger/equal than MR4 1 Force 0 PWM4 is forced to 0 2 Force 1 PWM4 is forced to 1 3 PWM5MODE PWM5 output mode 10 12 read-write PWM mode 1 During up-counting, PWM5 is 0 when TC is less than MR5. During down-counting, PWM5 is 1 when TC is larger/equal than MR5 0 PWM mode 2 During up-counting, PWM5 is 1 when TC is less than MR5. During down-counting, PWM5 is 0 when TC is larger/equal than MR5 1 Force 0 PWM5 is forced to 0 2 Force 1 PWM5 is forced to 1 3 PWM6MODE PWM6 output mode 12 14 read-write PWM mode 1 During up-counting, PWM6 is 0 when TC is less than MR6. During down-counting, PWM6 is 1 when TC is larger/equal than MR6 0 PWM mode 2 During up-counting, PWM6 is 1 when TC is less than MR6. During down-counting, PWM6 is 0 when TC is larger/equal than MR6 1 Force 0 PWM6 is forced to 0 2 Force 1 PWM6 is forced to 1 3 PWM7MODE PWM7 output mode 14 16 read-write PWM mode 1 During up-counting, PWM7 is 0 when TC is less than MR7. During down-counting, PWM7 is 1 when TC is larger/equal than MR7 0 PWM mode 2 During up-counting, PWM7 is 1 when TC is less than MR7. During down-counting, PWM7 is 0 when TC is larger/equal than MR7 1 Force 0 PWM7 is forced to 0 2 Force 1 PWM7 is forced to 1 3 PWM8MODE PWM8 output mode 16 18 read-write PWM mode 1 During up-counting, PWM8 is 0 when TC is less than MR8. During down-counting, PWM8 is 1 when TC is larger/equal than MR8 0 PWM mode 2 During up-counting, PWM8 is 1 when TC is less than MR8. During down-counting, PWM8 is 0 when TC is larger/equal than MR8 1 Force 0 PWM8 is forced to 0 2 Force 1 PWM8 is forced to 1 3 PWM9MODE PWM9 output mode 18 20 read-write PWM mode 1 During up-counting, PWM9 is 0 when TC is less than MR9. During down-counting, PWM9 is 1 when TC is larger/equal than MR9 0 PWM mode 2 During up-counting, PWM9 is 1 when TC is less than MR9. During down-counting, PWM9 is 0 when TC is larger/equal than MR9 1 Force 0 PWM9 is forced to 0 2 Force 1 PWM9 is forced to 1 3 PWMCTRL2 Offset:0x98 CT16Bn PWM Control Register 2 0x98 32 read-write n 0x0 0x0 PWM16MODE PWM16 output mode 0 2 read-write PWM mode 1 During up-counting, PWM16 is 0 when TC is less than MR16. During down-counting, PWM16 is 1 when TC is larger/equal than MR16 0 PWM mode 2 During up-counting, PWM16 is 1 when TC is less than MR16. During down-counting, PWM16 is 0 when TC is larger/equal than MR16 1 Force 0 PWM16 is forced to 0 2 Force 1 PWM16 is forced to 1 3 PWM17MODE PWM17 output mode 2 4 read-write PWM mode 1 During up-counting, PWM17 is 0 when TC is less than MR17. During down-counting, PWM17 is 1 when TC is larger/equal than MR17 0 PWM mode 2 During up-counting, PWM17 is 1 when TC is less than MR17. During down-counting, PWM17 is 0 when TC is larger/equal than MR17 1 Force 0 PWM17 is forced to 0 2 Force 1 PWM17 is forced to 1 3 PWM18MODE PWM18 output mode 4 6 read-write PWM mode 1 During up-counting, PWM18 is 0 when TC is less than MR18. During down-counting, PWM18 is 1 when TC is larger/equal than MR18 0 PWM mode 2 During up-counting, PWM18 is 1 when TC is less than MR18. During down-counting, PWM18 is 0 when TC is larger/equal than MR18 1 Force 0 PWM18 is forced to 0 2 Force 1 PWM18 is forced to 1 3 PWM19MODE PWM19 output mode 6 8 read-write PWM mode 1 During up-counting, PWM19 is 0 when TC is less than MR19. During down-counting, PWM19 is 1 when TC is larger/equal than MR19 0 PWM mode 2 During up-counting, PWM19 is 1 when TC is less than MR19. During down-counting, PWM19 is 0 when TC is larger/equal than MR19 1 Force 0 PWM19 is forced to 0 2 Force 1 PWM19 is forced to 1 3 PWM20MODE PWM20 output mode 8 10 read-write PWM mode 1 During up-counting, PWM20 is 0 when TC is less than MR20. During down-counting, PWM20 is 1 when TC is larger/equal than MR20 0 PWM mode 2 During up-counting, PWM20 is 1 when TC is less than MR20. During down-counting, PWM20 is 0 when TC is larger/equal than MR20 1 Force 0 PWM20 is forced to 0 2 Force 1 PWM20 is forced to 1 3 PWM21MODE PWM21 output mode 10 12 read-write PWM mode 1 During up-counting, PWM21 is 0 when TC is less than MR21. During down-counting, PWM21 is 1 when TC is larger/equal than MR21 0 PWM mode 2 During up-counting, PWM21 is 1 when TC is less than MR21. During down-counting, PWM21 is 0 when TC is larger/equal than MR21 1 Force 0 PWM21 is forced to 0 2 Force 1 PWM21 is forced to 1 3 PWM22MODE PWM22 output mode 12 14 read-write PWM mode 1 During up-counting, PWM22 is 0 when TC is less than MR22. During down-counting, PWM22 is 1 when TC is larger/equal than MR22 0 PWM mode 2 During up-counting, PWM22 is 1 when TC is less than MR22. During down-counting, PWM22 is 0 when TC is larger/equal than MR22 1 Force 0 PWM22 is forced to 0 2 Force 1 PWM22 is forced to 1 3 PWM23MODE PWM23 output mode 14 16 read-write PWM mode 1 During up-counting, PWM23 is 0 when TC is less than MR23. During down-counting, PWM22 is 1 when TC is larger/equal than MR23 0 PWM mode 2 During up-counting, PWM23 is 1 when TC is less than MR23. During down-counting, PWM22 is 0 when TC is larger/equal than MR23 1 Force 0 PWM23 is forced to 0 2 Force 1 PWM23 is forced to 1 3 PWMENB Offset:0x9C CT16Bn PWM Enable register 0x9C 32 read-write n 0x0 0x0 PWM0EN PWM0 enable 0 1 read-write Disable CT16Bn_PWM0 is controlled by EMC0 0 Enable Enable PWM mode for CT16Bn_PWM0 1 PWM10EN PWM10 enable 10 11 read-write Disable CT16Bn_PWM10 is controlled by EMC10 0 Enable Enable PWM mode for CT16Bn_PWM10 1 PWM11EN PWM11 enable 11 12 read-write Disable CT16Bn_PWM11 is controlled by EMC11 0 Enable Enable PWM mode for CT16Bn_PWM11 1 PWM12EN PWM12 enable 12 13 read-write Disable CT16Bn_PWM12 is controlled by EMC12 0 Enable Enable PWM mode for CT16Bn_PWM12 1 PWM13EN PWM13 enable 13 14 read-write Disable CT16Bn_PWM13 is controlled by EMC13 0 Enable Enable PWM mode for CT16Bn_PWM13 1 PWM14EN PWM14 enable 14 15 read-write Disable CT16Bn_PWM14 is controlled by EMC14 0 Enable Enable PWM mode for CT16Bn_PWM14 1 PWM15EN PWM15 enable 15 16 read-write Disable CT16Bn_PWM15 is controlled by EMC15 0 Enable Enable PWM mode for CT16Bn_PWM15 1 PWM16EN PWM16 enable 16 17 read-write Disable CT16Bn_PWM16 is controlled by EMC16 0 Enable Enable PWM mode for CT16Bn_PWM16 1 PWM17EN PWM17 enable 17 18 read-write Disable CT16Bn_PWM17 is controlled by EMC17 0 Enable Enable PWM mode for CT16Bn_PWM17 1 PWM18EN PWM18 enable 18 19 read-write Disable CT16Bn_PWM18 is controlled by EMC18 0 Enable Enable PWM mode for CT16Bn_PWM18 1 PWM19EN PWM19 enable 19 20 read-write Disable CT16Bn_PWM19 is controlled by EMC19 0 Enable Enable PWM mode for CT16Bn_PWM19 1 PWM1EN PWM1 enable 1 2 read-write Disable CT16Bn_PWM1 is controlled by EMC1 0 Enable Enable PWM mode for CT16Bn_PWM1 1 PWM20EN PWM20 enable 20 21 read-write Disable CT16Bn_PWM20 is controlled by EMC20 0 Enable Enable PWM mode for CT16Bn_PWM20 1 PWM21EN PWM21 enable 21 22 read-write Disable CT16Bn_PWM21 is controlled by EMC21 0 Enable Enable PWM mode for CT16Bn_PWM21 1 PWM22EN PWM22 enable 22 23 read-write Disable CT16Bn_PWM22 is controlled by EMC22 0 Enable Enable PWM mode for CT16Bn_PWM22 1 PWM23EN PWM23 enable 23 24 read-write Disable CT16Bn_PWM23 is controlled by EMC23 0 Enable Enable PWM mode for CT16Bn_PWM23 1 PWM2EN PWM2 enable 2 3 read-write Disable CT16Bn_PWM2 is controlled by EMC2 0 Enable Enable PWM mode for CT16Bn_PWM2 1 PWM3EN PWM3 enable 3 4 read-write Disable CT16Bn_PWM3 is controlled by EMC3 0 Enable Enable PWM mode for CT16Bn_PWM3 1 PWM4EN PWM4 enable 4 5 read-write Disable CT16Bn_PWM4 is controlled by EMC4 0 Enable Enable PWM mode for CT16Bn_PWM4 1 PWM5EN PWM5 enable 5 6 read-write Disable CT16Bn_PWM5 is controlled by EMC5 0 Enable Enable PWM mode for CT16Bn_PWM5 1 PWM6EN PWM6 enable 6 7 read-write Disable CT16Bn_PWM6 is controlled by EMC6 0 Enable Enable PWM mode for CT16Bn_PWM6 1 PWM7EN PWM7 enable 7 8 read-write Disable CT16Bn_PWM7 is controlled by EMC7 0 Enable Enable PWM mode for CT16Bn_PWM7 1 PWM8EN PWM8 enable 8 9 read-write Disable CT16Bn_PWM8 is controlled by EMC8 0 Enable Enable PWM mode for CT16Bn_PWM8 1 PWM9EN PWM9 enable 9 10 read-write Disable CT16Bn_PWM9 is controlled by EMC9 0 Enable Enable PWM mode for CT16Bn_PWM9 1 PWMIOENB Offset:0xA0 CT16Bn PWM IO Enable register 0xA0 32 read-write n 0x0 0x0 PWM0IOEN CT16Bn_PWM0/GPIO selection 0 1 read-write Disable CT16Bn_PWM0 pin is act as GPIO 0 Enable CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit 1 PWM10IOEN CT16Bn_PWM10/GPIO selection 10 11 read-write Disable CT16Bn_PWM10 pin is act as GPIO 0 Enable CT16Bn_PWM10 pin act as match output, and output depends on PWM10EN bit 1 PWM11IOEN CT16Bn_PWM11/GPIO selection 11 12 read-write Disable CT16Bn_PWM11 pin is act as GPIO 0 Enable CT16Bn_PWM11 pin act as match output, and output depends on PWM11EN bit 1 PWM12IOEN CT16Bn_PWM12/GPIO selection 12 13 read-write Disable CT16Bn_PWM12 pin is act as GPIO 0 Enable CT16Bn_PWM12 pin act as match output, and output depends on PWM12EN bit 1 PWM13IOEN CT16Bn_PWM13/GPIO selection 13 14 read-write Disable CT16Bn_PWM13 pin is act as GPIO 0 Enable CT16Bn_PWM13 pin act as match output, and output depends on PWM13EN bit 1 PWM14IOEN CT16Bn_PWM14/GPIO selection 14 15 read-write Disable CT16Bn_PWM14 pin is act as GPIO 0 Enable CT16Bn_PWM14 pin act as match output, and output depends on PWM14EN bit 1 PWM15IOEN CT16Bn_PWM15/GPIO selection 15 16 read-write Disable CT16Bn_PWM15 pin is act as GPIO 0 Enable CT16Bn_PWM15 pin act as match output, and output depends on PWM15EN bit 1 PWM16IOEN CT16Bn_PWM16/GPIO selection 16 17 read-write Disable CT16Bn_PWM16 pin is act as GPIO 0 Enable CT16Bn_PWM16 pin act as match output, and output depends on PWM16EN bit 1 PWM17IOEN CT16Bn_PWM17/GPIO selection 17 18 read-write Disable CT16Bn_PWM17 pin is act as GPIO 0 Enable CT16Bn_PWM17 pin act as match output, and output depends on PWM17EN bit 1 PWM18IOEN CT16Bn_PWM18/GPIO selection 18 19 read-write Disable CT16Bn_PWM18 pin is act as GPIO 0 Enable CT16Bn_PWM18 pin act as match output, and output depends on PWM18EN bit 1 PWM19IOEN CT16Bn_PWM19/GPIO selection 19 20 read-write Disable CT16Bn_PWM19 pin is act as GPIO 0 Enable CT16Bn_PWM19 pin act as match output, and output depends on PWM19EN bit 1 PWM1IOEN CT16Bn_PWM1/GPIO selection 1 2 read-write Disable CT16Bn_PWM1 pin is act as GPIO 0 Enable CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit 1 PWM20IOEN CT16Bn_PWM20/GPIO selection 20 21 read-write Disable CT16Bn_PWM20 pin is act as GPIO 0 Enable CT16Bn_PWM20 pin act as match output, and output depends on PWM20EN bit 1 PWM21IOEN CT16Bn_PWM21/GPIO selection 21 22 read-write Disable CT16Bn_PWM21 pin is act as GPIO 0 Enable CT16Bn_PWM21 pin act as match output, and output depends on PWM21EN bit 1 PWM22IOEN CT16Bn_PWM22/GPIO selection 22 23 read-write Disable CT16Bn_PWM22 pin is act as GPIO 0 Enable CT16Bn_PWM22 pin act as match output, and output depends on PWM22EN bit 1 PWM23IOEN CT16Bn_PWM23/GPIO selection 23 24 read-write Disable CT16Bn_PWM23 pin is act as GPIO 0 Enable CT16Bn_PWM23 pin act as match output, and output depends on PWM23EN bit 1 PWM2IOEN CT16Bn_PWM2/GPIO selection 2 3 read-write Disable CT16Bn_PWM2 pin is act as GPIO 0 Enable CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit 1 PWM3IOEN CT16Bn_PWM3/GPIO selection 3 4 read-write Disable CT16Bn_PWM3 pin is act as GPIO 0 Enable CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit 1 PWM4IOEN CT16Bn_PWM4/GPIO selection 4 5 read-write Disable CT16Bn_PWM4 pin is act as GPIO 0 Enable CT16Bn_PWM4 pin act as match output, and output depends on PWM4EN bit 1 PWM5IOEN CT16Bn_PWM5/GPIO selection 5 6 read-write Disable CT16Bn_PWM5 pin is act as GPIO 0 Enable CT16Bn_PWM5 pin act as match output, and output depends on PWM5EN bit 1 PWM6IOEN CT16Bn_PWM6/GPIO selection 6 7 read-write Disable CT16Bn_PWM6 pin is act as GPIO 0 Enable CT16Bn_PWM6 pin act as match output, and output depends on PWM6EN bit 1 PWM7IOEN CT16Bn_PWM7/GPIO selection 7 8 read-write Disable CT16Bn_PWM7 pin is act as GPIO 0 Enable CT16Bn_PWM7 pin act as match output, and output depends on PWM7EN bit 1 PWM8IOEN CT16Bn_PWM8/GPIO selection 8 9 read-write Disable CT16Bn_PWM8 pin is act as GPIO 0 Enable CT16Bn_PWM8 pin act as match output, and output depends on PWM8EN bit 1 PWM9IOEN CT16Bn_PWM9/GPIO selection 9 10 read-write Disable CT16Bn_PWM9 pin is act as GPIO 0 Enable CT16Bn_PWM9 pin act as match output, and output depends on PWM9EN bit 1 RIS Offset:0xA4 CT16Bn Raw Interrupt Status Register 0xA4 32 read-only n 0x0 0x0 MR0IF Match channel 0 interrupt flag 0 1 read-only No interrupt No interrupt on match channel 0 0 Met interrupt requirements Interrupt requirements met on match channel 0 1 MR10IF Match channel 10 interrupt flag 10 11 read-only No No interrupt on match channel 10 0 Met interrupt requirements Interrupt requirements met on match channel 10 1 MR11IF Match channel 11 interrupt flag 11 12 read-only No No interrupt on match channel 11 0 Met interrupt requirements Interrupt requirements met on match channel 11 1 MR12IF Match channel 12 interrupt flag 12 13 read-only No interrupt No interrupt on match channel 12 0 Met interrupt requirements Interrupt requirements met on match channel 12 1 MR13IF Match channel 13 interrupt flag 13 14 read-only No No interrupt on match channel 13 0 Met interrupt requirements Interrupt requirements met on match channel 13 1 MR14IF Match channel 14 interrupt flag 14 15 read-only No No interrupt on match channel 14 0 Met interrupt requirements Interrupt requirements met on match channel 14 1 MR15IF Match channel 15 interrupt flag 15 16 read-only No No interrupt on match channel 15 0 Met interrupt requirements Interrupt requirements met on match channel 15 1 MR16IF Match channel 16 interrupt flag 16 17 read-only No interrupt No interrupt on match channel 16 0 Met interrupt requirements Interrupt requirements met on match channel 16 1 MR17IF Match channel 17 interrupt flag 17 18 read-only No No interrupt on match channel 17 0 Met interrupt requirements Interrupt requirements met on match channel 17 1 MR18IF Match channel 18 interrupt flag 18 19 read-only No No interrupt on match channel 18 0 Met interrupt requirements Interrupt requirements met on match channel 18 1 MR19IF Match channel 19 interrupt flag 19 20 read-only No No interrupt on match channel 19 0 Met interrupt requirements Interrupt requirements met on match channel 19 1 MR1IF Match channel 1 interrupt flag 1 2 read-only No No interrupt on match channel 1 0 Met interrupt requirements Interrupt requirements met on match channel 1 1 MR20IF Match channel 20 interrupt flag 20 21 read-only No interrupt No interrupt on match channel 20 0 Met interrupt requirements Interrupt requirements met on match channel 20 1 MR21IF Match channel 21 interrupt flag 21 22 read-only No No interrupt on match channel 21 0 Met interrupt requirements Interrupt requirements met on match channel 21 1 MR22IF Match channel 22 interrupt flag 22 23 read-only No No interrupt on match channel 22 0 Met interrupt requirements Interrupt requirements met on match channel 22 1 MR23IF Match channel 23 interrupt flag 23 24 read-only No No interrupt on match channel 23 0 Met interrupt requirements Interrupt requirements met on match channel 23 1 MR24IF Match channel 24 interrupt flag 24 25 read-only No No interrupt on match channel 24 0 Met interrupt requirements Interrupt requirements met on match channel 24 1 MR2IF Match channel 2 interrupt flag 2 3 read-only No No interrupt on match channel 2 0 Met interrupt requirements Interrupt requirements met on match channel 2 1 MR3IF Match channel 3 interrupt flag 3 4 read-only No No interrupt on match channel 3 0 Met interrupt requirements Interrupt requirements met on match channel 3 1 MR4IF Match channel 4 interrupt flag 4 5 read-only No interrupt No interrupt on match channel 4 0 Met interrupt requirements Interrupt requirements met on match channel 4 1 MR5IF Match channel 5 interrupt flag 5 6 read-only No No interrupt on match channel 5 0 Met interrupt requirements Interrupt requirements met on match channel 5 1 MR6IF Match channel 6 interrupt flag 6 7 read-only No No interrupt on match channel 6 0 Met interrupt requirements Interrupt requirements met on match channel 6 1 MR7IF Match channel 7 interrupt flag 7 8 read-only No No interrupt on match channel 7 0 Met interrupt requirements Interrupt requirements met on match channel 7 1 MR8IF Match channel 8 interrupt flag 8 9 read-only No interrupt No interrupt on match channel 8 0 Met interrupt requirements Interrupt requirements met on match channel 8 1 MR9IF Match channel 9 interrupt flag 9 10 read-only No No interrupt on match channel 9 0 Met interrupt requirements Interrupt requirements met on match channel 9 1 TC Offset:0x04 CT16Bn Timer Counter Register 0x4 32 read-write n 0x0 0x0 TC Timer Counter 0 16 read-write TMRCTRL Offset:0x00 CT16Bn Timer Control Register 0x0 32 read-write n 0x0 0x0 CEN Counter enable 0 1 read-write Disable Disable counter 0 Enable Enable Timer Counter and Prescale Counter for counting 1 CRST Counter Reset 1 2 read-write Disable Disable 0 Reset Counter Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK 1 SN_FLASH FLASH Memory Control Registers FLASH 0x0 0x0 0x2000 registers n ADDR Offset:0x10 Flash Address Register 0x10 32 read-write n 0x0 0x0 CHKSUM Offset:0x14 Flash Checksum Register 0x14 32 read-only n 0x0 0x0 BootROM Checksum of Boot ROM 16 32 read-only UserROM Checksum of User ROM 0 16 read-only CTRL Offset:0x08 Flash Control Register 0x8 32 read-write n 0x0 0x0 CHK Checksum calculation chosen 7 8 read-write Disable Disable 0 Enable Trigger checksum calculation 1 MER Mass erase mode chosen bit 2 3 read-write 0 Disable masse erase mode 0 1 Enable mass erase mode 1 PER Page erase mode chosen bit 1 2 read-write 0 Disable page erase mode 0 1 Enable page erase mode 1 PG Flash program mode chosen bit 0 1 read-write 0 Disable Flash program mode 0 1 Enable Flash program mode 1 START Start erase/program operation 6 7 read-write 0 Stop/finish operation 0 1 Start erase/program operation 1 DATA Offset:0x0C Flash Data Register 0xC 32 read-write n 0x0 0x0 LPCTRL Offset:0x00 Flash Low Power Control Register 0x0 32 read-write n 0x0 0x0 FMCKEY FMC verify key 16 32 write-only LPMODE Flash Low Power mode selection bit 0 4 read-write 0000b HCLK is less than or equal to 12MHz 0 0010b HCLK is less than or equal to 8KHz 2 0011b HCLK is more than 12MHz, and less than or equal to 24MHz 3 0101b HCLK is more than 24MHz 5 STATUS Offset:0x04 Flash Status Register 0x4 32 read-write n 0x0 0x0 BUSY Busy flag 0 1 read-only Idle FMC is idle 0 Busy Flash operation is in process 1 ERR Erase/Error flag 2 3 read-write No error No error 0 Error The address is illegal or over page boundary 1 SN_GPIO0 General Purpose I/O GPIO 0x0 0x0 0x2000 registers n P0 31 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0x0 BCLR0 Clear Pn.0 0 1 write-only No effect No effect 0 Clear Clear Pn.0 1 BCLR1 Clear Pn.1 1 2 write-only No effect No effect 0 Clear Clear Pn.1 1 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR12 Clear Pn.12 12 13 write-only No effect No effect 0 Clear Clear Pn.12 1 BCLR13 Clear Pn.13 13 14 write-only No effect No effect 0 Clear Clear Pn.13 1 BCLR14 Clear Pn.14 14 15 write-only No effect No effect 0 Clear Clear Pn.14 1 BCLR15 Clear Pn.15 15 16 write-only No effect No effect 0 Clear Clear Pn.15 1 BCLR2 Clear Pn.2 2 3 write-only No effect No effect 0 Clear Clear Pn.2 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0x0 BSET0 Set Pn.0 0 1 write-only No effect No effect 0 Set Set Pn.0 to 1 1 BSET1 Set Pn.1 1 2 write-only No effect No effect 0 Set Set Pn.1 to 1 1 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET12 Set Pn.12 12 13 write-only No effect No effect 0 Set Set Pn.12 to 1 1 BSET13 Set Pn.13 13 14 write-only No effect No effect 0 Set Set Pn.13 to 1 1 BSET14 Set Pn.14 14 15 write-only No effect No effect 0 Set Set Pn.14 to 1 1 BSET15 Set Pn.15 15 16 write-only No effect No effect 0 Set Set Pn.15 to 1 1 BSET2 Set Pn.2 2 3 write-only No effect No effect 0 Set Set Pn.2 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0x0 0x0 CFG0 Configuration of Pn.0 0 2 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG1 Configuration of Pn.1 2 4 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG10 Configuration of Pn.10 20 22 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG11 Configuration of Pn.11 22 24 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG12 Configuration of Pn.12 24 26 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG13 Configuration of Pn.13 26 28 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG14 Configuration of Pn.14 28 30 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG15 Configuration of Pn.15 30 32 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG2 Configuration of Pn.2 4 6 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG3 Configuration of Pn.3 6 8 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG4 Configuration of Pn.4 8 10 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG5 Configuration of Pn.5 10 12 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG6 Configuration of Pn.6 12 14 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG7 Configuration of Pn.7 14 16 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG8 Configuration of Pn.8 16 18 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG9 Configuration of Pn.9 18 20 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0x0 DATA0 Data of Pn.0 0 1 read-write 0 Pn.0 is 0 0 1 Pn.0 is 1 1 DATA1 Data of Pn.1 1 2 read-write 0 Pn.1 is 0 0 1 Pn.1 is 1 1 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA12 Data of Pn.12 12 13 read-write 0 Pn.12 is 0 0 1 Pn.12 is 1 1 DATA13 Data of Pn.13 13 14 read-write 0 Pn.13 is 0 0 1 Pn.13 is 1 1 DATA14 Data of Pn.14 14 15 read-write 0 Pn.14 is 0 0 1 Pn.14 is 1 1 DATA15 Data of Pn.15 15 16 read-write 0 Pn.15 is 0 0 1 Pn.15 is 1 1 DATA2 Data of Pn.2 2 3 read-write 0 Pn.2 is 0 0 1 Pn.2 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0x0 IBS0 Interrupt on Pn.0 is triggered ob both edges 0 1 read-write IEV Interrupt on Pn.0 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.0 trigger an interrupt 1 IBS1 Interrupt on Pn.1 is triggered ob both edges 1 2 read-write IEV Interrupt on Pn.1 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.1 trigger an interrupt 1 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS12 Interrupt on Pn.12 is triggered ob both edges 12 13 read-write IEV Interrupt on Pn.12 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.12 trigger an interrupt 1 IBS13 Interrupt on Pn.13 is triggered ob both edges 13 14 read-write IEV Interrupt on Pn.13 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.13 trigger an interrupt 1 IBS14 Interrupt on Pn.14 is triggered ob both edges 14 15 read-write IEV Interrupt on Pn.14 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.14 trigger an interrupt 1 IBS15 Interrupt on Pn.15 is triggered ob both edges 15 16 read-write IEV Interrupt on Pn.15 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.15 trigger an interrupt 1 IBS2 Interrupt on Pn.2 is triggered ob both edges 2 3 read-write IEV Interrupt on Pn.2 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.2 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0x0 IC0 Pn.0 interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.0 1 IC1 Pn.1 interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.1 1 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC12 Pn.12 interrupt flag clear 12 13 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.12 1 IC13 Pn.13 interrupt flag clear 13 14 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.13 1 IC14 Pn.14 interrupt flag clear 14 15 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.14 1 IC15 Pn.15 interrupt flag clear 15 16 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.15 1 IC2 Pn.2 interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.2 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 IE0 Interrupt on Pn.0 enable 0 1 read-write Disable Disable interrupt on Pn.0 0 Enable Enable interrupt on Pn.0 1 IE1 Interrupt on Pn.1 enable 1 2 read-write Disable Disable interrupt on Pn.1 0 Enable Enable interrupt on Pn.1 1 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE12 Interrupt on Pn.11 enable 12 13 read-write Disable Disable interrupt on Pn.12 0 Enable Enable interrupt on Pn.12 1 IE13 Interrupt on Pn.13 enable 13 14 read-write Disable Disable interrupt on Pn.13 0 Enable Enable interrupt on Pn.13 1 IE14 Interrupt on Pn.14 enable 14 15 read-write Disable Disable interrupt on Pn.14 0 Enable Enable interrupt on Pn.14 1 IE15 Interrupt on Pn.15 enable 15 16 read-write Disable Disable interrupt on Pn.15 0 Enable Enable interrupt on Pn.15 1 IE2 Interrupt on Pn.2 enable 2 3 read-write Disable Disable interrupt on Pn.2 0 Enable Enable interrupt on Pn.2 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0x0 IEV0 Interrupt trigged evnet on Pn.0 0 1 read-write 0 Rising edge or High level on Pn.0 triggers an interrupt 0 1 Falling edge or Low level on Pn.0 triggers an interrupt 1 IEV1 Interrupt trigged evnet on Pn.1 1 2 read-write 0 Rising edge or High level on Pn.1 triggers an interrupt 0 1 Falling edge or Low level on Pn.1 triggers an interrupt 1 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV12 Interrupt trigged evnet on Pn.12 12 13 read-write 0 Rising edge or High level on Pn.12 triggers an interrupt 0 1 Falling edge or Low level on Pn.12 triggers an interrupt 1 IEV13 Interrupt trigged evnet on Pn.13 13 14 read-write 0 Rising edge or High level on Pn.13 triggers an interrupt 0 1 Falling edge or Low level on Pn.13 triggers an interrupt 1 IEV14 Interrupt trigged evnet on Pn.14 14 15 read-write 0 Rising edge or High level on Pn.14 triggers an interrupt 0 1 Falling edge or Low level on Pn.14 triggers an interrupt 1 IEV15 Interrupt trigged evnet on Pn.15 15 16 read-write 0 Rising edge or High level on Pn.15 triggers an interrupt 0 1 Falling edge or Low level on Pn.15 triggers an interrupt 1 IEV2 Interrupt trigged evnet on Pn.2 2 3 read-write 0 Rising edge or High level on Pn.2 triggers an interrupt 0 1 Falling edge or Low level on Pn.2 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0x0 IS0 Interrupt on Pn.0 is event or edge sensitive 0 1 read-write Edge Interrupt on Pn.0 is edge sensitive 0 Event Interrupt on Pn.0 is event sensitive 1 IS1 Interrupt on Pn.1 is event or edge sensitive 1 2 read-write Edge Interrupt on Pn.1 is edge sensitive 0 Event Interrupt on Pn.1 is event sensitive 1 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS12 Interrupt on Pn.12 is event or edge sensitive 12 13 read-write Edge Interrupt on Pn.12 is edge sensitive 0 Event Interrupt on Pn.12 is event sensitive 1 IS13 Interrupt on Pn.13 is event or edge sensitive 13 14 read-write Edge Interrupt on Pn.13 is edge sensitive 0 Event Interrupt on Pn.13 is event sensitive 1 IS14 Interrupt on Pn.14 is event or edge sensitive 14 15 read-write Edge Interrupt on Pn.14 is edge sensitive 0 Event Interrupt on Pn.14 is event sensitive 1 IS15 Interrupt on Pn.15 is event or edge sensitive 15 16 read-write Edge Interrupt on Pn.15 is edge sensitive 0 Event Interrupt on Pn.15 is event sensitive 1 IS2 Interrupt on Pn.2 is event or edge sensitive 2 3 read-write Edge Interrupt on Pn.2 is edge sensitive 0 Event Interrupt on Pn.2 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0x0 MODE0 Mode of Pn.0 0 1 read-write I Pn.0 is Input pin 0 O Pn.0 is Output pin 1 MODE1 Mode of Pn.1 1 2 read-write I Pn.1 is Input pin 0 O Pn.1 is Output pin 1 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE12 Mode of Pn.12 12 13 read-write I Pn.12 is Input pin 0 O Pn.12 is Output pin 1 MODE13 Mode of Pn.13 13 14 read-write I Pn.13 is Input pin 0 O Pn.13 is Output pin 1 MODE14 Mode of Pn.14 14 15 read-write I Pn.14 is Input pin 0 O Pn.14 is Output pin 1 MODE15 Mode of Pn.15 15 16 read-write I Pn.15 is Input pin 0 O Pn.15 is Output pin 1 MODE2 Mode of Pn.2 2 3 read-write I Pn.2 is Input pin 0 O Pn.2 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 IF0 Pn.0 raw interrupt flag 0 1 read-only 0 No interrupt on Pn.0 0 1 Interrupt requirements met on Pn.0 1 IF1 Pn.1 raw interrupt flag 1 2 read-only 0 No interrupt on Pn.1 0 1 Interrupt requirements met on Pn.1 1 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF12 Pn.12 raw interrupt flag 12 13 read-only 0 No interrupt on Pn.12 0 1 Interrupt requirements met on Pn.12 1 IF13 Pn.13 raw interrupt flag 13 14 read-only 0 No interrupt on Pn.13 0 1 Interrupt requirements met on Pn.13 1 IF14 Pn.14 raw interrupt flag 14 15 read-only 0 No interrupt on Pn.14 0 1 Interrupt requirements met on Pn.14 1 IF15 Pn.15 raw interrupt flag 15 16 read-only 0 No interrupt on Pn.15 0 1 Interrupt requirements met on Pn.15 1 IF2 Pn.2 raw interrupt flag 2 3 read-only 0 No interrupt on Pn.2 0 1 Interrupt requirements met on Pn.2 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_GPIO1 General Purpose I/O GPIO 0x0 0x0 0x2000 registers n P1 30 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0x0 BCLR0 Clear Pn.0 0 1 write-only No effect No effect 0 Clear Clear Pn.0 1 BCLR1 Clear Pn.1 1 2 write-only No effect No effect 0 Clear Clear Pn.1 1 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR12 Clear Pn.12 12 13 write-only No effect No effect 0 Clear Clear Pn.12 1 BCLR13 Clear Pn.13 13 14 write-only No effect No effect 0 Clear Clear Pn.13 1 BCLR14 Clear Pn.14 14 15 write-only No effect No effect 0 Clear Clear Pn.14 1 BCLR15 Clear Pn.15 15 16 write-only No effect No effect 0 Clear Clear Pn.15 1 BCLR2 Clear Pn.2 2 3 write-only No effect No effect 0 Clear Clear Pn.2 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0x0 BSET0 Set Pn.0 0 1 write-only No effect No effect 0 Set Set Pn.0 to 1 1 BSET1 Set Pn.1 1 2 write-only No effect No effect 0 Set Set Pn.1 to 1 1 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET12 Set Pn.12 12 13 write-only No effect No effect 0 Set Set Pn.12 to 1 1 BSET13 Set Pn.13 13 14 write-only No effect No effect 0 Set Set Pn.13 to 1 1 BSET14 Set Pn.14 14 15 write-only No effect No effect 0 Set Set Pn.14 to 1 1 BSET15 Set Pn.15 15 16 write-only No effect No effect 0 Set Set Pn.15 to 1 1 BSET2 Set Pn.2 2 3 write-only No effect No effect 0 Set Set Pn.2 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0x0 0x0 CFG0 Configuration of Pn.0 0 2 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG1 Configuration of Pn.1 2 4 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG10 Configuration of Pn.10 20 22 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG11 Configuration of Pn.11 22 24 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG12 Configuration of Pn.12 24 26 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG13 Configuration of Pn.13 26 28 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG14 Configuration of Pn.14 28 30 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG15 Configuration of Pn.15 30 32 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG2 Configuration of Pn.2 4 6 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG3 Configuration of Pn.3 6 8 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG4 Configuration of Pn.4 8 10 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG5 Configuration of Pn.5 10 12 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG6 Configuration of Pn.6 12 14 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG7 Configuration of Pn.7 14 16 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG8 Configuration of Pn.8 16 18 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG9 Configuration of Pn.9 18 20 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0x0 DATA0 Data of Pn.0 0 1 read-write 0 Pn.0 is 0 0 1 Pn.0 is 1 1 DATA1 Data of Pn.1 1 2 read-write 0 Pn.1 is 0 0 1 Pn.1 is 1 1 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA12 Data of Pn.12 12 13 read-write 0 Pn.12 is 0 0 1 Pn.12 is 1 1 DATA13 Data of Pn.13 13 14 read-write 0 Pn.13 is 0 0 1 Pn.13 is 1 1 DATA14 Data of Pn.14 14 15 read-write 0 Pn.14 is 0 0 1 Pn.14 is 1 1 DATA15 Data of Pn.15 15 16 read-write 0 Pn.15 is 0 0 1 Pn.15 is 1 1 DATA2 Data of Pn.2 2 3 read-write 0 Pn.2 is 0 0 1 Pn.2 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0x0 IBS0 Interrupt on Pn.0 is triggered ob both edges 0 1 read-write IEV Interrupt on Pn.0 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.0 trigger an interrupt 1 IBS1 Interrupt on Pn.1 is triggered ob both edges 1 2 read-write IEV Interrupt on Pn.1 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.1 trigger an interrupt 1 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS12 Interrupt on Pn.12 is triggered ob both edges 12 13 read-write IEV Interrupt on Pn.12 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.12 trigger an interrupt 1 IBS13 Interrupt on Pn.13 is triggered ob both edges 13 14 read-write IEV Interrupt on Pn.13 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.13 trigger an interrupt 1 IBS14 Interrupt on Pn.14 is triggered ob both edges 14 15 read-write IEV Interrupt on Pn.14 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.14 trigger an interrupt 1 IBS15 Interrupt on Pn.15 is triggered ob both edges 15 16 read-write IEV Interrupt on Pn.15 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.15 trigger an interrupt 1 IBS2 Interrupt on Pn.2 is triggered ob both edges 2 3 read-write IEV Interrupt on Pn.2 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.2 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0x0 IC0 Pn.0 interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.0 1 IC1 Pn.1 interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.1 1 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC12 Pn.12 interrupt flag clear 12 13 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.12 1 IC13 Pn.13 interrupt flag clear 13 14 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.13 1 IC14 Pn.14 interrupt flag clear 14 15 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.14 1 IC15 Pn.15 interrupt flag clear 15 16 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.15 1 IC2 Pn.2 interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.2 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 IE0 Interrupt on Pn.0 enable 0 1 read-write Disable Disable interrupt on Pn.0 0 Enable Enable interrupt on Pn.0 1 IE1 Interrupt on Pn.1 enable 1 2 read-write Disable Disable interrupt on Pn.1 0 Enable Enable interrupt on Pn.1 1 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE12 Interrupt on Pn.11 enable 12 13 read-write Disable Disable interrupt on Pn.12 0 Enable Enable interrupt on Pn.12 1 IE13 Interrupt on Pn.13 enable 13 14 read-write Disable Disable interrupt on Pn.13 0 Enable Enable interrupt on Pn.13 1 IE14 Interrupt on Pn.14 enable 14 15 read-write Disable Disable interrupt on Pn.14 0 Enable Enable interrupt on Pn.14 1 IE15 Interrupt on Pn.15 enable 15 16 read-write Disable Disable interrupt on Pn.15 0 Enable Enable interrupt on Pn.15 1 IE2 Interrupt on Pn.2 enable 2 3 read-write Disable Disable interrupt on Pn.2 0 Enable Enable interrupt on Pn.2 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0x0 IEV0 Interrupt trigged evnet on Pn.0 0 1 read-write 0 Rising edge or High level on Pn.0 triggers an interrupt 0 1 Falling edge or Low level on Pn.0 triggers an interrupt 1 IEV1 Interrupt trigged evnet on Pn.1 1 2 read-write 0 Rising edge or High level on Pn.1 triggers an interrupt 0 1 Falling edge or Low level on Pn.1 triggers an interrupt 1 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV12 Interrupt trigged evnet on Pn.12 12 13 read-write 0 Rising edge or High level on Pn.12 triggers an interrupt 0 1 Falling edge or Low level on Pn.12 triggers an interrupt 1 IEV13 Interrupt trigged evnet on Pn.13 13 14 read-write 0 Rising edge or High level on Pn.13 triggers an interrupt 0 1 Falling edge or Low level on Pn.13 triggers an interrupt 1 IEV14 Interrupt trigged evnet on Pn.14 14 15 read-write 0 Rising edge or High level on Pn.14 triggers an interrupt 0 1 Falling edge or Low level on Pn.14 triggers an interrupt 1 IEV15 Interrupt trigged evnet on Pn.15 15 16 read-write 0 Rising edge or High level on Pn.15 triggers an interrupt 0 1 Falling edge or Low level on Pn.15 triggers an interrupt 1 IEV2 Interrupt trigged evnet on Pn.2 2 3 read-write 0 Rising edge or High level on Pn.2 triggers an interrupt 0 1 Falling edge or Low level on Pn.2 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0x0 IS0 Interrupt on Pn.0 is event or edge sensitive 0 1 read-write Edge Interrupt on Pn.0 is edge sensitive 0 Event Interrupt on Pn.0 is event sensitive 1 IS1 Interrupt on Pn.1 is event or edge sensitive 1 2 read-write Edge Interrupt on Pn.1 is edge sensitive 0 Event Interrupt on Pn.1 is event sensitive 1 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS12 Interrupt on Pn.12 is event or edge sensitive 12 13 read-write Edge Interrupt on Pn.12 is edge sensitive 0 Event Interrupt on Pn.12 is event sensitive 1 IS13 Interrupt on Pn.13 is event or edge sensitive 13 14 read-write Edge Interrupt on Pn.13 is edge sensitive 0 Event Interrupt on Pn.13 is event sensitive 1 IS14 Interrupt on Pn.14 is event or edge sensitive 14 15 read-write Edge Interrupt on Pn.14 is edge sensitive 0 Event Interrupt on Pn.14 is event sensitive 1 IS15 Interrupt on Pn.15 is event or edge sensitive 15 16 read-write Edge Interrupt on Pn.15 is edge sensitive 0 Event Interrupt on Pn.15 is event sensitive 1 IS2 Interrupt on Pn.2 is event or edge sensitive 2 3 read-write Edge Interrupt on Pn.2 is edge sensitive 0 Event Interrupt on Pn.2 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0x0 MODE0 Mode of Pn.0 0 1 read-write I Pn.0 is Input pin 0 O Pn.0 is Output pin 1 MODE1 Mode of Pn.1 1 2 read-write I Pn.1 is Input pin 0 O Pn.1 is Output pin 1 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE12 Mode of Pn.12 12 13 read-write I Pn.12 is Input pin 0 O Pn.12 is Output pin 1 MODE13 Mode of Pn.13 13 14 read-write I Pn.13 is Input pin 0 O Pn.13 is Output pin 1 MODE14 Mode of Pn.14 14 15 read-write I Pn.14 is Input pin 0 O Pn.14 is Output pin 1 MODE15 Mode of Pn.15 15 16 read-write I Pn.15 is Input pin 0 O Pn.15 is Output pin 1 MODE2 Mode of Pn.2 2 3 read-write I Pn.2 is Input pin 0 O Pn.2 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 IF0 Pn.0 raw interrupt flag 0 1 read-only 0 No interrupt on Pn.0 0 1 Interrupt requirements met on Pn.0 1 IF1 Pn.1 raw interrupt flag 1 2 read-only 0 No interrupt on Pn.1 0 1 Interrupt requirements met on Pn.1 1 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF12 Pn.12 raw interrupt flag 12 13 read-only 0 No interrupt on Pn.12 0 1 Interrupt requirements met on Pn.12 1 IF13 Pn.13 raw interrupt flag 13 14 read-only 0 No interrupt on Pn.13 0 1 Interrupt requirements met on Pn.13 1 IF14 Pn.14 raw interrupt flag 14 15 read-only 0 No interrupt on Pn.14 0 1 Interrupt requirements met on Pn.14 1 IF15 Pn.15 raw interrupt flag 15 16 read-only 0 No interrupt on Pn.15 0 1 Interrupt requirements met on Pn.15 1 IF2 Pn.2 raw interrupt flag 2 3 read-only 0 No interrupt on Pn.2 0 1 Interrupt requirements met on Pn.2 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_GPIO2 General Purpose I/O GPIO 0x0 0x0 0x2000 registers n P2 29 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0x0 BCLR0 Clear Pn.0 0 1 write-only No effect No effect 0 Clear Clear Pn.0 1 BCLR1 Clear Pn.1 1 2 write-only No effect No effect 0 Clear Clear Pn.1 1 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR12 Clear Pn.12 12 13 write-only No effect No effect 0 Clear Clear Pn.12 1 BCLR13 Clear Pn.13 13 14 write-only No effect No effect 0 Clear Clear Pn.13 1 BCLR14 Clear Pn.14 14 15 write-only No effect No effect 0 Clear Clear Pn.14 1 BCLR15 Clear Pn.15 15 16 write-only No effect No effect 0 Clear Clear Pn.15 1 BCLR2 Clear Pn.2 2 3 write-only No effect No effect 0 Clear Clear Pn.2 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0x0 BSET0 Set Pn.0 0 1 write-only No effect No effect 0 Set Set Pn.0 to 1 1 BSET1 Set Pn.1 1 2 write-only No effect No effect 0 Set Set Pn.1 to 1 1 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET12 Set Pn.12 12 13 write-only No effect No effect 0 Set Set Pn.12 to 1 1 BSET13 Set Pn.13 13 14 write-only No effect No effect 0 Set Set Pn.13 to 1 1 BSET14 Set Pn.14 14 15 write-only No effect No effect 0 Set Set Pn.14 to 1 1 BSET15 Set Pn.15 15 16 write-only No effect No effect 0 Set Set Pn.15 to 1 1 BSET2 Set Pn.2 2 3 write-only No effect No effect 0 Set Set Pn.2 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0x0 0x0 CFG0 Configuration of Pn.0 0 2 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG1 Configuration of Pn.1 2 4 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG10 Configuration of Pn.10 20 22 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG11 Configuration of Pn.11 22 24 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG12 Configuration of Pn.12 24 26 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG13 Configuration of Pn.13 26 28 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG14 Configuration of Pn.14 28 30 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG15 Configuration of Pn.15 30 32 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG2 Configuration of Pn.2 4 6 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG3 Configuration of Pn.3 6 8 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG4 Configuration of Pn.4 8 10 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG5 Configuration of Pn.5 10 12 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG6 Configuration of Pn.6 12 14 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG7 Configuration of Pn.7 14 16 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG8 Configuration of Pn.8 16 18 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG9 Configuration of Pn.9 18 20 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0x0 DATA0 Data of Pn.0 0 1 read-write 0 Pn.0 is 0 0 1 Pn.0 is 1 1 DATA1 Data of Pn.1 1 2 read-write 0 Pn.1 is 0 0 1 Pn.1 is 1 1 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA12 Data of Pn.12 12 13 read-write 0 Pn.12 is 0 0 1 Pn.12 is 1 1 DATA13 Data of Pn.13 13 14 read-write 0 Pn.13 is 0 0 1 Pn.13 is 1 1 DATA14 Data of Pn.14 14 15 read-write 0 Pn.14 is 0 0 1 Pn.14 is 1 1 DATA15 Data of Pn.15 15 16 read-write 0 Pn.15 is 0 0 1 Pn.15 is 1 1 DATA2 Data of Pn.2 2 3 read-write 0 Pn.2 is 0 0 1 Pn.2 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0x0 IBS0 Interrupt on Pn.0 is triggered ob both edges 0 1 read-write IEV Interrupt on Pn.0 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.0 trigger an interrupt 1 IBS1 Interrupt on Pn.1 is triggered ob both edges 1 2 read-write IEV Interrupt on Pn.1 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.1 trigger an interrupt 1 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS12 Interrupt on Pn.12 is triggered ob both edges 12 13 read-write IEV Interrupt on Pn.12 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.12 trigger an interrupt 1 IBS13 Interrupt on Pn.13 is triggered ob both edges 13 14 read-write IEV Interrupt on Pn.13 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.13 trigger an interrupt 1 IBS14 Interrupt on Pn.14 is triggered ob both edges 14 15 read-write IEV Interrupt on Pn.14 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.14 trigger an interrupt 1 IBS15 Interrupt on Pn.15 is triggered ob both edges 15 16 read-write IEV Interrupt on Pn.15 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.15 trigger an interrupt 1 IBS2 Interrupt on Pn.2 is triggered ob both edges 2 3 read-write IEV Interrupt on Pn.2 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.2 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0x0 IC0 Pn.0 interrupt flag clear 0 1 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.0 1 IC1 Pn.1 interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.1 1 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC12 Pn.12 interrupt flag clear 12 13 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.12 1 IC13 Pn.13 interrupt flag clear 13 14 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.13 1 IC14 Pn.14 interrupt flag clear 14 15 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.14 1 IC15 Pn.15 interrupt flag clear 15 16 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.15 1 IC2 Pn.2 interrupt flag clear 2 3 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.2 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 IE0 Interrupt on Pn.0 enable 0 1 read-write Disable Disable interrupt on Pn.0 0 Enable Enable interrupt on Pn.0 1 IE1 Interrupt on Pn.1 enable 1 2 read-write Disable Disable interrupt on Pn.1 0 Enable Enable interrupt on Pn.1 1 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE12 Interrupt on Pn.11 enable 12 13 read-write Disable Disable interrupt on Pn.12 0 Enable Enable interrupt on Pn.12 1 IE13 Interrupt on Pn.13 enable 13 14 read-write Disable Disable interrupt on Pn.13 0 Enable Enable interrupt on Pn.13 1 IE14 Interrupt on Pn.14 enable 14 15 read-write Disable Disable interrupt on Pn.14 0 Enable Enable interrupt on Pn.14 1 IE15 Interrupt on Pn.15 enable 15 16 read-write Disable Disable interrupt on Pn.15 0 Enable Enable interrupt on Pn.15 1 IE2 Interrupt on Pn.2 enable 2 3 read-write Disable Disable interrupt on Pn.2 0 Enable Enable interrupt on Pn.2 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0x0 IEV0 Interrupt trigged evnet on Pn.0 0 1 read-write 0 Rising edge or High level on Pn.0 triggers an interrupt 0 1 Falling edge or Low level on Pn.0 triggers an interrupt 1 IEV1 Interrupt trigged evnet on Pn.1 1 2 read-write 0 Rising edge or High level on Pn.1 triggers an interrupt 0 1 Falling edge or Low level on Pn.1 triggers an interrupt 1 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV12 Interrupt trigged evnet on Pn.12 12 13 read-write 0 Rising edge or High level on Pn.12 triggers an interrupt 0 1 Falling edge or Low level on Pn.12 triggers an interrupt 1 IEV13 Interrupt trigged evnet on Pn.13 13 14 read-write 0 Rising edge or High level on Pn.13 triggers an interrupt 0 1 Falling edge or Low level on Pn.13 triggers an interrupt 1 IEV14 Interrupt trigged evnet on Pn.14 14 15 read-write 0 Rising edge or High level on Pn.14 triggers an interrupt 0 1 Falling edge or Low level on Pn.14 triggers an interrupt 1 IEV15 Interrupt trigged evnet on Pn.15 15 16 read-write 0 Rising edge or High level on Pn.15 triggers an interrupt 0 1 Falling edge or Low level on Pn.15 triggers an interrupt 1 IEV2 Interrupt trigged evnet on Pn.2 2 3 read-write 0 Rising edge or High level on Pn.2 triggers an interrupt 0 1 Falling edge or Low level on Pn.2 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0x0 IS0 Interrupt on Pn.0 is event or edge sensitive 0 1 read-write Edge Interrupt on Pn.0 is edge sensitive 0 Event Interrupt on Pn.0 is event sensitive 1 IS1 Interrupt on Pn.1 is event or edge sensitive 1 2 read-write Edge Interrupt on Pn.1 is edge sensitive 0 Event Interrupt on Pn.1 is event sensitive 1 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS12 Interrupt on Pn.12 is event or edge sensitive 12 13 read-write Edge Interrupt on Pn.12 is edge sensitive 0 Event Interrupt on Pn.12 is event sensitive 1 IS13 Interrupt on Pn.13 is event or edge sensitive 13 14 read-write Edge Interrupt on Pn.13 is edge sensitive 0 Event Interrupt on Pn.13 is event sensitive 1 IS14 Interrupt on Pn.14 is event or edge sensitive 14 15 read-write Edge Interrupt on Pn.14 is edge sensitive 0 Event Interrupt on Pn.14 is event sensitive 1 IS15 Interrupt on Pn.15 is event or edge sensitive 15 16 read-write Edge Interrupt on Pn.15 is edge sensitive 0 Event Interrupt on Pn.15 is event sensitive 1 IS2 Interrupt on Pn.2 is event or edge sensitive 2 3 read-write Edge Interrupt on Pn.2 is edge sensitive 0 Event Interrupt on Pn.2 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0x0 MODE0 Mode of Pn.0 0 1 read-write I Pn.0 is Input pin 0 O Pn.0 is Output pin 1 MODE1 Mode of Pn.1 1 2 read-write I Pn.1 is Input pin 0 O Pn.1 is Output pin 1 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE12 Mode of Pn.12 12 13 read-write I Pn.12 is Input pin 0 O Pn.12 is Output pin 1 MODE13 Mode of Pn.13 13 14 read-write I Pn.13 is Input pin 0 O Pn.13 is Output pin 1 MODE14 Mode of Pn.14 14 15 read-write I Pn.14 is Input pin 0 O Pn.14 is Output pin 1 MODE15 Mode of Pn.15 15 16 read-write I Pn.15 is Input pin 0 O Pn.15 is Output pin 1 MODE2 Mode of Pn.2 2 3 read-write I Pn.2 is Input pin 0 O Pn.2 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 IF0 Pn.0 raw interrupt flag 0 1 read-only 0 No interrupt on Pn.0 0 1 Interrupt requirements met on Pn.0 1 IF1 Pn.1 raw interrupt flag 1 2 read-only 0 No interrupt on Pn.1 0 1 Interrupt requirements met on Pn.1 1 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF12 Pn.12 raw interrupt flag 12 13 read-only 0 No interrupt on Pn.12 0 1 Interrupt requirements met on Pn.12 1 IF13 Pn.13 raw interrupt flag 13 14 read-only 0 No interrupt on Pn.13 0 1 Interrupt requirements met on Pn.13 1 IF14 Pn.14 raw interrupt flag 14 15 read-only 0 No interrupt on Pn.14 0 1 Interrupt requirements met on Pn.14 1 IF15 Pn.15 raw interrupt flag 15 16 read-only 0 No interrupt on Pn.15 0 1 Interrupt requirements met on Pn.15 1 IF2 Pn.2 raw interrupt flag 2 3 read-only 0 No interrupt on Pn.2 0 1 Interrupt requirements met on Pn.2 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_GPIO3 General Purpose I/O GPIO 0x0 0x0 0x2000 registers n P3 28 BCLR Offset:0x28 GPIO Port n Bits Clear Operation Register 0x28 32 write-only n 0x0 0x0 BCLR10 Clear Pn.10 10 11 write-only No effect No effect 0 Clear Clear Pn.10 1 BCLR11 Clear Pn.11 11 12 write-only No effect No effect 0 Clear Clear Pn.11 1 BCLR3 Clear Pn.3 3 4 write-only No effect No effect 0 Clear Clear Pn.3 1 BCLR4 Clear Pn.4 4 5 write-only No effect No effect 0 Clear Clear Pn.4 1 BCLR5 Clear Pn.5 5 6 write-only No effect No effect 0 Clear Clear Pn.5 1 BCLR6 Clear Pn.6 6 7 write-only No effect No effect 0 Clear Clear Pn.6 1 BCLR7 Clear Pn.7 7 8 write-only No effect No effect 0 Clear Clear Pn.7 1 BCLR8 Clear Pn.8 8 9 write-only No effect No effect 0 Clear Clear Pn.8 1 BCLR9 Clear Pn.9 9 10 write-only No effect No effect 0 Clear Clear Pn.9 1 BSET Offset:0x24 GPIO Port n Bits Set Operation Register 0x24 32 write-only n 0x0 0x0 BSET10 Set Pn.10 10 11 write-only No effect No effect 0 Set Set Pn.10 to 1 1 BSET11 Set Pn.11 11 12 write-only No effect No effect 0 Set Set Pn.11 to 1 1 BSET3 Set Pn.3 3 4 write-only No effect No effect 0 Set Set Pn.3 to 1 1 BSET4 Set Pn.4 4 5 write-only No effect No effect 0 Set Set Pn.4 to 1 1 BSET5 Set Pn.5 5 6 write-only No effect No effect 0 Set Set Pn.5 to 1 1 BSET6 Set Pn.6 6 7 write-only No effect No effect 0 Set Set Pn.6 to 1 1 BSET7 Set Pn.7 7 8 write-only No effect No effect 0 Set Set Pn.7 to 1 1 BSET8 Set Pn.8 8 9 write-only No effect No effect 0 Set Set Pn.8 to 1 1 BSET9 Set Pn.9 9 10 write-only No effect No effect 0 Set Set Pn.9 to 1 1 CFG Offset:0x08 GPIO Port n Configuration Register 0x8 32 read-write n 0x0 0x0 CFG10 Configuration of Pn.10 20 22 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG11 Configuration of Pn.11 22 24 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG3 Configuration of Pn.3 6 8 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG4 Configuration of Pn.4 8 10 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG5 Configuration of Pn.5 10 12 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG6 Configuration of Pn.6 12 14 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG7 Configuration of Pn.7 14 16 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG8 Configuration of Pn.8 16 18 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data register keep low) 3 CFG9 Configuration of Pn.9 18 20 read-write 00 Enable pull-up resistor 0 10 Inactive. (no pull-up resistor enabled, Schmitt trigger enabled) 2 11 No pull-up resistor enabled, Schmitt trigger disabled 3 DATA Offset:0x00 GPIO Port n Data Register 0x0 32 read-write n 0x0 0x0 DATA10 Data of Pn.10 10 11 read-write 0 Pn.10 is 0 0 1 Pn.10 is 1 1 DATA11 Data of Pn.11 11 12 read-write 0 Pn.11 is 0 0 1 Pn.11 is 1 1 DATA3 Data of Pn.3 3 4 read-write 0 Pn.3 is 0 0 1 Pn.3 is 1 1 DATA4 Data of Pn.4 4 5 read-write 0 Pn.4 is 0 0 1 Pn.4 is 1 1 DATA5 Data of Pn.5 5 6 read-write 0 Pn.5 is 0 0 1 Pn.5 is 1 1 DATA6 Data of Pn.6 6 7 read-write 0 Pn.6 is 0 0 1 Pn.6 is 1 1 DATA7 Data of Pn.7 7 8 read-write 0 Pn.7 is 0 0 1 Pn.7 is 1 1 DATA8 Data of Pn.8 8 9 read-write 0 Pn.8 is 0 0 1 Pn.8 is 1 1 DATA9 Data of Pn.9 9 10 read-write 0 Pn.9 is 0 0 1 Pn.9 is 1 1 IBS Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register 0x10 32 read-write n 0x0 0x0 IBS10 Interrupt on Pn.10 is triggered ob both edges 10 11 read-write IEV Interrupt on Pn.10 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.10 trigger an interrupt 1 IBS11 Interrupt on Pn.11 is triggered ob both edges 11 12 read-write IEV Interrupt on Pn.11 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.11 trigger an interrupt 1 IBS3 Interrupt on Pn.3 is triggered ob both edges 3 4 read-write IEV Interrupt on Pn.3 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.3 trigger an interrupt 1 IBS4 Interrupt on Pn.4 is triggered ob both edges 4 5 read-write IEV Interrupt on Pn.4 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.4 trigger an interrupt 1 IBS5 Interrupt on Pn.5 is triggered ob both edges 5 6 read-write IEV Interrupt on Pn.5 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.5 trigger an interrupt 1 IBS6 Interrupt on Pn.6 is triggered ob both edges 6 7 read-write IEV Interrupt on Pn.6 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.6 trigger an interrupt 1 IBS7 Interrupt on Pn.7 is triggered ob both edges 7 8 read-write IEV Interrupt on Pn.7 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.7 trigger an interrupt 1 IBS8 Interrupt on Pn.8 is triggered ob both edges 8 9 read-write IEV Interrupt on Pn.8 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.8 trigger an interrupt 1 IBS9 Interrupt on Pn.9 is triggered ob both edges 9 10 read-write IEV Interrupt on Pn.9 is controlled by GPIOn_IEV register 0 Both edge Both edges on Pn.9 trigger an interrupt 1 IC Offset:0x20 GPIO Port n Interrupt Clear Register 0x20 32 write-only n 0x0 0x0 IC10 Pn.10 interrupt flag clear 10 11 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.10 1 IC11 Pn.11 interrupt flag clear 11 12 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.11 1 IC3 Pn.3 interrupt flag clear 3 4 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.3 1 IC4 Pn.4 interrupt flag clear 4 5 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.4 1 IC5 Pn.5 interrupt flag clear 5 6 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.5 1 IC6 Pn.6 interrupt flag clear 6 7 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.6 1 IC7 Pn.7 interrupt flag clear 7 8 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.7 1 IC8 Pn.8 interrupt flag clear 8 9 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.8 1 IC9 Pn.9 interrupt flag clear 9 10 write-only No effect No effect 0 Clear Clear interrupt flag on Pn.9 1 IE Offset:0x18 GPIO Port n Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 IE10 Interrupt on Pn.10 enable 10 11 read-write Disable Disable interrupt on Pn.10 0 Enable Enable interrupt on Pn.10 1 IE11 Interrupt on Pn.11 enable 11 12 read-write Disable Disable interrupt on Pn.11 0 Enable Enable interrupt on Pn.11 1 IE3 Interrupt on Pn.3 enable 3 4 read-write Disable Disable interrupt on Pn.3 0 Enable Enable interrupt on Pn.3 1 IE4 Interrupt on Pn.4 enable 4 5 read-write Disable Disable interrupt on Pn.4 0 Enable Enable interrupt on Pn.4 1 IE5 Interrupt on Pn.5 enable 5 6 read-write Disable Disable interrupt on Pn.5 0 Enable Enable interrupt on Pn.5 1 IE6 Interrupt on Pn.6 enable 6 7 read-write Disable Disable interrupt on Pn.6 0 Enable Enable interrupt on Pn.6 1 IE7 Interrupt on Pn.7 enable 7 8 read-write Disable Disable interrupt on Pn.7 0 Enable Enable interrupt on Pn.7 1 IE8 Interrupt on Pn.8 enable 8 9 read-write Disable Disable interrupt on Pn.8 0 Enable Enable interrupt on Pn.8 1 IE9 Interrupt on Pn.9 enable 9 10 read-write Disable Disable interrupt on Pn.9 0 Enable Enable interrupt on Pn.9 1 IEV Offset:0x14 GPIO Port n Interrupt Event Register 0x14 32 read-write n 0x0 0x0 IEV10 Interrupt trigged evnet on Pn.10 10 11 read-write 0 Rising edge or High level on Pn.10 triggers an interrupt 0 1 Falling edge or Low level on Pn.10 triggers an interrupt 1 IEV11 Interrupt trigged evnet on Pn.11 11 12 read-write 0 Rising edge or High level on Pn.11 triggers an interrupt 0 1 Falling edge or Low level on Pn.11 triggers an interrupt 1 IEV3 Interrupt trigged evnet on Pn.3 3 4 read-write 0 Rising edge or High level on Pn.3 triggers an interrupt 0 1 Falling edge or Low level on Pn.3 triggers an interrupt 1 IEV4 Interrupt trigged evnet on Pn.4 4 5 read-write 0 Rising edge or High level on Pn.4 triggers an interrupt 0 1 Falling edge or Low level on Pn.4 triggers an interrupt 1 IEV5 Interrupt trigged evnet on Pn.5 5 6 read-write 0 Rising edge or High level on Pn.5 triggers an interrupt 0 1 Falling edge or Low level on Pn.5 triggers an interrupt 1 IEV6 Interrupt trigged evnet on Pn.6 6 7 read-write 0 Rising edge or High level on Pn.6 triggers an interrupt 0 1 Falling edge or Low level on Pn.6 triggers an interrupt 1 IEV7 Interrupt trigged evnet on Pn.7 7 8 read-write 0 Rising edge or High level on Pn.7 triggers an interrupt 0 1 Falling edge or Low level on Pn.7 triggers an interrupt 1 IEV8 Interrupt trigged evnet on Pn.8 8 9 read-write 0 Rising edge or High level on Pn.8 triggers an interrupt 0 1 Falling edge or Low level on Pn.8 triggers an interrupt 1 IEV9 Interrupt trigged evnet on Pn.9 9 10 read-write 0 Rising edge or High level on Pn.9 triggers an interrupt 0 1 Falling edge or Low level on Pn.9 triggers an interrupt 1 IS Offset:0x0C GPIO Port n Interrupt Sense Register 0xC 32 read-write n 0x0 0x0 IS10 Interrupt on Pn.10 is event or edge sensitive 10 11 read-write Edge Interrupt on Pn.10 is edge sensitive 0 Event Interrupt on Pn.10 is event sensitive 1 IS11 Interrupt on Pn.11 is event or edge sensitive 11 12 read-write Edge Interrupt on Pn.11 is edge sensitive 0 Event Interrupt on Pn.11 is event sensitive 1 IS3 Interrupt on Pn.3 is event or edge sensitive 3 4 read-write Edge Interrupt on Pn.3 is edge sensitive 0 Event Interrupt on Pn.3 is event sensitive 1 IS4 Interrupt on Pn.4 is event or edge sensitive 4 5 read-write Edge Interrupt on Pn.4 is edge sensitive 0 Event Interrupt on Pn.4 is event sensitive 1 IS5 Interrupt on Pn.5 is event or edge sensitive 5 6 read-write Edge Interrupt on Pn.5 is edge sensitive 0 Event Interrupt on Pn.5 is event sensitive 1 IS6 Interrupt on Pn.6 is event or edge sensitive 6 7 read-write Edge Interrupt on Pn.6 is edge sensitive 0 Event Interrupt on Pn.6 is event sensitive 1 IS7 Interrupt on Pn.7 is event or edge sensitive 7 8 read-write Edge Interrupt on Pn.7 is edge sensitive 0 Event Interrupt on Pn.7 is event sensitive 1 IS8 Interrupt on Pn.8 is event or edge sensitive 8 9 read-write Edge Interrupt on Pn.8 is edge sensitive 0 Event Interrupt on Pn.8 is event sensitive 1 IS9 Interrupt on Pn.9 is event or edge sensitive 9 10 read-write Edge Interrupt on Pn.9 is edge sensitive 0 Event Interrupt on Pn.9 is event sensitive 1 MODE Offset:0x04 GPIO Port n Mode Register 0x4 32 read-write n 0x0 0x0 MODE10 Mode of Pn.10 10 11 read-write I Pn.10 is Input pin 0 O Pn.10 is Output pin 1 MODE11 Mode of Pn.11 11 12 read-write I Pn.11 is Input pin 0 O Pn.11 is Output pin 1 MODE3 Mode of Pn.3 3 4 read-write I Pn.3 is Input pin 0 O Pn.3 is Output pin 1 MODE4 Mode of Pn.4 4 5 read-write I Pn.4 is Input pin 0 O Pn.4 is Output pin 1 MODE5 Mode of Pn.5 5 6 read-write I Pn.5 is Input pin 0 O Pn.5 is Output pin 1 MODE6 Mode of Pn.6 6 7 read-write I Pn.6 is Input pin 0 O Pn.6 is Output pin 1 MODE7 Mode of Pn.7 7 8 read-write I Pn.7 is Input pin 0 O Pn.7 is Output pin 1 MODE8 Mode of Pn.8 8 9 read-write I Pn.8 is Input pin 0 O Pn.8 is Output pin 1 MODE9 Mode of Pn.9 9 10 read-write I Pn.9 is Input pin 0 O Pn.9 is Output pin 1 RIS Offset:0x1C GPIO Port n Raw Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 IF10 Pn.10 raw interrupt flag 10 11 read-only 0 No interrupt on Pn.10 0 1 Interrupt requirements met on Pn.10 1 IF11 Pn.11 raw interrupt flag 11 12 read-only 0 No interrupt on Pn.11 0 1 Interrupt requirements met on Pn.11 1 IF3 Pn.3 raw interrupt flag 3 4 read-only 0 No interrupt on Pn.3 0 1 Interrupt requirements met on Pn.3 1 IF4 Pn.4 raw interrupt flag 4 5 read-only 0 No interrupt on Pn.4 0 1 Interrupt requirements met on Pn.4 1 IF5 Pn.5 raw interrupt flag 5 6 read-only 0 No interrupt on Pn.5 0 1 Interrupt requirements met on Pn.5 1 IF6 Pn.6 raw interrupt flag 6 7 read-only 0 No interrupt on Pn.6 0 1 Interrupt requirements met on Pn.6 1 IF7 Pn.7 raw interrupt flag 7 8 read-only 0 No interrupt on Pn.7 0 1 Interrupt requirements met on Pn.7 1 IF8 Pn.8 raw interrupt flag 8 9 read-only 0 No interrupt on Pn.8 0 1 Interrupt requirements met on Pn.8 1 IF9 Pn.9 raw interrupt flag 9 10 read-only 0 No interrupt on Pn.9 0 1 Interrupt requirements met on Pn.9 1 SN_I2C0 I2C0 I2C 0x0 0x0 0x2000 registers n I2C0 10 CTRL Offset:0x00 I2Cn Control Register 0x0 32 read-write n 0x0 0x0 ACK ACK assert flag 2 3 read-write No Master: No action/Slave: Assert NACK after receiving 0 Assert Assert ACK during the acknowledge clock pulse on SCLn 1 I2CEN I2Cn interface enable 8 9 read-write Disable Disable I2C 0 Enable Enable I2C 1 I2CMODE I2C mode 7 8 read-write Standard/Fast mode Standard/Fast mode 0 NACK NACK assert flag 1 2 read-write No action No action 0 Assert Assert NACK during the acknowledge clock pulse on SCLn 1 STA START assert flag 5 6 read-write No action No START condition or Repeated START condition will be generated 0 Assert Enter master mode and transmit a START or Repeated START condition 1 STO STOP assert flag 4 5 read-write Idle STOP condition idle 0 Assert Transmit a STOP condition in master mode, or recover from an error condition in slave mode 1 RXDATA Offset:0x0C I2Cn RX Data Register 0xC 32 read-only n 0x0 0x0 Data RX Data received when RX_DN=1 0 8 read-only SCLHT Offset:0x20 I2Cn SCL High Time Register 0x20 32 read-write n 0x0 0x0 SCLH SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle 0 8 read-write SCLLT Offset:0x24 I2Cn SCL Low Time Register 0x24 32 read-write n 0x0 0x0 SCLL SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle 0 8 read-write SLVADDR0 Offset:0x10 I2Cn Slave Address 0 Register 0x10 32 read-write n 0x0 0x0 ADDR I2Cn slave address 0 0 10 read-write ADD_MODE Slave address mode 31 32 read-write 0 7-bit slave address mode 0 1 10-bit slave address mode 1 GCEN General call address enable 30 31 read-write Disable Disable general call address 0 Enable Enable general call address (0x0) 1 SLVADDR1 Offset:0x14 I2Cn Slave Address 1 Register 0x14 32 read-write n 0x0 0x0 ADDR I2Cn slave address 1 0 10 read-write SLVADDR2 Offset:0x18 I2Cn Slave Address 2 Register 0x18 32 read-write n 0x0 0x0 ADDR I2Cn slave address 2 0 10 read-write SLVADDR3 Offset:0x1C I2Cn Slave Address 3 Register 0x1C 32 read-write n 0x0 0x0 ADDR I2Cn slave address 3 0 10 read-write STAT Offset:0x04 I2Cn Status Register 0x4 32 read-write n 0x0 0x0 ACK_STAT ACK done status 1 2 read-only No No ACK received 0 Done Receive an ACK 1 I2CIF I2C interrupt flag 15 16 read-write 0 I2C status doesn't change 0 1 I2C status changes 1 LOST_ARB Lost arbitration status 8 9 read-only 0 Not lost arbitration 0 1 Lost arbitration 1 MST I2C master/slave status 5 6 read-only Slave Act as Slave 0 Master Act as Master 1 NACK_STAT NACK done status 2 3 read-only No No NACK received 0 Done Receive a NACK 1 RX_DN RX done status 0 1 read-only Not done No RX with ACK/NACK transfer 0 Done 8-bit RX with ACK/NACK transfer 1 SLV_RX_HIT Slave RX address hit flag 6 7 read-only 0 No matched slave address 0 1 Slave address hit, and is called for RX 1 SLV_TX_HIT Slave TX address hit flag 7 8 read-only 0 No matched slave address 0 1 Slave address hit, and is called for TX 1 START_DN START done status 4 5 read-only No No START condition 0 Assert Transmit or receive a START condition 1 STOP_DN STOP done status 3 4 read-only No No STOP condition 0 Done Transmit or receive a STOP condition 1 TIMEOUT Time-out status 9 10 read-only 0 No timeout 0 1 Timeout 1 TOCTRL Offset:0x2C I2Cn Timeout Control Register 0x2C 32 read-write n 0x0 0x0 TO Timeout period time = TO*I2Cn_PCLK cycle 0 16 read-write TXDATA Offset:0x08 I2Cn TX Data Register 0x8 32 read-write n 0x0 0x0 Data TX Data 0 8 read-write SN_PFPA Peripheral Function Pin Assignment PFPA 0x0 0x0 0x2000 registers n CT16B1 Offset:0x00 PFPA for CT16B1 Register 0x0 32 read-write n 0x0 0x0 PWM00 CT16B1_PWM00 assigned pin 0 1 read-write P0.0 CT16B1_PWM00=P0.0 0 P1.8 CT16B1_PWM00=P1.8 1 PWM01 CT16B1_PWM01 assigned pin 1 2 read-write P0.1 CT16B1_PWM01=P0.1 0 P1.9 CT16B1_PWM01=P1.9 1 PWM02 CT16B1_PWM02 assigned pin 2 3 read-write P0.2 CT16B1_PWM02=P0.2 0 P1.10 CT16B1_PWM02=P1.10 1 PWM03 CT16B1_PWM03 assigned pin 3 4 read-write P0.3 CT16B1_PWM03=P0.3 0 P1.11 CT16B1_PWM03=P1.11 1 PWM04 CT16B1_PWM04 assigned pin 4 5 read-write P0.4 CT16B1_PWM04=P0.4 0 P1.12 CT16B1_PWM04=P1.12 1 PWM05 CT16B1_PWM05 assigned pin 5 6 read-write P0.5 CT16B1_PWM05=P0.5 0 P1.13 CT16B1_PWM05=P1.13 1 PWM06 CT16B1_PWM06 assigned pin 6 7 read-write P0.6 CT16B1_PWM06=P0.6 0 P1.14 CT16B1_PWM06=P1.14 1 PWM07 CT16B1_PWM07 assigned pin 7 8 read-write P0.7 CT16B1_PWM07=P0.7 0 P1.15 CT16B1_PWM07=P1.15 1 PWM08 CT16B1_PWM08 assigned pin 8 9 read-write P0.8 CT16B1_PWM08=P0.8 0 P2.0 CT16B1_PWM08=P2.0 1 PWM09 CT16B1_PWM09 assigned pin 9 10 read-write P0.9 CT16B1_PWM09=P0.9 0 P2.1 CT16B1_PWM09=P2.1 1 PWM10 CT16B1_PWM10 assigned pin 10 11 read-write P0.10 CT16B1_PWM10=P0.10 0 P2.2 CT16B1_PWM10=P2.2 1 PWM11 CT16B1_PWM11 assigned pin 11 12 read-write P0.11 CT16B1_PWM11=P0.11 0 P2.3 CT16B1_PWM11=P2.3 1 PWM12 CT16B1_PWM12 assigned pin 12 13 read-write P0.12 CT16B1_PWM12=P0.12 0 P2.4 CT16B1_PWM12=P2.4 1 PWM13 CT16B1_PWM13 assigned pin 13 14 read-write P0.13 CT16B1_PWM13=P0.13 0 P2.5 CT16B1_PWM13=P2.5 1 PWM14 CT16B1_PWM14 assigned pin 14 15 read-write P0.14 CT16B1_PWM14=P0.14 0 P2.6 CT16B1_PWM14=P2.6 1 PWM15 CT16B1_PWM15 assigned pin 15 16 read-write P0.15 CT16B1_PWM15=P0.15 0 P2.7 CT16B1_PWM15=P2.7 1 PWM16 CT16B1_PWM16 assigned pin 16 17 read-write P1.0 CT16B1_PWM16=P1.0 0 P2.8 CT16B1_PWM16=P2.8 1 PWM17 CT16B1_PWM17 assigned pin 17 18 read-write P1.1 CT16B1_PWM17=P1.1 0 P2.9 CT16B1_PWM17=P2.9 1 PWM18 CT16B1_PWM18 assigned pin 18 19 read-write P1.2 CT16B1_PWM18=P1.2 0 P2.10 CT16B1_PWM18=P2.10 1 PWM19 CT16B1_PWM19 assigned pin 19 20 read-write P1.3 CT16B1_PWM19=P1.3 0 P2.11 CT16B1_PWM19=P2.11 1 PWM20 CT16B1_PWM20 assigned pin 20 21 read-write P1.4 CT16B1_PWM20=P1.4 0 P2.12 CT16B1_PWM20=P2.12 1 PWM21 CT16B1_PWM21 assigned pin 21 22 read-write P1.5 CT16B1_PWM21=P1.5 0 P2.13 CT16B1_PWM21=P2.13 1 PWM22 CT16B1_PWM22 assigned pin 22 23 read-write P1.6 CT16B1_PWM22=P1.6 0 P2.14 CT16B1_PWM22=P2.14 1 PWM23 CT16B1_PWM23 assigned pin 23 24 read-write P1.7 CT16B1_PWM23=P1.7 0 P2.15 CT16B1_PWM23=P2.15 1 SN_PMU Power Management Unit PMU 0x0 0x0 0x2000 registers n NDT 0 CTRL Offset:0x40 PMU Control Register 0x40 32 read-write n 0x0 0x0 MODE Low Power mode selection 0 3 read-write Disable Disable 0 Deep-sleep mode WFI instruction will make MCU enter Deep-sleep mode 2 Sleep mode WFI instruction will make MCU enter Sleep mode 4 SN_SPI0 SPI0 SPI 0x0 0x0 0x2000 registers n SPI0 6 CLKDIV Offset:0x08 SPI0 Clock Divider Register 0x8 32 read-write n 0x0 0x0 DIV SPI0 SCK 0 8 read-write CTRL0 Offset:0x00 SPI0 Control Register 0 0x0 32 read-write n 0x0 0x0 DL Data length = DL[3:0]+1 8 12 read-write 1010 Data length=11 10 1011 Data length=12 11 1100 Data length=13 12 1101 Data length=14 13 1110 Data length=15 14 1111 Data length=16 15 0010 Data length=3 2 0011 Data length=4 3 0100 Data length=5 4 0101 Data length=6 5 0110 Data length=7 6 0111 Data length=8 7 1000 Data length=9 8 1001 Data length=10 9 FORMAT Interface format 4 5 read-write SPI SPI 0 FRESET SPI FSM and FIFO Reset 6 8 write-only 00 No effect 0 11 Reset FSM and FIFO 3 LOOPBACK Loopback mode enable 1 2 read-write Disable Disable loopback mode 0 Enable Enable loopback mode 1 MS Master/Slave selection 3 4 read-write Master Act as Master 0 Slave Act as Slave 1 RXFIFOTH RX FIFO Threshold level 15 18 read-write 0 RX FIFO threshold level is 0 0 1 RX FIFO threshold level is 1 1 2 RX FIFO threshold level is 2 2 3 RX FIFO threshold level is 3 3 4 RX FIFO threshold level is 4 4 5 RX FIFO threshold level is 5 5 6 RX FIFO threshold level is 6 6 7 RX FIFO threshold level is 7 7 SDODIS Slave data out disable 2 3 read-write Enable Enable slave data out 0 Disble Diable slave data out (MISO=0) 1 SELDIS Auto-SEL disable bit 18 19 read-write Enable Enable Auto-SEL flow control 0 Disable Disable Auto-SEL flow control 1 SPIEN SPI enable 0 1 read-write Disable Disable SPI 0 Enable Enable SPI 1 TXFIFOTH TX FIFO Threshold level 12 15 read-write 0 TX FIFO threshold level is 0 0 1 TX FIFO threshold level is 1 1 2 TX FIFO threshold level is 2 2 3 TX FIFO threshold level is 3 3 4 TX FIFO threshold level is 4 4 5 TX FIFO threshold level is 5 5 6 TX FIFO threshold level is 6 6 7 TX FIFO threshold level is 7 7 CTRL1 Offset:0x04 SPI0 Control Register 1 0x4 32 read-write n 0x0 0x0 CPHA Clock phase of edge sampling 2 3 read-write CPHA0 The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data 0 CPHA1 SCK 1st edge is for data transition, and receive/transmit data at 2nd edge 1 CPOL Clock priority selection 1 2 read-write Low SCK idles at low level 0 High SCK idles at high level 1 MLSB MSB/LSB seletion 0 1 read-write MSB MSB transmit first 0 LSB LSB transmit first 1 DATA Offset:0x1C SPI0 Data Register 0x1C 32 read-write n 0x0 0x0 Data Data 0 16 read-write DFDLY Offset:0x20 SPI0 Data Fetch Register 0x20 32 read-write n 0x0 0x0 DFETCH_EN SPI0 data fetch control bit 0 1 read-write Disable Disable 0 Enable Enable when SCKn frequency is higher than 6MHz 1 IC Offset:0x18 SPI0 Interrupt Clear Register 0x18 32 write-only n 0x0 0x0 RXFIFOTHIC RX Interrupt flag Clear 2 3 write-only No effect No effect 0 Clear Clear RXFIFOTH flag 1 RXOVFIC RX FIFO overflow flag clear 0 1 write-only No effect No effect 0 Clear Clear RXOVF flag 1 RXTOIC RX time-out interrupt flag clear 1 2 write-only No effect No effect 0 Clear Clear RXTO flag 1 TXFIFOTHIC TX Interrupt flag Clear 3 4 write-only No effect No effect 0 Clear Clear TXFIFOTH flag 1 IE Offset:0x10 SPI0 Interrupt Enable Register 0x10 32 read-write n 0x0 0x0 RXFIFOTHIE RX FIFO threshold interrupt enable 2 3 read-write Disable Disable RX FIFO threshold interrupt 0 Enable Enable RX FIFO threshold interrupt 1 RXOVFIE RX FIFO overflow interrupt enable 0 1 read-write Disable Disable RX FIFO overflow interrupt 0 Enable Enable RX FIFO overflow interrupt 1 RXTOIE RX time-out interrupt enable 1 2 read-write Disable Disable RX time-out interrupt 0 Enable Enable RX time-out interrupt 1 TXFIFOTHIE TX FIFO threshold interrupt enable 3 4 read-write Disable Disable TX FIFO threshold interrupt 0 Enable Enable TX FIFO threshold interrupt 1 RIS Offset:0x14 SPI0 Raw Interrupt Status Register 0x14 32 read-only n 0x0 0x0 RXFIFOTHIF RX FIFO threshold interrupt flag 2 3 read-only No RXFIFOTH interrupt No RXFIFOTH interrupt 0 Met RXFIFOTH interrupt requirements RX FIFO threshold is triggered when RXFIFOTHIE=1 1 RXOVFIF RX FIFO overflow interrupt flag 0 1 read-only No RXOVF interrupt No RXOVF interrupt 0 Met RXOVF interrupt requirements RXOVF interrupt is triggered when RXOVFIE=1 1 RXTOIF RX time-out interrupt flag 1 2 read-only No RXTO interrupt No RXTO interrupt 0 Met RXTO interrupt requirements RXTO interrupt is triggered when RXTOIE=1 1 TXFIFOTHIF TX FIFO threshold interrupt flag 3 4 read-only No TXFIFOTH interrupt No TXFIFOTH interrupt 0 Met TXFIFOTH interrupt requirements TX FIFO threshold is triggered when TXFIFOTHIE=1 1 STAT Offset:0x0C SPI0 Status Register 0xC 32 read-only n 0x0 0x0 BUSY Busy flag 4 5 read-only Idle SSPn is idle 0 Busy SSPn is transfering 1 RXFIFOTHF RX FIFO threshold flag 6 7 read-only 0 Data count in RX FIFO is less equal than RXFIFOTH 0 1 Data count in RX FIFO is larger than RXFIFOTH 1 RX_EMPTY RX FIFO empty flag 2 3 read-only 0 RX FIFO is not empty 0 1 RX FIFO is empty 1 RX_FULL RX FIFO full flag 3 4 read-only 0 RX FIFO is not full 0 1 RX FIFO is full 1 TXFIFOTHF TX FIFO threshold flag 5 6 read-only 0 Data count in TX FIFO is larger than TXFIFOTH 0 1 Data count in TX FIFO is less equal than TXFIFOTH 1 TX_EMPTY TX FIFO empty flag 0 1 read-only 0 TX FIFO is not empty 0 1 TX FIFO is empty 1 TX_FULL TX FIFO full flag 1 2 read-only 0 TX FIFO is not full 0 1 TX FIFO is full 1 SN_SYS0 System Control Registers SYSTEM 0x0 0x0 0x2000 registers n LVD 26 AHBCP Offset:0x10 AHB Clock Prescale Register 0x10 32 read-write n 0x0 0x0 AHBPRE AHB clock source prescaler 0 3 read-write 000 FAHB=FSYSCLK/1 0 001 FAHB=FSYSCLK/2 1 010 FAHB=FSYSCLK/4 2 011 FAHB=FSYSCLK/8 3 100 FAHB=FSYSCLK/16 4 101 FAHB=FSYSCLK/32 5 110 FAHB=FSYSCLK/64 6 111 FAHB=FSYSCLK/128 7 ANBCTRL Offset:0x00 Analog Block Control Register 0x0 32 read-write n 0x0 0x0 IHRCEN IHRC enable 0 1 read-write Disable Disable IHRC 0 Enable Enable IHRC 1 ANTIEFT Offset:0x30 Anti-EFT Ability Control Register 0x30 32 read-write n 0x0 0x0 AEFT Anti-EFT ability 0 3 read-write 0 No 0 2 Low 2 3 Medium 3 4 Strong 4 CLKCFG Offset:0x0C System Clock Configuration Register 0xC 32 read-write n 0x0 0x0 SYSCLKSEL System clock source selection 0 1 read-write IHRC IHRC is system clock 0 ILRC ILRC is system clock 1 SYSCLKST System clock switch status 4 5 read-only IHRC IHRC is used as system clock 0 ILRC ILRC is used as system clock 1 CSST Offset:0x08 Clock Source Status Register 0x8 32 read-only n 0x0 0x0 IHRCRDY IHRC ready flag 0 1 read-only 0 IHRC is Not Ready 0 1 IHRC is Ready 1 EXRSTCTRL Offset:0x1C External Reset Pin Control Register 0x1C 32 read-write n 0x0 0x0 RESETDIS External reset pin disable 0 1 read-write Enable P3.7 acts as nRESET pin 0 Disable P3.7 acts as GPIO pin 1 IVTM Offset:0x24 Interrupt Vector Table Mapping register 0x24 32 read-write n 0x0 0x0 IVTM Interrupt table mapping selection 0 2 read-write 00 Map to Boot ROM 0 01 Map to User ROM 1 10 Map to SRAM 2 IVTMKEY IVTM register key 16 32 write-only LVDCTRL Offset:0x18 LVD Control Register 0x18 32 read-write n 0x0 0x0 LVDEN LVD enable 15 16 read-write Diable Disable LVD 0 Enable Enable LVD 1 LVDINTLVL LVD interrupt level 4 7 read-write 2.40V LVD interrupt threshold is 2.40V 2 2.70V LVD interrupt threshold is 2.70V 3 3.00V LVD interrupt threshold is 3.00V 4 3.60V LVD interrupt threshold is 3.60V 5 LVDRSTEN LVD Reset enable 14 15 read-write Diable Disable LVD reset 0 Enable Enable LVD reset 1 LVDRSTLVL LVD reset level 0 3 read-write 2.40V LVD reset threshold is 2.40V 2 2.70V LVD reset threshold is 2.70V 3 3.00V LVD reset threshold is 3.00V 4 3.60V LVD reset threshold is 3.60V 5 NDTCTRL Offset:0x28 Noise Detect Control Register 0x28 32 read-write n 0x0 0x0 NDT5V_IE NDT for VDD 5V interrupt enable bit 1 2 read-write Disable Disable 0 Enable Enable 1 NDTSTS Offset:0x2C Noise Detect Status Register 0x2C 32 read-write n 0x0 0x0 NDT5V_DET Power noise status of NDT5V 1 2 read-write No No power noise is detected 0 Detected Power noise is detected by NDT5V IP 1 RSTST Offset:0x14 System Reset Status Register 0x14 32 read-write n 0x0 0x0 EXTRSTF External reset flag 3 4 read-write 0 No Extenral reset occurred 0 1 External reset occurred 1 LVDRSTF LVD reset flag 2 3 read-write 0 No LVD reset occurred 0 1 LVD reset occurred 1 PORRSTF POR reset flag 4 5 read-write 0 No POR occurred 0 1 POR occurred 1 SWRSTF Software reset flag 0 1 read-write 0 No SW reset occurred 0 1 SW reset occurred 1 WDTRSTF WDT reset flag 1 2 read-write 0 No WDT reset occurred 0 1 WDT reset occurred 1 SWDCTRL Offset:0x20 SWD Pin Control Register 0x20 32 read-write n 0x0 0x0 SWDDIS SWD pin disable 0 1 read-write Enable Enable SWD pins 0 Disable Disable SWD pins 1 SN_SYS1 System Control Registers SYSTEM 0x0 0x0 0x2000 registers n AHBCLKEN Offset:0x00 AHB Clock Enable Register 0x0 32 read-write n 0x0 0x0 ADCCLKEN Enable AHB clock for ADC 11 12 read-write Disable Disable 0 Enable Enable 1 CLKOUTSEL Clock output source selection 28 31 read-write 000 Disable 0 001 ILRC 1 100 HCLK 4 101 IHRC 5 CT16B0CLKEN Enable AHB clock for CT16B0 6 7 read-write Disable Disable 0 Enable Enable 1 CT16B1CLKEN Enable AHB clock for CT16B1 7 8 read-write Disable Disable 0 Enable Enable 1 I2C0CLKEN Enable AHB clock for I2C0 21 22 read-write Disable Disable 0 Enable Enable 1 P0CLKEN Enable AHB clock for P0 0 1 read-write Disable Disable 0 Enable Enable 1 P1CLKEN Enable AHB clock for P1 1 2 read-write Disable Disable 0 Enable Enable 1 P2CLKEN Enable AHB clock for P2 2 3 read-write Disable Disable 0 Enable Enable 1 P3CLKEN Enable AHB clock for P3 3 4 read-write Disable Disable 0 Enable Enable 1 SPI0CLKEN Enable AHB clock for SPI0 12 13 read-write Disable Disable 0 Enable Enable 1 UART0CLKEN Enable AHB clock for UART0 16 17 read-write Disable Disable 0 Enable Enable 1 UART1CLKEN Enable AHB clock for UART1 17 18 read-write Disable Disable 0 Enable Enable 1 UART2CLKEN Enable AHB clock for UART2 18 19 read-write Disable Disable 0 Enable Enable 1 USBCLKEN Enable AHB clock for USB 4 5 read-write Disable Disable 0 Enable Enable 1 WDTCLKEN Enable AHB clock for WDT 24 25 read-write Disable Disable 0 Enable Enable 1 APBCP1 Offset:0x08 APB Clock Prescale Register 1 0x8 32 read-write n 0x0 0x0 CLKOUTPRE CLKOUT APB clock source prescaler 28 31 read-write 000 FCLKOUT/1 0 001 FCLKOUT/2 1 010 FCLKOUT/4 2 011 FCLKOUT/8 3 100 FCLKOUT/16 4 101 FCLKOUT/32 5 110 FCLKOUT/64 6 111 FCLKOUT/128 7 WDTPRE WDT APB clock source prescaler 20 23 read-write 000 WDT_PCLK = WDT clock source/1 0 001 WDT_PCLK = WDT clock source/2 1 010 WDT_PCLK = WDT clock source/4 2 011 WDT_PCLK = WDT clock source/8 3 100 WDT_PCLK = WDT clock source/16 4 101 WDT_PCLK = WDT clock source/32 5 SN_UART0 UART0 UART 0x0 0x0 0x2000 registers n UART0 12 ABCTRL Offset:0x20 UARTn Auto-baud Control Register 0x20 32 read-write n 0x0 0x0 ABEOIFC Clear ABEOIF flag 8 9 write-only No effect No effect 0 Clear Clear ABEOIF bit 1 ABTOIFC Clear ABTOIF flag 9 10 write-only No effect No effect 0 Clear Clear ABTOIF bit 1 AUTORESTART Restart mode selection 2 3 read-write No restart No restart 0 Restart Auto restart in case of timeout 1 MODE Auto-baud mode selection 1 2 read-write Mode 0 Auto-baud mode 0 0 Mode 1 Auto-baud mode 1 1 START Auto-baud run bit 0 1 read-write Stop Auto-baud is not running 0 Start Auto-baud ids running 1 CTRL Offset:0x30 UARTn Control Register 0x30 32 read-write n 0x0 0x0 MODE UART mode 1 4 read-write 0 UART mode 0 RXEN RX enable 6 7 read-write Disable Disable RX 0 Enable Enable RX 1 TXEN TX enable 7 8 read-write Disable Disable TX 0 Enable Enable TX 1 UARTEN USART enable 0 1 read-write Disable Disable UART 0 Enable Enable UART 1 DLL Offset:0x00 UARTn Divisor Latch LSB Register 0x0 32 read-write n 0x0 0x0 DLL DLL and DLM register determines the baud rate of UARTn 0 8 read-write DLM Offset:0x04 UARTn Divisor Latch MSB Register 0x4 32 read-write n 0x0 0x0 DLM DLL and DLM register determines the baud rate of USARTn 0 8 read-write FD Offset:0x28 UARTn Fractional Divider Register 0x28 32 read-write n 0x0 0x0 DIVADDVAL Baud rate generation prescaler divisor value 0 4 read-write MULVAL Baud rate generation prescaler multiplier value 4 8 read-write 0000 Baud rate prescaler multiplier value is 1 0 0001 Baud rate prescaler multiplier value is 2 1 1010 Baud rate prescaler multiplier value is 11 10 1011 Baud rate prescaler multiplier value is 12 11 1100 Baud rate prescaler multiplier value is 13 12 1101 Baud rate prescaler multiplier value is 14 13 1110 Baud rate prescaler multiplier value is 15 14 1111 Baud rate prescaler multiplier value is 16 15 0010 Baud rate prescaler multiplier value is 3 2 0011 Baud rate prescaler multiplier value is 4 3 0100 Baud rate prescaler multiplier value is 5 4 0101 Baud rate prescaler multiplier value is 6 5 0110 Baud rate prescaler multiplier value is 7 6 0111 Baud rate prescaler multiplier value is 8 7 1000 Baud rate prescaler multiplier value is 9 8 1001 Baud rate prescaler multiplier value is 10 9 OVER8 Oversampling value 8 9 read-write 16 Oversampling by 16 0 8 Oversampling by 8 1 FIFOCTRL Offset:0x08 UARTn FIFO Control Register 0x8 32 write-only n 0x0 0x0 FIFOEN FIFO enable 0 1 write-only No effect No effect 0 Enable Enable FIFO 1 RXTL RX trigger level 6 8 write-only Trigger level 0 1 character 0 HDEN Offset:0x34 UARTn Control Register 0x34 32 read-write n 0x0 0x0 HDEN Half-duplex mode enable 0 1 read-write Disable Disable half-duplex mode 0 Enable Enable half-duplex mode 1 IE Offset:0x04 UARTn Interrupt Enable Register 0x4 32 read-write n 0x0 0x0 ABEOIE ABE0 interrupt enable 8 9 read-write Disable Disable ABEO interrupt 0 Enable Enable ABEO interrupt 1 ABTOIE ABT0 interrupt enable 9 10 read-write Disable Disable ABTO interrupt 0 Enable Enable ABTO interrupt 1 RDAIE RDA interrupt enable 0 1 read-write Disable Disable RDA interrupt 0 Enable Enable RDA interrupt 1 RLSIE RLS interrupt enable 2 3 read-write Disable Disable RLS interrupt 0 Enable Enable RLS interrupt 1 TEMTIE TEMT interrupt enable 4 5 read-write Disable Disable TEMT interrupt 0 Enable Enable TEMT interrupt 1 THREIE THRE interrupt enable 1 2 read-write Disable Disable THRE interrupt 0 Enable Enable THRE interrupt 1 II Offset:0x08 UARTn Interrupt Identification Register 0x8 32 read-only n 0x0 0x0 ABEOIF ABEO interrupt flag 8 9 read-only Not end Auto-baud has not finished 0 End Auto-baud has finished and interrupt is enabled 1 ABTOIF ABTO interrupt flag 9 10 read-only Not Time-out Auto-baud has not timed out 0 Time-out Auto-baud has timed out and interrupt is enabled 1 FIFOEN Equal to FIFOEN bits in USARTn_FIFOCTRL register 6 8 read-only INTID Interrupt ID of RX FIFO 1 4 read-only 3a THRE interrupt 1 2a RDA (Receive Data Available) 2 1 RLS (Receive Line Status) 3 3b TEMT interrupt 7 INTSTATUS Interrupt status 0 1 read-only Pending As least 1 interrupt is pending 0 No interrupt No interrupt 1 LC Offset:0x0C UARTn Line Control Register 0xC 32 read-write n 0x0 0x0 BC Break control 6 7 read-write Disable Disable break transmission 0 Enable Enable break transmission 1 DLAB Divisor Latch access 7 8 read-write Disable Disable access to Divisor Latch 0 Enable Enable access to Divisor Latch 1 PE Parity enable 3 4 read-write Disable Disable parity generation and checking 0 Enable Enable parity generation and checking 1 PS Parity selection 4 6 read-write 0 Odd parity 0 1 Even parity 1 2 Forced 1 sticky parity 2 3 Forced 0 sticky parity 3 SBS Stop bit selection 2 3 read-write 1 stop bit 1 stop bit 0 2 stop bit 2 stop bit (1.5 stop bit if WLS=0) 1 WLS Word length selection 0 2 read-write 5-bit 5-bit character 0 6-bit 6-bit character 1 7-bit 7-bit character 2 8-bit 8-bit character 3 LS Offset:0x14 UARTn Line Status Register 0x14 32 read-only n 0x0 0x0 BI Break interrupt flag 4 5 read-only No break interrupt No break interrupt 0 Break interrupt Break interrupt status is active 1 FE Framing error flag 3 4 read-only No framing error No framing error 0 Framing error Framing error status is active 1 OE Overrun error flag 1 2 read-only No overrun error No overrun error 0 Overrun error Overrun error status is active 1 PE Parity error flag 2 3 read-only No parity error No parity error 0 Parity error Parity error status is active 1 RDR Receiver data ready flag 0 1 read-only Not ready UARTn_RB FIFO is empty 0 Ready UARTn_RB FIFO contains valid data 1 RXFE Receiver FIFO error flag 7 8 read-only No RX FIFO error UARTn_RB contains no UART RX errors 0 RX FIFO error UARTn_RB contains at least 1 UART RX error 1 TEMT Transmitter empty flag 6 7 read-only Not empty THR and/or TSR contains valid data 0 Empty THR and TSR are both empty 1 THRE THR empty flag 5 6 read-only Not empty THR contains valid data 0 Empty THR (TX FIFO) is empty 1 RB Offset:0x00 UARTn Receiver Buffer Register 0x0 32 read-only n 0x0 0x0 RB The received byte in UART RX FIFO 0 8 read-only SP Offset:0x1C UARTn Scratch Pad Register 0x1C 32 read-write n 0x0 0x0 PAD Pad informaton 0 8 read-write TH Offset:0x00 UARTn Transmit Holding Register 0x0 32 write-only n 0x0 0x0 TH The byte to be transmitted in UART TX FIFO when transmitter is available 0 8 write-only SN_UART1 UART1 UART 0x0 0x0 0x2000 registers n UART1 13 ABCTRL Offset:0x20 UARTn Auto-baud Control Register 0x20 32 read-write n 0x0 0x0 ABEOIFC Clear ABEOIF flag 8 9 write-only No effect No effect 0 Clear Clear ABEOIF bit 1 ABTOIFC Clear ABTOIF flag 9 10 write-only No effect No effect 0 Clear Clear ABTOIF bit 1 AUTORESTART Restart mode selection 2 3 read-write No restart No restart 0 Restart Auto restart in case of timeout 1 MODE Auto-baud mode selection 1 2 read-write Mode 0 Auto-baud mode 0 0 Mode 1 Auto-baud mode 1 1 START Auto-baud run bit 0 1 read-write Stop Auto-baud is not running 0 Start Auto-baud ids running 1 CTRL Offset:0x30 UARTn Control Register 0x30 32 read-write n 0x0 0x0 MODE UART mode 1 4 read-write 0 UART mode 0 RXEN RX enable 6 7 read-write Disable Disable RX 0 Enable Enable RX 1 TXEN TX enable 7 8 read-write Disable Disable TX 0 Enable Enable TX 1 UARTEN USART enable 0 1 read-write Disable Disable UART 0 Enable Enable UART 1 DLL Offset:0x00 UARTn Divisor Latch LSB Register 0x0 32 read-write n 0x0 0x0 DLL DLL and DLM register determines the baud rate of UARTn 0 8 read-write DLM Offset:0x04 UARTn Divisor Latch MSB Register 0x4 32 read-write n 0x0 0x0 DLM DLL and DLM register determines the baud rate of USARTn 0 8 read-write FD Offset:0x28 UARTn Fractional Divider Register 0x28 32 read-write n 0x0 0x0 DIVADDVAL Baud rate generation prescaler divisor value 0 4 read-write MULVAL Baud rate generation prescaler multiplier value 4 8 read-write 0000 Baud rate prescaler multiplier value is 1 0 0001 Baud rate prescaler multiplier value is 2 1 1010 Baud rate prescaler multiplier value is 11 10 1011 Baud rate prescaler multiplier value is 12 11 1100 Baud rate prescaler multiplier value is 13 12 1101 Baud rate prescaler multiplier value is 14 13 1110 Baud rate prescaler multiplier value is 15 14 1111 Baud rate prescaler multiplier value is 16 15 0010 Baud rate prescaler multiplier value is 3 2 0011 Baud rate prescaler multiplier value is 4 3 0100 Baud rate prescaler multiplier value is 5 4 0101 Baud rate prescaler multiplier value is 6 5 0110 Baud rate prescaler multiplier value is 7 6 0111 Baud rate prescaler multiplier value is 8 7 1000 Baud rate prescaler multiplier value is 9 8 1001 Baud rate prescaler multiplier value is 10 9 OVER8 Oversampling value 8 9 read-write 16 Oversampling by 16 0 8 Oversampling by 8 1 FIFOCTRL Offset:0x08 UARTn FIFO Control Register 0x8 32 write-only n 0x0 0x0 FIFOEN FIFO enable 0 1 write-only No effect No effect 0 Enable Enable FIFO 1 RXTL RX trigger level 6 8 write-only Trigger level 0 1 character 0 HDEN Offset:0x34 UARTn Control Register 0x34 32 read-write n 0x0 0x0 HDEN Half-duplex mode enable 0 1 read-write Disable Disable half-duplex mode 0 Enable Enable half-duplex mode 1 IE Offset:0x04 UARTn Interrupt Enable Register 0x4 32 read-write n 0x0 0x0 ABEOIE ABE0 interrupt enable 8 9 read-write Disable Disable ABEO interrupt 0 Enable Enable ABEO interrupt 1 ABTOIE ABT0 interrupt enable 9 10 read-write Disable Disable ABTO interrupt 0 Enable Enable ABTO interrupt 1 RDAIE RDA interrupt enable 0 1 read-write Disable Disable RDA interrupt 0 Enable Enable RDA interrupt 1 RLSIE RLS interrupt enable 2 3 read-write Disable Disable RLS interrupt 0 Enable Enable RLS interrupt 1 TEMTIE TEMT interrupt enable 4 5 read-write Disable Disable TEMT interrupt 0 Enable Enable TEMT interrupt 1 THREIE THRE interrupt enable 1 2 read-write Disable Disable THRE interrupt 0 Enable Enable THRE interrupt 1 II Offset:0x08 UARTn Interrupt Identification Register 0x8 32 read-only n 0x0 0x0 ABEOIF ABEO interrupt flag 8 9 read-only Not end Auto-baud has not finished 0 End Auto-baud has finished and interrupt is enabled 1 ABTOIF ABTO interrupt flag 9 10 read-only Not Time-out Auto-baud has not timed out 0 Time-out Auto-baud has timed out and interrupt is enabled 1 FIFOEN Equal to FIFOEN bits in USARTn_FIFOCTRL register 6 8 read-only INTID Interrupt ID of RX FIFO 1 4 read-only 3a THRE interrupt 1 2a RDA (Receive Data Available) 2 1 RLS (Receive Line Status) 3 3b TEMT interrupt 7 INTSTATUS Interrupt status 0 1 read-only Pending As least 1 interrupt is pending 0 No interrupt No interrupt 1 LC Offset:0x0C UARTn Line Control Register 0xC 32 read-write n 0x0 0x0 BC Break control 6 7 read-write Disable Disable break transmission 0 Enable Enable break transmission 1 DLAB Divisor Latch access 7 8 read-write Disable Disable access to Divisor Latch 0 Enable Enable access to Divisor Latch 1 PE Parity enable 3 4 read-write Disable Disable parity generation and checking 0 Enable Enable parity generation and checking 1 PS Parity selection 4 6 read-write 0 Odd parity 0 1 Even parity 1 2 Forced 1 sticky parity 2 3 Forced 0 sticky parity 3 SBS Stop bit selection 2 3 read-write 1 stop bit 1 stop bit 0 2 stop bit 2 stop bit (1.5 stop bit if WLS=0) 1 WLS Word length selection 0 2 read-write 5-bit 5-bit character 0 6-bit 6-bit character 1 7-bit 7-bit character 2 8-bit 8-bit character 3 LS Offset:0x14 UARTn Line Status Register 0x14 32 read-only n 0x0 0x0 BI Break interrupt flag 4 5 read-only No break interrupt No break interrupt 0 Break interrupt Break interrupt status is active 1 FE Framing error flag 3 4 read-only No framing error No framing error 0 Framing error Framing error status is active 1 OE Overrun error flag 1 2 read-only No overrun error No overrun error 0 Overrun error Overrun error status is active 1 PE Parity error flag 2 3 read-only No parity error No parity error 0 Parity error Parity error status is active 1 RDR Receiver data ready flag 0 1 read-only Not ready UARTn_RB FIFO is empty 0 Ready UARTn_RB FIFO contains valid data 1 RXFE Receiver FIFO error flag 7 8 read-only No RX FIFO error UARTn_RB contains no UART RX errors 0 RX FIFO error UARTn_RB contains at least 1 UART RX error 1 TEMT Transmitter empty flag 6 7 read-only Not empty THR and/or TSR contains valid data 0 Empty THR and TSR are both empty 1 THRE THR empty flag 5 6 read-only Not empty THR contains valid data 0 Empty THR (TX FIFO) is empty 1 RB Offset:0x00 UARTn Receiver Buffer Register 0x0 32 read-only n 0x0 0x0 RB The received byte in UART RX FIFO 0 8 read-only SP Offset:0x1C UARTn Scratch Pad Register 0x1C 32 read-write n 0x0 0x0 PAD Pad informaton 0 8 read-write TH Offset:0x00 UARTn Transmit Holding Register 0x0 32 write-only n 0x0 0x0 TH The byte to be transmitted in UART TX FIFO when transmitter is available 0 8 write-only SN_UART2 UART2 UART 0x0 0x0 0x2000 registers n UART2 14 ABCTRL Offset:0x20 UARTn Auto-baud Control Register 0x20 32 read-write n 0x0 0x0 ABEOIFC Clear ABEOIF flag 8 9 write-only No effect No effect 0 Clear Clear ABEOIF bit 1 ABTOIFC Clear ABTOIF flag 9 10 write-only No effect No effect 0 Clear Clear ABTOIF bit 1 AUTORESTART Restart mode selection 2 3 read-write No restart No restart 0 Restart Auto restart in case of timeout 1 MODE Auto-baud mode selection 1 2 read-write Mode 0 Auto-baud mode 0 0 Mode 1 Auto-baud mode 1 1 START Auto-baud run bit 0 1 read-write Stop Auto-baud is not running 0 Start Auto-baud ids running 1 CTRL Offset:0x30 UARTn Control Register 0x30 32 read-write n 0x0 0x0 MODE UART mode 1 4 read-write 0 UART mode 0 RXEN RX enable 6 7 read-write Disable Disable RX 0 Enable Enable RX 1 TXEN TX enable 7 8 read-write Disable Disable TX 0 Enable Enable TX 1 UARTEN USART enable 0 1 read-write Disable Disable UART 0 Enable Enable UART 1 DLL Offset:0x00 UARTn Divisor Latch LSB Register 0x0 32 read-write n 0x0 0x0 DLL DLL and DLM register determines the baud rate of UARTn 0 8 read-write DLM Offset:0x04 UARTn Divisor Latch MSB Register 0x4 32 read-write n 0x0 0x0 DLM DLL and DLM register determines the baud rate of USARTn 0 8 read-write FD Offset:0x28 UARTn Fractional Divider Register 0x28 32 read-write n 0x0 0x0 DIVADDVAL Baud rate generation prescaler divisor value 0 4 read-write MULVAL Baud rate generation prescaler multiplier value 4 8 read-write 0000 Baud rate prescaler multiplier value is 1 0 0001 Baud rate prescaler multiplier value is 2 1 1010 Baud rate prescaler multiplier value is 11 10 1011 Baud rate prescaler multiplier value is 12 11 1100 Baud rate prescaler multiplier value is 13 12 1101 Baud rate prescaler multiplier value is 14 13 1110 Baud rate prescaler multiplier value is 15 14 1111 Baud rate prescaler multiplier value is 16 15 0010 Baud rate prescaler multiplier value is 3 2 0011 Baud rate prescaler multiplier value is 4 3 0100 Baud rate prescaler multiplier value is 5 4 0101 Baud rate prescaler multiplier value is 6 5 0110 Baud rate prescaler multiplier value is 7 6 0111 Baud rate prescaler multiplier value is 8 7 1000 Baud rate prescaler multiplier value is 9 8 1001 Baud rate prescaler multiplier value is 10 9 OVER8 Oversampling value 8 9 read-write 16 Oversampling by 16 0 8 Oversampling by 8 1 FIFOCTRL Offset:0x08 UARTn FIFO Control Register 0x8 32 write-only n 0x0 0x0 FIFOEN FIFO enable 0 1 write-only No effect No effect 0 Enable Enable FIFO 1 RXTL RX trigger level 6 8 write-only Trigger level 0 1 character 0 HDEN Offset:0x34 UARTn Control Register 0x34 32 read-write n 0x0 0x0 HDEN Half-duplex mode enable 0 1 read-write Disable Disable half-duplex mode 0 Enable Enable half-duplex mode 1 IE Offset:0x04 UARTn Interrupt Enable Register 0x4 32 read-write n 0x0 0x0 ABEOIE ABE0 interrupt enable 8 9 read-write Disable Disable ABEO interrupt 0 Enable Enable ABEO interrupt 1 ABTOIE ABT0 interrupt enable 9 10 read-write Disable Disable ABTO interrupt 0 Enable Enable ABTO interrupt 1 RDAIE RDA interrupt enable 0 1 read-write Disable Disable RDA interrupt 0 Enable Enable RDA interrupt 1 RLSIE RLS interrupt enable 2 3 read-write Disable Disable RLS interrupt 0 Enable Enable RLS interrupt 1 TEMTIE TEMT interrupt enable 4 5 read-write Disable Disable TEMT interrupt 0 Enable Enable TEMT interrupt 1 THREIE THRE interrupt enable 1 2 read-write Disable Disable THRE interrupt 0 Enable Enable THRE interrupt 1 II Offset:0x08 UARTn Interrupt Identification Register 0x8 32 read-only n 0x0 0x0 ABEOIF ABEO interrupt flag 8 9 read-only Not end Auto-baud has not finished 0 End Auto-baud has finished and interrupt is enabled 1 ABTOIF ABTO interrupt flag 9 10 read-only Not Time-out Auto-baud has not timed out 0 Time-out Auto-baud has timed out and interrupt is enabled 1 FIFOEN Equal to FIFOEN bits in USARTn_FIFOCTRL register 6 8 read-only INTID Interrupt ID of RX FIFO 1 4 read-only 3a THRE interrupt 1 2a RDA (Receive Data Available) 2 1 RLS (Receive Line Status) 3 3b TEMT interrupt 7 INTSTATUS Interrupt status 0 1 read-only Pending As least 1 interrupt is pending 0 No interrupt No interrupt 1 LC Offset:0x0C UARTn Line Control Register 0xC 32 read-write n 0x0 0x0 BC Break control 6 7 read-write Disable Disable break transmission 0 Enable Enable break transmission 1 DLAB Divisor Latch access 7 8 read-write Disable Disable access to Divisor Latch 0 Enable Enable access to Divisor Latch 1 PE Parity enable 3 4 read-write Disable Disable parity generation and checking 0 Enable Enable parity generation and checking 1 PS Parity selection 4 6 read-write 0 Odd parity 0 1 Even parity 1 2 Forced 1 sticky parity 2 3 Forced 0 sticky parity 3 SBS Stop bit selection 2 3 read-write 1 stop bit 1 stop bit 0 2 stop bit 2 stop bit (1.5 stop bit if WLS=0) 1 WLS Word length selection 0 2 read-write 5-bit 5-bit character 0 6-bit 6-bit character 1 7-bit 7-bit character 2 8-bit 8-bit character 3 LS Offset:0x14 UARTn Line Status Register 0x14 32 read-only n 0x0 0x0 BI Break interrupt flag 4 5 read-only No break interrupt No break interrupt 0 Break interrupt Break interrupt status is active 1 FE Framing error flag 3 4 read-only No framing error No framing error 0 Framing error Framing error status is active 1 OE Overrun error flag 1 2 read-only No overrun error No overrun error 0 Overrun error Overrun error status is active 1 PE Parity error flag 2 3 read-only No parity error No parity error 0 Parity error Parity error status is active 1 RDR Receiver data ready flag 0 1 read-only Not ready UARTn_RB FIFO is empty 0 Ready UARTn_RB FIFO contains valid data 1 RXFE Receiver FIFO error flag 7 8 read-only No RX FIFO error UARTn_RB contains no UART RX errors 0 RX FIFO error UARTn_RB contains at least 1 UART RX error 1 TEMT Transmitter empty flag 6 7 read-only Not empty THR and/or TSR contains valid data 0 Empty THR and TSR are both empty 1 THRE THR empty flag 5 6 read-only Not empty THR contains valid data 0 Empty THR (TX FIFO) is empty 1 RB Offset:0x00 UARTn Receiver Buffer Register 0x0 32 read-only n 0x0 0x0 RB The received byte in UART RX FIFO 0 8 read-only SP Offset:0x1C UARTn Scratch Pad Register 0x1C 32 read-write n 0x0 0x0 PAD Pad informaton 0 8 read-write TH Offset:0x00 UARTn Transmit Holding Register 0x0 32 write-only n 0x0 0x0 TH The byte to be transmitted in UART TX FIFO when transmitter is available 0 8 write-only SN_UC UC Registers UC 0x0 0x0 0x2000 registers n H4BYTE Offset:0x04 UC High 4 Byte Register 0x4 32 read-only n 0x0 0x0 L4BYTE Offset:0x00 UC Low 4 Byte Register 0x0 32 read-only n 0x0 0x0 SN_USB Universal Serial Bus Full Speed Device Interface (USB) USB 0x0 0x0 0x2000 registers n USB 1 ADDR Offset:0x0C USB Device Address Register 0xC 32 read-write n 0x0 0x0 UADDR USB device's address 0 7 read-write CFG Offset:0x10 USB Configuration Register 0x10 32 read-write n 0x0 0x0 DIS_PDEN Enable internal D+ and D- 175k pull-down resistor 26 27 read-write Disable Disable 0 Enable Enable 1 DPPU_EN Enable internal D+ 1.5k pull-up resistor 29 30 read-write Disable Disable internal D+ pull-up resistor 0 Enable Enable internal D+ pull-up resistor 1 EP1_DIR Endpoint 1 IN/OUT direction setting 0 1 read-write IN EP1 only handshakes to IN token packet 0 OUT EP1 only handshakes to OUT token packet 1 EP2_DIR Endpoint 2 IN/OUT direction setting 1 2 read-write IN EP2 only handshakes to IN token packet 0 OUT EP2 only handshakes to OUT token packet 1 EP3_DIR Endpoint 3 IN/OUT direction setting 2 3 read-write IN EP3 only handshakes to IN token packet 0 OUT EP3 only handshakes to OUT token packet 1 EP4_DIR Endpoint 4 IN/OUT direction setting 3 4 read-write IN EP4 only handshakes to IN token packet 0 OUT EP4 only handshakes to OUT token packet 1 ESD_EN Enable USB anti-ESD protection 27 28 read-write Disable Disable anti-ESD protection 0 Enable Enable anti-ESD protection 1 PHY_EN PHY Transceiver Function Enable 30 31 read-write Disable Disable PHY transceiver function 0 Enable Enable PHY transceiver function 1 SIE_EN USB Serial Interface Engine Enable 28 29 read-write Disable Disable USB SIE function 0 Enable Enable USB SIE function 1 VREG33_EN Enable the internal VREG33 ouput 31 32 read-write Disable Disable VREG33 ouput 0 Enable Enable VREG33 ouput 1 EP0CTL Offset:0x18 USB Endpoint 0 Control Register 0x18 32 read-write n 0x0 0x0 ENDP_CNT Endpoint byte count 0 7 read-write ENDP_EN Enable Endpoint 0 Function 31 32 read-write 0 Disable 0 1 Enable 1 ENDP_STATE Endpoint Handshake State 29 31 read-write 0 NAK 0 1 ACK 1 2 INOUT_STALL 2 3 INOUT_STALL 3 IN_STALL_EN Enable EP0 IN STALL handshake 28 29 read-write 0 Disable 0 1 Enable 1 OUT_STALL_EN Enable EP0 OUT STALL handshake 27 28 read-write 0 Disable 0 1 Enable 1 EP1BUFOS Offset:0x48 USB Endpoint 1 Buffer Offset Register 0x48 32 read-write n 0x0 0x0 OFFSET The offset address for endpoint data buffer 2 8 read-write EP1CTL Offset:0x1C USB Endpoint 1 Control Register 0x1C 32 read-write n 0x0 0x0 ENDP_CNT Endpoint byte count 0 7 read-write ENDP_EN Endpoint 1 Function enable bit 31 32 read-write 0 Disable 0 1 Enable 1 ENDP_STATE Endpoint Handshake State 29 31 read-write 0 NAK 0 1 ACK 1 2 STALL 2 3 STALL 3 EP2BUFOS Offset:0x4C USB Endpoint 2 Buffer Offset Register 0x4C 32 read-write n 0x0 0x0 OFFSET The offset address for endpoint data buffer 2 8 read-write EP2CTL Offset:0x20 USB Endpoint 2 Control Register 0x20 32 read-write n 0x0 0x0 ENDP_CNT Endpoint byte count 0 7 read-write ENDP_EN Endpoint 2 Function enable bit 31 32 read-write 0 Disable 0 1 Enable 1 ENDP_STATE Endpoint Handshake State 29 31 read-write 0 NAK 0 1 ACK 1 2 STALL 2 3 STALL 3 EP3BUFOS Offset:0x50 USB Endpoint 3 Buffer Offset Register 0x50 32 read-write n 0x0 0x0 OFFSET The offset address for endpoint data buffer 2 8 read-write EP3CTL Offset:0x24 USB Endpoint 3 Control Register 0x24 32 read-write n 0x0 0x0 ENDP_CNT Endpoint byte count 0 7 read-write ENDP_EN Endpoint 3 Function enable bit 31 32 read-write 0 Disable 0 1 Enable 1 ENDP_STATE Endpoint Handshake State 29 31 read-write 0 NAK 0 1 ACK 1 2 STALL 2 3 STALL 3 EP4BUFOS Offset:0x54 USB Endpoint 4 Buffer Offset Register 0x54 32 read-write n 0x0 0x0 OFFSET The offset address for endpoint data buffer 2 8 read-write EP4CTL Offset:0x28 USB Endpoint 4 Control Register 0x28 32 read-write n 0x0 0x0 ENDP_CNT Endpoint byte count 0 7 read-write ENDP_EN Endpoint 4 Function enable bit 31 32 read-write 0 Disable 0 1 Enable 1 ENDP_STATE Endpoint Handshake State 29 31 read-write 0 NAK 0 1 ACK 1 2 STALL 2 3 STALL 3 EPTOGGLE Offset:0x3C USB Endpoint Data Toggle Register 0x3C 32 read-write n 0x0 0x0 ENDP1_DATA01 Endpoint 1 data toggle bit 0 1 read-write Disable Clear EP1 toggle bit to DATA0 0 Toggle HW sets toggle bit automatically 1 ENDP2_DATA01 Endpoint 2 data toggle bit 1 2 read-write Disable Clear EP2 toggle bit to DATA0 0 Toggle HW sets toggle bit automatically 1 ENDP3_DATA01 Endpoint 3 data toggle bit 2 3 read-write Disable Clear EP3 toggle bit to DATA0 0 Toggle HW sets toggle bit automatically 1 ENDP4_DATA01 Endpoint 4 data toggle bit 3 4 read-write Disable Clear EP4 toggle bit to DATA0 0 Toggle HW sets toggle bit automatically 1 FRMNO Offset:0x60 USB Frame Number Register 0x60 32 read-only n 0x0 0x0 FRAME_NO The 11-bit frame number of the SOF packet 0 11 read-only INSTS Offset:0x04 USB Interrupt Event Status Register 0x4 32 read-only n 0x0 0x0 BUS_RESET USB Bus Reset signal flag 31 32 read-only 0 No bus reset signal is detected 0 1 Bus reset signal is detected 1 BUS_RESUME USB Bus Resume signal flag 29 30 read-only 0 No bus resume signal is detected 0 1 Bus resume signal from suspend mode is detected 1 BUS_SUSPEND USB Bus Suspend signal flag 30 31 read-only 0 No bus suspend is detected 0 1 Bus suspend is detected 1 BUS_WAKEUP Bus Wakeup Flag 25 26 read-only 0 No wakeup from suspend mode 0 1 Wakeup from suspend mode 1 EP0_IN EP0 IN ACK Transaction Flag 22 23 read-only 0 No EP0 IN Transaction 0 1 EP0 IN Transaction is completed 1 EP0_IN_STALL EP0 IN STALL Transaction is completed 20 21 read-only 0 No EP0 IN STALL transaction 0 1 EP0 IN STALL transaction is completed 1 EP0_OUT EP0 OUT ACK Transaction Flag 21 22 read-only 0 No EP0 OUT ACK transaction 0 1 EP0 OUT ACK transaction is completed 1 EP0_OUT_STALL EP0 OUT STALL transaction 19 20 read-only 0 No EP0 OUT STALL transaction 0 1 EP0 OUT STALL transaction is completed 1 EP0_PRESETUP EP0 Setup Token Packet Flag 24 25 read-only 0 No EP0 Setup token packet 0 1 EP0 Setup token packet is received 1 EP0_SETUP EP0 Setup Transaction Flag 23 24 read-only 0 No EP0 Setup transaction 0 1 EP0 Setup transaction is completed 1 EP1_ACK Endpoint 1 ACK transaction flag 8 9 read-only 0 No EP1 ACK transacation 0 1 EP1 ACK transaction completes 1 EP1_NAK Endpoint 1 NAK transaction flag 0 1 read-only 0 No EP1 NAK transacation 0 1 EP1 NAK transaction completes 1 EP2_ACK Endpoint 2 ACK transaction flag 9 10 read-only 0 No EP2 ACK transacation 0 1 EP2 ACK transaction completes 1 EP2_NAK Endpoint 2 NAK transaction flag 1 2 read-only 0 No EP2 NAK transacation 0 1 EP2 NAK transaction completes 1 EP3_ACK Endpoint 3 ACK transaction flag 10 11 read-only 0 No EP3 ACK transacation 0 1 EP3 ACK transaction completes 1 EP3_NAK Endpoint 3 NAK transaction flag 2 3 read-only 0 No EP3 NAK transacation 0 1 EP3 NAK transaction completes 1 EP4_ACK Endpoint 4 ACK transaction flag 11 12 read-only 0 No EP4 ACK transacation 0 1 EP4 ACK transaction completes 1 EP4_NAK Endpoint 4 NAK transaction flag 3 4 read-only 0 No EP4 NAK transacation 0 1 EP4 NAK transaction completes 1 ERR_SETUP Wrong Setup data received 18 19 read-only 0 Normal 8-byte Setup DATA0 is received 0 1 Setup data is not 8-byte or is not DATA0 1 ERR_TIMEOUT Timeout Status 17 18 read-only 0 No time out 0 1 Bus no any response more than 18 bits time 1 USB_SOF USB SOF packet received flag 26 27 read-only 0 No USB SOF packet 0 1 USB SOF packet is received 1 INSTSC Offset:0x08 USB Interrupt Event Status Clear Register 0x8 32 write-only n 0x0 0x0 BUS_RESETC USB Bus Reset clear bit 31 32 write-only No effect No effect 0 Clear Clear BUS_RESET bit 1 BUS_RESUMEC USB Bus Resume clear bit 29 30 write-only No effect No effect 0 Clear Clear BUS_RESUME bit 1 BUS_WAKEUPC Bus Wakeup clear bit 25 26 write-only No effect No effect 0 Clear Clear BUS_WAKEUP bit 1 EP0_INC EP0 IN clear bit 22 23 write-only No effect No effect 0 Clear Clear EP0_IN bit 1 EP0_IN_STALLC EP0 IN STALL clear bit 20 21 write-only No effect No effect 0 Clear Clear EP0_IN_STALL bit 1 EP0_OUTC EP0 OUT clear bit 21 22 write-only No effect No effect 0 Clear Clear EP0_OUT bit 1 EP0_OUT_STALLC EP0 OUT STALL clear bit 19 20 write-only No effect No effect 0 Clear Clear EP0_OUT_STALL bit 1 EP0_PRESETUPC EP0 PRESETUP clear bit 24 25 write-only No effect No effect 0 Clear Clear EP0_PRESETUP bit 1 EP0_SETUPC EP0 SETUP clear bit 23 24 write-only No effect No effect 0 Clear Clear EP0_SETUP bit 1 EP1_ACKC EP1 ACK clear bit 8 9 write-only No effect No effect 0 Clear Clear EP1_ACK bit 1 EP1_NAKC EP1 NAK clear bit 0 1 write-only No effect No effect 0 Clear Clear EP1_NAK bit 1 EP2_ACKC EP2 ACK clear bit 9 10 write-only No effect No effect 0 Clear Clear EP2_ACK bit 1 EP2_NAKC EP2 NAK clear bit 1 2 write-only No effect No effect 0 Clear Clear EP2_NAK bit 1 EP3_ACKC EP3 ACK clear bit 10 11 write-only No effect No effect 0 Clear Clear EP3_ACK bit 1 EP3_NAKC EP3 NAK clear bit 2 3 write-only No effect No effect 0 Clear Clear EP3_NAK bit 1 EP4_ACKC EP4 ACK clear bit 11 12 write-only No effect No effect 0 Clear Clear EP4_ACK bit 1 EP4_NAKC EP4 NAK clear bit 3 4 write-only No effect No effect 0 Clear Clear EP4_NAK bit 1 ERR_SETUPC Error Setup clear bit 18 19 write-only No effect No effect 0 Clear Clear ERR_SETUP bit 1 ERR_TIMEOUTC Timeout Error clear bit 17 18 write-only No effect No effect 0 Clear Clear ERR_TIMEOUT bit 1 USB_SOFC USB SOF clear bit 26 27 write-only No effect No effect 0 Clear Clear USB_SOF bit 1 INTEN Offset:0x00 USB Interrupt Enable Register 0x0 32 read-write n 0x0 0x0 BUSWK_IE USB Bus Wake Up Interrupt Enable 28 29 read-write Disable Disable Wake Up event interrupt 0 Enable Enable Wake Up event interrupt 1 BUS_IE Bus Event Interrupt Enable 31 32 read-write Disable Disable BUS event interrupt 0 Enable Enable Bus event interrupt 1 EP1_NAK_EN EP1 NAK Interrupt Enable 0 1 read-write Disable Disable EP1 NAK interrupt function 0 Enable Enable EP1 NAK interrupt function 1 EP2_NAK_EN EP2 NAK Interrupt Enable 1 2 read-write Disable Disable EP2 NAK interrupt function 0 Enable Enable EP2 NAK interrupt function 1 EP3_NAK_EN EP3 NAK Interrupt Enable 2 3 read-write Disable Disable EP3 NAK interrupt function 0 Enable Enable EP3 NAK interrupt function 1 EP4_NAK_EN EP4 NAK Interrupt Enable 3 4 read-write Disable Disable EP4 NAK interrupt function 0 Enable Enable EP4 NAK interrupt function 1 EPN_ACK_EN EPN ACK Interrupt Enable 4 5 read-write Disable Disable EP1~4 ACK interrupt function 0 Enable Enable EP1~4 ACK interrupt function 1 USB_IE USB Event Interrupt Enable 29 30 read-write Disable Disable USB event interrupt 0 Enable Enable USB event interrupt 1 USB_SOF_IE USB SOF Interrupt Enable 30 31 read-write Disable Disable USB SOF interrupt 0 Enable Enable USB SOF interrupt 1 PHYPRM Offset:0x64 USB PHY Parameter Register 0x64 32 read-write n 0x0 0x0 PHY_PARAM USB PHY parameter 0 6 read-write PHYPRM2 Offset:0x6C USB PHY Parameter 2 Register 0x6C 32 read-write n 0x0 0x0 PHY_PS USB PHY parameter 2 0 15 read-write PS2CTL Offset:0x70 PS/2 Control Register 0x70 32 read-write n 0x0 0x0 PS2ENB PS/2 internal 5kohm pull-up resistor control bit 31 32 read-write Disable Disable 0 Enable Enabled 1 SCK PS/2 SCK data buffer 2 3 read-write Disable Disable 0 Enable Enabled 1 SCKM PS/2 SCK mode control bit 0 1 read-write Disable Disable 0 Enable Enabled 1 SDA PS/2 SDA data buffer 3 4 read-write Disable Disable 0 Enable Enabled 1 SDAM PS/2 SDA mode control bit 1 2 read-write Disable Disable 0 Enable Enabled 1 RWADDR Offset:0x78 USB Read/Write Address Register 0x78 32 read-write n 0x0 0x0 RWADDR USB FIFO address to be read or written from/to USB FIFO 2 8 read-write RWADDR2 Offset:0x84 USB Read/Write Address Register 2 0x84 32 read-write n 0x0 0x0 RWADDR USB FIFO address to be read or written from/to USB FIFO 2 8 read-write RWDATA Offset:0x7C USB Read/Write Data Register 0x7C 32 read-write n 0x0 0x0 RWDATA Data to be read or written from/to USB FIFO 0 32 read-write RWDATA2 Offset:0x88 USB Read/Write Data Register 2 0x88 32 read-write n 0x0 0x0 RWDATA Data to be read or written from/to USB FIFO 0 32 read-write RWSTATUS Offset:0x80 USB Read/Write Status Register 0x80 32 read-write n 0x0 0x0 R_STATUS WRead status of USB FIFO 1 2 read-write operation ready this bit is automatically cleared as '0' by hardware 0 not ready If F/W is to read the data from USB FIFO now 1 W_STATUS Write status of USB FIFO 0 1 read-write operation ready this bit is automatically cleared as '0' by hardware 0 not ready F/W is to write data into USB FIFO now 1 RWSTATUS2 Offset:0x8C USB Read/Write Status Register 2 0x8C 32 read-write n 0x0 0x0 R_STATUS WRead status of USB FIFO 1 2 read-write operation ready this bit is automatically cleared as '0' by hardware 0 not ready If F/W is to read the data from USB FIFO now 1 W_STATUS Write status of USB FIFO 0 1 read-write operation ready this bit is automatically cleared as '0' by hardware 0 not ready F/W is to write data into USB FIFO now 1 SGCTL Offset:0x14 USB Signal Control Register 0x14 32 read-write n 0x0 0x0 BUS_DN USB D- state 0 1 read-write Low D- state is low 0 High D- state is high 1 BUS_DP USB DP state 1 2 read-write Low D+ state is low 0 High D+ state is high 1 BUS_DRVEN Enable to drive USB bus 2 3 read-write Disable Not to drive USB bus 0 Enable Drive USB bus 1 SN_WDT Watchdog Timer WDT 0x0 0x0 0x2000 registers n WDT 25 CFG Offset:0x00 WDT Configuration Register 0x0 32 read-write n 0x0 0x0 WDKEY WDT register key 16 32 write-only WDTEN WDT enable 0 1 read-write Disable Disable WDT 0 Enable Enable WDT 1 WDTIE WDT interrupt enable 1 2 read-write Disable WDT reset when WDT time-out 0 Enable Enable WDT interrupt 1 WDTINT WDT interrupt flag 2 3 read-write No No WDT time-out 0 WDT time-out WDT interrupt is triggered if WDTIE=1 1 FEED Offset:0x0C WDT Feed Register 0xC 32 write-only n 0x0 0x0 FV Watchdog feed value 0 16 write-only WDKEY WDT register key 16 32 write-only TC Offset:0x08 WDT Timer Constant Register 0x8 32 read-write n 0x0 0x0 TC Watchdog timer constant reload value 0 8 read-write WDKEY WDT register key 16 32 write-only