SONIX
SN32F700B
2024.04.23
ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 48MHz, etc.
CM0
r0p0
little
2
false
8
32
SN_ADC
ADC
ADC
0x0
0x0
0x2000
registers
n
ADC
24
ADB
Offset:0x04 ADC Data Register
0x4
32
read-only
n
0x0
0x0
ADM
Offset:0x00 ADC Management Register
0x0
32
read-write
n
0x0
0x0
ADCKS
ADC clock source divider
8
11
read-write
000b
ADC_PCLK/1
0
001b
ADC_PCLK/2
1
010b
ADC_PCLK/4
2
011b
ADC_PCLK/8
3
101b
ADC_PCLK/16
5
110b
ADC_PCLK/32
6
ADENB
ADC enable
11
12
read-write
Disable
Disable ADC
0
Enable
Enable ADC
1
ADLEN
ADC resolution
7
8
read-write
0
8-bit ADB
0
1
12-bit ADB
1
ADS
ADC start control
6
7
read-write
Stop
ADC stopped
0
Start
Start ADC conversion
1
AVREFHSEL
ADC high reference voltage source
12
13
read-write
Interal Ref. Voltage
P2.0 acts as GPIO or AIN0 pin
0
External reference voltage
P2.0 acts as AVREFH pin
1
CHS
ADC input channel
0
4
read-write
0
AIN0
0
1
AIN1
1
10
Internal Ref. voltage
10
2
AIN2
2
3
AIN3
3
4
AIN4
4
5
AIN5
5
6
AIN6
6
7
AIN7
7
8
AIN8
8
9
AIN9
9
EOC
ADC status
5
6
read-write
Busy
ADC processing
0
End
End of conversion
1
GCHS
ADC global channel enable
4
5
read-write
Disable
Disable AIN channel
0
Enable
Enable AIN channel
1
VHS
Internal Ref. voltage source
13
16
read-write
000b
Internal 2.0V as ADC internal reference high voltage
0
001b
Internal 3.0V as ADC internal reference high voltage
1
010b
Internal 4.5V as ADC internal reference high voltage
2
100b
VDD as ADC internal reference high voltage, Internal 2.0V as AIN10
4
101b
VDD as ADC internal reference high voltage, Internal 3.0V as AIN10
5
110b
VDD as ADC internal reference high voltage, Internal 4.5V as AIN10
6
111b
VDD as ADC internal reference high voltage
7
CALI
Offset:0x14 ADC Calibration Register
0x14
32
read-write
n
0x0
0x0
IE
Offset:0x0C ADC Interrupt Enable Register
0xC
32
read-write
n
0x0
0x0
IE0
AIN0 interrupt enable
0
1
read-write
Disable
Disable AIN0 interrupt
0
Enable
ADC interrupt is triggered when AIN0 completes ADC conversion
1
IE1
AIN1 interrupt enable
1
2
read-write
Disable
Disable AIN1 interrupt
0
Enable
ADC interrupt is triggered when AIN1 completes ADC conversion
1
IE10
AIN10 interrupt enable
10
11
read-write
Disable
Disable AIN10 interrupt
0
Enable
ADC interrupt is triggered when AIN10 completes ADC conversion
1
IE2
AIN2 interrupt enable
2
3
read-write
Disable
Disable AIN2 interrupt
0
Enable
ADC interrupt is triggered when AIN2 completes ADC conversion
1
IE3
AIN3 interrupt enable
3
4
read-write
Disable
Disable AIN3 interrupt
0
Enable
ADC interrupt is triggered when AIN3 completes ADC conversion
1
IE4
AIN4 interrupt enable
4
5
read-write
Disable
Disable AIN4 interrupt
0
Enable
ADC interrupt is triggered when AIN4 completes ADC conversion
1
IE5
AIN5 interrupt enable
5
6
read-write
Disable
Disable AIN5 interrupt
0
Enable
ADC interrupt is triggered when AIN5 completes ADC conversion
1
IE6
AIN6 interrupt enable
6
7
read-write
Disable
Disable AIN6 interrupt
0
Enable
ADC interrupt is triggered when AIN6 completes ADC conversion
1
IE7
AIN7 interrupt enable
7
8
read-write
Disable
Disable AIN7 interrupt
0
Enable
ADC interrupt is triggered when AIN7 completes ADC conversion
1
IE8
AIN8 interrupt enable
8
9
read-write
Disable
Disable AIN8 interrupt
0
Enable
ADC interrupt is triggered when AIN8 completes ADC conversion
1
IE9
AIN9 interrupt enable
9
10
read-write
Disable
Disable AIN9 interrupt
0
Enable
ADC interrupt is triggered when AIN9 completes ADC conversion
1
P2CON
Offset:0x08 ADC Port 2 Control Register
0x8
32
read-only
n
0x0
0x0
P2CON0
P2.0 Control
0
1
read-only
Both
P2.0 can be analog input or digital I/O pin
0
Analog
P2.0 is pure analog input, can't be digital I/O pin
1
P2CON1
P2.1 Control
1
2
read-only
Both
P2.1 can be analog input or digital I/O pin
0
Analog
P2.1 is pure analog input, can't be digital I/O pin
1
P2CON2
P2.2 Control
2
3
read-only
Both
P2.2 can be analog input or digital I/O pin
0
Analog
P2.2 is pure analog input, can't be digital I/O pin
1
P2CON3
P2.3 Control
3
4
read-only
Both
P2.3 can be analog input or digital I/O pin
0
Analog
P2.3 is pure analog input, can't be digital I/O pin
1
P2CON4
P2.4 Control
4
5
read-only
Both
P2.4 can be analog input or digital I/O pin
0
Analog
P2.4 is pure analog input, can't be digital I/O pin
1
P2CON5
P2.5 Control
5
6
read-only
Both
P2.5 can be analog input or digital I/O pin
0
Analog
P2.5 is pure analog input, can't be digital I/O pin
1
P2CON6
P2.6 Control
6
7
read-only
Both
P2.6 can be analog input or digital I/O pin
0
Analog
P2.6 is pure analog input, can't be digital I/O pin
1
P2CON7
P2.7 Control
7
8
read-only
Both
P2.7 can be analog input or digital I/O pin
0
Analog
P2.7 is pure analog input, can't be digital I/O pin
1
P2CON8
P2.8 Control
8
9
read-only
Both
P2.8 can be analog input or digital I/O pin
0
Analog
P2.8 is pure analog input, can't be digital I/O pin
1
P2CON9
P2.9 Control
9
10
read-only
Both
P2.9 can be analog input or digital I/O pin
0
Analog
P2.9 is pure analog input, can't be digital I/O pin
1
RIS
Offset:0x10 ADC Raw Interrupt Status Register
0x10
32
read-write
n
0x0
0x0
IF0
AIN0 interrupt flag
0
1
read-write
No interrupt
No interrupt on AIN0
0
Met interrupt requirements
AIN0 completes ADC conversion
1
IF1
AIN1 interrupt flag
1
2
read-write
No interrupt
No interrupt on AIN1
0
Met interrupt requirements
AIN1 completes ADC conversion
1
IF10
AIN10 interrupt flag
10
11
read-write
No interrupt
No interrupt on AIN10
0
Met interrupt requirements
AIN10 completes ADC conversion
1
IF2
AIN2 interrupt flag
2
3
read-write
No interrupt
No interrupt on AIN2
0
Met interrupt requirements
AIN2 completes ADC conversion
1
IF3
AIN0 interrupt flag
3
4
read-write
No interrupt
No interrupt on AIN3
0
Met interrupt requirements
AIN3 completes ADC conversion
1
IF4
AIN4 interrupt flag
4
5
read-write
No interrupt
No interrupt on AIN4
0
Met interrupt requirements
AIN4 completes ADC conversion
1
IF5
AIN5 interrupt flag
5
6
read-write
No interrupt
No interrupt on AIN5
0
Met interrupt requirements
AIN5 completes ADC conversion
1
IF6
AIN6 interrupt flag
6
7
read-write
No interrupt
No interrupt on AIN6
0
Met interrupt requirements
AIN6 completes ADC conversion
1
IF7
AIN7 interrupt flag
7
8
read-write
No interrupt
No interrupt on AIN7
0
Met interrupt requirements
AIN7 completes ADC conversion
1
IF8
AIN8 interrupt flag
8
9
read-write
No interrupt
No interrupt on AIN8
0
Met interrupt requirements
AIN8 completes ADC conversion
1
IF9
AIN9 interrupt flag
9
10
read-write
No interrupt
No interrupt on AIN9
0
Met interrupt requirements
AIN9 completes ADC conversion
1
SN_CMP
Comparator
CMP
0x0
0x0
0x2000
registers
n
CMP0
1
CMP1
2
CTRL
Offset:0x00 CMP Control Register
0x0
32
read-write
n
0x0
0x0
CM0EN
CMP0 Enable bit
0
1
read-write
Disable
Disable CMP0
0
Enable
Enable CMP0
1
CM0G
CMP0 interrupt trigger direction control bit
7
8
read-write
Falling range trigger
CMP0 output status is from high to low as VPREF0 less than CM0N
0
Rising edge trigger
CMP0 output status is from low to high as VPREF0 more than CM0N
1
CM0OEN
CMP0 Output pin control bit
6
7
read-write
Disable
Disable CM0O
0
Enable
Enable CM0O
1
CM0PREF
CMP0 Positive reference voltage (VPREF0) source
1
2
read-write
VIREF0
VPREF0=VIREF0
0
CM0P
CM0P is VPREF0 input pin.
1
CM0RS
CMP0 internal reference voltage (VIREF0) selection bits
2
6
read-write
0000b
VIREF0=VIREF
0
0001b
VIREF0=VIREF*1/16
1
1010b
VIREF0=VIREF*10/16
10
1011b
VIREF0=VIREF*11/16
11
1100b
VIREF0=VIREF*12/16
12
1101b
VIREF0=VIREF*13/16
13
1110b
VIREF0=VIREF*14/16
14
1111b
VIREF0=VIREF*15/16
15
0010b
VIREF0=VIREF*2/16
2
0011b
VIREF0=VIREF*3/16
3
0100b
VIREF0=VIREF*4/16
4
0101b
VIREF0=VIREF*5/16
5
0110b
VIREF0=VIREF*6/16
6
0111b
VIREF0=VIREF*7/16
7
1000b
VIREF0=VIREF*8/16
8
1001b
VIREF0=VIREF*9/16
9
CM1EN
CMP1 Enable bit
8
9
read-write
Disable
Disable CMP1
0
Enable
Enable CMP1
1
CM1G
CMP1 interrupt trigger direction control bit
15
16
read-write
Falling range trigger
CMP1 output status is from high to low as VPREF1 less than CM1N
0
Rising edge trigger
CMP1 output status is from low to high as VPREF1 more than CM1N
1
CM1OEN
CMP1 Output pin control bit
14
15
read-write
Disable
Disable CM1O
0
Enable
Enable CM1O
1
CM1PREF
CMP1 Positive reference voltage (VPREF1) source
9
10
read-write
VIREF1
VPREF1=VIREF1
0
CM1P
CM1P is VPREF1 input pin.
1
CM1RS
CMP1 internal reference voltage (VIREF1) selection bits
10
14
read-write
0000b
VIREF1=VIREF
0
0001b
VIREF1=VIREF*1/16
1
1010b
VIREF1=VIREF*10/16
10
1011b
VIREF1=VIREF*11/16
11
1100b
VIREF1=VIREF*12/16
12
1101b
VIREF1=VIREF*13/16
13
1110b
VIREF1=VIREF*14/16
14
1111b
VIREF1=VIREF*15/16
15
0010b
VIREF1=VIREF*2/16
2
0011b
VIREF1=VIREF*3/16
3
0100b
VIREF1=VIREF*4/16
4
0101b
VIREF1=VIREF*5/16
5
0110b
VIREF1=VIREF*6/16
6
0111b
VIREF1=VIREF*7/16
7
1000b
VIREF1=VIREF*8/16
8
1001b
VIREF1=VIREF*9/16
9
IC
Offset:0x14 CMP Interrupt Clear Register
0x14
32
write-only
n
0x0
0x0
CM0IC
CMP0 interrupt flag clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear CMP0 interrupt flag
1
CM1IC
CMP1 interrupt flag clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear CMP1 interrupt flag
1
IE
Offset:0x0C CMP Interrupt Enable Register
0xC
32
read-write
n
0x0
0x0
CM0IE
CMP0 interrupt enable
0
1
read-write
Disable
Disable CMP0 interrupt
0
Enable
Enable CMP0 interrupt
1
CM1IE
CMP1 interrupt enable
1
2
read-write
Disable
Disable CMP1 interrupt
0
Enable
Enable CMP1 interrupt
1
OS
Offset:0x08 CMP Output Status Register
0x8
32
read-only
n
0x0
0x0
CM0OUT
CMP0 Output flag bit
0
1
read-only
CMP0 positive voltage is less than CM0N voltage
VPREF0 is less than CM0N voltage
0
CMP0 positive voltage is more than CM0N voltage
VPREF0 is more than CM0N voltage
1
CM1OUT
CMP1 Output flag bit
1
2
read-only
CMP1 positive voltage is less than CM1N voltage
VPREF1 is less than CM1N voltage
0
CMP1 positive voltage is more than CM1N voltage
VPREF1 is more than CM1N voltage
1
RIS
Offset:0x10 CMP n Raw Interrupt Status Register
0x10
32
read-only
n
0x0
0x0
CM0IF
CMP0 raw interrupt flag
0
1
read-only
No interrupt
No interrupt on CMP0
0
Met interrupt requirements
Interrupt requirements met on CMP0
1
CM1IF
CMP1 raw interrupt flag
1
2
read-only
No interrupt
No interrupt on CMP1
0
Met interrupt requirements
Interrupt requirements met on CMP1
1
VIREF
Offset:0x04 CMP Internal Reference Voltage register
0x4
32
read-write
n
0x0
0x0
CMPIREF
CMP internal reference voltage (VIREF) source
1
2
read-write
VDD
VIREF=VDD
0
Internal 3V
VIREF=Internal 3V
1
CMPIREFEN
CMP internal reference voltage (VIREF) enable
0
1
read-write
Disable
Disable CMP internal reference voltage
0
Enable
Enable CMP internal reference voltage
1
SN_CT16B0
16-bit Timer 0 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B0
16
CAP0
Offset:0x2C CT16Bn CAP0 Register
0x2C
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x28 CT16Bn Capture Control Register
0x28
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function
1
CAP0FE
Capture on CT16Bn_CAP0 falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture on CT16Bn_CAP0 rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CIS
Counter Input Select
2
4
read-write
CT16Bn_CAP0
CT16Bn_CAP0
0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Every rising PCLK edge
0
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x30 CT16Bn External Match Register
0x30
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EM2
When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
2
3
read-write
EM3
When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM2 output.
3
4
read-write
EMC0
CT16Bn_PWM0 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
EMC2
CT16Bn_PWM2 functionality
8
10
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM2 pin is LOW
1
High
CT16Bn_PWM2 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM2 pin
3
EMC3
CT16Bn_PWM3 functionality
10
12
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM3 pin is LOW
1
High
CT16Bn_PWM3 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM3 pin
3
IC
Offset:0x3C CT16Bn Interrupt Clear Register
0x3C
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR2IC
MR2IF clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear MR2IF
1
MR3IC
MR3IF clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear MR3IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR2IE
Enable generating an interrupt when MR2 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR2 matches TC
1
MR2RST
Enable reset TC when MR2 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR2 matches TC
1
MR2STOP
Stop TC and PC and clear CEN bit when MR2 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
1
MR3IE
Enable generating an interrupt when MR3 matches TC
9
10
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR3 matches TC
1
MR3RST
Enable reset TC when MR3 matches TC
10
11
read-write
Disable
Disable
0
Enable
Reset TC when MR3 matches TC
1
MR3STOP
Stop TC and PC and clear CEN bit when MR3 matches TC
11
12
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
1
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
29
30
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
30
31
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
31
32
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
MR0
Offset:0x18 CT16Bn MR0 Register
0x18
32
read-write
n
0x0
0x0
MR1
Offset:0x1C CT16Bn MR1 Register
0x1C
32
read-write
n
0x0
0x0
MR2
Offset:0x20 CT16Bn MR2 Register
0x20
32
read-write
n
0x0
0x0
MR3
Offset:0x24 CT16Bn MR3 Register
0x24
32
read-write
n
0x0
0x0
MR9
Offset:0x40 CT16Bn MR9 Register
0x40
32
read-write
n
0x0
0x0
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescaler
0
8
read-write
PWM0NDB
Offset:0x44 CT16Bn PWM0N Dead-band Period Register
0x44
32
read-write
n
0x0
0x0
DB
PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM1NDB
Offset:0x48 CT16Bn PWM1N Dead-band Period Register
0x48
32
read-write
n
0x0
0x0
DB
PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM2NDB
Offset:0x4C CT16Bn PWM2N Dead-band Period Register
0x4C
32
read-write
n
0x0
0x0
DB
PWM2N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM3NDB
Offset:0x50 CT16Bn PWM3N Dead-band Period Register
0x50
32
read-write
n
0x0
0x0
DB
PWM3N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMCTRL
Offset:0x34 CT16Bn PWM Control Register
0x34
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0. During down-counting, PWM0 is 1 when TC is larger/equal than MR0
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0. During down-counting, PWM0 is 0 when TC is larger/equal than MR0
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM0NIOEN
CT16Bn_PWM0N/GPIO selection
24
26
read-write
0
CT16Bn_PWM0N pin is act as GPIO
0
1
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM0N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1. During down-counting, PWM1 is 1 when TC is larger/equal than MR1
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1. During down-counting, PWM1 is 0 when TC is larger/equal than MR1
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWM1NIOEN
CT16Bn_PWM1N/GPIO selection
26
28
read-write
0
CT16Bn_PWM1N pin is act as GPIO
0
1
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM1, but same High signal during dead-band period
1
2
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM1, but same Low signal during dead-band period
2
3
CT16Bn_PWM1N pin outputs the same signal with dead-band of CT16Bn_PWM1
3
PWM2EN
PWM2 enable
2
3
read-write
Disable
CT16Bn_PWM2 is controlled by EM2
0
Enable
Enable PWM mode for CT16Bn_PWM2
1
PWM2IOEN
CT16Bn_PWM2/GPIO selection
22
23
read-write
Disable
CT16Bn_PWM2 pin is act as GPIO
0
Enable
CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
1
PWM2MODE
PWM2 output mode
8
10
read-write
PWM mode 1
During up-counting, PWM2 is 0 when TC is less than MR2. During down-counting, PWM2 is 1 when TC is larger/equal than MR2
0
PWM mode 2
During up-counting, PWM2 is 1 when TC is less than MR2. During down-counting, PWM2 is 0 when TC is larger/equal than MR2
1
Force 0
PWM2 is forced to 0
2
Force 1
PWM2 is forced to 1
3
PWM2NIOEN
CT16Bn_PWM2N/GPIO selection
28
30
read-write
0
CT16Bn_PWM2N pin is act as GPIO
0
1
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM2, but same High signal during dead-band period
1
2
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM2, but same Low signal during dead-band period
2
3
CT16Bn_PWM2N pin outputs the same signal with dead-band of CT16Bn_PWM2
3
PWM3EN
PWM3 enable
3
4
read-write
Disable
CT16Bn_PWM3 is controlled by EM3
0
Enable
Enable PWM mode for CT16Bn_PWM3
1
PWM3IOEN
CT16Bn_PWM3/GPIO selection
23
24
read-write
Disable
CT16Bn_PWM3 pin is act as GPIO
0
Enable
CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
1
PWM3MODE
PWM3 output mode
10
12
read-write
PWM mode 1
During up-counting, PWM3 is 0 when TC is less than MR3. During down-counting, PWM3 is 1 when TC is larger/equal than MR3
0
PWM mode 2
During up-counting, PWM3 is 1 when TC is less than MR3. During down-counting, PWM3 is 0 when TC is larger/equal than MR3
1
Force 0
PWM3 is forced to 0
2
Force 1
PWM3 is forced to 1
3
PWM3NIOEN
CT16Bn_PWM3N/GPIO selection
30
32
read-write
0
CT16Bn_PWM3N pin is act as GPIO
0
1
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same High signal during dead-band period
1
2
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same Low signal during dead-band period
2
3
CT16Bn_PWM3N pin outputs the same signal with dead-band of CT16Bn_PWM3
3
RIS
Offset:0x38 CT16Bn Raw Interrupt Status Register
0x38
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR2IF
Match channel 2 interrupt flag
2
3
read-only
No
No interrupt on match channel 2
0
Met interrupt requirements
Interrupt requirements met on match channel 2
1
MR3IF
Match channel 3 interrupt flag
3
4
read-only
No
No interrupt on match channel 3
0
Met interrupt requirements
Interrupt requirements met on match channel 3
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
Clock source
2
3
read-write
HCLK
CT16Bn clock source=HCLK
0
ELS XTAL
CT16Bn clock source=ELS XTAL
1
CM
Counting Mode
4
7
read-write
Edge-aligned Up-counting mode
Edge-aligned Up-counting mode
0
Edge-aligned Down-counting mode
Edge-aligned Down-counting mode
1
Center-aligned mode 1
The match interrupt flag is set during the down-counting period.
2
Center-aligned mode 2
The match interrupt flag is set during the up-counting period.
4
Center-aligned mode 3
The match interrupt flag is set during both up-counting and down-counting period.
6
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_CT16B1
16-bit Timer 0 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B1
17
CAP0
Offset:0x2C CT16Bn CAP0 Register
0x2C
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x28 CT16Bn Capture Control Register
0x28
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function
1
CAP0FE
Capture on CT16Bn_CAP0 falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture on CT16Bn_CAP0 rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CIS
Counter Input Select
2
4
read-write
CT16Bn_CAP0
CT16Bn_CAP0
0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Every rising PCLK edge
0
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x30 CT16Bn External Match Register
0x30
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EM2
When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
2
3
read-write
EM3
When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM2 output.
3
4
read-write
EMC0
CT16Bn_PWM0 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
EMC2
CT16Bn_PWM2 functionality
8
10
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM2 pin is LOW
1
High
CT16Bn_PWM2 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM2 pin
3
EMC3
CT16Bn_PWM3 functionality
10
12
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM3 pin is LOW
1
High
CT16Bn_PWM3 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM3 pin
3
IC
Offset:0x3C CT16Bn Interrupt Clear Register
0x3C
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR2IC
MR2IF clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear MR2IF
1
MR3IC
MR3IF clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear MR3IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR2IE
Enable generating an interrupt when MR2 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR2 matches TC
1
MR2RST
Enable reset TC when MR2 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR2 matches TC
1
MR2STOP
Stop TC and PC and clear CEN bit when MR2 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
1
MR3IE
Enable generating an interrupt when MR3 matches TC
9
10
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR3 matches TC
1
MR3RST
Enable reset TC when MR3 matches TC
10
11
read-write
Disable
Disable
0
Enable
Reset TC when MR3 matches TC
1
MR3STOP
Stop TC and PC and clear CEN bit when MR3 matches TC
11
12
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
1
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
29
30
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
30
31
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
31
32
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
MR0
Offset:0x18 CT16Bn MR0 Register
0x18
32
read-write
n
0x0
0x0
MR1
Offset:0x1C CT16Bn MR1 Register
0x1C
32
read-write
n
0x0
0x0
MR2
Offset:0x20 CT16Bn MR2 Register
0x20
32
read-write
n
0x0
0x0
MR3
Offset:0x24 CT16Bn MR3 Register
0x24
32
read-write
n
0x0
0x0
MR9
Offset:0x40 CT16Bn MR9 Register
0x40
32
read-write
n
0x0
0x0
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescaler
0
8
read-write
PWM0NDB
Offset:0x44 CT16Bn PWM0N Dead-band Period Register
0x44
32
read-write
n
0x0
0x0
DB
PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM1NDB
Offset:0x48 CT16Bn PWM1N Dead-band Period Register
0x48
32
read-write
n
0x0
0x0
DB
PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM2NDB
Offset:0x4C CT16Bn PWM2N Dead-band Period Register
0x4C
32
read-write
n
0x0
0x0
DB
PWM2N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM3NDB
Offset:0x50 CT16Bn PWM3N Dead-band Period Register
0x50
32
read-write
n
0x0
0x0
DB
PWM3N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMCTRL
Offset:0x34 CT16Bn PWM Control Register
0x34
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0. During down-counting, PWM0 is 1 when TC is larger/equal than MR0
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0. During down-counting, PWM0 is 0 when TC is larger/equal than MR0
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM0NIOEN
CT16Bn_PWM0N/GPIO selection
24
26
read-write
0
CT16Bn_PWM0N pin is act as GPIO
0
1
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM0N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1. During down-counting, PWM1 is 1 when TC is larger/equal than MR1
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1. During down-counting, PWM1 is 0 when TC is larger/equal than MR1
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWM1NIOEN
CT16Bn_PWM1N/GPIO selection
26
28
read-write
0
CT16Bn_PWM1N pin is act as GPIO
0
1
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM1, but same High signal during dead-band period
1
2
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM1, but same Low signal during dead-band period
2
3
CT16Bn_PWM1N pin outputs the same signal with dead-band of CT16Bn_PWM1
3
PWM2EN
PWM2 enable
2
3
read-write
Disable
CT16Bn_PWM2 is controlled by EM2
0
Enable
Enable PWM mode for CT16Bn_PWM2
1
PWM2IOEN
CT16Bn_PWM2/GPIO selection
22
23
read-write
Disable
CT16Bn_PWM2 pin is act as GPIO
0
Enable
CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
1
PWM2MODE
PWM2 output mode
8
10
read-write
PWM mode 1
During up-counting, PWM2 is 0 when TC is less than MR2. During down-counting, PWM2 is 1 when TC is larger/equal than MR2
0
PWM mode 2
During up-counting, PWM2 is 1 when TC is less than MR2. During down-counting, PWM2 is 0 when TC is larger/equal than MR2
1
Force 0
PWM2 is forced to 0
2
Force 1
PWM2 is forced to 1
3
PWM2NIOEN
CT16Bn_PWM2N/GPIO selection
28
30
read-write
0
CT16Bn_PWM2N pin is act as GPIO
0
1
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM2, but same High signal during dead-band period
1
2
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM2, but same Low signal during dead-band period
2
3
CT16Bn_PWM2N pin outputs the same signal with dead-band of CT16Bn_PWM2
3
PWM3EN
PWM3 enable
3
4
read-write
Disable
CT16Bn_PWM3 is controlled by EM3
0
Enable
Enable PWM mode for CT16Bn_PWM3
1
PWM3IOEN
CT16Bn_PWM3/GPIO selection
23
24
read-write
Disable
CT16Bn_PWM3 pin is act as GPIO
0
Enable
CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
1
PWM3MODE
PWM3 output mode
10
12
read-write
PWM mode 1
During up-counting, PWM3 is 0 when TC is less than MR3. During down-counting, PWM3 is 1 when TC is larger/equal than MR3
0
PWM mode 2
During up-counting, PWM3 is 1 when TC is less than MR3. During down-counting, PWM3 is 0 when TC is larger/equal than MR3
1
Force 0
PWM3 is forced to 0
2
Force 1
PWM3 is forced to 1
3
PWM3NIOEN
CT16Bn_PWM3N/GPIO selection
30
32
read-write
0
CT16Bn_PWM3N pin is act as GPIO
0
1
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same High signal during dead-band period
1
2
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same Low signal during dead-band period
2
3
CT16Bn_PWM3N pin outputs the same signal with dead-band of CT16Bn_PWM3
3
RIS
Offset:0x38 CT16Bn Raw Interrupt Status Register
0x38
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR2IF
Match channel 2 interrupt flag
2
3
read-only
No
No interrupt on match channel 2
0
Met interrupt requirements
Interrupt requirements met on match channel 2
1
MR3IF
Match channel 3 interrupt flag
3
4
read-only
No
No interrupt on match channel 3
0
Met interrupt requirements
Interrupt requirements met on match channel 3
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
Clock source
2
3
read-write
HCLK
CT16Bn clock source=HCLK
0
ELS XTAL
CT16Bn clock source=ELS XTAL
1
CM
Counting Mode
4
7
read-write
Edge-aligned Up-counting mode
Edge-aligned Up-counting mode
0
Edge-aligned Down-counting mode
Edge-aligned Down-counting mode
1
Center-aligned mode 1
The match interrupt flag is set during the down-counting period.
2
Center-aligned mode 2
The match interrupt flag is set during the up-counting period.
4
Center-aligned mode 3
The match interrupt flag is set during both up-counting and down-counting period.
6
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_CT16B2
16-bit Timer 0 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B2
12
CAP0
Offset:0x2C CT16Bn CAP0 Register
0x2C
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x28 CT16Bn Capture Control Register
0x28
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function
1
CAP0FE
Capture on CT16Bn_CAP0 falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture on CT16Bn_CAP0 rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CIS
Counter Input Select
2
4
read-write
CT16Bn_CAP0
CT16Bn_CAP0
0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Every rising PCLK edge
0
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
Counter Mode
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x30 CT16Bn External Match Register
0x30
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EM2
When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
2
3
read-write
EM3
When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM2 output.
3
4
read-write
EMC0
CT16Bn_PWM0 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
EMC2
CT16Bn_PWM2 functionality
8
10
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM2 pin is LOW
1
High
CT16Bn_PWM2 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM2 pin
3
EMC3
CT16Bn_PWM3 functionality
10
12
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM3 pin is LOW
1
High
CT16Bn_PWM3 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM3 pin
3
IC
Offset:0x3C CT16Bn Interrupt Clear Register
0x3C
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR2IC
MR2IF clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear MR2IF
1
MR3IC
MR3IF clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear MR3IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR2IE
Enable generating an interrupt when MR2 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR2 matches TC
1
MR2RST
Enable reset TC when MR2 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR2 matches TC
1
MR2STOP
Stop TC and PC and clear CEN bit when MR2 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
1
MR3IE
Enable generating an interrupt when MR3 matches TC
9
10
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR3 matches TC
1
MR3RST
Enable reset TC when MR3 matches TC
10
11
read-write
Disable
Disable
0
Enable
Reset TC when MR3 matches TC
1
MR3STOP
Stop TC and PC and clear CEN bit when MR3 matches TC
11
12
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
1
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
29
30
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
30
31
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
31
32
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
MR0
Offset:0x18 CT16Bn MR0 Register
0x18
32
read-write
n
0x0
0x0
MR1
Offset:0x1C CT16Bn MR1 Register
0x1C
32
read-write
n
0x0
0x0
MR2
Offset:0x20 CT16Bn MR2 Register
0x20
32
read-write
n
0x0
0x0
MR3
Offset:0x24 CT16Bn MR3 Register
0x24
32
read-write
n
0x0
0x0
MR9
Offset:0x40 CT16Bn MR9 Register
0x40
32
read-write
n
0x0
0x0
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescaler
0
8
read-write
PWM0NDB
Offset:0x44 CT16Bn PWM0N Dead-band Period Register
0x44
32
read-write
n
0x0
0x0
DB
PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM1NDB
Offset:0x48 CT16Bn PWM1N Dead-band Period Register
0x48
32
read-write
n
0x0
0x0
DB
PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM2NDB
Offset:0x4C CT16Bn PWM2N Dead-band Period Register
0x4C
32
read-write
n
0x0
0x0
DB
PWM2N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWM3NDB
Offset:0x50 CT16Bn PWM3N Dead-band Period Register
0x50
32
read-write
n
0x0
0x0
DB
PWM3N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMCTRL
Offset:0x34 CT16Bn PWM Control Register
0x34
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0. During down-counting, PWM0 is 1 when TC is larger/equal than MR0
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0. During down-counting, PWM0 is 0 when TC is larger/equal than MR0
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM0NIOEN
CT16Bn_PWM0N/GPIO selection
24
26
read-write
0
CT16Bn_PWM0N pin is act as GPIO
0
1
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM0N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1. During down-counting, PWM1 is 1 when TC is larger/equal than MR1
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1. During down-counting, PWM1 is 0 when TC is larger/equal than MR1
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWM1NIOEN
CT16Bn_PWM1N/GPIO selection
26
28
read-write
0
CT16Bn_PWM1N pin is act as GPIO
0
1
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM1, but same High signal during dead-band period
1
2
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM1, but same Low signal during dead-band period
2
3
CT16Bn_PWM1N pin outputs the same signal with dead-band of CT16Bn_PWM1
3
PWM2EN
PWM2 enable
2
3
read-write
Disable
CT16Bn_PWM2 is controlled by EM2
0
Enable
Enable PWM mode for CT16Bn_PWM2
1
PWM2IOEN
CT16Bn_PWM2/GPIO selection
22
23
read-write
Disable
CT16Bn_PWM2 pin is act as GPIO
0
Enable
CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
1
PWM2MODE
PWM2 output mode
8
10
read-write
PWM mode 1
During up-counting, PWM2 is 0 when TC is less than MR2. During down-counting, PWM2 is 1 when TC is larger/equal than MR2
0
PWM mode 2
During up-counting, PWM2 is 1 when TC is less than MR2. During down-counting, PWM2 is 0 when TC is larger/equal than MR2
1
Force 0
PWM2 is forced to 0
2
Force 1
PWM2 is forced to 1
3
PWM2NIOEN
CT16Bn_PWM2N/GPIO selection
28
30
read-write
0
CT16Bn_PWM2N pin is act as GPIO
0
1
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM2, but same High signal during dead-band period
1
2
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM2, but same Low signal during dead-band period
2
3
CT16Bn_PWM2N pin outputs the same signal with dead-band of CT16Bn_PWM2
3
PWM3EN
PWM3 enable
3
4
read-write
Disable
CT16Bn_PWM3 is controlled by EM3
0
Enable
Enable PWM mode for CT16Bn_PWM3
1
PWM3IOEN
CT16Bn_PWM3/GPIO selection
23
24
read-write
Disable
CT16Bn_PWM3 pin is act as GPIO
0
Enable
CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
1
PWM3MODE
PWM3 output mode
10
12
read-write
PWM mode 1
During up-counting, PWM3 is 0 when TC is less than MR3. During down-counting, PWM3 is 1 when TC is larger/equal than MR3
0
PWM mode 2
During up-counting, PWM3 is 1 when TC is less than MR3. During down-counting, PWM3 is 0 when TC is larger/equal than MR3
1
Force 0
PWM3 is forced to 0
2
Force 1
PWM3 is forced to 1
3
PWM3NIOEN
CT16Bn_PWM3N/GPIO selection
30
32
read-write
0
CT16Bn_PWM3N pin is act as GPIO
0
1
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same High signal during dead-band period
1
2
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same Low signal during dead-band period
2
3
CT16Bn_PWM3N pin outputs the same signal with dead-band of CT16Bn_PWM3
3
RIS
Offset:0x38 CT16Bn Raw Interrupt Status Register
0x38
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR2IF
Match channel 2 interrupt flag
2
3
read-only
No
No interrupt on match channel 2
0
Met interrupt requirements
Interrupt requirements met on match channel 2
1
MR3IF
Match channel 3 interrupt flag
3
4
read-only
No
No interrupt on match channel 3
0
Met interrupt requirements
Interrupt requirements met on match channel 3
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
Clock source
2
3
read-write
HCLK
CT16Bn clock source=HCLK
0
ELS XTAL
CT16Bn clock source=ELS XTAL
1
CM
Counting Mode
4
7
read-write
Edge-aligned Up-counting mode
Edge-aligned Up-counting mode
0
Edge-aligned Down-counting mode
Edge-aligned Down-counting mode
1
Center-aligned mode 1
The match interrupt flag is set during the down-counting period.
2
Center-aligned mode 2
The match interrupt flag is set during the up-counting period.
4
Center-aligned mode 3
The match interrupt flag is set during both up-counting and down-counting period.
6
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_FLASH
FLASH Memory Control Registers
FLASH
0x0
0x0
0x2000
registers
n
ADDR
Offset:0x10 Flash Address Register
0x10
32
read-write
n
0x0
0x0
CHKSUM
Offset:0x14 Flash Checksum Register
0x14
32
read-only
n
0x0
0x0
BootROM
Checksum of Boot ROM
16
32
read-only
UserROM
Checksum of User ROM
0
16
read-only
CTRL
Offset:0x08 Flash Control Register
0x8
32
read-write
n
0x0
0x0
CHK
Checksum calculation chosen
7
8
read-write
Disable
Disable
0
Enable
Trigger checksum calculation
1
PER
Page erase mode chosen bit
1
2
read-write
Disable
Disable page erase mode
0
Enable
Enable page erase mode
1
PG
Flash program mode chosen bit
0
1
read-write
Disable
Disable Flash program mode
0
Enable
Enable Flash program mode
1
START
Start erase/program operation
6
7
read-write
0
Stop/finish operation
0
1
Start erase/program operation
1
DATA
Offset:0x0C Flash Data Register
0xC
32
read-write
n
0x0
0x0
LPCTRL
Offset:0x00 Flash Low Power Control Register
0x0
32
read-write
n
0x0
0x0
LPMODE
Flash Low Power mode selection bit
0
4
read-write
0
HCLK is less than or equal to 12MHz
0
13
HCLK is more than 24MHz
13
2
HCLK is less than or equal to 8KHz
2
3
HCLK is more than 12MHz, and less than or equal to 24MHz
3
STATUS
Offset:0x04 Flash Status Register
0x4
32
read-write
n
0x0
0x0
BUSY
Busy flag
0
1
read-only
Idle
FMC is idle
0
Busy
Flash operation is in process
1
ERR
Erase/Error flag
2
3
read-write
No error
No error
0
Error
The address is illegal or over page boundary
1
SN_GPIO0
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P0
31
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR10
Clear Pn.10
10
11
write-only
No effect
No effect
0
Clear
Clear Pn.10
1
BCLR11
Clear Pn.11
11
12
write-only
No effect
No effect
0
Clear
Clear Pn.11
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET10
Set Pn.10
10
11
write-only
No effect
No effect
0
Set
Set Pn.10 to 1
1
BSET11
Set Pn.11
11
12
write-only
No effect
No effect
0
Set
Set Pn.11 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG10
Configuration of Pn.10
20
22
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG11
Configuration of Pn.11
22
24
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA10
Data of Pn.10
10
11
read-write
0
Pn.10 is 0
0
1
Pn.10 is 1
1
DATA11
Data of Pn.11
11
12
read-write
0
Pn.11 is 0
0
1
Pn.11 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS10
Interrupt on Pn.10 is triggered ob both edges
10
11
read-write
IEV
Interrupt on Pn.10 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.10 trigger an interrupt
1
IBS11
Interrupt on Pn.11 is triggered ob both edges
11
12
read-write
IEV
Interrupt on Pn.11 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.11 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC10
Pn.10 interrupt flag clear
10
11
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.10
1
IC11
Pn.11 interrupt flag clear
11
12
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.11
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE10
Interrupt on Pn.10 enable
10
11
read-write
Disable
Disable interrupt on Pn.10
0
Enable
Enable interrupt on Pn.10
1
IE11
Interrupt on Pn.11 enable
11
12
read-write
Disable
Disable interrupt on Pn.11
0
Enable
Enable interrupt on Pn.11
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV10
Interrupt trigged evnet on Pn.10
10
11
read-write
0
Rising edge or High level on Pn.10 triggers an interrupt
0
1
Falling edge or Low level on Pn.10 triggers an interrupt
1
IEV11
Interrupt trigged evnet on Pn.11
11
12
read-write
0
Rising edge or High level on Pn.11 triggers an interrupt
0
1
Falling edge or Low level on Pn.11 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS10
Interrupt on Pn.10 is event or edge sensitive
10
11
read-write
Edge
Interrupt on Pn.10 is edge sensitive
0
Event
Interrupt on Pn.10 is event sensitive
1
IS11
Interrupt on Pn.11 is event or edge sensitive
11
12
read-write
Edge
Interrupt on Pn.11 is edge sensitive
0
Event
Interrupt on Pn.11 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE10
Mode of Pn.10
10
11
read-write
I
Pn.10 is Input pin
0
O
Pn.10 is Output pin
1
MODE11
Mode of Pn.11
11
12
read-write
I
Pn.11 is Input pin
0
O
Pn.11 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
ODCTRL
Offset:0x2C GPIO Port n Open-drain Control Register
0x2C
32
read-write
n
0x0
0x0
Pn4OC
Pn.4 open-drain control
4
5
read-write
Disable
Disable
0
Enable
Enable
1
Pn5OC
Pn.5 open-drain control
5
6
read-write
Disable
Disable
0
Enable
Enable
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF10
Pn.10 raw interrupt flag
10
11
read-only
0
No interrupt on Pn.10
0
1
Interrupt requirements met on Pn.10
1
IF11
Pn.11 raw interrupt flag
11
12
read-only
0
No interrupt on Pn.11
0
1
Interrupt requirements met on Pn.11
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_GPIO1
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P1
30
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR10
Clear Pn.10
10
11
write-only
No effect
No effect
0
Clear
Clear Pn.10
1
BCLR11
Clear Pn.11
11
12
write-only
No effect
No effect
0
Clear
Clear Pn.11
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET10
Set Pn.10
10
11
write-only
No effect
No effect
0
Set
Set Pn.10 to 1
1
BSET11
Set Pn.11
11
12
write-only
No effect
No effect
0
Set
Set Pn.11 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG10
Configuration of Pn.10
20
22
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG11
Configuration of Pn.11
22
24
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA10
Data of Pn.10
10
11
read-write
0
Pn.10 is 0
0
1
Pn.10 is 1
1
DATA11
Data of Pn.11
11
12
read-write
0
Pn.11 is 0
0
1
Pn.11 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS10
Interrupt on Pn.10 is triggered ob both edges
10
11
read-write
IEV
Interrupt on Pn.10 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.10 trigger an interrupt
1
IBS11
Interrupt on Pn.11 is triggered ob both edges
11
12
read-write
IEV
Interrupt on Pn.11 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.11 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC10
Pn.10 interrupt flag clear
10
11
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.10
1
IC11
Pn.11 interrupt flag clear
11
12
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.11
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE10
Interrupt on Pn.10 enable
10
11
read-write
Disable
Disable interrupt on Pn.10
0
Enable
Enable interrupt on Pn.10
1
IE11
Interrupt on Pn.11 enable
11
12
read-write
Disable
Disable interrupt on Pn.11
0
Enable
Enable interrupt on Pn.11
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV10
Interrupt trigged evnet on Pn.10
10
11
read-write
0
Rising edge or High level on Pn.10 triggers an interrupt
0
1
Falling edge or Low level on Pn.10 triggers an interrupt
1
IEV11
Interrupt trigged evnet on Pn.11
11
12
read-write
0
Rising edge or High level on Pn.11 triggers an interrupt
0
1
Falling edge or Low level on Pn.11 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS10
Interrupt on Pn.10 is event or edge sensitive
10
11
read-write
Edge
Interrupt on Pn.10 is edge sensitive
0
Event
Interrupt on Pn.10 is event sensitive
1
IS11
Interrupt on Pn.11 is event or edge sensitive
11
12
read-write
Edge
Interrupt on Pn.11 is edge sensitive
0
Event
Interrupt on Pn.11 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE10
Mode of Pn.10
10
11
read-write
I
Pn.10 is Input pin
0
O
Pn.10 is Output pin
1
MODE11
Mode of Pn.11
11
12
read-write
I
Pn.11 is Input pin
0
O
Pn.11 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
ODCTRL
Offset:0x2C GPIO Port n Open-drain Control Register
0x2C
32
read-write
n
0x0
0x0
Pn4OC
Pn.4 open-drain control
4
5
read-write
Disable
Disable
0
Enable
Enable
1
Pn5OC
Pn.5 open-drain control
5
6
read-write
Disable
Disable
0
Enable
Enable
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF10
Pn.10 raw interrupt flag
10
11
read-only
0
No interrupt on Pn.10
0
1
Interrupt requirements met on Pn.10
1
IF11
Pn.11 raw interrupt flag
11
12
read-only
0
No interrupt on Pn.11
0
1
Interrupt requirements met on Pn.11
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_GPIO2
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P2
29
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_GPIO3
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P3
28
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR10
Clear Pn.10
10
11
write-only
No effect
No effect
0
Clear
Clear Pn.10
1
BCLR11
Clear Pn.11
11
12
write-only
No effect
No effect
0
Clear
Clear Pn.11
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET10
Set Pn.10
10
11
write-only
No effect
No effect
0
Set
Set Pn.10 to 1
1
BSET11
Set Pn.11
11
12
write-only
No effect
No effect
0
Set
Set Pn.11 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG10
Configuration of Pn.10
20
22
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG11
Configuration of Pn.11
22
24
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
01b
Enable pull-down resistor
1
10b
No pull-up/pull-down resistor enabled
2
11b
Repeater mode
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA10
Data of Pn.10
10
11
read-write
0
Pn.10 is 0
0
1
Pn.10 is 1
1
DATA11
Data of Pn.11
11
12
read-write
0
Pn.11 is 0
0
1
Pn.11 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS10
Interrupt on Pn.10 is triggered ob both edges
10
11
read-write
IEV
Interrupt on Pn.10 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.10 trigger an interrupt
1
IBS11
Interrupt on Pn.11 is triggered ob both edges
11
12
read-write
IEV
Interrupt on Pn.11 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.11 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC10
Pn.10 interrupt flag clear
10
11
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.10
1
IC11
Pn.11 interrupt flag clear
11
12
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.11
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE10
Interrupt on Pn.10 enable
10
11
read-write
Disable
Disable interrupt on Pn.10
0
Enable
Enable interrupt on Pn.10
1
IE11
Interrupt on Pn.11 enable
11
12
read-write
Disable
Disable interrupt on Pn.11
0
Enable
Enable interrupt on Pn.11
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV10
Interrupt trigged evnet on Pn.10
10
11
read-write
0
Rising edge or High level on Pn.10 triggers an interrupt
0
1
Falling edge or Low level on Pn.10 triggers an interrupt
1
IEV11
Interrupt trigged evnet on Pn.11
11
12
read-write
0
Rising edge or High level on Pn.11 triggers an interrupt
0
1
Falling edge or Low level on Pn.11 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS10
Interrupt on Pn.10 is event or edge sensitive
10
11
read-write
Edge
Interrupt on Pn.10 is edge sensitive
0
Event
Interrupt on Pn.10 is event sensitive
1
IS11
Interrupt on Pn.11 is event or edge sensitive
11
12
read-write
Edge
Interrupt on Pn.11 is edge sensitive
0
Event
Interrupt on Pn.11 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE10
Mode of Pn.10
10
11
read-write
I
Pn.10 is Input pin
0
O
Pn.10 is Output pin
1
MODE11
Mode of Pn.11
11
12
read-write
I
Pn.11 is Input pin
0
O
Pn.11 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
ODCTRL
Offset:0x2C GPIO Port n Open-drain Control Register
0x2C
32
read-write
n
0x0
0x0
Pn4OC
Pn.4 open-drain control
4
5
read-write
Disable
Disable
0
Enable
Enable
1
Pn5OC
Pn.5 open-drain control
5
6
read-write
Disable
Disable
0
Enable
Enable
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF10
Pn.10 raw interrupt flag
10
11
read-only
0
No interrupt on Pn.10
0
1
Interrupt requirements met on Pn.10
1
IF11
Pn.11 raw interrupt flag
11
12
read-only
0
No interrupt on Pn.11
0
1
Interrupt requirements met on Pn.11
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_I2C0
I2C0
I2C
0x0
0x0
0x2000
registers
n
I2C0
15
CTRL
Offset:0x00 I2Cn Control Register
0x0
32
read-write
n
0x0
0x0
ACK
ACK assert flag
2
3
read-write
No
Master: No action/Slave: Assert NACK after receiving
0
Assert
Assert ACK during the acknowledge clock pulse on SCLn
1
I2CEN
I2Cn interface enable
8
9
read-write
Disable
Disable I2C
0
Enable
Enable I2C
1
I2CMODE
I2C mode
7
8
read-write
Standard/Fast mode
Standard/Fast mode
0
NACK
NACK assert flag
1
2
read-write
No action
No action
0
Assert
Assert NACK during the acknowledge clock pulse on SCLn
1
STA
START assert flag
5
6
read-write
No action
No START condition or Repeated START condition will be generated
0
Assert
Enter master mode and transmit a START or Repeated START condition
1
STO
STOP assert flag
4
5
read-write
Idle
STOP condition idle
0
Assert
Transmit a STOP condition in master mode, or recover from an error condition in slave mode
1
RXDATA
Offset:0x0C I2Cn RX Data Register
0xC
32
read-only
n
0x0
0x0
Data
RX Data received when RX_DN=1
0
8
read-only
SCLHT
Offset:0x20 I2Cn SCL High Time Register
0x20
32
read-write
n
0x0
0x0
SCLH
SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle
0
8
read-write
SCLLT
Offset:0x24 I2Cn SCL Low Time Register
0x24
32
read-write
n
0x0
0x0
SCLL
SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle
0
8
read-write
SLVADDR0
Offset:0x10 I2Cn Slave Address 0 Register
0x10
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 0
0
10
read-write
ADD_MODE
Slave address mode
31
32
read-write
0
7-bit slave address mode
0
1
10-bit slave address mode
1
GCEN
General call address enable
30
31
read-write
Disable
Disable general call address
0
Enable
Enable general call address (0x0)
1
SLVADDR1
Offset:0x14 I2Cn Slave Address 1 Register
0x14
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 1
0
10
read-write
SLVADDR2
Offset:0x18 I2Cn Slave Address 2 Register
0x18
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 2
0
10
read-write
SLVADDR3
Offset:0x1C I2Cn Slave Address 3 Register
0x1C
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 3
0
10
read-write
STAT
Offset:0x04 I2Cn Status Register
0x4
32
read-write
n
0x0
0x0
ACK_STAT
ACK done status
1
2
read-only
No
No ACK received
0
Done
Receive an ACK
1
I2CIF
I2C interrupt flag
15
16
read-write
0
I2C status doesn't change
0
1
I2C status changes
1
LOST_ARB
Lost arbitration status
8
9
read-only
0
Not lost arbitration
0
1
Lost arbitration
1
MST
I2C master/slave status
5
6
read-only
Slave
Act as Slave
0
Master
Act as Master
1
NACK_STAT
NACK done status
2
3
read-only
No
No NACK received
0
Done
Receive a NACK
1
RX_DN
RX done status
0
1
read-only
Not done
No RX with ACK/NACK transfer
0
Done
8-bit RX with ACK/NACK transfer
1
SLV_RX_HIT
Slave RX address hit flag
6
7
read-only
0
No matched slave address
0
1
Slave address hit, and is called for RX
1
SLV_TX_HIT
Slave TX address hit flag
7
8
read-only
0
No matched slave address
0
1
Slave address hit, and is called for TX
1
START_DN
START done status
4
5
read-only
No
No START condition
0
Assert
Transmit or receive a START condition
1
STOP_DN
STOP done status
3
4
read-only
No
No STOP condition
0
Done
Transmit or receive a STOP condition
1
TIMEOUT
Time-out status
9
10
read-only
0
No timeout
0
1
Timeout
1
TOCTRL
Offset:0x2C I2Cn Timeout Control Register
0x2C
32
read-write
n
0x0
0x0
TO
Timeout period time = TO*32*I2Cn_PCLK cycle
0
16
read-write
TXDATA
Offset:0x08 I2Cn TX Data Register
0x8
32
read-write
n
0x0
0x0
Data
TX Data
0
8
read-write
SN_PMU
Power Management Unit
PMU
0x0
0x0
0x2000
registers
n
BKP0
Offset:0x00 PMU Backup Register 0
0x0
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
BKP1
Offset:0x04 PMU Backup Register 1
0x4
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
BKP2
Offset:0x08 PMU Backup Register 2
0x8
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
BKP3
Offset:0x0C PMU Backup Register 3
0xC
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
BKP4
Offset:0x10 PMU Backup Register 4
0x10
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
BKP5
Offset:0x14 PMU Backup Register 5
0x14
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
BKP6
Offset:0x18 PMU Backup Register 6
0x18
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
BKP7
Offset:0x1C PMU Backup Register 7
0x1C
32
read-write
n
0x0
0x0
BACKUPDATA
Data retained
0
8
read-write
CTRL
Offset:0x40 PMU Control Register
0x40
32
read-write
n
0x0
0x0
MODE
Low Power mode selection
0
3
read-write
Disable
Disable Low-power mode
0
Deep-sleep mode
WFI instruction will make MCU enter Deep-sleep mode
2
Sleep mode
WFI instruction will make MCU enter Sleep mode
4
LATCHCTRL1
Offset:0x44 PMU Latch Control Register 1
0x44
32
read-write
n
0x0
0x0
LATCHEN
Latch enable bit
0
1
read-write
0
No effect
0
1
Enable GPIO latch function
1
LATCHKEY
Latch register key
16
32
write-only
LATCHCTRL2
Offset:0x48 PMU Latch Control Register 2
0x48
32
read-write
n
0x0
0x0
LATCHDIS
Latch disable bit
0
1
read-write
0
No effect
0
1
Disable GPIO latch function
1
LATCHKEY
Latch register key
16
32
write-only
LATCHST
Offset:0x4C PMU Latch Status Register
0x4C
32
read-only
n
0x0
0x0
LATCHST
Latch status
0
1
read-only
Not latched
GPIO is Not latched
0
Latched
GPIO status is latched
1
SN_RTC
Real-time Clock
RTC
0x0
0x0
0x2000
registers
n
RTC
27
CLKS
Offset:0x04 RTC Clock Source Register
0x4
32
read-write
n
0x0
0x0
CLKSEL
RTC clock source
0
2
read-write
ILRC
RTC clock source=ILRC
0
ELS XTAL
RTC clock source=ELS XTAL
1
EHS XTAL clock/128
RTC clock source=EHS XTAL/128
3
CTRL
Offset:0x00 RTC Control Register
0x0
32
read-write
n
0x0
0x0
RTCEN
RTC enable
0
1
read-write
Disable
Disable RTC
0
Enable
Enable RTC
1
IC
Offset:0x10 RTC Interrupt Clear Register
0x10
32
write-only
n
0x0
0x0
SECIC
Second interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear second interrupt flag
1
IE
Offset:0x08 RTC Interrupt Enable Register
0x8
32
read-write
n
0x0
0x0
SECIE
Second interrupt enable
0
1
read-write
Disable
Disable second interrupt
0
Enable
Enable second interrupt
1
RIS
Offset:0x0C RTC Raw Interrupt Status Register
0xC
32
read-only
n
0x0
0x0
SECIF
Second interrupt flag
0
1
read-only
No
No second interrupt
0
Met second interrupt requirements
Second interrupt is triggered when SECIE=1
1
SECCNT
Offset:0x18 RTC Second Counter Register
0x18
32
read-only
n
0x0
0x0
SECCNTV
Offset:0x14 RTC Second Counter Reload Value Register
0x14
32
read-write
n
0x0
0x0
SN_SPI0
SPI0
SPI
0x0
0x0
0x2000
registers
n
SPI0
13
CLKDIV
Offset:0x08 SPIn Clock Divider Register
0x8
32
read-write
n
0x0
0x0
DIV
SPIn SCK=SPIn_PCLK/(2*DIV+2)
0
8
read-write
CTRL0
Offset:0x00 SPIn Control Register 0
0x0
32
read-write
n
0x0
0x0
DL
Data length = DL[3:0]+1
8
12
read-write
1010b
Data length=11
10
1011b
Data length=12
11
1100b
Data length=13
12
1101b
Data length=14
13
1110b
Data length=15
14
1111b
Data length=16
15
0010b
Data length=3
2
0011b
Data length=4
3
0100b
Data length=5
4
0101b
Data length=6
5
0110b
Data length=7
6
0111b
Data length=8
7
1000b
Data length=9
8
1001b
Data length=10
9
FRESET
FSM and FIFO Reset
6
8
write-only
00b
No effect
0
11b
Reset FSM and FIFO
3
LOOPBACK
Loopback mode enable
1
2
read-write
Disable
Disable loopback mode
0
Enable
Enable loopback mode
1
MS
Master/Slave selection
3
4
read-write
Master
Act as Master
0
Slave
Act as Slave
1
RXFIFOTH
RX FIFO Threshold level
15
18
read-write
0
RX FIFO threshold level is 0
0
1
RX FIFO threshold level is 1
1
2
RX FIFO threshold level is 2
2
3
RX FIFO threshold level is 3
3
4
RX FIFO threshold level is 4
4
5
RX FIFO threshold level is 5
5
6
RX FIFO threshold level is 6
6
7
RX FIFO threshold level is 7
7
SDODIS
Slave data out disable
2
3
read-write
Enable
Enable slave data out
0
Disble
Diable slave data out (MISO=0)
1
SELDIS
Auto-SEL disable bit
18
19
read-write
Enable
Enable Auto-SEL flow control
0
Disable
Disable Auto-SEL flow control
1
SPIEN
SPI enable
0
1
read-write
Disable
Disable SPI
0
Enable
Enable SPI
1
TXFIFOTH
TX FIFO Threshold level
12
15
read-write
0
TX FIFO threshold level is 0
0
1
TX FIFO threshold level is 1
1
2
TX FIFO threshold level is 2
2
3
TX FIFO threshold level is 3
3
4
TX FIFO threshold level is 4
4
5
TX FIFO threshold level is 5
5
6
TX FIFO threshold level is 6
6
7
TX FIFO threshold level is 7
7
CTRL1
Offset:0x04 SPIn Control Register 1
0x4
32
read-write
n
0x0
0x0
CPHA
Clock phase of edge sampling
2
3
read-write
CPHA0
The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data
0
CPHA1
SCK 1st edge is for data transition, and receive/transmit data at 2nd edge
1
CPOL
Clock priority selection
1
2
read-write
Low
SCK idles at low level
0
High
SCK idles at high level
1
MLSB
MSB/LSB seletion
0
1
read-write
MSB
MSB transmit first
0
LSB
LSB transmit first
1
DATA
Offset:0x1C SPIn Data Register
0x1C
32
read-write
n
0x0
0x0
Data
Data
0
16
read-write
DF
Offset:0x20 SPIn Data Fetch Register
0x20
32
read-write
n
0x0
0x0
DF
SPI data fetch control bit
0
1
read-write
Disable
Disable
0
Enable
Enable when SCKn frequency is higher than 6MHz
1
IC
Offset:0x18 SPIn Interrupt Clear Register
0x18
32
write-only
n
0x0
0x0
RXFIFOTHIC
RX Interrupt flag Clear
2
3
write-only
No effect
No effect
0
Clear
Clear RXFIFOTH flag
1
RXOVFIC
RX FIFO overflow flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear RXOVF flag
1
RXTOIC
RX time-out interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear RXTO flag
1
TXFIFOTHIC
TX Interrupt flag Clear
3
4
write-only
No effect
No effect
0
Clear
Clear TXFIFOTH flag
1
IE
Offset:0x10 SPIn Interrupt Enable Register
0x10
32
read-write
n
0x0
0x0
RXFIFOTHIE
RX FIFO threshold interrupt enable
2
3
read-write
Disable
Disable RX FIFO threshold interrupt
0
Enable
Enable RX FIFO threshold interrupt
1
RXOVFIE
RX FIFO overflow interrupt enable
0
1
read-write
Disable
Disable RX FIFO overflow interrupt
0
Enable
Enable RX FIFO overflow interrupt
1
RXTOIE
RX time-out interrupt enable
1
2
read-write
Disable
Disable RX time-out interrupt
0
Enable
Enable RX time-out interrupt
1
TXFIFOTHIE
TX FIFO threshold interrupt enable
3
4
read-write
Disable
Disable TX FIFO threshold interrupt
0
Enable
Enable TX FIFO threshold interrupt
1
RIS
Offset:0x14 SPIn Raw Interrupt Status Register
0x14
32
read-only
n
0x0
0x0
RXFIFOTHIF
RX FIFO threshold interrupt flag
2
3
read-only
No RXFIFOTH interrupt
No RXFIFOTH interrupt
0
Met RXFIFOTH interrupt requirements
RX FIFO threshold is triggered when RXFIFOTHIE=1
1
RXOVFIF
RX FIFO overflow interrupt flag
0
1
read-only
No RXOVF interrupt
No RXOVF interrupt
0
Met RXOVF interrupt requirements
RXOVF interrupt is triggered when RXOVFIE=1
1
RXTOIF
RX time-out interrupt flag
1
2
read-only
No RXTO interrupt
No RXTO interrupt
0
Met RXTO interrupt requirements
RXTO interrupt is triggered when RXTOIE=1
1
TXFIFOTHIF
TX FIFO threshold interrupt flag
3
4
read-only
No TXFIFOTH interrupt
No TXFIFOTH interrupt
0
Met TXFIFOTH interrupt requirements
TX FIFO threshold is triggered when TXFIFOTHIE=1
1
STAT
Offset:0x0C SPIn Status Register
0xC
32
read-only
n
0x0
0x0
BUSY
Busy flag
4
5
read-only
Idle
SPIn is idle
0
Busy
SPIn is transfering
1
RXFIFOTHF
RX FIFO threshold flag
6
7
read-only
0
Data count in RX FIFO is less equal than RXFIFOTH
0
1
Data count in RX FIFO is larger than RXFIFOTH
1
RX_EMPTY
RX FIFO empty flag
2
3
read-only
0
RX FIFO is not empty
0
1
RX FIFO is empty
1
RX_FULL
RX FIFO full flag
3
4
read-only
0
RX FIFO is not full
0
1
RX FIFO is full
1
TXFIFOTHF
TX FIFO threshold flag
5
6
read-only
0
Data count in TX FIFO is larger than TXFIFOTH
0
1
Data count in TX FIFO is less equal than TXFIFOTH
1
TX_EMPTY
TX FIFO empty flag
0
1
read-only
0
TX FIFO is not empty
0
1
TX FIFO is empty
1
TX_FULL
TX FIFO full flag
1
2
read-only
0
TX FIFO is not full
0
1
TX FIFO is full
1
SN_SYS0
System Control Registers
SYSTEM
0x0
0x0
0x2000
registers
n
NDT
NDT interrupt
0
LVD
LVD interrupt
26
AHBCP
Offset:0x10 AHB Clock Prescale Register
0x10
32
read-write
n
0x0
0x0
AHBPRE
AHB clock source prescaler
0
3
read-write
000b
FAHB=FSYSCLK/1
0
001b
FAHB=FSYSCLK/2
1
010b
FAHB=FSYSCLK/4
2
011b
FAHB=FSYSCLK/8
3
100b
FAHB=FSYSCLK/16
4
101b
FAHB=FSYSCLK/32
5
110b
FAHB=FSYSCLK/64
6
111b
FAHB=FSYSCLK/128
7
ANBCTRL
Offset:0x00 Analog Block Control Register
0x0
32
read-write
n
0x0
0x0
EHSEN
EHS XTAL enable
4
5
read-write
Disable
Disable EHS Xtal
0
Enable
Enable EHS Xtal
1
EHSFREQ
EHS XTAL frequency range
5
6
read-write
Low
Less equal than 8MHz
0
High
Greater than 8MHz
1
ELSEN
ELS XTAL enable
2
3
read-write
Disable
Disable ELS Xtal
0
Enable
Enable ELS Xtal
1
IHRCEN
IHRC enable
0
1
read-write
Disable
Disable IHRC
0
Enable
Enable IHRC
1
CLKCFG
Offset:0x0C System Clock Configuration Register
0xC
32
read-write
n
0x0
0x0
SYSCLKSEL
System clock source selection
0
3
read-write
IHRC
HCLK=IHRC
0
ILRC
HCLK=ILRC
1
EHS XTAL
HCLK=EHS XTAL
2
ELS XTAL
HCLK=ELS XTAL
3
PLL Output
HCLK=PLL output
4
SYSCLKST
System clock switch status
4
7
read-only
IHRC
IHRC is used as system clock
0
ILRC
ILRC is used as system clock
1
EHS XTAL
EHS XTAL is used as system clock
2
ELS XTAL
ELS XTAL is used as system clock
3
PLL
PLL output is used as system clock
4
CSST
Offset:0x08 Clock Source Status Register
0x8
32
read-only
n
0x0
0x0
EHSRDY
EHS XTAL ready flag
4
5
read-only
0
EHS Xtal is Not Ready
0
1
EHS Xtal is Ready
1
ELSRDY
ELS XTAL ready flag
2
3
read-only
0
ELS Xtal is Not Ready
0
1
ELS Xtal is Ready
1
IHRCRDY
IHRC ready flag
0
1
read-only
0
IHRC is Not Ready
0
1
IHRC is Ready
1
PLLRDY
PLL ready flag
6
7
read-only
0
PLL is Not locked
0
1
PLL is locked
1
EXRSTCTRL
Offset:0x1C External Reset Pin Control Register
0x1C
32
read-write
n
0x0
0x0
RESETDIS
External reset pin disable
0
1
read-write
Enable
P3.6 acts as External Reset pin
0
Disable
P3.6 acts as GPIO pin
1
LVDCTRL
Offset:0x18 LVD Control Register
0x18
32
read-write
n
0x0
0x0
LVDEN
LVD enable
15
16
read-write
Diable
Disable LVD
0
Enable
Enable LVD
1
LVDINTLVL
LVD interrupt level
4
7
read-write
1.80V
LVD interrupt threshold is 1.80V
0
2.00V
LVD interrupt threshold is 2.00V
1
2.40V
LVD interrupt threshold is 2.40V
2
2.70V
LVD interrupt threshold is 2.70V
3
3.00V
LVD interrupt threshold is 3.00V
4
3.60V
LVD interrupt threshold is 3.60V
5
LVDRSTEN
LVD Reset enable
14
15
read-write
Diable
Disable LVD reset
0
Enable
Enable LVD reset
1
LVDRSTLVL
LVD reset level
0
3
read-write
1.80V
LVD reset threshold is 1.80V
0
2.00V
LVD reset threshold is 2.00V
1
2.40V
LVD reset threshold is 2.40V
2
2.70V
LVD reset threshold is 2.70V
3
3.00V
LVD reset threshold is 3.00V
4
3.60V
LVD reset threshold is 3.60V
5
PLLCTRL
Offset:0x04 PLL Control Register
0x4
32
read-write
n
0x0
0x0
MSEL
M value
0
3
read-write
000b
M=4
0
001b
M=6
1
010b
M=8
2
011b
M=10
3
100b
M=12
4
PLLCLKSEL
PLL clock source
12
13
read-write
IHRC
12MHz
0
EHS XTAL
10MHz~16MHz
1
PLLEN
PLL enable
15
16
read-write
Disable
Disable PLL
0
Enable
Enable PLL
1
PSEL
P value
5
6
read-write
0
P=2
0
1
P=4
1
RSTST
Offset:0x14 System Reset Status Register
0x14
32
read-write
n
0x0
0x0
EXTRSTF
External reset flag
3
4
read-write
0
No Extenral reset occurred
0
1
External reset occurred
1
LVDRSTF
LVD reset flag
2
3
read-write
0
No LVD reset occurred
0
1
LVD reset occurred
1
PORRSTF
POR reset flag
4
5
read-write
0
No POR occurred
0
1
POR occurred
1
SWRSTF
Software reset flag
0
1
read-write
0
No SW reset occurred
0
1
SW reset occurred
1
WDTRSTF
WDT reset flag
1
2
read-write
0
No WDT reset occurred
0
1
WDT reset occurred
1
SWDCTRL
Offset:0x20 SWD Pin Control Register
0x20
32
read-write
n
0x0
0x0
SWDDIS
SWD pin disable
0
1
read-write
Enable
Enable SWD pins
0
Disable
Disable SWD pins
1
SN_SYS1
System Control Registers
SYSTEM
0x0
0x0
0x2000
registers
n
AHBCLKEN
Offset:0x00 AHB Clock Enable Register
0x0
32
read-write
n
0x0
0x0
ADCCLKEN
Enable AHB clock for ADC
11
12
read-write
Disable
Disable
0
Enable
Enable
1
CLKOUTSEL
Clock output source selection
28
31
read-write
000b
Disable
0
001b
ILRC
1
010b
ELS XTAL
2
100b
HCLK
4
101b
IHRC
5
110b
EHS XTAL
6
111b
PLL output
7
CMPCLKEN
Enable AHB clock for CMP
14
15
read-write
Disable
Disable
0
Enable
Enable
1
CT16B0CLKEN
Enable AHB clock for CT16B0
6
7
read-write
Disable
Disable
0
Enable
Enable
1
CT16B1CLKEN
Enable AHB clock for CT16B1
7
8
read-write
Disable
Disable
0
Enable
Enable
1
CT16B2CLKEN
Enable AHB clock for CT16B2
10
11
read-write
Disable
Disable
0
Enable
Enable
1
I2C0CLKEN
Enable AHB clock for I2C0
21
22
read-write
Disable
Disable
0
Enable
Enable
1
P0CLKEN
Enable AHB clock for P0
0
1
read-write
Disable
Disable
0
Enable
Enable
1
P1CLKEN
Enable AHB clock for P1
1
2
read-write
Disable
Disable
0
Enable
Enable
1
P2CLKEN
Enable AHB clock for P2
2
3
read-write
Disable
Disable
0
Enable
Enable
1
P3CLKEN
Enable AHB clock for P3
3
4
read-write
Disable
Disable
0
Enable
Enable
1
RTCCLKEN
Enable AHB clock for RTC
23
24
read-write
Disable
Disable
0
Enable
Enable
1
SPI0CLKEN
Enable AHB clock for SPI0
12
13
read-write
Disable
Disable
0
Enable
Enable
1
UART0CLKEN
Enable AHB clock for UART0
16
17
read-write
Disable
Disable
0
Enable
Enable
1
UART1CLKEN
Enable AHB clock for UART1
17
18
read-write
Disable
Disable
0
Enable
Enable
1
WDTCLKEN
Enable AHB clock for WDT
24
25
read-write
Disable
Disable
0
Enable
Enable
1
APBCP0
Offset:0x04 APB Clock Prescale Register 0
0x4
32
read-write
n
0x0
0x0
ADCPRE
ADC APB clock source prescaler
16
19
read-write
000b
HCLK/1
0
001b
HCLK/2
1
010b
HCLK/4
2
011b
HCLK/8
3
100b
HCLK/16
4
APBCP1
Offset:0x08 APB Clock Prescale Register 1
0x8
32
read-write
n
0x0
0x0
CLKOUTPRE
CLKOUT APB clock source prescaler
28
31
read-write
000b
FCLKOUT/1
0
001b
FCLKOUT/2
1
010b
FCLKOUT/4
2
011b
FCLKOUT/8
3
100b
FCLKOUT/16
4
101b
FCLKOUT/32
5
110b
FCLKOUT/64
6
111b
FCLKOUT/128
7
WDTPRE
WDT APB clock source prescaler
20
23
read-write
000b
WDT_PCLK = WDT clock source / 1
0
001b
WDT_PCLK = WDT clock source / 2
1
010b
WDT_PCLK = WDT clock source / 4
2
011b
WDT_PCLK = WDT clock source / 8
3
100b
WDT_PCLK = WDT clock source / 16
4
101b
WDT_PCLK = WDT clock source / 32
5
SN_UART0
UART0
UART
0x0
0x0
0x2000
registers
n
UART0
21
ABCTRL
Offset:0x20 UARTn Auto-baud Control Register
0x20
32
read-write
n
0x0
0x0
ABEOIFC
Clear ABEOIF flag
8
9
write-only
No effect
No effect
0
Clear
Clear ABEOIF bit
1
ABTOIFC
Clear ABTOIF flag
9
10
write-only
No effect
No effect
0
Clear
Clear ABTOIF bit
1
AUTORESTART
Restart mode selection
2
3
read-write
No restart
No restart
0
Restart
Auto restart in case of timeout
1
MODE
Auto-baud mode selection
1
2
read-write
Mode 0
Auto-baud mode 0
0
Mode 1
Auto-baud mode 1
1
START
Auto-baud run bit
0
1
read-write
Stop
Auto-baud is not running
0
Start
Auto-baud ids running
1
CTRL
Offset:0x30 UARTn Control Register
0x30
32
read-write
n
0x0
0x0
MODE
UART mode
1
4
read-write
0
UART mode
0
RXEN
RX enable
6
7
read-write
Disable
Disable RX
0
Enable
Enable RX
1
TXEN
TX enable
7
8
read-write
Disable
Disable TX
0
Enable
Enable TX
1
UARTEN
USART enable
0
1
read-write
Disable
Disable UART
0
Enable
Enable UART
1
DLL
Offset:0x00 UARTn Divisor Latch LSB Register
RB
0x0
32
read-write
n
0x0
0x0
DLL
DLL and DLM register determines the baud rate of UARTn
0
8
read-write
DLM
Offset:0x04 UARTn Divisor Latch MSB Register
0x4
32
read-write
n
0x0
0x0
DLM
DLL and DLM register determines the baud rate of USARTn
0
8
read-write
FD
Offset:0x28 UARTn Fractional Divider Register
0x28
32
read-write
n
0x0
0x0
DIVADDVAL
Baud rate generation prescaler divisor value
0
4
read-write
MULVAL
Baud rate generation prescaler multiplier value
4
8
read-write
0000b
Baud rate prescaler multiplier value is 1
0
0001b
Baud rate prescaler multiplier value is 2
1
1010b
Baud rate prescaler multiplier value is 11
10
1011b
Baud rate prescaler multiplier value is 12
11
1100b
Baud rate prescaler multiplier value is 13
12
1101b
Baud rate prescaler multiplier value is 14
13
1110b
Baud rate prescaler multiplier value is 15
14
1111b
Baud rate prescaler multiplier value is 16
15
0010b
Baud rate prescaler multiplier value is 3
2
0011b
Baud rate prescaler multiplier value is 4
3
0100b
Baud rate prescaler multiplier value is 5
4
0101b
Baud rate prescaler multiplier value is 6
5
0110b
Baud rate prescaler multiplier value is 7
6
0111b
Baud rate prescaler multiplier value is 8
7
1000b
Baud rate prescaler multiplier value is 9
8
1001b
Baud rate prescaler multiplier value is 10
9
OVER8
Oversampling value
8
9
read-write
16
Oversampling by 16
0
8
Oversampling by 8
1
FIFOCTRL
Offset:0x08 UARTn FIFO Control Register
0x8
32
write-only
n
0x0
0x0
FIFOEN
FIFO enable
0
1
write-only
No effect
No effect
0
Enable
Enable FIFO
1
RXTL
RX trigger level
6
8
write-only
Trigger level 0
1 character
0
HDEN
Offset:0x34 UARTn Control Register
0x34
32
read-write
n
0x0
0x0
HDEN
Half-duplex mode enable
0
1
read-write
Disable
Disable half-duplex mode
0
Enable
Enable half-duplex mode
1
IE
Offset:0x04 UARTn Interrupt Enable Register
DLM
0x4
32
read-write
n
0x0
0x0
ABEOIE
ABE0 interrupt enable
8
9
read-write
Disable
Disable ABEO interrupt
0
Enable
Enable ABEO interrupt
1
ABTOIE
ABT0 interrupt enable
9
10
read-write
Disable
Disable ABTO interrupt
0
Enable
Enable ABTO interrupt
1
RDAIE
RDA interrupt enable
0
1
read-write
Disable
Disable RDA interrupt
0
Enable
Enable RDA interrupt
1
RLSIE
RLS interrupt enable
2
3
read-write
Disable
Disable RLS interrupt
0
Enable
Enable RLS interrupt
1
TEMTIE
TEMT interrupt enable
4
5
read-write
Disable
Disable TEMT interrupt
0
Enable
Enable TEMT interrupt
1
THREIE
THRE interrupt enable
1
2
read-write
Disable
Disable THRE interrupt
0
Enable
Enable THRE interrupt
1
II
Offset:0x08 UARTn Interrupt Identification Register
0x8
32
read-only
n
0x0
0x0
ABEOIF
ABEO interrupt flag
8
9
read-only
Not end
Auto-baud has not finished
0
End
Auto-baud has finished and interrupt is enabled
1
ABTOIF
ABTO interrupt flag
9
10
read-only
Not Time-out
Auto-baud has not timed out
0
Time-out
Auto-baud has timed out and interrupt is enabled
1
FIFOEN
Equal to FIFOEN bits in USARTn_FIFOCTRL register
6
8
read-only
INTID
Interrupt ID of RX FIFO
1
4
read-only
3a
THRE interrupt
1
2a
RDA (Receive Data Available)
2
1
RLS (Receive Line Status)
3
3b
TEMT interrupt
7
INTSTATUS
Interrupt status
0
1
read-only
Pending
As least 1 interrupt is pending
0
No interrupt
No interrupt
1
LC
Offset:0x0C UARTn Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
Break control
6
7
read-write
Disable
Disable break transmission
0
Enable
Enable break transmission
1
DLAB
Divisor Latch access
7
8
read-write
Disable
Disable access to Divisor Latch
0
Enable
Enable access to Divisor Latch
1
PE
Parity enable
3
4
read-write
Disable
Disable parity generation and checking
0
Enable
Enable parity generation and checking
1
PS
Parity selection
4
6
read-write
0
Odd parity
0
1
Even parity
1
2
Forced 1 sticky parity
2
3
Forced 0 sticky parity
3
SBS
Stop bit selection
2
3
read-write
1 stop bit
1 stop bit
0
2 stop bit
2 stop bit (1.5 stop bit if WLS=0)
1
WLS
Word length selection
0
2
read-write
5-bit
5-bit character
0
6-bit
6-bit character
1
7-bit
7-bit character
2
8-bit
8-bit character
3
LS
Offset:0x14 UARTn Line Status Register
0x14
32
read-only
n
0x0
0x0
BI
Break interrupt flag
4
5
read-only
No break interrupt
No break interrupt
0
Break interrupt
Break interrupt status is active
1
FE
Framing error flag
3
4
read-only
No framing error
No framing error
0
Framing error
Framing error status is active
1
OE
Overrun error flag
1
2
read-only
No overrun error
No overrun error
0
Overrun error
Overrun error status is active
1
PE
Parity error flag
2
3
read-only
No parity error
No parity error
0
Parity error
Parity error status is active
1
RDR
Receiver data ready flag
0
1
read-only
Not ready
UARTn_RB FIFO is empty
0
Ready
UARTn_RB FIFO contains valid data
1
RXFE
Receiver FIFO error flag
7
8
read-only
No RX FIFO error
UARTn_RB contains no UART RX errors
0
RX FIFO error
UARTn_RB contains at least 1 UART RX error
1
TEMT
Transmitter empty flag
6
7
read-only
Not empty
THR and/or TSR contains valid data
0
Empty
THR and TSR are both empty
1
THRE
THR empty flag
5
6
read-only
Not empty
THR contains valid data
0
Empty
THR (TX FIFO) is empty
1
RB
Offset:0x00 UARTn Receiver Buffer Register
0x0
32
read-only
n
0x0
0x0
RB
The received byte in UART RX FIFO
0
8
read-only
SP
Offset:0x1C UARTn Scratch Pad Register
0x1C
32
read-write
n
0x0
0x0
PAD
Pad informaton
0
8
read-write
TH
Offset:0x00 UARTn Transmit Holding Register
RB
0x0
32
read-write
n
0x0
0x0
TH
The byte to be transmitted in UART TX FIFO when transmitter is available
0
8
write-only
SN_UART1
UART0
UART
0x0
0x0
0x2000
registers
n
UART1
22
ABCTRL
Offset:0x20 UARTn Auto-baud Control Register
0x20
32
read-write
n
0x0
0x0
ABEOIFC
Clear ABEOIF flag
8
9
write-only
No effect
No effect
0
Clear
Clear ABEOIF bit
1
ABTOIFC
Clear ABTOIF flag
9
10
write-only
No effect
No effect
0
Clear
Clear ABTOIF bit
1
AUTORESTART
Restart mode selection
2
3
read-write
No restart
No restart
0
Restart
Auto restart in case of timeout
1
MODE
Auto-baud mode selection
1
2
read-write
Mode 0
Auto-baud mode 0
0
Mode 1
Auto-baud mode 1
1
START
Auto-baud run bit
0
1
read-write
Stop
Auto-baud is not running
0
Start
Auto-baud ids running
1
CTRL
Offset:0x30 UARTn Control Register
0x30
32
read-write
n
0x0
0x0
MODE
UART mode
1
4
read-write
0
UART mode
0
RXEN
RX enable
6
7
read-write
Disable
Disable RX
0
Enable
Enable RX
1
TXEN
TX enable
7
8
read-write
Disable
Disable TX
0
Enable
Enable TX
1
UARTEN
USART enable
0
1
read-write
Disable
Disable UART
0
Enable
Enable UART
1
DLL
Offset:0x00 UARTn Divisor Latch LSB Register
RB
0x0
32
read-write
n
0x0
0x0
DLL
DLL and DLM register determines the baud rate of UARTn
0
8
read-write
DLM
Offset:0x04 UARTn Divisor Latch MSB Register
0x4
32
read-write
n
0x0
0x0
DLM
DLL and DLM register determines the baud rate of USARTn
0
8
read-write
FD
Offset:0x28 UARTn Fractional Divider Register
0x28
32
read-write
n
0x0
0x0
DIVADDVAL
Baud rate generation prescaler divisor value
0
4
read-write
MULVAL
Baud rate generation prescaler multiplier value
4
8
read-write
0000b
Baud rate prescaler multiplier value is 1
0
0001b
Baud rate prescaler multiplier value is 2
1
1010b
Baud rate prescaler multiplier value is 11
10
1011b
Baud rate prescaler multiplier value is 12
11
1100b
Baud rate prescaler multiplier value is 13
12
1101b
Baud rate prescaler multiplier value is 14
13
1110b
Baud rate prescaler multiplier value is 15
14
1111b
Baud rate prescaler multiplier value is 16
15
0010b
Baud rate prescaler multiplier value is 3
2
0011b
Baud rate prescaler multiplier value is 4
3
0100b
Baud rate prescaler multiplier value is 5
4
0101b
Baud rate prescaler multiplier value is 6
5
0110b
Baud rate prescaler multiplier value is 7
6
0111b
Baud rate prescaler multiplier value is 8
7
1000b
Baud rate prescaler multiplier value is 9
8
1001b
Baud rate prescaler multiplier value is 10
9
OVER8
Oversampling value
8
9
read-write
16
Oversampling by 16
0
8
Oversampling by 8
1
FIFOCTRL
Offset:0x08 UARTn FIFO Control Register
0x8
32
write-only
n
0x0
0x0
FIFOEN
FIFO enable
0
1
write-only
No effect
No effect
0
Enable
Enable FIFO
1
RXTL
RX trigger level
6
8
write-only
Trigger level 0
1 character
0
HDEN
Offset:0x34 UARTn Control Register
0x34
32
read-write
n
0x0
0x0
HDEN
Half-duplex mode enable
0
1
read-write
Disable
Disable half-duplex mode
0
Enable
Enable half-duplex mode
1
IE
Offset:0x04 UARTn Interrupt Enable Register
DLM
0x4
32
read-write
n
0x0
0x0
ABEOIE
ABE0 interrupt enable
8
9
read-write
Disable
Disable ABEO interrupt
0
Enable
Enable ABEO interrupt
1
ABTOIE
ABT0 interrupt enable
9
10
read-write
Disable
Disable ABTO interrupt
0
Enable
Enable ABTO interrupt
1
RDAIE
RDA interrupt enable
0
1
read-write
Disable
Disable RDA interrupt
0
Enable
Enable RDA interrupt
1
RLSIE
RLS interrupt enable
2
3
read-write
Disable
Disable RLS interrupt
0
Enable
Enable RLS interrupt
1
TEMTIE
TEMT interrupt enable
4
5
read-write
Disable
Disable TEMT interrupt
0
Enable
Enable TEMT interrupt
1
THREIE
THRE interrupt enable
1
2
read-write
Disable
Disable THRE interrupt
0
Enable
Enable THRE interrupt
1
II
Offset:0x08 UARTn Interrupt Identification Register
0x8
32
read-only
n
0x0
0x0
ABEOIF
ABEO interrupt flag
8
9
read-only
Not end
Auto-baud has not finished
0
End
Auto-baud has finished and interrupt is enabled
1
ABTOIF
ABTO interrupt flag
9
10
read-only
Not Time-out
Auto-baud has not timed out
0
Time-out
Auto-baud has timed out and interrupt is enabled
1
FIFOEN
Equal to FIFOEN bits in USARTn_FIFOCTRL register
6
8
read-only
INTID
Interrupt ID of RX FIFO
1
4
read-only
3a
THRE interrupt
1
2a
RDA (Receive Data Available)
2
1
RLS (Receive Line Status)
3
3b
TEMT interrupt
7
INTSTATUS
Interrupt status
0
1
read-only
Pending
As least 1 interrupt is pending
0
No interrupt
No interrupt
1
LC
Offset:0x0C UARTn Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
Break control
6
7
read-write
Disable
Disable break transmission
0
Enable
Enable break transmission
1
DLAB
Divisor Latch access
7
8
read-write
Disable
Disable access to Divisor Latch
0
Enable
Enable access to Divisor Latch
1
PE
Parity enable
3
4
read-write
Disable
Disable parity generation and checking
0
Enable
Enable parity generation and checking
1
PS
Parity selection
4
6
read-write
0
Odd parity
0
1
Even parity
1
2
Forced 1 sticky parity
2
3
Forced 0 sticky parity
3
SBS
Stop bit selection
2
3
read-write
1 stop bit
1 stop bit
0
2 stop bit
2 stop bit (1.5 stop bit if WLS=0)
1
WLS
Word length selection
0
2
read-write
5-bit
5-bit character
0
6-bit
6-bit character
1
7-bit
7-bit character
2
8-bit
8-bit character
3
LS
Offset:0x14 UARTn Line Status Register
0x14
32
read-only
n
0x0
0x0
BI
Break interrupt flag
4
5
read-only
No break interrupt
No break interrupt
0
Break interrupt
Break interrupt status is active
1
FE
Framing error flag
3
4
read-only
No framing error
No framing error
0
Framing error
Framing error status is active
1
OE
Overrun error flag
1
2
read-only
No overrun error
No overrun error
0
Overrun error
Overrun error status is active
1
PE
Parity error flag
2
3
read-only
No parity error
No parity error
0
Parity error
Parity error status is active
1
RDR
Receiver data ready flag
0
1
read-only
Not ready
UARTn_RB FIFO is empty
0
Ready
UARTn_RB FIFO contains valid data
1
RXFE
Receiver FIFO error flag
7
8
read-only
No RX FIFO error
UARTn_RB contains no UART RX errors
0
RX FIFO error
UARTn_RB contains at least 1 UART RX error
1
TEMT
Transmitter empty flag
6
7
read-only
Not empty
THR and/or TSR contains valid data
0
Empty
THR and TSR are both empty
1
THRE
THR empty flag
5
6
read-only
Not empty
THR contains valid data
0
Empty
THR (TX FIFO) is empty
1
RB
Offset:0x00 UARTn Receiver Buffer Register
0x0
32
read-only
n
0x0
0x0
RB
The received byte in UART RX FIFO
0
8
read-only
SP
Offset:0x1C UARTn Scratch Pad Register
0x1C
32
read-write
n
0x0
0x0
PAD
Pad informaton
0
8
read-write
TH
Offset:0x00 UARTn Transmit Holding Register
RB
0x0
32
read-write
n
0x0
0x0
TH
The byte to be transmitted in UART TX FIFO when transmitter is available
0
8
write-only
SN_UC
UC Registers
UC
0x0
0x0
0x2000
registers
n
H4BYTE
Offset:0x04 UC High 4 Byte Register
0x4
32
read-only
n
0x0
0x0
L4BYTE
Offset:0x00 UC Low 4 Byte Register
0x0
32
read-only
n
0x0
0x0
SN_WDT
Watchdog Timer
WDT
0x0
0x0
0x2000
registers
n
WDT
25
CFG
Offset:0x00 WDT Configuration Register
0x0
32
read-write
n
0x0
0x0
WDKEY
WDT register key
16
32
write-only
WDTEN
WDT enable
0
1
read-write
Disable
Disable WDT
0
Enable
Enable WDT
1
WDTIE
WDT interrupt enable
1
2
read-write
Disable
WDT reset when WDT time-out
0
Enable
Enable WDT interrupt
1
WDTINT
WDT interrupt flag
2
3
read-write
No
No WDT time-out
0
WDT time-out
WDT interrupt is triggered if WDTIE=1
1
CLKSOURCE
Offset:0x04 WDT Clock Source Register
0x4
32
read-write
n
0x0
0x0
CLKSEL
WDT clock source
0
2
read-write
ILRC
WDT clock source=ILRC
2
ELS XTAL
WDT clock source=ELS XTAL
3
WDKEY
WDT register key
16
32
write-only
FEED
Offset:0x0C WDT Feed Register
0xC
32
write-only
n
0x0
0x0
FV
Watchdog feed value
0
16
write-only
WDKEY
WDT register key
16
32
write-only
TC
Offset:0x08 WDT Timer Constant Register
0x8
32
read-write
n
0x0
0x0
TC
Watchdog timer constant reload value
0
8
read-write
WDKEY
WDT register key
16
32
write-only