SONIX
SN32F780
2024.04.19
ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 72MHz, etc.
CM0
r0p0
little
2
false
8
32
SN_ADC
ADC
ADC
0x0
0x0
0x2000
registers
n
ADC
ADC
24
ADB
Offset:0x04 ADC Data Register
0x4
32
read-only
n
0x0
0x0
ADB
ADB11~ADB4 bits for 8-bit ADC, ADB11~ADB0 bits for 12-bit ADC
0
12
read-only
ADM
Offset:0x00 ADC Management Register
0x0
32
read-write
n
0x0
0x0
ADCKS
ADC clock source divider
9
12
read-write
000b
ADC_PCLK/1
0
001b
ADC_PCLK/2
1
010b
ADC_PCLK/4
2
011b
ADC_PCLK/8
3
101b
ADC_PCLK/16
5
110b
ADC_PCLK/32
6
ADENB
ADC enable
12
13
read-write
Disable
Disable ADC
0
Enable
Enable ADC
1
ADLEN
ADC resolution
8
9
read-write
8-bit
8-bit ADB
0
12-bit
12-bit ADB
1
ADS
ADC start control
7
8
read-write
Stop
ADC stopped
0
Start
Start ADC conversion
1
AVREFHSEL
ADC high reference voltage source
13
14
read-write
Interal VDD
P2.0 acts as GPIO or AIN0 pin
0
External reference voltage
P2.0 acts as AVREFH pin
1
CHS
ADC input channel
0
5
read-write
0
AIN0
0
1
AIN1
1
10
AIN10
10
11
AIN11
11
12
AIN12
12
13
AIN13
13
14
AIN14
14
15
AIN15
15
16
AIN16(Internal reference voltage 4.5V/3V/2V)
16
17
AIN17(OP0O)
17
18
AIN18(OP1O)
18
2
AIN2
2
3
AIN3
3
4
AIN4
4
5
AIN5
5
6
AIN6
6
7
AIN7
7
8
AIN8
8
9
AIN9
9
EOC
ADC status
6
7
read-write
Busy
ADC processing
0
End
End of conversion
1
GCHS
ADC global channel enable
5
6
read-write
Disable
Disable AIN channel
0
Enable
Enable AIN channel
1
VHS
Internal Ref. voltage source
14
17
read-write
000b
Internal 2.0V as ADC internal reference high voltage
0
001b
Internal 3.0V as ADC internal reference high voltage
1
010b
Internal 4.5V as ADC internal reference high voltage
2
100b
VDD as ADC internal reference high voltage, Internal 2.0V as AIN10
4
101b
VDD as ADC internal reference high voltage, Internal 3.0V as AIN10
5
110b
VDD as ADC internal reference high voltage, Internal 4.5V as AIN10
6
111b
VDD as ADC internal reference high voltage
7
CALI
Offset:0x14 ADC Calibration Register
0x14
32
read-write
n
0x0
0x0
IE
Offset:0x0C ADC Interrupt Enable Register
0xC
32
read-write
n
0x0
0x0
IE0
AIN0 interrupt enable
0
1
read-write
Disable
Disable AIN0 interrupt
0
Enable
ADC interrupt is triggered when AIN0 completes ADC conversion
1
IE1
AIN1 interrupt enable
1
2
read-write
Disable
Disable AIN1 interrupt
0
Enable
ADC interrupt is triggered when AIN1 completes ADC conversion
1
IE10
AIN10 interrupt enable
10
11
read-write
Disable
Disable AIN10 interrupt
0
Enable
ADC interrupt is triggered when AIN10 completes ADC conversion
1
IE11
AIN11 interrupt enable
11
12
read-write
Disable
Disable AIN11 interrupt
0
Enable
ADC interrupt is triggered when AIN11 completes ADC conversion
1
IE12
AIN12 interrupt enable
12
13
read-write
Disable
Disable AIN12 interrupt
0
Enable
ADC interrupt is triggered when AIN12 completes ADC conversion
1
IE13
AIN13 interrupt enable
13
14
read-write
Disable
Disable AIN13 interrupt
0
Enable
ADC interrupt is triggered when AIN13 completes ADC conversion
1
IE14
AIN14 interrupt enable
14
15
read-write
Disable
Disable AIN14 interrupt
0
Enable
ADC interrupt is triggered when AIN14 completes ADC conversion
1
IE15
AIN15 interrupt enable
15
16
read-write
Disable
Disable AIN15 interrupt
0
Enable
ADC interrupt is triggered when AIN15 completes ADC conversion
1
IE16
AIN16 interrupt enable
16
17
read-write
Disable
Disable AIN16 interrupt
0
Enable
ADC interrupt is triggered when AIN16 completes ADC conversion
1
IE17
AIN17 interrupt enable
17
18
read-write
Disable
Disable AIN17 interrupt
0
Enable
ADC interrupt is triggered when AIN17 completes ADC conversion
1
IE18
AIN18 interrupt enable
18
19
read-write
Disable
Disable AIN18 interrupt
0
Enable
ADC interrupt is triggered when AIN18 completes ADC conversion
1
IE2
AIN2 interrupt enable
2
3
read-write
Disable
Disable AIN2 interrupt
0
Enable
ADC interrupt is triggered when AIN2 completes ADC conversion
1
IE3
AIN3 interrupt enable
3
4
read-write
Disable
Disable AIN3 interrupt
0
Enable
ADC interrupt is triggered when AIN3 completes ADC conversion
1
IE4
AIN4 interrupt enable
4
5
read-write
Disable
Disable AIN4 interrupt
0
Enable
ADC interrupt is triggered when AIN4 completes ADC conversion
1
IE5
AIN5 interrupt enable
5
6
read-write
Disable
Disable AIN5 interrupt
0
Enable
ADC interrupt is triggered when AIN5 completes ADC conversion
1
IE6
AIN6 interrupt enable
6
7
read-write
Disable
Disable AIN6 interrupt
0
Enable
ADC interrupt is triggered when AIN6 completes ADC conversion
1
IE7
AIN7 interrupt enable
7
8
read-write
Disable
Disable AIN7 interrupt
0
Enable
ADC interrupt is triggered when AIN7 completes ADC conversion
1
IE8
AIN8 interrupt enable
8
9
read-write
Disable
Disable AIN8 interrupt
0
Enable
ADC interrupt is triggered when AIN8 completes ADC conversion
1
IE9
AIN9 interrupt enable
9
10
read-write
Disable
Disable AIN9 interrupt
0
Enable
ADC interrupt is triggered when AIN9 completes ADC conversion
1
RIS
Offset:0x10 ADC Raw Interrupt Status Register
0x10
32
read-write
n
0x0
0x0
EOCIF0
AIN0 interrupt flag
0
1
read-write
No interrupt
No interrupt on AIN0
0
Met interrupt requirements
AIN0 completes ADC conversion
1
EOCIF1
AIN1 interrupt flag
1
2
read-write
No interrupt
No interrupt on AIN1
0
Met interrupt requirements
AIN1 completes ADC conversion
1
EOCIF10
AIN10 interrupt flag
10
11
read-write
No interrupt
No interrupt on AIN10
0
Met interrupt requirements
AIN10 completes ADC conversion
1
EOCIF11
AIN11 interrupt flag
11
12
read-write
No interrupt
No interrupt on AIN11
0
Met interrupt requirements
AIN11 completes ADC conversion
1
EOCIF12
AIN12 interrupt flag
12
13
read-write
No interrupt
No interrupt on AIN12
0
Met interrupt requirements
AIN12 completes ADC conversion
1
EOCIF13
AIN13 interrupt flag
13
14
read-write
No interrupt
No interrupt on AIN13
0
Met interrupt requirements
AIN13 completes ADC conversion
1
EOCIF14
AIN14 interrupt flag
14
15
read-write
No interrupt
No interrupt on AIN14
0
Met interrupt requirements
AIN14 completes ADC conversion
1
EOCIF15
AIN15 interrupt flag
15
16
read-write
No interrupt
No interrupt on AIN15
0
Met interrupt requirements
AIN15 completes ADC conversion
1
EOCIF16
AIN16 interrupt flag
16
17
read-write
No interrupt
No interrupt on AIN16
0
Met interrupt requirements
AIN16 completes ADC conversion
1
EOCIF17
AIN17 interrupt flag
17
18
read-write
No interrupt
No interrupt on AIN17
0
Met interrupt requirements
AIN17 completes ADC conversion
1
EOCIF18
AIN18 interrupt flag
18
19
read-write
No interrupt
No interrupt on AIN18
0
Met interrupt requirements
AIN18 completes ADC conversion
1
EOCIF2
AIN2 interrupt flag
2
3
read-write
No interrupt
No interrupt on AIN2
0
Met interrupt requirements
AIN2 completes ADC conversion
1
EOCIF3
AIN0 interrupt flag
3
4
read-write
No interrupt
No interrupt on AIN3
0
Met interrupt requirements
AIN3 completes ADC conversion
1
EOCIF4
AIN4 interrupt flag
4
5
read-write
No interrupt
No interrupt on AIN4
0
Met interrupt requirements
AIN4 completes ADC conversion
1
EOCIF5
AIN5 interrupt flag
5
6
read-write
No interrupt
No interrupt on AIN5
0
Met interrupt requirements
AIN5 completes ADC conversion
1
EOCIF6
AIN6 interrupt flag
6
7
read-write
No interrupt
No interrupt on AIN6
0
Met interrupt requirements
AIN6 completes ADC conversion
1
EOCIF7
AIN7 interrupt flag
7
8
read-write
No interrupt
No interrupt on AIN7
0
Met interrupt requirements
AIN7 completes ADC conversion
1
EOCIF8
AIN8 interrupt flag
8
9
read-write
No interrupt
No interrupt on AIN8
0
Met interrupt requirements
AIN8 completes ADC conversion
1
EOCIF9
AIN9 interrupt flag
9
10
read-write
No interrupt
No interrupt on AIN9
0
Met interrupt requirements
AIN9 completes ADC conversion
1
SN_CMP
Comparator
CMP
0x0
0x0
0x2000
registers
n
CMP3
CMP3
5
CMP2
CMP2
12
CMP1
CMP1
18
CMP0
CMP0
27
CSCNT
Offset:0x28 CMP CapSensing Counter Register
0x28
32
read-only
n
0x0
0x0
CSC
CSC 16-bit timer counter (CSC counter clock source is CS_PCLK)
16
32
read-only
CSV
CSV 16-bit event counter (CSV counter clock source is CS_4MHz)
0
16
read-only
CSCTRL
Offset:0x20 CMP Cap-sensing Control Register
0x20
32
read-write
n
0x0
0x0
CCAL
Cap Calibration parameter
20
24
read-write
0000b
0pF
0
0001b
0.2pF
1
1010b
2.0pF
10
1011b
2.2pF
11
1100b
2.4pF
12
1101b
2.6pF
13
1110b
2.8pF
14
1111b
3.0pF
15
0010b
0.4pF
2
0011b
0.6pF
3
0100b
0.8pF
4
0101b
1.0pF
5
0110b
1.2pF
6
0111b
1.4pF
7
1000b
1.6pF
8
1001b
1.8pF
9
CCAL4
Cap Calibration select bit
24
25
read-write
VSS
Cap Calibration circuit is connect to VSS
0
VDD
Cap Calibration circuit is connect to VDD
1
CHG
Cap-sensing charging time
15
18
read-write
000b
2us
0
001b
4us
1
010b
8us
2
011b
16us
3
100b
32us
4
101b
64us
5
110b
128us
6
111b
256us
7
CMP
Comparator reference control bits
11
14
read-write
000b
0.3083*VREG33
0
001b
0.3583*VREG33
1
010b
0.3917*VREG33
2
011b
0.4417*VREG33
3
100b
0.5083*VREG33
4
101b
0.5583*VREG33
5
110b
0.5917*VREG33
6
111b
0.6417*VREG33
7
CS1ST
Cap-sensing channel scan group start bit
2
3
read-write
Not New
Not group scan start
0
New
New group scan start
1
CSDIS
Channel discharge signl (CK_TCH) controll bit
26
27
read-write
Enable
Enable
0
Disable
Disable
1
CSEN
Cap-sensing module enable bit
0
1
read-write
Disable
Disable CS module
0
Enable
Enable CS module
1
CSFAPC
CSF active controll
30
31
read-write
Disable
CSF can be triggered any time
0
Enable
CSF can be triggered while CSS is high.
1
CSH
Cap-sensing channel
3
8
read-write
00000b
CT0
0
00001b
CT1
1
01010b
CT10
10
01011b
CT11
11
01100b
CT12
12
01101b
CT13
13
01110b
CT14
14
01111b
CT15
15
10000b
CT16
16
10001b
CT17
17
10010b
CT18
18
10011b
CT19
19
00010b
CT2
2
10100b
CT20
20
10101b
CT21
21
10110b
CT22
22
10111b
CT23
23
11000b
CT24 (Internal reference channel)
24
00011b
CT3
3
00100b
CT4
4
00101b
CT5
5
00110b
CT6
6
00111b
CT7
7
01000b
CT8
8
01001b
CT9
9
CSOUTEN
Cap-sening output pin enable bit
25
26
read-write
Disable
CSOUT pin is GPIO
0
Enable
CSOUT pin is Cap-sensing output pin
1
CSRDY
Cap-sensing module ready flag
31
32
read-only
Not Ready
Cap-sensing module are not ready
0
Ready
Cap-sensing module are ready
1
CSS
Cap-sensing operation start bit
1
2
read-write
Stop
Cap-sensing operation stops
0
Start
Cap-sensing operation starts
1
TNON
Non-overlap time
18
20
read-write
0
13ns
0
1
26ns
1
2
39ns
2
3
52ns
3
VDSEL
Cap-sensing voltage detects select bit
14
15
read-write
Reserved
Reserved
0
Comparator
Cap-sensing voltage is detected by Comparator
1
CSCTRL1
Offset:0x24 CMP Cap-sensing Control Register 1
0x24
32
read-write
n
0x0
0x0
CSCOV
CSC 16-bit timer counter overflow indicator (Clock source is CS_PCLK)
14
15
read-write
No
No overflow
0
Overflow
CSC[15:0] timer counter overflows
1
CSVCOV
CSV 16-bit event counter overflow indicator (Clock source is Cap-sensing 4MHz)
13
14
read-write
No
No overflow
0
Overflow
CSV[15:0] event counter overflows
1
OSCR
Ring OSC.4MHz clock range
8
13
read-write
00000b
4.096MHz
0
00001b
3.973MHz
1
01010b
4.427MHz
10
01011b
4.299MHz
11
01100b
3.808MHz
12
01101b
3.714MHz
13
01110b
3.715MHz
14
01111b
3.626MHz
15
10000b
5.157MHz
16
10001b
5.004MHz
17
10010b
5.004MHz
18
10011b
4.860MHz
19
00010b
3.973MHz
2
10100b
4.308MHz
20
10101b
4.203MHz
21
10110b
4.203MHz
22
10111b
4.103MHz
23
11000b
6.416MHz
24
11001b
6.227MHz
25
11010b
6.227MHz
26
11011b
6.051MHz
27
11100b
5.372MHz
28
11101b
5.243MHz
29
00011b
3.857MHz
3
11110b
5.243MHz
30
11111b
5.120MHz
31
00100b
3.414MHz
4
00101b
3.329MHz
5
00110b
3.330MHz
6
00111b
3.250MHz
7
01000b
4.564MHz
8
01001b
4.428MHz
9
SGFRQ
Spread Spectrum frequency
0
2
read-write
00b
4MHz
0
01b
2MHz
1
10b
1MHz
2
11b
0.5MHz
3
SGSEL
Cap-sensing 4MHz clock source and SSCG select bit
6
8
read-write
00b
4MHz IHRC and disable PRBS function
0
10b
4MHz Ring OSC. and disable PRBS function
2
CTRL
Offset:0x00 CMP Control Register
0x0
32
read-write
n
0x0
0x0
CM0EN
CMP0 Enable bit
0
1
read-write
Disable
Disable CMP0
0
Enable
Enable CMP0
1
CM0G
CMP0 interrupt trigger direction control bit
12
13
read-write
Falling range trigger
CMP0 output status is from high to low as VPREF0 less than CM0N
0
Rising edge trigger
CMP0 output status is from low to high as VPREF0 more than CM0N
1
CM0NS
CMP0 Negative input pin
3
5
read-write
CM0N0
CM0N0 is negative input pin
0
CM0N1
CM0N1 is negative input pin
1
CM0N2
CM0N2 is negative input pin
2
VIREF0
CM0N0/CM0N1/CM0N2 pins are GPIO mode
3
CM0OEN
CMP0 Output pin control bits
10
12
read-write
Disable
Disable CM0O
0
P2.0
P2.0 is CM0O and isolate GPIO function
1
P2.6
P2.6 is CM0O and isolate GPIO function
2
P3.3
P3.3 is CM0O and isolate GPIO function
3
CM0PS
CMP0 Positive input selection bits
1
3
read-write
No
CM0P0/CM0P1/CM0P2 pins are GPIO mode
0
CM0P0
CM0P0 is positive input pin
1
CM0P1
CM0P1 is positive input pin
2
CM0P2
CM0P2 is positive input pin
3
CM0RS
CMP0 internal reference voltage (VIREF0) selection bits
5
10
read-write
00000b
VIREF0=VIREF
0
00001b
VIREF0=VIREF*1/32
1
01010b
VIREF0=VIREF*10/32
10
01011b
VIREF0=VIREF*11/32
11
01100b
VIREF0=VIREF*12/32
12
01101b
VIREF0=VIREF*13/32
13
01110b
VIREF0=VIREF*14/32
14
01111b
VIREF0=VIREF*15/32
15
10000b
VIREF0=VIREF*16/32
16
10001b
VIREF0=VIREF*17/32
17
10010b
VIREF0=VIREF*18/32
18
10011b
VIREF0=VIREF*19/32
19
00010b
VIREF0=VIREF*2/32
2
10100b
VIREF0=VIREF*20/32
20
10101b
VIREF0=VIREF*21/32
21
10110b
VIREF0=VIREF*22/32
22
10111b
VIREF0=VIREF*23/32
23
11000b
VIREF0=VIREF*24/32
24
11001b
VIREF0=VIREF*25/32
25
11010b
VIREF0=VIREF*26/32
26
11011b
VIREF0=VIREF*27/32
27
11100b
VIREF0=VIREF*28/32
28
11101b
VIREF0=VIREF*29/32
29
00011b
VIREF0=VIREF*3/32
3
11110b
VIREF0=VIREF*30/32
30
11111b
VIREF0=VIREF*31/32
31
00100b
VIREF0=VIREF*4/32
4
00101b
VIREF0=VIREF*5/32
5
00110b
VIREF0=VIREF*6/32
6
00111b
VIREF0=VIREF*7/32
7
01000b
VIREF0=VIREF*8/32
8
01001b
VIREF0=VIREF*9/32
9
CM1EN
CMP1 Enable bit
16
17
read-write
Disable
Disable CMP1
0
Enable
Enable CMP1
1
CM1G
CMP1 interrupt trigger direction control bit
28
29
read-write
Falling range trigger
CMP1 output status is from high to low as VPREF1 less than CM1N
0
Rising edge trigger
CMP1 output status is from low to high as VPREF1 more than CM1N
1
CM1NS
CMP1 Negative input pin
19
21
read-write
CM1N0
CM1N0
0
CM1N1
CM1N1
1
CM1N2
CM1N2
2
VIREF1
CM1N0/CM1N1/CM1N2 pins are GPIO mode
3
CM1OEN
CMP1 Output pin control bits
26
28
read-write
Disable
Disable CM1O
0
P2.2
P2.2 is CM1O and isolate GPIO function
1
P2.7
P2.7 is CM1O and isolate GPIO function
2
P3.4
P3.4 is CM1O and isolate GPIO function
3
CM1PS
CMP1 Positive input selection bits
17
19
read-write
No
CM1P0/CM1P1/CM1P2 pins are GPIO mode
0
CM1P0
CM1P0 is positive input pin
1
CM1P1
CM1P1 is positive input pin
2
CM1P2
CM1P2 is positive input pin
3
CM1RS
CMP1 internal reference voltage (VIREF1) selection bits
21
26
read-write
00000b
VIREF1=VIREF
0
00001b
VIREF1=VIREF*1/32
1
01010b
VIREF1=VIREF*10/32
10
01011b
VIREF1=VIREF*11/32
11
01100b
VIREF1=VIREF*12/32
12
01101b
VIREF1=VIREF*13/32
13
01110b
VIREF1=VIREF*14/32
14
01111b
VIREF1=VIREF*15/32
15
10000b
VIREF1=VIREF*16/32
16
10001b
VIREF1=VIREF*17/32
17
10010b
VIREF1=VIREF*18/32
18
10011b
VIREF1=VIREF*19/32
19
00010b
VIREF1=VIREF*2/32
2
10100b
VIREF1=VIREF*20/32
20
10101b
VIREF1=VIREF*21/32
21
10110b
VIREF1=VIREF*22/32
22
10111b
VIREF1=VIREF*23/32
23
11000b
VIREF1=VIREF*24/32
24
11001b
VIREF0=VIREF*25/32
25
11010b
VIREF1=VIREF*26/32
26
11011b
VIREF1=VIREF*27/32
27
11100b
VIREF1=VIREF*28/32
28
11101b
VIREF1=VIREF*29/32
29
00011b
VIREF1=VIREF*3/32
3
11110b
VIREF1=VIREF*30/32
30
11111b
VIREF1=VIREF*31/32
31
00100b
VIREF1=VIREF*4/32
4
00101b
VIREF1=VIREF*5/32
5
00110b
VIREF1=VIREF*6/32
6
00111b
VIREF1=VIREF*7/32
7
01000b
VIREF1=VIREF*8/32
8
01001b
VIREF1=VIREF*9/32
9
CTRL1
Offset:0x04 CMP Control Register 1
0x4
32
read-write
n
0x0
0x0
CM2EN
CMP2 Enable bit
0
1
read-write
Disable
Disable CMP2
0
Enable
Enable CMP2
1
CM2G
CMP2 interrupt trigger direction control bit
12
13
read-write
Falling range trigger
CMP2 output status is from high to low as VPREF2 less than CM2N
0
Rising edge trigger
CMP2 output status is from low to high as VPREF2 more than CM2N
1
CM2NS
CMP2 Negative input pin
3
5
read-write
CM2N0
CM2N0
0
CM2N1
CM2N1
1
CM2N2
CM2N2
2
VIREF2
CM2N0/CM2N1/CM2N2 pins are GPIO mode
3
CM2OEN
CMP2 Output pin control bits
10
12
read-write
Disable
Disable CM2O
0
P0.12
P0.12 is CM2O and isolate GPIO function
1
P0.3
P0.3 is CM2O and isolate GPIO function
2
P3.8
P3.8 is CM2O and isolate GPIO function
3
CM2PS
CMP2 Positive input selection bits
1
3
read-write
No
CM2P0/CM2P1/CM2P2 pins are GPIO mode
0
CM2P0
CM2P0 is positive input pin
1
CM2P1
CM2P1 is positive input pin
2
CM2P2
CM2P2 is positive input pin
3
CM2RS
CMP2 internal reference voltage (VIREF2) selection bits
5
10
read-write
00000b
VIREF2=VIREF
0
00001b
VIREF2=VIREF*1/32
1
01010b
VIREF2=VIREF*10/32
10
01011b
VIREF2=VIREF*11/32
11
01100b
VIREF2=VIREF*12/32
12
01101b
VIREF2=VIREF*13/32
13
01110b
VIREF2=VIREF*14/32
14
01111b
VIREF2=VIREF*15/32
15
10000b
VIREF2=VIREF*16/32
16
10001b
VIREF2=VIREF*17/32
17
10010b
VIREF2=VIREF*18/32
18
10011b
VIREF2=VIREF*19/32
19
00010b
VIREF2=VIREF*2/32
2
10100b
VIREF2=VIREF*20/32
20
10101b
VIREF2=VIREF*21/32
21
10110b
VIREF2=VIREF*22/32
22
10111b
VIREF2=VIREF*23/32
23
11000b
VIREF2=VIREF*24/32
24
11001b
VIREF2=VIREF*25/32
25
11010b
VIREF2=VIREF*26/32
26
11011b
VIREF2=VIREF*27/32
27
11100b
VIREF2=VIREF*28/32
28
11101b
VIREF2=VIREF*29/32
29
00011b
VIREF2=VIREF*3/32
3
11110b
VIREF2=VIREF*30/32
30
11111b
VIREF2=VIREF*31/32
31
00100b
VIREF2=VIREF*4/32
4
00101b
VIREF2=VIREF*5/32
5
00110b
VIREF2=VIREF*6/32
6
00111b
VIREF2=VIREF*7/32
7
01000b
VIREF2=VIREF*8/32
8
01001b
VIREF2=VIREF*9/32
9
DB
Offset:0x1C CMP Interrupt Clear Register
0x1C
32
read-write
n
0x0
0x0
CM0DB
Count for CMP0 output debounce time
0
3
read-write
000b
No CMP0 output debounce time
0
001b
CMP0 output debounce time=2*CMP0_PCLK
1
010b
CMP0 output debounce time=4*CMP0_PCLK
2
011b
CMP0 output debounce time=8*CMP0_PCLK
3
100b
CMP0 output debounce time=16*CMP0_PCLK
4
101b
CMP0 output debounce time=32*CMP0_PCLK
5
110b
CMP0 output debounce time=64*CMP0_PCLK
6
111b
CMP0 output debounce time=128*CMP0_PCLK
7
CM1DB
Count for CMP1 output debounce time
4
7
read-write
000b
No CMP1 output debounce time
0
001b
CMP1 output debounce time=2*CMP1_PCLK
1
010b
CMP1 output debounce time=4*CMP1_PCLK
2
011b
CMP1 output debounce time=8*CMP1_PCLK
3
100b
CMP1 output debounce time=16*CMP1_PCLK
4
101b
CMP1 output debounce time=32*CMP1_PCLK
5
110b
CMP1 output debounce time=64*CMP1_PCLK
6
111b
CMP1 output debounce time=128*CMP1_PCLK
7
CM2DB
Count for CMP2 output debounce time
8
11
read-write
000b
No CMP2 output debounce time
0
001b
CMP2 output debounce time=2*CMP2_PCLK
1
010b
CMP2 output debounce time=4*CMP2_PCLK
2
011b
CMP2 output debounce time=8*CMP2_PCLK
3
100b
CMP2 output debounce time=16*CMP2_PCLK
4
101b
CMP2 output debounce time=32*CMP2_PCLK
5
110b
CMP2 output debounce time=64*CMP2_PCLK
6
111b
CMP2 output debounce time=128*CMP2_PCLK
7
CSDB
Count for Cap-sensing output debounce time
12
17
read-write
00000b
No Cap-sening output debounce time
0
00001b
Cap-sensing output debounce time=1*CS_PCLK
1
01010b
Cap-sensing output debounce time=10*CS_PCLK
10
01011b
Cap-sensing output debounce time=11*CS_PCLK
11
01100b
Cap-sensing output debounce time=12*CS_PCLK
12
01101b
Cap-sensing output debounce time=13*CS_PCLK
13
01110b
Cap-sensing output debounce time=14*CS_PCLK
14
01111b
Cap-sensing output debounce time=15*CS_PCLK
15
10000b
Cap-sensing output debounce time=16*CS_PCLK
16
10001b
Cap-sensing output debounce time=17*CS_PCLK
17
10010b
Cap-sensing output debounce time=18*CS_PCLK
18
10011b
Cap-sensing output debounce time=19*CS_PCLK
19
00010b
Cap-sensing output debounce time=2*CS_PCLK
2
10100b
Cap-sensing output debounce time=20*CS_PCLK
20
10101b
Cap-sensing output debounce time=21*CS_PCLK
21
10110b
Cap-sensing output debounce time=22*CS_PCLK
22
10111b
Cap-sensing output debounce time=23*CS_PCLK
23
11000b
Cap-sensing output debounce time=24*CS_PCLK
24
11001b
Cap-sensing output debounce time=25*CS_PCLK
25
11010b
Cap-sensing output debounce time=26*CS_PCLK
26
11011b
Cap-sensing output debounce time=27*CS_PCLK
27
11100b
Cap-sensing output debounce time=28*CS_PCLK
28
11101b
Cap-sensing output debounce time=29*CS_PCLK
29
00011b
Cap-sensing output debounce time=3*CS_PCLK
3
11110b
Cap-sensing output debounce time=30*CS_PCLK
30
11111b
Cap-sensing output debounce time=31*CS_PCLK
31
00100b
Cap-sensing output debounce time=4*CS_PCLK
4
00101b
Cap-sensing output debounce time=5*CS_PCLK
5
00110b
Cap-sensing output debounce time=6*CS_PCLK
6
00111b
Cap-sensing output debounce time=7*CS_PCLK
7
01000b
Cap-sensing output debounce time=8*CS_PCLK
8
01001b
Cap-sensing output debounce time=9*CS_PCLK
9
IC
Offset:0x18 CMP Interrupt Clear Register
0x18
32
write-only
n
0x0
0x0
CM0IC
CMP0 interrupt flag clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear CMP0 interrupt flag
1
CM1IC
CMP1 interrupt flag clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear CMP1 interrupt flag
1
CM2IC
CMP2 interrupt flag clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear CMP2 interrupt flag
1
CSIC
Cap-sensing interrupt flag clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear CS interrupt flag
1
IE
Offset:0x10 CMP Interrupt Enable Register
0x10
32
read-write
n
0x0
0x0
CM0IE
CMP0 interrupt enable
0
1
read-write
Disable
Disable CMP0 interrupt
0
Enable
Enable CMP0 interrupt
1
CM1IE
CMP1 interrupt enable
1
2
read-write
Disable
Disable CMP1 interrupt
0
Enable
Enable CMP1 interrupt
1
CM2IE
CMP2 interrupt enable
2
3
read-write
Disable
Disable CMP2 interrupt
0
Enable
Enable CMP2 interrupt
1
CSIE
Cap-sensing interrupt enable
3
4
read-write
Disable
Disable CS interrupt
0
Enable
Enable CS interrupt
1
OS
Offset:0xC CMP Output Status Register
0xC
32
read-only
n
0x0
0x0
CM0OUT
CMP0 Output flag bit
0
1
read-only
CMP0 V+ is less than V-
V0+ is less than V0-
0
CMP0 V+ is more than V-
V0+ is more than V0-
1
CM1OUT
CMP1 Output flag bit
1
2
read-only
CMP1 V+ is less than V-
V1+ is less than V1-
0
CMP1 V+ is more than V-
V1+ is more than V1- voltage
1
CM2OUT
CMP2 Output flag bit
2
3
read-only
CMP2 V+ is less than V-
V2+ is less than V2- voltage
0
CMP2 V+ is more than V-
V2+ is more than V2- voltage
1
RIS
Offset:0x14 CMP n Raw Interrupt Status Register
0x14
32
read-only
n
0x0
0x0
CM0IF
CMP0 raw interrupt flag
0
1
read-only
No interrupt
No interrupt on CMP0
0
Met interrupt requirements
Interrupt requirements met on CMP0
1
CM1IF
CMP1 raw interrupt flag
1
2
read-only
No interrupt
No interrupt on CMP1
0
Met interrupt requirements
Interrupt requirements met on CMP1
1
CM2IF
CMP2 raw interrupt flag
2
3
read-only
No interrupt
No interrupt on CMP2
0
Met interrupt requirements
Interrupt requirements met on CMP2
1
CSIF
Cap-sensing raw interrupt flag
3
4
read-only
No interrupt
No interrupt on Cap-sensing function
0
Met interrupt requirements
Interrupt requirements met on Cap-sensing function
1
VIREF
Offset:0x08 CMP Internal Reference Voltage register
0x8
32
read-write
n
0x0
0x0
CMPIREF
CMP internal reference voltage (VIREF) source
1
3
read-write
VDD
VIREF=VDD
0
Internal 1P5V
VIREF=Internal 1P5V
1
Internal 2V
VIREF=Internal 2V
2
Internal 3V
VIREF=Internal 3V
3
CMPIREFEN
CMP internal reference voltage (VIREF) enable
0
1
read-write
Disable
Disable CMP internal reference voltage
0
Enable
Enable CMP internal reference voltage
1
SN_CRC
Cyclic Redundancy Check
CRC
0x0
0x0
0x2000
registers
n
CTRL
Offset:0x0 CRC Control Register
0x0
32
read-write
n
0x0
0x0
BUSY
CRC calculation busy flag
4
5
read-only
Idle/Finish
CRC calculation idle/finished
0
Busy
CRC calculation is in process
1
CRC
CRC Polynomial
0
2
read-write
CRC-16-CCITT
CRC-16-CCITT Polynomial
0
CRC-16
CRC-16 Polynomial
1
CRC-32
CRC-32 Polynomial
2
RESET
CRC Reset bit
2
3
read-write
No
No effect
0
Reset
Reset CRC circuit
1
URCRCEN
CRC calculation for the User ROM enable bit
3
4
read-write
Stop/Finish
Stop/Finish CRC calculation
0
Enable
Start CRC calculation for the User ROM
1
DATA
Offset:0x4 CRC Data Register
0x4
32
read-write
n
0x0
0x0
DATA
CRC Data
0
32
read-write
SN_CT16B0
16-bit Timer 0 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B0
16-bit Timer 0
15
CAP0
Offset:0x88 CT16Bn CAP0 Register
0x88
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x84 CT16Bn Capture Control Register
0x84
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function for external Capture pin
1
CAP0FE
Capture/Reset on CT16Bn_CAP0 signal falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture/Reset on CT16Bn_CAP0 signal rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Timer Mode: every rising PCLK edge
0
Counter Mode 1
TC is incremented on rising edges on the CAP0 input selected by CIS bits.
1
Counter Mode 2
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2
Counter Mode 3
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x8C CT16Bn External Match Register
0x8C
32
read-write
n
0x0
0x0
EM0
When the TC doesn't match MR0 and EMC0 is not 0, this bit will drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC doesn't match MR1 and EMC1 is not 0, this bit will drive the state of CT16Bn_PWM1 output.
1
2
read-write
EM2
When the TC doesn't match MR2 and EMC2 is not 0, this bit will drive the state of CT16Bn_PWM2 output.
2
3
read-write
EM3
When the TC doesn't match MR3 and EMC3 is not 0, this bit will drive the state of CT16Bn_PWM3 output.
3
4
read-write
EMC0
CT16Bn_PWM0 functionality when MR0=TC
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality when MR1=TC
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
EMC2
CT16Bn_PWM2 functionality when MR2=TC
8
10
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM2 pin is LOW
1
High
CT16Bn_PWM2 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM2 pin
3
EMC3
CT16Bn_PWM3 functionality when MR3=TC
10
12
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM3 pin is LOW
1
High
CT16Bn_PWM3 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM3 pin
3
PWMKEY
PWM register key.
24
32
write-only
IC
Offset:0xAC CT16Bn Interrupt Clear Register
0xAC
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR2IC
MR2IF clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear MR2IF
1
MR3IC
MR3IF clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear MR3IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR2IE
Enable generating an interrupt when MR2 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR2 matches TC
1
MR2RST
Enable reset TC when MR2 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR2 matches TC
1
MR2STOP
Stop TC and PC and clear CEN bit when MR2 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
1
MR3IE
Enable generating an interrupt when MR3 matches TC
9
10
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR3 matches TC
1
MR3RST
Enable reset TC when MR3 matches TC
10
11
read-write
Disable
Disable
0
Enable
Reset TC when MR3 matches TC
1
MR3STOP
Stop TC and PC and clear CEN bit when MR3 matches TC
11
12
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
1
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
21
22
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
22
23
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
23
24
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
PWMKEY
PWM register key.
24
32
write-only
MR0
Offset:0x20 CT16Bn MR0 Register
0x20
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
MR1
Offset:0x24 CT16Bn MR1 Register
0x24
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
MR2
Offset:0x28 CT16Bn MR2 Register
0x28
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
MR3
Offset:0x2C CT16Bn MR3 Register
0x2C
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
MR9
Offset:0x44 CT16Bn MR9 Register
0x44
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescaler
0
8
read-write
PWM0NDB
Offset:0xB4 CT16Bn PWM0N Dead-band Period Register
0xB4
32
read-write
n
0x0
0x0
DB
PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWM1NDB
Offset:0xB8 CT16Bn PWM1N Dead-band Period Register
0xB8
32
read-write
n
0x0
0x0
DB
PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWM2NDB
Offset:0xBC CT16Bn PWM2N Dead-band Period Register
0xBC
32
read-write
n
0x0
0x0
DB
PWM2N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWM3NDB
Offset:0xC0 CT16Bn PWM3N Dead-band Period Register
0xC0
32
read-write
n
0x0
0x0
DB
PWM3N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWMCTRL
Offset:0x98 CT16Bn PWM Control Register
0x98
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EMC0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0.
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0.
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EMC1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1.
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1.
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWM2EN
PWM2 enable
2
3
read-write
Disable
CT16Bn_PWM2 is controlled by EMC2
0
Enable
Enable PWM mode for CT16Bn_PWM2
1
PWM2IOEN
CT16Bn_PWM2/GPIO selection
22
23
read-write
Disable
CT16Bn_PWM2 pin is act as GPIO
0
Enable
CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
1
PWM2MODE
PWM2 output mode
8
10
read-write
PWM mode 1
During up-counting, PWM2 is 0 when TC is less than MR2.
0
PWM mode 2
During up-counting, PWM2 is 1 when TC is less than MR2.
1
Force 0
PWM2 is forced to 0
2
Force 1
PWM2 is forced to 1
3
PWM3EN
PWM2 enable
3
4
read-write
Disable
CT16Bn_PWM3 is controlled by EMC3
0
Enable
Enable PWM mode for CT16Bn_PWM3
1
PWM3IOEN
CT16Bn_PWM3/GPIO selection
23
24
read-write
Disable
CT16Bn_PWM3 pin is act as GPIO
0
Enable
CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
1
PWM3MODE
PWM3 output mode
10
12
read-write
PWM mode 1
During up-counting, PWM3 is 0 when TC is less than MR3.
0
PWM mode 2
During up-counting, PWM3 is 1 when TC is less than MR3.
1
Force 0
PWM3 is forced to 0
2
Force 1
PWM3 is forced to 1
3
PWMKEY
PWM register key.
24
32
write-only
PWMmNIOCTRL
Offset:0xB0 CT16Bn PWMmN IO Control register
0xB0
32
read-write
n
0x0
0x0
PWM0NIOEN
CT16Bn_PWM0N/GPIO selection bit
0
2
read-write
0
CT16Bn_PWM0N pin is act as GPIO
0
1
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM0N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM1NIOEN
CT16Bn_PWM0N/GPIO selection bit
2
4
read-write
0
CT16Bn_PWM1N pin is act as GPIO
0
1
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM1N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM2NIOEN
CT16Bn_PWM0N/GPIO selection bit
4
6
read-write
0
CT16Bn_PWM2N pin is act as GPIO
0
1
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM2N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM2N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM3NIOEN
CT16Bn_PWM3N/GPIO selection bit
6
8
read-write
0
CT16Bn_PWM3N pin is act as GPIO
0
1
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same High signal during dead-band period
1
2
CT16Bn_PWM3N pin outputs the inverse signal with dead-band of CT16Bn_PWM3, but same Low signal during dead-band period
2
3
CT16Bn_PWM3N pin outputs the same signal with dead-band of CT16Bn_PWM3
3
PWMKEY
PWM register key.
24
32
write-only
RIS
Offset:0xA8 CT16Bn Raw Interrupt Status Register
0xA8
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR2IF
Match channel 2 interrupt flag
2
3
read-only
No
No interrupt on match channel 2
0
Met interrupt requirements
Interrupt requirements met on match channel 2
1
MR3IF
Match channel 3 interrupt flag
3
4
read-only
No
No interrupt on match channel 3
0
Met interrupt requirements
Interrupt requirements met on match channel 3
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
PCLK source
2
3
read-write
HCLK
CT16Bn PCLK source=HCLK
0
PLL_VCO
CT16Bn PCLK source=PLL_VCO
1
CM
Counting mode selection
4
7
read-write
Up-counting mode
Edge-aligned Up-counting mode
0
Down-counting mode
Edge-aligned Down-counting mode
1
Center-aligned counting mode 1
The match interrupt flag is set during the down-counting period
2
Center-aligned counting mode 2
The match interrupt flag is set during the up-counting period
4
Center-aligned counting mode 3
The match interrupt flag is set during both up-counting and down-counting period
6
CRST
Counter Reset
1
2
read-write
Disable
Disable Counter
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_CT16B1
16-bit Timer 1 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B1
CT16B1
16
CAP0
Offset:0x88 CT16Bn CAP0 Register
0x88
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x84 CT16Bn Capture Control Register
0x84
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function for external Capture pin
1
CAP0FE
Capture/Reset on CT16Bn_CAP0 signal falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture/Reset on CT16Bn_CAP0 signal rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Timer Mode: every rising PCLK edge
0
Counter Mode 1
TC is incremented on rising edges on the CAP0 input selected by CIS bits.
1
Counter Mode 2
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2
Counter Mode 3
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x8C CT16Bn External Match Register
0x8C
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EM10
When the TC matches MR10, this bit will act according to EMC10[1:0], and also drive the state of CT16Bn_PWM2 output.
10
11
read-write
EM11
When the TC matches MR11, this bit will act according to EMC11[1:0], and also drive the state of CT16Bn_PWM3 output.
11
12
read-write
EM2
When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
2
3
read-write
EM3
When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output.
3
4
read-write
EM4
When the TC matches MR4, this bit will act according to EMC4[1:0], and also drive the state of CT16Bn_PWM0 output.
4
5
read-write
EM5
When the TC matches MR5, this bit will act according to EMC5[1:0], and also drive the state of CT16Bn_PWM1 output.
5
6
read-write
EM6
When the TC matches MR6, this bit will act according to EMC6[1:0], and also drive the state of CT16Bn_PWM2 output.
6
7
read-write
EM7
When the TC matches MR7, this bit will act according to EMC7[1:0], and also drive the state of CT16Bn_PWM3 output.
7
8
read-write
EM8
When the TC matches MR8, this bit will act according to EMC8[1:0], and also drive the state of CT16Bn_PWM0 output.
8
9
read-write
EM9
When the TC matches MR9, this bit will act according to EMC9[1:0], and also drive the state of CT16Bn_PWM1 output.
9
10
read-write
EMC
Offset:0x90 CT16Bn External Match Control register
0x90
32
read-write
n
0x0
0x0
EMC0
CT16Bn_PWM0 functionality
0
2
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
2
4
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
EMC10
CT16Bn_PWM10 functionality
20
22
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM10 pin is LOW
1
High
CT16Bn_PWM10 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM10 pin
3
EMC11
CT16Bn_PWM11 functionality
22
24
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM11 pin is LOW
1
High
CT16Bn_PWM11 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM11 pin
3
EMC2
CT16Bn_PWM2 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM2 pin is LOW
1
High
CT16Bn_PWM2 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM2 pin
3
EMC3
CT16Bn_PWM3 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM3 pin is LOW
1
High
CT16Bn_PWM3 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM3 pin
3
EMC4
CT16Bn_PWM4 functionality
8
10
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM4 pin is LOW
1
High
CT16Bn_PWM4 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM4 pin
3
EMC5
CT16Bn_PWM5 functionality
10
12
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM5 pin is LOW
1
High
CT16Bn_PWM5 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM5 pin
3
EMC6
CT16Bn_PWM6 functionality
12
14
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM6 pin is LOW
1
High
CT16Bn_PWM6 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM6 pin
3
EMC7
CT16Bn_PWM7 functionality
14
16
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM7 pin is LOW
1
High
CT16Bn_PWM7 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM7 pin
3
EMC8
CT16Bn_PWM8 functionality
16
18
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM8 pin is LOW
1
High
CT16Bn_PWM8 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM8 pin
3
EMC9
CT16Bn_PWM9 functionality
18
20
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM9 pin is LOW
1
High
CT16Bn_PWM9 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM9 pin
3
IC
Offset:0xAC CT16Bn Interrupt Clear Register
0xAC
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
13
14
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR10IC
MR10IF clear bit
10
11
write-only
No effect
No effect
0
Clear
Clear MR10IF
1
MR11IC
MR11IF clear bit
11
12
write-only
No effect
No effect
0
Clear
Clear MR11IF
1
MR12IC
MR12IF clear bit
12
13
write-only
No effect
No effect
0
Clear
Clear MR12IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR2IC
MR2IF clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear MR2IF
1
MR3IC
MR3IF clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear MR3IF
1
MR4IC
MR4IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear MR4IF
1
MR5IC
MR5IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR5IF
1
MR6IC
MR6IF clear bit
6
7
write-only
No effect
No effect
0
Clear
Clear MR6IF
1
MR7IC
MR7IF clear bit
7
8
write-only
No effect
No effect
0
Clear
Clear MR7IF
1
MR8IC
MR8IF clear bit
8
9
write-only
No effect
No effect
0
Clear
Clear MR8IF
1
MR9IC
MR9IF clear bit
9
10
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR2IE
Enable generating an interrupt when MR2 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR2 matches TC
1
MR2RST
Enable reset TC when MR2 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR2 matches TC
1
MR2STOP
Stop TC and PC and clear CEN bit when MR2 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
1
MR3IE
Enable generating an interrupt when MR3 matches TC
9
10
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR3 matches TC
1
MR3RST
Enable reset TC when MR3 matches TC
10
11
read-write
Disable
Disable
0
Enable
Reset TC when MR3 matches TC
1
MR3STOP
Stop TC and PC and clear CEN bit when MR3 matches TC
11
12
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
1
MR4IE
Enable generating an interrupt when MR4 matches TC
12
13
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR4 matches TC
1
MR4RST
Enable reset TC when MR4 matches TC
13
14
read-write
Disable
Disable
0
Enable
Reset TC when MR4 matches TC
1
MR4STOP
Stop TC and PC and clear CEN bit when MR4 matches TC
14
15
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR4 matches TC
1
MR5IE
Enable generating an interrupt when MR5 matches TC
15
16
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR5 matches TC
1
MR5RST
Enable reset TC when MR5 matches TC
16
17
read-write
Disable
Disable
0
Enable
Reset TC when MR5 matches TC
1
MR5STOP
Stop TC and PC and clear CEN bit when MR5 matches TC
17
18
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR5 matches TC
1
MR6IE
Enable generating an interrupt when MR6 matches TC
18
19
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR6 matches TC
1
MR6RST
Enable reset TC when MR6 matches TC
19
20
read-write
Disable
Disable
0
Enable
Reset TC when MR6 matches TC
1
MR6STOP
Stop TC and PC and clear CEN bit when MR6 matches TC
20
21
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR6 matches TC
1
MR7IE
Enable generating an interrupt when MR7 matches TC
21
22
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR7 matches TC
1
MR7RST
Enable reset TC when MR7 matches TC
22
23
read-write
Disable
Disable
0
Enable
Reset TC when MR7 matches TC
1
MR7STOP
Stop TC and PC and clear CEN bit when MR7 matches TC
23
24
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR7 matches TC
1
MR8IE
Enable generating an interrupt when MR8 matches TC
24
25
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR8 matches TC
1
MR8RST
Enable reset TC when MR8 matches TC
25
26
read-write
Disable
Disable
0
Enable
Reset TC when MR8 matches TC
1
MR8STOP
Stop TC and PC and clear CEN bit when MR8 matches TC
26
27
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR8 matches TC
1
MR9IE
Enable generating an interrupt when MR9 matches TC
27
28
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
28
29
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
29
30
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
MCTRL2
Offset:0x18 CT16Bn Match Control Register 2
0x18
32
read-write
n
0x0
0x0
MR10IE
Enable generating an interrupt when MR10 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR10 matches TC
1
MR10RST
Enable reset TC when MR10 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR10 matches TC
1
MR10STOP
Stop TC and PC and clear CEN bit when MR10 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR10 matches TC
1
MR11IE
Enable generating an interrupt when MR11 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR11 matches TC
1
MR11RST
Enable reset TC when MR11 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR11 matches TC
1
MR11STOP
Stop TC and PC and clear CEN bit when MR11 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR11 matches TC
1
MR12IE
Enable generating an interrupt when MR12 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR12 matches TC
1
MR12RST
Enable reset TC when MR12 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR12 matches TC
1
MR12STOP
Stop TC and PC and clear CEN bit when MR12 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR12 matches TC
1
MR0
Offset:0x20 CT16Bn MR0 Register
0x20
32
read-write
n
0x0
0x0
MR1
Offset:0x24 CT16Bn MR1 Register
0x24
32
read-write
n
0x0
0x0
MR10
Offset:0x48 CT16Bn MR10 Register
0x48
32
read-write
n
0x0
0x0
MR11
Offset:0x4C CT16Bn MR11 Register
0x4C
32
read-write
n
0x0
0x0
MR12
Offset:0x50 CT16Bn MR12 Register
0x50
32
read-write
n
0x0
0x0
MR2
Offset:0x28 CT16Bn MR2 Register
0x28
32
read-write
n
0x0
0x0
MR3
Offset:0x2C CT16Bn MR3 Register
0x2C
32
read-write
n
0x0
0x0
MR4
Offset:0x30 CT16Bn MR4 Register
0x30
32
read-write
n
0x0
0x0
MR5
Offset:0x34 CT16Bn MR5 Register
0x34
32
read-write
n
0x0
0x0
MR6
Offset:0x38 CT16Bn MR6 Register
0x38
32
read-write
n
0x0
0x0
MR7
Offset:0x3C CT16Bn MR7 Register
0x3C
32
read-write
n
0x0
0x0
MR8
Offset:0x40 CT16Bn MR8 Register
0x40
32
read-write
n
0x0
0x0
MR9
Offset:0x44 CT16Bn MR9 Register
0x44
32
read-write
n
0x0
0x0
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescaler
0
8
read-write
PWMCTRL
Offset:0x98 CT16Bn PWM Control Register
0x98
32
read-write
n
0x0
0x0
PWM0MODE
PWM0 output mode
0
2
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0. During down-counting, PWM0 is 1 when TC is larger/equal than MR0
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0. During down-counting, PWM0 is 0 when TC is larger/equal than MR0
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM10MODE
PWM10 output mode
20
22
read-write
PWM mode 1
During up-counting, PWM10 is 0 when TC is less than MR10. During down-counting, PWM10 is 1 when TC is larger/equal than MR10
0
PWM mode 2
During up-counting, PWM10 is 1 when TC is less than MR10. During down-counting, PWM10 is 0 when TC is larger/equal than MR10
1
Force 0
PWM10 is forced to 0
2
Force 1
PWM10 is forced to 1
3
PWM11MODE
PWM11 output mode
22
24
read-write
PWM mode 1
During up-counting, PWM11 is 0 when TC is less than MR11. During down-counting, PWM11 is 1 when TC is larger/equal than MR11
0
PWM mode 2
During up-counting, PWM11 is 1 when TC is less than MR11. During down-counting, PWM11 is 0 when TC is larger/equal than MR11
1
Force 0
PWM11 is forced to 0
2
Force 1
PWM11 is forced to 1
3
PWM1MODE
PWM1 output mode
2
4
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1. During down-counting, PWM1 is 1 when TC is larger/equal than MR1
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1. During down-counting, PWM1 is 0 when TC is larger/equal than MR1
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWM2MODE
PWM2 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM2 is 0 when TC is less than MR2. During down-counting, PWM2 is 1 when TC is larger/equal than MR2
0
PWM mode 2
During up-counting, PWM2 is 1 when TC is less than MR2. During down-counting, PWM2 is 0 when TC is larger/equal than MR2
1
Force 0
PWM2 is forced to 0
2
Force 1
PWM2 is forced to 1
3
PWM3MODE
PWM3 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM3 is 0 when TC is less than MR3. During down-counting, PWM3 is 1 when TC is larger/equal than MR3
0
PWM mode 2
During up-counting, PWM3 is 1 when TC is less than MR3. During down-counting, PWM3 is 0 when TC is larger/equal than MR3
1
Force 0
PWM3 is forced to 0
2
Force 1
PWM3 is forced to 1
3
PWM4MODE
PWM4 output mode
8
10
read-write
PWM mode 1
During up-counting, PWM4 is 0 when TC is less than MR4. During down-counting, PWM4 is 1 when TC is larger/equal than MR4
0
PWM mode 2
During up-counting, PWM4 is 1 when TC is less than MR4. During down-counting, PWM4 is 0 when TC is larger/equal than MR4
1
Force 0
PWM4 is forced to 0
2
Force 1
PWM4 is forced to 1
3
PWM5MODE
PWM5 output mode
10
12
read-write
PWM mode 1
During up-counting, PWM5 is 0 when TC is less than MR5. During down-counting, PWM5 is 1 when TC is larger/equal than MR5
0
PWM mode 2
During up-counting, PWM5 is 1 when TC is less than MR5. During down-counting, PWM5 is 0 when TC is larger/equal than MR5
1
Force 0
PWM5 is forced to 0
2
Force 1
PWM5 is forced to 1
3
PWM6MODE
PWM6 output mode
12
14
read-write
PWM mode 1
During up-counting, PWM6 is 0 when TC is less than MR6. During down-counting, PWM6 is 1 when TC is larger/equal than MR6
0
PWM mode 2
During up-counting, PWM6 is 1 when TC is less than MR6. During down-counting, PWM6 is 0 when TC is larger/equal than MR6
1
Force 0
PWM6 is forced to 0
2
Force 1
PWM6 is forced to 1
3
PWM7MODE
PWM7 output mode
14
16
read-write
PWM mode 1
During up-counting, PWM7 is 0 when TC is less than MR7. During down-counting, PWM7 is 1 when TC is larger/equal than MR7
0
PWM mode 2
During up-counting, PWM7 is 1 when TC is less than MR7. During down-counting, PWM7 is 0 when TC is larger/equal than MR7
1
Force 0
PWM7 is forced to 0
2
Force 1
PWM7 is forced to 1
3
PWM8MODE
PWM8 output mode
16
18
read-write
PWM mode 1
During up-counting, PWM8 is 0 when TC is less than MR8. During down-counting, PWM8 is 1 when TC is larger/equal than MR8
0
PWM mode 2
During up-counting, PWM8 is 1 when TC is less than MR8. During down-counting, PWM8 is 0 when TC is larger/equal than MR8
1
Force 0
PWM8 is forced to 0
2
Force 1
PWM8 is forced to 1
3
PWM9MODE
PWM9 output mode
18
20
read-write
PWM mode 1
During up-counting, PWM9 is 0 when TC is less than MR9. During down-counting, PWM9 is 1 when TC is larger/equal than MR9
0
PWM mode 2
During up-counting, PWM9 is 1 when TC is less than MR9. During down-counting, PWM9 is 0 when TC is larger/equal than MR9
1
Force 0
PWM9 is forced to 0
2
Force 1
PWM9 is forced to 1
3
PWMENB
Offset:0xA0 CT16Bn PWM Enable register
0xA0
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM10EN
PWM10 enable
10
11
read-write
Disable
CT16Bn_PWM10 is controlled by EM10
0
Enable
Enable PWM mode for CT16Bn_PWM10
1
PWM11EN
PWM11 enable
11
12
read-write
Disable
CT16Bn_PWM11 is controlled by EM11
0
Enable
Enable PWM mode for CT16Bn_PWM11
1
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM2EN
PWM2 enable
2
3
read-write
Disable
CT16Bn_PWM2 is controlled by EM2
0
Enable
Enable PWM mode for CT16Bn_PWM2
1
PWM3EN
PWM3 enable
3
4
read-write
Disable
CT16Bn_PWM3 is controlled by EM3
0
Enable
Enable PWM mode for CT16Bn_PWM3
1
PWM4EN
PWM4 enable
4
5
read-write
Disable
CT16Bn_PWM4 is controlled by EM4
0
Enable
Enable PWM mode for CT16Bn_PWM4
1
PWM5EN
PWM5 enable
5
6
read-write
Disable
CT16Bn_PWM5 is controlled by EM5
0
Enable
Enable PWM mode for CT16Bn_PWM5
1
PWM6EN
PWM6 enable
6
7
read-write
Disable
CT16Bn_PWM6 is controlled by EM6
0
Enable
Enable PWM mode for CT16Bn_PWM6
1
PWM7EN
PWM7 enable
7
8
read-write
Disable
CT16Bn_PWM7 is controlled by EM7
0
Enable
Enable PWM mode for CT16Bn_PWM7
1
PWM8EN
PWM8 enable
8
9
read-write
Disable
CT16Bn_PWM8 is controlled by EM8
0
Enable
Enable PWM mode for CT16Bn_PWM8
1
PWM9EN
PWM9 enable
9
10
read-write
Disable
CT16Bn_PWM9 is controlled by EM9
0
Enable
Enable PWM mode for CT16Bn_PWM9
1
PWMIOENB
Offset:0xA4 CT16Bn PWM IO Enable register
0xA4
32
read-write
n
0x0
0x0
PWM0IOEN
CT16Bn_PWM0/GPIO selection
0
1
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM10IOEN
CT16Bn_PWM10/GPIO selection
10
11
read-write
Disable
CT16Bn_PWM10 pin is act as GPIO
0
Enable
CT16Bn_PWM10 pin act as match output, and output depends on PWM10EN bit
1
PWM11IOEN
CT16Bn_PWM11/GPIO selection
11
12
read-write
Disable
CT16Bn_PWM11 pin is act as GPIO
0
Enable
CT16Bn_PWM11 pin act as match output, and output depends on PWM11EN bit
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
1
2
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM2IOEN
CT16Bn_PWM2/GPIO selection
2
3
read-write
Disable
CT16Bn_PWM2 pin is act as GPIO
0
Enable
CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
1
PWM3IOEN
CT16Bn_PWM3/GPIO selection
3
4
read-write
Disable
CT16Bn_PWM3 pin is act as GPIO
0
Enable
CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
1
PWM4IOEN
CT16Bn_PWM4/GPIO selection
4
5
read-write
Disable
CT16Bn_PWM4 pin is act as GPIO
0
Enable
CT16Bn_PWM4 pin act as match output, and output depends on PWM4EN bit
1
PWM5IOEN
CT16Bn_PWM5/GPIO selection
5
6
read-write
Disable
CT16Bn_PWM5 pin is act as GPIO
0
Enable
CT16Bn_PWM5 pin act as match output, and output depends on PWM5EN bit
1
PWM6IOEN
CT16Bn_PWM6/GPIO selection
6
7
read-write
Disable
CT16Bn_PWM6 pin is act as GPIO
0
Enable
CT16Bn_PWM6 pin act as match output, and output depends on PWM6EN bit
1
PWM7IOEN
CT16Bn_PWM7/GPIO selection
7
8
read-write
Disable
CT16Bn_PWM7 pin is act as GPIO
0
Enable
CT16Bn_PWM7 pin act as match output, and output depends on PWM7EN bit
1
PWM8IOEN
CT16Bn_PWM8/GPIO selection
8
9
read-write
Disable
CT16Bn_PWM8 pin is act as GPIO
0
Enable
CT16Bn_PWM8 pin act as match output, and output depends on PWM8EN bit
1
PWM9IOEN
CT16Bn_PWM9/GPIO selection
9
10
read-write
Disable
CT16Bn_PWM9 pin is act as GPIO
0
Enable
CT16Bn_PWM9 pin act as match output, and output depends on PWM9EN bit
1
RIS
Offset:0xA8 CT16Bn Raw Interrupt Status Register
0xA8
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
13
14
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR10IF
Match channel 10 interrupt flag
10
11
read-only
No
No interrupt on match channel 10
0
Met interrupt requirements
Interrupt requirements met on match channel 10
1
MR11IF
Match channel 11 interrupt flag
11
12
read-only
No
No interrupt on match channel 11
0
Met interrupt requirements
Interrupt requirements met on match channel 11
1
MR12IF
Match channel 12 interrupt flag
12
13
read-only
No
No interrupt on match channel 12
0
Met interrupt requirements
Interrupt requirements met on match channel 12
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR2IF
Match channel 2 interrupt flag
2
3
read-only
No
No interrupt on match channel 2
0
Met interrupt requirements
Interrupt requirements met on match channel 2
1
MR3IF
Match channel 3 interrupt flag
3
4
read-only
No
No interrupt on match channel 3
0
Met interrupt requirements
Interrupt requirements met on match channel 3
1
MR4IF
Match channel 4 interrupt flag
4
5
read-only
No interrupt
No interrupt on match channel 4
0
Met interrupt requirements
Interrupt requirements met on match channel 4
1
MR5IF
Match channel 5 interrupt flag
5
6
read-only
No
No interrupt on match channel 5
0
Met interrupt requirements
Interrupt requirements met on match channel 5
1
MR6IF
Match channel 6 interrupt flag
6
7
read-only
No
No interrupt on match channel 6
0
Met interrupt requirements
Interrupt requirements met on match channel 6
1
MR7IF
Match channel 7 interrupt flag
7
8
read-only
No
No interrupt on match channel 7
0
Met interrupt requirements
Interrupt requirements met on match channel 7
1
MR8IF
Match channel 8 interrupt flag
8
9
read-only
No interrupt
No interrupt on match channel 8
0
Met interrupt requirements
Interrupt requirements met on match channel 8
1
MR9IF
Match channel 9 interrupt flag
9
10
read-only
No
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
PCLK source
2
3
read-write
HCLK
CT16Bn PCLK source=HCLK
0
PLL_VCO
CT16Bn PCLK source=PLL_VCO
1
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_CT16B2
16-bit Timer 2 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B2
16-bit Timer 2
17
CAP0
Offset:0x88 CT16Bn CAP0 Register
0x88
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x84 CT16Bn Capture Control Register
0x84
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function for external Capture pin
1
CAP0FE
Capture/Reset on CT16Bn_CAP0 signal falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture/Reset on CT16Bn_CAP0 signal rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Timer Mode: every rising PCLK edge
0
Counter Mode 1
TC is incremented on rising edges on the CAP0 input selected by CIS bits.
1
Counter Mode 2
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2
Counter Mode 3
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x8C CT16Bn External Match Register
0x8C
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EM2
When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
2
3
read-write
EM3
When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output.
3
4
read-write
EMC0
CT16Bn_PWM0 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
EMC2
CT16Bn_PWM2 functionality
8
10
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM2 pin is LOW
1
High
CT16Bn_PWM2 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM2 pin
3
EMC3
CT16Bn_PWM3 functionality
10
12
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM3 pin is LOW
1
High
CT16Bn_PWM3 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM3 pin
3
PWMKEY
PWM register key.
24
32
write-only
IC
Offset:0xAC CT16Bn Interrupt Clear Register
0xAC
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR2IC
MR2IF clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear MR2IF
1
MR3IC
MR3IF clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear MR3IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR2IE
Enable generating an interrupt when MR2 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR2 matches TC
1
MR2RST
Enable reset TC when MR2 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR2 matches TC
1
MR2STOP
Stop TC and PC and clear CEN bit when MR2 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
1
MR3IE
Enable generating an interrupt when MR3 matches TC
9
10
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR3 matches TC
1
MR3RST
Enable reset TC when MR3 matches TC
10
11
read-write
Disable
Disable
0
Enable
Reset TC when MR3 matches TC
1
MR3STOP
Stop TC and PC and clear CEN bit when MR3 matches TC
11
12
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
1
MR9IE
Enable generating an interrupt when MR9 matches TC
21
22
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
22
23
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
23
24
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
PWMKEY
PWM register key.
24
32
write-only
MR0
Offset:0x20 CT16Bn MR0 Register
0x20
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR1
Offset:0x24 CT16Bn MR1 Register
0x24
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR2
Offset:0x28 CT16Bn MR2 Register
0x28
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR3
Offset:0x2C CT16Bn MR3 Register
0x2C
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR9
Offset:0x44 CT16Bn MR9 Register
0x44
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescalzer
0
8
read-write
PWMCTRL
Offset:0x98 CT16Bn PWM Control Register
0x98
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0.
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0.
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1.
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1.
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWM2EN
PWM2 enable
2
3
read-write
Disable
CT16Bn_PWM2 is controlled by EM2
0
Enable
Enable PWM mode for CT16Bn_PWM2
1
PWM2IOEN
CT16Bn_PWM2/GPIO selection
22
23
read-write
Disable
CT16Bn_PWM2 pin is act as GPIO
0
Enable
CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
1
PWM2MODE
PWM2 output mode
8
10
read-write
PWM mode 1
During up-counting, PWM2 is 0 when TC is less than MR2.
0
PWM mode 2
During up-counting, PWM2 is 1 when TC is less than MR2.
1
Force 0
PWM2 is forced to 0
2
Force 1
PWM2 is forced to 1
3
PWM3EN
PWM2 enable
3
4
read-write
Disable
CT16Bn_PWM3 is controlled by EM3
0
Enable
Enable PWM mode for CT16Bn_PWM3
1
PWM3IOEN
CT16Bn_PWM3/GPIO selection
23
24
read-write
Disable
CT16Bn_PWM3 pin is act as GPIO
0
Enable
CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
1
PWM3MODE
PWM3 output mode
10
12
read-write
PWM mode 1
During up-counting, PWM3 is 0 when TC is less than MR3.
0
PWM mode 2
During up-counting, PWM3 is 1 when TC is less than MR3.
1
Force 0
PWM3 is forced to 0
2
Force 1
PWM3 is forced to 1
3
PWMKEY
PWM register key.
24
32
write-only
RIS
Offset:0xA8 CT16Bn Raw Interrupt Status Register
0xA8
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No interrupt
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR2IF
Match channel 2 interrupt flag
2
3
read-only
No interrupt
No interrupt on match channel 2
0
Met interrupt requirements
Interrupt requirements met on match channel 2
1
MR3IF
Match channel 3 interrupt flag
3
4
read-only
No interrupt
No interrupt on match channel 3
0
Met interrupt requirements
Interrupt requirements met on match channel 3
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No interrupt
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
PCLK source
2
3
read-write
HCLK
CT16Bn PCLK source=HCLK
0
PLL_VCO
CT16Bn PCLK source=PLL_VCO
1
CM
Counting mode selection
4
7
read-write
Up-counting mode
Edge-aligned Up-counting mode
0
Down-counting mode
Edge-aligned Down-counting mode
1
Center-aligned counting mode 1
The match interrupt flag is set during the down-counting period
2
Center-aligned counting mode 2
The match interrupt flag is set during the up-counting period
4
Center-aligned counting mode 3
The match interrupt flag is set during both up-counting and down-counting period
6
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_CT16B3
16-bit Timer 3 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B3
16-bit Timer 3
19
CAP0
Offset:0x88 CT16Bn CAP0 Register
0x88
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x84 CT16Bn Capture Control Register
0x84
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function for external Capture pin
1
CAP0FE
Capture/Reset on CT16Bn_CAP0 signal falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture/Reset on CT16Bn_CAP0 signal rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Timer Mode: every rising PCLK edge
0
Counter Mode 1
TC is incremented on rising edges on the CAP0 input selected by CIS bits.
1
Counter Mode 2
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2
Counter Mode 3
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x8C CT16Bn External Match Register
0x8C
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EMC0
CT16Bn_PWM0 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
IC
Offset:0xAC CT16Bn Interrupt Clear Register
0xAC
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
21
22
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
22
23
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
23
24
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
PWMKEY
PWM register key.
24
32
write-only
MR0
Offset:0x20 CT16Bn MR0 Register
0x20
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR1
Offset:0x24 CT16Bn MR1 Register
0x24
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR9
Offset:0x44 CT16Bn MR9 Register
0x44
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescalzer
0
8
read-write
PWM0NDB
Offset:0xB4 CT16Bn PWM0N Dead-band Period Register
0xB4
32
read-write
n
0x0
0x0
DB
PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWM1NDB
Offset:0xB8 CT16Bn PWM1N Dead-band Period Register
0xB8
32
read-write
n
0x0
0x0
DB
PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWMCTRL
Offset:0x98 CT16Bn PWM Control Register
0x98
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0.
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0.
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1.
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1.
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWMKEY
PWM register key.
24
32
write-only
PWMmNIOCTRL
Offset:0xB0 CT16Bn PWMmN IO Control register
0xB0
32
read-write
n
0x0
0x0
PWM0NIOEN
CT16Bn_PWM0N/GPIO selection bit
0
2
read-write
0
CT16Bn_PWM0N pin is act as GPIO
0
1
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM0N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM1NIOEN
CT16Bn_PWM0N/GPIO selection bit
2
4
read-write
0
CT16Bn_PWM1N pin is act as GPIO
0
1
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM1N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWMKEY
PWM register key.
24
32
write-only
RIS
Offset:0xA8 CT16Bn Raw Interrupt Status Register
0xA8
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No interrupt
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No interrupt
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
PCLK source
2
3
read-write
HCLK
CT16Bn PCLK source=HCLK
0
PLL_VCO
CT16Bn PCLK source=PLL_VCO
1
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_CT16B4
16-bit Timer 3 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B4
16-bit Timer 4
20
CAP0
Offset:0x88 CT16Bn CAP0 Register
0x88
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x84 CT16Bn Capture Control Register
0x84
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function for external Capture pin
1
CAP0FE
Capture/Reset on CT16Bn_CAP0 signal falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture/Reset on CT16Bn_CAP0 signal rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Timer Mode: every rising PCLK edge
0
Counter Mode 1
TC is incremented on rising edges on the CAP0 input selected by CIS bits.
1
Counter Mode 2
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2
Counter Mode 3
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x8C CT16Bn External Match Register
0x8C
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EMC0
CT16Bn_PWM0 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
IC
Offset:0xAC CT16Bn Interrupt Clear Register
0xAC
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
21
22
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
22
23
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
23
24
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
PWMKEY
PWM register key.
24
32
write-only
MR0
Offset:0x20 CT16Bn MR0 Register
0x20
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR1
Offset:0x24 CT16Bn MR1 Register
0x24
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR9
Offset:0x44 CT16Bn MR9 Register
0x44
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescalzer
0
8
read-write
PWM0NDB
Offset:0xB4 CT16Bn PWM0N Dead-band Period Register
0xB4
32
read-write
n
0x0
0x0
DB
PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWM1NDB
Offset:0xB8 CT16Bn PWM1N Dead-band Period Register
0xB8
32
read-write
n
0x0
0x0
DB
PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) cycle
0
10
read-write
PWMKEY
PWM register key.
24
32
write-only
PWMCTRL
Offset:0x98 CT16Bn PWM Control Register
0x98
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0.
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0.
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1.
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1.
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWMKEY
PWM register key.
24
32
write-only
PWMmNIOCTRL
Offset:0xB0 CT16Bn PWMmN IO Control register
0xB0
32
read-write
n
0x0
0x0
PWM0NIOEN
CT16Bn_PWM0N/GPIO selection bit
0
2
read-write
0
CT16Bn_PWM0N pin is act as GPIO
0
1
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM0N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM0N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWM1NIOEN
CT16Bn_PWM0N/GPIO selection bit
2
4
read-write
0
CT16Bn_PWM1N pin is act as GPIO
0
1
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same High signal during dead-band period
1
2
CT16Bn_PWM1N pin outputs the inverse signal with dead-band of CT16Bn_PWM0, but same Low signal during dead-band period
2
3
CT16Bn_PWM1N pin outputs the same signal with dead-band of CT16Bn_PWM0
3
PWMKEY
PWM register key.
24
32
write-only
RIS
Offset:0xA8 CT16Bn Raw Interrupt Status Register
0xA8
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No interrupt
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No interrupt
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
PCLK source
2
3
read-write
HCLK
CT16Bn PCLK source=HCLK
0
PLL_VCO
CT16Bn PCLK source=PLL_VCO
1
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_CT16B5
16-bit Timer 5 with Capture function
TIMER
0x0
0x0
0x2000
registers
n
CT16B5
16-bit Timer 5
21
CAP0
Offset:0x88 CT16Bn CAP0 Register
0x88
32
read-only
n
0x0
0x0
CAP0
Timer counter capture value
0
16
read-only
CAPCTRL
Offset:0x84 CT16Bn Capture Control Register
0x84
32
read-write
n
0x0
0x0
CAP0EN
CAP0 function enable
3
4
read-write
Disable
Disable
0
Enable
Enable CAP0 function for external Capture pin
1
CAP0FE
Capture/Reset on CT16Bn_CAP0 signal falling edge
1
2
read-write
Disable
Disable
0
Enable
A sequence of 1 then 0 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CAP0IE
Interrupt on CT16Bn_CAP0 event
2
3
read-write
Disable
Disable
0
Enable
A CAP0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1
CAP0RE
Capture/Reset on CT16Bn_CAP0 signal rising edge
0
1
read-write
Disable
Disable
0
Enable
A sequence of 0 then 1 on CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
1
CNTCTRL
Offset:0x10 CT16Bn Counter Control Register
0x10
32
read-write
n
0x0
0x0
CTM
Counter/Timer Mode
0
2
read-write
Timer Mode
Timer Mode: every rising PCLK edge
0
Counter Mode 1
TC is incremented on rising edges on the CAP0 input selected by CIS bits.
1
Counter Mode 2
TC is incremented on falling edges on the CAP0 input selected by CIS bits.
2
Counter Mode 3
TC is incremented on both edges on the CAP0 input selected by CIS bits.
3
EM
Offset:0x8C CT16Bn External Match Register
0x8C
32
read-write
n
0x0
0x0
EM0
When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output.
0
1
read-write
EM1
When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output.
1
2
read-write
EM2
When the TC matches MR2, this bit will act according to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output.
2
3
read-write
EM3
When the TC matches MR3, this bit will act according to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output.
3
4
read-write
EMC0
CT16Bn_PWM0 functionality
4
6
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM0 pin is LOW
1
High
CT16Bn_PWM0 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM0 pin
3
EMC1
CT16Bn_PWM1 functionality
6
8
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM1 pin is LOW
1
High
CT16Bn_PWM1 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM1 pin
3
EMC2
CT16Bn_PWM2 functionality
8
10
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM2 pin is LOW
1
High
CT16Bn_PWM2 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM2 pin
3
EMC3
CT16Bn_PWM3 functionality
10
12
read-write
Do Nothing
Do nothing
0
Low
CT16Bn_PWM3 pin is LOW
1
High
CT16Bn_PWM3 pin is HIGH
2
Toggle
Toggle CT16Bn_PWM3 pin
3
PWMKEY
PWM register key.
24
32
write-only
IC
Offset:0xAC CT16Bn Interrupt Clear Register
0xAC
32
write-only
n
0x0
0x0
CAP0IC
CAP0IF clear bit
4
5
write-only
No effect
No effect
0
Clear
Clear CAP0IF
1
MR0IC
MR0IF clear bit
0
1
write-only
No effect
No effect
0
Clear
Clear MR0IF
1
MR1IC
MR1IF clear bit
1
2
write-only
No effect
No effect
0
Clear
Clear MR1IF
1
MR2IC
MR2IF clear bit
2
3
write-only
No effect
No effect
0
Clear
Clear MR2IF
1
MR3IC
MR3IF clear bit
3
4
write-only
No effect
No effect
0
Clear
Clear MR3IF
1
MR9IC
MR9IF clear bit
5
6
write-only
No effect
No effect
0
Clear
Clear MR9IF
1
MCTRL
Offset:0x14 CT16Bn Match Control Register
0x14
32
read-write
n
0x0
0x0
MR0IE
Enable generating an interrupt when MR0 matches TC
0
1
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR0 matches TC
1
MR0RST
Enable reset TC when MR0 matches TC
1
2
read-write
Disable
Disable
0
Enable
Reset TC when MR0 matches TC
1
MR0STOP
Stop TC and PC and clear CEN bit when MR0 matches TC
2
3
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR0 matches TC
1
MR1IE
Enable generating an interrupt when MR1 matches TC
3
4
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR1 matches TC
1
MR1RST
Enable reset TC when MR1 matches TC
4
5
read-write
Disable
Disable
0
Enable
Reset TC when MR1 matches TC
1
MR1STOP
Stop TC and PC and clear CEN bit when MR1 matches TC
5
6
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR1 matches TC
1
MR2IE
Enable generating an interrupt when MR2 matches TC
6
7
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR2 matches TC
1
MR2RST
Enable reset TC when MR2 matches TC
7
8
read-write
Disable
Disable
0
Enable
Reset TC when MR2 matches TC
1
MR2STOP
Stop TC and PC and clear CEN bit when MR2 matches TC
8
9
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR2 matches TC
1
MR3IE
Enable generating an interrupt when MR3 matches TC
9
10
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR3 matches TC
1
MR3RST
Enable reset TC when MR3 matches TC
10
11
read-write
Disable
Disable
0
Enable
Reset TC when MR3 matches TC
1
MR3STOP
Stop TC and PC and clear CEN bit when MR3 matches TC
11
12
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR3 matches TC
1
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the value in the TC
21
22
read-write
Disable
Disable
0
Enable
Generating an interrupt when MR9 matches TC
1
MR9RST
Enable reset TC when MR9 matches TC
22
23
read-write
Disable
Disable
0
Enable
Reset TC when MR9 matches TC
1
MR9STOP
Stop TC and PC and clear CEN bit when MR9 matches TC
23
24
read-write
Disable
Disable
0
Enable
Stop TC and PC and clear CEN bit when MR9 matches TC
1
PWMKEY
PWM register key.
24
32
write-only
MR0
Offset:0x20 CT16Bn MR0 Register
0x20
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key.
24
32
write-only
MR1
Offset:0x24 CT16Bn MR1 Register
0x24
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
MR2
Offset:0x28 CT16Bn MR2 Register
0x28
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
MR3
Offset:0x2C CT16Bn MR3 Register
0x2C
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
MR9
Offset:0x44 CT16Bn MR9 Register
0x44
32
read-write
n
0x0
0x0
MR
Timer counter match value
0
16
read-write
PWMKEY
PWM register key
24
32
write-only
PC
Offset:0x0C CT16Bn Prescale Counter Register
0xC
32
read-write
n
0x0
0x0
PC
Prescaler Counter
0
8
read-write
PRE
Offset:0x08 CT16Bn Prescale Register
0x8
32
read-write
n
0x0
0x0
PRE
Prescalzer
0
8
read-write
PWMCTRL
Offset:0x98 CT16Bn PWM Control Register
0x98
32
read-write
n
0x0
0x0
PWM0EN
PWM0 enable
0
1
read-write
Disable
CT16Bn_PWM0 is controlled by EM0
0
Enable
Enable PWM mode for CT16Bn_PWM0
1
PWM0IOEN
CT16Bn_PWM0/GPIO selection
20
21
read-write
Disable
CT16Bn_PWM0 pin is act as GPIO
0
Enable
CT16Bn_PWM0 pin act as match output, and output depends on PWM0EN bit
1
PWM0MODE
PWM0 output mode
4
6
read-write
PWM mode 1
During up-counting, PWM0 is 0 when TC is less than MR0.
0
PWM mode 2
During up-counting, PWM0 is 1 when TC is less than MR0.
1
Force 0
PWM0 is forced to 0
2
Force 1
PWM0 is forced to 1
3
PWM1EN
PWM1 enable
1
2
read-write
Disable
CT16Bn_PWM1 is controlled by EM1
0
Enable
Enable PWM mode for CT16Bn_PWM1
1
PWM1IOEN
CT16Bn_PWM1/GPIO selection
21
22
read-write
Disable
CT16Bn_PWM1 pin is act as GPIO
0
Enable
CT16Bn_PWM1 pin act as match output, and output depends on PWM1EN bit
1
PWM1MODE
PWM1 output mode
6
8
read-write
PWM mode 1
During up-counting, PWM1 is 0 when TC is less than MR1.
0
PWM mode 2
During up-counting, PWM1 is 1 when TC is less than MR1.
1
Force 0
PWM1 is forced to 0
2
Force 1
PWM1 is forced to 1
3
PWM2EN
PWM2 enable
2
3
read-write
Disable
CT16Bn_PWM2 is controlled by EM2
0
Enable
Enable PWM mode for CT16Bn_PWM2
1
PWM2IOEN
CT16Bn_PWM2/GPIO selection
22
23
read-write
Disable
CT16Bn_PWM2 pin is act as GPIO
0
Enable
CT16Bn_PWM2 pin act as match output, and output depends on PWM2EN bit
1
PWM2MODE
PWM2 output mode
8
10
read-write
PWM mode 1
During up-counting, PWM2 is 0 when TC is less than MR2.
0
PWM mode 2
During up-counting, PWM2 is 1 when TC is less than MR2.
1
Force 0
PWM2 is forced to 0
2
Force 1
PWM2 is forced to 1
3
PWM3EN
PWM2 enable
3
4
read-write
Disable
CT16Bn_PWM3 is controlled by EM3
0
Enable
Enable PWM mode for CT16Bn_PWM3
1
PWM3IOEN
CT16Bn_PWM3/GPIO selection
23
24
read-write
Disable
CT16Bn_PWM3 pin is act as GPIO
0
Enable
CT16Bn_PWM3 pin act as match output, and output depends on PWM3EN bit
1
PWM3MODE
PWM3 output mode
10
12
read-write
PWM mode 1
During up-counting, PWM3 is 0 when TC is less than MR3.
0
PWM mode 2
During up-counting, PWM3 is 1 when TC is less than MR3.
1
Force 0
PWM3 is forced to 0
2
Force 1
PWM3 is forced to 1
3
PWMKEY
PWM register key.
24
32
write-only
RIS
Offset:0xA8 CT16Bn Raw Interrupt Status Register
0xA8
32
read-only
n
0x0
0x0
CAP0IF
Capture channel 0 interrupt flag
4
5
read-only
No
No interrupt on CAP0
0
Met interrupt requirements
Interrupt requirements met on CAP0
1
MR0IF
Match channel 0 interrupt flag
0
1
read-only
No interrupt
No interrupt on match channel 0
0
Met interrupt requirements
Interrupt requirements met on match channel 0
1
MR1IF
Match channel 1 interrupt flag
1
2
read-only
No interrupt
No interrupt on match channel 1
0
Met interrupt requirements
Interrupt requirements met on match channel 1
1
MR2IF
Match channel 2 interrupt flag
2
3
read-only
No interrupt
No interrupt on match channel 2
0
Met interrupt requirements
Interrupt requirements met on match channel 2
1
MR3IF
Match channel 3 interrupt flag
3
4
read-only
No interrupt
No interrupt on match channel 3
0
Met interrupt requirements
Interrupt requirements met on match channel 3
1
MR9IF
Match channel 9 interrupt flag
5
6
read-only
No interrupt
No interrupt on match channel 9
0
Met interrupt requirements
Interrupt requirements met on match channel 9
1
TC
Offset:0x04 CT16Bn Timer Counter Register
0x4
32
read-write
n
0x0
0x0
TC
Timer Counter
0
16
read-write
TMRCTRL
Offset:0x00 CT16Bn Timer Control Register
0x0
32
read-write
n
0x0
0x0
CEN
Counter enable
0
1
read-write
Disable
Disable counter
0
Enable
Enable Timer Counter and Prescale Counter for counting
1
CLKSEL
PCLK source
2
4
read-write
HCLK
CT16Bn PCLK source=HCLK
0
PLL_VCO
CT16Bn PCLK source=PLL_VCO
1
ELS Xtal
CT16Bn PCLK source=ELS Xtal
2
CM
Counting mode selection
4
7
read-write
Up-counting mode
Edge-aligned Up-counting mode
0
Down-counting mode
Edge-aligned Down-counting mode
1
Center-aligned counting mode 1
The match interrupt flag is set during the down-counting period
2
Center-aligned counting mode 2
The match interrupt flag is set during the up-counting period
4
Center-aligned counting mode 3
The match interrupt flag is set during both up-counting and down-counting period
6
CRST
Counter Reset
1
2
read-write
Disable
Disable
0
Reset Counter
Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK
1
SN_EBI
External Bus Interface
EBI
0x0
0x0
0x2000
registers
n
EBI
External Bus Interface
22
ALCTRL
Offset:0x4 EBI Address Latch Control Register
0x4
32
read-write
n
0x0
0x0
AL0
Bank 0 address length=AL0+16
0
4
read-write
0000b
AL0=0
0
0001b
AL0=1
1
1010b
AL0=10
10
1011b
AL0=10
11
1100b
AL0=10
12
1101b
AL0=10
13
1110b
AL0=10
14
1111b
AL0=10
15
0010b
AL0=2
2
0011b
AL0=3
3
0100b
AL0=4
4
0101b
AL0=5
5
0110b
AL0=6
6
0111b
AL0=7
7
1000b
AL0=8
8
1001b
AL0=9
9
AL1
Bank 1 address length=AL1+16
4
8
read-write
0000b
AL1=0
0
0001b
AL1=1
1
1010b
AL1=10
10
1011b
AL1=10
11
1100b
AL1=10
12
1101b
AL1=10
13
1110b
AL1=10
14
1111b
AL1=10
15
0010b
AL1=2
2
0011b
AL1=3
3
0100b
AL1=4
4
0101b
AL1=5
5
0110b
AL1=6
6
0111b
AL1=7
7
1000b
AL1=8
8
1001b
AL1=9
9
AL2
Bank 2 address length=AL2+16
8
12
read-write
0000b
AL2=0
0
0001b
AL2=1
1
1010b
AL2=10
10
1011b
AL2=10
11
1100b
AL2=10
12
1101b
AL2=10
13
1110b
AL2=10
14
1111b
AL2=10
15
0010b
AL2=2
2
0011b
AL2=3
3
0100b
AL2=4
4
0101b
AL2=5
5
0110b
AL2=6
6
0111b
AL2=7
7
1000b
AL2=8
8
1001b
AL2=9
9
AL3
Bank 3 address length=AL3+16
12
16
read-write
0000b
AL3=0
0
0001b
AL3=1
1
1010b
AL3=10
10
1011b
AL3=10
11
1100b
AL3=10
12
1101b
AL3=10
13
1110b
AL3=10
14
1111b
AL3=10
15
0010b
AL3=2
2
0011b
AL3=3
3
0100b
AL3=4
4
0101b
AL3=5
5
0110b
AL3=6
6
0111b
AL3=7
7
1000b
AL3=8
8
1001b
AL3=9
9
CTRL
Offset:0x0 EBI Control Register
0x0
32
read-write
n
0x0
0x0
ARDY0EN
ARDY of bank 0 enable bit
16
17
read-write
Disable
Disable bank 0 ARDY function
0
Enable
Enable bank 0 ARDY function
1
ARDY1EN
ARDY of bank 1 enable bit
17
18
read-write
Disable
Disable bank 1 ARDY function
0
Enable
Enable bank 1 ARDY function
1
ARDY2EN
ARDY of bank 2 enable bit
18
19
read-write
Disable
Disable bank 2 ARDY function
0
Enable
Enable bank 2 ARDY function
1
ARDY3EN
ARDY of bank 3 enable bit
19
20
read-write
Disable
Disable bank 3 ARDY function
0
Enable
Enable bank 3 ARDY function
1
BANK0EN
EBI bank 0 enable bit
8
9
read-write
Disable
Disable bank 0
0
Enable
Enable bank 0
1
BANK1EN
EBI bank 1 enable bit
9
10
read-write
Disable
Disable bank 1
0
Enable
Enable bank 1
1
BANK2EN
EBI bank 2 enable bit
10
11
read-write
Disable
Disable bank 2
0
Enable
Enable bank 2
1
BANK3EN
EBI bank 3 enable bit
11
12
read-write
Disable
Disable bank 3
0
Enable
Enable bank 3
1
BC0EN
Byte control of bank 0 enable bit
12
13
read-write
Disable
Disable byte control of bank 0
0
Enable
Enable byte control of bank 0
1
BC1EN
Byte control of bank 1 enable bit
13
14
read-write
Disable
Disable byte control of bank 1
0
Enable
Enable byte control of bank 1
1
BC2EN
Byte control of bank 2 enable bit
14
15
read-write
Disable
Disable byte control of bank 2
0
Enable
Enable byte control of bank 2
1
BC3EN
Byte control of bank 3 enable bit
15
16
read-write
Disable
Disable byte control of bank 3
0
Enable
Enable byte control of bank 3
1
BK8080MODE0
Bank0 8080 Mode
24
25
read-write
A1D16
A1D16 mode
0
A1D8
A1D8 mode
1
BK8080MODE1
Bank1 8080 Mode
25
26
read-write
A1D16
A1D16 mode
0
A1D8
A1D8 mode
1
BK8080MODE2
Bank2 8080 Mode
26
27
read-write
A1D16
A1D16 mode
0
A1D8
A1D8 mode
1
BK8080MODE3
Bank3 8080 Mode
27
28
read-write
A1D16
A1D16 mode
0
A1D8
A1D8 mode
1
IDLETIME
Bus idle time
20
24
read-write
No
No Idle time
0
1T
Idle time=1*PCLK
1
10T
Idle time=10*PCLK
10
11T
Idle time=11*PCLK
11
12T
Idle time=12*PCLK
12
13T
Idle time=13*PCLK
13
14T
Idle time=14*PCLK
14
15T
Idle time=15*PCLK
15
2T
Idle time=2*PCLK
2
3T
Idle time=3*PCLK
3
4T
Idle time=4*PCLK
4
5T
Idle time=5*PCLK
5
6T
Idle time=6*PCLK
6
7T
Idle time=7*PCLK
7
8T
Idle time=8*PCLK
8
9T
Idle time=9*PCLK
9
MODE0
EBI bank 0 access mode
0
2
read-write
AnD8
AnD8 mode
0
AnD16
AnD16 mode
1
AnD16ALE
AnD16ALE mode
2
8080
8080 mode
3
MODE1
EBI bank 1 access mode
2
4
read-write
AnD8
AnD8 mode
0
AnD16
AnD16 mode
1
AnD16ALE
AnD16ALE mode
2
8080
8080 mode
3
MODE2
EBI bank 2 access mode
4
6
read-write
AnD8
AnD8 mode
0
AnD16
AnD16 mode
1
AnD16ALE
AnD16ALE mode
2
8080
8080 mode
3
MODE3
EBI bank 3 access mode
6
8
read-write
AnD8
AnD8 mode
0
AnD16
AnD16 mode
1
AnD16ALE
AnD16ALE mode
2
8080
8080 mode
3
CURCNT
Offset:0x6C EBI DMA Current Transfer Data Counter Register
0x6C
32
read-only
n
0x0
0x0
CURCNT
Number of data to DMA RX half count transfer
0
28
read-only
DMACNT
Offset:0x64 DMA Number of data transfer register
0x64
32
read-write
n
0x0
0x0
CNT
Number of data to DMA RX count transfer
0
28
read-write
DMACTRL
Offset:0x5C EBI DMA Control Register
0x5C
32
read-write
n
0x0
0x0
BANKSELECT
EBI Bank n select bits
2
4
read-write
BANK 0
EBI Bank 0
0
BANK 1
EBI Bank 1
1
BANK 2
EBI Bank 2
2
BANK 3
EBI Bank 3
3
DMAEN
EBI DMA enable bit
0
1
read-write
Disable
Disable EBI DMA
0
Enable
Enable EBI DMA
1
SPISELECT
SPIn select bit
1
2
read-write
SPI0
SPI0
0
SPI1
SPI1
1
DMAHTCNT
Offset:0x68 EBI DMA Half-transfer Register
0x68
32
read-write
n
0x0
0x0
HTCNT
Number of data to DMA RX half count transfer
0
28
read-write
IC
Offset:0x58 EBI Interrupt Clear Register
0x58
32
write-only
n
0x0
0x0
ACCDISIC
Select ACCDISIF flag to be cleared
1
2
write-only
No effect
No effect
0
Clear
Clear ACCDISIF flag
1
ARDYTOIC
Select ARDYTOIF flag to be cleared
0
1
write-only
No effect
No effect
0
Clear
Clear ARDYIF flag
1
DMAHTIC
Select DMA half-transfer flag to be cleared
4
5
write-only
No effect
No effect
0
Clear
Clear DMAHTIF flag
1
DMATCIC
Select DMA transfer complete flag to be cleared
5
6
write-only
No effect
No effect
0
Clear
Clear DMATCIF flag
1
RWERRIC
Select RWERRIF flag to be cleared
3
4
write-only
No effect
No effect
0
Clear
Clear RWERRIF flag
1
SMRSTIC
Select SMRSTIF flag to be cleared
2
3
write-only
No effect
No effect
0
Clear
Clear SMRSTIF flag
1
IE
Offset:0x50 EBI Interrupt Enable Register
0x50
32
read-write
n
0x0
0x0
ACCDISEN
Interrupt for accessing the disabled bank enable bit
1
2
read-write
Disable
Disable ACCDIS interrupt
0
Enable
Enable ACCDIS interrupt
1
ARDYTOEN
EBI asynchronous ready time-out interrupt enable bit
0
1
read-write
Disable
Disable ARDYTO interrupt
0
Enable
Enable ARDYTO interrupt
1
DMAHTIE
DMA half-transfer interrupt enable bit
4
5
read-write
Disable
Disable DMAHT interrupt
0
Enable
Enable DMAHT interrupt
1
DMATCIE
DMA transfer complete interrupt enable bit
5
6
read-write
Disable
Disable DMATC interrupt
0
Enable
Enable DMATC interrupt
1
RWERREN
Interrupt for read/writer error enable bit
3
4
read-write
Disable
Disable RWERR interrupt
0
Enable
Enable RWERR interrupt
1
SMRSTEN
Interrupt for issuing a transaction during EBI state machine reset period enable bit
2
3
read-write
Disable
Disable SMRST interrupt
0
Enable
Enable SMRST interrupt
1
PR0
Offset:0x40 EBI Polarity Register 0
0x40
32
read-write
n
0x0
0x0
ALEPOL
Address Latch polarity
3
4
read-only
Active Low
ALE is active low
0
Reserved
Reserved
1
ARDYPOL
Asynchronous Ready polarity
4
5
read-write
Active Low
ARDY is active low
0
Active High
ARDY is active high
1
CSPOL
Chip Select polarity
0
1
read-only
Active Low
CS is active low
0
Reserved
Reserved
1
OEPOL
Output Enable polarity
1
2
read-only
Active Low
OE is active low
0
Reserved
Reserved
1
UBLBPOL
Upper Byte and Lower Byte polarity
5
6
read-only
Active Low
Upper byte and Lower byte are active low
0
Reserved
Reserved
1
WEPOL
Write Enable polarity
2
3
read-only
Active Low
WE is active low
0
Reserved
Reserved
1
PR1
Offset:0x44 EBI Polarity Register 1
0x44
32
read-write
n
0x0
0x0
ALEPOL
Address Latch polarity
3
4
read-only
Active Low
ALE is active low
0
Reserved
Reserved
1
ARDYPOL
Asynchronous Ready polarity
4
5
read-write
Active Low
ARDY is active low
0
Active High
ARDY is active high
1
CSPOL
Chip Select polarity
0
1
read-only
Active Low
CS is active low
0
Reserved
Reserved
1
OEPOL
Output Enable polarity
1
2
read-only
Active Low
OE is active low
0
Reserved
Reserved
1
UBLBPOL
Upper Byte and Lower Byte polarity
5
6
read-only
Active Low
Upper byte and Lower byte are active low
0
Reserved
Reserved
1
WEPOL
Write Enable polarity
2
3
read-only
Active Low
WE is active low
0
Reserved
Reserved
1
PR2
Offset:0x48 EBI Polarity Register 2
0x48
32
read-write
n
0x0
0x0
ALEPOL
Address Latch polarity
3
4
read-only
Active Low
ALE is active low
0
Reserved
Reserved
1
ARDYPOL
Asynchronous Ready polarity
4
5
read-write
Active Low
ARDY is active low
0
Active High
ARDY is active high
1
CSPOL
Chip Select polarity
0
1
read-only
Active Low
CS is active low
0
Reserved
Reserved
1
OEPOL
Output Enable polarity
1
2
read-only
Active Low
OE is active low
0
Reserved
Reserved
1
UBLBPOL
Upper Byte and Lower Byte polarity
5
6
read-only
Active Low
Upper byte and Lower byte are active low
0
Reserved
Reserved
1
WEPOL
Write Enable polarity
2
3
read-only
Active Low
WE is active low
0
Reserved
Reserved
1
PR3
Offset:0x4C EBI Polarity Register 3
0x4C
32
read-write
n
0x0
0x0
ALEPOL
Address Latch polarity
3
4
read-only
Active Low
ALE is active low
0
Reserved
Reserved
1
ARDYPOL
Asynchronous Ready polarity
4
5
read-write
Active Low
ARDY is active low
0
Active High
ARDY is active high
1
CSPOL
Chip Select polarity
0
1
read-only
Active Low
CS is active low
0
Reserved
Reserved
1
OEPOL
Output Enable polarity
1
2
read-only
Active Low
OE is active low
0
Reserved
Reserved
1
UBLBPOL
Upper Byte and Lower Byte polarity
5
6
read-only
Active Low
Upper byte and Lower byte are active low
0
Reserved
Reserved
1
WEPOL
Write Enable polarity
2
3
read-only
Active Low
WE is active low
0
Reserved
Reserved
1
RIS
Offset:0x54 EBI Interrupt Flag Register
0x54
32
read-only
n
0x0
0x0
ACCDISIF
EBI accessing the disabled bank flag
1
2
read-only
Not accessing
Not accessing the disabled bank
0
Accessing
EBI is accessing the disabled bank
1
ARDYTOIF
EBI asynchronous ready time-out flag
0
1
read-only
Not timeout
ARDY Not Timeout
0
Timeout
ARDY Timeout
1
DMAHTIF
DMA half-transfer flag
4
5
read-only
No event
No half-transfer event
0
Half-transfer event
A half-transfer event occurs
1
DMATCIF
DMA transfer complete flag
5
6
read-only
No DMA transfer completed
No DMA transfer completed
0
DMA Transfer completed
A transfer complete event occurs
1
RWERRIF
EBI read/write error flag
3
4
read-only
Not error
Not read/write error
0
Error
Read/write error
1
SMRSTIF
EBI state machine reset flag
2
3
read-only
Not resetting
Not resetting the EBI state machine
0
Resetting
EBI is resetting the state machine
1
STATUS
Offset:0x8 EBI Status Register
0x8
32
read-write
n
0x0
0x0
EBIARDY
EBI Asynchronous Ready status
4
5
read-only
Inactive
EBI_ARDY is inactive
0
Active
EBI_ARDY is active
1
EBIBUSY
EBI Busy
0
1
read-only
Idle
EBI is idle
0
Busy
EBI is busy
1
EBINSRST
EBI State machine reset
8
9
read-write
Normal
Normal mode
0
Reset
Reset EBI state machine
1
TADDR0
Offset:0x10 EBI Address Timing Register 0
0x10
32
read-write
n
0x0
0x0
ADDRHOLD
Address Hold time
8
12
read-write
0000b
No Hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
ADDRSETUP
Address Setup time
0
4
read-write
0000b
1*PCLK
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
TADDR1
Offset:0x14 EBI Address Timing Register 1
0x14
32
read-write
n
0x0
0x0
ADDRHOLD
Address Hold time
8
12
read-write
0000b
No Hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
ADDRSETUP
Address Setup time
0
4
read-write
0000b
1*PCLK
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
TADDR2
Offset:0x18 EBI Address Timing Register 2
0x18
32
read-write
n
0x0
0x0
ADDRHOLD
Address Hold time
8
12
read-write
0000b
No Hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
ADDRSETUP
Address Setup time
0
4
read-write
0000b
1*PCLK
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
TADDR3
Offset:0x1C EBI Address Timing Register 3
0x1C
32
read-write
n
0x0
0x0
ADDRHOLD
Address Hold time
8
12
read-write
0000b
No address hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
ADDRSETUP
Address Setup time
0
4
read-write
0000b
1*PCLK
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
TREAD0
Offset:0x20 EBI Read Timing Register 0
0x20
32
read-write
n
0x0
0x0
RDHOLD
Read Hold time
16
20
read-write
0000b
No read hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSETUP
Read Setup time
0
4
read-write
0000b
No read setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSTRB
Read Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
TREAD1
Offset:0x24 EBI Read Timing Register 1
0x24
32
read-write
n
0x0
0x0
RDHOLD
Read Hold time
16
20
read-write
0000b
No read hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSETUP
Read Setup time
0
4
read-write
0000b
No read setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSTRB
Read Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
TREAD2
Offset:0x28 EBI Read Timing Register 2
0x28
32
read-write
n
0x0
0x0
RDHOLD
Read Hold time
16
20
read-write
0000b
No read hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSETUP
Read Setup time
0
4
read-write
0000b
No read setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSTRB
Read Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
TREAD3
Offset:0x2C EBI Read Timing Register 3
0x2C
32
read-write
n
0x0
0x0
RDHOLD
Read Hold time
16
20
read-write
0000b
No read hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSETUP
Read Setup time
0
4
read-write
0000b
No read setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
RDSTRB
Read Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
TWRITE0
Offset:0x30 EBI Write Timing Register 0
0x30
32
read-write
n
0x0
0x0
WEHOLD
Write Hold time
16
20
read-write
0000b
No write hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESETUP
Write Setup time
0
4
read-write
0000b
No write setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESTRB
Write Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
TWRITE1
Offset:0x34 EBI Write Timing Register 1
0x34
32
read-write
n
0x0
0x0
WEHOLD
Write Hold time
16
20
read-write
0000b
No write hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESETUP
Write Setup time
0
4
read-write
0000b
No write setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESTRB
Write Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
TWRITE2
Offset:0x38 EBI Write Timing Register 2
0x38
32
read-write
n
0x0
0x0
WEHOLD
Write Hold time
16
20
read-write
0000b
No write hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESETUP
Write Setup time
0
4
read-write
0000b
No write setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESTRB
Write Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
TWRITE3
Offset:0x3C EBI Write Timing Register 3
0x3C
32
read-write
n
0x0
0x0
WEHOLD
Write Hold time
16
20
read-write
0000b
No write hold time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESETUP
Write Setup time
0
4
read-write
0000b
No write setup time
0
0001b
1*PCLK
1
1010b
10*PCLK
10
1011b
11*PCLK
11
1100b
12*PCLK
12
1101b
13*PCLK
13
1110b
14*PCLK
14
1111b
15*PCLK
15
0010b
2*PCLK
2
0011b
3*PCLK
3
0100b
4*PCLK
4
0101b
5*PCLK
5
0110b
6*PCLK
6
0111b
7*PCLK
7
1000b
8*PCLK
8
1001b
9*PCLK
9
WESTRB
Write Strobe time
8
14
read-write
000000b
1*PCLK
0
000001b
1*PCLK
1
001010b
10*PCLK
10
001011b
11*PCLK
11
001100b
12*PCLK
12
001101b
13*PCLK
13
001110b
14*PCLK
14
001111b
15*PCLK
15
010000b
16*PCLK
16
010001b
17*PCLK
17
010010b
18*PCLK
18
010011b
19*PCLK
19
000010b
2*PCLK
2
010100b
20*PCLK
20
010101b
21*PCLK
21
010110b
22*PCLK
22
010111b
23*PCLK
23
011000b
24*PCLK
24
011001b
25*PCLK
25
011010b
26*PCLK
26
011011b
27*PCLK
27
011100b
28*PCLK
28
011101b
29*PCLK
29
000011b
3*PCLK
3
011110b
30*PCLK
30
011111b
31*PCLK
31
100000b
32*PCLK
32
100001b
33*PCLK
33
100010b
34*PCLK
34
100011b
35*PCLK
35
100100b
36*PCLK
36
100101b
37*PCLK
37
100110b
38*PCLK
38
100111b
39*PCLK
39
000100b
4*PCLK
4
101000b
40*PCLK
40
101001b
41*PCLK
41
101010b
42*PCLK
42
101011b
43*PCLK
43
101100b
44*PCLK
44
101101b
45*PCLK
45
101110b
46*PCLK
46
101111b
47*PCLK
47
110000b
48*PCLK
48
110001b
49*PCLK
49
000101b
5*PCLK
5
110010b
50*PCLK
50
110011b
51*PCLK
51
110100b
52*PCLK
52
110101b
53*PCLK
53
110110b
54*PCLK
54
110111b
55*PCLK
55
111000b
56*PCLK
56
111001b
57*PCLK
57
111010b
58*PCLK
58
111011b
59*PCLK
59
000110b
6*PCLK
6
111100b
60*PCLK
60
111101b
61*PCLK
61
111110b
62*PCLK
62
111111b
63*PCLK
63
000111b
7*PCLK
7
001000b
8*PCLK
8
001001b
9*PCLK
9
SN_FLASH
FLASH Memory Control Registers
FLASH
0x0
0x0
0x2000
registers
n
ADDR
Offset:0x10 Flash Address Register
0x10
32
read-write
n
0x0
0x0
CHKSUM
Offset:0x14 Flash Checksum Register
0x14
32
read-only
n
0x0
0x0
BootROM
Checksum of Boot ROM
16
32
read-only
UserROM
Checksum of User ROM
0
16
read-only
CHKSUM1
Offset:0x18 Flash Checksum Register 1
0x18
32
read-only
n
0x0
0x0
UserROM1
Checksum of User ROM 1
0
16
read-only
UserROM2
Checksum of User ROM 2
16
32
read-only
CHKSUM2
Offset:0x1C Flash Checksum Register 2
0x1C
32
read-only
n
0x0
0x0
UserROM3
Checksum of User ROM 3
0
16
read-only
UserROM4
Checksum of User ROM 4
16
32
read-only
CTRL
Offset:0x08 Flash Control Register
0x8
32
read-write
n
0x0
0x0
CHK
Checksum calculation chosen
7
8
read-write
Disable
Disable checksum calcuation
0
Enable
Trigger checksum calculation
1
MER
Mass erase mode chosen bit
2
3
read-write
0
Disable masse erase mode
0
1
Enable mass erase mode
1
PER
Page erase mode chosen bit
1
2
read-write
0
Disable page erase mode
0
1
Enable page erase mode
1
PG
Flash program mode chosen bit
0
1
read-write
0
Disable Flash program mode
0
1
Enable Flash program mode
1
START
Start erase/program operation
6
7
read-write
Stop/Finish
Stop/finish operation
0
Start
Start erase/program operation
1
DATA
Offset:0x0C Flash Data Register
0xC
32
read-write
n
0x0
0x0
LPCTRL
Offset:0x00 Flash Low Power Control Register
0x0
32
read-write
n
0x0
0x0
FMCKEY
FMC verify key
16
32
write-only
LPMODE
Flash Low Power mode selection bit
0
6
read-write
0x0
HCLK is less than 24MHz
0
0x19
HCLK is more than 24MHz, and less than or equal to 48MHz
25
0x29
HCLK is more than or equal to 24MHz, and less than or equal to 48MHz
41
0x39
HCLK is more than 48MHz
57
STATUS
Offset:0x04 Flash Status Register
0x4
32
read-write
n
0x0
0x0
BUSY
Busy flag
0
1
read-only
Idle
FMC is idle
0
Busy
Flash operation is in process
1
ERR
Erase/Error flag
2
3
read-write
No error
No error
0
Error
The address is illegal or over page boundary
1
SN_GPIO0
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P0
GPIO0
31
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR10
Clear Pn.10
10
11
write-only
No effect
No effect
0
Clear
Clear Pn.10
1
BCLR11
Clear Pn.11
11
12
write-only
No effect
No effect
0
Clear
Clear Pn.11
1
BCLR12
Clear Pn.12
12
13
write-only
No effect
No effect
0
Clear
Clear Pn.12
1
BCLR13
Clear Pn.13
13
14
write-only
No effect
No effect
0
Clear
Clear Pn.13
1
BCLR14
Clear Pn.14
14
15
write-only
No effect
No effect
0
Clear
Clear Pn.14
1
BCLR15
Clear Pn.15
15
16
write-only
No effect
No effect
0
Clear
Clear Pn.15
1
BCLR16
Clear Pn.16
16
17
write-only
No effect
No effect
0
Clear
Clear Pn.16
1
BCLR17
Clear Pn.17
17
18
write-only
No effect
No effect
0
Clear
Clear Pn.17
1
BCLR18
Clear Pn.18
18
19
write-only
No effect
No effect
0
Clear
Clear Pn.18
1
BCLR19
Clear Pn.19
19
20
write-only
No effect
No effect
0
Clear
Clear Pn.19
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET10
Set Pn.10
10
11
write-only
No effect
No effect
0
Set
Set Pn.10 to 1
1
BSET11
Set Pn.11
11
12
write-only
No effect
No effect
0
Set
Set Pn.11 to 1
1
BSET12
Set Pn.12
12
13
write-only
No effect
No effect
0
Set
Set Pn.12 to 1
1
BSET13
Set Pn.13
13
14
write-only
No effect
No effect
0
Set
Set Pn.13 to 1
1
BSET14
Set Pn.14
14
15
write-only
No effect
No effect
0
Set
Set Pn.14 to 1
1
BSET15
Set Pn.15
15
16
write-only
No effect
No effect
0
Set
Set Pn.15 to 1
1
BSET16
Set Pn.16
16
17
write-only
No effect
No effect
0
Set
Set Pn.16 to 1
1
BSET17
Set Pn.17
17
18
write-only
No effect
No effect
0
Set
Set Pn.17 to 1
1
BSET18
Set Pn.18
18
19
write-only
No effect
No effect
0
Set
Set Pn.18 to 1
1
BSET19
Set Pn.19
19
20
write-only
No effect
No effect
0
Set
Set Pn.19 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG10
Configuration of Pn.10
20
22
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG11
Configuration of Pn.11
22
24
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG12
Configuration of Pn.12
24
26
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG13
Configuration of Pn.13
26
28
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG14
Configuration of Pn.14
28
30
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG15
Configuration of Pn.15
30
32
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Offset:0x30 GPIO Port n Configuration Register 1
0x30
32
read-write
n
0x0
0x0
CFG16
Configuration of Pn.16
0
2
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG17
Configuration of Pn.17
2
4
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG18
Configuration of Pn.18
4
6
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG19
Configuration of Pn.19
6
8
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA10
Data of Pn.10
10
11
read-write
0
Pn.10 is 0
0
1
Pn.10 is 1
1
DATA11
Data of Pn.11
11
12
read-write
0
Pn.11 is 0
0
1
Pn.11 is 1
1
DATA12
Data of Pn.12
12
13
read-write
0
Pn.12 is 0
0
1
Pn.12 is 1
1
DATA13
Data of Pn.13
13
14
read-write
0
Pn.13 is 0
0
1
Pn.13 is 1
1
DATA14
Data of Pn.14
14
15
read-write
0
Pn.14 is 0
0
1
Pn.14 is 1
1
DATA15
Data of Pn.15
15
16
read-write
0
Pn.15 is 0
0
1
Pn.15 is 1
1
DATA16
Data of Pn.16
16
17
read-write
0
Pn.16 is 0
0
1
Pn.16 is 1
1
DATA17
Data of Pn.17
17
18
read-write
0
Pn.17 is 0
0
1
Pn.17 is 1
1
DATA18
Data of Pn.18
18
19
read-write
0
Pn.18 is 0
0
1
Pn.18 is 1
1
DATA19
Data of Pn.19
19
20
read-write
0
Pn.19 is 0
0
1
Pn.19 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS10
Interrupt on Pn.10 is triggered ob both edges
10
11
read-write
IEV
Interrupt on Pn.10 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.10 trigger an interrupt
1
IBS11
Interrupt on Pn.11 is triggered ob both edges
11
12
read-write
IEV
Interrupt on Pn.11 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.11 trigger an interrupt
1
IBS12
Interrupt on Pn.12 is triggered ob both edges
12
13
read-write
IEV
Interrupt on Pn.12 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.12 trigger an interrupt
1
IBS13
Interrupt on Pn.13 is triggered ob both edges
13
14
read-write
IEV
Interrupt on Pn.13 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.13 trigger an interrupt
1
IBS14
Interrupt on Pn.14 is triggered ob both edges
14
15
read-write
IEV
Interrupt on Pn.14 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.14 trigger an interrupt
1
IBS15
Interrupt on Pn.15 is triggered ob both edges
15
16
read-write
IEV
Interrupt on Pn.15 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.15 trigger an interrupt
1
IBS16
Interrupt on Pn.16 is triggered ob both edges
16
17
read-write
IEV
Interrupt on Pn.16 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.16 trigger an interrupt
1
IBS17
Interrupt on Pn.17 is triggered ob both edges
17
18
read-write
IEV
Interrupt on Pn.17 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.17 trigger an interrupt
1
IBS18
Interrupt on Pn.18 is triggered ob both edges
18
19
read-write
IEV
Interrupt on Pn.18 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.18 trigger an interrupt
1
IBS19
Interrupt on Pn.19 is triggered ob both edges
19
20
read-write
IEV
Interrupt on Pn.19 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.19 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC10
Pn.10 interrupt flag clear
10
11
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.10
1
IC11
Pn.11 interrupt flag clear
11
12
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.11
1
IC12
Pn.12 interrupt flag clear
12
13
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.12
1
IC13
Pn.13 interrupt flag clear
13
14
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.13
1
IC14
Pn.14 interrupt flag clear
14
15
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.14
1
IC15
Pn.15 interrupt flag clear
15
16
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.15
1
IC16
Pn.16 interrupt flag clear
16
17
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.16
1
IC17
Pn.17 interrupt flag clear
17
18
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.17
1
IC18
Pn.18 interrupt flag clear
18
19
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.18
1
IC19
Pn.19 interrupt flag clear
19
20
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.19
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE10
Interrupt on Pn.10 enable
10
11
read-write
Disable
Disable interrupt on Pn.10
0
Enable
Enable interrupt on Pn.10
1
IE11
Interrupt on Pn.11 enable
11
12
read-write
Disable
Disable interrupt on Pn.11
0
Enable
Enable interrupt on Pn.11
1
IE12
Interrupt on Pn.11 enable
12
13
read-write
Disable
Disable interrupt on Pn.12
0
Enable
Enable interrupt on Pn.12
1
IE13
Interrupt on Pn.13 enable
13
14
read-write
Disable
Disable interrupt on Pn.13
0
Enable
Enable interrupt on Pn.13
1
IE14
Interrupt on Pn.14 enable
14
15
read-write
Disable
Disable interrupt on Pn.14
0
Enable
Enable interrupt on Pn.14
1
IE15
Interrupt on Pn.15 enable
15
16
read-write
Disable
Disable interrupt on Pn.15
0
Enable
Enable interrupt on Pn.15
1
IE16
Interrupt on Pn.16 enable
16
17
read-write
Disable
Disable interrupt on Pn.16
0
Enable
Enable interrupt on Pn.16
1
IE17
Interrupt on Pn.17 enable
17
18
read-write
Disable
Disable interrupt on Pn.17
0
Enable
Enable interrupt on Pn.17
1
IE18
Interrupt on Pn.18 enable
18
19
read-write
Disable
Disable interrupt on Pn.18
0
Enable
Enable interrupt on Pn.18
1
IE19
Interrupt on Pn.19 enable
19
20
read-write
Disable
Disable interrupt on Pn.19
0
Enable
Enable interrupt on Pn.19
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV10
Interrupt trigged evnet on Pn.10
10
11
read-write
0
Rising edge or High level on Pn.10 triggers an interrupt
0
1
Falling edge or Low level on Pn.10 triggers an interrupt
1
IEV11
Interrupt trigged evnet on Pn.11
11
12
read-write
0
Rising edge or High level on Pn.11 triggers an interrupt
0
1
Falling edge or Low level on Pn.11 triggers an interrupt
1
IEV12
Interrupt trigged evnet on Pn.12
12
13
read-write
0
Rising edge or High level on Pn.12 triggers an interrupt
0
1
Falling edge or Low level on Pn.12 triggers an interrupt
1
IEV13
Interrupt trigged evnet on Pn.13
13
14
read-write
0
Rising edge or High level on Pn.13 triggers an interrupt
0
1
Falling edge or Low level on Pn.13 triggers an interrupt
1
IEV14
Interrupt trigged evnet on Pn.14
14
15
read-write
0
Rising edge or High level on Pn.14 triggers an interrupt
0
1
Falling edge or Low level on Pn.14 triggers an interrupt
1
IEV15
Interrupt trigged evnet on Pn.15
15
16
read-write
0
Rising edge or High level on Pn.15 triggers an interrupt
0
1
Falling edge or Low level on Pn.15 triggers an interrupt
1
IEV16
Interrupt trigged evnet on Pn.16
16
17
read-write
0
Rising edge or High level on Pn.16 triggers an interrupt
0
1
Falling edge or Low level on Pn.16 triggers an interrupt
1
IEV17
Interrupt trigged evnet on Pn.17
17
18
read-write
0
Rising edge or High level on Pn.17 triggers an interrupt
0
1
Falling edge or Low level on Pn.17 triggers an interrupt
1
IEV18
Interrupt trigged evnet on Pn.18
18
19
read-write
0
Rising edge or High level on Pn.18 triggers an interrupt
0
1
Falling edge or Low level on Pn.18 triggers an interrupt
1
IEV19
Interrupt trigged evnet on Pn.19
19
20
read-write
0
Rising edge or High level on Pn.19 triggers an interrupt
0
1
Falling edge or Low level on Pn.19 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS10
Interrupt on Pn.10 is event or edge sensitive
10
11
read-write
Edge
Interrupt on Pn.10 is edge sensitive
0
Event
Interrupt on Pn.10 is event sensitive
1
IS11
Interrupt on Pn.11 is event or edge sensitive
11
12
read-write
Edge
Interrupt on Pn.11 is edge sensitive
0
Event
Interrupt on Pn.11 is event sensitive
1
IS12
Interrupt on Pn.12 is event or edge sensitive
12
13
read-write
Edge
Interrupt on Pn.12 is edge sensitive
0
Event
Interrupt on Pn.12 is event sensitive
1
IS13
Interrupt on Pn.13 is event or edge sensitive
13
14
read-write
Edge
Interrupt on Pn.13 is edge sensitive
0
Event
Interrupt on Pn.13 is event sensitive
1
IS14
Interrupt on Pn.14 is event or edge sensitive
14
15
read-write
Edge
Interrupt on Pn.14 is edge sensitive
0
Event
Interrupt on Pn.14 is event sensitive
1
IS15
Interrupt on Pn.15 is event or edge sensitive
15
16
read-write
Edge
Interrupt on Pn.15 is edge sensitive
0
Event
Interrupt on Pn.15 is event sensitive
1
IS16
Interrupt on Pn.16 is event or edge sensitive
16
17
read-write
Edge
Interrupt on Pn.16 is edge sensitive
0
Event
Interrupt on Pn.16 is event sensitive
1
IS17
Interrupt on Pn.17 is event or edge sensitive
17
18
read-write
Edge
Interrupt on Pn.17 is edge sensitive
0
Event
Interrupt on Pn.17 is event sensitive
1
IS18
Interrupt on Pn.18 is event or edge sensitive
18
19
read-write
Edge
Interrupt on Pn.18 is edge sensitive
0
Event
Interrupt on Pn.18 is event sensitive
1
IS19
Interrupt on Pn.19 is event or edge sensitive
19
20
read-write
Edge
Interrupt on Pn.19 is edge sensitive
0
Event
Interrupt on Pn.19 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE10
Mode of Pn.10
10
11
read-write
I
Pn.10 is Input pin
0
O
Pn.10 is Output pin
1
MODE11
Mode of Pn.11
11
12
read-write
I
Pn.11 is Input pin
0
O
Pn.11 is Output pin
1
MODE12
Mode of Pn.12
12
13
read-write
I
Pn.12 is Input pin
0
O
Pn.12 is Output pin
1
MODE13
Mode of Pn.13
13
14
read-write
I
Pn.13 is Input pin
0
O
Pn.13 is Output pin
1
MODE14
Mode of Pn.14
14
15
read-write
I
Pn.14 is Input pin
0
O
Pn.14 is Output pin
1
MODE15
Mode of Pn.15
15
16
read-write
I
Pn.15 is Input pin
0
O
Pn.15 is Output pin
1
MODE16
Mode of Pn.16
16
17
read-write
I
Pn.16 is Input pin
0
O
Pn.16 is Output pin
1
MODE17
Mode of Pn.17
17
18
read-write
I
Pn.17 is Input pin
0
O
Pn.17 is Output pin
1
MODE18
Mode of Pn.18
18
19
read-write
I
Pn.18 is Input pin
0
O
Pn.18 is Output pin
1
MODE19
Mode of Pn.19
19
20
read-write
I
Pn.19 is Input pin
0
O
Pn.19 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF10
Pn.10 raw interrupt flag
10
11
read-only
0
No interrupt on Pn.10
0
1
Interrupt requirements met on Pn.10
1
IF11
Pn.11 raw interrupt flag
11
12
read-only
0
No interrupt on Pn.11
0
1
Interrupt requirements met on Pn.11
1
IF12
Pn.12 raw interrupt flag
12
13
read-only
0
No interrupt on Pn.12
0
1
Interrupt requirements met on Pn.12
1
IF13
Pn.13 raw interrupt flag
13
14
read-only
0
No interrupt on Pn.13
0
1
Interrupt requirements met on Pn.13
1
IF14
Pn.14 raw interrupt flag
14
15
read-only
0
No interrupt on Pn.14
0
1
Interrupt requirements met on Pn.14
1
IF15
Pn.15 raw interrupt flag
15
16
read-only
0
No interrupt on Pn.15
0
1
Interrupt requirements met on Pn.15
1
IF16
Pn.16 raw interrupt flag
16
17
read-only
0
No interrupt on Pn.16
0
1
Interrupt requirements met on Pn.16
1
IF17
Pn.17 raw interrupt flag
17
18
read-only
0
No interrupt on Pn.17
0
1
Interrupt requirements met on Pn.17
1
IF18
Pn.18 raw interrupt flag
18
19
read-only
0
No interrupt on Pn.18
0
1
Interrupt requirements met on Pn.18
1
IF19
Pn.19 raw interrupt flag
19
20
read-only
0
No interrupt on Pn.19
0
1
Interrupt requirements met on Pn.19
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_GPIO1
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P1
GPIO1
30
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR10
Clear Pn.10
10
11
write-only
No effect
No effect
0
Clear
Clear Pn.10
1
BCLR11
Clear Pn.11
11
12
write-only
No effect
No effect
0
Clear
Clear Pn.11
1
BCLR12
Clear Pn.12
12
13
write-only
No effect
No effect
0
Clear
Clear Pn.12
1
BCLR13
Clear Pn.13
13
14
write-only
No effect
No effect
0
Clear
Clear Pn.13
1
BCLR14
Clear Pn.14
14
15
write-only
No effect
No effect
0
Clear
Clear Pn.14
1
BCLR15
Clear Pn.15
15
16
write-only
No effect
No effect
0
Clear
Clear Pn.15
1
BCLR16
Clear Pn.16
16
17
write-only
No effect
No effect
0
Clear
Clear Pn.16
1
BCLR17
Clear Pn.17
17
18
write-only
No effect
No effect
0
Clear
Clear Pn.17
1
BCLR18
Clear Pn.18
18
19
write-only
No effect
No effect
0
Clear
Clear Pn.18
1
BCLR19
Clear Pn.19
19
20
write-only
No effect
No effect
0
Clear
Clear Pn.19
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET10
Set Pn.10
10
11
write-only
No effect
No effect
0
Set
Set Pn.10 to 1
1
BSET11
Set Pn.11
11
12
write-only
No effect
No effect
0
Set
Set Pn.11 to 1
1
BSET12
Set Pn.12
12
13
write-only
No effect
No effect
0
Set
Set Pn.12 to 1
1
BSET13
Set Pn.13
13
14
write-only
No effect
No effect
0
Set
Set Pn.13 to 1
1
BSET14
Set Pn.14
14
15
write-only
No effect
No effect
0
Set
Set Pn.14 to 1
1
BSET15
Set Pn.15
15
16
write-only
No effect
No effect
0
Set
Set Pn.15 to 1
1
BSET16
Set Pn.16
16
17
write-only
No effect
No effect
0
Set
Set Pn.16 to 1
1
BSET17
Set Pn.17
17
18
write-only
No effect
No effect
0
Set
Set Pn.17 to 1
1
BSET18
Set Pn.18
18
19
write-only
No effect
No effect
0
Set
Set Pn.18 to 1
1
BSET19
Set Pn.19
19
20
write-only
No effect
No effect
0
Set
Set Pn.19 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG10
Configuration of Pn.10
20
22
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG11
Configuration of Pn.11
22
24
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG12
Configuration of Pn.12
24
26
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG13
Configuration of Pn.13
26
28
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG14
Configuration of Pn.14
28
30
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG15
Configuration of Pn.15
30
32
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Offset:0x30 GPIO Port n Configuration Register 1
0x30
32
read-write
n
0x0
0x0
CFG16
Configuration of Pn.16
0
2
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG17
Configuration of Pn.17
2
4
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG18
Configuration of Pn.18
4
6
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG19
Configuration of Pn.19
6
8
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA10
Data of Pn.10
10
11
read-write
0
Pn.10 is 0
0
1
Pn.10 is 1
1
DATA11
Data of Pn.11
11
12
read-write
0
Pn.11 is 0
0
1
Pn.11 is 1
1
DATA12
Data of Pn.12
12
13
read-write
0
Pn.12 is 0
0
1
Pn.12 is 1
1
DATA13
Data of Pn.13
13
14
read-write
0
Pn.13 is 0
0
1
Pn.13 is 1
1
DATA14
Data of Pn.14
14
15
read-write
0
Pn.14 is 0
0
1
Pn.14 is 1
1
DATA15
Data of Pn.15
15
16
read-write
0
Pn.15 is 0
0
1
Pn.15 is 1
1
DATA16
Data of Pn.16
16
17
read-write
0
Pn.16 is 0
0
1
Pn.16 is 1
1
DATA17
Data of Pn.17
17
18
read-write
0
Pn.17 is 0
0
1
Pn.17 is 1
1
DATA18
Data of Pn.18
18
19
read-write
0
Pn.18 is 0
0
1
Pn.18 is 1
1
DATA19
Data of Pn.19
19
20
read-write
0
Pn.19 is 0
0
1
Pn.19 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS10
Interrupt on Pn.10 is triggered ob both edges
10
11
read-write
IEV
Interrupt on Pn.10 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.10 trigger an interrupt
1
IBS11
Interrupt on Pn.11 is triggered ob both edges
11
12
read-write
IEV
Interrupt on Pn.11 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.11 trigger an interrupt
1
IBS12
Interrupt on Pn.12 is triggered ob both edges
12
13
read-write
IEV
Interrupt on Pn.12 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.12 trigger an interrupt
1
IBS13
Interrupt on Pn.13 is triggered ob both edges
13
14
read-write
IEV
Interrupt on Pn.13 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.13 trigger an interrupt
1
IBS14
Interrupt on Pn.14 is triggered ob both edges
14
15
read-write
IEV
Interrupt on Pn.14 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.14 trigger an interrupt
1
IBS15
Interrupt on Pn.15 is triggered ob both edges
15
16
read-write
IEV
Interrupt on Pn.15 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.15 trigger an interrupt
1
IBS16
Interrupt on Pn.16 is triggered ob both edges
16
17
read-write
IEV
Interrupt on Pn.16 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.16 trigger an interrupt
1
IBS17
Interrupt on Pn.17 is triggered ob both edges
17
18
read-write
IEV
Interrupt on Pn.17 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.17 trigger an interrupt
1
IBS18
Interrupt on Pn.18 is triggered ob both edges
18
19
read-write
IEV
Interrupt on Pn.18 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.18 trigger an interrupt
1
IBS19
Interrupt on Pn.19 is triggered ob both edges
19
20
read-write
IEV
Interrupt on Pn.19 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.19 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC10
Pn.10 interrupt flag clear
10
11
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.10
1
IC11
Pn.11 interrupt flag clear
11
12
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.11
1
IC12
Pn.12 interrupt flag clear
12
13
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.12
1
IC13
Pn.13 interrupt flag clear
13
14
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.13
1
IC14
Pn.14 interrupt flag clear
14
15
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.14
1
IC15
Pn.15 interrupt flag clear
15
16
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.15
1
IC16
Pn.16 interrupt flag clear
16
17
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.16
1
IC17
Pn.17 interrupt flag clear
17
18
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.17
1
IC18
Pn.18 interrupt flag clear
18
19
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.18
1
IC19
Pn.19 interrupt flag clear
19
20
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.19
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE10
Interrupt on Pn.10 enable
10
11
read-write
Disable
Disable interrupt on Pn.10
0
Enable
Enable interrupt on Pn.10
1
IE11
Interrupt on Pn.11 enable
11
12
read-write
Disable
Disable interrupt on Pn.11
0
Enable
Enable interrupt on Pn.11
1
IE12
Interrupt on Pn.11 enable
12
13
read-write
Disable
Disable interrupt on Pn.12
0
Enable
Enable interrupt on Pn.12
1
IE13
Interrupt on Pn.13 enable
13
14
read-write
Disable
Disable interrupt on Pn.13
0
Enable
Enable interrupt on Pn.13
1
IE14
Interrupt on Pn.14 enable
14
15
read-write
Disable
Disable interrupt on Pn.14
0
Enable
Enable interrupt on Pn.14
1
IE15
Interrupt on Pn.15 enable
15
16
read-write
Disable
Disable interrupt on Pn.15
0
Enable
Enable interrupt on Pn.15
1
IE16
Interrupt on Pn.16 enable
16
17
read-write
Disable
Disable interrupt on Pn.16
0
Enable
Enable interrupt on Pn.16
1
IE17
Interrupt on Pn.17 enable
17
18
read-write
Disable
Disable interrupt on Pn.17
0
Enable
Enable interrupt on Pn.17
1
IE18
Interrupt on Pn.18 enable
18
19
read-write
Disable
Disable interrupt on Pn.18
0
Enable
Enable interrupt on Pn.18
1
IE19
Interrupt on Pn.19 enable
19
20
read-write
Disable
Disable interrupt on Pn.19
0
Enable
Enable interrupt on Pn.19
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV10
Interrupt trigged evnet on Pn.10
10
11
read-write
0
Rising edge or High level on Pn.10 triggers an interrupt
0
1
Falling edge or Low level on Pn.10 triggers an interrupt
1
IEV11
Interrupt trigged evnet on Pn.11
11
12
read-write
0
Rising edge or High level on Pn.11 triggers an interrupt
0
1
Falling edge or Low level on Pn.11 triggers an interrupt
1
IEV12
Interrupt trigged evnet on Pn.12
12
13
read-write
0
Rising edge or High level on Pn.12 triggers an interrupt
0
1
Falling edge or Low level on Pn.12 triggers an interrupt
1
IEV13
Interrupt trigged evnet on Pn.13
13
14
read-write
0
Rising edge or High level on Pn.13 triggers an interrupt
0
1
Falling edge or Low level on Pn.13 triggers an interrupt
1
IEV14
Interrupt trigged evnet on Pn.14
14
15
read-write
0
Rising edge or High level on Pn.14 triggers an interrupt
0
1
Falling edge or Low level on Pn.14 triggers an interrupt
1
IEV15
Interrupt trigged evnet on Pn.15
15
16
read-write
0
Rising edge or High level on Pn.15 triggers an interrupt
0
1
Falling edge or Low level on Pn.15 triggers an interrupt
1
IEV16
Interrupt trigged evnet on Pn.16
16
17
read-write
0
Rising edge or High level on Pn.16 triggers an interrupt
0
1
Falling edge or Low level on Pn.16 triggers an interrupt
1
IEV17
Interrupt trigged evnet on Pn.17
17
18
read-write
0
Rising edge or High level on Pn.17 triggers an interrupt
0
1
Falling edge or Low level on Pn.17 triggers an interrupt
1
IEV18
Interrupt trigged evnet on Pn.18
18
19
read-write
0
Rising edge or High level on Pn.18 triggers an interrupt
0
1
Falling edge or Low level on Pn.18 triggers an interrupt
1
IEV19
Interrupt trigged evnet on Pn.19
19
20
read-write
0
Rising edge or High level on Pn.19 triggers an interrupt
0
1
Falling edge or Low level on Pn.19 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS10
Interrupt on Pn.10 is event or edge sensitive
10
11
read-write
Edge
Interrupt on Pn.10 is edge sensitive
0
Event
Interrupt on Pn.10 is event sensitive
1
IS11
Interrupt on Pn.11 is event or edge sensitive
11
12
read-write
Edge
Interrupt on Pn.11 is edge sensitive
0
Event
Interrupt on Pn.11 is event sensitive
1
IS12
Interrupt on Pn.12 is event or edge sensitive
12
13
read-write
Edge
Interrupt on Pn.12 is edge sensitive
0
Event
Interrupt on Pn.12 is event sensitive
1
IS13
Interrupt on Pn.13 is event or edge sensitive
13
14
read-write
Edge
Interrupt on Pn.13 is edge sensitive
0
Event
Interrupt on Pn.13 is event sensitive
1
IS14
Interrupt on Pn.14 is event or edge sensitive
14
15
read-write
Edge
Interrupt on Pn.14 is edge sensitive
0
Event
Interrupt on Pn.14 is event sensitive
1
IS15
Interrupt on Pn.15 is event or edge sensitive
15
16
read-write
Edge
Interrupt on Pn.15 is edge sensitive
0
Event
Interrupt on Pn.15 is event sensitive
1
IS16
Interrupt on Pn.16 is event or edge sensitive
16
17
read-write
Edge
Interrupt on Pn.16 is edge sensitive
0
Event
Interrupt on Pn.16 is event sensitive
1
IS17
Interrupt on Pn.17 is event or edge sensitive
17
18
read-write
Edge
Interrupt on Pn.17 is edge sensitive
0
Event
Interrupt on Pn.17 is event sensitive
1
IS18
Interrupt on Pn.18 is event or edge sensitive
18
19
read-write
Edge
Interrupt on Pn.18 is edge sensitive
0
Event
Interrupt on Pn.18 is event sensitive
1
IS19
Interrupt on Pn.19 is event or edge sensitive
19
20
read-write
Edge
Interrupt on Pn.19 is edge sensitive
0
Event
Interrupt on Pn.19 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE10
Mode of Pn.10
10
11
read-write
I
Pn.10 is Input pin
0
O
Pn.10 is Output pin
1
MODE11
Mode of Pn.11
11
12
read-write
I
Pn.11 is Input pin
0
O
Pn.11 is Output pin
1
MODE12
Mode of Pn.12
12
13
read-write
I
Pn.12 is Input pin
0
O
Pn.12 is Output pin
1
MODE13
Mode of Pn.13
13
14
read-write
I
Pn.13 is Input pin
0
O
Pn.13 is Output pin
1
MODE14
Mode of Pn.14
14
15
read-write
I
Pn.14 is Input pin
0
O
Pn.14 is Output pin
1
MODE15
Mode of Pn.15
15
16
read-write
I
Pn.15 is Input pin
0
O
Pn.15 is Output pin
1
MODE16
Mode of Pn.16
16
17
read-write
I
Pn.16 is Input pin
0
O
Pn.16 is Output pin
1
MODE17
Mode of Pn.17
17
18
read-write
I
Pn.17 is Input pin
0
O
Pn.17 is Output pin
1
MODE18
Mode of Pn.18
18
19
read-write
I
Pn.18 is Input pin
0
O
Pn.18 is Output pin
1
MODE19
Mode of Pn.19
19
20
read-write
I
Pn.19 is Input pin
0
O
Pn.19 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF10
Pn.10 raw interrupt flag
10
11
read-only
0
No interrupt on Pn.10
0
1
Interrupt requirements met on Pn.10
1
IF11
Pn.11 raw interrupt flag
11
12
read-only
0
No interrupt on Pn.11
0
1
Interrupt requirements met on Pn.11
1
IF12
Pn.12 raw interrupt flag
12
13
read-only
0
No interrupt on Pn.12
0
1
Interrupt requirements met on Pn.12
1
IF13
Pn.13 raw interrupt flag
13
14
read-only
0
No interrupt on Pn.13
0
1
Interrupt requirements met on Pn.13
1
IF14
Pn.14 raw interrupt flag
14
15
read-only
0
No interrupt on Pn.14
0
1
Interrupt requirements met on Pn.14
1
IF15
Pn.15 raw interrupt flag
15
16
read-only
0
No interrupt on Pn.15
0
1
Interrupt requirements met on Pn.15
1
IF16
Pn.16 raw interrupt flag
16
17
read-only
0
No interrupt on Pn.16
0
1
Interrupt requirements met on Pn.16
1
IF17
Pn.17 raw interrupt flag
17
18
read-only
0
No interrupt on Pn.17
0
1
Interrupt requirements met on Pn.17
1
IF18
Pn.18 raw interrupt flag
18
19
read-only
0
No interrupt on Pn.18
0
1
Interrupt requirements met on Pn.18
1
IF19
Pn.19 raw interrupt flag
19
20
read-only
0
No interrupt on Pn.19
0
1
Interrupt requirements met on Pn.19
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_GPIO2
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P2
GPIO2
29
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR10
Clear Pn.10
10
11
write-only
No effect
No effect
0
Clear
Clear Pn.10
1
BCLR11
Clear Pn.11
11
12
write-only
No effect
No effect
0
Clear
Clear Pn.11
1
BCLR12
Clear Pn.12
12
13
write-only
No effect
No effect
0
Clear
Clear Pn.12
1
BCLR13
Clear Pn.13
13
14
write-only
No effect
No effect
0
Clear
Clear Pn.13
1
BCLR14
Clear Pn.14
14
15
write-only
No effect
No effect
0
Clear
Clear Pn.14
1
BCLR15
Clear Pn.15
15
16
write-only
No effect
No effect
0
Clear
Clear Pn.15
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET10
Set Pn.10
10
11
write-only
No effect
No effect
0
Set
Set Pn.10 to 1
1
BSET11
Set Pn.11
11
12
write-only
No effect
No effect
0
Set
Set Pn.11 to 1
1
BSET12
Set Pn.12
12
13
write-only
No effect
No effect
0
Set
Set Pn.12 to 1
1
BSET13
Set Pn.13
13
14
write-only
No effect
No effect
0
Set
Set Pn.13 to 1
1
BSET14
Set Pn.14
14
15
write-only
No effect
No effect
0
Set
Set Pn.14 to 1
1
BSET15
Set Pn.15
15
16
write-only
No effect
No effect
0
Set
Set Pn.15 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG10
Configuration of Pn.10
20
22
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG11
Configuration of Pn.11
22
24
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG12
Configuration of Pn.12
24
26
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG13
Configuration of Pn.13
26
28
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG14
Configuration of Pn.14
28
30
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG15
Configuration of Pn.15
30
32
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA10
Data of Pn.10
10
11
read-write
0
Pn.10 is 0
0
1
Pn.10 is 1
1
DATA11
Data of Pn.11
11
12
read-write
0
Pn.11 is 0
0
1
Pn.11 is 1
1
DATA12
Data of Pn.12
12
13
read-write
0
Pn.12 is 0
0
1
Pn.12 is 1
1
DATA13
Data of Pn.13
13
14
read-write
0
Pn.13 is 0
0
1
Pn.13 is 1
1
DATA14
Data of Pn.14
14
15
read-write
0
Pn.14 is 0
0
1
Pn.14 is 1
1
DATA15
Data of Pn.15
15
16
read-write
0
Pn.15 is 0
0
1
Pn.15 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS10
Interrupt on Pn.10 is triggered ob both edges
10
11
read-write
IEV
Interrupt on Pn.10 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.10 trigger an interrupt
1
IBS11
Interrupt on Pn.11 is triggered ob both edges
11
12
read-write
IEV
Interrupt on Pn.11 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.11 trigger an interrupt
1
IBS12
Interrupt on Pn.12 is triggered ob both edges
12
13
read-write
IEV
Interrupt on Pn.12 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.12 trigger an interrupt
1
IBS13
Interrupt on Pn.13 is triggered ob both edges
13
14
read-write
IEV
Interrupt on Pn.13 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.13 trigger an interrupt
1
IBS14
Interrupt on Pn.14 is triggered ob both edges
14
15
read-write
IEV
Interrupt on Pn.14 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.14 trigger an interrupt
1
IBS15
Interrupt on Pn.15 is triggered ob both edges
15
16
read-write
IEV
Interrupt on Pn.15 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.15 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC10
Pn.10 interrupt flag clear
10
11
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.10
1
IC11
Pn.11 interrupt flag clear
11
12
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.11
1
IC12
Pn.12 interrupt flag clear
12
13
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.12
1
IC13
Pn.13 interrupt flag clear
13
14
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.13
1
IC14
Pn.14 interrupt flag clear
14
15
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.14
1
IC15
Pn.15 interrupt flag clear
15
16
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.15
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE10
Interrupt on Pn.10 enable
10
11
read-write
Disable
Disable interrupt on Pn.10
0
Enable
Enable interrupt on Pn.10
1
IE11
Interrupt on Pn.11 enable
11
12
read-write
Disable
Disable interrupt on Pn.11
0
Enable
Enable interrupt on Pn.11
1
IE12
Interrupt on Pn.11 enable
12
13
read-write
Disable
Disable interrupt on Pn.12
0
Enable
Enable interrupt on Pn.12
1
IE13
Interrupt on Pn.13 enable
13
14
read-write
Disable
Disable interrupt on Pn.13
0
Enable
Enable interrupt on Pn.13
1
IE14
Interrupt on Pn.14 enable
14
15
read-write
Disable
Disable interrupt on Pn.14
0
Enable
Enable interrupt on Pn.14
1
IE15
Interrupt on Pn.15 enable
15
16
read-write
Disable
Disable interrupt on Pn.15
0
Enable
Enable interrupt on Pn.15
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV10
Interrupt trigged evnet on Pn.10
10
11
read-write
0
Rising edge or High level on Pn.10 triggers an interrupt
0
1
Falling edge or Low level on Pn.10 triggers an interrupt
1
IEV11
Interrupt trigged evnet on Pn.11
11
12
read-write
0
Rising edge or High level on Pn.11 triggers an interrupt
0
1
Falling edge or Low level on Pn.11 triggers an interrupt
1
IEV12
Interrupt trigged evnet on Pn.12
12
13
read-write
0
Rising edge or High level on Pn.12 triggers an interrupt
0
1
Falling edge or Low level on Pn.12 triggers an interrupt
1
IEV13
Interrupt trigged evnet on Pn.13
13
14
read-write
0
Rising edge or High level on Pn.13 triggers an interrupt
0
1
Falling edge or Low level on Pn.13 triggers an interrupt
1
IEV14
Interrupt trigged evnet on Pn.14
14
15
read-write
0
Rising edge or High level on Pn.14 triggers an interrupt
0
1
Falling edge or Low level on Pn.14 triggers an interrupt
1
IEV15
Interrupt trigged evnet on Pn.15
15
16
read-write
0
Rising edge or High level on Pn.15 triggers an interrupt
0
1
Falling edge or Low level on Pn.15 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS10
Interrupt on Pn.10 is event or edge sensitive
10
11
read-write
Edge
Interrupt on Pn.10 is edge sensitive
0
Event
Interrupt on Pn.10 is event sensitive
1
IS11
Interrupt on Pn.11 is event or edge sensitive
11
12
read-write
Edge
Interrupt on Pn.11 is edge sensitive
0
Event
Interrupt on Pn.11 is event sensitive
1
IS12
Interrupt on Pn.12 is event or edge sensitive
12
13
read-write
Edge
Interrupt on Pn.12 is edge sensitive
0
Event
Interrupt on Pn.12 is event sensitive
1
IS13
Interrupt on Pn.13 is event or edge sensitive
13
14
read-write
Edge
Interrupt on Pn.13 is edge sensitive
0
Event
Interrupt on Pn.13 is event sensitive
1
IS14
Interrupt on Pn.14 is event or edge sensitive
14
15
read-write
Edge
Interrupt on Pn.14 is edge sensitive
0
Event
Interrupt on Pn.14 is event sensitive
1
IS15
Interrupt on Pn.15 is event or edge sensitive
15
16
read-write
Edge
Interrupt on Pn.15 is edge sensitive
0
Event
Interrupt on Pn.15 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE10
Mode of Pn.10
10
11
read-write
I
Pn.10 is Input pin
0
O
Pn.10 is Output pin
1
MODE11
Mode of Pn.11
11
12
read-write
I
Pn.11 is Input pin
0
O
Pn.11 is Output pin
1
MODE12
Mode of Pn.12
12
13
read-write
I
Pn.12 is Input pin
0
O
Pn.12 is Output pin
1
MODE13
Mode of Pn.13
13
14
read-write
I
Pn.13 is Input pin
0
O
Pn.13 is Output pin
1
MODE14
Mode of Pn.14
14
15
read-write
I
Pn.14 is Input pin
0
O
Pn.14 is Output pin
1
MODE15
Mode of Pn.15
15
16
read-write
I
Pn.15 is Input pin
0
O
Pn.15 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF10
Pn.10 raw interrupt flag
10
11
read-only
0
No interrupt on Pn.10
0
1
Interrupt requirements met on Pn.10
1
IF11
Pn.11 raw interrupt flag
11
12
read-only
0
No interrupt on Pn.11
0
1
Interrupt requirements met on Pn.11
1
IF12
Pn.12 raw interrupt flag
12
13
read-only
0
No interrupt on Pn.12
0
1
Interrupt requirements met on Pn.12
1
IF13
Pn.13 raw interrupt flag
13
14
read-only
0
No interrupt on Pn.13
0
1
Interrupt requirements met on Pn.13
1
IF14
Pn.14 raw interrupt flag
14
15
read-only
0
No interrupt on Pn.14
0
1
Interrupt requirements met on Pn.14
1
IF15
Pn.15 raw interrupt flag
15
16
read-only
0
No interrupt on Pn.15
0
1
Interrupt requirements met on Pn.15
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_GPIO3
General Purpose I/O
GPIO
0x0
0x0
0x2000
registers
n
P3
GPIO3
28
BCLR
Offset:0x28 GPIO Port n Bits Clear Operation Register
0x28
32
write-only
n
0x0
0x0
BCLR0
Clear Pn.0
0
1
write-only
No effect
No effect
0
Clear
Clear Pn.0
1
BCLR1
Clear Pn.1
1
2
write-only
No effect
No effect
0
Clear
Clear Pn.1
1
BCLR10
Clear Pn.10
10
11
write-only
No effect
No effect
0
Clear
Clear Pn.10
1
BCLR11
Clear Pn.11
11
12
write-only
No effect
No effect
0
Clear
Clear Pn.11
1
BCLR12
Clear Pn.12
12
13
write-only
No effect
No effect
0
Clear
Clear Pn.12
1
BCLR13
Clear Pn.13
13
14
write-only
No effect
No effect
0
Clear
Clear Pn.13
1
BCLR14
Clear Pn.14
14
15
write-only
No effect
No effect
0
Clear
Clear Pn.14
1
BCLR15
Clear Pn.15
15
16
write-only
No effect
No effect
0
Clear
Clear Pn.15
1
BCLR16
Clear Pn.16
16
17
write-only
No effect
No effect
0
Clear
Clear Pn.16
1
BCLR17
Clear Pn.17
17
18
write-only
No effect
No effect
0
Clear
Clear Pn.17
1
BCLR18
Clear Pn.18
18
19
write-only
No effect
No effect
0
Clear
Clear Pn.18
1
BCLR19
Clear Pn.19
19
20
write-only
No effect
No effect
0
Clear
Clear Pn.19
1
BCLR2
Clear Pn.2
2
3
write-only
No effect
No effect
0
Clear
Clear Pn.2
1
BCLR3
Clear Pn.3
3
4
write-only
No effect
No effect
0
Clear
Clear Pn.3
1
BCLR4
Clear Pn.4
4
5
write-only
No effect
No effect
0
Clear
Clear Pn.4
1
BCLR5
Clear Pn.5
5
6
write-only
No effect
No effect
0
Clear
Clear Pn.5
1
BCLR6
Clear Pn.6
6
7
write-only
No effect
No effect
0
Clear
Clear Pn.6
1
BCLR7
Clear Pn.7
7
8
write-only
No effect
No effect
0
Clear
Clear Pn.7
1
BCLR8
Clear Pn.8
8
9
write-only
No effect
No effect
0
Clear
Clear Pn.8
1
BCLR9
Clear Pn.9
9
10
write-only
No effect
No effect
0
Clear
Clear Pn.9
1
BSET
Offset:0x24 GPIO Port n Bits Set Operation Register
0x24
32
write-only
n
0x0
0x0
BSET0
Set Pn.0
0
1
write-only
No effect
No effect
0
Set
Set Pn.0 to 1
1
BSET1
Set Pn.1
1
2
write-only
No effect
No effect
0
Set
Set Pn.1 to 1
1
BSET10
Set Pn.10
10
11
write-only
No effect
No effect
0
Set
Set Pn.10 to 1
1
BSET11
Set Pn.11
11
12
write-only
No effect
No effect
0
Set
Set Pn.11 to 1
1
BSET12
Set Pn.12
12
13
write-only
No effect
No effect
0
Set
Set Pn.12 to 1
1
BSET13
Set Pn.13
13
14
write-only
No effect
No effect
0
Set
Set Pn.13 to 1
1
BSET14
Set Pn.14
14
15
write-only
No effect
No effect
0
Set
Set Pn.14 to 1
1
BSET15
Set Pn.15
15
16
write-only
No effect
No effect
0
Set
Set Pn.15 to 1
1
BSET16
Set Pn.16
16
17
write-only
No effect
No effect
0
Set
Set Pn.16 to 1
1
BSET17
Set Pn.17
17
18
write-only
No effect
No effect
0
Set
Set Pn.17 to 1
1
BSET18
Set Pn.18
18
19
write-only
No effect
No effect
0
Set
Set Pn.18 to 1
1
BSET19
Set Pn.19
19
20
write-only
No effect
No effect
0
Set
Set Pn.19 to 1
1
BSET2
Set Pn.2
2
3
write-only
No effect
No effect
0
Set
Set Pn.2 to 1
1
BSET3
Set Pn.3
3
4
write-only
No effect
No effect
0
Set
Set Pn.3 to 1
1
BSET4
Set Pn.4
4
5
write-only
No effect
No effect
0
Set
Set Pn.4 to 1
1
BSET5
Set Pn.5
5
6
write-only
No effect
No effect
0
Set
Set Pn.5 to 1
1
BSET6
Set Pn.6
6
7
write-only
No effect
No effect
0
Set
Set Pn.6 to 1
1
BSET7
Set Pn.7
7
8
write-only
No effect
No effect
0
Set
Set Pn.7 to 1
1
BSET8
Set Pn.8
8
9
write-only
No effect
No effect
0
Set
Set Pn.8 to 1
1
BSET9
Set Pn.9
9
10
write-only
No effect
No effect
0
Set
Set Pn.9 to 1
1
CFG
Offset:0x08 GPIO Port n Configuration Register
0x8
32
read-write
n
0x0
0x0
CFG0
Configuration of Pn.0
0
2
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Configuration of Pn.1
2
4
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG10
Configuration of Pn.10
20
22
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG11
Configuration of Pn.11
22
24
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG12
Configuration of Pn.12
24
26
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG13
Configuration of Pn.13
26
28
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG14
Configuration of Pn.14
28
30
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG15
Configuration of Pn.15
30
32
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG2
Configuration of Pn.2
4
6
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG3
Configuration of Pn.3
6
8
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG4
Configuration of Pn.4
8
10
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG5
Configuration of Pn.5
10
12
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG6
Configuration of Pn.6
12
14
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG7
Configuration of Pn.7
14
16
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG8
Configuration of Pn.8
16
18
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG9
Configuration of Pn.9
18
20
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG1
Offset:0x30 GPIO Port n Configuration Register 1
0x30
32
read-write
n
0x0
0x0
CFG16
Configuration of Pn.16
0
2
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG17
Configuration of Pn.17
2
4
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG18
Configuration of Pn.18
4
6
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
CFG19
Configuration of Pn.19
6
8
read-write
00b
Enable pull-up resistor
0
10b
Inactive (schmitt trigger enabled)
2
11b
Inactive (schmitt trigger disabled)
3
DATA
Offset:0x00 GPIO Port n Data Register
0x0
32
read-write
n
0x0
0x0
DATA0
Data of Pn.0
0
1
read-write
0
Pn.0 is 0
0
1
Pn.0 is 1
1
DATA1
Data of Pn.1
1
2
read-write
0
Pn.1 is 0
0
1
Pn.1 is 1
1
DATA10
Data of Pn.10
10
11
read-write
0
Pn.10 is 0
0
1
Pn.10 is 1
1
DATA11
Data of Pn.11
11
12
read-write
0
Pn.11 is 0
0
1
Pn.11 is 1
1
DATA12
Data of Pn.12
12
13
read-write
0
Pn.12 is 0
0
1
Pn.12 is 1
1
DATA13
Data of Pn.13
13
14
read-write
0
Pn.13 is 0
0
1
Pn.13 is 1
1
DATA14
Data of Pn.14
14
15
read-write
0
Pn.14 is 0
0
1
Pn.14 is 1
1
DATA15
Data of Pn.15
15
16
read-write
0
Pn.15 is 0
0
1
Pn.15 is 1
1
DATA16
Data of Pn.16
16
17
read-write
0
Pn.16 is 0
0
1
Pn.16 is 1
1
DATA17
Data of Pn.17
17
18
read-write
0
Pn.17 is 0
0
1
Pn.17 is 1
1
DATA18
Data of Pn.18
18
19
read-write
0
Pn.18 is 0
0
1
Pn.18 is 1
1
DATA19
Data of Pn.19
19
20
read-write
0
Pn.19 is 0
0
1
Pn.19 is 1
1
DATA2
Data of Pn.2
2
3
read-write
0
Pn.2 is 0
0
1
Pn.2 is 1
1
DATA3
Data of Pn.3
3
4
read-write
0
Pn.3 is 0
0
1
Pn.3 is 1
1
DATA4
Data of Pn.4
4
5
read-write
0
Pn.4 is 0
0
1
Pn.4 is 1
1
DATA5
Data of Pn.5
5
6
read-write
0
Pn.5 is 0
0
1
Pn.5 is 1
1
DATA6
Data of Pn.6
6
7
read-write
0
Pn.6 is 0
0
1
Pn.6 is 1
1
DATA7
Data of Pn.7
7
8
read-write
0
Pn.7 is 0
0
1
Pn.7 is 1
1
DATA8
Data of Pn.8
8
9
read-write
0
Pn.8 is 0
0
1
Pn.8 is 1
1
DATA9
Data of Pn.9
9
10
read-write
0
Pn.9 is 0
0
1
Pn.9 is 1
1
IBS
Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register
0x10
32
read-write
n
0x0
0x0
IBS0
Interrupt on Pn.0 is triggered ob both edges
0
1
read-write
IEV
Interrupt on Pn.0 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.0 trigger an interrupt
1
IBS1
Interrupt on Pn.1 is triggered ob both edges
1
2
read-write
IEV
Interrupt on Pn.1 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.1 trigger an interrupt
1
IBS10
Interrupt on Pn.10 is triggered ob both edges
10
11
read-write
IEV
Interrupt on Pn.10 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.10 trigger an interrupt
1
IBS11
Interrupt on Pn.11 is triggered ob both edges
11
12
read-write
IEV
Interrupt on Pn.11 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.11 trigger an interrupt
1
IBS12
Interrupt on Pn.12 is triggered ob both edges
12
13
read-write
IEV
Interrupt on Pn.12 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.12 trigger an interrupt
1
IBS13
Interrupt on Pn.13 is triggered ob both edges
13
14
read-write
IEV
Interrupt on Pn.13 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.13 trigger an interrupt
1
IBS14
Interrupt on Pn.14 is triggered ob both edges
14
15
read-write
IEV
Interrupt on Pn.14 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.14 trigger an interrupt
1
IBS15
Interrupt on Pn.15 is triggered ob both edges
15
16
read-write
IEV
Interrupt on Pn.15 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.15 trigger an interrupt
1
IBS16
Interrupt on Pn.16 is triggered ob both edges
16
17
read-write
IEV
Interrupt on Pn.16 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.16 trigger an interrupt
1
IBS17
Interrupt on Pn.17 is triggered ob both edges
17
18
read-write
IEV
Interrupt on Pn.17 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.17 trigger an interrupt
1
IBS18
Interrupt on Pn.18 is triggered ob both edges
18
19
read-write
IEV
Interrupt on Pn.18 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.18 trigger an interrupt
1
IBS19
Interrupt on Pn.19 is triggered ob both edges
19
20
read-write
IEV
Interrupt on Pn.19 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.19 trigger an interrupt
1
IBS2
Interrupt on Pn.2 is triggered ob both edges
2
3
read-write
IEV
Interrupt on Pn.2 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.2 trigger an interrupt
1
IBS3
Interrupt on Pn.3 is triggered ob both edges
3
4
read-write
IEV
Interrupt on Pn.3 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.3 trigger an interrupt
1
IBS4
Interrupt on Pn.4 is triggered ob both edges
4
5
read-write
IEV
Interrupt on Pn.4 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.4 trigger an interrupt
1
IBS5
Interrupt on Pn.5 is triggered ob both edges
5
6
read-write
IEV
Interrupt on Pn.5 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.5 trigger an interrupt
1
IBS6
Interrupt on Pn.6 is triggered ob both edges
6
7
read-write
IEV
Interrupt on Pn.6 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.6 trigger an interrupt
1
IBS7
Interrupt on Pn.7 is triggered ob both edges
7
8
read-write
IEV
Interrupt on Pn.7 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.7 trigger an interrupt
1
IBS8
Interrupt on Pn.8 is triggered ob both edges
8
9
read-write
IEV
Interrupt on Pn.8 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.8 trigger an interrupt
1
IBS9
Interrupt on Pn.9 is triggered ob both edges
9
10
read-write
IEV
Interrupt on Pn.9 is controlled by GPIOn_IEV register
0
Both edge
Both edges on Pn.9 trigger an interrupt
1
IC
Offset:0x20 GPIO Port n Interrupt Clear Register
0x20
32
write-only
n
0x0
0x0
IC0
Pn.0 interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.0
1
IC1
Pn.1 interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.1
1
IC10
Pn.10 interrupt flag clear
10
11
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.10
1
IC11
Pn.11 interrupt flag clear
11
12
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.11
1
IC12
Pn.12 interrupt flag clear
12
13
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.12
1
IC13
Pn.13 interrupt flag clear
13
14
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.13
1
IC14
Pn.14 interrupt flag clear
14
15
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.14
1
IC15
Pn.15 interrupt flag clear
15
16
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.15
1
IC16
Pn.16 interrupt flag clear
16
17
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.16
1
IC17
Pn.17 interrupt flag clear
17
18
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.17
1
IC18
Pn.18 interrupt flag clear
18
19
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.18
1
IC19
Pn.19 interrupt flag clear
19
20
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.19
1
IC2
Pn.2 interrupt flag clear
2
3
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.2
1
IC3
Pn.3 interrupt flag clear
3
4
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.3
1
IC4
Pn.4 interrupt flag clear
4
5
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.4
1
IC5
Pn.5 interrupt flag clear
5
6
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.5
1
IC6
Pn.6 interrupt flag clear
6
7
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.6
1
IC7
Pn.7 interrupt flag clear
7
8
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.7
1
IC8
Pn.8 interrupt flag clear
8
9
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.8
1
IC9
Pn.9 interrupt flag clear
9
10
write-only
No effect
No effect
0
Clear
Clear interrupt flag on Pn.9
1
IE
Offset:0x18 GPIO Port n Interrupt Enable Register
0x18
32
read-write
n
0x0
0x0
IE0
Interrupt on Pn.0 enable
0
1
read-write
Disable
Disable interrupt on Pn.0
0
Enable
Enable interrupt on Pn.0
1
IE1
Interrupt on Pn.1 enable
1
2
read-write
Disable
Disable interrupt on Pn.1
0
Enable
Enable interrupt on Pn.1
1
IE10
Interrupt on Pn.10 enable
10
11
read-write
Disable
Disable interrupt on Pn.10
0
Enable
Enable interrupt on Pn.10
1
IE11
Interrupt on Pn.11 enable
11
12
read-write
Disable
Disable interrupt on Pn.11
0
Enable
Enable interrupt on Pn.11
1
IE12
Interrupt on Pn.11 enable
12
13
read-write
Disable
Disable interrupt on Pn.12
0
Enable
Enable interrupt on Pn.12
1
IE13
Interrupt on Pn.13 enable
13
14
read-write
Disable
Disable interrupt on Pn.13
0
Enable
Enable interrupt on Pn.13
1
IE14
Interrupt on Pn.14 enable
14
15
read-write
Disable
Disable interrupt on Pn.14
0
Enable
Enable interrupt on Pn.14
1
IE15
Interrupt on Pn.15 enable
15
16
read-write
Disable
Disable interrupt on Pn.15
0
Enable
Enable interrupt on Pn.15
1
IE16
Interrupt on Pn.16 enable
16
17
read-write
Disable
Disable interrupt on Pn.16
0
Enable
Enable interrupt on Pn.16
1
IE17
Interrupt on Pn.17 enable
17
18
read-write
Disable
Disable interrupt on Pn.17
0
Enable
Enable interrupt on Pn.17
1
IE18
Interrupt on Pn.18 enable
18
19
read-write
Disable
Disable interrupt on Pn.18
0
Enable
Enable interrupt on Pn.18
1
IE19
Interrupt on Pn.19 enable
19
20
read-write
Disable
Disable interrupt on Pn.19
0
Enable
Enable interrupt on Pn.19
1
IE2
Interrupt on Pn.2 enable
2
3
read-write
Disable
Disable interrupt on Pn.2
0
Enable
Enable interrupt on Pn.2
1
IE3
Interrupt on Pn.3 enable
3
4
read-write
Disable
Disable interrupt on Pn.3
0
Enable
Enable interrupt on Pn.3
1
IE4
Interrupt on Pn.4 enable
4
5
read-write
Disable
Disable interrupt on Pn.4
0
Enable
Enable interrupt on Pn.4
1
IE5
Interrupt on Pn.5 enable
5
6
read-write
Disable
Disable interrupt on Pn.5
0
Enable
Enable interrupt on Pn.5
1
IE6
Interrupt on Pn.6 enable
6
7
read-write
Disable
Disable interrupt on Pn.6
0
Enable
Enable interrupt on Pn.6
1
IE7
Interrupt on Pn.7 enable
7
8
read-write
Disable
Disable interrupt on Pn.7
0
Enable
Enable interrupt on Pn.7
1
IE8
Interrupt on Pn.8 enable
8
9
read-write
Disable
Disable interrupt on Pn.8
0
Enable
Enable interrupt on Pn.8
1
IE9
Interrupt on Pn.9 enable
9
10
read-write
Disable
Disable interrupt on Pn.9
0
Enable
Enable interrupt on Pn.9
1
IEV
Offset:0x14 GPIO Port n Interrupt Event Register
0x14
32
read-write
n
0x0
0x0
IEV0
Interrupt trigged evnet on Pn.0
0
1
read-write
0
Rising edge or High level on Pn.0 triggers an interrupt
0
1
Falling edge or Low level on Pn.0 triggers an interrupt
1
IEV1
Interrupt trigged evnet on Pn.1
1
2
read-write
0
Rising edge or High level on Pn.1 triggers an interrupt
0
1
Falling edge or Low level on Pn.1 triggers an interrupt
1
IEV10
Interrupt trigged evnet on Pn.10
10
11
read-write
0
Rising edge or High level on Pn.10 triggers an interrupt
0
1
Falling edge or Low level on Pn.10 triggers an interrupt
1
IEV11
Interrupt trigged evnet on Pn.11
11
12
read-write
0
Rising edge or High level on Pn.11 triggers an interrupt
0
1
Falling edge or Low level on Pn.11 triggers an interrupt
1
IEV12
Interrupt trigged evnet on Pn.12
12
13
read-write
0
Rising edge or High level on Pn.12 triggers an interrupt
0
1
Falling edge or Low level on Pn.12 triggers an interrupt
1
IEV13
Interrupt trigged evnet on Pn.13
13
14
read-write
0
Rising edge or High level on Pn.13 triggers an interrupt
0
1
Falling edge or Low level on Pn.13 triggers an interrupt
1
IEV14
Interrupt trigged evnet on Pn.14
14
15
read-write
0
Rising edge or High level on Pn.14 triggers an interrupt
0
1
Falling edge or Low level on Pn.14 triggers an interrupt
1
IEV15
Interrupt trigged evnet on Pn.15
15
16
read-write
0
Rising edge or High level on Pn.15 triggers an interrupt
0
1
Falling edge or Low level on Pn.15 triggers an interrupt
1
IEV16
Interrupt trigged evnet on Pn.16
16
17
read-write
0
Rising edge or High level on Pn.16 triggers an interrupt
0
1
Falling edge or Low level on Pn.16 triggers an interrupt
1
IEV17
Interrupt trigged evnet on Pn.17
17
18
read-write
0
Rising edge or High level on Pn.17 triggers an interrupt
0
1
Falling edge or Low level on Pn.17 triggers an interrupt
1
IEV18
Interrupt trigged evnet on Pn.18
18
19
read-write
0
Rising edge or High level on Pn.18 triggers an interrupt
0
1
Falling edge or Low level on Pn.18 triggers an interrupt
1
IEV19
Interrupt trigged evnet on Pn.19
19
20
read-write
0
Rising edge or High level on Pn.19 triggers an interrupt
0
1
Falling edge or Low level on Pn.19 triggers an interrupt
1
IEV2
Interrupt trigged evnet on Pn.2
2
3
read-write
0
Rising edge or High level on Pn.2 triggers an interrupt
0
1
Falling edge or Low level on Pn.2 triggers an interrupt
1
IEV3
Interrupt trigged evnet on Pn.3
3
4
read-write
0
Rising edge or High level on Pn.3 triggers an interrupt
0
1
Falling edge or Low level on Pn.3 triggers an interrupt
1
IEV4
Interrupt trigged evnet on Pn.4
4
5
read-write
0
Rising edge or High level on Pn.4 triggers an interrupt
0
1
Falling edge or Low level on Pn.4 triggers an interrupt
1
IEV5
Interrupt trigged evnet on Pn.5
5
6
read-write
0
Rising edge or High level on Pn.5 triggers an interrupt
0
1
Falling edge or Low level on Pn.5 triggers an interrupt
1
IEV6
Interrupt trigged evnet on Pn.6
6
7
read-write
0
Rising edge or High level on Pn.6 triggers an interrupt
0
1
Falling edge or Low level on Pn.6 triggers an interrupt
1
IEV7
Interrupt trigged evnet on Pn.7
7
8
read-write
0
Rising edge or High level on Pn.7 triggers an interrupt
0
1
Falling edge or Low level on Pn.7 triggers an interrupt
1
IEV8
Interrupt trigged evnet on Pn.8
8
9
read-write
0
Rising edge or High level on Pn.8 triggers an interrupt
0
1
Falling edge or Low level on Pn.8 triggers an interrupt
1
IEV9
Interrupt trigged evnet on Pn.9
9
10
read-write
0
Rising edge or High level on Pn.9 triggers an interrupt
0
1
Falling edge or Low level on Pn.9 triggers an interrupt
1
IS
Offset:0x0C GPIO Port n Interrupt Sense Register
0xC
32
read-write
n
0x0
0x0
IS0
Interrupt on Pn.0 is event or edge sensitive
0
1
read-write
Edge
Interrupt on Pn.0 is edge sensitive
0
Event
Interrupt on Pn.0 is event sensitive
1
IS1
Interrupt on Pn.1 is event or edge sensitive
1
2
read-write
Edge
Interrupt on Pn.1 is edge sensitive
0
Event
Interrupt on Pn.1 is event sensitive
1
IS10
Interrupt on Pn.10 is event or edge sensitive
10
11
read-write
Edge
Interrupt on Pn.10 is edge sensitive
0
Event
Interrupt on Pn.10 is event sensitive
1
IS11
Interrupt on Pn.11 is event or edge sensitive
11
12
read-write
Edge
Interrupt on Pn.11 is edge sensitive
0
Event
Interrupt on Pn.11 is event sensitive
1
IS12
Interrupt on Pn.12 is event or edge sensitive
12
13
read-write
Edge
Interrupt on Pn.12 is edge sensitive
0
Event
Interrupt on Pn.12 is event sensitive
1
IS13
Interrupt on Pn.13 is event or edge sensitive
13
14
read-write
Edge
Interrupt on Pn.13 is edge sensitive
0
Event
Interrupt on Pn.13 is event sensitive
1
IS14
Interrupt on Pn.14 is event or edge sensitive
14
15
read-write
Edge
Interrupt on Pn.14 is edge sensitive
0
Event
Interrupt on Pn.14 is event sensitive
1
IS15
Interrupt on Pn.15 is event or edge sensitive
15
16
read-write
Edge
Interrupt on Pn.15 is edge sensitive
0
Event
Interrupt on Pn.15 is event sensitive
1
IS16
Interrupt on Pn.16 is event or edge sensitive
16
17
read-write
Edge
Interrupt on Pn.16 is edge sensitive
0
Event
Interrupt on Pn.16 is event sensitive
1
IS17
Interrupt on Pn.17 is event or edge sensitive
17
18
read-write
Edge
Interrupt on Pn.17 is edge sensitive
0
Event
Interrupt on Pn.17 is event sensitive
1
IS18
Interrupt on Pn.18 is event or edge sensitive
18
19
read-write
Edge
Interrupt on Pn.18 is edge sensitive
0
Event
Interrupt on Pn.18 is event sensitive
1
IS19
Interrupt on Pn.19 is event or edge sensitive
19
20
read-write
Edge
Interrupt on Pn.19 is edge sensitive
0
Event
Interrupt on Pn.19 is event sensitive
1
IS2
Interrupt on Pn.2 is event or edge sensitive
2
3
read-write
Edge
Interrupt on Pn.2 is edge sensitive
0
Event
Interrupt on Pn.2 is event sensitive
1
IS3
Interrupt on Pn.3 is event or edge sensitive
3
4
read-write
Edge
Interrupt on Pn.3 is edge sensitive
0
Event
Interrupt on Pn.3 is event sensitive
1
IS4
Interrupt on Pn.4 is event or edge sensitive
4
5
read-write
Edge
Interrupt on Pn.4 is edge sensitive
0
Event
Interrupt on Pn.4 is event sensitive
1
IS5
Interrupt on Pn.5 is event or edge sensitive
5
6
read-write
Edge
Interrupt on Pn.5 is edge sensitive
0
Event
Interrupt on Pn.5 is event sensitive
1
IS6
Interrupt on Pn.6 is event or edge sensitive
6
7
read-write
Edge
Interrupt on Pn.6 is edge sensitive
0
Event
Interrupt on Pn.6 is event sensitive
1
IS7
Interrupt on Pn.7 is event or edge sensitive
7
8
read-write
Edge
Interrupt on Pn.7 is edge sensitive
0
Event
Interrupt on Pn.7 is event sensitive
1
IS8
Interrupt on Pn.8 is event or edge sensitive
8
9
read-write
Edge
Interrupt on Pn.8 is edge sensitive
0
Event
Interrupt on Pn.8 is event sensitive
1
IS9
Interrupt on Pn.9 is event or edge sensitive
9
10
read-write
Edge
Interrupt on Pn.9 is edge sensitive
0
Event
Interrupt on Pn.9 is event sensitive
1
MODE
Offset:0x04 GPIO Port n Mode Register
0x4
32
read-write
n
0x0
0x0
MODE0
Mode of Pn.0
0
1
read-write
I
Pn.0 is Input pin
0
O
Pn.0 is Output pin
1
MODE1
Mode of Pn.1
1
2
read-write
I
Pn.1 is Input pin
0
O
Pn.1 is Output pin
1
MODE10
Mode of Pn.10
10
11
read-write
I
Pn.10 is Input pin
0
O
Pn.10 is Output pin
1
MODE11
Mode of Pn.11
11
12
read-write
I
Pn.11 is Input pin
0
O
Pn.11 is Output pin
1
MODE12
Mode of Pn.12
12
13
read-write
I
Pn.12 is Input pin
0
O
Pn.12 is Output pin
1
MODE13
Mode of Pn.13
13
14
read-write
I
Pn.13 is Input pin
0
O
Pn.13 is Output pin
1
MODE14
Mode of Pn.14
14
15
read-write
I
Pn.14 is Input pin
0
O
Pn.14 is Output pin
1
MODE15
Mode of Pn.15
15
16
read-write
I
Pn.15 is Input pin
0
O
Pn.15 is Output pin
1
MODE16
Mode of Pn.16
16
17
read-write
I
Pn.16 is Input pin
0
O
Pn.16 is Output pin
1
MODE17
Mode of Pn.17
17
18
read-write
I
Pn.17 is Input pin
0
O
Pn.17 is Output pin
1
MODE18
Mode of Pn.18
18
19
read-write
I
Pn.18 is Input pin
0
O
Pn.18 is Output pin
1
MODE19
Mode of Pn.19
19
20
read-write
I
Pn.19 is Input pin
0
O
Pn.19 is Output pin
1
MODE2
Mode of Pn.2
2
3
read-write
I
Pn.2 is Input pin
0
O
Pn.2 is Output pin
1
MODE3
Mode of Pn.3
3
4
read-write
I
Pn.3 is Input pin
0
O
Pn.3 is Output pin
1
MODE4
Mode of Pn.4
4
5
read-write
I
Pn.4 is Input pin
0
O
Pn.4 is Output pin
1
MODE5
Mode of Pn.5
5
6
read-write
I
Pn.5 is Input pin
0
O
Pn.5 is Output pin
1
MODE6
Mode of Pn.6
6
7
read-write
I
Pn.6 is Input pin
0
O
Pn.6 is Output pin
1
MODE7
Mode of Pn.7
7
8
read-write
I
Pn.7 is Input pin
0
O
Pn.7 is Output pin
1
MODE8
Mode of Pn.8
8
9
read-write
I
Pn.8 is Input pin
0
O
Pn.8 is Output pin
1
MODE9
Mode of Pn.9
9
10
read-write
I
Pn.9 is Input pin
0
O
Pn.9 is Output pin
1
RIS
Offset:0x1C GPIO Port n Raw Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
IF0
Pn.0 raw interrupt flag
0
1
read-only
0
No interrupt on Pn.0
0
1
Interrupt requirements met on Pn.0
1
IF1
Pn.1 raw interrupt flag
1
2
read-only
0
No interrupt on Pn.1
0
1
Interrupt requirements met on Pn.1
1
IF10
Pn.10 raw interrupt flag
10
11
read-only
0
No interrupt on Pn.10
0
1
Interrupt requirements met on Pn.10
1
IF11
Pn.11 raw interrupt flag
11
12
read-only
0
No interrupt on Pn.11
0
1
Interrupt requirements met on Pn.11
1
IF12
Pn.12 raw interrupt flag
12
13
read-only
0
No interrupt on Pn.12
0
1
Interrupt requirements met on Pn.12
1
IF13
Pn.13 raw interrupt flag
13
14
read-only
0
No interrupt on Pn.13
0
1
Interrupt requirements met on Pn.13
1
IF14
Pn.14 raw interrupt flag
14
15
read-only
0
No interrupt on Pn.14
0
1
Interrupt requirements met on Pn.14
1
IF15
Pn.15 raw interrupt flag
15
16
read-only
0
No interrupt on Pn.15
0
1
Interrupt requirements met on Pn.15
1
IF16
Pn.16 raw interrupt flag
16
17
read-only
0
No interrupt on Pn.16
0
1
Interrupt requirements met on Pn.16
1
IF17
Pn.17 raw interrupt flag
17
18
read-only
0
No interrupt on Pn.17
0
1
Interrupt requirements met on Pn.17
1
IF18
Pn.18 raw interrupt flag
18
19
read-only
0
No interrupt on Pn.18
0
1
Interrupt requirements met on Pn.18
1
IF19
Pn.19 raw interrupt flag
19
20
read-only
0
No interrupt on Pn.19
0
1
Interrupt requirements met on Pn.19
1
IF2
Pn.2 raw interrupt flag
2
3
read-only
0
No interrupt on Pn.2
0
1
Interrupt requirements met on Pn.2
1
IF3
Pn.3 raw interrupt flag
3
4
read-only
0
No interrupt on Pn.3
0
1
Interrupt requirements met on Pn.3
1
IF4
Pn.4 raw interrupt flag
4
5
read-only
0
No interrupt on Pn.4
0
1
Interrupt requirements met on Pn.4
1
IF5
Pn.5 raw interrupt flag
5
6
read-only
0
No interrupt on Pn.5
0
1
Interrupt requirements met on Pn.5
1
IF6
Pn.6 raw interrupt flag
6
7
read-only
0
No interrupt on Pn.6
0
1
Interrupt requirements met on Pn.6
1
IF7
Pn.7 raw interrupt flag
7
8
read-only
0
No interrupt on Pn.7
0
1
Interrupt requirements met on Pn.7
1
IF8
Pn.8 raw interrupt flag
8
9
read-only
0
No interrupt on Pn.8
0
1
Interrupt requirements met on Pn.8
1
IF9
Pn.9 raw interrupt flag
9
10
read-only
0
No interrupt on Pn.9
0
1
Interrupt requirements met on Pn.9
1
SN_I2C0
I2C0
I2C
0x0
0x0
0x2000
registers
n
I2C0
I2C0
10
CTRL
Offset:0x00 I2Cn Control Register
0x0
32
read-write
n
0x0
0x0
ACK
ACK assert flag
2
3
read-write
No
Master: No action/Slave: Assert NACK after receiving
0
Assert
Assert ACK during the acknowledge clock pulse on SCLn
1
I2CEN
I2Cn interface enable
8
9
read-write
Disable
Disable I2C
0
Enable
Enable I2C
1
I2CMODE
I2C mode
7
8
read-write
Standard/Fast mode
Standard/Fast mode
0
NACK
NACK assert flag
1
2
read-write
No action
No action
0
Assert
Assert NACK during the acknowledge clock pulse on SCLn
1
STA
START assert flag
5
6
read-write
No action
No START condition or Repeated START condition will be generated
0
Assert
Enter master mode and transmit a START or Repeated START condition
1
STO
STOP assert flag
4
5
read-write
Idle
STOP condition idle
0
Assert
Transmit a STOP condition in master mode, or recover from an error condition in slave mode
1
RXDATA
Offset:0x0C I2Cn RX Data Register
0xC
32
read-only
n
0x0
0x0
Data
RX Data received when RX_DN=1
0
8
read-only
SCLHT
Offset:0x20 I2Cn SCL High Time Register
0x20
32
read-write
n
0x0
0x0
SCLH
SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle
0
8
read-write
SCLLT
Offset:0x24 I2Cn SCL Low Time Register
0x24
32
read-write
n
0x0
0x0
SCLL
SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle
0
8
read-write
SLVADDR0
Offset:0x10 I2Cn Slave Address 0 Register
0x10
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 0
0
10
read-write
ADD_MODE
Slave address mode
31
32
read-write
0
7-bit slave address mode
0
1
10-bit slave address mode
1
GCEN
General call address enable
30
31
read-write
Disable
Disable general call address
0
Enable
Enable general call address (0x0)
1
SLVADDR1
Offset:0x14 I2Cn Slave Address 1 Register
0x14
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 1
0
10
read-write
SLVADDR2
Offset:0x18 I2Cn Slave Address 2 Register
0x18
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 2
0
10
read-write
SLVADDR3
Offset:0x1C I2Cn Slave Address 3 Register
0x1C
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 3
0
10
read-write
STAT
Offset:0x04 I2Cn Status Register
0x4
32
read-write
n
0x0
0x0
ACK_STAT
ACK done status
1
2
read-only
No
No ACK received
0
Done
Receive an ACK
1
I2CIF
I2C interrupt flag
15
16
read-write
0
I2C status doesn't change
0
1
I2C status changes
1
LOST_ARB
Lost arbitration status
8
9
read-only
0
Not lost arbitration
0
1
Lost arbitration
1
MST
I2C master/slave status
5
6
read-only
Slave
Act as Slave
0
Master
Act as Master
1
NACK_STAT
NACK done status
2
3
read-only
No
No NACK received
0
Done
Receive a NACK
1
RX_DN
RX done status
0
1
read-only
Not done
No RX with ACK/NACK transfer
0
Done
8-bit RX with ACK/NACK transfer
1
SLV_RX_HIT
Slave RX address hit flag
6
7
read-only
0
No matched slave address
0
1
Slave address hit, and is called for RX
1
SLV_TX_HIT
Slave TX address hit flag
7
8
read-only
0
No matched slave address
0
1
Slave address hit, and is called for TX
1
START_DN
START done status
4
5
read-only
No
No START condition
0
Assert
Transmit or receive a START condition
1
STOP_DN
STOP done status
3
4
read-only
No
No STOP condition
0
Done
Transmit or receive a STOP condition
1
TIMEOUT
Time-out status
9
10
read-only
0
No timeout
0
1
Timeout
1
TOCTRL
Offset:0x2C I2Cn Timeout Control Register
0x2C
32
read-write
n
0x0
0x0
TO
Timeout period time = TO*32*I2Cn_PCLK cycle
0
16
read-write
TXDATA
Offset:0x08 I2Cn TX Data Register
0x8
32
read-write
n
0x0
0x0
Data
TX Data
0
8
read-write
SN_I2C1
I2C0
I2C
0x0
0x0
0x2000
registers
n
I2C1
I2C1
11
CTRL
Offset:0x00 I2Cn Control Register
0x0
32
read-write
n
0x0
0x0
ACK
ACK assert flag
2
3
read-write
No
Master: No action/Slave: Assert NACK after receiving
0
Assert
Assert ACK during the acknowledge clock pulse on SCLn
1
I2CEN
I2Cn interface enable
8
9
read-write
Disable
Disable I2C
0
Enable
Enable I2C
1
I2CMODE
I2C mode
7
8
read-write
Standard/Fast mode
Standard/Fast mode
0
NACK
NACK assert flag
1
2
read-write
No action
No action
0
Assert
Assert NACK during the acknowledge clock pulse on SCLn
1
STA
START assert flag
5
6
read-write
No action
No START condition or Repeated START condition will be generated
0
Assert
Enter master mode and transmit a START or Repeated START condition
1
STO
STOP assert flag
4
5
read-write
Idle
STOP condition idle
0
Assert
Transmit a STOP condition in master mode, or recover from an error condition in slave mode
1
RXDATA
Offset:0x0C I2Cn RX Data Register
0xC
32
read-only
n
0x0
0x0
Data
RX Data received when RX_DN=1
0
8
read-only
SCLHT
Offset:0x20 I2Cn SCL High Time Register
0x20
32
read-write
n
0x0
0x0
SCLH
SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle
0
8
read-write
SCLLT
Offset:0x24 I2Cn SCL Low Time Register
0x24
32
read-write
n
0x0
0x0
SCLL
SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle
0
8
read-write
SLVADDR0
Offset:0x10 I2Cn Slave Address 0 Register
0x10
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 0
0
10
read-write
ADD_MODE
Slave address mode
31
32
read-write
0
7-bit slave address mode
0
1
10-bit slave address mode
1
GCEN
General call address enable
30
31
read-write
Disable
Disable general call address
0
Enable
Enable general call address (0x0)
1
SLVADDR1
Offset:0x14 I2Cn Slave Address 1 Register
0x14
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 1
0
10
read-write
SLVADDR2
Offset:0x18 I2Cn Slave Address 2 Register
0x18
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 2
0
10
read-write
SLVADDR3
Offset:0x1C I2Cn Slave Address 3 Register
0x1C
32
read-write
n
0x0
0x0
ADDR
I2Cn slave address 3
0
10
read-write
STAT
Offset:0x04 I2Cn Status Register
0x4
32
read-write
n
0x0
0x0
ACK_STAT
ACK done status
1
2
read-only
No
No ACK received
0
Done
Receive an ACK
1
I2CIF
I2C interrupt flag
15
16
read-write
0
I2C status doesn't change
0
1
I2C status changes
1
LOST_ARB
Lost arbitration status
8
9
read-only
0
Not lost arbitration
0
1
Lost arbitration
1
MST
I2C master/slave status
5
6
read-only
Slave
Act as Slave
0
Master
Act as Master
1
NACK_STAT
NACK done status
2
3
read-only
No
No NACK received
0
Done
Receive a NACK
1
RX_DN
RX done status
0
1
read-only
Not done
No RX with ACK/NACK transfer
0
Done
8-bit RX with ACK/NACK transfer
1
SLV_RX_HIT
Slave RX address hit flag
6
7
read-only
0
No matched slave address
0
1
Slave address hit, and is called for RX
1
SLV_TX_HIT
Slave TX address hit flag
7
8
read-only
0
No matched slave address
0
1
Slave address hit, and is called for TX
1
START_DN
START done status
4
5
read-only
No
No START condition
0
Assert
Transmit or receive a START condition
1
STOP_DN
STOP done status
3
4
read-only
No
No STOP condition
0
Done
Transmit or receive a STOP condition
1
TIMEOUT
Time-out status
9
10
read-only
0
No timeout
0
1
Timeout
1
TOCTRL
Offset:0x2C I2Cn Timeout Control Register
0x2C
32
read-write
n
0x0
0x0
TO
Timeout period time = TO*32*I2Cn_PCLK cycle
0
16
read-write
TXDATA
Offset:0x08 I2Cn TX Data Register
0x8
32
read-write
n
0x0
0x0
Data
TX Data
0
8
read-write
SN_I2S0
I2S
I2S
0x0
0x0
0x2000
registers
n
I2S0
I2S0
3
CLK
Offset:0x04 I2Sn Clock Register
0x4
32
read-write
n
0x0
0x0
BCLKDIV
BCLK divider
8
16
read-write
CLKSEL
I2S clock source
16
17
read-write
HCLK
HCLK is I2S clock source
0
EHS XTAL
EHS Xtal is I2S clock source
1
MCLKDIV
MCLK divider
0
3
read-write
0
MCLK=MCLK source
0
1
MCLK=MCLK source/2
1
2
MCLK=MCLK source/4
2
3
MCLK=MCLK source/6
3
4
MCLK=MCLK source/8
4
5
MCLK=MCLK source/10
5
6
MCLK=MCLK source/12
6
7
MCLK=MCLK source/14
7
MCLKOEN
MLCK output enable
3
4
read-write
Disable
Disable MCLK output
0
Enable
Enable MCLK output
1
MCLKSEL
MLCK source selection
4
5
read-write
I2S_PCLK
MCLK source of master is from I2S_PCLK
0
GPIO
MCLK source of master is from GPIO
1
CTRL
Offset:0x00 I2Sn Control Register
0x0
32
read-write
n
0x0
0x0
CHLENGTH
Bit number of single channel
20
25
read-write
10
11 bits
10
11
12 bits
11
12
13 bits
12
13
14 bits
13
14
15 bits
14
15
16 bits
15
16
17 bits
16
17
18 bits
17
18
19 bits
18
19
20 bits
19
20
21 bits
20
21
22 bits
21
22
23 bits
22
23
24 bits
23
24
25 bits
24
25
26 bits
25
26
27 bits
26
27
28 bits
27
28
29 bits
28
29
30 bits
29
30
31 bits
30
31
32 bits (Max)
31
7
8 bits
7
8
9 bits
8
9
10 bits
9
CLRRXFIFO
Clear I2S RX FIFO
9
10
write-only
0
No effect
0
1
Reset RX FIFO
1
CLRTXFIFO
Clear I2S TX FIFO
8
9
write-only
0
No effect
0
1
Reset TX FIFO
1
DL
Data length
10
12
read-write
8
Data length=8 bits
0
16
Data length=16 bits
1
24
Data length=24 bits
2
32
Data length=32 bits
3
FORMAT
I2S operation format
4
6
read-write
0
Standard I2S format
0
01
Left-justified format
1
10
Right(MSB)-justified format
2
I2SEN
I2S enable
31
32
read-write
Disable
Disable I2S
0
Enable
Enable I2S
1
MONO
Mono/stereo selection
2
3
read-write
Stereo
Stereo mode
0
Mono
Mono mode
1
MS
Master/Slave selection bit
3
4
read-write
Master
Act as Master using internally generated BCLK and WS signals.
0
Slave
Act as Slave using externally BCLK and WS signals.
1
MUTE
Mute enable
1
2
read-write
Disable
Disable mute
0
Enable
Enable mute (I2SSDA output is 0)
1
RXEN
Receiver enable bit
7
8
read-write
Disable
Disable RX
0
Enable
Enable RX
1
RXFIFOTH
RX FIFO threshold level
16
19
read-write
0
RX FIFO threshold level=0
0
1
RX FIFO threshold level=1
1
2
RX FIFO threshold level=2
2
3
RX FIFO threshold level=3
3
4
RX FIFO threshold level=4
4
5
RX FIFO threshold level=5
5
6
RX FIFO threshold level=6
6
7
RX FIFO threshold level=7
7
START
Start Transmit/Receive
0
1
read-write
Stop
Stop transmit/receive
0
Start
Start transmit/receive
1
TXEN
Transmit enable bit
6
7
read-write
Disable
Disable TX
0
Enable
Enable TX
1
TXFIFOTH
TX FIFO threshold level
12
15
read-write
0
TX FIFO threshold level=0
0
1
TX FIFO threshold level=1
1
2
TX FIFO threshold level=2
2
3
TX FIFO threshold level=3
3
4
TX FIFO threshold level=4
4
5
TX FIFO threshold level=5
5
6
TX FIFO threshold level=6
6
7
TX FIFO threshold level=7
7
IC
Offset:0x14 I2Sn Interrupt Clear Register
0x14
32
write-only
n
0x0
0x0
RXFIFOTHIC
RX FIFO threshold interrupt clear
7
8
write-only
No effect
No effect
0
Clear
Clear RXFIFOTHIF bit
1
RXFIFOUDIC
RX FIFO underflow interrupt clear
5
6
write-only
No effect
No effect
0
Clear
Clear RXFIFOUDIF bit
1
TXFIFOOVIC
TX FIFO overflow interrupt clear
4
5
write-only
No effect
No effect
0
Clear
Clear TXFIFOOVIF bit
1
TXFIFOTHIC
TX FIFO threshold interrupt clear
6
7
write-only
No effect
No effect
0
Clear
Clear TXFIFOTHIF bit
1
IE
Offset:0x0C I2Sn Interrupt Enable Register
0xC
32
read-write
n
0x0
0x0
RXFIFOTHIEN
RX FIFO threshold interrupt enable
7
8
read-write
Disable
Disable RX FIFO threshold interrupt
0
Enable
Enable RX FIFO threshold interrupt
1
RXFIFOUDFIEN
RX FIFO underflow interrupt enable
5
6
read-write
Disable
Disable RX FIFO underflow interrupt
0
Enable
Enable RX FIFO underflow interrupt
1
TXFIFOOVFIEN
TX FIFO overflow interrupt enable
4
5
read-write
Disable
Disable TX FIFO overflow interrupt
0
Enable
Enable TX FIFO overflow interrupt
1
TXFIFOTHIEN
TX FIFO threshold interrupt enable
6
7
read-write
Disable
Disable TX FIFO threshold interrupt
0
Enable
Enable TX FIFO threshold interrupt
1
RIS
Offset:0x10 I2Sn Raw Interrupt Status Register
0x10
32
read-only
n
0x0
0x0
RXFIFOTHIF
RX FIFO threshold interrupt flag
7
8
read-only
0
No RX FIFO threshold interrupt
0
1
RX FIFO threshold triggered
1
RXFIFOUDIF
RX FIFO underflow interrupt flag
5
6
read-only
0
No RX FIFO underflow
0
1
RX FIFO underflow
1
TXFIFOOVIF
TX FIFO overflow interrupt flag
4
5
read-only
0
No TX FIFO overflow
0
1
TX FIFO overflow
1
TXFIFOTHIF
TX FIFO threshold interrupt flag
6
7
read-only
0
No TX FIFO threshold interrupt
0
1
TX FIFO threshold triggered
1
RXFIFO
Offset:0x18 I2Sn RX FIFO Register
0x18
32
read-only
n
0x0
0x0
STATUS
Offset:0x08 I2Sn Status Register
0x8
32
read-only
n
0x0
0x0
I2SINT
I2S interrupt flag
0
1
read-only
No
No I2S interrupt
0
Occurs
I2S interrupt occurs
1
RIGHTCH
Current channel status
1
2
read-only
Left
Current channel is left channel
0
Right
Current channel is right channel
1
RXFIFOEMPTY
RX FIFO empty flag
11
12
read-only
0
RX FIFO is not empty
0
1
RX FIFO is empty
1
RXFIFOFULL
RX FIFO full flag
9
10
read-only
0
RX FIFO is not full
0
1
RX FIFO is full
1
RXFIFOLV
RX FIFO used level
17
21
read-only
0
0/8 RX FIFO is used (Empty)
0
1
1/8 RX FIFO is used
1
2
2/8 RX FIFO is used
2
3
3/8 RX FIFO is used
3
4
4/8 RX FIFO is used
4
5
5/8 RX FIFO is used
5
6
6/8 RX FIFO is used
6
7
7/8 RX FIFO is used
7
8
8/8 RX FIFO is used (Full)
8
RXFIFOTHF
RX FIFO threshold flag
7
8
read-only
0
RXFIFOLV is less equal than RXFIFOTH
0
1
RXFIFOLV is larger than RXFIFOTH
1
TXFIFOEMPTY
TX FIFO empty flag
10
11
read-only
0
TX FIFO is not empty
0
1
TX FIFO is empty
1
TXFIFOFULL
TX FIFO full flag
8
9
read-only
Not full
TX FIFO is not full
0
Full
TX FIFO is full
1
TXFIFOLV
TX FIFO used level
12
16
read-only
0
0/8 TX FIFO is used (Empty)
0
1
1/8 TX FIFO is used
1
2
2/8 TX FIFO is used
2
3
3/8 TX FIFO is used
3
4
4/8 TX FIFO is used
4
5
5/8 TX FIFO is used
5
6
6/8 TX FIFO is used
6
7
7/8 TX FIFO is used
7
8
8/8 TX FIFO is used (Full)
8
TXFIFOTHF
TX FIFO threshold flag
6
7
read-only
0
TXFIFOLV is larger equal than TXFIFOTH
0
1
TXFIFOLV is less than TXFIFOTH
1
TXFIFO
Offset:0x1C I2Sn TX FIFO Register
0x1C
32
write-only
n
0x0
0x0
SN_I2S1
I2S
I2S
0x0
0x0
0x2000
registers
n
I2S1
I2S1
4
CLK
Offset:0x04 I2Sn Clock Register
0x4
32
read-write
n
0x0
0x0
BCLKDIV
BCLK divider
8
16
read-write
CLKSEL
I2S clock source
16
17
read-write
HCLK
HCLK is I2S clock source
0
EHS XTAL
EHS Xtal is I2S clock source
1
MCLKDIV
MCLK divider
0
3
read-write
0
MCLK=MCLK source
0
1
MCLK=MCLK source/2
1
2
MCLK=MCLK source/4
2
3
MCLK=MCLK source/6
3
4
MCLK=MCLK source/8
4
5
MCLK=MCLK source/10
5
6
MCLK=MCLK source/12
6
7
MCLK=MCLK source/14
7
MCLKOEN
MLCK output enable
3
4
read-write
Disable
Disable MCLK output
0
Enable
Enable MCLK output
1
MCLKSEL
MLCK source selection
4
5
read-write
I2S_PCLK
MCLK source of master is from I2S_PCLK
0
GPIO
MCLK source of master is from GPIO
1
CTRL
Offset:0x00 I2Sn Control Register
0x0
32
read-write
n
0x0
0x0
CHLENGTH
Bit number of single channel
20
25
read-write
10
11 bits
10
11
12 bits
11
12
13 bits
12
13
14 bits
13
14
15 bits
14
15
16 bits
15
16
17 bits
16
17
18 bits
17
18
19 bits
18
19
20 bits
19
20
21 bits
20
21
22 bits
21
22
23 bits
22
23
24 bits
23
24
25 bits
24
25
26 bits
25
26
27 bits
26
27
28 bits
27
28
29 bits
28
29
30 bits
29
30
31 bits
30
31
32 bits (Max)
31
7
8 bits
7
8
9 bits
8
9
10 bits
9
CLRRXFIFO
Clear I2S RX FIFO
9
10
write-only
0
No effect
0
1
Reset RX FIFO
1
CLRTXFIFO
Clear I2S TX FIFO
8
9
write-only
0
No effect
0
1
Reset TX FIFO
1
DL
Data length
10
12
read-write
8
Data length=8 bits
0
16
Data length=16 bits
1
24
Data length=24 bits
2
32
Data length=32 bits
3
FORMAT
I2S operation format
4
6
read-write
0
Standard I2S format
0
01
Left-justified format
1
10
Right(MSB)-justified format
2
I2SEN
I2S enable
31
32
read-write
Disable
Disable I2S
0
Enable
Enable I2S
1
MONO
Mono/stereo selection
2
3
read-write
Stereo
Stereo mode
0
Mono
Mono mode
1
MS
Master/Slave selection bit
3
4
read-write
Master
Act as Master using internally generated BCLK and WS signals.
0
Slave
Act as Slave using externally BCLK and WS signals.
1
MUTE
Mute enable
1
2
read-write
Disable
Disable mute
0
Enable
Enable mute (I2SSDA output is 0)
1
RXEN
Receiver enable bit
7
8
read-write
Disable
Disable RX
0
Enable
Enable RX
1
RXFIFOTH
RX FIFO threshold level
16
19
read-write
0
RX FIFO threshold level=0
0
1
RX FIFO threshold level=1
1
2
RX FIFO threshold level=2
2
3
RX FIFO threshold level=3
3
4
RX FIFO threshold level=4
4
5
RX FIFO threshold level=5
5
6
RX FIFO threshold level=6
6
7
RX FIFO threshold level=7
7
START
Start Transmit/Receive
0
1
read-write
Stop
Stop transmit/receive
0
Start
Start transmit/receive
1
TXEN
Transmit enable bit
6
7
read-write
Disable
Disable TX
0
Enable
Enable TX
1
TXFIFOTH
TX FIFO threshold level
12
15
read-write
0
TX FIFO threshold level=0
0
1
TX FIFO threshold level=1
1
2
TX FIFO threshold level=2
2
3
TX FIFO threshold level=3
3
4
TX FIFO threshold level=4
4
5
TX FIFO threshold level=5
5
6
TX FIFO threshold level=6
6
7
TX FIFO threshold level=7
7
IC
Offset:0x14 I2Sn Interrupt Clear Register
0x14
32
write-only
n
0x0
0x0
RXFIFOTHIC
RX FIFO threshold interrupt clear
7
8
write-only
No effect
No effect
0
Clear
Clear RXFIFOTHIF bit
1
RXFIFOUDIC
RX FIFO underflow interrupt clear
5
6
write-only
No effect
No effect
0
Clear
Clear RXFIFOUDIF bit
1
TXFIFOOVIC
TX FIFO overflow interrupt clear
4
5
write-only
No effect
No effect
0
Clear
Clear TXFIFOOVIF bit
1
TXFIFOTHIC
TX FIFO threshold interrupt clear
6
7
write-only
No effect
No effect
0
Clear
Clear TXFIFOTHIF bit
1
IE
Offset:0x0C I2Sn Interrupt Enable Register
0xC
32
read-write
n
0x0
0x0
RXFIFOTHIEN
RX FIFO threshold interrupt enable
7
8
read-write
Disable
Disable RX FIFO threshold interrupt
0
Enable
Enable RX FIFO threshold interrupt
1
RXFIFOUDFIEN
RX FIFO underflow interrupt enable
5
6
read-write
Disable
Disable RX FIFO underflow interrupt
0
Enable
Enable RX FIFO underflow interrupt
1
TXFIFOOVFIEN
TX FIFO overflow interrupt enable
4
5
read-write
Disable
Disable TX FIFO overflow interrupt
0
Enable
Enable TX FIFO overflow interrupt
1
TXFIFOTHIEN
TX FIFO threshold interrupt enable
6
7
read-write
Disable
Disable TX FIFO threshold interrupt
0
Enable
Enable TX FIFO threshold interrupt
1
RIS
Offset:0x10 I2Sn Raw Interrupt Status Register
0x10
32
read-only
n
0x0
0x0
RXFIFOTHIF
RX FIFO threshold interrupt flag
7
8
read-only
0
No RX FIFO threshold interrupt
0
1
RX FIFO threshold triggered
1
RXFIFOUDIF
RX FIFO underflow interrupt flag
5
6
read-only
0
No RX FIFO underflow
0
1
RX FIFO underflow
1
TXFIFOOVIF
TX FIFO overflow interrupt flag
4
5
read-only
0
No TX FIFO overflow
0
1
TX FIFO overflow
1
TXFIFOTHIF
TX FIFO threshold interrupt flag
6
7
read-only
0
No TX FIFO threshold interrupt
0
1
TX FIFO threshold triggered
1
RXFIFO
Offset:0x18 I2Sn RX FIFO Register
0x18
32
read-only
n
0x0
0x0
STATUS
Offset:0x08 I2Sn Status Register
0x8
32
read-only
n
0x0
0x0
I2SINT
I2S interrupt flag
0
1
read-only
No
No I2S interrupt
0
Occurs
I2S interrupt occurs
1
RIGHTCH
Current channel status
1
2
read-only
Left
Current channel is left channel
0
Right
Current channel is right channel
1
RXFIFOEMPTY
RX FIFO empty flag
11
12
read-only
0
RX FIFO is not empty
0
1
RX FIFO is empty
1
RXFIFOFULL
RX FIFO full flag
9
10
read-only
0
RX FIFO is not full
0
1
RX FIFO is full
1
RXFIFOLV
RX FIFO used level
17
21
read-only
0
0/8 RX FIFO is used (Empty)
0
1
1/8 RX FIFO is used
1
2
2/8 RX FIFO is used
2
3
3/8 RX FIFO is used
3
4
4/8 RX FIFO is used
4
5
5/8 RX FIFO is used
5
6
6/8 RX FIFO is used
6
7
7/8 RX FIFO is used
7
8
8/8 RX FIFO is used (Full)
8
RXFIFOTHF
RX FIFO threshold flag
7
8
read-only
0
RXFIFOLV is less equal than RXFIFOTH
0
1
RXFIFOLV is larger than RXFIFOTH
1
TXFIFOEMPTY
TX FIFO empty flag
10
11
read-only
0
TX FIFO is not empty
0
1
TX FIFO is empty
1
TXFIFOFULL
TX FIFO full flag
8
9
read-only
Not full
TX FIFO is not full
0
Full
TX FIFO is full
1
TXFIFOLV
TX FIFO used level
12
16
read-only
0
0/8 TX FIFO is used (Empty)
0
1
1/8 TX FIFO is used
1
2
2/8 TX FIFO is used
2
3
3/8 TX FIFO is used
3
4
4/8 TX FIFO is used
4
5
5/8 TX FIFO is used
5
6
6/8 TX FIFO is used
6
7
7/8 TX FIFO is used
7
8
8/8 TX FIFO is used (Full)
8
TXFIFOTHF
TX FIFO threshold flag
6
7
read-only
0
TXFIFOLV is larger equal than TXFIFOTH
0
1
TXFIFOLV is less than TXFIFOTH
1
TXFIFO
Offset:0x1C I2Sn TX FIFO Register
0x1C
32
write-only
n
0x0
0x0
SN_LCD
LCD Driver
LCD
0x0
0x0
0x2000
registers
n
LCD
LCD Driver
2
CTRL
Offset:0x00 LCD Control register
0x0
32
read-write
n
0x0
0x0
LCDBIA
LCD bias resistance selection bit
14
17
read-write
Disable
Disable
0
75K
75K Ohm
1
225K
225K Ohm
2
56.25K
56.25K Ohm
3
900K
900K Ohm
4
69.23K
69.23K Ohm
5
180K
180K Ohm
6
52.94K
52.94K Ohm
7
LCDBNK
LCD blank control bit
11
12
read-write
Normal
Normal display
0
Blank
All LCD dots Off
1
LCDCKS
LCD clock source selection
10
11
read-write
ILRC
ILRC is LCD clock source
0
ELS XTAL
ELS Xtal is LCD clock source
1
LCDCOM
Duty selection
8
10
read-write
1/4 duty
COM0~COM3 organize 1 frame
0
1/6 duty
COM0~COM5 organize 1 frame
1
1/7 duty
COM0~COM6 organize 1 frame
2
1/8 duty
COM0~COM7 organize 1 frame
3
LCDENB
LCD driver enable bit
0
1
read-write
Disable
Disable LCD
0
Enable
Enable LCD
1
LCDIDLE
LCD idle state enable bit
5
6
read-write
Disable
When LCD is disabled, COM0~7 pins are GPIO
0
Enable
When LCD is disabled, COM0~7 pins are V1 or VDD depends on LSTC bit
1
LCDOUT
LCD VLCD/C2/V1 debug pins output control bit
17
18
read-write
Disable
Disable LCD voltage debug function
0
Enable
Enable LCD voltage debug function
1
LCDRATE
LCD clock rate
12
14
read-write
/16
LCD clock rate=LCD clock source/16
0
/32
LCD clock rate=LCD clock source/32
1
/64
LCD clock rate=LCD clock source/64
2
/128
LCD clock rate=LCD clock source/128
3
LCDSFM
LCD single frame function enable bit
6
7
read-write
Disable
Disable LCD single frame function
0
Enable
Enable LCD single frame function
1
LSTC
LCD static mode control bit
7
8
read-write
1/3 bias
LCD driver is 1/3 bias
0
Static
LCd driver is Static mode
1
VLCD
VLCD voltage adjustment
1
5
read-write
VCC
VLCD=VCC
0
0.97*VCC
VLCD=0.97*VCC
1
0.67*VCC
VLCD=0.67*VCC
10
0.63*VCC
VLCD=0.63*VCC
11
0.60*VCC
VLCD=0.60*VCC
12
0.57*VCC
VLCD=0.57*VCC
13
0.53*VCC
VLCD=0.53*VCC
14
0.50*VCC
VLCD=0.50*VCC
15
0.93*VCC
VLCD=0.93*VCC
2
0.90*VCC
VLCD=0.90*VCC
3
0.87*VCC
VLCD=0.87*VCC
4
0.83*VCC
VLCD=0.83*VCC
5
0.80*VCC
VLCD=0.80*VCC
6
0.77*VCC
VLCD=0.77*VCC
7
0.73*VCC
VLCD=0.73*VCC
8
0.70*VCC
VLCD=0.70*VCC
9
FCC
Offset:0x04 LCD Frame Counter Control register
0x4
32
read-write
n
0x0
0x0
FCENB
LCD frame counter enable bit
0
1
read-write
Disable
Disable LCD frame counter
0
Enable
Enable LCD frame counter
1
FCIE
LCD frame interrupt enable bit
7
8
read-write
Disable
Disable LCD frame interrupt
0
Enable
Enable LCD frame interrupt
1
FCT
LCD frame counter threshold value
1
7
read-write
RIS
Offset:0x08 LCD Raw Interrupt Status register
0x8
32
read-write
n
0x0
0x0
FCIF
LCD frame interrupt flag
0
1
read-write
No
No interrupt
0
Met
FC interrupt requirements met
1
SEGM0
Offset:0x14 LCD SEG Memory register 0
0x14
32
read-write
n
0x0
0x0
SEG0
SEG0 data for COM0~COM7
0
8
read-write
SEG1
SEG1 data for COM0~COM7
8
16
read-write
SEG2
SEG2 data for COM0~COM7
16
24
read-write
SEG3
SEG3 data for COM0~COM7
24
32
read-write
SEGM1
Offset:0x18 LCD SEG Memory register 1
0x18
32
read-write
n
0x0
0x0
SEG4
SEG4 data for COM0~COM7
0
8
read-write
SEG5
SEG5 data for COM0~COM7
8
16
read-write
SEG6
SEG6 data for COM0~COM7
16
24
read-write
SEG7
SEG7 data for COM0~COM7
24
32
read-write
SEGM2
Offset:0x1C LCD SEG Memory register 2
0x1C
32
read-write
n
0x0
0x0
SEG10
SEG10 data for COM0~COM7
16
24
read-write
SEG11
SEG11 data for COM0~COM7
24
32
read-write
SEG8
SEG8 data for COM0~COM7
0
8
read-write
SEG9
SEG9 data for COM0~COM7
8
16
read-write
SEGM3
Offset:0x20 LCD SEG Memory register 3
0x20
32
read-write
n
0x0
0x0
SEG12
SEG12 data for COM0~COM7
0
8
read-write
SEG13
SEG13 data for COM0~COM7
8
16
read-write
SEG14
SEG14 data for COM0~COM7
16
24
read-write
SEG15
SEG15 data for COM0~COM7
24
32
read-write
SEGM4
Offset:0x24 LCD SEG Memory register 4
0x24
32
read-write
n
0x0
0x0
SEG16
SEG16 data for COM0~COM7
0
8
read-write
SEG17
SEG17 data for COM0~COM7
8
16
read-write
SEG18
SEG18 data for COM0~COM7
16
24
read-write
SEG19
SEG19 data for COM0~COM7
24
32
read-write
SEGM5
Offset:0x28 LCD SEG Memory register 5
0x28
32
read-write
n
0x0
0x0
SEG20
SEG20 data for COM0~COM7
0
8
read-write
SEG21
SEG21 data for COM0~COM7
8
16
read-write
SEG22
SEG22 data for COM0~COM7
16
24
read-write
SEG23
SEG23 data for COM0~COM7
24
32
read-write
SEGM6
Offset:0x2C LCD SEG Memory register 6
0x2C
32
read-write
n
0x0
0x0
SEG24
SEG24 data for COM0~COM7
0
8
read-write
SEG25
SEG25 data for COM0~COM7
8
16
read-write
SEG26
SEG26 data for COM0~COM7
16
24
read-write
SEG27
SEG27 data for COM0~COM7
24
32
read-write
SEGM7
Offset:0x30 LCD SEG Memory register 7
0x30
32
read-write
n
0x0
0x0
SEG28
SEG28 data for COM0~COM7
0
8
read-write
SEG29
SEG29 data for COM0~COM7
8
16
read-write
SEG30
SEG30 data for COM0~COM7
16
24
read-write
SEG31
SEG31 data for COM0~COM7
24
32
read-write
SEGM8
Offset:0x34 LCD SEG Memory register 8
0x34
32
read-write
n
0x0
0x0
SEG32
SEG32 data for COM0~COM7
0
8
read-write
SEG33
SEG33 data for COM0~COM7
8
16
read-write
SEG34
SEG34 data for COM0~COM7
16
24
read-write
SEG35
SEG35 data for COM0~COM7
24
32
read-write
SEGM9
Offset:0x38 LCD SEG Memory register 9
0x38
32
read-write
n
0x0
0x0
SEG36
SEG36 data for COM0~COM7
0
8
read-write
SEG37
SEG37 data for COM0~COM7
8
16
read-write
SEG38
SEG38 data for COM0~COM7
16
24
read-write
SEG39
SEG39 data for COM0~COM7
24
32
read-write
SEGSEL1
Offset:0x0C LCD SEG Select register 1
0xC
32
read-write
n
0x0
0x0
SEG0EN
SEG0 Enable bit
0
1
read-write
Disable
Disable SEG0
0
Enable
Enable SEG0
1
SEG10EN
SEG10 Enable bit
10
11
read-write
Disable
Disable SEG10
0
Enable
Enable SEG10
1
SEG11EN
SEG11 Enable bit
11
12
read-write
Disable
Disable SEG11
0
Enable
Enable SEG11
1
SEG12EN
SEG12 Enable bit
12
13
read-write
Disable
Disable SEG12
0
Enable
Enable SEG12
1
SEG13EN
SEG13 Enable bit
13
14
read-write
Disable
Disable SEG13
0
Enable
Enable SEG13
1
SEG14EN
SEG14 Enable bit
14
15
read-write
Disable
Disable SEG14
0
Enable
Enable SEG14
1
SEG15EN
SEG15 Enable bit
15
16
read-write
Disable
Disable SEG15
0
Enable
Enable SEG15
1
SEG16EN
SEG16 Enable bit
16
17
read-write
Disable
Disable SEG16
0
Enable
Enable SEG16
1
SEG17EN
SEG17 Enable bit
17
18
read-write
Disable
Disable SEG17
0
Enable
Enable SEG17
1
SEG18EN
SEG18 Enable bit
18
19
read-write
Disable
Disable SEG18
0
Enable
Enable SEG18
1
SEG19EN
SEG19 Enable bit
19
20
read-write
Disable
Disable SEG19
0
Enable
Enable SEG19
1
SEG1EN
SEG1 Enable bit
1
2
read-write
Disable
Disable SEG1
0
Enable
Enable SEG1
1
SEG20EN
SEG20 Enable bit
20
21
read-write
Disable
Disable SEG20
0
Enable
Enable SEG20
1
SEG21EN
SEG21 Enable bit
21
22
read-write
Disable
Disable SEG21
0
Enable
Enable SEG21
1
SEG22EN
SEG22 Enable bit
22
23
read-write
Disable
Disable SEG22
0
Enable
Enable SEG22
1
SEG23EN
SEG23 Enable bit
23
24
read-write
Disable
Disable SEG23
0
Enable
Enable SEG23
1
SEG24EN
SEG24 Enable bit
24
25
read-write
Disable
Disable SEG24
0
Enable
Enable SEG24
1
SEG25EN
SEG25 Enable bit
25
26
read-write
Disable
Disable SEG25
0
Enable
Enable SEG25
1
SEG26EN
SEG26 Enable bit
26
27
read-write
Disable
Disable SEG26
0
Enable
Enable SEG26
1
SEG27EN
SEG27 Enable bit
27
28
read-write
Disable
Disable SEG27
0
Enable
Enable SEG27
1
SEG28EN
SEG28 Enable bit
28
29
read-write
Disable
Disable SEG28
0
Enable
Enable SEG28
1
SEG29EN
SEG29 Enable bit
29
30
read-write
Disable
Disable SEG29
0
Enable
Enable SEG29
1
SEG2EN
SEG2 Enable bit
2
3
read-write
Disable
Disable SEG2
0
Enable
Enable SEG2
1
SEG30EN
SEG30 Enable bit
30
31
read-write
Disable
Disable SEG30
0
Enable
Enable SEG30
1
SEG31EN
SEG31 Enable bit
31
32
read-write
Disable
Disable SEG31
0
Enable
Enable SEG31
1
SEG3EN
SEG3 Enable bit
3
4
read-write
Disable
Disable SEG3
0
Enable
Enable SEG3
1
SEG4EN
SEG4 Enable bit
4
5
read-write
Disable
Disable SEG4
0
Enable
Enable SEG4
1
SEG5EN
SEG5 Enable bit
5
6
read-write
Disable
Disable SEG5
0
Enable
Enable SEG5
1
SEG6EN
SEG6 Enable bit
6
7
read-write
Disable
Disable SEG6
0
Enable
Enable SEG6
1
SEG7EN
SEG7 Enable bit
7
8
read-write
Disable
Disable SEG7
0
Enable
Enable SEG7
1
SEG8EN
SEG8 Enable bit
8
9
read-write
Disable
Disable SEG8
0
Enable
Enable SEG8
1
SEG9EN
SEG9 Enable bit
9
10
read-write
Disable
Disable SEG9
0
Enable
Enable SEG9
1
SEGSEL2
Offset:0x10 LCD SEG Select register 2
0x10
32
read-write
n
0x0
0x0
SEG32EN
SEG32 Enable bit
0
1
read-write
Disable
Disable SEG32
0
Enable
Enable SEG32
1
SEG33EN
SEG33 Enable bit
1
2
read-write
Disable
Disable SEG33
0
Enable
Enable SEG33
1
SEG34EN
SEG34 Enable bit
2
3
read-write
Disable
Disable SEG34
0
Enable
Enable SEG34
1
SEG35EN
SEG35 Enable bit
3
4
read-write
Disable
Disable SEG35
0
Enable
Enable SEG35
1
SEG36EN
SEG36 Enable bit
4
5
read-write
Disable
Disable SEG36
0
Enable
Enable SEG36
1
SEG37EN
SEG37 Enable bit
5
6
read-write
Disable
Disable SEG37
0
Enable
Enable SEG37
1
SEG38EN
SEG38 Enable bit
6
7
read-write
Disable
Disable SEG38
0
Enable
Enable SEG38
1
SEG39EN
SEG39 Enable bit
7
8
read-write
Disable
Disable SEG39
0
Enable
Enable SEG39
1
SN_OPA
OP Amplifier
OPA
0x0
0x0
0x2000
registers
n
CTRL
Offset:0x0 OPA Control Register
0x0
32
read-write
n
0x0
0x0
OP0EN
OP-Amp 0 enable bit
0
1
read-write
Disable
Disable OPA0
0
Enable
Enable OPA0
1
OP0NS
OP-Amp 0 Negatiove input selection bit
4
5
read-write
VOPAIREF
OP0N pin is GPIO mode.
0
OP0N
OP0N is OPA0 negative input pin, and isolate GPIO function
1
OP0PS
OP-Amp 0 Positive input selection bit
3
4
read-write
VOPAIREF
OP0P pin is GPIO mode.
0
OP0P
OP0P is OPA0 positive input pin, and isolate GPIO function
1
OP1EN
OP-Amp 1 enable bit
8
9
read-write
Disable
Disable OPA1
0
Enable
Enable OPA1
1
OP1NS
OP-Amp 1 Negatiove input selection bit
12
13
read-write
VOPAIREF
OP1N pin is GPIO mode.
0
OP1N
OP1N is OPA1 negative input pin, and isolate GPIO function
1
OP1PS
OP-Amp 1 Positive input selection bit
11
12
read-write
VOPAIREF
OP1P pin is GPIO mode.
0
OP0P
OP1P is OPA1 positive input pin, and isolate GPIO function
1
SN_PFPA
Peripheral Function Pin Assignment
PFPA
0x0
0x0
0x2000
registers
n
CT16B0
Offset:0x00 PFPA for CT16B0 Register
0x0
32
read-write
n
0x0
0x0
PWM0
CT16B0_PWM0 assigned pin
0
2
read-write
P0.2
CT16B0_PWM0=P0.2
0
P3.0
CT16B0_PWM0=P3.0
1
P2.6
CT16B0_PWM0=P2.6
2
P1.12
CT16B0_PWM0=P1.12
3
PWM0N
CT16B0_PWM0N assigned pin
2
4
read-write
P0.3
CT16B0_PWM0N=P0.3
0
P1.13
CT16B0_PWM0N=P1.13
1
P2.7
CT16B0_PWM0N=P2.7
2
P0.12
CT16B0_PWM0N=P0.12
3
PWM1
CT16B0_PWM1 assigned pin
4
6
read-write
P2.9
CT16B0_PWM1=P2.9
0
P3.1
CT16B0_PWM1=P3.1
1
P0.1
CT16B0_PWM1=P0.1
2
P2.5
CT16B0_PWM1=P2.5
3
PWM1N
CT16B0_PWM1N assigned pin
6
8
read-write
P1.14
CT16B0_PWM1N=P1.14
0
P0.0
CT16B0_PWM1N=P0.0
1
P2.8
CT16B0_PWM1N=P2.8
2
P2.4
CT16B0_PWM1N=P2.4
3
PWM2
CT16B0_PWM2 assigned pin
8
10
read-write
P2.7
CT16B0_PWM2=P2.7
0
P3.2
CT16B0_PWM2=P3.2
1
P0.0
CT16B0_PWM2=P0.0
2
P2.8
CT16B0_PWM2=P2.8
3
PWM2N
CT16B0_PWM2N assigned pin
10
12
read-write
P1.15
CT16B0_PWM2N=P1.15
0
P2.6
CT16B0_PWM2N=P2.6
1
P2.9
CT16B0_PWM2N=P2.9
2
P0.1
CT16B0_PWM2N=P0.1
3
PWM3
CT16B0_PWM3 assigned pin
12
14
read-write
P0.1
CT16B0_PWM3=P0.1
0
P3.3
CT16B0_PWM3=P3.3
1
P0.3
CT16B0_PWM3=P0.3
2
P2.14
CT16B0_PWM3=P2.14
3
PWM3N
CT16B0_PWM3N assigned pin
14
16
read-write
P0.0
CT16B0_PWM3N=P0.0
0
P1.16
CT16B0_PWM3N=P1.16
1
P0.2
CT16B0_PWM3N=P0.2
2
P2.15
CT16B0_PWM3N=P2.15
3
CT16B1
Offset:0x04 PFPA for CT16B1 Register
0x4
32
read-write
n
0x0
0x0
PWM00
CT16B1_PWM00 assigned pin
0
1
read-write
P0.0
CT16B1_PWM00=P0.0
0
P1.8
CT16B1_PWM00=P1.8
1
PWM01
CT16B1_PWM01 assigned pin
1
2
read-write
P0.1
CT16B1_PWM01=P0.1
0
P1.9
CT16B1_PWM01=P1.9
1
PWM02
CT16B1_PWM02 assigned pin
2
3
read-write
P0.2
CT16B1_PWM02=P0.2
0
P1.10
CT16B1_PWM02=P1.10
1
PWM03
CT16B1_PWM03 assigned pin
3
4
read-write
P0.3
CT16B1_PWM03=P0.3
0
P1.11
CT16B1_PWM03=P1.11
1
PWM04
CT16B1_PWM04 assigned pin
4
5
read-write
P0.4
CT16B1_PWM04=P0.4
0
P1.12
CT16B1_PWM04=P1.12
1
PWM05
CT16B1_PWM05 assigned pin
5
6
read-write
P0.5
CT16B1_PWM05=P0.5
0
P1.13
CT16B1_PWM05=P1.13
1
PWM06
CT16B1_PWM06 assigned pin
6
7
read-write
P0.6
CT16B1_PWM06=P0.6
0
P1.14
CT16B1_PWM06=P1.14
1
PWM07
CT16B1_PWM07 assigned pin
7
8
read-write
P0.7
CT16B1_PWM07=P0.7
0
P1.15
CT16B1_PWM07=P1.15
1
PWM08
CT16B1_PWM08 assigned pin
8
9
read-write
P0.8
CT16B1_PWM08=P0.8
0
P2.0
CT16B1_PWM08=P2.0
1
PWM09
CT16B1_PWM09 assigned pin
9
10
read-write
P0.9
CT16B1_PWM09=P0.9
0
P2.4
CT16B1_PWM09=P2.4
1
PWM10
CT16B1_PWM10 assigned pin
10
11
read-write
P0.10
CT16B1_PWM10=P0.10
0
P2.7
CT16B1_PWM10=P2.7
1
PWM11
CT16B1_PWM11 assigned pin
11
12
read-write
P0.11
CT16B1_PWM11=P0.11
0
P2.9
CT16B1_PWM11=P2.9
1
CT16B2
Offset:0x18 PFPA for CT16B2 Register
0x18
32
read-write
n
0x0
0x0
PWM0
CT16B2_PWM0 assigned pin
0
2
read-write
P2.0
CT16B2_PWM0=P2.0
0
P2.5
CT16B2_PWM0=P2.5
1
P1.8
CT16B2_PWM0=P1.8
2
P0.0
CT16B2_PWM0=P0.0
3
PWM1
CT16B2_PWM1 assigned pin
2
4
read-write
P2.1
CT16B2_PWM1=P2.1
0
P1.0
CT16B2_PWM1=P1.0
1
P1.7
CT16B2_PWM1=P1.7
2
P0.3
CT16B2_PWM1=P0.3
3
PWM2
CT16B2_PWM2 assigned pin
4
6
read-write
P2.2
CT16B2_PWM2=P2.2
0
P0.1
CT16B2_PWM2=P0.1
1
P1.6
CT16B2_PWM2=P1.6
2
P1.18
CT16B2_PWM2=P1.18
3
PWM3
CT16B2_PWM3 assigned pin
6
8
read-write
P2.3
CT16B2_PWM3=P2.3
0
P0.2
CT16B2_PWM3=P0.2
1
P1.10
CT16B2_PWM3=P1.10
2
P1.17
CT16B2_PWM3=P1.17
3
CT16B3
Offset:0x1C PFPA for CT16B3 Register
0x1C
32
read-write
n
0x0
0x0
PWM0
CT16B3_PWM0 assigned pin
0
2
read-write
P1.14
CT16B3_PWM0=P1.14
0
P2.2
CT16B3_PWM0=P2.2
1
P2.6
CT16B3_PWM0=P2.6
2
P1.4
CT16B3_PWM0=P1.4
3
PWM0N
CT16B3_PWM0N assigned pin
2
4
read-write
P1.15
CT16B3_PWM0N=P1.15
0
P2.1
CT16B3_PWM0N=P2.1
1
P0.10
CT16B3_PWM0N=P0.10
2
P1.3
CT16B3_PWM0N=P1.3
3
PWM1
CT16B3_PWM1 assigned pin
4
6
read-write
P2.3
CT16B3_PWM1=P2.3
0
P1.15
CT16B3_PWM1=P1.15
1
P1.12
CT16B3_PWM1=P1.12
2
P1.5
CT16B3_PWM1=P1.5
3
PWM1N
CT16B0_PWM1N assigned pin
6
8
read-write
P2.4
CT16B0_PWM1N=P2.4
0
P0.11
CT16B0_PWM1N=P0.11
1
P1.13
CT16B0_PWM1N=P1.13
2
P0.8
CT16B0_PWM1N=P0.8
3
CT16B4
Offset:0x20 PFPA for CT16B4 Register
0x20
32
read-write
n
0x0
0x0
PWM0
CT16B4_PWM0 assigned pin
0
2
read-write
P2.7
CT16B4_PWM0=P2.7
0
P1.5
CT16B4_PWM0=P1.5
1
P0.10
CT16B4_PWM0=P0.10
2
P0.9
CT16B4_PWM0=P0.9
3
PWM0N
CT16B4_PWM0N assigned pin
2
4
read-write
P0.11
CT16B4_PWM0N=P0.11
0
P2.6
CT16B4_PWM0N=P2.6
1
P1.2
CT16B4_PWM0N=P1.2
2
P0.8
CT16B4_PWM0N=P0.8
3
PWM1
CT16B4_PWM1 assigned pin
4
6
read-write
P2.6
CT16B4_PWM1=P2.6
0
P1.4
CT16B4_PWM1=P1.4
1
P2.5
CT16B4_PWM1=P2.5
2
P1.12
CT16B4_PWM1=P1.12
3
PWM1N
CT16B4_PWM1N assigned pin
6
8
read-write
P0.10
CT16B4_PWM1N=P0.10
0
P1.3
CT16B4_PWM1N=P1.3
1
P2.4
CT16B4_PWM1N=P2.4
2
P1.13
CT16B4_PWM1N=P1.13
3
CT16B5
Offset:0x24 PFPA for CT16B5 Register
0x24
32
read-write
n
0x0
0x0
PWM0
CT16B5_PWM0 assigned pin
0
2
read-write
P2.6
CT16B5_PWM0=P2.6
0
P0.15
CT16B5_PWM0=P0.15
1
P1.1
CT16B5_PWM0=P1.1
2
P3.16
CT16B5_PWM0=P3.16
3
PWM1
CT16B5_PWM1 assigned pin
2
4
read-write
P2.7
CT16B5_PWM1=P2.7
0
P0.14
CT16B5_PWM1=P0.14
1
P1.2
CT16B5_PWM1=P1.2
2
P3.17
CT16B2_PWM5=P3.17
3
PWM2
CT16B5_PWM2 assigned pin
4
6
read-write
P2.8
CT16B5_PWM2=P2.8
0
P0.13
CT16B5_PWM2=P0.13
1
P1.0
CT16B5_PWM2=P1.0
2
P3.18
CT16B5_PWM2=P3.18
3
PWM3
CT16B5_PWM3 assigned pin
6
8
read-write
P2.9
CT16B5_PWM3=P2.9
0
P0.12
CT16B5_PWM3=P0.12
1
P1.18
CT16B5_PWM3=P1.18
2
P3.19
CT16B5_PWM3=P3.19
3
I2C
Offset:0x0C PFPA for I2C Register
0xC
32
read-write
n
0x0
0x0
SCL0
SCL0 assigned pin
2
4
read-write
P0.6
SCL0=P0.6
0
P1.4
SCL0=P1.4
1
P0.10
SCL0=P0.10
2
P1.1
SCL0=P1.1
3
SCL1
SCL1 assigned pin
6
8
read-write
P1.10
SCL1=P1.10
0
P1.13
SCL1=P1.13
1
P0.1
SCL1=P0.1
2
P1.8
SCL1=P1.8
3
SDA0
SDA0 assigned pin
0
2
read-write
P0.7
SDA0=P0.7
0
P1.5
SDA0=P1.5
1
P0.11
SDA0=P0.11
2
P1.2
SDA0=P1.2
3
SDA1
SDA1 assigned pin
4
6
read-write
P1.11
SDA1=P1.11
0
P1.14
SDA1=P1.14
1
P0.2
SDA1=P0.2
2
P1.9
SDA1=P1.9
3
I2S
Offset:0x14 PFPA for I2S Register
0x14
32
read-write
n
0x0
0x0
BCLK0
BCLK0 assigned pin
2
4
read-write
P3.1
BCLK0=P3.1
0
P2.5
BCLK0=P2.5
1
P1.0
BCLK0=P1.0
2
BCLK1
BCLK1 assigned pin
12
14
read-write
P3.17
BCLK1=P3.17
0
P1.6
BCLK1=P1.6
1
P1.13
BCLK1=P1.13
2
P0.1
BCLK1=P0.1
3
DIN0
DIN0 assigned pin
8
10
read-write
P3.4
DIN0=P3.4
0
P2.8
DIN0=P2.8
1
P1.3
DIN0=P1.3
2
DIN1
DIN1 assigned pin
18
20
read-write
P3.18
DIN0=P3.18
0
P1.1
DIN0=P1.1
1
P1.19
DIN0=P1.19
2
P1.10
DIN0=P1.10
3
DOUT0
DOUT0 assigned pin
6
8
read-write
P3.3
DOUT0=P3.3
0
P2.7
DOUT0=P2.7
1
P1.2
DOUT0=P1.2
2
DOUT1
DOUT1 assigned pin
16
18
read-write
P3.15
DOUT1=P3.15
0
P1.2
DOUT1=P1.2
1
P1.15
DOUT1=P1.15
2
P2.13
DOUT1=P2.13
3
MCLK0
MCLK0 assigned pin
0
2
read-write
P3.0
MCLK0=P3.0
0
P2.6
MCLK0=P2.6
1
P1.1
MCLK0=P1.1
2
MCLK1
MCLK1 assigned pin
10
12
read-write
P3.14
MCLK1=P3.14
0
P1.7
MCLK1=P1.7
1
P1.14
MCLK1=P1.14
2
P2.12
MCLK1=P2.12
3
WS0
WS0 assigned pin
4
6
read-write
P3.2
WS0=P3.2
0
P2.4
WS0=P2.4
1
P1.8
WS0=P1.8
2
WS1
WS1 assigned pin
14
16
read-write
P3.16
WS1=P3.16
0
P1.5
WS1=P1.5
1
P1.12
WS1=P1.12
2
P1.9
WS1=P1.9
3
SPI
Offset:0x10 PFPA for SPI Register
0x10
32
read-write
n
0x0
0x0
MISO0
MISO0 assigned pin
0
2
read-write
P0.2
MISO0=P0.2
0
P2.6
MISO0=P2.6
1
P1.1
MISO0=P1.1
2
P3.1
MISO0=P3.1
3
MISO1
MISO1 assigned pin
8
10
read-write
P1.14
MISO1=P1.14
0
P1.10
MISO1=P1.10
1
P2.12
MISO1=P2.12
2
P3.14
MISO1=P3.14
3
MOSI0
MOSI0 assigned pin
2
4
read-write
P0.3
MOSI0=P0.3
0
P2.7
MOSI0=P2.7
1
P1.2
MOSI0=P1.2
2
P3.2
MOSI0=P3.2
3
MOSI1
MOSI1 assigned pin
10
12
read-write
P1.15
MOSI1=P1.15
0
P1.11
MOSI1=P1.11
1
P2.13
MOSI1=P2.13
2
P3.15
MOSI1=P3.15
3
SCK0
SCK0 assigned pin
4
6
read-write
P0.0
SCK0=P0.0
0
P2.5
SCK0=P2.5
1
P1.0
SCK0=P1.0
2
P3.0
SCK0=P3.0
3
SCK1
SCK1 assigned pin
12
14
read-write
P1.13
SCK1=P1.13
0
P1.8
SCK1=P1.8
1
P0.1
SCK1=P0.1
2
P0.12
SCK1=P0.12
3
SEL0
SEL0 assigned pin
6
8
read-write
P0.1
SEL0=P0.1
0
P2.4
SEL0=P2.4
1
P1.8
SEL0=P1.8
2
P1.7
SCK0=P1.7
3
SEL1
SEL1 assigned pin
14
16
read-write
P1.12
SEL1=P1.12
0
P1.9
SEL1=P1.9
1
P1.5
SEL1=P1.5
2
P0.13
SEL1=P0.13
3
UART
Offset:0x08 PFPA for UART Register
0x8
32
read-write
n
0x0
0x0
URXD0
URXD0 assigned pin
2
4
read-write
P0.11
URXD0=P0.11
0
P2.0
URXD0=P2.0
1
P3.2
URXD0=P3.2
2
URXD1
URXD1 assigned pin
6
8
read-write
P1.8
URXD1=P1.8
0
P2.3
URXD1=P2.3
1
P1.17
URXD1=P1.17
2
P3.4
URXD1=P3.4
3
URXD2
URXD2 assigned pin
10
12
read-write
P0.2
URXD2=P0.2
0
P1.3
URXD2=P1.3
1
P2.15
URXD2=P2.15
2
P1.6
URXD2=P1.6
3
URXD3
URXD3 assigned pin
14
16
read-write
P3.13
URXD3=P3.13
0
P1.6
URXD3=P1.6
1
P2.1
URXD3=P2.1
2
UTXD0
UTXD0 assigned pin
0
2
read-write
P0.10
UTXD0=P0.10
0
P2.1
UTXD0=P2.1
1
P3.1
UTXD0=P3.1
2
UTXD1
UTXD1 assigned pin
4
6
read-write
P1.9
UTXD1=P1.9
0
P2.2
UTXD1=P2.2
1
P1.16
UTXD1=P1.16
2
P3.6
UTXD1=P3.6
3
UTXD2
UTXD2 assigned pin
8
10
read-write
P0.1
UTXD2=P0.1
0
P1.4
UTXD2=P1.4
1
P2.14
UTXD2=P2.14
2
P1.7
UTXD2=P1.7
3
UTXD3
UTXD3 assigned pin
12
14
read-write
P3.12
UTXD3=P3.12
0
P1.7
UTXD3=P1.7
1
P2.0
UTXD3=P2.0
2
SN_PMU
Power Management Unit
PMU
0x0
0x0
0x2000
registers
n
CTRL
Offset:0x40 PMU Control Register
0x40
32
read-write
n
0x0
0x0
MODE
Low Power mode selection
0
3
read-write
Disable
Disable
0
Deep-sleep mode
WFI instruction will make MCU enter Deep-sleep mode
2
Sleep mode
WFI instruction will make MCU enter Sleep mode
4
SN_RTC
Real-time Clock
RTC
0x0
0x0
0x2000
registers
n
RTC
Real-time Clock
23
CLKS
Offset:0x04 RTC Clock Source Register
0x4
32
read-write
n
0x0
0x0
CLKSEL
RTC clock source
0
1
read-write
ILRC
RTC clock source=ILRC
0
ELS XTAL
RTC clock source=ELS XTAL
1
CTRL
Offset:0x00 RTC Control Register
0x0
32
read-write
n
0x0
0x0
RTCEN
RTC enable
0
1
read-write
Disable
Disable RTC
0
Enable
Enable RTC
1
IC
Offset:0x10 RTC Interrupt Clear Register
0x10
32
write-only
n
0x0
0x0
SECIC
Second interrupt flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear second interrupt flag
1
IE
Offset:0x08 RTC Interrupt Enable Register
0x8
32
read-write
n
0x0
0x0
SECIE
Second interrupt enable
0
1
read-write
Disable
Disable second interrupt
0
Enable
Enable second interrupt
1
RIS
Offset:0x0C RTC Raw Interrupt Status Register
0xC
32
read-only
n
0x0
0x0
SECIF
Second interrupt flag
0
1
read-only
No
No second interrupt
0
Met
Second interrupt is triggered when SECIE=1
1
SECCNT
Offset:0x18 RTC Second Counter Register
0x18
32
read-only
n
0x0
0x0
SECCNTV
Offset:0x14 RTC Second Counter Reload Value Register
0x14
32
read-write
n
0x0
0x0
SN_SPI0
SPI0
SPI
0x0
0x0
0x2000
registers
n
SPI0
SPI0
6
CLKDIV
Offset:0x08 SPI0 Clock Divider Register
0x8
32
read-write
n
0x0
0x0
DIV
SPI0 SCK
0
8
read-write
CTRL0
Offset:0x00 SPI0 Control Register 0
0x0
32
read-write
n
0x0
0x0
DL
Data length = DL[3:0]+1
8
12
read-write
1010
Data length=11
10
1011
Data length=12
11
1100
Data length=13
12
1101
Data length=14
13
1110
Data length=15
14
1111
Data length=16
15
0010
Data length=3
2
0011
Data length=4
3
0100
Data length=5
4
0101
Data length=6
5
0110
Data length=7
6
0111
Data length=8
7
1000
Data length=9
8
1001
Data length=10
9
FORMAT
Interface format
4
5
read-write
SPI
SPI format
0
FRESET
SPI FSM and FIFO Reset
6
8
write-only
00
No effect
0
11
Reset FSM and FIFO
3
LOOPBACK
Loopback mode enable
1
2
read-write
Disable
Disable loopback mode
0
Enable
Enable loopback mode
1
MS
Master/Slave selection
3
4
read-write
Master
Act as Master
0
Slave
Act as Slave
1
RXFIFOTH
RX FIFO Threshold level
15
18
read-write
0
RX FIFO threshold level is 0
0
1
RX FIFO threshold level is 1
1
2
RX FIFO threshold level is 2
2
3
RX FIFO threshold level is 3
3
4
RX FIFO threshold level is 4
4
5
RX FIFO threshold level is 5
5
6
RX FIFO threshold level is 6
6
7
RX FIFO threshold level is 7
7
SDODIS
Slave data out disable
2
3
read-write
Enable
Enable slave data out
0
Disble
Diable slave data out (MISO=0)
1
SELDIS
Auto-SEL disable bit
18
19
read-write
Enable
Enable Auto-SEL flow control
0
Disable
Disable Auto-SEL flow control
1
SPIEN
SPI enable
0
1
read-write
Disable
Disable SPI
0
Enable
Enable SPI
1
TXFIFOTH
TX FIFO Threshold level
12
15
read-write
0
TX FIFO threshold level is 0
0
1
TX FIFO threshold level is 1
1
2
TX FIFO threshold level is 2
2
3
TX FIFO threshold level is 3
3
4
TX FIFO threshold level is 4
4
5
TX FIFO threshold level is 5
5
6
TX FIFO threshold level is 6
6
7
TX FIFO threshold level is 7
7
CTRL1
Offset:0x04 SPI0 Control Register 1
0x4
32
read-write
n
0x0
0x0
CPHA
Clock phase of edge sampling
2
3
read-write
CPHA0
The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data
0
CPHA1
SCK 1st edge is for data transition, and receive/transmit data at 2nd edge
1
CPOL
Clock priority selection
1
2
read-write
Low
SCK idles at low level
0
High
SCK idles at high level
1
MLSB
MSB/LSB seletion
0
1
read-write
MSB
MSB transmit first
0
LSB
LSB transmit first
1
CURCNT
Offset:0x30 SPI0 DMA Control register
0x30
32
read-only
n
0x0
0x0
CURCNT
This field indicates DMA current transfer data counter pointer.
0
28
read-only
DATA
Offset:0x1C SPI0 Data Register
0x1C
32
read-write
n
0x0
0x0
Data
Data
0
16
read-write
DFDLY
Offset:0x20 SPI0 Data Fetch Register
0x20
32
read-write
n
0x0
0x0
DFETCH_EN
SPI0 data fetch control bit
0
1
read-write
Disable
Disable
0
Enable
Enable when SCKn frequency is higher than 6MHz
1
DMACNT
Offset:0x28 SPI0 DMA Control register
0x28
32
read-write
n
0x0
0x0
CNT
Number of data to DMA RX count transfer
0
28
read-write
DMACTRL
Offset:0x24 SPI0 DMA Control register
0x24
32
read-write
n
0x0
0x0
DIR
SPI data transfer direction
1
2
read-write
SPI1toSPI0
SPI1_DATA(RX) to SPI0_DATA(TX), when DMATCIE and DMAHTIE enable, and trigger SPI0 interrupt
0
SPI0toSPI1
SPI0_DATA(RX) to SPI1_DATA(TX) , when DMATCIE and DMAHTIE enable, and trigger SPI1 interrupt
1
DMAEN
SPI to SPI DMA enable bit
0
1
read-write
Disable
Disable
0
Enable
Enable
1
DMAHTCNT
Offset:0x2C SPI0 DMA Control register
0x2C
32
read-write
n
0x0
0x0
HTCNT
Number of data to DMA RX half count transfer
0
28
read-write
IC
Offset:0x18 SPI0 Interrupt Clear Register
0x18
32
write-only
n
0x0
0x0
DMAHTIC
Select the DMAHTIF flag to be cleared
4
5
write-only
No effect
No effect
0
Clear
Clear DMAHTIF flag
1
DMATCIC
Select the DMATCIF flag to be cleared
5
6
write-only
No effect
No effect
0
Clear
Clear DMATCIF flag
1
RXFIFOTHIC
RX Interrupt flag Clear
2
3
write-only
No effect
No effect
0
Clear
Clear RXFIFOTH flag
1
RXOVFIC
RX FIFO overflow flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear RXOVF flag
1
RXTOIC
RX time-out interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear RXTO flag
1
TXFIFOTHIC
TX Interrupt flag Clear
3
4
write-only
No effect
No effect
0
Clear
Clear TXFIFOTH flag
1
IE
Offset:0x10 SPI0 Interrupt Enable Register
0x10
32
read-write
n
0x0
0x0
DMAHTIE
DMA half transfer interrupt enable bit
4
5
read-write
Disable
Disable DMA half transfer interrupt
0
Enable
Enable DMA half transfer interrupt
1
DMATCIE
DMA transfer complete interrupt enable bit
5
6
read-write
Disable
Disable DMA transfer complete interrupt
0
Enable
Enable DMA transfer complete interrupt
1
RXFIFOTHIE
RX FIFO threshold interrupt enable
2
3
read-write
Disable
Disable RX FIFO threshold interrupt
0
Enable
Enable RX FIFO threshold interrupt
1
RXOVFIE
RX FIFO overflow interrupt enable
0
1
read-write
Disable
Disable RX FIFO overflow interrupt
0
Enable
Enable RX FIFO overflow interrupt
1
RXTOIE
RX time-out interrupt enable
1
2
read-write
Disable
Disable RX time-out interrupt
0
Enable
Enable RX time-out interrupt
1
TXFIFOTHIE
TX FIFO threshold interrupt enable
3
4
read-write
Disable
Disable TX FIFO threshold interrupt
0
Enable
Enable TX FIFO threshold interrupt
1
RIS
Offset:0x14 SPI0 Raw Interrupt Status Register
0x14
32
read-only
n
0x0
0x0
DMAHTIF
RX FIFO threshold interrupt flag
4
5
read-only
No
No half transfer event
0
Met
A half transfer event occurs
1
DMATCIF
DMA transfer complete flag
5
6
read-only
No
No transfer completion
0
Met
A transfer complete event occurs
1
RXFIFOTHIF
RX FIFO threshold interrupt flag
2
3
read-only
No
No RXFIFOTH interrupt
0
Met
RX FIFO threshold is triggered when RXFIFOTHIE=1
1
RXOVFIF
RX FIFO overflow interrupt flag
0
1
read-only
No
No RXOVF interrupt
0
Met
RXOVF interrupt is triggered when RXOVFIE=1
1
RXTOIF
RX time-out interrupt flag
1
2
read-only
No
No RXTO interrupt
0
Met
RXTO interrupt is triggered when RXTOIE=1
1
TXFIFOTHIF
TX FIFO threshold interrupt flag
3
4
read-only
No
No TXFIFOTH interrupt
0
Met
TX FIFO threshold is triggered when TXFIFOTHIE=1
1
STAT
Offset:0x0C SPI0 Status Register
0xC
32
read-only
n
0x0
0x0
BUSY
Busy flag
4
5
read-only
Idle
SSPn is idle
0
Busy
SSPn is transfering
1
RXFIFOTHF
RX FIFO threshold flag
6
7
read-only
0
Data count in RX FIFO is less equal than RXFIFOTH
0
1
Data count in RX FIFO is larger than RXFIFOTH
1
RX_EMPTY
RX FIFO empty flag
2
3
read-only
0
RX FIFO is not empty
0
1
RX FIFO is empty
1
RX_FULL
RX FIFO full flag
3
4
read-only
0
RX FIFO is not full
0
1
RX FIFO is full
1
TXFIFOTHF
TX FIFO threshold flag
5
6
read-only
0
Data count in TX FIFO is larger than TXFIFOTH
0
1
Data count in TX FIFO is less equal than TXFIFOTH
1
TX_EMPTY
TX FIFO empty flag
0
1
read-only
0
TX FIFO is not empty
0
1
TX FIFO is empty
1
TX_FULL
TX FIFO full flag
1
2
read-only
0
TX FIFO is not full
0
1
TX FIFO is full
1
SN_SPI1
SPI1
SPI
0x0
0x0
0x2000
registers
n
SPI1
SPI1
7
CLKDIV
Offset:0x08 SPI1 Clock Divider Register
0x8
32
read-write
n
0x0
0x0
DIV
SPI1 SCK
0
8
read-write
CTRL0
Offset:0x00 SPI1 Control Register 0
0x0
32
read-write
n
0x0
0x0
DL
Data length = DL[3:0]+1
8
12
read-write
1010
Data length=11
10
1011
Data length=12
11
1100
Data length=13
12
1101
Data length=14
13
1110
Data length=15
14
1111
Data length=16
15
0010
Data length=3
2
0011
Data length=4
3
0100
Data length=5
4
0101
Data length=6
5
0110
Data length=7
6
0111
Data length=8
7
1000
Data length=9
8
1001
Data length=10
9
FORMAT
Interface format
4
5
read-write
SPI
SPI format
0
FRESET
SPI FSM and FIFO Reset
6
8
write-only
00
No effect
0
11
Reset FSM and FIFO
3
LOOPBACK
Loopback mode enable
1
2
read-write
Disable
Disable loopback mode
0
Enable
Enable loopback mode
1
MS
Master/Slave selection
3
4
read-write
Master
Act as Master
0
Slave
Act as Slave
1
RXFIFOTH
RX FIFO Threshold level
15
18
read-write
0
RX FIFO threshold level is 0
0
1
RX FIFO threshold level is 1
1
2
RX FIFO threshold level is 2
2
3
RX FIFO threshold level is 3
3
4
RX FIFO threshold level is 4
4
5
RX FIFO threshold level is 5
5
6
RX FIFO threshold level is 6
6
7
RX FIFO threshold level is 7
7
SDODIS
Slave data out disable
2
3
read-write
Enable
Enable slave data out
0
Disble
Diable slave data out (MISO=0)
1
SELDIS
Auto-SEL disable bit
18
19
read-write
Enable
Enable Auto-SEL flow control
0
Disable
Disable Auto-SEL flow control
1
SPIEN
SPI enable
0
1
read-write
Disable
Disable SPI
0
Enable
Enable SPI
1
TXFIFOTH
TX FIFO Threshold level
12
15
read-write
0
TX FIFO threshold level is 0
0
1
TX FIFO threshold level is 1
1
2
TX FIFO threshold level is 2
2
3
TX FIFO threshold level is 3
3
4
TX FIFO threshold level is 4
4
5
TX FIFO threshold level is 5
5
6
TX FIFO threshold level is 6
6
7
TX FIFO threshold level is 7
7
CTRL1
Offset:0x04 SPI1 Control Register 1
0x4
32
read-write
n
0x0
0x0
CPHA
Clock phase of edge sampling
2
3
read-write
CPHA0
The 1st bit is fixed already, and SCK 1st edge is to receive/transmit data
0
CPHA1
SCK 1st edge is for data transition, and receive/transmit data at 2nd edge
1
CPOL
Clock priority selection
1
2
read-write
Low
SCK idles at low level
0
High
SCK idles at high level
1
MLSB
MSB/LSB seletion
0
1
read-write
MSB
MSB transmit first
0
LSB
LSB transmit first
1
DATA
Offset:0x1C SPI1 Data Register
0x1C
32
read-write
n
0x0
0x0
Data
Data
0
16
read-write
DFDLY
Offset:0x20 SPI1 Data Fetch Register
0x20
32
read-write
n
0x0
0x0
DFETCH_EN
SPI1 data fetch control bit
0
1
read-write
Disable
Disable
0
Enable
Enable when SCKn frequency is higher than 6MHz
1
IC
Offset:0x18 SPI1 Interrupt Clear Register
0x18
32
write-only
n
0x0
0x0
RXFIFOTHIC
RX Interrupt flag Clear
2
3
write-only
No effect
No effect
0
Clear
Clear RXFIFOTH flag
1
RXOVFIC
RX FIFO overflow flag clear
0
1
write-only
No effect
No effect
0
Clear
Clear RXOVF flag
1
RXTOIC
RX time-out interrupt flag clear
1
2
write-only
No effect
No effect
0
Clear
Clear RXTO flag
1
TXFIFOTHIC
TX Interrupt flag Clear
3
4
write-only
No effect
No effect
0
Clear
Clear TXFIFOTH flag
1
IE
Offset:0x10 SPI1 Interrupt Enable Register
0x10
32
read-write
n
0x0
0x0
RXFIFOTHIE
RX FIFO threshold interrupt enable
2
3
read-write
Disable
Disable RX FIFO threshold interrupt
0
Enable
Enable RX FIFO threshold interrupt
1
RXOVFIE
RX FIFO overflow interrupt enable
0
1
read-write
Disable
Disable RX FIFO overflow interrupt
0
Enable
Enable RX FIFO overflow interrupt
1
RXTOIE
RX time-out interrupt enable
1
2
read-write
Disable
Disable RX time-out interrupt
0
Enable
Enable RX time-out interrupt
1
TXFIFOTHIE
TX FIFO threshold interrupt enable
3
4
read-write
Disable
Disable TX FIFO threshold interrupt
0
Enable
Enable TX FIFO threshold interrupt
1
RIS
Offset:0x14 SPI1 Raw Interrupt Status Register
0x14
32
read-only
n
0x0
0x0
RXFIFOTHIF
RX FIFO threshold interrupt flag
2
3
read-only
No
No RXFIFOTH interrupt
0
Met
RX FIFO threshold is triggered when RXFIFOTHIE=1
1
RXOVFIF
RX FIFO overflow interrupt flag
0
1
read-only
No
No RXOVF interrupt
0
Met
RXOVF interrupt is triggered when RXOVFIE=1
1
RXTOIF
RX time-out interrupt flag
1
2
read-only
No
No RXTO interrupt
0
Met
RXTO interrupt is triggered when RXTOIE=1
1
TXFIFOTHIF
TX FIFO threshold interrupt flag
3
4
read-only
No
No TXFIFOTH interrupt
0
Met
TX FIFO threshold is triggered when TXFIFOTHIE=1
1
STAT
Offset:0x0C SPI1 Status Register
0xC
32
read-only
n
0x0
0x0
BUSY
Busy flag
4
5
read-only
Idle
SSPn is idle
0
Busy
SSPn is transfering
1
RXFIFOTHF
RX FIFO threshold flag
6
7
read-only
0
Data count in RX FIFO is less equal than RXFIFOTH
0
1
Data count in RX FIFO is larger than RXFIFOTH
1
RX_EMPTY
RX FIFO empty flag
2
3
read-only
0
RX FIFO is not empty
0
1
RX FIFO is empty
1
RX_FULL
RX FIFO full flag
3
4
read-only
0
RX FIFO is not full
0
1
RX FIFO is full
1
TXFIFOTHF
TX FIFO threshold flag
5
6
read-only
0
Data count in TX FIFO is larger than TXFIFOTH
0
1
Data count in TX FIFO is less equal than TXFIFOTH
1
TX_EMPTY
TX FIFO empty flag
0
1
read-only
0
TX FIFO is not empty
0
1
TX FIFO is empty
1
TX_FULL
TX FIFO full flag
1
2
read-only
0
TX FIFO is not full
0
1
TX FIFO is full
1
SN_SYS0
System Control Registers 0
SYSTEM
0x0
0x0
0x2000
registers
n
NDT
Noise Detection
0
LVD
Low Voltage Detection
26
AHBCP
Offset:0x10 AHB Clock Prescale Register
0x10
32
read-write
n
0x0
0x0
AHBPRE
AHB clock source prescaler
0
3
read-write
000b
FAHB=FSYSCLK/1
0
001b
FAHB=FSYSCLK/2
1
010b
FAHB=FSYSCLK/4
2
011b
FAHB=FSYSCLK/8
3
100b
FAHB=FSYSCLK/16
4
101b
FAHB=FSYSCLK/32
5
110b
FAHB=FSYSCLK/64
6
111b
FAHB=FSYSCLK/128
7
DIV1P5
SYSCLK prescaler
3
4
read-write
DIV1
SYSCLK = SYSCLK/1
0
DIV1P5
SYSCLK = SYSCLK/1.5
1
ANBCTRL
Offset:0x00 Analog Block Control Register
0x0
32
read-write
n
0x0
0x0
EHSEN
EHS XTAL enable
4
5
read-write
Disable
Disable EHS Xtal
0
Enable
Enable EHS Xtal
1
EHSFREQ
EHS XTAL frequency range
5
6
read-write
Low
Less equal than 12MHz
0
High
Greater than 12MHz
1
ELSEN
ELS XTAL enable
2
3
read-write
Disable
Disable ELS Xtal
0
Enable
Enable ELS Xtal
1
IHRCEN
IHRC enable
0
1
read-write
Disable
Disable IHRC
0
Enable
Enable IHRC
1
CLKCFG
Offset:0x0C System Clock Configuration Register
0xC
32
read-write
n
0x0
0x0
SYSCLKSEL
System clock source selection
0
3
read-write
IHRC
HCLK=IHRC
0
ILRC
HCLK=ILRC
1
EHS XTAL
HCLK=EHS XTAL
2
ELS XTAL
HCLK=ELS XTAL
3
PLL Output
HCLK=PLL output
4
SYSCLKST
System clock switch status
4
7
read-only
IHRC
IHRC is used as system clock
0
ILRC
ILRC is used as system clock
1
EHS XTAL
EHS XTAL is used as system clock
2
ELS XTAL
ELS XTAL is used as system clock
3
PLL
PLL output is used as system clock
4
CSST
Offset:0x08 Clock Source Status Register
0x8
32
read-only
n
0x0
0x0
EHSRDY
EHS XTAL ready flag
4
5
read-only
Not Ready
EHS Xtal is Not Ready
0
Ready
EHS Xtal is Ready
1
ELSRDY
ELS XTAL ready flag
2
3
read-only
Not Ready
ELS Xtal is Not Ready
0
Ready
ELS Xtal is Ready
1
IHRCRDY
IHRC ready flag
0
1
read-only
Not Ready
IHRC is Not Ready
0
Ready
IHRC is Ready
1
PLLRDY
PLL ready flag
6
7
read-only
Not Locked
PLL is Not locked
0
Locked
PLL is locked
1
EXRSTCTRL
Offset:0x1C External Reset Pin Control Register
0x1C
32
read-write
n
0x0
0x0
RESETDIS
External reset pin disable
0
1
read-write
Enable
P3.7 acts as nRESET pin
0
Disable
P3.7 acts as GPIO pin
1
IHRCADJ
Offset:0x34 IHRC Frequency Adjustment register
0x34
32
read-write
n
0x0
0x0
ADJ
IHRC frequency adjusting bits
4
12
read-write
ADJEN
IHRC frequency adjustment enable bit
0
1
read-write
Disable
Disable IHRC frequency adjustment
0
Enable
Enable IHRC frequency adjustment
1
DIR
IHRC frequency adjusting direction bit
1
2
read-write
Positive
Positive direction
0
Negative
Negative direction
1
SYSKEY
System register key
16
32
write-only
IVTM
Offset:0x24 Interrupt Vector Table Mapping register
0x24
32
read-write
n
0x0
0x0
IVTM
Interrupt table mapping selection
0
3
read-write
000b
Map to Boot ROM
0
001b
Map to User ROM 1
1
010b
Map to SRAM
2
011b
Map to User ROM 2
3
100b
Map to User ROM 3
4
101b
Map to User ROM 4
5
IVTMKEY
IVTM register key
16
32
write-only
LVDCTRL
Offset:0x18 LVD Control Register
0x18
32
read-write
n
0x0
0x0
LVDEN
LVD enable
15
16
read-write
Diable
Disable LVD
0
Enable
Enable LVD
0
Disable
Disable LVD
1
LVDINTLVL
LVD interrupt level
4
7
read-write
Reserved
Reserved
3
2.70V
LVD interrupt threshold is 2.70V
4
3.00V
LVD interrupt threshold is 3.00V
4
3.60V
LVD interrupt threshold is 3.60V
5
LVDRSTEN
LVD Reset enable
14
15
read-write
Diable
Disable LVD reset
0
Enable
Enable LVD reset
0
Disable
Disable LVD reset
1
LVDRSTLVL
LVD reset level
0
3
read-write
Reserved
Reserved
3
2.70V
LVD reset threshold is 2.70V
4
3.00V
LVD reset threshold is 3.00V
4
3.60V
LVD reset threshold is 3.60V
5
NDTCTRL
Offset:0x28 Noise Detect Control Register
0x28
32
read-write
n
0x0
0x0
NDT5V_IE
NDT for VDD 5V interrupt enable bit
1
2
read-write
Disable
Disable NDT5V interrupt
0
Enable
Enable NDT5V interrupt
1
NDTSTS
Offset:0x2C Noise Detect Status Register
0x2C
32
read-write
n
0x0
0x0
NDT5V_DET
Power noise status of NDT5V
1
2
read-write
No
No power noise is detected
0
Detected
Power noise is detected by NDT5V IP
1
PLLCTRL
Offset:0x04 PLL Control Register
0x4
32
read-write
n
0x0
0x0
MSEL
M value
0
3
read-write
000b
M=4
0
001b
M=6
1
010b
M=8
2
011b
M=10
3
100b
M=12
4
PLLCLKSEL
PLL clock source
12
13
read-write
IHRC
12MHz
0
EHS XTAL
10MHz~25MHz
1
PLLEN
PLL enable
15
16
read-write
Disable
Disable PLL
0
Enable
Enable PLL
1
PSEL
P value
5
6
read-write
2
P=2
0
4
P=4
1
RSTST
Offset:0x14 System Reset Status Register
0x14
32
read-write
n
0x0
0x0
EXTRSTF
External reset flag
3
4
read-write
0
No Extenral reset occurred
0
1
External reset occurred
1
LVDRSTF
LVD reset flag
2
3
read-write
0
No LVD reset occurred
0
1
LVD reset occurred
1
PORRSTF
POR reset flag
4
5
read-write
0
No POR occurred
0
1
POR occurred
1
SWRSTF
Software reset flag
0
1
read-write
0
No SW reset occurred
0
1
SW reset occurred
1
WDTRSTF
WDT reset flag
1
2
read-write
0
No WDT reset occurred
0
1
WDT reset occurred
1
SWDCTRL
Offset:0x20 SWD Pin Control Register
0x20
32
read-write
n
0x0
0x0
SWDDIS
SWD pin disable
0
1
read-write
Enable
Enable SWD pins
0
Disable
Disable SWD pins
1
SN_SYS1
System Control Registers 1
SYSTEM
0x0
0x0
0x2000
registers
n
AHBCLKEN
Offset:0x00 AHB Clock Enable Register
0x0
32
read-write
n
0x0
0x0
ADCCLKEN
Enable AHB clock for ADC
11
12
read-write
Disable
Disable
0
Enable
Enable
1
CLKOUTSEL
Clock output source selection
28
31
read-write
000b
Disable
0
001b
ILRC
1
010b
ELS XTAL
2
011b
CS Clockout selected by SGSEL[1:0] bits
3
100b
HCLK
4
101b
IHRC
5
110b
EHS XTAL
6
111b
PLL output
7
CMPCLKEN
Enable AHB clock for CMP
14
15
read-write
Disable
Disable
0
Enable
Enable
1
CRCCLKEN
Enable AHB clock for CRC
27
28
read-write
Disable
Disable
0
Enable
Enable
1
CT16B0CLKEN
Enable AHB clock for CT16B0
5
6
read-write
Disable
Disable
0
Enable
Enable
1
CT16B1CLKEN
Enable AHB clock for CT16B1
6
7
read-write
Disable
Disable
0
Enable
Enable
1
CT16B2CLKEN
Enable AHB clock for CT16B2
7
8
read-write
Disable
Disable
0
Enable
Enable
1
CT16B3CLKEN
Enable AHB clock for CT16B3
8
9
read-write
Disable
Disable
0
Enable
Enable
1
CT16B4CLKEN
Enable AHB clock for CT16B4
9
10
read-write
Disable
Disable
0
Enable
Enable
1
CT16B5CLKEN
Enable AHB clock for CT16B5
10
11
read-write
Disable
Disable
0
Enable
Enable
1
EBICLKEN
Enable AHB clock for EBI
15
16
read-write
Disable
Disable
0
Enable
Enable
1
I2C0CLKEN
Enable AHB clock for I2C0
21
22
read-write
Disable
Disable
0
Enable
Enable
1
I2C1CLKEN
Enable AHB clock for I2C1
20
21
read-write
Disable
Disable
0
Enable
Enable
1
I2S0CLKEN
Enable AHB clock for I2S0
22
23
read-write
Disable
Disable
0
Enable
Enable
1
I2S1CLKEN
Enable AHB clock for I2S1
25
26
read-write
Disable
Disable
0
Enable
Enable
1
LCDCLKEN
Enable AHB clock for LCD
26
27
read-write
Disable
Disable
0
Enable
Enable
1
OPACLKEN
Enable AHB clock for OPA
3
4
read-write
Disable
Disable
0
Enable
Enable
1
RTCCLKEN
Enable AHB clock for RTC
23
24
read-write
Disable
Disable
0
Enable
Enable
1
SPI0CLKEN
Enable AHB clock for SPI0
12
13
read-write
Disable
Disable
0
Enable
Enable
1
SPI1CLKEN
Enable AHB clock for SPI1
13
14
read-write
Disable
Disable
0
Enable
Enable
1
UART0CLKEN
Enable AHB clock for UART0
16
17
read-write
Disable
Disable
0
Enable
Enable
1
UART1CLKEN
Enable AHB clock for UART1
17
18
read-write
Disable
Disable
0
Enable
Enable
1
UART2CLKEN
Enable AHB clock for UART2
18
19
read-write
Disable
Disable
0
Enable
Enable
1
UART3CLKEN
Enable AHB clock for UART3
19
20
read-write
Disable
Disable
0
Enable
Enable
1
USBCLKEN
Enable AHB clock for USB
4
5
read-write
Disable
Disable
0
Enable
Enable
1
WDTCLKEN
Enable AHB clock for WDT
24
25
read-write
Disable
Disable
0
Enable
Enable
1
APBCP0
Offset:0x04 APB Clock Prescale Register 0
0x4
32
read-write
n
0x0
0x0
ADCPRE
ADC APB clock source prescaler
16
19
read-write
000b
HCLK/1
0
001b
HCLK/2
1
010b
HCLK/4
2
011b
HCLK/8
3
100b
HCLK/16
4
APBCP1
Offset:0x08 APB Clock Prescale Register 1
0x8
32
read-write
n
0x0
0x0
CLKOUTPRE
CLKOUT APB clock source prescaler
28
31
read-write
000b
FCLKOUT/1
0
001b
FCLKOUT/2
1
010b
FCLKOUT/4
2
011b
FCLKOUT/8
3
100b
FCLKOUT/16
4
101b
FCLKOUT/32
5
110b
FCLKOUT/64
6
111b
FCLKOUT/128
7
I2C0PRE
I2C0 APB clock source prescaler
8
11
write-only
000b
HCLK/1
0
001b
HCLK/2
1
010b
HCLK/4
2
011b
HCLK/8
3
100b
HCLK/16
4
I2C1PRE
I2C1 APB clock source prescaler
24
27
write-only
000b
HCLK/1
0
001b
HCLK/2
1
010b
HCLK/4
2
011b
HCLK/8
3
100b
HCLK/16
4
I2S0PRE
I2S0 APB clock source prescaler
12
15
read-write
000b
HCLK/1
0
001b
HCLK/2
1
010b
HCLK/4
2
011b
HCLK/8
3
100b
HCLK/16
4
111b
HCLK/3
7
I2S1PRE
I2S1 APB clock source prescaler
15
18
read-write
000b
HCLK/1
0
001b
HCLK/2
1
010b
HCLK/4
2
011b
HCLK/8
3
100b
HCLK/16
4
111b
HCLK/3
7
WDTPRE
WDT APB clock source prescaler
20
23
read-write
000b
WDT_PCLK = WDT clock source / 1
0
001b
WDT_PCLK = WDT clock source / 2
1
010b
WDT_PCLK = WDT clock source / 4
2
011b
WDT_PCLK = WDT clock source / 8
3
100b
WDT_PCLK = WDT clock source / 16
4
101b
WDT_PCLK = WDT clock source / 32
5
PRST
Offset:0x10 Peripheral Reset Register
0x10
32
read-write
n
0x0
0x0
ADCRST
ADC Reset
11
12
read-write
0
No effect
0
1
Reset ADC
1
CMPRST
CMP Reset
14
15
read-write
0
No effect
0
1
Reset CMP
1
CRCRST
CRC Reset
26
27
read-write
0
No effect
0
1
Reset CRC
1
CT16B0RST
CT16B0 Reset
5
6
read-write
0
No effect
0
1
Reset CT16B0
1
CT16B1RST
CT16B1 Reset
6
7
read-write
0
No effect
0
1
Reset CT16B1
1
CT16B2RST
CT16B2 Reset
7
8
read-write
0
No effect
0
1
Reset CT16B2
1
CT16B3RST
CT16B3 Reset
8
9
read-write
0
No effect
0
1
Reset CT16B3
1
CT16B4RST
CT16B4 Reset
9
10
read-write
0
No effect
0
1
Reset CT16B4
1
CT16B5RST
CT16B5 Reset
10
11
read-write
0
No effect
0
1
Reset CT16B5
1
EBIRST
EBI Reset
4
5
read-write
0
No effect
0
1
Reset GPIO3
1
GPIO0RST
GPIO0 Reset
0
1
read-write
0
No effect
0
1
Reset GPIO0
1
GPIO1RST
GPIO1 Reset
1
2
read-write
0
No effect
0
1
Reset GPIO1
1
GPIO2RST
GPIO2 Reset
2
3
read-write
0
No effect
0
1
Reset GPIO2
1
GPIO3RST
GPIO3 Reset
3
4
read-write
0
No effect
0
1
Reset GPIO3
1
I2C0RST
I2C0 Reset
21
22
read-write
0
No effect
0
1
Reset I2C0
1
I2C1RST
I2C1 Reset
20
21
read-write
0
No effect
0
1
Reset I2C1
1
I2S0RST
I2S0 Reset
22
23
read-write
0
No effect
0
1
Reset I2S0
1
I2S1RST
I2S1 Reset
25
26
read-write
0
No effect
0
1
Reset I2S1
1
LCDRST
LCD Reset
15
16
read-write
0
No effect
0
1
Reset LCD
1
OPARST
USB Reset
28
29
read-write
0
No effect
0
1
Reset OPA
1
RTCRST
RTC Reset
23
24
read-write
0
No effect
0
1
Reset RTC
1
SPI0RST
SPI0 Reset
12
13
read-write
0
No effect
0
1
Reset SPI0
1
SPI1RST
SPI1 Reset
13
14
read-write
0
No effect
0
1
Reset SPI1
1
UART0RST
UART0 Reset
16
17
read-write
0
No effect
0
1
Reset UART0
1
UART1RST
UART1 Reset
17
18
read-write
0
No effect
0
1
Reset UART1
1
UART2RST
UART2 Reset
18
19
read-write
0
No effect
0
1
Reset UART2
1
UART3RST
UART1 Reset
19
20
read-write
0
No effect
0
1
Reset UART3
1
USBRST
USB Reset
27
28
read-write
0
No effect
0
1
Reset USB
1
WDTRST
WDT Reset
24
25
read-write
0
No effect
0
1
Reset WDT
1
SN_UART0
UART0
UART
0x0
0x0
0x2000
registers
n
UART0
UART0
13
ABCTRL
Offset:0x20 UARTn Auto-baud Control Register
0x20
32
read-write
n
0x0
0x0
ABEOIFC
Clear ABEOIF flag
8
9
write-only
No effect
No effect
0
Clear
Clear ABEOIF bit
1
ABTOIFC
Clear ABTOIF flag
9
10
write-only
No effect
No effect
0
Clear
Clear ABTOIF bit
1
AUTORESTART
Restart mode selection
2
3
read-write
No restart
No restart
0
Restart
Auto restart in case of timeout
1
MODE
Auto-baud mode selection
1
2
read-write
Mode 0
Auto-baud mode 0
0
Mode 1
Auto-baud mode 1
1
START
Auto-baud run bit
0
1
read-write
Stop
Auto-baud is not running
0
Start
Auto-baud ids running
1
CTRL
Offset:0x30 UARTn Control Register
0x30
32
read-write
n
0x0
0x0
MODE
UART mode
1
4
read-write
0
UART mode
0
RXEN
RX enable
6
7
read-write
Disable
Disable RX
0
Enable
Enable RX
1
TXEN
TX enable
7
8
read-write
Disable
Disable TX
0
Enable
Enable TX
1
UARTEN
USART enable
0
1
read-write
Disable
Disable UART
0
Enable
Enable UART
1
DLL
Offset:0x00 UARTn Divisor Latch LSB Register
RB
0x0
32
read-write
n
0x0
0x0
DLL
DLL and DLM register determines the baud rate of UARTn
0
8
read-write
DLM
Offset:0x04 UARTn Divisor Latch MSB Register
0x4
32
read-write
n
0x0
0x0
DLM
DLL and DLM register determines the baud rate of USARTn
0
8
read-write
FD
Offset:0x28 UARTn Fractional Divider Register
0x28
32
read-write
n
0x0
0x0
DIVADDVAL
Baud rate generation prescaler divisor value
0
4
read-write
MULVAL
Baud rate generation prescaler multiplier value
4
8
read-write
0000
Baud rate prescaler multiplier value is 1
0
0001
Baud rate prescaler multiplier value is 2
1
1010
Baud rate prescaler multiplier value is 11
10
1011
Baud rate prescaler multiplier value is 12
11
1100
Baud rate prescaler multiplier value is 13
12
1101
Baud rate prescaler multiplier value is 14
13
1110
Baud rate prescaler multiplier value is 15
14
1111
Baud rate prescaler multiplier value is 16
15
0010
Baud rate prescaler multiplier value is 3
2
0011
Baud rate prescaler multiplier value is 4
3
0100
Baud rate prescaler multiplier value is 5
4
0101
Baud rate prescaler multiplier value is 6
5
0110
Baud rate prescaler multiplier value is 7
6
0111
Baud rate prescaler multiplier value is 8
7
1000
Baud rate prescaler multiplier value is 9
8
1001
Baud rate prescaler multiplier value is 10
9
OVER8
Oversampling value
8
9
read-write
16
Oversampling by 16
0
8
Oversampling by 8
1
FIFOCTRL
Offset:0x08 UARTn FIFO Control Register
0x8
32
write-only
n
0x0
0x0
FIFOEN
FIFO enable
0
1
write-only
No effect
No effect
0
Enable
Enable FIFO
1
RXTL
RX trigger level
6
8
write-only
Trigger level 0
1 character
0
HDEN
Offset:0x34 UARTn Control Register
0x34
32
read-write
n
0x0
0x0
HDEN
Half-duplex mode enable
0
1
read-write
Disable
Disable half-duplex mode
0
Enable
Enable half-duplex mode
1
IE
Offset:0x04 UARTn Interrupt Enable Register
DLM
0x4
32
read-write
n
0x0
0x0
ABEOIE
ABE0 interrupt enable
8
9
read-write
Disable
Disable ABEO interrupt
0
Enable
Enable ABEO interrupt
1
ABTOIE
ABT0 interrupt enable
9
10
read-write
Disable
Disable ABTO interrupt
0
Enable
Enable ABTO interrupt
1
RDAIE
RDA interrupt enable
0
1
read-write
Disable
Disable RDA interrupt
0
Enable
Enable RDA interrupt
1
RLSIE
RLS interrupt enable
2
3
read-write
Disable
Disable RLS interrupt
0
Enable
Enable RLS interrupt
1
TEMTIE
TEMT interrupt enable
4
5
read-write
Disable
Disable TEMT interrupt
0
Enable
Enable TEMT interrupt
1
THREIE
THRE interrupt enable
1
2
read-write
Disable
Disable THRE interrupt
0
Enable
Enable THRE interrupt
1
II
Offset:0x08 UARTn Interrupt Identification Register
0x8
32
read-only
n
0x0
0x0
ABEOIF
ABEO interrupt flag
8
9
read-only
Not end
Auto-baud has not finished
0
End
Auto-baud has finished and interrupt is enabled
1
ABTOIF
ABTO interrupt flag
9
10
read-only
Not Time-out
Auto-baud has not timed out
0
Time-out
Auto-baud has timed out and interrupt is enabled
1
FIFOEN
Equal to FIFOEN bits in USARTn_FIFOCTRL register
6
8
read-only
INTID
Interrupt ID of RX FIFO
1
4
read-only
3a
THRE interrupt
1
2a
RDA (Receive Data Available)
2
1
RLS (Receive Line Status)
3
3b
TEMT interrupt
7
INTSTATUS
Interrupt status
0
1
read-only
Pending
As least 1 interrupt is pending
0
No interrupt
No interrupt
1
LC
Offset:0x0C UARTn Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
Break control
6
7
read-write
Disable
Disable break transmission
0
Enable
Enable break transmission
1
DLAB
Divisor Latch access
7
8
read-write
Disable
Disable access to Divisor Latch
0
Enable
Enable access to Divisor Latch
1
PE
Parity enable
3
4
read-write
Disable
Disable parity generation and checking
0
Enable
Enable parity generation and checking
1
PS
Parity selection
4
6
read-write
0
Odd parity
0
1
Even parity
1
2
Forced 1 sticky parity
2
3
Forced 0 sticky parity
3
SBS
Stop bit selection
2
3
read-write
1 stop bit
1 stop bit
0
2 stop bit
2 stop bit (1.5 stop bit if WLS=0)
1
WLS
Word length selection
0
2
read-write
5-bit
5-bit character
0
6-bit
6-bit character
1
7-bit
7-bit character
2
8-bit
8-bit character
3
LS
Offset:0x14 UARTn Line Status Register
0x14
32
read-only
n
0x0
0x0
BI
Break interrupt flag
4
5
read-only
No
No break interrupt
0
Break interrupt
Break interrupt status is active
1
FE
Framing error flag
3
4
read-only
No
No framing error
0
Framing error
Framing error status is active
1
OE
Overrun error flag
1
2
read-only
No
No overrun error
0
Overrun error
Overrun error status is active
1
PE
Parity error flag
2
3
read-only
No
No parity error
0
Parity error
Parity error status is active
1
RDR
Receiver data ready flag
0
1
read-only
Not ready
UARTn_RB FIFO is empty
0
Ready
UARTn_RB FIFO contains valid data
1
RXFE
Receiver FIFO error flag
7
8
read-only
No RX FIFO error
UARTn_RB contains no UART RX errors
0
RX FIFO error
UARTn_RB contains at least 1 UART RX error
1
TEMT
Transmitter empty flag
6
7
read-only
Not empty
THR and/or TSR contains valid data
0
Empty
THR and TSR are both empty
1
THRE
THR empty flag
5
6
read-only
Not empty
THR contains valid data
0
Empty
THR (TX FIFO) is empty
1
RB
Offset:0x00 UARTn Receiver Buffer Register
0x0
32
read-only
n
0x0
0x0
RB
The received byte in UART RX FIFO
0
8
read-only
SP
Offset:0x1C UARTn Scratch Pad Register
0x1C
32
read-write
n
0x0
0x0
PAD
Pad informaton
0
8
read-write
TH
Offset:0x00 UARTn Transmit Holding Register
RB
0x0
32
write-only
n
0x0
0x0
TH
The byte to be transmitted in UART TX FIFO when transmitter is available
0
8
write-only
SN_UART1
UART0
UART
0x0
0x0
0x2000
registers
n
UART1
UART1
14
ABCTRL
Offset:0x20 UARTn Auto-baud Control Register
0x20
32
read-write
n
0x0
0x0
ABEOIFC
Clear ABEOIF flag
8
9
write-only
No effect
No effect
0
Clear
Clear ABEOIF bit
1
ABTOIFC
Clear ABTOIF flag
9
10
write-only
No effect
No effect
0
Clear
Clear ABTOIF bit
1
AUTORESTART
Restart mode selection
2
3
read-write
No restart
No restart
0
Restart
Auto restart in case of timeout
1
MODE
Auto-baud mode selection
1
2
read-write
Mode 0
Auto-baud mode 0
0
Mode 1
Auto-baud mode 1
1
START
Auto-baud run bit
0
1
read-write
Stop
Auto-baud is not running
0
Start
Auto-baud ids running
1
CTRL
Offset:0x30 UARTn Control Register
0x30
32
read-write
n
0x0
0x0
MODE
UART mode
1
4
read-write
0
UART mode
0
RXEN
RX enable
6
7
read-write
Disable
Disable RX
0
Enable
Enable RX
1
TXEN
TX enable
7
8
read-write
Disable
Disable TX
0
Enable
Enable TX
1
UARTEN
USART enable
0
1
read-write
Disable
Disable UART
0
Enable
Enable UART
1
DLL
Offset:0x00 UARTn Divisor Latch LSB Register
RB
0x0
32
read-write
n
0x0
0x0
DLL
DLL and DLM register determines the baud rate of UARTn
0
8
read-write
DLM
Offset:0x04 UARTn Divisor Latch MSB Register
0x4
32
read-write
n
0x0
0x0
DLM
DLL and DLM register determines the baud rate of USARTn
0
8
read-write
FD
Offset:0x28 UARTn Fractional Divider Register
0x28
32
read-write
n
0x0
0x0
DIVADDVAL
Baud rate generation prescaler divisor value
0
4
read-write
MULVAL
Baud rate generation prescaler multiplier value
4
8
read-write
0000
Baud rate prescaler multiplier value is 1
0
0001
Baud rate prescaler multiplier value is 2
1
1010
Baud rate prescaler multiplier value is 11
10
1011
Baud rate prescaler multiplier value is 12
11
1100
Baud rate prescaler multiplier value is 13
12
1101
Baud rate prescaler multiplier value is 14
13
1110
Baud rate prescaler multiplier value is 15
14
1111
Baud rate prescaler multiplier value is 16
15
0010
Baud rate prescaler multiplier value is 3
2
0011
Baud rate prescaler multiplier value is 4
3
0100
Baud rate prescaler multiplier value is 5
4
0101
Baud rate prescaler multiplier value is 6
5
0110
Baud rate prescaler multiplier value is 7
6
0111
Baud rate prescaler multiplier value is 8
7
1000
Baud rate prescaler multiplier value is 9
8
1001
Baud rate prescaler multiplier value is 10
9
OVER8
Oversampling value
8
9
read-write
16
Oversampling by 16
0
8
Oversampling by 8
1
FIFOCTRL
Offset:0x08 UARTn FIFO Control Register
0x8
32
write-only
n
0x0
0x0
FIFOEN
FIFO enable
0
1
write-only
No effect
No effect
0
Enable
Enable FIFO
1
RXTL
RX trigger level
6
8
write-only
Trigger level 0
1 character
0
HDEN
Offset:0x34 UARTn Control Register
0x34
32
read-write
n
0x0
0x0
HDEN
Half-duplex mode enable
0
1
read-write
Disable
Disable half-duplex mode
0
Enable
Enable half-duplex mode
1
IE
Offset:0x04 UARTn Interrupt Enable Register
DLM
0x4
32
read-write
n
0x0
0x0
ABEOIE
ABE0 interrupt enable
8
9
read-write
Disable
Disable ABEO interrupt
0
Enable
Enable ABEO interrupt
1
ABTOIE
ABT0 interrupt enable
9
10
read-write
Disable
Disable ABTO interrupt
0
Enable
Enable ABTO interrupt
1
RDAIE
RDA interrupt enable
0
1
read-write
Disable
Disable RDA interrupt
0
Enable
Enable RDA interrupt
1
RLSIE
RLS interrupt enable
2
3
read-write
Disable
Disable RLS interrupt
0
Enable
Enable RLS interrupt
1
TEMTIE
TEMT interrupt enable
4
5
read-write
Disable
Disable TEMT interrupt
0
Enable
Enable TEMT interrupt
1
THREIE
THRE interrupt enable
1
2
read-write
Disable
Disable THRE interrupt
0
Enable
Enable THRE interrupt
1
II
Offset:0x08 UARTn Interrupt Identification Register
0x8
32
read-only
n
0x0
0x0
ABEOIF
ABEO interrupt flag
8
9
read-only
Not end
Auto-baud has not finished
0
End
Auto-baud has finished and interrupt is enabled
1
ABTOIF
ABTO interrupt flag
9
10
read-only
Not Time-out
Auto-baud has not timed out
0
Time-out
Auto-baud has timed out and interrupt is enabled
1
FIFOEN
Equal to FIFOEN bits in USARTn_FIFOCTRL register
6
8
read-only
INTID
Interrupt ID of RX FIFO
1
4
read-only
3a
THRE interrupt
1
2a
RDA (Receive Data Available)
2
1
RLS (Receive Line Status)
3
3b
TEMT interrupt
7
INTSTATUS
Interrupt status
0
1
read-only
Pending
As least 1 interrupt is pending
0
No interrupt
No interrupt
1
LC
Offset:0x0C UARTn Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
Break control
6
7
read-write
Disable
Disable break transmission
0
Enable
Enable break transmission
1
DLAB
Divisor Latch access
7
8
read-write
Disable
Disable access to Divisor Latch
0
Enable
Enable access to Divisor Latch
1
PE
Parity enable
3
4
read-write
Disable
Disable parity generation and checking
0
Enable
Enable parity generation and checking
1
PS
Parity selection
4
6
read-write
0
Odd parity
0
1
Even parity
1
2
Forced 1 sticky parity
2
3
Forced 0 sticky parity
3
SBS
Stop bit selection
2
3
read-write
1 stop bit
1 stop bit
0
2 stop bit
2 stop bit (1.5 stop bit if WLS=0)
1
WLS
Word length selection
0
2
read-write
5-bit
5-bit character
0
6-bit
6-bit character
1
7-bit
7-bit character
2
8-bit
8-bit character
3
LS
Offset:0x14 UARTn Line Status Register
0x14
32
read-only
n
0x0
0x0
BI
Break interrupt flag
4
5
read-only
No
No break interrupt
0
Break interrupt
Break interrupt status is active
1
FE
Framing error flag
3
4
read-only
No
No framing error
0
Framing error
Framing error status is active
1
OE
Overrun error flag
1
2
read-only
No
No overrun error
0
Overrun error
Overrun error status is active
1
PE
Parity error flag
2
3
read-only
No
No parity error
0
Parity error
Parity error status is active
1
RDR
Receiver data ready flag
0
1
read-only
Not ready
UARTn_RB FIFO is empty
0
Ready
UARTn_RB FIFO contains valid data
1
RXFE
Receiver FIFO error flag
7
8
read-only
No RX FIFO error
UARTn_RB contains no UART RX errors
0
RX FIFO error
UARTn_RB contains at least 1 UART RX error
1
TEMT
Transmitter empty flag
6
7
read-only
Not empty
THR and/or TSR contains valid data
0
Empty
THR and TSR are both empty
1
THRE
THR empty flag
5
6
read-only
Not empty
THR contains valid data
0
Empty
THR (TX FIFO) is empty
1
RB
Offset:0x00 UARTn Receiver Buffer Register
0x0
32
read-only
n
0x0
0x0
RB
The received byte in UART RX FIFO
0
8
read-only
SP
Offset:0x1C UARTn Scratch Pad Register
0x1C
32
read-write
n
0x0
0x0
PAD
Pad informaton
0
8
read-write
TH
Offset:0x00 UARTn Transmit Holding Register
RB
0x0
32
write-only
n
0x0
0x0
TH
The byte to be transmitted in UART TX FIFO when transmitter is available
0
8
write-only
SN_UART2
UART0
UART
0x0
0x0
0x2000
registers
n
UART2
UART2
8
ABCTRL
Offset:0x20 UARTn Auto-baud Control Register
0x20
32
read-write
n
0x0
0x0
ABEOIFC
Clear ABEOIF flag
8
9
write-only
No effect
No effect
0
Clear
Clear ABEOIF bit
1
ABTOIFC
Clear ABTOIF flag
9
10
write-only
No effect
No effect
0
Clear
Clear ABTOIF bit
1
AUTORESTART
Restart mode selection
2
3
read-write
No restart
No restart
0
Restart
Auto restart in case of timeout
1
MODE
Auto-baud mode selection
1
2
read-write
Mode 0
Auto-baud mode 0
0
Mode 1
Auto-baud mode 1
1
START
Auto-baud run bit
0
1
read-write
Stop
Auto-baud is not running
0
Start
Auto-baud ids running
1
CTRL
Offset:0x30 UARTn Control Register
0x30
32
read-write
n
0x0
0x0
MODE
UART mode
1
4
read-write
0
UART mode
0
RXEN
RX enable
6
7
read-write
Disable
Disable RX
0
Enable
Enable RX
1
TXEN
TX enable
7
8
read-write
Disable
Disable TX
0
Enable
Enable TX
1
UARTEN
USART enable
0
1
read-write
Disable
Disable UART
0
Enable
Enable UART
1
DLL
Offset:0x00 UARTn Divisor Latch LSB Register
RB
0x0
32
read-write
n
0x0
0x0
DLL
DLL and DLM register determines the baud rate of UARTn
0
8
read-write
DLM
Offset:0x04 UARTn Divisor Latch MSB Register
0x4
32
read-write
n
0x0
0x0
DLM
DLL and DLM register determines the baud rate of USARTn
0
8
read-write
FD
Offset:0x28 UARTn Fractional Divider Register
0x28
32
read-write
n
0x0
0x0
DIVADDVAL
Baud rate generation prescaler divisor value
0
4
read-write
MULVAL
Baud rate generation prescaler multiplier value
4
8
read-write
0000
Baud rate prescaler multiplier value is 1
0
0001
Baud rate prescaler multiplier value is 2
1
1010
Baud rate prescaler multiplier value is 11
10
1011
Baud rate prescaler multiplier value is 12
11
1100
Baud rate prescaler multiplier value is 13
12
1101
Baud rate prescaler multiplier value is 14
13
1110
Baud rate prescaler multiplier value is 15
14
1111
Baud rate prescaler multiplier value is 16
15
0010
Baud rate prescaler multiplier value is 3
2
0011
Baud rate prescaler multiplier value is 4
3
0100
Baud rate prescaler multiplier value is 5
4
0101
Baud rate prescaler multiplier value is 6
5
0110
Baud rate prescaler multiplier value is 7
6
0111
Baud rate prescaler multiplier value is 8
7
1000
Baud rate prescaler multiplier value is 9
8
1001
Baud rate prescaler multiplier value is 10
9
OVER8
Oversampling value
8
9
read-write
16
Oversampling by 16
0
8
Oversampling by 8
1
FIFOCTRL
Offset:0x08 UARTn FIFO Control Register
0x8
32
write-only
n
0x0
0x0
FIFOEN
FIFO enable
0
1
write-only
No effect
No effect
0
Enable
Enable FIFO
1
RXTL
RX trigger level
6
8
write-only
Trigger level 0
1 character
0
HDEN
Offset:0x34 UARTn Control Register
0x34
32
read-write
n
0x0
0x0
HDEN
Half-duplex mode enable
0
1
read-write
Disable
Disable half-duplex mode
0
Enable
Enable half-duplex mode
1
IE
Offset:0x04 UARTn Interrupt Enable Register
DLM
0x4
32
read-write
n
0x0
0x0
ABEOIE
ABE0 interrupt enable
8
9
read-write
Disable
Disable ABEO interrupt
0
Enable
Enable ABEO interrupt
1
ABTOIE
ABT0 interrupt enable
9
10
read-write
Disable
Disable ABTO interrupt
0
Enable
Enable ABTO interrupt
1
RDAIE
RDA interrupt enable
0
1
read-write
Disable
Disable RDA interrupt
0
Enable
Enable RDA interrupt
1
RLSIE
RLS interrupt enable
2
3
read-write
Disable
Disable RLS interrupt
0
Enable
Enable RLS interrupt
1
TEMTIE
TEMT interrupt enable
4
5
read-write
Disable
Disable TEMT interrupt
0
Enable
Enable TEMT interrupt
1
THREIE
THRE interrupt enable
1
2
read-write
Disable
Disable THRE interrupt
0
Enable
Enable THRE interrupt
1
II
Offset:0x08 UARTn Interrupt Identification Register
0x8
32
read-only
n
0x0
0x0
ABEOIF
ABEO interrupt flag
8
9
read-only
Not end
Auto-baud has not finished
0
End
Auto-baud has finished and interrupt is enabled
1
ABTOIF
ABTO interrupt flag
9
10
read-only
Not Time-out
Auto-baud has not timed out
0
Time-out
Auto-baud has timed out and interrupt is enabled
1
FIFOEN
Equal to FIFOEN bits in USARTn_FIFOCTRL register
6
8
read-only
INTID
Interrupt ID of RX FIFO
1
4
read-only
3a
THRE interrupt
1
2a
RDA (Receive Data Available)
2
1
RLS (Receive Line Status)
3
3b
TEMT interrupt
7
INTSTATUS
Interrupt status
0
1
read-only
Pending
As least 1 interrupt is pending
0
No interrupt
No interrupt
1
LC
Offset:0x0C UARTn Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
Break control
6
7
read-write
Disable
Disable break transmission
0
Enable
Enable break transmission
1
DLAB
Divisor Latch access
7
8
read-write
Disable
Disable access to Divisor Latch
0
Enable
Enable access to Divisor Latch
1
PE
Parity enable
3
4
read-write
Disable
Disable parity generation and checking
0
Enable
Enable parity generation and checking
1
PS
Parity selection
4
6
read-write
0
Odd parity
0
1
Even parity
1
2
Forced 1 sticky parity
2
3
Forced 0 sticky parity
3
SBS
Stop bit selection
2
3
read-write
1 stop bit
1 stop bit
0
2 stop bit
2 stop bit (1.5 stop bit if WLS=0)
1
WLS
Word length selection
0
2
read-write
5-bit
5-bit character
0
6-bit
6-bit character
1
7-bit
7-bit character
2
8-bit
8-bit character
3
LS
Offset:0x14 UARTn Line Status Register
0x14
32
read-only
n
0x0
0x0
BI
Break interrupt flag
4
5
read-only
No
No break interrupt
0
Break interrupt
Break interrupt status is active
1
FE
Framing error flag
3
4
read-only
No
No framing error
0
Framing error
Framing error status is active
1
OE
Overrun error flag
1
2
read-only
No
No overrun error
0
Overrun error
Overrun error status is active
1
PE
Parity error flag
2
3
read-only
No
No parity error
0
Parity error
Parity error status is active
1
RDR
Receiver data ready flag
0
1
read-only
Not ready
UARTn_RB FIFO is empty
0
Ready
UARTn_RB FIFO contains valid data
1
RXFE
Receiver FIFO error flag
7
8
read-only
No RX FIFO error
UARTn_RB contains no UART RX errors
0
RX FIFO error
UARTn_RB contains at least 1 UART RX error
1
TEMT
Transmitter empty flag
6
7
read-only
Not empty
THR and/or TSR contains valid data
0
Empty
THR and TSR are both empty
1
THRE
THR empty flag
5
6
read-only
Not empty
THR contains valid data
0
Empty
THR (TX FIFO) is empty
1
RB
Offset:0x00 UARTn Receiver Buffer Register
0x0
32
read-only
n
0x0
0x0
RB
The received byte in UART RX FIFO
0
8
read-only
SP
Offset:0x1C UARTn Scratch Pad Register
0x1C
32
read-write
n
0x0
0x0
PAD
Pad informaton
0
8
read-write
TH
Offset:0x00 UARTn Transmit Holding Register
RB
0x0
32
write-only
n
0x0
0x0
TH
The byte to be transmitted in UART TX FIFO when transmitter is available
0
8
write-only
SN_UART3
UART0
UART
0x0
0x0
0x2000
registers
n
UART3
UART3
9
ABCTRL
Offset:0x20 UARTn Auto-baud Control Register
0x20
32
read-write
n
0x0
0x0
ABEOIFC
Clear ABEOIF flag
8
9
write-only
No effect
No effect
0
Clear
Clear ABEOIF bit
1
ABTOIFC
Clear ABTOIF flag
9
10
write-only
No effect
No effect
0
Clear
Clear ABTOIF bit
1
AUTORESTART
Restart mode selection
2
3
read-write
No restart
No restart
0
Restart
Auto restart in case of timeout
1
MODE
Auto-baud mode selection
1
2
read-write
Mode 0
Auto-baud mode 0
0
Mode 1
Auto-baud mode 1
1
START
Auto-baud run bit
0
1
read-write
Stop
Auto-baud is not running
0
Start
Auto-baud ids running
1
CTRL
Offset:0x30 UARTn Control Register
0x30
32
read-write
n
0x0
0x0
MODE
UART mode
1
4
read-write
0
UART mode
0
RXEN
RX enable
6
7
read-write
Disable
Disable RX
0
Enable
Enable RX
1
TXEN
TX enable
7
8
read-write
Disable
Disable TX
0
Enable
Enable TX
1
UARTEN
USART enable
0
1
read-write
Disable
Disable UART
0
Enable
Enable UART
1
DLL
Offset:0x00 UARTn Divisor Latch LSB Register
RB
0x0
32
read-write
n
0x0
0x0
DLL
DLL and DLM register determines the baud rate of UARTn
0
8
read-write
DLM
Offset:0x04 UARTn Divisor Latch MSB Register
0x4
32
read-write
n
0x0
0x0
DLM
DLL and DLM register determines the baud rate of USARTn
0
8
read-write
FD
Offset:0x28 UARTn Fractional Divider Register
0x28
32
read-write
n
0x0
0x0
DIVADDVAL
Baud rate generation prescaler divisor value
0
4
read-write
MULVAL
Baud rate generation prescaler multiplier value
4
8
read-write
0000
Baud rate prescaler multiplier value is 1
0
0001
Baud rate prescaler multiplier value is 2
1
1010
Baud rate prescaler multiplier value is 11
10
1011
Baud rate prescaler multiplier value is 12
11
1100
Baud rate prescaler multiplier value is 13
12
1101
Baud rate prescaler multiplier value is 14
13
1110
Baud rate prescaler multiplier value is 15
14
1111
Baud rate prescaler multiplier value is 16
15
0010
Baud rate prescaler multiplier value is 3
2
0011
Baud rate prescaler multiplier value is 4
3
0100
Baud rate prescaler multiplier value is 5
4
0101
Baud rate prescaler multiplier value is 6
5
0110
Baud rate prescaler multiplier value is 7
6
0111
Baud rate prescaler multiplier value is 8
7
1000
Baud rate prescaler multiplier value is 9
8
1001
Baud rate prescaler multiplier value is 10
9
OVER8
Oversampling value
8
9
read-write
16
Oversampling by 16
0
8
Oversampling by 8
1
FIFOCTRL
Offset:0x08 UARTn FIFO Control Register
0x8
32
write-only
n
0x0
0x0
FIFOEN
FIFO enable
0
1
write-only
No effect
No effect
0
Enable
Enable FIFO
1
RXTL
RX trigger level
6
8
write-only
Trigger level 0
1 character
0
HDEN
Offset:0x34 UARTn Control Register
0x34
32
read-write
n
0x0
0x0
HDEN
Half-duplex mode enable
0
1
read-write
Disable
Disable half-duplex mode
0
Enable
Enable half-duplex mode
1
IE
Offset:0x04 UARTn Interrupt Enable Register
DLM
0x4
32
read-write
n
0x0
0x0
ABEOIE
ABE0 interrupt enable
8
9
read-write
Disable
Disable ABEO interrupt
0
Enable
Enable ABEO interrupt
1
ABTOIE
ABT0 interrupt enable
9
10
read-write
Disable
Disable ABTO interrupt
0
Enable
Enable ABTO interrupt
1
RDAIE
RDA interrupt enable
0
1
read-write
Disable
Disable RDA interrupt
0
Enable
Enable RDA interrupt
1
RLSIE
RLS interrupt enable
2
3
read-write
Disable
Disable RLS interrupt
0
Enable
Enable RLS interrupt
1
TEMTIE
TEMT interrupt enable
4
5
read-write
Disable
Disable TEMT interrupt
0
Enable
Enable TEMT interrupt
1
THREIE
THRE interrupt enable
1
2
read-write
Disable
Disable THRE interrupt
0
Enable
Enable THRE interrupt
1
II
Offset:0x08 UARTn Interrupt Identification Register
0x8
32
read-only
n
0x0
0x0
ABEOIF
ABEO interrupt flag
8
9
read-only
Not end
Auto-baud has not finished
0
End
Auto-baud has finished and interrupt is enabled
1
ABTOIF
ABTO interrupt flag
9
10
read-only
Not Time-out
Auto-baud has not timed out
0
Time-out
Auto-baud has timed out and interrupt is enabled
1
FIFOEN
Equal to FIFOEN bits in USARTn_FIFOCTRL register
6
8
read-only
INTID
Interrupt ID of RX FIFO
1
4
read-only
3a
THRE interrupt
1
2a
RDA (Receive Data Available)
2
1
RLS (Receive Line Status)
3
3b
TEMT interrupt
7
INTSTATUS
Interrupt status
0
1
read-only
Pending
As least 1 interrupt is pending
0
No interrupt
No interrupt
1
LC
Offset:0x0C UARTn Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
Break control
6
7
read-write
Disable
Disable break transmission
0
Enable
Enable break transmission
1
DLAB
Divisor Latch access
7
8
read-write
Disable
Disable access to Divisor Latch
0
Enable
Enable access to Divisor Latch
1
PE
Parity enable
3
4
read-write
Disable
Disable parity generation and checking
0
Enable
Enable parity generation and checking
1
PS
Parity selection
4
6
read-write
0
Odd parity
0
1
Even parity
1
2
Forced 1 sticky parity
2
3
Forced 0 sticky parity
3
SBS
Stop bit selection
2
3
read-write
1 stop bit
1 stop bit
0
2 stop bit
2 stop bit (1.5 stop bit if WLS=0)
1
WLS
Word length selection
0
2
read-write
5-bit
5-bit character
0
6-bit
6-bit character
1
7-bit
7-bit character
2
8-bit
8-bit character
3
LS
Offset:0x14 UARTn Line Status Register
0x14
32
read-only
n
0x0
0x0
BI
Break interrupt flag
4
5
read-only
No
No break interrupt
0
Break interrupt
Break interrupt status is active
1
FE
Framing error flag
3
4
read-only
No
No framing error
0
Framing error
Framing error status is active
1
OE
Overrun error flag
1
2
read-only
No
No overrun error
0
Overrun error
Overrun error status is active
1
PE
Parity error flag
2
3
read-only
No
No parity error
0
Parity error
Parity error status is active
1
RDR
Receiver data ready flag
0
1
read-only
Not ready
UARTn_RB FIFO is empty
0
Ready
UARTn_RB FIFO contains valid data
1
RXFE
Receiver FIFO error flag
7
8
read-only
No RX FIFO error
UARTn_RB contains no UART RX errors
0
RX FIFO error
UARTn_RB contains at least 1 UART RX error
1
TEMT
Transmitter empty flag
6
7
read-only
Not empty
THR and/or TSR contains valid data
0
Empty
THR and TSR are both empty
1
THRE
THR empty flag
5
6
read-only
Not empty
THR contains valid data
0
Empty
THR (TX FIFO) is empty
1
RB
Offset:0x00 UARTn Receiver Buffer Register
0x0
32
read-only
n
0x0
0x0
RB
The received byte in UART RX FIFO
0
8
read-only
SP
Offset:0x1C UARTn Scratch Pad Register
0x1C
32
read-write
n
0x0
0x0
PAD
Pad informaton
0
8
read-write
TH
Offset:0x00 UARTn Transmit Holding Register
RB
0x0
32
write-only
n
0x0
0x0
TH
The byte to be transmitted in UART TX FIFO when transmitter is available
0
8
write-only
SN_UC
UC Registers
UC
0x0
0x0
0x2000
registers
n
H4BYTE
Offset:0x08 UC High 4 Byte Register
0x8
32
read-only
n
0x0
0x0
L4BYTE
Offset:0x00 UC Low 4 Byte Register
0x0
32
read-only
n
0x0
0x0
SN_WDT
Watchdog Timer
WDT
0x0
0x0
0x2000
registers
n
WDT
Watchdog Timer
25
CFG
Offset:0x00 WDT Configuration Register
0x0
32
read-write
n
0x0
0x0
WDKEY
WDT register key
16
32
write-only
WDTEN
WDT enable
0
1
read-write
Disable
Disable WDT
0
Enable
Enable WDT
1
WDTIE
WDT interrupt enable
1
2
read-write
Disable
WDT reset when WDT time-out
0
Enable
Enable WDT interrupt
1
WDTINT
WDT interrupt flag
2
3
read-write
No
No WDT time-out
0
WDT time-out
WDT interrupt is triggered if WDTIE=1
1
FEED
Offset:0x0C WDT Feed Register
0xC
32
write-only
n
0x0
0x0
FV
Watchdog feed value
0
16
write-only
WDKEY
WDT register key
16
32
write-only
TC
Offset:0x08 WDT Timer Constant Register
0x8
32
read-write
n
0x0
0x0
TC
Watchdog timer constant reload value
0
8
read-write
WDKEY
WDT register key
16
32
write-only