STMicroelectronics BlueNRG1 2024.05.03 ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 32MHz CM0 r0p0 little 2 false 8 32 ADC ADC ADC 0x0 0x0 0x1000 registers n ADC ADC interrupt 13 CONF ADC configuration register 0x4 32 read-write n 0x0 0x0 CHSEL Select the input channel:

000b: All switches open.
001b: Single ended through ADC2 pin. InP=VREF (internal), InN=ADC2 pin.
010b: Single ended through ADC1 pin. InP=ADC1 pin, InN=VREF (internal).
011b: Differential ADC1 pin - ADC2 pin, InP=ADC1 pin, InN=ADC2 pin.
101b: Battery level detector. InP=0.6V (internal), InN=BLD.
110b: Short InN=InP=0.6V (internal).

1 3 ALL_SWITCH_OPEN All switch open 0 SINGLE_VINP Single ended InP=ANATEST2 pin, InN=VREF (internal) 1 SINGLE_VINN Single ended InN=ANATEST3 pin, InP=VREF (internal) 2 DIFF_INP_INN Differential InP=ANATEST2 pin, InN=ANATEST3 pin 3 TEMP_SENS InP=VTEMPSENS (internal), InN=0.6V (internal) 4 BATT_SENS InP=VBATSENS (internal), InN=0.6V (internal) 5 SHORT InP=InN=0.6V (internal) 6 CONT Enable the continuous conversion mode:

0: Single conversion.
1: Continuous conversion.

11 1 SINGLE Single conversion mode 0 CONT Continuous conversion mode 1 DECIM_RATE Set the ADC resolution:

00b: Set the decimation factor to 200.
01b: Set the decimation factor to 100.
10b: Set the decimation factor to 64.
11b: Set the decimation factor to 32.

6 2 DECIM_200 Set the decimation factor to 200 0 DECIM_100 Set the decimation factor to 100 1 DECIM_64 Set the decimation factor to 64 2 DECIM_32 Set the decimation factor to 32 3 DIG_FILT_CLK Frequency clock selection value on GPIO0 when MIC_SEL=1:

0: 0.8 MHz.
1: 1.6 MHz.

20 1 CLK_0MHz8 Frequency clock to 0.8 MHz 0 CLK_1MHz6 Frequency clock to 1.6 MHz 1 DIS_WKP_WAIT Disable the wake-up timer before to start the conversion from input:

0: Do not disable the wake up time before conversion.
1: Disable the wake up time before conversion.

21 1 ENABLE Do not disable the wake up time before conversion 0 DISABLE Disable the wake up time before conversion 1 EN_DFMODE Control the current in differential mode:

0: Differential mode with DC common mode current not nulled.
1: Differential mode with DC common mode current nulled.

0 1 DFMODE_OFF Differential mode with DC common mode current not nulled 0 DFMODE_ON Differential mode with DC common mode current nulled 1 MIC_SEL Provides the clock on GPIO:

0: Do not provided any external clock source.
1: Provide clock source from GPIO.

22 1 DISABLE Do not provided any external clock source 0 ENABLE Provide clock source from GPIO 1 PGASEL Set the input attenuator value:

000b: Input attenuator at 0 dB.
001b: Input attenuator at 6.02 dB.
010b: Input attenuator at 9.54 dB.

8 2 IN_ATT_0dB0 Input attenuator at 0 dB 0 IN_ATT_6dB02 Input attenuator at 6.02 dB 1 IN_ATT_9dB54 Input attenuator at 9.54 dB 2 REFSEL Set the VREF for single ended conversion:

00b: 0.0V.
01b: 0.4V.
10b: 0.6V.
11b: 1.2V.

4 2 RESEL_0V0 Set the VREF at 0.0 V 0 RESEL_0V4 Set the VREF at 0.4 V 1 RESEL_0V6 Set the VREF at 0.6 V 2 RESEL_1V2 Set the VREF at 1.2 V 3 ROUND16 Result mapped on 32 or 16 bits:

0: Output result mapped to 32 bits.
1: Output result mapped to 16 bits.

17 1 MAPPED_32 Output result mapped to 32 bits 0 MAPPED_16 Output result mapped to 16 bits 1 SKIP It permits to bypass the filter comb to speed up the conversion for signal at low frequency:

0: Filter for comb not bypassed.
1: Filter for comb bypassed.

18 1 FILTER_OFF Filter for comb not bypassed 0 FILTER_ON Filter for comb bypassed 1 CTRL ADC control register 0x2 16 read-write n 0x0 0x0 AUTO_OFFSET Enables the update of ADC_OFFSET register.

0: ADC_OFFSET register is not updated.
1: ADC_OFFSET register is updated.

7 1 CAL_OFF ADC automatic calibration disable 0 CAL_ON ADC automatic calibration enable 1 CALEN Enables the calibration phase when set to 1. This bit is cleared and the calibration is disabled by setting the RSTADCCALEN bit. 1 1 CAL_OFF ADC automatic calibration disable 0 CAL_ON ADC automatic calibration enable 1 DMA_EN Enables the DMA.

0: DMA is disabled.
1: DMA is enabled.

9 1 DMA_OFF ADC DMA disable 0 DMA_ON ADC DMA enable 1 ENAB_COMP Enables the window comparator when set to 1. WDOG flag is ADC_SR register is set if the converted value is between ADCTHRESHOLD_HI and ADCTHRESHOLD_LO value. 5 1 MIC_ON Enables the filter chain for voice when set to 1.

0: Filter chain is disabled.
1: Filter chain is enabled.

8 1 MIC_OFF Filter chain disable 0 MIC_ON Filter chain enable 1 ON Starts ADC analog subsystem. This bit must be set before starting a conversion.

0: ADC is OFF.
1: ADC is ON.

0 1 OFF ADC analog part disable 0 ON ADC analog part enable 1 RESET Reset all the ADC APB registers when set. 3 1 RESET Reset all the registers content 1 RSTCALEN Disable the calibration phase when set to 1. This bit has to be set to disable the calibration each time calibration is enabled. 6 1 RESET Reset the ADCCALEN bit. Disable the automatic calibration when it is enabled 1 STOP Permits to stop the continuous conversion.

0: continuous conversion is enabled but SWSTART and ADCON bits must be set.
1: stop the continuous conversion and switch off the ADC.

4 1 STOP Stop the continuous mode conversion 1 SWSTART Starts the ADC conversion phase when set. 2 1 START Starts the ADC conversion phase when set. 1 DATA_CONV Result of the conversion in two complement format:

if ROUND16=0: result is mapped on all 32-bit (can be truncated with loss of ADCDATAOUT[30:15])
if ROUND16=1: result is mapped on 16-bit (can be truncated with loss of ADCDATAOUT[15:0])

0x14 32 read-only n 0x0 0x0 IRQMASK It sets the mask for ADC interrupt 0xC 8 read-write n 0x0 0x0 BUSY Interrupt mask for the ADC busy event:

0: Interrupt is enabled.
1: Interrupt is disabled.

1 1 ENDCAL Interrupt mask for the end of calibration event:

0: Interrupt is enabled.
1: Interrupt is disabled.

0 1 EOC Interrupt mask for the end of conversion event:

0: Interrupt is enabled.
1: Interrupt is disabled.

2 1 WDOG Interrupt mask for the within the threhsold event:

0: Interrupt is enabled.
1: Interrupt is disabled.

3 1 IRQSTAT IRQ masked status register 0x8 8 read-only n 0x0 0x0 BUSY 1: during conversion. Clear on register read if BUSY condition no more active. 1 1 ENDCAL 1: when the calibration is completed. Clear on register read. 0 1 EOC 1: when the conversion is completed. Clear on register read. 2 1 WDOG 1: when the data is within the thresholds. Clear on register read. 3 1 OFFSET Offset for correction of converted data 0x18 32 read-write n 0x0 0x0 SR_REG ADC status register 0x20 8 read-write n 0x0 0x0 BUSY 1: during conversion. 1 1 ENDCAL 1: when the calibration is completed. The result of the calibration is written in the ADC_OFFSET register. 0 1 EOC 1: when the conversion is completed. 2 1 WDOG If ENAB_COMP=1, this bit indicates the result of the conversion is between high and low threshold:

0: DATAOUT[31:0] is NOT between THRESHOLD_HI and THRESHOLD_LO values.
1: DATAOUT[31:0] is between THRESHOLD_HI and THRESHOLD_LO values.

3 1 THRESHOLD_HI High threshold for window comparator 0x24 32 read-write n 0x0 0x0 THRESHOLD_LO Low threshold for window comparator 0x28 32 read-write n 0x0 0x0 AHBUPCONV AHB up/down converter converter AHBUPCONV 0x0 0x0 0x1000 registers n COMMAND AHB up/down converter command register 0x0 8 read-write n 0x0 0x0 BLUE_CTRL BLUE Controller BLUE_CTRL 0x0 0x0 0x1000 registers n BLUE_CTRL BLUE controller interrupt 6 RADIO_CONFIG Radio configuration register 0xC 32 read-write n 0x0 0x0 TIMEOUT Timeout programming register 0x4 32 read-write n 0x0 0x0 CKGEN_BLE Clock Gen BLE CKGEN_BLE 0x0 0x0 0x1000 registers n CLK32K_COUNT Counter of 32 kHz clock 0xC 16 read-write n 0x0 0x0 SLOW_COUNT Program the window length (in slow clock period unit) for slow clock measurement 0 9 CLK32K_FREQ Measurement of frequency of 32 kHz clock 0x14 32 read-only n 0x0 0x0 SLOW_FREQ Value equal to 2^33 / SLOW_PERIOD 0 27 read-only CLK32K_IT Interrupt event for 32 kHz clock measurement 0x18 16 read-write n 0x0 0x0 CLK32K_MEAS_IRQ When read, provides the status of the interrupt indicating slow lock measurement is finished:

0: No pending interrupt.
1: Pending interrupt.

When written, clears the interrupt:

0: No effect.
1: Clear the interrupt.

0 1 CLK32K_PERIOD Period of 32 kHz clock 0x10 32 read-write n 0x0 0x0 SLOW_PERIOD Indicates slow clock period information. The result provided in this field corresponds to the length of SLOW_COUNT periods of the slow clock (32 kHz) measured in 16 MHz half-period unit. The measurement is done automatically each time the device enters in active2 mode using SLOW_COUNT = 16. A new calculation can be launched by writing zero in CLK32K_PERIOD register. In this case, the time window uses the value programmed in SLOW_COUNT field. 0 19 read-only REASON_RST Indicates the reset reason from BLE 0x8 16 read-only n 0x0 0x0 BOR Reset from BOR 1 1 read-only POR Reset from POR 2 1 read-only WKP2_BLUE Wakeup coms from the timer 2 expiration in the wakeup control block of the BLE radio 10 1 read-only WKP_BLUE Wakeup coms from the timer 1 expiration in the wakeup control block of the BLE radio 8 1 read-only WKP_IO10 Wakeup from external IO10 4 1 read-only WKP_IO11 Wakeup from external IO11 5 1 read-only WKP_IO12 Wakeup from external IO12 6 1 read-only WKP_IO13 Wakeup from external IO13 7 1 read-only WKP_IO9 Wakeup from external IO9 3 1 read-only CKGEN_SOC Clock Gen SOC CKGEN_SOC 0x0 0x0 0x1000 registers n CLOCK_EN Enable or gates the APB clock of the peripherals 0x20 32 read-write n 0x0 0x0 ADC ADC clock 8 1 read-write DMA DMA AHB clock 16 1 read-write GPIO GPIO clock 0 1 read-write I2C1 I2C1 clock 9 1 read-write I2C2 I2C2 clock 10 1 read-write MFT1 MFT1 clock 11 1 read-write MFT2 MFT2 clock 12 1 read-write NVM Flash controller clock 1 1 read-write RNG RNG AHB clock 17 1 read-write RTC RTC clock 13 1 read-write SPI SPI clock 4 1 read-write SYSCTRL System controller clock 2 1 read-write UART UART clock 3 1 read-write WDOG Watchdog clock 7 1 read-write CONTROL Control clock and reset of SOC 0x0 32 read-write n 0x0 0x0 UART_CKDIV UART baud rate clock setting from 1 to 16 MHz according to the formula 16 / (n + 1) MHz. 10 4 read-write DIE_ID Identification information of the device 0x1C 32 read-only n 0x0 0x0 PRODUCT Product 9 3 read-only REV Cut revision 0 4 read-only VERSION Cut version 4 5 read-only DMA_CONFIG DMA config 0x24 8 read-write n 0x0 0x0 ADC_CH0 Select ADC on DMA channel 0 instead of peripheral 0 1 read-write disable disable 0 enable enable 1 ADC_CH1 Select ADC on DMA channel 1 instead of peripheral 1 ADC_CH2 Select ADC on DMA channel 2 instead of peripheral 2 ADC_CH3 Select ADC on DMA channel 3 instead of peripheral 3 ADC_CH4 Select ADC on DMA channel 4 instead of peripheral 4 ADC_CH5 Select ADC on DMA channel 5 instead of peripheral 5 ADC_CH6 Select ADC on DMA channel 6 instead of peripheral 6 ADC_CH7 Select ADC on DMA channel 7 instead of peripheral 7 REASON_RST Indicates the reset reason from Cortex-M0 0x8 8 read-only n 0x0 0x0 LOCKUP Reset caused by Cortex-M0 asserting LOCKUP signal 3 1 read-only SYSREQ Reset caused by Cortex-M0 debug asserting SYSRESETREQ 1 1 read-only WDG Reset caused by assertion of watchdog reset 2 1 read-only DMA DMA DMA 0x0 0x0 0x1000 registers n DMA DMA interrupt 23 IFCR DMA interrupt flag clear register 0x4 32 write-only n 0x0 0x0 CGIF0 Channel 0 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

0 1 CGIF1 Channel 1 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

4 1 CGIF2 Channel 2 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

8 1 CGIF3 Channel 3 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

12 1 CGIF4 Channel 4 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

16 1 CGIF5 Channel 5 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

20 1 CGIF6 Channel 6 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

24 1 CGIF7 Channel 7 global interrupt flag. This bit is set by software.

0: No effect.
1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

28 1 CHTIF0 Channel 0 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

2 1 CHTIF1 Channel 1 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

6 1 CHTIF2 Channel 2 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

10 1 CHTIF3 Channel 3 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

14 1 CHTIF4 Channel 4 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

18 1 CHTIF5 Channel 5 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

22 1 CHTIF6 Channel 6 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

26 1 CHTIF7 Channel 7 half transfer flag. This bit is set by software.

0: No effect.
1: Clears the corresponding HTIF flag in the ISR register.

30 1 CTCIF0 Channel 0 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

1 1 CTCIF1 Channel 1 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

5 1 CTCIF2 Channel 2 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

9 1 CTCIF3 Channel 3 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

13 1 CTCIF4 Channel 4 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

17 1 CTCIF5 Channel 5 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

21 1 CTCIF6 Channel 6 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

25 1 CTCIF7 Channel 7 transfer complete flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TCIF flag in the ISR register.

29 1 CTEIF0 Channel 0 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

3 1 CTEIF1 Channel 1 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

7 1 CTEIF2 Channel 2 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

11 1 CTEIF3 Channel 3 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

15 1 CTEIF4 Channel 4 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

19 1 CTEIF5 Channel 5 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

23 1 CTEIF6 Channel 6 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

27 1 CTEIF7 Channel 7 transfer error flag. This bit is set by software.

0: No effect.
1: Clears the corresponding TEIF flag in the ISR register.

31 1 ISR DMA interrupt status register 0x0 32 read-only n 0x0 0x0 GIF0 Channel 0 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 0.
1: A TE, HT or TC event occurred on channel 0.

0 1 GIF1 Channel 1 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 1.
1: A TE, HT or TC event occurred on channel 1.

4 1 GIF2 Channel 2 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 2.
1: A TE, HT or TC event occurred on channel 2.

8 1 GIF3 Channel 3 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 3.
1: A TE, HT or TC event occurred on channel 3.

12 1 GIF4 Channel 4 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 4.
1: A TE, HT or TC event occurred on channel 4.

16 1 GIF5 Channel 5 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 5.
1: A TE, HT or TC event occurred on channel 5.

20 1 GIF6 Channel 6 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 6.
1: A TE, HT or TC event occurred on channel 6.

24 1 GIF7 Channel 7 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 7.
1: A TE, HT or TC event occurred on channel 7.

28 1 HTIF0 Channel 0 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 0.
1: A half transfer (HT) event occurred on channel 0.

2 1 HTIF1 Channel 1 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 1.
1: A half transfer (HT) event occurred on channel 1.

6 1 HTIF2 Channel 2 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 2.
1: A half transfer (HT) event occurred on channel 2.

10 1 HTIF3 Channel 3 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 3.
1: A half transfer (HT) event occurred on channel 3.

14 1 HTIF4 Channel 4 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 4.
1: A half transfer (HT) event occurred on channel 4.

18 1 HTIF5 Channel 5 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 5.
1: A half transfer (HT) event occurred on channel 5.

22 1 HTIF6 Channel 6 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 6.
1: A half transfer (HT) event occurred on channel 6.

26 1 HTIF7 Channel 7 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 7.
1: A half transfer (HT) event occurred on channel 7.

30 1 TCIF0 Channel 0 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 0.
1: A transfer complete (TC) occurred on channel 0.

1 1 TCIF1 Channel 1 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 1.
1: A transfer complete (TC) occurred on channel 1.

5 1 TCIF2 Channel 2 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 2.
1: A transfer complete (TC) occurred on channel 2.

9 1 TCIF3 Channel 3 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 3.
1: A transfer complete (TC) occurred on channel 3.

13 1 TCIF4 Channel 4 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 4.
1: A transfer complete (TC) occurred on channel 4.

17 1 TCIF5 Channel 5 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 5.
1: A transfer complete (TC) occurred on channel 5.

21 1 TCIF6 Channel 6 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 6.
1: A transfer complete (TC) occurred on channel 6.

25 1 TCIF7 Channel 7 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 7.
1: A transfer complete (TC) occurred on channel 7.

29 1 TEIF0 Channel 0 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 0.
1: A transfer error (TE) occurred on channel 0.

3 1 TEIF1 Channel 1 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 1.
1: A transfer error (TE) occurred on channel 1.

7 1 TEIF2 Channel 2 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 2.
1: A transfer error (TE) occurred on channel 2.

11 1 TEIF3 Channel 3 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 3.
1: A transfer error (TE) occurred on channel 3.

15 1 TEIF4 Channel 4 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 4.
1: A transfer error (TE) occurred on channel 4.

19 1 TEIF5 Channel 5 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 5.
1: A transfer error (TE) occurred on channel 5.

23 1 TEIF6 Channel 6 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 6.
1: A transfer error (TE) occurred on channel 6.

27 1 TEIF7 Channel 7 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 7.
1: A transfer error (TE) occurred on channel 7.

31 1 DMA_CH0 DMA channel DMA_CH 0x0 0x0 0x1000 registers n CCR DMA channel configuration register 0x0 32 read-write n 0x0 0x0 CIRC Circular mode.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

0: Circular mode disabled.
1: Circular mode enabled.

5 1 read-write DISABLE Circular mode disable 0 ENABLE Circular mode enable 1 DIR Data transfer direction.

0: Read from peripheral.
1: Read from memory.

4 1 read-write FROM_PERIPHERAL Read from peripheral 0 FROM_MEMORY Read from memory 1 EN DMA channel enable.

0: DMA channel disabled.
1: DMA channel enabled.

0 1 read-write DISABLE DMA channel disable 0 ENABLE DMA channel enable 1 HTIE Half transfer interrupt enable.

0: HT interrupt disabled.
1: HT interrupt enabled.

2 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 MEM2MEM Memory to memory mode.

0: Memory to memory mode disabled.
0: Memory to memory mode enabled.

14 1 read-write MINC Memory increment mode.

0: Memory increment disabled.
1: Memory increment enabled.

7 1 read-write DISABLE Memory increment disable 0 ENABLE Memory increment enable 1 MSIZE Memory size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

10 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 PINC Peripheral increment mode.

0: Peripheral increment disabled.
1: Peripheral increment enabled.

6 1 read-write DISABLE Peripheral increment disable 0 ENABLE Peripheral increment enable 1 PL Channel priority level.

00b: Low priority.
01b: Medium priority.
10b: High priority.
11b: Very high priority.

12 2 read-write LOW Low priority 0 MEDIUM Medium priority 1 HIGH High priority 2 VERY_HIGH Very high priority 3 PSIZE Peripheral size.

00b: Size 8 bits.
01b: Size 16 bits.
10b: Size 32 bits.

8 2 read-write SIZE8BIT Size 8 bits 0 SIZE16BIT Size 16 bits 1 SIZE32BIT Size 32 bits 2 RESERVED1 Reserved 15 17 read-only TCIE Transfer complete interrupt enable.

0: TC interrupt disabled.
1: TC interrupt enabled.

1 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 TEIE Transfer error interrupt enable.

0: TE interrupt disabled.
1: TE interrupt enabled.

3 1 read-write DISABLE Interrupt source disable 0 ENABLE Interrupt source enable 1 CMAR DMA channel memory address register 0xC 32 read-write n 0x0 0x0 MA Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. 0 32 read-write CNDTR DMA channel number of data register. 0x4 32 read-write n 0x0 0x0 NDT Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 0 16 read-write RESERVED1 Reserved 16 16 read-only CPAR DMA channel peripheral address register 0x8 32 read-write n 0x0 0x0 PA Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. 0 32 read-write FLASH Flash Controller Flash 0x0 0x0 0x1000 registers n NVM Non-volatile memory (Flash) controller interrupt 1 ADDRESS Address for programming Flash, will auto-increment 0x18 32 read-write n 0x0 0x0 COMMAND Commands for the module 0x0 16 read-write n 0x0 0x0 CONFIG Configure the wrapper 0x4 16 read-write n 0x0 0x0 DATA0 Program cycle data 0x40 32 read-write n 0x0 0x0 DATA1 Program cycle data 0x44 32 read-write n 0x0 0x0 DATA2 Program cycle data 0x48 32 read-write n 0x0 0x0 DATA3 Program cycle data 0x4C 32 read-write n 0x0 0x0 IRQMASK Mask for interrupts 0xC 16 read-write n 0x0 0x0 CMDDONE Command is done. 0 1 IRQ_NOT_PENDING Irq not pending 0 IRQ_PENDING Irq pending 1 CMDERR Command written while BUSY 2 CMDSTART Command is started. 1 FLNREADY Flash not ready (sleep). 5 ILLCMD Illegal command written 3 READOK Mass read was OK. 4 IRQRAW Status interrupts (unmasked) 0x10 16 read-write n 0x0 0x0 CMDDONE Command is done. 0 1 IRQ_NOT_PENDING Irq not pending 0 IRQ_PENDING Irq pending 1 CMDERR Command written while BUSY 2 CMDSTART Command is started. 1 FLNREADY Flash not ready (sleep). 5 ILLCMD Illegal command written 3 READOK Mass read was OK. 4 IRQSTAT Flash status interrupt (masked) 0x8 16 read-write n 0x0 0x0 CMDDONE Command is done. 0 1 IRQ_NOT_PENDING Irq not pending 0 IRQ_PENDING Irq pending 1 CMDERR Command written while BUSY 2 CMDSTART Command is started. 1 FLNREADY Flash not ready (sleep). 5 ILLCMD Illegal command written 3 READOK Mass read was OK. 4 LFSRVAL LFSR register needed for check after MASS READ command 0x24 32 read-only n 0x0 0x0 SIZE Indicates the last usable address of the main Flash 0x14 16 read-only n 0x0 0x0 TIMETRIM1 Trimming values for Flash erase/modify sequences 0x28 32 read-write n 0x0 0x0 TIMETRIM2 Trimming values for Flash erase/modify sequences 0x2C 32 read-write n 0x0 0x0 TIMETRIM3 Trimming values for Flash wake-up sequence 0x30 32 read-write n 0x0 0x0 GPIO GPIO Controller GPIO 0x0 0x0 0x1000 registers n GPIO GPIO bus interrupt 0 DATA IO0 to IO14 data value.

Writing to a bit will drive the written value on the corresponding IO when it is configured in GPIO mode and the output direction. Reading a bit indicates the pin value

0x0 32 read-write n 0x0 0x0 DATC Clear some bits of DATA when in GPIO mode without affecting the others (1 bit per IO).

0: no effect.
1: clear at 0 the bit

0x40 32 read-write n 0x0 0x0 DATS Set some bits of DATA when in GPIO mode without affecting the others (1 bit per IO).

0: no effect.
1: set at 1 the bit

0x3C 32 read-write n 0x0 0x0 DS IO driver strength (1 bit per IO).

0: 2mA.
1: 4 mA

0xC 32 read-write n 0x0 0x0 IBE Interrupt edge register (1 bit per IO).

0: single edge.
1: both edges

0x14 32 read-write n 0x0 0x0 IC Interrupt clear register (1 bit per IO).

0: no effect.
1: clear interrupt

0x28 32 write-only n 0x0 0x0 oneToClear IE Interrupt mask register (1 bit per IO).

0: masked.
1: not masked

0x1C 32 read-write n 0x0 0x0 IEV Interrupt event register (1 bit per IO).

0: falling edge or low level.
1: rising edge or high level

0x18 32 read-write n 0x0 0x0 IS Interrupt sense register (1 bit per IO).

0: edge detection.
1: level detection

0x10 32 read-write n 0x0 0x0 MFTX Select the IO to be used as capture input for the MFTX timers 0x44 32 read-write n 0x0 0x0 MFT1_TIMER_A MFT1 timer A.

0x00: IO0.
0x01: IO1
0x02: IO2
...
0x0E: IO14

0 8 read-write IO0 IO0 0x0 IO1 IO1 0x1 IO16 IO16 0x10 IO17 IO17 0x11 IO18 IO18 0x12 IO19 IO19 0x13 IO20 IO20 0x14 IO21 IO21 0x15 IO22 IO22 0x16 IO23 IO23 0x17 IO24 IO24 0x18 IO25 IO25 0x19 IO2 IO2 0x2 IO3 IO3 0x3 IO4 IO4 0x4 IO5 IO5 0x5 IO6 IO6 0x6 IO7 IO7 0x7 IO8 IO8 0x8 IO9 IO9 0x9 IO10 IO10 0xA IO11 IO11 0xB IO12 IO12 0xC IO13 IO13 0xD IO14 IO14 0xE IO15 IO15 0xF MFT1_TIMER_B MFT1 timer B.

0x00: IO0.
0x01: IO1
0x02: IO2
...
0x0E: IO14

8 MFT2_TIMER_A MFT2 timer A.

0x00: IO0.
0x01: IO1
0x02: IO2
...
0x0E: IO14

16 MFT2_TIMER_B MFT2 timer B.

0x00: IO0.
0x01: IO1
0x02: IO2
...
0x0E: IO14

24 MIS Masked interrupt status register (1 bit per IO) 0x24 32 read-only n 0x0 0x0 MODE0 Select mode for IO0 to IO7.

000b: GPIO mode.
001b: Serial1 mode.
100b: Serial0 mode.
101b: Microphone/ADC mode.

0x2C 32 read-write n 0x0 0x0 IO0 IO0 mode 0 3 read-write GPIO_MODE GPIO mode 0x0 SERIAL1_MODE serial1 mode 0x1 STANDALONE_MODE standalone mode 0x2 BLUE_MODE BLE mode 0x3 SERIAL0_MODE serial0 mode 0x4 MICROPHONE_ADC_MODE ADC mode for microphone 0x5 IO1 IO1 mode 4 3 IO2 IO2 mode 8 3 IO3 IO3 mode 12 3 IO4 IO4 mode 16 3 IO5 IO5 mode 20 3 IO6 IO6 mode 24 3 IO7 IO7 mode 28 3 MODE1 Select mode for IO8 to IO14.

000b: GPIO mode.
001b: Serial1 mode.
100b: Serial0 mode.
101b: Microphone/ADC mode.

0x30 32 read-write n 0x0 0x0 IO10 IO10 mode 8 3 IO11 IO11 mode 12 3 IO12 IO12 mode 16 3 IO13 IO13 mode 20 3 IO14 IO14 mode 24 3 IO8 IO8 mode 0 3 read-write GPIO_MODE GPIO mode 0x0 SERIAL1_MODE serial1 mode 0x1 STANDALONE_MODE standalone mode 0x2 BLUE_MODE BLE mode 0x3 SERIAL0_MODE serial0 mode 0x4 MICROPHONE_ADC_MODE ADC mode for microphone 0x5 IO9 IO9 mode 4 3 OEN GPIO output enable register (1 bit per GPIO).

0: input mode.
1: output mode

0x4 32 read-write n 0x0 0x0 PE Pull enable (1 bit per IO).

0: pull disabled.
1: pull enabled

0x8 32 read-write n 0x0 0x0 I2C1 I2C1 I2C 0x0 0x0 0x1000 registers n I2C1 I2C 1 interrupt 15 BRCR I2C Baud-rate counter register 0x28 16 read-write n 0x0 0x0 BRCNT Baud rate counter. BRCNT defines the counter value used to set up the I2C baud rate in standard and fast mode, when the peripheral is operating in master mode. 0 16 CR I2C Control register 0x0 32 read-write n 0x0 0x0 DMA_RX_EN Enables the DMA RX interface.

0: Idle state, the DMA RX interface is disabled.
1: Run state, the DMA RX interface is enabled.

On the completion of the DMA transfer, the DMA RX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time. 10 1 DISABLE DMA RX interface disable 0x00 ENABLE DMA RX interface enable 0x01 DMA_TX_EN Enables the DMA TX interface.

0: Idle state, the DMA TX interface is disabled.
1: Run state, the DMA TX interface is enabled.

On the completion of the DMA transfer, the DMA TX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time. 9 1 DISABLE DMA TX interface disable 0x00 ENABLE DMA TX interface enable 0x01 FON Filtering on sets the digital filters on the SDA, SCL line, according to the I2C bus requirements, when standard open-drain pads are used:

00b: No digital filters are inserted.
01b: Digital filters (filter 1 ck wide spikes) are inserted.
10b: Digital filters (filter 2 ck wide spikes) are inserted.
11b: Digital filters (filter 4 ck wide spikes) are inserted.

13 2 NONE No digital filters are inserted 0x00 CK1_SPIKES Digital filters (filter 1 ck wide spikes) are inserted 0x01 CK2_SPIKES Digital filters (filter 2 ck wide spikes) are inserted 0x02 CK4_SPIKES Digital filters (filter 4 ck wide spikes) are inserted 0x03 FRX FRX flushes the receive circuitry (FIFO, fsm).The configuration of the I2C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I2C clocks) and needs several system clock cycles before to be completed. Upon completion, the I2C node (internal logic) clears this bit. The application must not access the Rx FIFO during the flushing operation and should poll on this bit waiting for the completion.

0: Flush operation is completed (I2C controller clears the bit).
1: Flush operation is started and in progress (set by application).

8 1 oneToSet FS_1 Force stop enable bit. When set to 1b, the STOP condition is generated.

0: Force stop disabled.
1: Enable force stop.

15 1 DISABLE Force stop disable 0x00 ENABLE Force stop enable 0x01 FTX FTX flushes the transmit circuitry (FIFO, fsm). The configuration of the I2C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I2C clocks) and needs several system clock cycles before being completed. Upon completion, the I2C node (internal logic) clears this bit. The application must not access the Tx FIFO during the flushing operation and should poll on this bit waiting for completion.

0: Flush operation is completed (I2C controller clears the bit).
1: Flush operation is started and in progress (set by application).

7 1 oneToSet OM Select the operating mode:

00b: Slave mode. The peripheral can only respond (transmit/receive) when addressed by a master device
01b: Master mode. The peripheral works in a multi-master system where itself cannot be addressed by another master device. It can only initiate a new transfer as master device.
10b: Master/slave mode. The peripheral works in a multi-master system where itself can be addressed by another master device, besides to initiate a transfer as master device.

1 2 SLAVE The peripheral can only respond (transmit/receive) when addressed by a master device 0x00 MASTER The peripheral works in a multi-master system where itself cannot be addressed by another master device. It can only initiate a new transfer as master device 0x01 MASTER_SLAVE The peripheral works in a multi-master system where itself can be addressed by another master device, besides to initiate a transfer as master device 0x02 PE I2C enable disable:

0: I2C disable.
1: I2C enable.

This bit when deasserted works as software reset for I2C peripheral. 0 1 DISABLE I2C disable 0 ENABLE I2C enable 1 SAM Slave addressing mode. SAM defines the slave addressing mode when the peripheral works in slave or master/slave mode. The received address is compared with the content of the register SCR.

0: 7-bit addressing mode.
1: 10-bit addressing mode.

3 1 ADDR_7BIT 7-bit addressing mode 0x00 ADDR_10BIT 10-bit addressing mode 0x01 SGCM Slave general call mode defines the operating mode of the slave controller when a general call is received. This setting does not affect the hardware general call that is always managed in transparent mode.

0: transparent mode, the slave receiver recognizes the general call but any action is taken by the hardware after the decoding of the message included in the Rx FIFO.
1: direct mode, the slave receiver recognizes the general call and executes directly (without software intervention) the related actions. Only the status code word is stored in the I2C_SR register for notification to the application.

6 1 TRANSPARENT_MODE Transparent mode, the slave receiver recognizes the general call ut any action is taken by software after the decoding of the message included in the Rx FIFO 0x00 DIRECT_MODE Direct mode, the slave receiver recognizes the general call and executes directly (without software intervention) the related actions. Only the status code word is stored in the SR register for notification to the application 0x01 SM Speed mode. SM defines the speed mode related to the serial bit rate:

0: Standard mode (up to 100 K/s).
1: Fast mode (up to 400 K/s).

4 2 STANDARD_MODE Standard mode (up to 100 K/s) 0x00 FAST_MODE Fast mode (up to 400 K/s) 0x01 DMAR I2C DMA register 0x24 16 read-write n 0x0 0x0 BURST_TX Defines the type of DMA request generated by the DMA TX interface.

0: Single request mode. Transfers a single data (one byte) in the TX FIFO.
1: Burst request mode. Transfers a programmed burst of data according to DBSIZE_TX field.

When the burst mode is programmed, the DMA transfer can be completed by one or more single requests as required. 11 1 DBSIZE_TX Destination burst size. This register field is valid only if the BURST_TX bit is set to '1'. If burst size is smaller than the transaction length, only single request are generated. 8 3 ICR I2C interrupt clear register 0x38 32 read-write n 0x0 0x0 oneToClear BERRIC Bus Error interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

25 1 LBRIC Length number of bytes received interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

15 1 MALIC Master Arbitration lost interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

24 1 MTDIC Master Transaction done interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

19 1 MTDWSIC Master Transaction done without stop interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

28 1 RFSEIC Read-from-Slave empty interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

17 1 RFSRIC Read-from-Slave request interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

16 1 SALIC Slave Arbitration lost interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

23 1 STDIC Slave Transaction done interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

20 1 TIMEOUTIC Timeout or Tlow error interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

30 1 TXFOVRIC Tx FIFO overrun interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

3 1 WTSRIC Write-to-Slave request interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

18 1 IMSCR I2C interrupt mask set/clear register 0x2C 32 read-write n 0x0 0x0 BERRM Bus Error mask. BERRM enables the interrupt bit BERR:

0: BERR interrupt is disabled.
1: BERR interrupt is enabled.

25 MALM Master Arbitration lost mask. MALM enables the interrupt bit MAL:

0: MAL interrupt is disabled.
1: MAL interrupt is enabled.

24 MTDM Master Transaction done mask. MTDM enables the interrupt bit MTD:

0: MTD interrupt is disabled.
1: MTD interrupt is enabled.

19 MTDWSM Master Transaction done without stop mask. MTDWSM enables the interrupt bit MTDWS:

0: MTDWS interrupt is disabled.
1: MTDWS interrupt is enabled.

28 RFSEM Read-from-Slave empty mask. RFSEM enables the interrupt bit RFSE:

0: RFSE interrupt is disabled.
1: RFSE interrupt is enabled.

17 RFSRM Read-from-Slave request mask. RFSRM enables the interrupt bit RFSR:

0: RFSR interrupt is disabled.
1: RFSR interrupt is enabled.

16 RXFEM RX FIFO empty mask. RXFEM enables the interrupt bit RXFE:

0: RXFE interrupt is disabled.
1: RXFE interrupt is enabled.

4 RXFFM RX FIFO full mask. RXFFM enables the interrupt bit RXFF:

0: RXFF interrupt is disabled.
1: RXFF interrupt is enabled.

6 RXFNFM RX FIFO nearly full mask. RXNFM enables the interrupt bit RXNF:

0: RXNF interrupt is disabled.
1: RXNF interrupt is enabled

5 STDM Slave Transaction done mask. STDM enables the interrupt bit STD:

0: STDM interrupt is disabled.
1: STDM interrupt is enabled.

20 TXFEM TX FIFO empty mask. TXFEM enables the interrupt bit TXFE:

0: TXFE interrupt is disabled.
1: TXFE interrupt is enabled.

0 1 DISABLE Disable the interrupt mask 0 ENABLE Enable the interrupt mask 1 TXFFM TX FIFO full mask. TXFFM enables the interrupt bit TXFF:

0: TXFF interrupt is disabled.
1: TXFF interrupt is enabled.

2 TXFNEM TX FIFO nearly empty mask. TXFNEM enables the interrupt bit TXFNE:

0: TXFNE interrupt is disabled.
1: TXFNE interrupt is enabled.

1 TXFOVRM TX FIFO overrun mask. TXOVRM enables the interrupt bit TXOVR:

0: TXOVR interrupt is disabled.
1: TXOVR interrupt is enabled.

3 WTSRM Write-to-Slave request mask. WTSRM enables the interrupt bit WTSR:

0: WTSR interrupt is disabled.
1: WTSR interrupt is enabled.

18 MCR I2C master control register 0xC 32 read-write n 0x0 0x0 A7 Address. Includes the 7-bit address or the LSB bits of the10-bit address used to initiate the current transaction 1 7 AM Address type:

00b: The transaction is initiated by a general call command. In this case the fields OP, A7, EA10 are "don't care".
01b: The transaction is initiated by the 7-bit address included in the A7 field.
10b: The transaction is initiated by the 10-bit address included in the EA10 and A7 fields.

12 2 GENERAL_CALL The transaction is initiated by a general call command 0x00 BIT7_ADDRESS The transaction is initiated by the 7-bit address included in the A7 field 0x01 BIT10_ADDRESS The transaction is initiated by the 10-bit address included in the EA10 and A7 fields 0x02 EA10 Extended address. Includes the extension (MSB bits) of the field A7 used to initiate the current transaction 8 3 LENGTH Transaction length. Defines the length, in terms of the number of bytes to be transmitted (MW) or received (MR). In case of write operation, the payload is stored in the Tx FIFO. A transaction can be larger than the Tx FIFO size. In case of read operation the length refers to the number of bytes to be received before generating a not-acknowledge response. A transaction can be larger than the Rx FIFO size. The I2C clock line is stretched low until the data in Rx FIFO are consumed. 15 11 OP Operation

0: Indicates a master write operation.
1: Indicates a master read operation.

0 1 MASTER_WRITE Indicates a master write operation 0x00 MASTER_READ Indicates a master read operation 0x01 P Stop condition:

0: The current transaction is not terminated by a STOP condition. A repeated START condition is generated on the next operation which is required to avoid to stall the I2C line.
1: The current transaction is terminated by a STOP condition.

14 1 SB Start byte:

0: The start byte procedure is not applied to the current transaction.
1: The start byte procedure is prefixed to the current transaction.

11 1 MISR I2C masked interrupt status register 0x34 32 read-only n 0x0 0x0 BERRMIS Bus Error masked interrupt status.

0: No bus error detection.
1: Bus error detection.

25 1 LBRMIS Length number of bytes received masked interrupt status.

0: Length number of bytes is not received.
1: Length number of bytes is received.

15 1 MALMIS Master Arbitration lost masked interrupt status.

0: No master arbitration lost.
1: Master arbitration lost.

24 1 MTDMIS Master Transaction done masked interrupt status.

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment).

19 1 MTDWSMIS Master Transaction done without stop masked interrupt status.

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment) and stop is not applied into the I2C bus.

28 1 RFSEMIS Read-from-Slave empty masked interrupt status.

0: TX FIFO is not empty.
1: TX FIFO is empty with the read-from-slave operation in progress.

17 1 RFSRMIS Read-from-Slave request masked interrupt status.

0: Read-from-slave request has been served.
1: Read-from-slave request is pending.

16 1 RXFEMIS RX FIFO empty masked interrupt status.

0: RX FIFO is not empty.
1: RX FIFO is empty..

4 1 RXFFMIS RX FIFO full masked interrupt status.

0: RX FIFO is not full.
1: RX FIFO is full.

6 1 RXFNFMIS RX FIFO nearly full masked interrupt status.

0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.
1: Number of entries in the RX FIFO greater than or equal to the RFTR:THRESHOLD_RX register.

5 1 SALMIS Slave Arbitration lost masked interrupt status.

0: No slave arbitration lost.
1: Slave arbitration lost.

23 1 STDMIS Slave Transaction done masked interrupt status.

0: Slave transaction acknowledged.
1: Slave transaction done (ready for acknowledgment).

20 1 TIMEOUTMIS Timeout or Tlow error masked interrupt status.

0: No timeout error.
1: SCL remained LOW for 25 ms (Timeout).

30 1 TXFEMIS TX FIFO empty masked interrupt status.

0: TX FIFO is not empty.
1: TX FIFO is empty.

0 1 TXFFMIS Tx FIFO full masked interrupt status.

0: TX FIFO is not full.
1: TX FIFO is full.

2 1 TXFNEMIS TX FIFO nearly empty masked interrupt status.

0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.
1: Number of entries in TX FIFO less than or equal to the TFTR:THRESHOLD_TX register.

1 1 TXFOVRMIS Tx FIFO overrun masked interrupt status.

0: No overrun condition occurred in TX FIFO.
1: Overrun condition occurred in TX FIFO.

3 1 WTSRMIS Write-to-Slave request masked interrupt status.

0: No write-to-slave request pending.
1: Write-to-slave request is pending.

18 1 RFR I2C receive FIFO register 0x18 8 read-only n 0x0 0x0 RDATA Receive data. RDATA contains the received payload, related to a master read or write-to-slave operation, to be read from the Rx FIFO. The RDATA(0) is the first LSB bit received over the I2C line. In case the FIFO is full, the I2C controller stretches automatically the I2C clock line until a new entry is available.

For a write-to-slave operation, when the slave is addressed, the interrupt I2C_RISR:WTSR bit is asserted for notification to the CPU. In CPU mode the FIFO management shall be based on the assertion of the interrupt bit I2C_RISR:RXFNF, related to the nearly-full threshold.

In DMA mode, the single requests are automatically executed based on the number of entries contained in the Rx FIFO.

0 8 RFTR I2C receive FIFO threshold register 0x20 16 read-write n 0x0 0x0 THRESH_RX Threshold RX, contains the threshold value, in terms of number of bytes, of the Rx FIFO.

When the number of entries of the RX FIFO is greater than or equal to the threshold value, the interrupt bit RISR:RXFNF is set in order to request the download of received data to the application. The application shall download the received data based on the threshold. (RISR:RXFNF).

0 10 RISR I2C raw interrupt status register 0x30 32 read-only n 0x0 0x0 BERR Bus Error. BERR is set when an unexpected Start/Stop condition occurs during a transaction. The related actions are different, depending on the type of operation in progress.The status code word in the SR contains a specific error tag (CAUSE field) for this error condition. This interrupt is cleared by setting the related bit of the ICR register.

0: No bus error detection.
1: Bus error detection.

25 1 LBR Length number of bytes received. LBR is set in case of MR or WTS and when the number of bytes received is equal to the transaction length programmed in the MCR:LENGTH (master mode) or SMB_SCR:LENGTH (slave mode). On the assertion of this interrupt and when the bit CR:FRC_STRTCH is set, the hardware starts clock stretching, the CPU shall download the data byte (Command code, Byte Count, Data...) from RX FIFO, re-set the expected length of the transaction in SMB_SCR:LENGTH and clear the interrupt. When clearing this interrupt the hardware continues the transfer. This interrupt is cleared by setting the related bit of the ICR register.

0: Length number of bytes is not received.
1: Length number of bytes is received.

15 1 MAL Master arbitration lost. MAL is set when the master loses the arbitration. The status code word in the SR contains a specific error tag (CAUSE field) for this error condition. A collision occurs when 2 stations transmit simultaneously 2 opposite values on the serial line. The station that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stops the transmission, leaves the bus and waits for the idle state (STOP condition received) on the bus line before retrying the same transaction. The station which transmits the first unique zero wins the bus arbitration. This interrupt is cleared by setting the related bit of the ICR register.

0: No master arbitration lost.
1: Master arbitration lost.

24 1 MTD Master Transaction done. MTD is set when a master operation (master write or master read) has been executed after a stop condition. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a master read operation) and clear this interrupt (transaction acknowledgment). A subsequent master operation can be issued (writing the MCR register) after the clearing of this interrupt. A subsequent slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I2C clock line will be stretched low. This interrupt is cleared by setting the related bit of the ICR register.

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment).

19 1 MTDWS Master transaction done without stop. MTDWS is set when a master operation (write or read) has been executed and a stop (MCR:P field) is not programmed. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a master read operation) and clear this interrupt (transaction acknowledgment). A subsequent master operation can be issued (by writing the MCR register) after clearing this interrupt. A subsequent slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I2C clock line will be stretched low. This interrupt is cleared by setting the related bit of the ICR register:

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment) and stop is not applied into the I2C bus.

28 1 RFSE Read-from-Slave empty. RFSE is set when a read-from-slave operation is in progress and TX FIFO is empty. On the assertion of this interrupt, the CPU shall download in TX FIFO the data required for the slave operation. This bit is self-cleared by writing in TX FIFO. At the end of the read-from-slave operation this bit is cleared although the TX FIFO is empty.

0: TX FIFO is not empty.
1: TX FIFO is empty with the read-from-slave operation in progress.

17 1 RFSR Read-from-slave request. RFSR is set when a read-from-slave "Slavetransmitter" request is received (I2C slave is addressed) from the I2C line. On the assertion of this interrupt the TX FIFO is flushed (pending data are cleared) and the CPU shall put the data in TX FIFO. This bit is self-cleared by writing data in FIFO. In case the FIFO is empty before the completion of the read operation, the RISR:RFSE interrupt bit is set.This interrupt is cleared by setting the related bit of the ICR register.

0: Read-from-slave request has been served.
1: Read-from-slave request is pending.

16 1 RXFE RX FIFO empty. RXFE is set when the RX FIFO is empty. This bit is self-cleared when the slave RX FIFO is not empty:

0: RX FIFO is not empty..
1: RX FIFO is empty..

4 1 RXFF RX FIFO full. RXFF is set when a full condition occurs in RX FIFO. This bit is self-cleared when the data are read from the RX FIFO.

0: RX FIFO is not full.
1: RX FIFO is full.

6 1 RXFNF RX FIFO nearly full. RXFNF is set when the number of entries in RX FIFO is greater than or equal to the threshold value programmed in the RFTR:THRESHOLD_RX register. Its self-cleared when the threshold level is under the programmed threshold:

0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.
1: Number of entries in the RX FIFO greater than or equal to the RFTR:THRESHOLD_RX register.

5 1 SAL Slave Arbitration lost. SAL is set when the slave loses the arbitration during the data phase. A collision occurs when 2 devices transmit simultaneously 2 opposite values on the serial data line. The device that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stops the transmission, releases the bus and waits for the idle state (STOP condition received) on the bus line. The device which transmits the first unique zero wins the bus arbitration. This interrupt is cleared by setting the related bit of the ICR register.

0: No slave arbitration lost.
1: Slave arbitration lost.

23 1 STD Slave Transaction done. STD is set when a slave operation (write-to-slave or read-from-slave) has been executed. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a write-to-slave operation) and clear this interrupt (transaction acknowledgment). A subsequent slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I2C clock line will be stretched low. A subsequent master operation can be issued (by writing the MCR register) after clearing this interrupt. This interrupt is cleared by setting the related bit of the ICR register:

0: Slave transaction acknowledged.
1: Slave transaction done (ready for acknowledgment).

20 1 TXFE TX FIFO empty. TXFE is set when TX FIFO is empty. This bit is self-cleared by writing in TX FIFO.

0: TX FIFO is not empty.
1: TX FIFO is empty.

0 1 TXFF TX FIFO full. TXFF is set when a full condition occurs in TX FIFO. This bit is self-cleared when the TX FIFO is not full:

0: TX FIFO is not full.
1: TX FIFO is full.

2 1 TXFNE TX FIFO nearly empty. TXFNE is set when the number of entries in TX FIFO is less than or equal to the threshold value programmed in the I2C_TFTR:THRESHOLD_TX register. It is self-cleared when the threshold level is over the programmed threshold.

0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.
1: Number of entries in TX FIFO less than or equal to the TFTR:THRESHOLD_TX register.

1 1 TXFOVR TX FIFO overrun. TXFOVR is set when a write operation in TX FIFO is performed and TX FIFO is full. The application must avoid an overflow condition by a proper data flow control. Anyway in case of overrun, the application shall flush the transmitter (CR:FTX bit to set) because the TX FIFO content is corrupted (at least one word has been lost in FIFO). This interrupt is cleared by setting the related bit of the ICR register:

0: No overrun condition occurred in TX FIFO.
1: Overrun condition occurred in TX FIFO.

3 1 WTSR Write-to-Slave request. WTSR is set when a write-to-slave operation is received (I2C slave is addressed) from the I2C line. This notification can be used by the application to program the DMA descriptor when required. This interrupt is cleared by setting the related bit of the ICR register:

0: No write-to-slave request pending.
1: Write-to-slave request is pending.

18 1 SCR I2C Slave Control register 0x4 32 read-write n 0x0 0x0 ESA10 Extended slave address 10-bit. ESA10 includes the extension (MSB bits) to the SA7 register field in case of slave addressing mode set to 10-bit 7 3 SA7 Slave address 7-bit. SA7 includes the slave address 7-bit or the LSB bits of the slave address 10-bit 0 7 SLSU Slave data setup time. SLSU defines the data setup time after SCL clock stretching in terms of i2c_clk cycles. Data setup time is actually equal to SLSU-1 clock cycles. The typical values for i2c_clk of 16 MHz are SLSU = 5 in standard mode and SLSU = 3 in fast modes. 16 16 SR I2C status register 0x14 32 read-only n 0x0 0x0 CAUSE Abort cause. This field is valid only when the STATUS field contains the ABORT tag. Others: RESERVED.

000b: NACK_ADDR: The master receives a not-acknowledge after the transmission of the address. Valid for the operation MW, MR.
001b: NACK_DATA: The master receives a not-acknowledge during the data phase of a MW operation. Valid for the operation MW.
011b: ARB_LOST: The master loses the arbitration during a MW or MR operation. Valid for the operation MW, MR.
100b: BERR_START: Slave restarts, a START Condition occurs while the byte transfer is not terminated.
101b: BERR_STOP: Slave reset, a STOP Condition while the byte transfer is not terminated.
110b: OVFL: The slave receives a frame related to the WTS operation longer than the maximum size = 2047 bytes. In this case the slave device returns a NACK to complete the data transfer. Valid for WTS operation

4 3 NACK_ADDR The master receives a not-acknowledge after the transmission of the address 0x00 NACK_DATA The master receives a not-acknowledge during the data phase of a MW operation 0x01 ARB_LOST The master loses the arbitration during a MW or MR operation 0x03 BERR_START Slave restarts, a START Condition occurs while the byte transfer is not terminated 0x04 BERR_STOP Slave reset, a STOP Condition while the byte transfer is not terminated 0x05 OVFL The slave receives a frame related to the WTS operation longer than the maximum size = 2047 bytes 0x06 DUALF Dual flag (slave mode):

0: Received address matched with slave address (SA7).
1: Received address matched with dual slave address (DSA7).

Cleared by hardware after a Stop condition or repeated Start condition, bus error or when PE=0. 29 1 DUAL_SLAVE_ADDR_OFF Received address matched with slave address (SA7) 0 DUAL_SLAVE_ADDR_ON Received address matched with dual slave address (DSA7) 1 LENGTH Transfer length. For an MR, WTS operation the LENGTH field defines the actual size of the subsequent payload, in terms of number of bytes. For an MW, RFS operation the LENGTH field defines the actual number of bytes transferred by the master/slave device. For a WTS operation if the transfer length exceeds 2047 bytes, the operation is stopped by the slave returning a NACK handshake and the flag OVFL is set. For an RFS operation if the transfer length exceeds 2047 bytes, the operation continues normally but the LENGTH field is reset to 0. 9 10 OP Operation:

00b: MW: master write operation.
01b: MR: master read operation.
10b: WTS: write-to-slave operation.
11b: RFS: read-from-slave operation.

0 2 MW Master write operation 0x00 MR Master read operation 0x01 WTS Write to slave operation 0x02 RFS Read from slave operation 0x03 STATUS Controller status. Valid for the operations MW, MR, WTS RFS:

00b: NOP: No operation is in progress.
01b: ON_GOING: An operation is ongoing.
10b: OK: The operation (OP field) has been completed successfully.
11b: ABORT: The operation (OP field) has been aborted due to the occurrence of the event described in the CAUSE field.

2 2 NOP No operation is in progress 0x00 ON_GOING An operation is ongoing 0x01 OK The operation (OP field) has been completed successfully 0x02 ABORT The operation (OP field) has been aborted due to the occurrence of the event descried in the CAUSE field 0x03 TYPE Receive type. Valid only for the operation WTS:

00b: FRAME: The slave has received a normal frame.
01b: GCALL: The slave has received a general call. If the it I2C_CR:SGCM is set to 1, the general call is directly executed without software intervention and only the control code word is reported in FIFO (LENGTH =0).
10b: HW_GCALL: The slave has received a hardware general call.

7 2 FRAME The slave has received a normal frame 0x00 GCALL The slave has received a general call 0x01 HW_GCALL The slave has received a hardware general call 0x02 TFR I2C transmit FIFO register 0x10 8 read-write n 0x0 0x0 TDATA Transmission Data. TDATA contains the payload related to a master write or read-from-slave operation to be written in the Tx FIFO. TDATA(0) is the first LSB bit transmitted over the I2C line.

In case of master write operation, the Tx FIFO shall be preloaded otherwise the I2C controller cannot start the operation until data are available.

In case of read-from-slave operation, when the slave is addressed, the interrupt RISR:RFSR bit is asserted and the CPU shall download the data in the FIFO. If the FIFO is empty and the I2C master is still requiring data, a new request (RISR:RFSE interrupt bit) is asserted to require additional data to the CPU. The slave controller stretches the I2C clock line when no data are available for transmission. Since the Tx FIFO could contain some pending data related to the previous transfer (the transfer length may be unknown to the slave controller), the Tx FIFO is self-flushed before asserting the I2C_RISR:RFSR bit. Upon completion of the read-from-slave operation the interrupt bit I2C_RISR:STD is asserted and the related status of the operation is stored in the I2C_SR register. In CPU mode, the FIFO management shall be based on the assertion of the interrupt bit RISR:TXFNE, related to the nearly-empty threshold.

In DMA mode, the single/burst requests are automatically executed based on the number of entries available in the TX FIFO and the related destination burst size programmed in the I2C_DMAR:DBSIZE_TX register field. The DMA requests are terminated at the end of the I2C read operation (notacknowledge received by the master) by a dummy last single/burst request.

0 8 TFTR I2C transmit FIFO threshold register 0x1C 16 read-write n 0x0 0x0 THRESH_TX Threshold TX, contains the threshold value, in terms of number of bytes, of the Tx FIFO.

When the number of entries of the Tx FIFO is less or equal than the threshold value, the interrupt bit I2C_RISR:TXFNE is set in order to request the loading of data to the application.

0 10 THDDAT I2C hold time data 0x4C 16 read-write n 0x0 0x0 THDDAT Hold time data value. In master or slave mode, when the I2C controller detects a falling edge in the SCL line, the counter, which is loaded by the THDDAT, is launched. Once the THDDAT value is reached, the data is transferred. 0 9 THDSTA_FST_STD I2C hold time start condition F/S 0x50 32 read-write n 0x0 0x0 THDSTA_FST Hold time start condition value for fast mode. When the start condition is asserted, the decimeter loads the value of THDSTA_FST for fast mode, once the THDSTA_FST value is reached, the SCL line assert slow. 16 9 THDSTA_STD Hold time start condition value for standard mode. When the start condition is asserted, the decimeter loads the value of THDSTA_STD for standard mode, once the THDSTA_STD value is reached, the SCL line asserts low. 0 9 TSUSTA_FST_STD I2C setup time start condition F/S 0x58 32 read-write n 0x0 0x0 TSUSTA_FST Setup time start condition value for fast mode. After a non-stop on the SCL line the decimeter loads the value of TSUSTA_FST according to fast mode. Once the counter is expired the start condition is generated. 16 9 TSUSTA_STD Setup time start condition value for standard mode. After a non-stop on the SCL line the decimeter loads the value of TSUSTA_STD according to standard mode. Once the counter is expired, the start condition is generated. 0 9 I2C2 I2C2 I2C 0x0 0x0 0x1000 registers n I2C2 I2C 2 interrupt 14 BRCR I2C Baud-rate counter register 0x28 16 read-write n 0x0 0x0 BRCNT Baud rate counter. BRCNT defines the counter value used to set up the I2C baud rate in standard and fast mode, when the peripheral is operating in master mode. 0 16 CR I2C Control register 0x0 32 read-write n 0x0 0x0 DMA_RX_EN Enables the DMA RX interface.

0: Idle state, the DMA RX interface is disabled.
1: Run state, the DMA RX interface is enabled.

0: Idle state, the DMA TX interface is disabled.
1: Run state, the DMA TX interface is enabled.

00b: No digital filters are inserted.
01b: Digital filters (filter 1 ck wide spikes) are inserted.
10b: Digital filters (filter 2 ck wide spikes) are inserted.
11b: Digital filters (filter 4 ck wide spikes) are inserted.

0: Flush operation is completed (I2C controller clears the bit).
1: Flush operation is started and in progress (set by application).

8 1 oneToSet FS_1 Force stop enable bit. When set to 1b, the STOP condition is generated.

0: Force stop disabled.
1: Enable force stop.

0: Flush operation is completed (I2C controller clears the bit).
1: Flush operation is started and in progress (set by application).

7 1 oneToSet OM Select the operating mode:

00b: Slave mode. The peripheral can only respond (transmit/receive) when addressed by a master device
01b: Master mode. The peripheral works in a multi-master system where itself cannot be addressed by another master device. It can only initiate a new transfer as master device.
10b: Master/slave mode. The peripheral works in a multi-master system where itself can be addressed by another master device, besides to initiate a transfer as master device.

0: I2C disable.
1: I2C enable.

0: 7-bit addressing mode.
1: 10-bit addressing mode.

0: transparent mode, the slave receiver recognizes the general call but any action is taken by the hardware after the decoding of the message included in the Rx FIFO.
1: direct mode, the slave receiver recognizes the general call and executes directly (without software intervention) the related actions. Only the status code word is stored in the I2C_SR register for notification to the application.

0: Standard mode (up to 100 K/s).
1: Fast mode (up to 400 K/s).

0: Single request mode. Transfers a single data (one byte) in the TX FIFO.
1: Burst request mode. Transfers a programmed burst of data according to DBSIZE_TX field.

0: Has no effect.
1: Clears interrupt pending.

25 1 LBRIC Length number of bytes received interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

15 1 MALIC Master Arbitration lost interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

24 1 MTDIC Master Transaction done interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

19 1 MTDWSIC Master Transaction done without stop interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

28 1 RFSEIC Read-from-Slave empty interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

17 1 RFSRIC Read-from-Slave request interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

16 1 SALIC Slave Arbitration lost interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

23 1 STDIC Slave Transaction done interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

20 1 TIMEOUTIC Timeout or Tlow error interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

30 1 TXFOVRIC Tx FIFO overrun interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

3 1 WTSRIC Write-to-Slave request interrupt clear.

0: Has no effect.
1: Clears interrupt pending.

18 1 IMSCR I2C interrupt mask set/clear register 0x2C 32 read-write n 0x0 0x0 BERRM Bus Error mask. BERRM enables the interrupt bit BERR:

0: BERR interrupt is disabled.
1: BERR interrupt is enabled.

25 MALM Master Arbitration lost mask. MALM enables the interrupt bit MAL:

0: MAL interrupt is disabled.
1: MAL interrupt is enabled.

24 MTDM Master Transaction done mask. MTDM enables the interrupt bit MTD:

0: MTD interrupt is disabled.
1: MTD interrupt is enabled.

19 MTDWSM Master Transaction done without stop mask. MTDWSM enables the interrupt bit MTDWS:

0: MTDWS interrupt is disabled.
1: MTDWS interrupt is enabled.

28 RFSEM Read-from-Slave empty mask. RFSEM enables the interrupt bit RFSE:

0: RFSE interrupt is disabled.
1: RFSE interrupt is enabled.

17 RFSRM Read-from-Slave request mask. RFSRM enables the interrupt bit RFSR:

0: RFSR interrupt is disabled.
1: RFSR interrupt is enabled.

16 RXFEM RX FIFO empty mask. RXFEM enables the interrupt bit RXFE:

0: RXFE interrupt is disabled.
1: RXFE interrupt is enabled.

4 RXFFM RX FIFO full mask. RXFFM enables the interrupt bit RXFF:

0: RXFF interrupt is disabled.
1: RXFF interrupt is enabled.

6 RXFNFM RX FIFO nearly full mask. RXNFM enables the interrupt bit RXNF:

0: RXNF interrupt is disabled.
1: RXNF interrupt is enabled

5 STDM Slave Transaction done mask. STDM enables the interrupt bit STD:

0: STDM interrupt is disabled.
1: STDM interrupt is enabled.

20 TXFEM TX FIFO empty mask. TXFEM enables the interrupt bit TXFE:

0: TXFE interrupt is disabled.
1: TXFE interrupt is enabled.

0 1 DISABLE Disable the interrupt mask 0 ENABLE Enable the interrupt mask 1 TXFFM TX FIFO full mask. TXFFM enables the interrupt bit TXFF:

0: TXFF interrupt is disabled.
1: TXFF interrupt is enabled.

2 TXFNEM TX FIFO nearly empty mask. TXFNEM enables the interrupt bit TXFNE:

0: TXFNE interrupt is disabled.
1: TXFNE interrupt is enabled.

1 TXFOVRM TX FIFO overrun mask. TXOVRM enables the interrupt bit TXOVR:

0: TXOVR interrupt is disabled.
1: TXOVR interrupt is enabled.

3 WTSRM Write-to-Slave request mask. WTSRM enables the interrupt bit WTSR:

0: WTSR interrupt is disabled.
1: WTSR interrupt is enabled.

00b: The transaction is initiated by a general call command. In this case the fields OP, A7, EA10 are "don't care".
01b: The transaction is initiated by the 7-bit address included in the A7 field.
10b: The transaction is initiated by the 10-bit address included in the EA10 and A7 fields.

0: Indicates a master write operation.
1: Indicates a master read operation.

0 1 MASTER_WRITE Indicates a master write operation 0x00 MASTER_READ Indicates a master read operation 0x01 P Stop condition:

0: The current transaction is not terminated by a STOP condition. A repeated START condition is generated on the next operation which is required to avoid to stall the I2C line.
1: The current transaction is terminated by a STOP condition.

14 1 SB Start byte:

0: The start byte procedure is not applied to the current transaction.
1: The start byte procedure is prefixed to the current transaction.

11 1 MISR I2C masked interrupt status register 0x34 32 read-only n 0x0 0x0 BERRMIS Bus Error masked interrupt status.

0: No bus error detection.
1: Bus error detection.

25 1 LBRMIS Length number of bytes received masked interrupt status.

0: Length number of bytes is not received.
1: Length number of bytes is received.

15 1 MALMIS Master Arbitration lost masked interrupt status.

0: No master arbitration lost.
1: Master arbitration lost.

24 1 MTDMIS Master Transaction done masked interrupt status.

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment).

19 1 MTDWSMIS Master Transaction done without stop masked interrupt status.

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment) and stop is not applied into the I2C bus.

28 1 RFSEMIS Read-from-Slave empty masked interrupt status.

0: TX FIFO is not empty.
1: TX FIFO is empty with the read-from-slave operation in progress.

17 1 RFSRMIS Read-from-Slave request masked interrupt status.

0: Read-from-slave request has been served.
1: Read-from-slave request is pending.

16 1 RXFEMIS RX FIFO empty masked interrupt status.

0: RX FIFO is not empty.
1: RX FIFO is empty..

4 1 RXFFMIS RX FIFO full masked interrupt status.

0: RX FIFO is not full.
1: RX FIFO is full.

6 1 RXFNFMIS RX FIFO nearly full masked interrupt status.

0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.
1: Number of entries in the RX FIFO greater than or equal to the RFTR:THRESHOLD_RX register.

5 1 SALMIS Slave Arbitration lost masked interrupt status.

0: No slave arbitration lost.
1: Slave arbitration lost.

23 1 STDMIS Slave Transaction done masked interrupt status.

0: Slave transaction acknowledged.
1: Slave transaction done (ready for acknowledgment).

20 1 TIMEOUTMIS Timeout or Tlow error masked interrupt status.

0: No timeout error.
1: SCL remained LOW for 25 ms (Timeout).

30 1 TXFEMIS TX FIFO empty masked interrupt status.

0: TX FIFO is not empty.
1: TX FIFO is empty.

0 1 TXFFMIS Tx FIFO full masked interrupt status.

0: TX FIFO is not full.
1: TX FIFO is full.

2 1 TXFNEMIS TX FIFO nearly empty masked interrupt status.

0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.
1: Number of entries in TX FIFO less than or equal to the TFTR:THRESHOLD_TX register.

1 1 TXFOVRMIS Tx FIFO overrun masked interrupt status.

0: No overrun condition occurred in TX FIFO.
1: Overrun condition occurred in TX FIFO.

3 1 WTSRMIS Write-to-Slave request masked interrupt status.

0: No write-to-slave request pending.
1: Write-to-slave request is pending.

In DMA mode, the single requests are automatically executed based on the number of entries contained in the Rx FIFO.

0 8 RFTR I2C receive FIFO threshold register 0x20 16 read-write n 0x0 0x0 THRESH_RX Threshold RX, contains the threshold value, in terms of number of bytes, of the Rx FIFO.

0: No bus error detection.
1: Bus error detection.

0: Length number of bytes is not received.
1: Length number of bytes is received.

0: No master arbitration lost.
1: Master arbitration lost.

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment).

0: Master transaction acknowledged.
1: Master transaction done (ready for acknowledgment) and stop is not applied into the I2C bus.

0: TX FIFO is not empty.
1: TX FIFO is empty with the read-from-slave operation in progress.

0: Read-from-slave request has been served.
1: Read-from-slave request is pending.

16 1 RXFE RX FIFO empty. RXFE is set when the RX FIFO is empty. This bit is self-cleared when the slave RX FIFO is not empty:

0: RX FIFO is not empty..
1: RX FIFO is empty..

4 1 RXFF RX FIFO full. RXFF is set when a full condition occurs in RX FIFO. This bit is self-cleared when the data are read from the RX FIFO.

0: RX FIFO is not full.
1: RX FIFO is full.

0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.
1: Number of entries in the RX FIFO greater than or equal to the RFTR:THRESHOLD_RX register.

0: No slave arbitration lost.
1: Slave arbitration lost.

0: Slave transaction acknowledged.
1: Slave transaction done (ready for acknowledgment).

20 1 TXFE TX FIFO empty. TXFE is set when TX FIFO is empty. This bit is self-cleared by writing in TX FIFO.

0: TX FIFO is not empty.
1: TX FIFO is empty.

0 1 TXFF TX FIFO full. TXFF is set when a full condition occurs in TX FIFO. This bit is self-cleared when the TX FIFO is not full:

0: TX FIFO is not full.
1: TX FIFO is full.

0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.
1: Number of entries in TX FIFO less than or equal to the TFTR:THRESHOLD_TX register.

0: No overrun condition occurred in TX FIFO.
1: Overrun condition occurred in TX FIFO.

0: No write-to-slave request pending.
1: Write-to-slave request is pending.

000b: NACK_ADDR: The master receives a not-acknowledge after the transmission of the address. Valid for the operation MW, MR.
001b: NACK_DATA: The master receives a not-acknowledge during the data phase of a MW operation. Valid for the operation MW.
011b: ARB_LOST: The master loses the arbitration during a MW or MR operation. Valid for the operation MW, MR.
100b: BERR_START: Slave restarts, a START Condition occurs while the byte transfer is not terminated.
101b: BERR_STOP: Slave reset, a STOP Condition while the byte transfer is not terminated.
110b: OVFL: The slave receives a frame related to the WTS operation longer than the maximum size = 2047 bytes. In this case the slave device returns a NACK to complete the data transfer. Valid for WTS operation

0: Received address matched with slave address (SA7).
1: Received address matched with dual slave address (DSA7).

00b: MW: master write operation.
01b: MR: master read operation.
10b: WTS: write-to-slave operation.
11b: RFS: read-from-slave operation.

00b: NOP: No operation is in progress.
01b: ON_GOING: An operation is ongoing.
10b: OK: The operation (OP field) has been completed successfully.
11b: ABORT: The operation (OP field) has been aborted due to the occurrence of the event described in the CAUSE field.

00b: FRAME: The slave has received a normal frame.
01b: GCALL: The slave has received a general call. If the it I2C_CR:SGCM is set to 1, the general call is directly executed without software intervention and only the control code word is reported in FIFO (LENGTH =0).
10b: HW_GCALL: The slave has received a hardware general call.

In case of master write operation, the Tx FIFO shall be preloaded otherwise the I2C controller cannot start the operation until data are available.

0 8 TFTR I2C transmit FIFO threshold register 0x1C 16 read-write n 0x0 0x0 THRESH_TX Threshold TX, contains the threshold value, in terms of number of bytes, of the Tx FIFO.

When the number of entries of the Tx FIFO is less or equal than the threshold value, the interrupt bit I2C_RISR:TXFNE is set in order to request the loading of data to the application.

0 10 THDDAT I2C hold time data 0x4C 16 read-write n 0x0 0x0 THDDAT Hold time data value. In master or slave mode, when the I2C controller detects a falling edge in the SCL line, the counter, which is loaded by the THDDAT, is launched. Once the THDDAT value is reached, the data is transferred. 0 9 THDSTA_FST_STD I2C hold time start condition F/S 0x50 32 read-write n 0x0 0x0 THDSTA_FST Hold time start condition value for fast mode. When the start condition is asserted, the decimeter loads the value of THDSTA_FST for fast mode, once the THDSTA_FST value is reached, the SCL line assert slow. 16 9 THDSTA_STD Hold time start condition value for standard mode. When the start condition is asserted, the decimeter loads the value of THDSTA_STD for standard mode, once the THDSTA_STD value is reached, the SCL line asserts low. 0 9 TSUSTA_FST_STD I2C setup time start condition F/S 0x58 32 read-write n 0x0 0x0 TSUSTA_FST Setup time start condition value for fast mode. After a non-stop on the SCL line the decimeter loads the value of TSUSTA_FST according to fast mode. Once the counter is expired the start condition is generated. 16 9 TSUSTA_STD Setup time start condition value for standard mode. After a non-stop on the SCL line the decimeter loads the value of TSUSTA_STD according to standard mode. Once the counter is expired, the start condition is generated. 0 9 MFT1 MFT1 MFTX 0x0 0x0 0x1000 registers n MFT1A Multi functional timer MFT1 interrupt A 17 MFT1B Multi functional timer MFT1 interrupt B 18 TNCKC Clock unit control register 0x14 8 read-write n 0x0 0x0 TNC1CSEL Define the clock mode for timer/counter 1:

000b: No clock (Timer/Counter 1 stopped).
001b: Prescaled system clock.
010b: External event on TnB (mode 1 and 3 only).
011b: Pulse accumulate (mode 1 and 3 only).
100b: Low-speed clock.

0 3 NO_CLOCK No clock (Timer/Counter 1 stopped) 0 PRESCALED Prescaled system clock pclk 1 EXTERNAL_EVENT External event on TnB 2 PULSE_ACCUMULATE Pulse accumulate 3 LOW_SPEED_CLOCK Low-speed clock slow_clk_c 4 TNC2CSEL Define the clock mode for timer/counter 2:

000b: No clock (Timer/Counter 1 stopped).
001b: Prescaled system clock.
010b: External event on TnB (mode 1 and 3 only).
011b: Pulse accumulate (mode 1 and 3 only).
100b: Low-speed clock.

3 3 TNCNT1 Timer / Counter1 register 0x0 16 read-write n 0x0 0x0 TNCNT2 Timer / Counter2 register 0xC 16 read-write n 0x0 0x0 TNCRA Capture / Reload A register 0x4 16 read-write n 0x0 0x0 TNCRB Capture / Reload B register 0x8 16 read-write n 0x0 0x0 TNICLR Timer interrupt clear register 0x20 8 write-only n 0x0 0x0 TNACLR Clear timer interrupt source A. 0 1 TNBCLR Clear timer interrupt source B. 1 1 TNCCLR Clear timer interrupt source C. 2 1 TNDCLR Clear timer interrupt source D. 3 1 TNICTRL Timer interrupt control register 0x1C 8 read-write n 0x0 0x0 TNAIEN Timer interrupt A enable:

0: Interrupt disabled.
1: Interrupt enabled.

4 1 TNAPND Timer interrupt A pending:

0: No interrupt source pending.
1: Interrupt source pending.

0 1 read-only TNBIEN Timer interrupt B enable:

0: Interrupt disabled.
1: Interrupt enabled.

5 1 TNBPND Timer interrupt B pending:

0: No interrupt source pending.
1: Interrupt source pending.

1 1 read-only TNCIEN Timer interrupt C enable:

0: Interrupt disabled.
1: Interrupt enabled.

6 1 TNCPND Timer interrupt C pending:

0: No interrupt source pending.
1: Interrupt source pending.

2 1 read-only TNDIEN Timer interrupt D enable:

0: Interrupt disabled.
1: Interrupt enabled.

7 1 TNDPND Timer interrupt D pending:

0: No interrupt source pending.
1: Interrupt source pending.

3 1 read-only TNMCTRL Timer mode control register 0x18 16 read-write n 0x0 0x0 TNAEDG TnA edge polarity:

0: Input is sensitive to falling edges.
1: Input is sensitive to rising edges.

2 1 FALLING_EDGE Input is sensitive to falling edges 0 RISING_EDGE Input is sensitive to rising edges 1 TNAEN TnA enable:

0: TnA in disable.
1: TnA in enable.

4 1 TNA_IN_DISABLE TnA in disable 0 TNA_IN_ENABLE TnA in enable 1 TNAOUT TnA output data:

0: Pin is low.
1: Pin is high.

6 1 LOW Pin is low 0 HIGH Pin is high 1 TNBEDG TnB edge polarity:

0: Input is sensitive to falling edges.
1: Input is sensitive to rising edges.

3 1 TNBEN TnB enable:

0: TnB in disable.
1: TnB in enable.

5 1 TNB_IN_DISABLE TNB in disable 0 TNB_IN_ENABLE TNB in enable 1 TNEN MFTX enable:

0: MFTX disable.
1: MFTX enable.

7 1 MFTX_DISABLE MFTX disable 0 MFTX_ENABLE MFTX enable 1 TNMDSEL MFTX mode select:

00b: Mode 1 or 1a: PWM mode and system timer or pulse train.
01b: Mode 2: Dual-input capture and system timer.
10b: Mode 3: Dual independent timer/counter.
11b: Mode 4: Single timer and single input capture.

0 2 PWM PWM mode and system timer or pulse train 0 DUAL_INPUT_CAPTURE Dual-input capture and system timer 1 DUAL_INDEPENDENT Dual independent timer/counter 2 SINGLE Single timer and single input capture 3 TNPTEN Tn pulse-train mode enable:

0: Mode 1a not selected.
1: Mode 1a selected (if TnMDSEL = 00).

8 1 TNPTET Tn pulse-train event trigger:

0: No pulse-train event trigger occurred.
1: Pulse-train event trigger occurred (in mode 1a).

10 1 TNPTSE Tn pulse-train sofware trigger enable:

0: No effect.
1: Pulse-train generation trigger (in mode 1a)

9 1 TNPRSC Clock prescaler register 0x10 8 read-write n 0x0 0x0 MFT2 MFT1 MFTX 0x0 0x0 0x1000 registers n MFT2A Multi functional timer MFT2 interrupt A 19 MFT2B Multi functional timer MFT2 interrupt B 20 TNCKC Clock unit control register 0x14 8 read-write n 0x0 0x0 TNC1CSEL Define the clock mode for timer/counter 1:

000b: No clock (Timer/Counter 1 stopped).
001b: Prescaled system clock.
010b: External event on TnB (mode 1 and 3 only).
011b: Pulse accumulate (mode 1 and 3 only).
100b: Low-speed clock.

000b: No clock (Timer/Counter 1 stopped).
001b: Prescaled system clock.
010b: External event on TnB (mode 1 and 3 only).
011b: Pulse accumulate (mode 1 and 3 only).
100b: Low-speed clock.

0: Interrupt disabled.
1: Interrupt enabled.

4 1 TNAPND Timer interrupt A pending:

0: No interrupt source pending.
1: Interrupt source pending.

0 1 read-only TNBIEN Timer interrupt B enable:

0: Interrupt disabled.
1: Interrupt enabled.

5 1 TNBPND Timer interrupt B pending:

0: No interrupt source pending.
1: Interrupt source pending.

1 1 read-only TNCIEN Timer interrupt C enable:

0: Interrupt disabled.
1: Interrupt enabled.

6 1 TNCPND Timer interrupt C pending:

0: No interrupt source pending.
1: Interrupt source pending.

2 1 read-only TNDIEN Timer interrupt D enable:

0: Interrupt disabled.
1: Interrupt enabled.

7 1 TNDPND Timer interrupt D pending:

0: No interrupt source pending.
1: Interrupt source pending.

3 1 read-only TNMCTRL Timer mode control register 0x18 16 read-write n 0x0 0x0 TNAEDG TnA edge polarity:

0: Input is sensitive to falling edges.
1: Input is sensitive to rising edges.

2 1 FALLING_EDGE Input is sensitive to falling edges 0 RISING_EDGE Input is sensitive to rising edges 1 TNAEN TnA enable:

0: TnA in disable.
1: TnA in enable.

4 1 TNA_IN_DISABLE TnA in disable 0 TNA_IN_ENABLE TnA in enable 1 TNAOUT TnA output data:

0: Pin is low.
1: Pin is high.

6 1 LOW Pin is low 0 HIGH Pin is high 1 TNBEDG TnB edge polarity:

0: Input is sensitive to falling edges.
1: Input is sensitive to rising edges.

3 1 TNBEN TnB enable:

0: TnB in disable.
1: TnB in enable.

5 1 TNB_IN_DISABLE TNB in disable 0 TNB_IN_ENABLE TNB in enable 1 TNEN MFTX enable:

0: MFTX disable.
1: MFTX enable.

7 1 MFTX_DISABLE MFTX disable 0 MFTX_ENABLE MFTX enable 1 TNMDSEL MFTX mode select:

00b: Mode 1 or 1a: PWM mode and system timer or pulse train.
01b: Mode 2: Dual-input capture and system timer.
10b: Mode 3: Dual independent timer/counter.
11b: Mode 4: Single timer and single input capture.

0: Mode 1a not selected.
1: Mode 1a selected (if TnMDSEL = 00).

8 1 TNPTET Tn pulse-train event trigger:

0: No pulse-train event trigger occurred.
1: Pulse-train event trigger occurred (in mode 1a).

10 1 TNPTSE Tn pulse-train sofware trigger enable:

0: No effect.
1: Pulse-train generation trigger (in mode 1a)

9 1 TNPRSC Clock prescaler register 0x10 8 read-write n 0x0 0x0 PKA PKA PKA 0x0 0x0 0x1000 registers n PKA PKA interrupt 22 RNG RNG RNG 0x0 0x0 0x1000 registers n CR RNG configuration register 0x0 32 read-write n 0x0 0x0 DIS Set the state of the random number generator.

0: RNG is enable.
1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block.

2 1 read-write TST_CLK RNG test clock bit. Writing this bit with 1b starts the logic that detects the presence of the CLK. Then wait (with a timeout of at least four RNGCLK cycles) for REVCLK = 1b in SR register. If REVCLK = 0b after timeout elapsed, it means that RNGCLK is not present and reading VAL register will trigger an AHB error response. For security reason, software should check before reading random values that the RNGCLK is present. 3 1 read-write SR RNG status register 0x4 32 read-only n 0x0 0x0 FAULT Fault reveal bit. This bit is set by hardware when a faulty sequence of bits occurs. The faulty sequences are:

0: Sequence of more than 32 consecutive bits of same value (0b or 1b).
1: Sequence of more than 16 consecutive alternation of 0b and 1b (010101...01b).

Writing this bit:

0: No effect.
1: Clear the bit.

2 1 read-write RDY New random value ready.

0: The RNG_VAL register value is not yet valid. If performing a read access to VAL, the host will be put on hold (by wait-states insertion on the AHB bus) until a random value is available.
1: The VAL register contains a valid random number.

This bit remains at 0 when the RNG is disabled (RNGDIS bit = 1b in CR) 0 1 read-only REVCLK REVCLK clock reveal bit. A write with 1b to bit TSTCLK in CR resets this bit. If the RNGCLK is present, this bit will be 1b after four RNGCLK cycles after the end of the write to RNG_CR.If REVCLK = 0b after this period, it means the RNGCLK is not present and reading VAL will trigger a AHB error response. 1 1 read-write VAL RNG 16 bit random value 0x8 32 read-only n 0x0 0x0 RTC Real-Time Counter TIMER 0x0 0x0 0x1000 registers n RTC RTC interrupt 21 CTCR Control Trim and Counter Register 0x18 32 read-write n 0x0 0x0 CKDEL Trim delete count. This value represents the number of CLK32K clock pulses to delete every 1023 CLK32K clock cycles to get a better reference 1 Hz clock for incrementing the RTC counter.

0x000: No CLK32K clock cycle is deleted every 1023 CLK1HZ clock cycles (default value after PORn reset).
0x001: 1 CLK32K clock cycle is deleted every 1023 CLK1HZ clock cycles.
...
0x3FF: 1023 CLK32K clock cycles are deleted every 1023 CLK1HZ clock cycles.

Writing to this bit-field will be disregarded if CWEN = 1. A read returns the value of the CKDEL bit-field. 16 10 CKDIV Clock divider factor. This value plus one represents the integer part of the CLK32K clock divider used to produce the reference 1 Hz clock.

0x000: CLK1HZ clock is similar to CLK32K for RTC timer and stopped for RTC clockwatch.
0x0001: 2 CLK32K clock cycles per CLK1HZ clock cycle.
...
0x7FFF: 32768 CLK32K clock cycles per CLK1HZ clock cycle (default value after PORn reset).
...
0xFFFF: CLK32K clock cycles per CLK1HZ clock cycle.

Writing to this bit-field will be disregarded if CWEN = 1. A read returns the value of the CKDIV bit-field. 0 15 CWEN Clockwatch enable bit. When set to 1, the clockwatch is enabled. Once it is enabled, any write to this register has no effect until a power-on reset. A read returns the value of the CWEN bit value. 26 1 CWDLR Clockwatch Data Load Register 0x8 32 read-write n 0x0 0x0 CWDAYML RTC clockwatch day of month load value. 1 to 28/29/30 or 31 depending on month:

1 to 28: February month, non-leap year.
1 to 29: February month, leap year.
1 to 30: April, June, September, November month.
1 to 31: January, March, May, August, October, December month.
Other values must not be used.

20 5 CWDAYWL RTC clockwatch day of week load value. Clockwatch day of week:

000b: Must not be used.
001b: Sunday.
010b: Monday.
011b: Tuesday.
100b: Wednesday.
101b: Thursday.
110b: Friday.
111b: Saturday.

17 3 CWHOURL RTC clockwatch hour load value. Clockwatch hours from 0 to 23 (0x17). Other values must not be used. 12 5 CWMINL RTC clockwatch minute load value. Clockwatch minutes from 0 to 59 (0x3B). Other values must not be used. 6 6 CWMONTHL RTC clockwatch month load value:

0001b: January.
...
1100: December.

Other values must not be used. 25 4 CWSECL RTC clockwatch second load value. Clockwatch seconds from 0 to 59 (0x3B). Other values must not be used. 0 6 CWDMR Clockwatch Data Match Register 0x4 32 read-write n 0x0 0x0 CWDAYMM RTC clockwatch day of month match value:

0000b: (month is don't care in the comparison. Default value after PORn).
1 to 31: day of month match value.

20 5 CWDAYWM RTC clockwatch day of week match value:

000b: day of week is don't care in the comparison. (Default value after PORn).
001b to 111b: (1 to 7) day of week match value.

17 3 CWHOURM RTC clockwatch hour match value:

00000b to 10111b: (0 to 23 or 0x00 to 0x17) hour match value.
11000b to 11111b - (24 to 31 or 0x18 to 0x1F).

Non-valid data, match never occurs. 12 5 CWMINM RTC clockwatch minute match value:

00 0000 to 11 1011: (0 to 59 or 0x00 to 0x3B) clockwatch minutes.
11 1100 to 11 1111 - (60 to 63 or 0x3C to 0x3F).

Non-valid data, match never occurs. 6 6 CWMONTHM RTC clockwatch month match value:

0000b: (day of month is don't care in the comparison. Default value after PORn).
0001b to 1100b: (1 to 12) month match value.
1101b (13, 0xD) to 1111b (0xF) non-valid data, match never occurs.

25 4 CWSECM RTC clockwatch second match value:

00 0000 to 11 1011: (0 to 59 or 0x00 to 0x3B) clockwatch seconds.
11 1100 to 11 1111 - (60 to 63 or 0x3C to 0x3F).

Non-valid data, match never occurs. 0 6 CWDR Clockwatch Data Register 0x0 32 read-only n 0x0 0x0 CWDAYM RTC clockwatch day of month value: 1 to 28/29/30 or 31. Range of value to program depends on the month:

1 to 28: February month, non-leap year.
1 to 29: February month, leap year.
1 to 30: April, June, September, November month.
1 to 31: January, March, May, August, October, December month.

20 5 CWDAYW RTC clockwatch day of week value. Clockwatch day of week:

001b: Sunday.
010b: Monday.
011b: Tuesday.
100b: Wednesday.
101b: Thursday.
110b: Friday.
111b: Saturday.

17 3 CWHOUR RTC clockwatch hour value. Clockwatch seconds: 0 to 23 (max 0x17). 12 5 CWMIN RTC clockwatch minute value. Clockwatch seconds: 0 to 59 (max 0x3B). 6 6 CWMONTH RTC clockwatch month value:

0001b: January.
...
1100: December.

25 4 CWSEC RTC clockwatch second value. Clockwatch seconds: 0 to 59 (max 0x3B). 0 6 CWYLR Clockwatch Year Load Register 0x14 16 read-write n 0x0 0x0 CWYEARL RTC clockwatch year load value. Clockwatch year load value is in BCD format from 0 to 3999. 0 14 CWYMR Clockwatch Year Match Register 0x10 16 read-write n 0x0 0x0 CWYEARM RTC clockwatch year match value. Clockwatch year match value is in BCD format from 0 to 3999. 0 14 CWYR Clockwatch Year Register 0xC 16 read-only n 0x0 0x0 CWYEAR RTC clockwatch year value. Clockwatch year, in BCD format is from 0 to 3999. 0 14 ICR RTC interrupt clear register 0x28 8 write-only n 0x0 0x0 oneToClear TIC RTC timer interrupt clear register bit. Clears the RTC timer interrupt TINTR.

0: No effect.
1: Clears the interrupt.

1 1 WIC RTC clock watch interrupt clear register bit. Clears the RTC clock watch interrupt WINTR.

0: No effect.
1: Clears the interrupt.

0 1 IMSC RTC interrupt mask register 0x1C 8 read-write n 0x0 0x0 TIMSC RTC timer interrupt enable bit:

When set to 0, sets the mask for RTC timer interrupt (default after PORn reset). The interrupt is disabled.
When set to 1, clears this mask and enables the interrupt.

1 1 WIMSC RTC clock watch interrupt enable bit:

When set to 0, clears the interrupt mask (default after PORn reset). The interrupt is disabled.
When set to 1, the interrupt for RTC clockwatch interrupt is enabled.

0 1 MIS RTC masked interrupt status register 0x24 8 read-only n 0x0 0x0 TMIS RTC timer interrupt status bit. Gives the masked interrupt status (after masking) of the RTC timer interrupt TINTR. 1 1 WMIS RTC clock watch interrupt status bit. Gives the masked interrupt status (after masking) of the RTC clock watch interrupt WINTR. 0 1 RIS RTC raw interrupt status register 0x20 8 read-only n 0x0 0x0 TRIS RTC timer raw interrupt status bit. Gives the raw interrupt state (prior to masking) of the RTC timer interrupt. 1 1 WRIS RTC clock watch raw interrupt status bit. Gives the raw interrupt state (prior to masking) of the RTC clock watch interrupt. 0 1 TCR RTC timer control register 0x30 16 read-write n 0x0 0x0 BYPASS_GATED Enable or disable the internal clock gating:

0: The internal clock gating is activated.
1: No clock gating, clock is always enabled.

12 1 CLK RTC Timer clock.

0: The RTC timer is clocked by CLK32K.
1: The RTC timer is clocked by the trimmed clock.

11 1 KHZ32_CLK RTC timer is clocked by CLK32K 0 TRIMMED_CLK RTC timer is clocked by the trimmed clock 1 EN RTC Timer enable bit.

0: The RTC timer is stopped on the next CLK32K cycle.
1: The RTC timer is enabled on the next CLK32K cycle.

When the RTC timer is stopped, the content of the counter is frozen. A read returns the value of the EN bit. This bit set by hardware when the TLR register is written to while the counter is stopped. When the device is active, this bit is cleared by hardware when the counter reaches zero in one-shot mode. 1 1 OS RTC Timer one shot count.

0: Periodic mode (default). When reaching zero, the RTC timer raises its interrupt and is reloaded from the LD content.
1: One-shot mode. When reaching zero, the RTC timer raise its interrupt and stops.

0 1 S RTC Timer self start bit. When written to 1b, each write in a load register or a pattern will set EN to 1b, so, start the counter in the next CLK32K cycle. 2 1 SP RTC Timer Pattern size. Number of pattern bits crossed by the pointer. It defines the useful pattern size. 4 7 TDR RTC timer load value 0x2C 32 read-only n 0x0 0x0 TIN RTC Timer Interrupt Number Register 0x4C 32 read-write n 0x0 0x0 TLR1 RTC Timer first Load Register 0x34 32 read-write n 0x0 0x0 TLR2 RTC Timer second Load Register 0x38 32 read-write n 0x0 0x0 TPR1 RTC Timer Pattern Register (pattern[31:0]) 0x3C 32 read-write n 0x0 0x0 TPR2 RTC Timer Pattern Register (pattern[63:32]) 0x40 32 read-write n 0x0 0x0 TPR3 RTC Timer Pattern Register (pattern[95:64]) 0x44 32 read-write n 0x0 0x0 TPR4 RTC Timer Pattern Register (pattern[127:96]) 0x48 32 read-write n 0x0 0x0 SPI Serial peripheral interface SPI 0x0 0x0 0x1000 registers n SPI SPI interrupt 5 CHN Dummy character register 0x2C 32 read-write n 0x0 0x0 CPSR Clock prescale register 0x10 8 read-write n 0x0 0x0 CPSDVSR Clock prescale divisor.It must be an even number from 2 to 254. The value is used to generate the transmit and receive bit rate of the SPI. The bit rate is:

FSSPCLK / [CPSDVR x (1+SCR)]

where SCR is a value from 0 to 255, programmed through the SSP_CR0 register. 0 8 CR0 Control Register 0 0x0 32 read-write n 0x0 0x0 CS1 Chip Selection for slave one

0: the slave 1 is selected.
1: the slave 1 is not selected.

26 1 CS1_NOT_SELECT Slave 1 is select 0 CS1_SELECT Slave 1 is not select 1 DSS Data size select. (DSS+1) defines the number of bits:

0x00: Reserved.
0x01: Reserved.
0x02: Reserved.
0x03: 4-bit data.
0x04: 5-bit data.
...
0x1F: 32-bit data.

0 5 DATA_11BIT 11-bit data 10 DATA_12BIT 12-bit data 11 DATA_13BIT 13-bit data 12 DATA_14BIT 14-bit data 13 DATA_15BIT 15-bit data 14 DATA_16BIT 16-bit data 15 DATA_17BIT 17-bit data 16 DATA_18BIT 18-bit data 17 DATA_19BIT 19-bit data 18 DATA_20BIT 20-bit data 19 DATA_21BIT 21-bit data 20 DATA_22BIT 22-bit data 21 DATA_23BIT 23-bit data 22 DATA_24BIT 24-bit data 23 DATA_25BIT 25-bit data 24 DATA_26BIT 26-bit data 25 DATA_27BIT 27-bit data 26 DATA_28BIT 28-bit data 27 DATA_29BIT 29-bit data 28 DATA_30BIT 30-bit data 29 DATA_4BIT 4-bit data 3 DATA_31BIT 31-bit data 30 DATA_32BIT 32-bit data 31 DATA_5BIT 5-bit data 4 DATA_6BIT 6-bit data 5 DATA_7BIT 7-bit data 6 DATA_8BIT 8-bit data 7 DATA_9BIT 9-bit data 8 DATA_10BIT 10-bit data 9 INVCLK Activate inversion (in master mode only).

0: Master samples the received data respecting the Motorola SPI protocol.
1: The sampling of the received data by master is delayed by half an SPI clock cycle..

25 1 SCR Serial Clock Rate.

The SRC value is used to generate the transmit and receive bit rate of the SPI. The bit rate is: f_SPICLK / (CPSDVR * (1 + SCR)), where CPSDVR is an even value from 2 to 254 and SCR is a value from 0 to 255.

8 8 SPH Clock phase.

0: Steady state of clock phase is low.
1: Steady state of clock phase is high.

7 1 PHASE_0 Received data is captured on the rising edge (SPO=0) or on the falling edge (SPO=1) of SSPCLKO. Transmitted data is sent on the falling edge (SPO=0) or on the rising edge (SPO=1) of SSPCLKO 0 PHASE_1 Received data is captured on the falling edge (SPO=0) or on the rising edge (SPO=1) of SSPCLKO.Transmitted data is sent on the rising edge (SPO=0) or on the falling edge (SPO=1) of SSPCLKO 1 SPIM SPI transmission mode.

00b: Full duplex mode.
01b: Transmit mode.
10b: Receive mode.
11b: Combined mode.

23 2 FULL_DUPLEX SPI is configured in full duplex mode 0 TRANSMIT SPI is configured in transmit mode 1 RECEIVE SPI is configured in receive mode 2 COMBINED SPI is configured in combined mode 3 SPO Clock polarity.

0: Steady state of clock polarity is low.
1: Steady state of clock polarity is high.

6 1 INACTIVE_LOW The inactive or idle state of SSPCLKO is LOW 0 INACTIVE_HIGH The inactive or idle state of SSPCLKO is HIGH 1 CR1 Control Register 1 0x4 32 read-write n 0x0 0x0 DATAINDEL Data input delay.

0: No delay is inserted in data input.
1: A delay of 2 clock cycles is inserted in the data input path.

21 1 FLOWCTRLEN Flow Control Enable.

0: Flow control is disabled.
1: Flow control is enabled.

13 1 DISABLE Flow control disable 0 ENABLE Flow control enable 1 MS Master or slave mode select.

0: Master mode.
1: Slave mode.

2 1 MASTER Master mode 0 SLAVE Slave mode 1 MSPIWAIT SPI Wait mode. This value is used to insert a wait state between frames. 14 4 RENDN Receive endian format.

00b: The element is received MSByte-first and MSbit-first.
01b: The element is received LSByte-first and MSbit-first.
10b: The element is received MSByte-first and LSbit-first.
11b: The element is received LSByte-first and LSbit-first.

The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits. 4 2 MSB_FIRST_MSB_FIRST The element is received MSByte-first and MSbit-first 0 LSB_FIRST_MSB_FIRST The element is received LSByte-first and MSbit-first 1 MSB_FIRST_LSB_FIRST The element is received MSByte-first and LSbit-first 2 LSB_FIRST_LSB_FIRST The element is received LSByte-first and LSbit-first 3 RXIFLSEL Receive interrupt FIFO level select. This bit field selects the trigger points to receive FIFO interrupt:

000b: RX FIFO contains 1 element or more.
001b: RX FIFO contains 4 elements or more.
010b: RX FIFO contains 8 elements or more.
Others: Reserved.

7 3 MIN_1ELEMENT Rx FIFO contains 1 element or more 0 MIN_4ELEMENTS Rx FIFO contains 4 elements or more 1 MIN_8ELEMENTS Rx FIFO contains 8 elements or more 2 SOD Slave mode output disable (slave mode only).

0: SPI can drive the MISO signal in slave mode.
1: SPI must not drive the MISO signal in slave mode.

In multiple slave system, it is possible for a SPI master to broadcast a message to all slaves in the system while ensuring only one slave drives data onto the serial output line MISO. 3 1 SSE SPI enable.

0: SPI disable.
1: SPI enable.

1 1 DISABLE SSP operation disable 0 ENABLE SSP operation enable 1 TENDN Transmit endian format.

00b: The element is transmitted MSByte-first and MSbit-first.
01b: The element is transmitted LSByte-first and MSbit-first.
10b: The element is transmitted MSByte-first and LSbit-first.
11b: The element is transmitted LSByte-first and LSbit-first.

The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits. 18 2 TXIFLSEL Transmit interrupt FIFO level select. This bit field selects the trigger points to transmit FIFO interrupt:

000b: TX FIFO contains 1 element or more.
001b: TX FIFO contains 4 elements or more.
010b: TX FIFO contains 8 elements or more.
Others: Reserved.

10 3 MIN_1ELEMENT Tx FIFO contains 1 element or more 0 MIN_4ELEMENTS Tx FIFO contains 4 elements or more 1 MIN_8ELEMENTS Tx FIFO contains 8 elements or more 2 DMACR SPI DMA control register 0x24 8 read-write n 0x0 0x0 RXDMASE Single receive DMA request.

0: Single transfer DMA in receive disable.
1: Single transfer DMA in receive enable.

0 1 RX_DMA_DISABLE Single transfer DMA in receive disable 0 RX_DMA_ENABLE Single transfer DMA in receive enable 1 TXDMASE Signle transmit DMA request.

0: Single transfer DMA in transmit disable.
1: Single transfer DMA in transmit enable.

2 1 TX_DMA_DISABLE Single transfer DMA in transmit disable 0 TX_DMA_ENABLE Single transfer DMA in transmit enable 1 DR Data Register 0x8 32 read-write n 0x0 0x0 DATA Transmit/Receive data:

Read: RX FIFO is read.
Write: TX FIFO is written.

Data must be right-justified when a data size of less than 32-bit is programmed. Unused bits are ignored by the transmit logic. The receive logic automatically right-justifies data. 0 32 ICR Interrupt clear register 0x20 8 write-only n 0x0 0x0 oneToClear RORIC Receive Overrun Clear Interrupt: writing 1 clears the receive overrun interrupt. 0 1 RTIC Receive Time Out Clear Interrupt: writing 1 clears the receive timeout interrupt. 1 1 TURIC Transmit Underrun Clear Interrupt: writing 1 clears the transmit overrun interrupt. 2 1 IMSC Interrupt mask set or clear register 0x14 8 read-write n 0x0 0x0 RORIM Receive overrun interrupt mask:

0: RX FIFO written to while full condition interrupt is masked (irq disabled).
1: RX FIFO written to while full condition interrupt is not masked (irq enabled).

0 1 IRQ_DISABLE irq disable 0 IRQ_ENABLE irq enable 1 RTIM Receive timeout interrupt mask:

0: RX FIFO not empty or no read prior to the timeout period interrupt is masked (irq disabled).
1: RX FIFO not empty or no read prior to the timeout period interrupt is not masked (irq enabled).

1 1 RXIM Receive FIFO interrupt mask:

0: Receive interrupt is masked (irq disabled).
1: Receive interrupt is not masked (irq enabled).

2 1 TEIM Transmit FIFO empty interrupt mask:

0: TX FIFO empty interrupt is masked (irq disabled).
1: TX FIFO empty interrupt is not masked (irq enabled).

5 1 TURIM Transmit underrun interrupt mask:

0: Transmit underrun interrupt is masked (irq disabled).
1: Transmit underrun interrupt is not masked (irq enabled).

4 1 TXIM Transmit FIFO interrupt mask:

0: Transmit interrupt is masked (irq disabled).
1: Transmit interrupt is not masked (irq enabled).

3 1 ITCR Integration test control register 0x80 8 read-write n 0x0 0x0 SWAPFIFO FIFO control mode:

0: FIFO normal mode. Write in TDR register puts data in TX FIFO and read from TDR register read data from RX FIFO.
1: FIFO swapped mode. Write in TDR register puts data in RX FIFO and read from TDR register read data from TX FIFO.

1 1 FIFO_NORMAL_MODE FIFO normal mode 0 FIFO_TEST_MODE FIFO test mode 1 MIS Masked Interrupt Status Register 0x1C 8 read-only n 0x0 0x0 RORMIS Receive Overrun Masked Interrupt Status: gives the interrupt status after masking of the receive overrun interrupt. 0 1 RTMIS Receive Time Out Masked Interrupt Status: gives the interrupt status after masking of receive timeout interrupt. 1 1 RXMIS Receive Masked Interrupt Status: gives the interrupt status after masking of the receive interrupt. 2 1 TEMIS Transmit FIFO Empty Masked Interrupt Status: gives the interrupt status after masking of the transmit FIFO empty interrupt. 5 1 TURMIS Transmit Underrun Masked Interrupt Status: gives the interrupt status after masking of the transmit underrun interrupt. 4 1 TXMIS Transmit Masked Interrupt Status: gives the interrupt status after masking of the transmit interrupt. 3 1 RIS Raw interrupt status register 0x18 8 read-only n 0x0 0x0 RORRIS Receive overrun raw interrupt status 0 1 RTRIS Receive time out raw interrupt status 1 1 RXRIS Receive raw interrupt status 2 1 TERIS Transmit FIFO Empty Raw Interrupt Status 5 1 TURRIS Transmit underrun raw interrupt Status 4 1 TXRIS Transmit raw interrupt status 3 1 RXFRM SPI Receive Frame register. Indicates the number of frames to receive from the slave. 0x28 16 read-write n 0x0 0x0 SR Status Register 0xC 8 read-only n 0x0 0x0 BSY SPI busy flag:

0: SPI is idle.
1: SPI is currently transmitting and/or receiving a frame or the TX FIFO is not empty.

4 1 RFF Receive FIFO full:

0: RX FIFO is not full.
1: RX FIFO is full.

3 1 RNE Receive FIFO not empty:

0: RX FIFO is empty.
1: RX FIFO is not empty.

2 1 TFE Transmit FIFO empty:

0: TX FIFO is not empty.
1: TX FIFO is empty.

0 1 TNF Transmit FIFO not full:

0: TX FIFO is full.
1: TX FIFO is not full.

1 1 TDR FIFO Test Data Register 0x8C 32 read-write n 0x0 0x0 WDTXF SPI transmit FIFO receive frame number. Indicates the number of frames to receive from the transmit FIFO. 0x30 16 read-write n 0x0 0x0 SYSTEM_CTRL System controller SYSTEM_CONTROLLER 0x0 0x0 0x1000 registers n CTRL XO frequency indication to provide by the application 0x8 8 read-write n 0x0 0x0 MHZ32_SEL Indicates the crystal frequency used in the application.

0: The 16 MHz is selected.
1: The 32 MHz is selected.

0 1 read-write MHz16 16 MHz is selected 0 MHz32 32 MHz is selected 1 WKP_IO_IE Enables the IO that wakes up the device (1 bit for IO) IO[13:9].

0: The wakes up feature on the IO is disabled.
1: The wakes up feature on the IO is enabled.

0x4 8 read-write n 0x0 0x0 WKP_IO_IS Level selection for wakeup IO (1 bit for IO) IO[13:9].

0: The system wakes up when IO is low.
1: The system wakes up when IO is high.

0x0 8 read-write n 0x0 0x0 UART UART UART 0x0 0x0 0x1000 registers n UART UART interrupt 4 CR Control Register 0x30 32 read-write n 0x0 0x0 CTSEN CTS hardware flow control enable.

0b: CTS disabled.
1b: CTS enabled. Data is only transmitted when the CTS is asserted.

15 1 CTS_DISABLE CTS hardware flow control disable 0 CTS_ENABLE CTS hardware flow control enable 1 OVSFACT UART oversampling factor.This bit enables the UART oversampling factor. If UARTCLK is 16 MHz thus max. baud-rate is 1 Mbaud when OVSFACT = 0b, and 2 Mbaud when OVSFACT = 1b.

0: UART it is 16 UARTCLK clock cycles.
1: UART it is 8 UARTCLK clock cycles.

3 1 Cycles_16 16 UARTCLK clock cycles 0 Cycles_8 8 UARTCLK clock cycles 1 RTS Request to send.

0: RTS is high.
1: RTS is low.

11 1 REQUEST_TO_SEND_LOW request to send low 0 REQUEST_TO_SEND_HIGH request to send high 1 RTSEN RTS hardware flow control enable.

0b: RTS disabled.
1b: RTS enabled. Data is only requested when there is space in the receive FIFO for it to be received.

14 1 RTS_DISABLE RTS hardware flow control disable 0 RTS_ENABLE RTS hardware flow control enable 1 RXE Receive enable.

0b: UART RX disabled.
1b: UART RX enabled.

9 1 RX_DISABLE Disable the RX UART 0 RX_ENABLE Enable the RX UART 1 STA_B_DURATION START bit duration Receiver state. These bits can be used to configure the START bit duration (in clock cycles) to get the bit sampled in the middle of the UART receiver. These bits can be used only when using high baud rates (IBRD = 1, FBRD >= 0 and OVSFACT = 1). Below the formula to calculate the START bit duration receiver state:

STA_B_DURATION = Integer(Fuartclk/(2* BAUD RATE)) - 1

Example: when UARTCLK = 16 MHz and BAUD RATE = 2.0 Mbps then STA_B_DURATION = 4 - 1 = 3. STA_B_DURATION field should be configured with 4'b0011. 16 4 TXE Transmit enable.

0b: UART TX disabled.
1b: UART TX enabled.

8 1 TX_DISABLE Disable the TX UART 0 TX_ENABLE Enable the TX UART 1 UARTEN UART enable. This bit enables the UART.

0: UART is disabled.
1: UART is enabled. Data transmission and reception can occur. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

0 1 DISABLE Disable the UART 0 ENABLE Enable the UART 1 DMACR DMA control register 0x48 8 read-write n 0x0 0x0 DMAONERR DMA on error.

0: UART error interrupt status has no impact in receive DMA mode.
1: DMA receive requests are disabled when the UART error interrupt is asserted.

3 1 DMA_ON_ERR_DISABLE UART error interrupt status has no impact in receive DMA mode 0 DMA_ON_ERR_ENABLE DMA receive requests are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable bit.

0: DMA mode is disabled for reception.
1: DMA mode is enabled for reception.

0 1 DMA_MODE_RX_DISABLE DMA mode for reception disable 0 DMA_MODE_RX_ENABLE DMA mode for reception enable 1 TXDMAE Transmit DMA enable bit.

0: DMA mode is disabled for transmit.
1: DMA mode is enabled for transmit.

1 1 DMA_MODE_TX_DISABLE DMA mode for transmission disable 0 DMA_MODE_TX_ENABLE DMA mode for transmission enable 1 DR Data Register 0x0 16 read-write n 0x0 0x0 BE Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to HIGH (marking state), and the next valid start bit is received 10 1 read-only DATA UART data register:

Receive: read data character.
Transmit: write data character.

0 8 read-write FE Frame error. This bit is set to 1 if the received character did not have a valid stop bit. In FIFO mode, this error is associated with the character at the top of the FIFO. 8 1 read-only OE Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0b once there is an empty space in the FIFO and a new character can be written to it. The FIFO content remains valid since no further data is written when the FIFO is full, only the content of the shift register is overwritten. 11 1 read-only PE Parity error. This bit is set to 1 if the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCRH_RX register. In FIFO mode, this error is associated with the character at the top of the FIFO. 9 1 read-only ECR Error Clear Register. A write to this register clears the framing (FE), parity (PE), break (BE), and overrun (OE) errors. RSR 0x4 32 read-write n 0x0 0x0 FBRD Fractional Baud Rate Register 0x28 8 read-write n 0x0 0x0 DIVFRAC Baud rate fraction. Baud rate integer. The baud rate divisor is calculated as follows:

When OVSFACT = 0b in the CR register: Baud rate divisor = (Frequency (UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: Baud rate divisor = (Frequency (UARTCLK)/(8*Baud rate))

where Frequency (UARTCLK) is the UART reference clock frequency. The baud rate divisor comprises the integer value (DIVINT) and the fractional value (DIVFRAC). The contents of the IBRD and FBRD registers are not updated until transmission or reception of the current character has completed. 0 6 FR Flag Register 0x18 16 read-only n 0x0 0x0 BUSY UART Busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. However, if the transmit section of the UART is disabled in the middle of a transmission, the BUSY bit gets cleared. This bit is set again once the transmit section is re-enabled to complete the remaining transmission.This bit is set as soon as the transmit FIFO becomes nonempty (regardless of whether the UART is enabled or not). 3 1 CTS Clear to send. 0 1 DCTS Delta Clear To Send. This bit is set CTS changes since the last read of the FR register. 9 1 RTXDIS Remote Transmitter Disabled (software flow control). This bit indicates an Xoff character was sent to the remote transmitter to stop it after the received FIFO has passed over its trigger limit. This bit is cleared when a Xon character is sent to the remote transmitter. 13 1 RXFE Receive FIFO empty. If the FIFO is disabled (bit FEN = 0b), this bit is set when the receive holding register is empty. If the FIFO is enabled (FEN = 1b), the RXFE bit is set when the receive FIFO is empty. 4 1 RXFF Receive FIFO full. If the FIFO is disabled (bit FEN = 0b), this bit is set when the receive holding register is full. If the FIFO is enabled (FEN = 1b), the RXFF bit is set when the receive FIFO is full. 6 1 TXFE Transmit FIFO empty. If the FIFO is disabled (bit FEN = 0b), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN = 1b), the TXFE bit is set when the transmit FIFO is empty. 7 1 TXFF Transmit FIFO full. If the FIFO is disabled (bit FEN = 0b), this bit is set when the transmit holding register is full. If the FIFO is enabled (FEN = 1b), the TXFF bit is set when the transmit FIFO is full. 5 1 IBRD Integer Baud Rate Register 0x24 16 read-write n 0x0 0x0 DIVINT Baud rate integer. The baud rate divisor is calculated as follows:

When OVSFACT = 0b in the CR register: Baud rate divisor = (Frequency (UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: Baud rate divisor = (Frequency (UARTCLK)/(8*Baud rate))

0: No effect.
1: Clears the interrupt.

9 1 CTSMIC Clear to send modem interrupt clear.

0: No effect.
1: Clears the interrupt.

1 1 FEIC Framing error interrupt clear.

0: No effect.
1: Clears the interrupt.

7 1 OEIC Overrun error interrupt clear.

0: No effect.
1: Clears the interrupt.

10 1 PEIC Parity error interrupt clear.

0: No effect.
1: Clears the interrupt.

8 1 RTIC Receive timeout interrupt clear.

0: No effect.
1: Clears the interrupt.

6 1 RXIC Receive interrupt clear.

0: No effect.
1: Clears the interrupt.

4 1 TXFEIC TX FIFO empty interrupt clear.

0: No effect.
1: Clears the interrupt.

12 1 TXIC Transmit interrupt clear.

0: No effect.
1: Clears the interrupt.

5 1 XOFFIC XOFF interrupt clear.

0: No effect.
1: Clears the interrupt.

11 1 IFLS Interrupt FIFO level select register 0x34 8 read-write n 0x0 0x0 RXIFLSEL Receive interrupt FIFO level select. This bit field selects the trigger points for RX FIFO interrupt:

000b: Interrupt when FIFO >= 1/64 full.
001b: Interrupt when FIFO >= 1/32 full.
010b: Interrupt when FIFO >= 1/16 full.
011b: Interrupt when FIFO >= 1/8 full.
100b: Interrupt when FIFO >= 1/4 full.
101b: Interrupt when FIFO >= 1/2 full.
110b: Interrupt when FIFO >= 3/4 full.

3 3 RXFIFO_1_64 Interrupt when FIFO >= 1/64 full 0 RXFIFO_1_32 Interrupt when FIFO >= 1/32 full 1 RXFIFO_1_16 Interrupt when FIFO >= 1/16 full 2 RXFIFO_1_8 Interrupt when FIFO >= 1/8 full 3 RXFIFO_1_4 Interrupt when FIFO >= 1/4 full 4 RXFIFO_1_2 Interrupt when FIFO >= 1/2 full 5 RXFIFO_3_4 Interrupt when FIFO >= 3/4 full 6 TXIFLSEL Transmit interrupt FIFO level select. This bit field selects the trigger points for TX FIFO interrupt:

000b: Interrupt when FIFO >= 1/64 empty.
001b: Interrupt when FIFO >= 1/32 empty.
010b: Interrupt when FIFO >= 1/16 empty.
011b: Interrupt when FIFO >= 1/8 empty.
100b: Interrupt when FIFO >= 1/4 empty.
101b: Interrupt when FIFO >= 1/2 empty.
110b: Interrupt when FIFO >= 3/4 empty.

0 3 TXFIFO_1_64 Interrupt when FIFO >= 1/64 empty 0 TXFIFO_1_32 Interrupt when FIFO >= 1/32 empty 1 TXFIFO_1_16 Interrupt when FIFO >= 1/16 empty 2 TXFIFO_1_8 Interrupt when FIFO >= 1/8 empty 3 TXFIFO_1_4 Interrupt when FIFO >= 1/4 empty 4 TXFIFO_1_2 Interrupt when FIFO >= 1/2 empty 5 TXFIFO_3_4 Interrupt when FIFO >= 3/4 empty 6 IMSC Interrupt Mask Set/Clear Register 0x38 16 read-write n 0x0 0x0 BEIM Break error interrupt mask. On a read, the current mask for the BEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

9 CTSMIM Clear to send modem interrupt mask. On a read, the current mask for the CTSMIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

1 1 CLEAR_MASK clear the interrupt mask 0 SET_MASK set the interrupt mask 1 FEIM Framing error interrupt mask. On a read, the current mask for the FEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

7 OEIM Overrun error interrupt mask. On a read, the current mask for the OEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

10 PEIM Parity error interrupt mask. On a read, the current mask for the PEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

8 RTIM Receive timeout interrupt mask. On a read, the current mask for the RTIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

6 RXIM Receive interrupt mask. On a read, the current mask for the RXIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

4 TXFEIM TX FIFO empty interrupt mask. On a read, the current mask for the TXFEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

12 TXIM Transmit interrupt mask. On a read, the current mask for the TXIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

5 XOFFIM XOFF interrupt mask. On a read, the current mask for the XOFFIM interrupt is returned.

0: Clears the mask (interrupt is disabled).
1: Sets the mask (interrupt is enabled).

11 LCRH_RX Receive Line Control Register 0x1C 8 read-write n 0x0 0x0 EPS_RX RX even parity selection, when the parity is enabled.

0: Odd parity generation and checking is performed during reception, which check for an odd number of 1s in data and parity bits.
1: Even parity generation and checking is performed during reception, which check for an even number of 1s in data and parity bits.

2 1 ODD Odd parity generation and checking is performed during reception, which check for an odd number of 1s in data and parity bits 0 EVEN Even parity generation and checking is performed during reception, which check for an even number of 1s in data and parity bits 1 FEN_RX RX enable FIFOs. This bit enables/disables the receive RX FIFO buffer:

0: RX FIFO is disabled (character mode).
1: RX FIFO is enabled.

4 1 RXFIFO_DISABLED RX FIFO is disabled 0 RXFIFO_ENABLED RX FIFO is enabled 1 PEN_RX RX parity enable:

0: Parity disabled.
1: Parity enabled.

1 1 PARITY_DISABLE Parity Disable 0 PARITY_ENABLE Parity Enable 1 SPS_RX RX stick parity select:

0: stick parity is disabled.
1: when PEN_RX = 1b (parity enabled) and EPS_RX = 1b (even parity), the parity is checked as a 0. When PEN_RX = 1b and EPS_RX = 0b (odd parity), the parity bit is checked as a 1.

7 1 STICK_PARITY_DISABLE stick parity disable 0 STICK_PARITY_ENABLE stick parity enable 1 STP2_RX RX two stop bits select. This bit enables the check for two stop bits being received:

0: 1 stop bit received.
1: 2 stop bits received.

3 1 STOP_BIT1 1 stop bit received 0 STOP_BITS2 2 stop bits received 1 WLEN_RX RX Word length. This bit field indicates the number of data bits received in a frame as follows:

00b: 5 bits.
01b: 6 bits.
10b: 7 bits.
11b: 8 bits.

5 2 BIT5 5 bits 0 BIT6 6 bits 1 BIT7 7 bits 2 BIT8 8 bits 3 LCRH_TX Transmit Line Control Register 0x2C 8 read-write n 0x0 0x0 BRK Send break. This bit allows a continuous low-level to be forced on TX output, after completion of the current character. This bit must be asserted for at least one complete frame transmission time in order to generate a break condition. The transmit FIFO contents remain unaffected during a break condition.

0: Normal transmission.
1: Break condition transmission.

0 1 TX_NORMAL Normal transmission 0 TX_BREAK_CONDITION Break condition transmission 1 EPS_TX TX even parity select. This bit selects the parity generation, when the parity is enabled (PEN_TX =1b). This bit has no effect when parity is disabled (PEN_TX = 0b).

0: Odd parity generation and checking is performed during transmission, which check for an odd number of 1s in data and parity bits.
1: Even parity generation and checking is performed during transmission, which check for an even number of 1s in data and parity bits.

2 1 ODD Odd parity generation and checking is performed during transmission, which check for an odd number of 1s in data and parity bits 0 EVEN Even parity generation and checking is performed during transmission, which check for an even number of 1s in data and parity bits 1 FEN_TX TX Enable FIFO. This bit enables/disables the transmit TX FIFO buffer:

0: TX FIFO is disabled (character mode), i.e. the TX FIFO becomes a 1-byte deep holding register.
1: TX FIFO is enabled.

4 1 TXFIFO_DISABLED TX FIFO is disabled 0 TXFIFO_ENABLED TX FIFO is enabled 1 PEN_TX TX parity enable:

0: Parity disabled.
1: Parity Enable.

1 1 PARITY_DISABLE Parity Disable 0 PARITY_ENABLE Parity Enable 1 SPS_TX TX Stick parity check:

0: stick parity disable.
1: when PEN_TX = 1b (parity enabled) and EPS_TX = 1b (even parity), the parity is transmitted as a 0. When PEN_TX = 1b and EPS_TX = 0b (odd parity), the parity bit is transmitted as a 1.

7 1 STICK_PARITY_DISABLE stick parity disable 0 STICK_PARITY_ENABLE stick parity enable 1 STP2_TX TX two stop bits select. This bit enables the check for two stop bits being received:

0: 1 stop bit received.
1: 2 stop bits received.

3 1 STOP_BIT1 1 stop bit received 0 STOP_BITS2 2 stop bits received 1 WLEN_TX TX word length. This bit field indicates the number of data bits transmitted in a frame as follows:

00b: 5 bits.
01b: 6 bits.
10b: 7 bits.
11b: 8 bits.

5 2 BIT5 5 bits 0 BIT6 6 bits 1 BIT7 7 bits 2 BIT8 8 bits 3 MIS Masked Interrupt Status Register 0x40 16 read-only n 0x0 0x0 BEMIS Break error masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

9 1 CTSMMIS Clear to send masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

1 1 INTERRUPT_NOT_PENDING interrupt not pending 0 INTERRUPT_PENDING interrupt pending 1 FEMIS Framing error masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

7 1 OEMIS Overrun error masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

10 1 PEMIS Parity error masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

8 1 RTMIS Receive timeout masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

6 1 RXMIS Receive masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

4 1 TXFEMIS TX FIFO empty masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

12 1 TXMIS Transmit masked interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

5 1 XOFFMIS XOFF interrupt masked status.

0: The interrupt is not pending.
1: The interrupt is pending.

11 1 RIS Raw Interrupt Status Register 0x3C 16 read-only n 0x0 0x0 BEIS Break error interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

9 1 CTSMIS Clear to send interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

1 1 INTERRUPT_NOT_PENDING interrupt not pending 0 INTERRUPT_PENDING interrupt pending 1 FEIS Framing error interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

7 1 OEIS Overrun error interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

10 1 PEIS Parity error interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

8 1 RTIS Receive timeout interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

6 1 RXIS Receive interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

4 1 TXFEIS TX FIFO empty interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

12 1 TXIM Transmit interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

5 1 XOFFIS XOFF interrupt status.

0: The interrupt is not pending.
1: The interrupt is pending.

11 1 RSR Receive Status Register 0x4 32 read-only n 0x0 0x0 BE Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity and stop bits). This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to HIGH (marking state), and the next valid start bit is received. 2 1 read-only FE Frame error. This bit is set to 1 if the received character did not have a valid stop bit (a valid stop bit is 1).This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO. 0 1 read-only OE Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 by a write to ECR (data value is not important). The FIFO contents remain valid since no further data is written when the FIFO is full, only the content of the shift register are overwritten. The CPU or DMA must now read the data in order to empty the FIFO. 3 1 read-only PE Parity error. This bit is set to 1 if the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCRH_RX register.This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO. 1 1 read-only TIMEOUT Timeout Register 0xC 32 read-write n 0x0 0x0 PERIOD Timeout period configuration. This bit field contains the timeout period for the UART timeout interrupt assertion. The receive timeout interrupt is asserted when the receive FIFO is not empty and no further data is received over a programmed timeout period. The duration before the timeout interrupt will assert is calculated by the following formula:

Timeout_Duration = (TIMEOUT_PERIOD) / (OVSP * Baud_Rate)

Timeout_Duration = (TIMEOUT_PERIOD) * Baud_Divisor * Tuartclk

0 22 XFCR XON/XOFF Control Register 0x50 8 read-write n 0x0 0x0 SFEN Software flow control enable.

0: Software flow control disable.
1: software flow control enable.

0 1 SOFTWARE_FLOW_CTRL_DISABLE software flow ctrl disable 0 SOFTWARE_FLOW_CTRL_ENABLE software flow ctrl enable 1 SFRMOD Software receive flow control mode:

00b: Receive flow control is disabled.
01b: Xon1, Xoff1 characters are used in receiving software flow control.
10b: Xon2, Xoff2 characters are used in receiving software flow control.
11b: Xon1 and Xon2, Xoff1 and Xoff2 characters are used in receiving software flow control.

1 2 SFR_MODE_DISABLE Receive flow control is disable 0 SFR_MODE_XON1_XOFF1 Xon1, Xoff1 characters are used in receive software flow control 1 SFR_MODE_XON2_XOFF2 Xon2, Xoff2 characters are used in receive software flow control 2 SFR_MODE_XON1_XON2_XOFF1_XOFF2 Xon1 and Xon2, Xoff1 and Xoff2 characters are used in receive software flow control 3 SFTMOD Software transmit flow control mode:

00b: Transmit flow control is disabled.
01b: Xon1, Xoff1 characters are used in transmitting software flow control.
10b: Xon2, Xoff2 characters are used in transmitting software flow control.
11b: Xon1 and Xon2, Xoff1 and Xoff2 characters are used in transmitting software flow control.

3 2 SFR_MODE_DISABLE Transmit flow control is disable 0 SFR_MODE_XON1_XOFF1 Xon1, Xoff1 characters are used in transmit software flow control 1 SFR_MODE_XON2_XOFF2 Xon2, Xoff2 characters are used in transmit software flow control 2 SFR_MODE_XON1_XON2_XOFF1_XOFF2 Xon1 and Xon2, Xoff1 and Xoff2 characters are used in transmit software flow control 3 SPECHAR Special character detection bit.

0: Special character detection disabled.
1: Special character detection enabled.

6 1 SPECHAR_DISABLE pecial character detection disabled 0 SPECHAR_ENABLE special character detection enabled 1 XONANY Xon-any bit:

0: Incoming character must match Xon programmed value(s) to be a valid Xon.
1: Any incoming character is considered as a valid Xon.

5 1 XONANY_DISABLE incoming character must match Xon programmed value(s) to be a valid Xon 0 XONANY_ENABLE any incoming character is considered as a valid Xon 1 XOFF1 Register used to store the Xoff1 character used for software flow control 0x5C 8 read-write n 0x0 0x0 XOFF1 Value of Xoff1 character used in the software flow control 0 8 XOFF2 Register used to store the Xoff2 character used for software flow control 0x60 8 read-write n 0x0 0x0 XOFF2 Value of Xoff2 character used in the software flow control 0 8 XON1 Register used to store the Xon1 character used for software flow control 0x54 8 read-write n 0x0 0x0 XON1 Value of Xon1 character used in the software flow control 0 8 XON2 Register used to store the Xon2 character used for software flow control 0x58 8 read-write n 0x0 0x0 XON2 Value of Xon2 character used in the software flow control 0 8 WDG Watchdog WDG 0x0 0x0 0x1000 registers n WDG Watchdog interrupt 7 CR Watchdog Control Register 0x8 8 read-write n 0x0 0x0 INTEN Watchdog interrupt enable. Enable the interrupt event:

0: watchdog interrupt is disabled.
1: watchdog interrupt is enabled.

0 1 DISABLE Disable watchdog interrupt 0 ENABLE Enable watchdog interrupt 1 RESEN Watchdog reset enable. Enable the watchdog reset output:

0: watchdog reset is disabled.
1: watchdog reset is enabled.

1 1 DISABLE Disable watchdog reset 0 ENABLE Enable watchdog reset 1 ICR Watchdog Interrupt Clear Register 0xC 32 read-write n 0x0 0x0 clear WDTICLR Watchdog interrupt enable:

Writing any value will clear the watchdog interrupt and reloads the counter from the LR register.
A read returns zero.

0 32 LOCK Watchdog Lock Register 0xC00 32 read-write n 0x0 0x0 LOCKVAL Watchdog lock value. When read, returns the lock status:

0: Write access to all watchdog other registers is enabled.
1: Write access to all watchdog other registers is disabled.

When written, allows enabling or disabling write access to all other watchdog registers:

Writing 0x1ACCE551: Write access to all other registers is enabled.
Writing any other value: Write access to all other registers is disabled.

0 32 LR Watchdog Load Register 0x0 32 read-write n 0x0 0x0 LOAD Watchdog load value. Value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value. 0 32 MIS Watchdog Masked Interrupt Status Register 0x14 8 read-only n 0x0 0x0 MIS Watchdog masked interrupt status bit. Masked value of watchdog interrupt status:

0: watchdog interrupt is not active.
1: watchdog interrupt is active.

Read-only bit. A write has no effect. 0 1 IRQ_NOT_PENDING Watchdog interrupt masked is not active 0 IRQ_PENDING Watchdog interrupt masked is active 1 RIS Watchdog Raw Interrupt Status Register 0x10 8 read-only n 0x0 0x0 RIS Watchdog raw interrupt status bit. Reflects the status of the interrupt status from the watchdog:

0: watchdog interrupt is not active.
1: watchdog interrupt is active.

Read-only bit. A write has no effect. 0 1 IRQ_NOT_PENDING Watchdog interrupt is not active 0 IRQ_PENDING Watchdog interrupt is active 1 VAL Watchdog Value Register 0x4 32 read-only n 0x0 0x0 WDTVAL Watchdog load value. When read, returns the current value of the decrementing watchdog counter. A write has no effect. 0 32