STMicroelectronics BlueNRG_LP 2024.04.28 BlueNRG_LP CM0+ r0p0 little 2 false 8 32 ADC ADC ADC 0x0 0x0 0x400 registers n ADC ADC interrupt 12 COMP_1 COMP_1 ADC Gain and offset correction values register 1 0x28 32 read-write n 0x0 0x0 GAIN1 first calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 OFFSET1 first calibration point: signed offset compensation[6:0] 12 7 COMP_2 COMP_2 ADC Gain and offset correction values register 2 0x2C 32 read-write n 0x0 0x0 GAIN2 second calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 OFFSET2 second calibration point: signed offset compensation[6:0] 12 7 COMP_3 COMP_3 ADC Gain and offset correction values register 3 0x30 32 read-write n 0x0 0x0 GAIN3 third calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 OFFSET3 third calibration point: signed offset compensation[6:0] 12 7 COMP_4 COMP_4 ADC Gain and offset correction values register 4 0x34 32 read-write n 0x0 0x0 GAIN4 fourth calibration point: gain AUXADC_GAIN_1V2[11:0] 0 12 OFFSET4 fourth calibration point: signed offset compensation[6:0] 12 7 COMP_SEL COMP_SEL ADC Gain and Offset selection values register 0x38 32 read-write n 0x0 0x0 GAIN_OFFSET0 gain / offset used in ADC single negative mode with Vinput range = 1.2V 0 2 GAIN_OFFSET1 gain / offset used in ADC single positive mode with Vinput range = 1.2V 2 2 GAIN_OFFSET2 gain / offset used in ADC differential mode with Vinput range = 1.2V 4 2 GAIN_OFFSET3 gain / offset used in ADC single negative mode with Vinput range = 2.4V 6 2 GAIN_OFFSET4 gain / offset used in ADC single positive mode with Vinput range = 2.4V 8 2 GAIN_OFFSET5 gain / offset used in ADC differential mode with Vinput range = 2.4V 10 2 GAIN_OFFSET6 gain / offset used in ADC single negative mode with Vinput range = 3.6V 12 2 GAIN_OFFSET7 gain / offset used in ADC single positive mode with Vinput range = 3.6V 14 2 GAIN_OFFSET8 gain / offset used in ADC differential mode with Vinput range = 3.6V 16 2 CONF CONF ADC configuration register 0x4 32 read-write n 0x0 0x0 ADC_CONT_1V2 select the input sampling method 19 1 BIT_INVERT_DIFF invert bit to bit the ADC data output when a differential 18 1 BIT_INVERT_SN invert bit to bit the ADC data output when a single 17 1 CONT regular sequence runs continuously when ADC mode is enabled 0 1 DMA_DF_ENA enable DMA mode for Decimation Filter data path 14 1 DMA_DS_ENA enable DMA mode for Down Sampler data path 13 1 OP_MODE ADC mode selection (= data path selection) 7 2 OVR_DF_CFG decimation overrun configuration 16 1 OVR_DS_CFG Down Sampler overrun configuration 15 1 SAMPLE_RATE conversion rate of ADC 11 2 SEQUENCE enable the sequence mode (active by default) 1 1 SEQ_LEN number of conversions in a regular sequence 2 4 SMPS_SYNCHRO_ENA synchronize the ADC start conversion with a pulse generated by the 6 1 VBIAS_PRECH_FORCE possibility to keep the VBIAS_PRECH enabled to deactivate the filter 20 1 CTRL CTRL ADC control register 0x8 32 read-write n 0x0 0x0 ADC_LDO_ENA enable the LDO associated to the ADC block 5 1 ADC_ON_OFF 0 1 DIG_AUD_MODE enable the digital audio mode (the data path uses the decimation filter) 3 1 START_CON generate a start pulse to initiate an ADC conversion 1 1 STOP_OP_MOD stop the on-going OP_MODE (ADC mode, Analog audio mode, Full 2 1 TEST_MODE select the functional or the test mode of the ADC 4 1 DF_CONF DF_CONF Decimation filter configuration register 0x18 32 read-write n 0x0 0x0 DF_CIC_DEC_FACTOR 0 7 DF_CIC_DHF CIC filter decimator half factor 7 1 DF_HALF_D_EN half dynamic enable. 17 1 DF_HPF_EN high pass filter enable. 16 1 DF_ITP1P2 1.2 fractional interpolator enable 8 1 DF_I_U2S select signed/unsigned format for input 9 1 DF_MICROL_RN left/right channel selection on digital microphone 15 1 DF_O_S2U select signed/unsigned format for data output 10 1 PDM_RATE select the PDM clock rate. 11 4 DF_DATAOUT DF_DATAOUT Decimation filter Data output register 0x48 32 read-only n 0x0 0x0 DF_DATA contain the converted data at the output of the decimation filter. 0 16 DS_CONF DS_CONF Downsampler configuration register 0x1C 32 read-write n 0x0 0x0 DS_RATIO program the Down Sampler ratio (N factor) 0 3 DS_WIDTH program the Down Sampler width of data output (DSDTATA) 3 3 DS_DATAOUT DS_DATAOUT Downsampler Data output register 0x44 32 read-only n 0x0 0x0 DS_DATA contain the converted data at the output of the Down Sampler. 0 16 DTB_CONF DTB_CONF DTB_CONF register 0x64 32 read-write n 0x0 0x0 ADC_DBG_CONF use for debug purpose. 0 4 ADC_DTB_CONF configure the DTB output. 8 2 DF_DTB_CONF internal decimation filter multiplexing. 4 4 FSM_CUR_STATE show the last executed state by the state machine. 24 3 FSM_STATE show the state of the state machine. 16 8 IRQ_ENABLE IRQ_ENABLE Enable/disable Interrupts 0x50 32 read-write n 0x0 0x0 AWD_IRQ_ENA analog watchdog interrupt enable 4 1 DF_OVRFL_IRQ_ENA decimation filter saturation interrupt enable 7 1 EOC_IRQ_ENA (Used in test mode only): End of ADC conversion interrupt enable 0 1 EODF_IRQ_ENA End of conversion interrupt enable for the decimation filter output 2 1 EODS_IRQ_ENA End of conversion interrupt enable for the Down Sampler output 1 1 EOS_IRQ_ENA End of regular sequence interrupt enable 3 1 OVR_DF_IRQ_ENA decimation filter overrun interrupt enable 6 1 OVR_DS_IRQ_ENA Down Sampler overrun interrupt enable 5 1 IRQ_STATUS IRQ_STATUS Interrupt Status register 0x4C 32 read-write n 0x0 0x0 AWD_IRQ set when an analog watchdog event occurs. 4 1 DF_OVRFL_IRQ set to indicate the decimation filter is saturated. 7 1 EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. 0 1 EODF_IRQ set when the decimation filter conversion is completed. 2 1 EODS_IRQ set when the Down Sampler conversion is completed. 1 1 EOS_IRQ set when a sequence of conversion is completed. 3 1 OVR_DF_IRQ set to indicate a decimation filter overrun (a data is lost) 6 1 OVR_DS_IRQ set to indicate a Down Sampler overrun (at least one data is lost) 5 1 OCM_CTRL OCM_CTRL Occasionnal mode control register 0xC 32 read-write n 0x0 0x0 OCM_ENA start occasional conversion in analog audio and full modes 1 1 OCM_SRC select the occasional conversion source 0 1 PGA_CONF PGA_CONF PGA configuration register 0x10 32 read-write n 0x0 0x0 PGA_BIAS set the microphone bias voltage 4 3 PGA_GAIN from 6 to 30 dB 0 4 SEQ_1 SEQ_1 ADC regular sequence configuration register 1 0x20 32 read-write n 0x0 0x0 SEQ0 channel number code for first conversion of the sequence 0 4 SEQ1 channel number code for second conversion of the sequence. 4 4 SEQ2 channel number code for 3rd conversion of the sequence. 8 4 SEQ3 channel number code for 4th conversion of the sequence. 12 4 SEQ4 channel number code for 5th conversion of the sequence. 16 4 SEQ5 channel number code for 6th conversion of the sequence. 20 4 SEQ6 channel number code for 7th conversion of the sequence. 24 4 SEQ7 channel number code for 8th conversion of the sequence. 28 4 SEQ_2 SEQ_2 ADC regular sequence configuration register 2 0x24 32 read-write n 0x0 0x0 SEQ10 channel number code for 11th conversion of the sequence. 8 4 SEQ11 channel number code for 12th conversion of the sequence. 12 4 SEQ12 channel number code for 13th conversion of the sequence. 16 4 SEQ13 channel number code for 14th conversion of the sequence. 20 4 SEQ14 channel number code for 15th conversion of the sequence. 24 4 SEQ15 channel number code for 16th conversion of the sequence. 28 4 SEQ8 channel number code for 9th conversion of the sequence 0 4 SEQ9 channel number code for 10th conversion of the sequence. 4 4 SWITCH SWITCH ADC switch control for Input Selection 0x14 32 read-write n 0x0 0x0 SE_VIN_0 input voltage for VINM[0] / VINP[0]-VINM[0] 0 2 SE_VIN_1 input voltage for VINM[1] / VINP[1]-VINM[1] 2 2 SE_VIN_2 input voltage for VINM[2] / VINP[2]-VINM[2] 4 2 SE_VIN_3 input voltage for VINM[3] / VINP[3]-VINM[3] 6 2 SE_VIN_4 input voltage for VINP[0] 8 2 SE_VIN_5 input voltage for VINP[1] 10 2 SE_VIN_6 input voltage for VINP[2] 12 2 SE_VIN_7 input voltage for VINP[3] 14 2 TEST_CONF TEST_CONF TEST_CONF 0x60 32 read-write n 0x0 0x0 ADC_ENABLE 22 1 ADC_RUN Start/stop ADC conversion. 21 1 ADC_SWITCH_EN enable individually each connection of the switching matrix at the ADC input, corresponding to AUXADC_INSEL_1V2[15:0]. 0 16 LDO_ADC_ENABLE 23 1 PGA_ENABLE PGA_ENABLE 20 1 SEL_VIN_TYPE operation mode of the selected VIN 18 2 VBIAS_PRECH_ENABLE set and reset by the software, knowing the bit must stay high at 24 1 TIMER_CONF TIMER_CONF Time to add after an LDO Enable or ADC Enable to let the HW to be stable before using it 0x54 32 read-write n 0x0 0x0 ADC_LDO_DELAY define the duration of a waiting time to be inserted between the ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a conversion. 0 8 PRECH_DELAY_SEL Select the time step PD_STEP for the VBIAS_PRECH_DELAY timer. 16 1 VBIAS_PRECH_DELAY define the duration of a waiting time starting at rising edge of PGA_EN signal and corresponding to the VBIAS precharge duration. 8 8 VERSION_ID VERSION_ID VERSION_ID register 0x0 32 read-only n 0x0 0x0 VERSION_ID version of the embedded IP. 0 8 WD_CONF WD_CONF Channel selection for event monitoring register 0x40 32 read-write n 0x0 0x0 AWD_CHX analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog. 0 16 WD_TH WD_TH High/low limits for event monitoring a channel register 0x3C 32 read-write n 0x0 0x0 WD_HT analog watchdog high level threshold. 16 12 WD_LT analog watchdog low level threshold. 0 12 BLUE BLUE BLUE 0x0 0x0 0x1000 registers n PVD_BORH PVD/BORH interrupt 2 BLE_TX_RX_IRQn BLE Tx/Rx interrupt 18 BLE_AES_IRQn BLE AES interrupt 19 BLE_DBG_IRQn BLE Debug interrupt 20 MR_BLE_IRQn RRM and Radio FSM interrupt 22 CPU_WKUP_IRQn CPU Wakeup interrupt 23 BLE_WKUP_IRQn BLE Wakeup interrupt 24 AESLEPRIVCMDREG AESLEPRIVCMDREG AesLePrivCmd register 0x6C 32 read-write n 0x0 0x0 INTENA INTENA 1 1 NBKEYS NBKEYS 2 8 START START 0 1 AESLEPRIVHASHREG AESLEPRIVHASHREG AesLePrivHash register 0x64 32 read-write n 0x0 0x0 HASH HASH 0 24 AESLEPRIVPOINTERREG AESLEPRIVPOINTERREG AesLePrivPointer register 0x60 32 read-write n 0x0 0x0 POINTER POINTER 0 24 AESLEPRIVPRANDREG AESLEPRIVPRANDREG AesLePrivPrand register 0x68 32 read-write n 0x0 0x0 PRAND PRAND 0 24 AESLEPRIVSTATREG AESLEPRIVSTATREG AesLePrivStat register 0x70 32 read-only n 0x0 0x0 BUSY BUSY 0 1 KEYFND KEYFND 1 1 KEYFNDINDEX KEYFNDINDEX 2 8 CMDREG CMDREG Cmd register 0x18 32 read-write n 0x0 0x0 CLEARSEMAREQ CLEARSEMAREQ 3 1 LOCKAHBFIRSTINITEN LOCKAHBFIRSTINITEN 2 1 LOCKAHBWRITEBACKEN LOCKAHBWRITEBACKEN 1 1 TXRXSKIP TXRXSKIP 0 1 CONTROLLERVERNUMREG CONTROLLERVERNUM Controller Version Number register 0x0 32 read-only n 0x0 0x0 SUBVERNUM SUBVERNUM 0 8 TYP TYP 16 8 VERNUM VERNUM 8 8 DEBUGCMDREG DEBUGCMDREG DebugCmd register 0x74 32 read-write n 0x0 0x0 AESDEBUGMODE AESDEBUGMODE 16 4 CLEARDEBUGINT CLEARDEBUGINT 0 1 SEQDEBUGBUSSEL SEQDEBUGBUSSEL 2 4 SEQDEBUGMODE SEQDEBUGMODE 1 1 DEBUGSTATUSREG DEBUGSTATUSREG DebugStatus register 0x78 32 read-only n 0x0 0x0 AESDBG_0 AESDBG_0 16 1 AESDBG_1 AESDBG_1 17 1 AESDBG_2 AESDBG_2 18 1 AESDBG_3 AESDBG_3 19 1 SEQERROR_0 SEQERROR_0 0 1 SEQERROR_1 SEQERROR_1 1 1 SEQERROR_2 SEQERROR_2 2 1 SEQERROR_3 SEQERROR_3 3 1 SEQERROR_4 SEQERROR_4 4 1 SEQERROR_5 SEQERROR_5 5 1 INTERRUPT1ENABLEREG INTERRUPT1ENABLEREG Interrupt1Enable register 0x20 32 read-only n 0x0 0x0 ACTIVE2ERROR ACTIVE2ERROR 22 1 ADDPOINTERROR ADDPOINTERROR 4 1 ALLTABLEREADYERROR ALLTABLEREADYERROR 14 1 CONFIGERROR CONFIGERROR 23 1 DONE DONE 25 1 ENCERROR ENCERROR 13 1 INITDELAYERROR INITDELAYERROR 17 1 NOACTIVELERROR NOACTIVELERROR 16 1 RCVCMD RCVCMD 28 1 RCVCRCERR RCVCRCERR 30 1 RCVLENGTHERROR RCVLENGTHERROR 18 1 RCVNOMD RCVNOMD 27 1 RCVOK RCVOK 31 1 RCVTIMEOUT RCVTIMEOUT 26 1 RXOVERFLOWERROR RXOVERFLOWERROR 5 1 SEMATIMEOUTERROR SEMATIMEOUTERROR 19 1 SEMAWASPREEMPT SEMAWASPREEMPT 20 1 SEQDONE SEQDONE 7 1 TIMECAPTURETRIG TIMECAPTURETRIG 29 1 TXDATAREADYERROR TXDATAREADYERROR 15 1 TXERROR_0 TXERROR_0 8 1 TXERROR_1 TXERROR_1 9 1 TXERROR_2 TXERROR_2 10 1 TXERROR_3 TXERROR_3 11 1 TXERROR_4 TXERROR_4 12 1 TXOK TXOK 24 1 TXRXSKIP TXRXSKIP 21 1 INTERRUPT1LATENCYREG INTERRUPT1LATENCY Interrupt1Latency register 0x24 32 read-only n 0x0 0x0 INTERRUPT1LATENCY INTERRUPT1LATENCY 0 8 INTERRUPT1REG INTERRUPT1REG Interrupt1 register 0x4 32 read-write n 0x0 0x0 ACTIVE2ERROR ACTIVE2ERROR 22 1 ADDPOINTERROR ADDPOINTERROR 4 1 ALLTABLEREADYERROR ALLTABLEREADYERROR 14 1 CONFIGERROR CONFIGERROR 23 1 DONE DONE 25 1 ENCERROR ENCERROR 13 1 INITDELAYERROR INITDELAYERROR 17 1 NOACTIVELERROR NOACTIVELERROR 16 1 RCVCMD RCVCMD 28 1 RCVCRCERR RCVCRCERR 30 1 RCVLENGTHERROR RCVLENGTHERROR 18 1 RCVNOMD RCVNOMD 27 1 RCVOK RCVOK 31 1 RCVTIMEOUT RCVTIMEOUT 26 1 RXOVERFLOWERROR RXOVERFLOWERROR 5 1 SEMATIMEOUTERROR SEMATIMEOUTERROR 19 1 SEMAWASPREEMPT SEMAWASPREEMPT 20 1 SEQDONE SEQDONE 7 1 TIMECAPTURETRIG TIMECAPTURETRIG 29 1 TXDATAREADYERROR TXDATAREADYERROR 15 1 TXERROR_0 TXERROR_0 8 1 TXERROR_1 TXERROR_1 9 1 TXERROR_2 TXERROR_2 10 1 TXERROR_3 TXERROR_3 11 1 TXERROR_4 TXERROR_4 12 1 TXOK TXOK 24 1 TXRXSKIP TXRXSKIP 21 1 INTERRUPT2REG INTERRUPT2REG Interrupt2 register 0x8 32 read-write n 0x0 0x0 AESLEPRIVINT AESLEPRIVINT 1 1 AESMANENCINT AESMANENCINT 0 1 MANAESCIPHERTEXT0REG MANAESCIPHERTEXT0REG ManAESCipherText0 register 0x48 32 read-only n 0x0 0x0 AES_CIPHER_31_0 AES_CIPHER_31_0 0 32 MANAESCIPHERTEXT1REG MANAESCIPHERTEXT1REG ManAESCipherText1 register 0x4C 32 read-only n 0x0 0x0 AES_CIPHER_63_32 AES_CIPHER_63_32 0 32 MANAESCIPHERTEXT2REG MANAESCIPHERTEXT2 ManAESCipherText2 register 0x50 32 read-only n 0x0 0x0 AES_CIPHER_95_64 AES_CIPHER_95_64 0 32 MANAESCIPHERTEXT3REG MANAESCIPHERTEXT3REG ManAESCipherText3 register 0x54 32 read-only n 0x0 0x0 AES_CIPHER_127_96 AES_CIPHER_127_96 0 32 MANAESCLEARTEXT0REG MANAESCLEARTEXT0REG ManAesClearText0 register 0x38 32 read-write n 0x0 0x0 AES_CLEAR_31_0 AES_CLEAR_31_0 0 32 MANAESCLEARTEXT1REG MANAESCLEARTEXT1REG ManAesClearText1 register 0x3C 32 read-write n 0x0 0x0 AES_CLEAR_63_32 AES_CLEAR_63_32 0 32 MANAESCLEARTEXT2REG MANAESCLEARTEXT2REG ManAesClearText2 register 0x40 32 read-write n 0x0 0x0 AES_CLEAR_95_64 AES_CLEAR_95_64 0 32 MANAESCLEARTEXT3REG MANAESCLEARTEXT3REG ManAesClearText3 register 0x44 32 read-write n 0x0 0x0 AES_CLEAR_127_96 AES_CLEAR_127_96 0 32 MANAESCMDREG MANAESCMDREG ManAESCmd register 0x58 32 read-write n 0x0 0x0 INTENA INTENA 1 1 START START 0 1 MANAESKEY0REG MANAESKEY0REG ManAesKey0 register 0x28 32 read-write n 0x0 0x0 MANAESKEY_31_0 MANAESKEY_31_0 0 32 MANAESKEY1REG MANAESKEY1REG ManAesKey1 register 0x2C 32 read-write n 0x0 0x0 MANAESKEY_63_32 MANAESKEY_63_32 0 32 MANAESKEY2REG MANAESKEY2REG ManAesKey2 register 0x30 32 read-write n 0x0 0x0 MANAESKEY_95_64 MANAESKEY_95_64 0 32 MANAESKEY3REG MANAESKEY3REG ManAesKey3 register 0x34 32 read-write n 0x0 0x0 MANAESKEY_127_96 MANAESKEY_127_96 0 32 MANAESSTATREG MANAESSTATREG ManAESStat register 0x5C 32 read-only n 0x0 0x0 BUSY BUSY 0 1 SPARE SPARE SpareReg register 0x7C 32 read-write n 0x0 0x0 STATUSREG STATUSREG Status register 0x1C 32 read-only n 0x0 0x0 ACTIVE2ERROR ACTIVE2ERROR 22 1 ADDPOINTERROR ADDPOINTERROR 4 1 AESONFLYBUSY AESONFLYBUSY 0 1 ALLTABLEREADYERROR ALLTABLEREADYERROR 14 1 CONFIGERROR CONFIGERROR 23 1 DONE DONE 25 1 ENCERROR ENCERROR 13 1 INITDELAYERROR INITDELAYERROR 17 1 NOACTIVELERROR NOACTIVELERROR 16 1 PREVTRANSMIT PREVTRANSMIT 6 1 RCVCMD RCVCMD 28 1 RCVCRCERR RCVCRCERR 30 1 RCVLENGTHERROR RCVLENGTHERROR 18 1 RCVNOMD RCVNOMD 27 1 RCVOK RCVOK 31 1 RCVTIMEOUT RCVTIMEOUT 26 1 RXOVERFLOWERROR RXOVERFLOWERROR 5 1 SEMATIMEOUTERROR SEMATIMEOUTERROR 19 1 SEMAWASPREEMPT SEMAWASPREEMPT 20 1 SEQDONE SEQDONE 7 1 TIMECAPTURETRIG TIMECAPTURETRIG 29 1 TXDATAREADYERROR TXDATAREADYERROR 15 1 TXERROR_0 TXERROR_0 8 1 TXERROR_1 TXERROR_1 9 1 TXERROR_2 TXERROR_2 10 1 TXERROR_3 TXERROR_3 11 1 TXERROR_4 TXERROR_4 12 1 TXOK TXOK 24 1 TXRXSKIP TXRXSKIP 21 1 TIMEOUTDESTREG TIMEOUTDEST TimeoutDest register 0xC 32 read-write n 0x0 0x0 DESTINATION DESTINATION 0 2 TIMEOUTREG TIMEOUTREG Timeout register 0x10 32 read-write n 0x0 0x0 TIMEOUT TIMEOUT 0 32 TIMERCAPTUREREG TIMERCAPTUREREG TimerCapture register 0x14 32 read-only n 0x0 0x0 TIMERCAPTURE TIMERCAPTURE 0 32 CRC Cyclic redundancy check calculation unit CRC 0x0 0x0 0x400 registers n CR CR Control register 0x8 32 read-write n 0x0 0x0 POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only REV_IN Reverse input data 5 2 read-write REV_OUT Reverse output data 7 1 read-write DR DR Data register 0x0 32 read-write n 0x0 0x0 DR Data register bits 0 32 IDR IDR Independent data register 0x4 32 read-write n 0x0 0x0 IDR General-purpose 32-bit data register bits 0 32 INIT INIT Initial CRC value 0x10 32 read-write n 0x0 0x0 INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 32 read-write n 0x0 0x0 POL Programmable polynomial 0 32 DMA Direct memory access controller DMA 0x0 0x0 0x400 registers n DMA DMA interrupt 17 CCR1 CCR1 channel 1 configuration register 0x8 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR2 CCR2 channel 2 configuration register 0x1C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR3 CCR3 channel 3 configuration register 0x30 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR4 CCR4 channel 4 configuration register 0x44 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR5 CCR5 channel 5 configuration register 0x58 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR6 CCR6 channel 6 configuration register 0x6C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR7 CCR7 channel 7 configuration register 0x80 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR8 CCR8 channel 8 configuration register 0x94 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CMAR1 CMAR1 channel x memory address register 0x14 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR2 CMAR2 channel 2 memory address register 0x28 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR3 CMAR3 channel 3 memory address register 0x3C 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR4 CMAR4 channel 4 memory address register 0x50 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR5 CMAR channel 5 memory address register 0x64 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR6 CMAR6 channel 6 memory address register 0x78 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR7 CMAR7 channel 7 memory address register 0x8C 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR8 CMAR8 channel 8 memory address register 0xA0 32 read-write n 0x0 0x0 MA Memory address 0 32 CNDTR1 CNDTR1 channel 1 number of data register 0xC 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR2 CNDTR channel 2 number of data register 0x20 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR3 CNDTR3 channel 3 number of data register 0x34 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR4 CNDTR4 channel 4 number of data register 0x48 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR5 CNDTR5 channel 5 number of data register 0x5C 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR6 CNDTR6 channel 6 number of data register 0x70 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR7 CNDTR7 channel 7 number of data register 0x84 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR8 CNDTR8 channel 8 number of data register 0x98 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CPAR1 CPAR1 channel 1 peripheral address register 0x10 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR2 CPAR2 channel 2 peripheral address register 0x24 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR3 CPAR channel 3 peripheral address register 0x38 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR4 CPAR4 channel 4 peripheral address register 0x4C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR5 CPAR5 channel 5 peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR6 CPAR6 channel 6 peripheral address register 0x74 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR7 CPAR7 channel 7 peripheral address register 0x88 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR8 CPAR8 channel 8 peripheral address register 0x9C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 IFCR IFCR interrupt flag clear register 0x4 32 write-only n 0x0 0x0 CGIF1 Channel 1 global interrupt clear 0 1 CGIF2 Channel 2 global interrupt clear 4 1 CGIF3 Channel 3 global interrupt clear 8 1 CGIF4 Channel 4 global interrupt clear 12 1 CGIF5 Channel 5 global interrupt clear 16 1 CGIF6 Channel 6 global interrupt clear 20 1 CGIF7 Channel 7 global interrupt clear 24 1 CGIF8 Channel 8 global interrupt clear 28 1 CHTIF1 Channel 1 half transfer clear 2 1 CHTIF2 Channel 2 half transfer clear 6 1 CHTIF3 Channel 3 half transfer clear 10 1 CHTIF4 Channel 4 half transfer clear 14 1 CHTIF5 Channel 5 half transfer clear 18 1 CHTIF6 Channel 6 half transfer clear 22 1 CHTIF7 Channel 7 half transfer clear 26 1 CHTIF8 Channel 8 half transfer clear 30 1 CTCIF1 Channel 1 transfer complete clear 1 1 CTCIF2 Channel 2 transfer complete clear 5 1 CTCIF3 Channel 3 transfer complete clear 9 1 CTCIF4 Channel 4 transfer complete clear 13 1 CTCIF5 Channel 5 transfer complete clear 17 1 CTCIF6 Channel 6 transfer complete clear 21 1 CTCIF7 Channel 7 transfer complete clear 25 1 CTCIF8 Channel 8 transfer complete clear 29 1 CTEIF1 Channel 1 transfer error clear 3 1 CTEIF2 Channel 2 transfer error clear 7 1 CTEIF3 Channel 3 transfer error clear 11 1 CTEIF4 Channel 4 transfer error clear 15 1 CTEIF5 Channel 5 transfer error clear 19 1 CTEIF6 Channel 6 transfer error clear 23 1 CTEIF7 Channel 7 transfer error clear 27 1 CTEIF8 Channel 8 transfer error clear 31 1 ISR ISR interrupt status register 0x0 32 read-only n 0x0 0x0 GIF1 Channel 1 global interrupt flag 0 1 GIF2 Channel 2 global interrupt flag 4 1 GIF3 Channel 3 global interrupt flag 8 1 GIF4 Channel 4 global interrupt flag 12 1 GIF5 Channel 5 global interrupt flag 16 1 GIF6 Channel 6 global interrupt flag 20 1 GIF7 Channel 7 global interrupt flag 24 1 GIF8 Channel 8 global interrupt flag 28 1 HTIF1 Channel 1 half transfer flag 2 1 HTIF2 Channel 2 half transfer flag 6 1 HTIF3 Channel 3 half transfer flag 10 1 HTIF4 Channel 4 half transfer flag 14 1 HTIF5 Channel 5 half transfer flag 18 1 HTIF6 Channel 6 half transfer flag 22 1 HTIF7 Channel 7 half transfer flag 26 1 HTIF8 Channel 8 half transfer flag 30 1 TCIF1 Channel 1 transfer complete flag 1 1 TCIF2 Channel 2 transfer complete flag 5 1 TCIF3 Channel 3 transfer complete flag 9 1 TCIF4 Channel 4 transfer complete flag 13 1 TCIF5 Channel 5 transfer complete flag 17 1 TCIF6 Channel 6 transfer complete flag 21 1 TCIF7 Channel 7 transfer complete flag 25 1 TCIF8 Channel 8 transfer complete flag 29 1 TEIF1 Channel 1 transfer error flag 3 1 TEIF2 Channel 2 transfer error flag 7 1 TEIF3 Channel 3 transfer error flag 11 1 TEIF4 Channel 4 transfer error flag 15 1 TEIF5 Channel 5 transfer error flag 19 1 TEIF6 Channel 6 transfer error flag 23 1 TEIF7 Channel 7 transfer error flag 27 1 TEIF8 Channel 8 transfer error flag 31 1 DMAMUX Direct memory access Multiplexer DMAMUX 0x0 0x0 0x400 registers n C0CR C0CR DMA Multiplexer Channel 0 Control register 0x0 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 C1CR C1CR DMA Multiplexer Channel 1 Control register 0x4 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 C2CR C2CR DMA Multiplexer Channel 2 Control register 0x8 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 C3CR C3CR DMA Multiplexer Channel 3 Control register 0xC 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 C4CR C4CR DMA Multiplexer Channel 4 Control register 0x10 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 C5CR C5CR DMA Multiplexer Channel 5 Control register 0x14 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 C6CR C6CR DMA Multiplexer Channel 6 Control register 0x18 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 C7CR C7CR DMA Multiplexer Channel 7 Control register 0x1C 32 read-write n 0x0 0x0 DMAREQ_ID DMA Request ID 0 5 FLASH FLASH FLASH 0x0 0x0 0x90 registers n FLASH NVM interrupt 0 ADDRESS ADDRESS Address register 0x18 32 read-write n 0x0 0x0 XADDR page number (from 0 to 127) row number (from 0 to 7) 6 10 YADDR word number inside the selected row (from 0 to 63) 0 6 COMMAND COMMAND Command register 0x0 32 read-write n 0x0 0x0 COMMAND Command opcode to launch any operation on Flash memory. See for command list and detail. 0 8 CONFIG CONFIG Configuration register 0x4 32 read-write n 0x0 0x0 DIS_GROUP_WRITE 2 1 LONGACCESS debug and test only 0 1 PREMAP bit to redirect boot area on IFR or main Flash. 3 1 REMAP bit to redirect boot area on SRAM0. 1 1 WAIT_STATES Number of wait states to be inserted on Flash read (AHB accesses). 4 2 DATA0 DATA0 Data register 0 0x40 32 read-write n 0x0 0x0 DATA0 this register has several usage 0 32 DATA1 DATA1 Data register 1 0x44 32 read-write n 0x0 0x0 DATA1 data that will be written at ADDRESS+1 during a BURSTWRITE command. 0 32 DATA2 DATA2 Data register 2 0x48 32 read-write n 0x0 0x0 DATA2 data that will be written at ADDRESS+2 during a BURSTWRITE command 0 32 DATA3 DATA3 Data register 3 0x4C 32 read-write n 0x0 0x0 DATA3 data that will be written at ADDRESS+3 during a BURSTWRITE command. 0 32 IRQMASK IRQMASK The mask bit in IRQMASK will mask the condition in the status register IRQSTAT and prevent the generation of the interrupt. 0xC 32 read-write n 0x0 0x0 CMDDONEM Command done mask. 0 1 CMDERRM command error mask. 2 1 CMDSTARTM Command started mask. 1 1 ILLCMDM Illegal command mask. 3 1 READOKM Mass read OK mask. 4 1 IRQRAW IRQRAW The raw status register shows the unmasked condition of interrupt events. 0x10 32 read-write n 0x0 0x0 CMDDONE_RIS Command done raw/unmasked interrupt status. 0 1 CMDERR_RIS command error raw/unmasked interrupt status. 2 1 CMDSTART_RIS Command started raw/unmasked interrupt status. 1 1 ILLCMD_RIS Illegal command raw/unmasked interrupt status. 3 1 READOK_RIS Mass read OK raw/unmasked interrupt status. 4 1 IRQSTAT IRQSTAT The interrupt status register shows the masked version of the interrupt raw register. 0x8 32 read-write n 0x0 0x0 CMDDONE_MIS Command done masked interrupt status. 0 1 CMDERR_MIS command error masked interrupt status. 2 1 CMDSTART_MIS Command started masked interrupt status. 1 1 ILLCMD_MIS Illegal command masked interrupt status. 3 1 READOK_MIS Mass read OK masked interrupt status. 4 1 LFSRVAL LFSRVAL Linear Feedback Shift register contains the signature issued by a MASSREAD command. 0x24 32 read-only n 0x0 0x0 LFSRVAL signature after a MASSREAD command, generated through a Linear Feedback Shift Register block 0 32 PAGEPROT0 PAGEPROT0 The PAGEPROTx registers allows protecting from accidental write a contiguous set of pages called segment in the following description. 0x34 32 read-write n 0x0 0x0 SEG0 First segment definition. 0 16 SEG1 second segment definition. 16 16 PAGEPROT1 PAGEPROT1 The PAGEPROTx registers allows protecting from accidental write a contiguous set of pages called segment in the following description. 0x38 32 read-write n 0x0 0x0 SEG2 third segment definition. 0 16 SEG3 fourth segment definition. 16 16 SIZE SIZE SIZE register 0x14 32 read-write n 0x0 0x0 FLASH_SECURE indicates the main FLASH is locked by a customer key. 19 1 FLASH_SIZE indicates the last usable address of the Flash using memory component address format. 0 16 RAM_SIZE indicates the size of RAM available in the device 17 2 SWD_DISABLE indicates the SWD JTAG is disabled on the device 20 1 TIMETRIM1 TIMETRIM1 Time trim registers 1 0x28 32 read-write n 0x0 0x0 T_ERASE Page erase time. 0 8 T_ME Mass erase time. 8 8 T_NVH NVSTR hold time. 16 8 T_RCV Recovery time. 24 8 TIMETRIM2 TIMETRIM2 Time trim registers 2 0x2C 32 read-write n 0x0 0x0 T_NVH1 NVSTR hold time for mass erase 8 8 T_NVS NVSTR setup time 0 8 T_PGS NVSTR to PROGRAM setup time 24 8 T_PROG Program time 16 8 TIMETRIM3 TIMETRIM3 Time trim registers 3 0x30 32 read-write n 0x0 0x0 T_WK Wakeup time. 0 8 GPIOA General-purpose I/Os GPIOA 0x0 0x0 0x400 registers n GPIOA GPIOA interrupt 15 AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFSEL10 Alternate function selection for port A bit 10 8 4 AFSEL11 Alternate function selection for port A bit 11 12 4 AFSEL12 Alternate function selection for port A bit 12 16 4 AFSEL13 Alternate function selection for port A bit 13 20 4 AFSEL14 Alternate function selection for port A bit 14 24 4 AFSEL15 Alternate function selection for port A bit 15 28 4 AFSEL8 Alternate function selection for port A bit 8 0 4 AFSEL9 Alternate function selection for port A bit 9 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFSEL0 Alternate function selection for port A bit 0 0 4 AFSEL1 Alternate function selection for port A bit 1 4 4 AFSEL2 Alternate function selection for port A bit 2 8 4 AFSEL3 Alternate function selection for port A bit 3 12 4 AFSEL4 Alternate function selection for port A bit 4 16 4 AFSEL5 Alternate function selection for port A bit 5 20 4 AFSEL6 Alternate function selection for port A bit 6 24 4 AFSEL7 Alternate function selection for port A bit 7 28 4 BRR BRR GPIO alternate function high register 0x28 32 write-only n 0x0 0x0 BR0 Port A output data bit 0 0 1 BR1 Port A output data bit 1 1 1 BR10 Port A output data bit 10 10 1 BR11 Port A output data bit 11 11 1 BR12 Port A output data bit 12 12 1 BR13 Port A output data bit 13 13 1 BR14 Port A output data bit 14 14 1 BR15 Port A output data bit 15 15 1 BR2 Port A output data bit 2 2 1 BR3 Port A output data bit 3 3 1 BR4 Port A output data bit 4 4 1 BR5 Port A output data bit 5 5 1 BR6 Port A output data bit 6 6 1 BR7 Port A output data bit 7 7 1 BR8 Port A output data bit 8 8 1 BR9 Port A output data bit 9 9 1 BSRR BSRR GPIO port A bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port A set bit 0 16 1 BR1 Port A reset bit 1 17 1 BR10 Port A reset bit 10 26 1 BR11 Port A reset bit 11 27 1 BR12 Port A reset bit 12 28 1 BR13 Port A reset bit 13 29 1 BR14 Port A reset bit 14 30 1 BR15 Port A reset bit 15 31 1 BR2 Port A reset bit 2 18 1 BR3 Port A reset bit 3 19 1 BR4 Port A reset bit 4 20 1 BR5 Port A reset bit 5 21 1 BR6 Port A reset bit 6 22 1 BR7 Port A reset bit 7 23 1 BR8 Port A reset bit 8 24 1 BR9 Port A reset bit 9 25 1 BS0 Port A set bit 0 0 1 BS1 Port A set bit 1 1 1 BS10 Port A set bit 10 10 1 BS11 Port A set bit 11 11 1 BS12 Port A set bit 12 12 1 BS13 Port A set bit 13 13 1 BS14 Port A set bit 14 14 1 BS15 Port A set bit 15 15 1 BS2 Port A set bit 2 2 1 BS3 Port A set bit 3 3 1 BS4 Port A set bit 4 4 1 BS5 Port A set bit 5 5 1 BS6 Port A set bit 6 6 1 BS7 Port A set bit 7 7 1 BS8 Port A set bit 8 8 1 BS9 Port A set bit 9 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 ID0 Port A input data bit 0 0 1 ID1 Port A input data bit 1 1 1 ID10 Port A input data bit 10 10 1 ID11 Port A input data bit 11 11 1 ID12 Port A input data bit 12 12 1 ID13 Port A input data bit 13 13 1 ID14 Port A input data bit 14 14 1 ID15 Port A input data bit 15 15 1 ID2 Port A input data bit 2 2 1 ID3 Port A input data bit 3 3 1 ID4 Port A input data bit 4 4 1 ID5 Port A input data bit 5 5 1 ID6 Port A input data bit 6 6 1 ID7 Port A input data bit 7 7 1 ID8 Port A input data bit 8 8 1 ID9 Port A input data bit 9 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port A lock bit 0 0 1 LCK1 Port A lock bit 1 1 1 LCK10 Port A lock bit 10 10 1 LCK11 Port A lock bit 11 11 1 LCK12 Port A lock bit 12 12 1 LCK13 Port A lock bit 13 13 1 LCK14 Port A lock bit 14 14 1 LCK15 Port A lock bit 15 15 1 LCK2 Port A lock bit 2 2 1 LCK3 Port A lock bit 3 3 1 LCK4 Port A lock bit 4 4 1 LCK5 Port A lock bit 5 5 1 LCK6 Port A lock bit 6 6 1 LCK7 Port A lock bit 7 7 1 LCK8 Port A lock bit 8 8 1 LCK9 Port A lock bit 9 9 1 LCKK Lock key. This bit can be read any time. It can only be modified using the lock key write sequence. 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODE0 Port A configuration bit 0 0 2 MODE1 Port A configuration bit 1 2 2 MODE10 Port A configuration bit 10 20 2 MODE11 Port A configuration bit 11 22 2 MODE12 Port A configuration bit 12 24 2 MODE13 Port A configuration bit 13 26 2 MODE14 Port A configuration bit 14 28 2 MODE15 Port A configuration bit 15 30 2 MODE2 Port A configuration bit 2 4 2 MODE3 Port A configuration bit 3 6 2 MODE4 Port A configuration bit 4 8 2 MODE5 Port A configuration bit 5 10 2 MODE6 Port A configuration bit 6 12 2 MODE7 Port A configuration bit 7 14 2 MODE8 Port A configuration bit 8 16 2 MODE9 Port A configuration bit 9 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 OD0 Port A output data bit 0 0 1 OD1 Port A output data bit 1 1 1 OD10 Port A output data bit 10 10 1 OD11 Port A output data bit 11 11 1 OD12 Port A output data bit 12 12 1 OD13 Port A output data bit 13 13 1 OD14 Port A output data bit 14 14 1 OD15 Port A output data bit 15 15 1 OD2 Port A output data bit 2 2 1 OD3 Port A output data bit 3 3 1 OD4 Port A output data bit 4 4 1 OD5 Port A output data bit 5 5 1 OD6 Port A output data bit 6 6 1 OD7 Port A output data bit 7 7 1 OD8 Port A output data bit 8 8 1 OD9 Port A output data bit 9 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEED0 Port A configuration bit 0 0 2 OSPEED1 Port A configuration bit 1 2 2 OSPEED10 Port A configuration bit 10 20 2 OSPEED11 Port A configuration bit 11 22 2 OSPEED12 Port A configuration bit 12 24 2 OSPEED13 Port A configuration bit 13 26 2 OSPEED14 Port A configuration bit 14 28 2 OSPEED15 Port A configuration bit 15 30 2 OSPEED2 Port A configuration bit 2 4 2 OSPEED3 Port A configuration bit 3 6 2 OSPEED4 Port A configuration bit 4 8 2 OSPEED5 Port A configuration bit 5 10 2 OSPEED6 Port A configuration bit 6 12 2 OSPEED7 Port A configuration bit 7 14 2 OSPEED8 Port A configuration bit 8 16 2 OSPEED9 Port A configuration bit 9 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port A configuration bit 0 0 1 OT1 Port A configuration bit 1 1 1 OT10 Port A configuration bit 10 10 1 OT11 Port A configuration bit 11 11 1 OT12 Port A configuration bit 12 12 1 OT13 Port A configuration bit 13 13 1 OT14 Port A configuration bit 14 14 1 OT15 Port A configuration bit 15 15 1 OT2 Port A configuration bit 2 2 1 OT3 Port A configuration bit 3 3 1 OT4 Port A configuration bit 4 4 1 OT5 Port A configuration bit 5 5 1 OT6 Port A configuration bit 6 6 1 OT7 Port A configuration bit 7 7 1 OT8 Port A configuration bit 8 8 1 OT9 Port A configuration bit 9 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPD0 Port A configuration bit 0 0 2 PUPD1 Port A configuration bit 1 2 2 PUPD10 Port A configuration bit 10 20 2 PUPD11 Port A configuration bit 11 22 2 PUPD12 Port A configuration bit 12 24 2 PUPD13 Port A configuration bit 13 26 2 PUPD14 Port A configuration bit 14 28 2 PUPD15 Port A configuration bit 15 30 2 PUPD2 Port A configuration bit 2 4 2 PUPD3 Port A configuration bit 3 6 2 PUPD4 Port A configuration bit 4 8 2 PUPD5 Port A configuration bit 5 10 2 PUPD6 Port A configuration bit 6 12 2 PUPD7 Port A configuration bit7 14 2 PUPD8 Port A configuration bit 8 16 2 PUPD9 Port A configuration bit 9 18 2 GPIOB General-purpose I/Os GPIOB 0x0 0x0 0x400 registers n GPIOB GPIOB interrupt 16 AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFSEL10 Alternate function selection for port A bit 10 8 4 AFSEL11 Alternate function selection for port A bit 11 12 4 AFSEL12 Alternate function selection for port A bit 12 16 4 AFSEL13 Alternate function selection for port A bit 13 20 4 AFSEL14 Alternate function selection for port A bit 14 24 4 AFSEL15 Alternate function selection for port A bit 15 28 4 AFSEL8 Alternate function selection for port A bit 8 0 4 AFSEL9 Alternate function selection for port A bit 9 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFSEL0 Alternate function selection for port A bit 0 0 4 AFSEL1 Alternate function selection for port A bit 1 4 4 AFSEL2 Alternate function selection for port A bit 2 8 4 AFSEL3 Alternate function selection for port A bit 3 12 4 AFSEL4 Alternate function selection for port A bit 4 16 4 AFSEL5 Alternate function selection for port A bit 5 20 4 AFSEL6 Alternate function selection for port A bit 6 24 4 AFSEL7 Alternate function selection for port A bit 7 28 4 BRR BRR GPIO alternate function high register 0x28 32 write-only n 0x0 0x0 BR0 Port B output data bit 0 0 1 BR1 Port B output data bit 1 1 1 BR10 Port B output data bit 10 10 1 BR11 Port B output data bit 11 11 1 BR12 Port B output data bit 12 12 1 BR13 Port B output data bit 13 13 1 BR14 Port B output data bit 14 14 1 BR15 Port B output data bit 15 15 1 BR2 Port B output data bit 2 2 1 BR3 Port B output data bit 3 3 1 BR4 Port B output data bit 4 4 1 BR5 Port B output data bit 5 5 1 BR6 Port B output data bit 6 6 1 BR7 Port B output data bit 7 7 1 BR8 Port B output data bit 8 8 1 BR9 Port B output data bit 9 9 1 BSRR BSRR GPIO port A bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port B set bit 0 16 1 BR1 Port B reset bit 1 17 1 BR10 Port B reset bit 10 26 1 BR11 Port B reset bit 11 27 1 BR12 Port B reset bit 12 28 1 BR13 Port B reset bit 13 29 1 BR14 Port B reset bit 14 30 1 BR15 Port B reset bit 15 31 1 BR2 Port B reset bit 2 18 1 BR3 Port B reset bit 3 19 1 BR4 Port B reset bit 4 20 1 BR5 Port B reset bit 5 21 1 BR6 Port B reset bit 6 22 1 BR7 Port B reset bit 7 23 1 BR8 Port B reset bit 8 24 1 BR9 Port B reset bit 9 25 1 BS0 Port B set bit 0 0 1 BS1 Port B set bit 1 1 1 BS10 Port B set bit 10 10 1 BS11 Port B set bit 11 11 1 BS12 Port B set bit 12 12 1 BS13 Port B set bit 13 13 1 BS14 Port B set bit 14 14 1 BS15 Port B set bit 15 15 1 BS2 Port B set bit 2 2 1 BS3 Port B set bit 3 3 1 BS4 Port B set bit 4 4 1 BS5 Port B set bit 5 5 1 BS6 Port B set bit 6 6 1 BS7 Port B set bit 7 7 1 BS8 Port B set bit 8 8 1 BS9 Port B set bit 9 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 ID0 Port B input data bit 0 0 1 ID1 Port B input data bit 1 1 1 ID10 Port B input data bit 10 10 1 ID11 Port B input data bit 11 11 1 ID12 Port B input data bit 12 12 1 ID13 Port B input data bit 13 13 1 ID14 Port B input data bit 14 14 1 ID15 Port B input data bit 15 15 1 ID2 Port B input data bit 2 2 1 ID3 Port B input data bit 3 3 1 ID4 Port B input data bit 4 4 1 ID5 Port B input data bit 5 5 1 ID6 Port B input data bit 6 6 1 ID7 Port B input data bit 7 7 1 ID8 Port B input data bit 8 8 1 ID9 Port B input data bit 9 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port B lock bit 0 0 1 LCK1 Port B lock bit 1 1 1 LCK10 Port B lock bit 10 10 1 LCK11 Port B lock bit 11 11 1 LCK12 Port B lock bit 12 12 1 LCK13 Port B lock bit 13 13 1 LCK14 Port B lock bit 14 14 1 LCK15 Port B lock bit 15 15 1 LCK2 Port B lock bit 2 2 1 LCK3 Port B lock bit 3 3 1 LCK4 Port B lock bit 4 4 1 LCK5 Port B lock bit 5 5 1 LCK6 Port B lock bit 6 6 1 LCK7 Port B lock bit 7 7 1 LCK8 Port B lock bit 8 8 1 LCK9 Port B lock bit 9 9 1 LCKK Lock key. This bit can be read any time. It can only be modified using the lock key write sequence. 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODE0 Port B configuration bit 0 0 2 MODE1 Port B configuration bit 1 2 2 MODE10 Port B configuration bit 10 20 2 MODE11 Port B configuration bit 11 22 2 MODE12 Port B configuration bit 12 24 2 MODE13 Port B configuration bit 13 26 2 MODE14 Port B configuration bit 14 28 2 MODE15 Port B configuration bit 15 30 2 MODE2 Port B configuration bit 2 4 2 MODE3 Port B configuration bit 3 6 2 MODE4 Port B configuration bit 4 8 2 MODE5 Port B configuration bit 5 10 2 MODE6 Port B configuration bit 6 12 2 MODE7 Port B configuration bit 7 14 2 MODE8 Port B configuration bit 8 16 2 MODE9 Port B configuration bit 9 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 OD0 Port B output data bit 0 0 1 OD1 Port B output data bit 1 1 1 OD10 Port B output data bit 10 10 1 OD11 Port B output data bit 11 11 1 OD12 Port B output data bit 12 12 1 OD13 Port B output data bit 13 13 1 OD14 Port B output data bit 14 14 1 OD15 Port B output data bit 15 15 1 OD2 Port B output data bit 2 2 1 OD3 Port B output data bit 3 3 1 OD4 Port B output data bit 4 4 1 OD5 Port B output data bit 5 5 1 OD6 Port B output data bit 6 6 1 OD7 Port B output data bit 7 7 1 OD8 Port B output data bit 8 8 1 OD9 Port B output data bit 9 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEED0 Port B configuration bit 0 0 2 OSPEED1 Port B configuration bit 1 2 2 OSPEED10 Port B configuration bit 10 20 2 OSPEED11 Port B configuration bit 11 22 2 OSPEED12 Port B configuration bit 12 24 2 OSPEED13 Port B configuration bit 13 26 2 OSPEED14 Port B configuration bit 14 28 2 OSPEED15 Port B configuration bit 15 30 2 OSPEED2 Port B configuration bit 2 4 2 OSPEED3 Port B configuration bit 3 6 2 OSPEED4 Port B configuration bit 4 8 2 OSPEED5 Port B configuration bit 5 10 2 OSPEED6 Port B configuration bit 6 12 2 OSPEED7 Port B configuration bit 7 14 2 OSPEED8 Port B configuration bit 8 16 2 OSPEED9 Port B configuration bit 9 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port B configuration bit 0 0 1 OT1 Port B configuration bit 1 1 1 OT10 Port B configuration bit 10 10 1 OT11 Port B configuration bit 11 11 1 OT12 Port B configuration bit 12 12 1 OT13 Port B configuration bit 13 13 1 OT14 Port B configuration bit 14 14 1 OT15 Port B configuration bit 15 15 1 OT2 Port B configuration bit 2 2 1 OT3 Port B configuration bit 3 3 1 OT4 Port B configuration bit 4 4 1 OT5 Port B configuration bit 5 5 1 OT6 Port B configuration bit 6 6 1 OT7 Port B configuration bit 7 7 1 OT8 Port B configuration bit 8 8 1 OT9 Port B configuration bit 9 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPD0 Port B configuration bit 0 0 2 PUPD1 Port B configuration bit 1 2 2 PUPD10 Port B configuration bit 10 20 2 PUPD11 Port B configuration bit 11 22 2 PUPD12 Port B configuration bit 12 24 2 PUPD13 Port B configuration bit 13 26 2 PUPD14 Port B configuration bit 14 28 2 PUPD15 Port B configuration bit 15 30 2 PUPD2 Port B configuration bit 2 4 2 PUPD3 Port B configuration bit 3 6 2 PUPD4 Port B configuration bit 4 8 2 PUPD5 Port B configuration bit 5 10 2 PUPD6 Port B configuration bit 6 12 2 PUPD7 Port B configuration bit7 14 2 PUPD8 Port B configuration bit 8 16 2 PUPD9 Port B configuration bit 9 18 2 I2C1 Inter-integrated circuit I2C1 0x0 0x0 0x400 registers n I2C1 I2C1 interrurpt 3 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 read-only NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 read-only RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 read-only STOP Stop generation (master mode) 14 1 read-only ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 IWDG Independent watchdog IWDG 0x0 0x0 0x400 registers n KR KR Key register 0x0 32 write-only n 0x0 0x0 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 32 read-write n 0x0 0x0 RL Watchdog counter reload value 0 12 SR SR Status register 0xC 32 read-only n 0x0 0x0 PVU Watchdog prescaler prescaler update 0 1 RVU Watchdog counter reload prescaler update 1 1 WVU Watchdog counter window prescaler update 2 1 WINR WINR Window register 0x10 32 read-write n 0x0 0x0 WIN Watchdog counter window value 0 12 LPUART1 Universal synchronous asynchronous receiver transmitter LPUART1 0x0 0x0 0x400 registers n LPUART Low Power UART interrupt 9 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR BRR 0 20 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT_0 DEAT0 21 1 DEAT_1 DEAT1 22 1 DEAT_2 DEAT2 23 1 DEAT_3 DEAT3 24 1 DEAT_4 Driver Enable assertion time 25 1 DEDT_0 DEDT0 16 1 DEDT_1 DEDT1 17 1 DEDT_2 DEDT2 18 1 DEDT_3 DEDT3 19 1 DEDT_4 Driver Enable de-assertion time 20 1 FIFOEN FIFOEN 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RXFFIE RXFFIE 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFEIE 30 1 UE USART enable 0 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit address Detection 4 1 DATAINV Binary data inversion 18 1 MSBFIRST Most significant bit first 19 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFTIE 28 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE TXFIFO threshold interrupt enable 23 1 ICR ICR Interrupt flag clear register 0x20 32 read-write n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 NECF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 FE FE 1 1 IDLE IDLE 4 1 NE START bit Noise detection flag 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER_0 PRESCALER_0 0 1 PRESCALER_1 PRESCALER_1 1 1 PRESCALER_2 PRESCALER_2 2 1 PRESCALER_3 PRESCALER_3 3 1 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ TXFRQ 4 1 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 PKA PKA PKA 0x0 0x0 0x1000 registers n PKA PKA interrupt 13 CSR Command and status register 0x0 32 read-write n 0x0 0x0 GO PKA start processing command:

• 0: has no effect.
• 1: starts the processing.

After this bitfield is written to 1, it must be written back to zero manually. 0 1 write-only READY PKA readiness status:

• 0: the PKA is computing. It is not ready.
• 1: the PKA is ready to start a new processing.

The rising edge of the READY bit set the PROC_END flag in the ISR register. 1 1 read-only SFT_RST PKA software reset:

• 0: has no effect.
• 1: reset the PKA peripheral.

After this bitfield is written to 1, it must be written back to zero manually. 7 1 write-only IEN Interrupt enable register 0x8 32 read-write n 0x0 0x0 ADDERR_EN AHB address error interrupt enable.

• 0: interrupt disabled.
• 1: interrupt enabled.

3 1 RAMERR_EN RAM access error interrupt enable.

• 0: interrupt disabled.
• 1: interrupt enabled.

2 1 READY_EN READY_EN 0 1 ISR Interrupt status register 0x4 32 read-write n 0x0 0x0 ADD_ERR AHB address error interrupt. When read:

• 0: All AHB read or write access to the PKA RAM occurred in a mapped address range.
• 1: All AHB read or write access to the PKA RAM occurred in an unmapped address range.

When written:

• 0: no effect.
• 1: clears the AHB Address error interrupt.

3 1 PROC_END PKA process ending interrupt. When read:

• 0: no event.
• 1: PKA process is ended.

When written:

• 0: no effect.
• 1: clears the PKA process ending interrupt.

0 1 RAM_ERR RAM read / write access error interrupt. When read:

• 0: All AHB read or write access to the PKA RAM occurred while the PKA was stopped.
• 1: All the AHB read or write access to the PKA RAM occurred while the PKA was operating and using the internal RAM. Those read or write could not succeed as the PKA internal RAM is disconnected from the AHB bus when the PKA is operating (READY bit low).

When written:

• 0: no effect.
• 1: clears the RAM access error interrupt.

2 1 PWR Power control PWR 0x0 0x0 0x400 registers n CR1 CR1 Power control register 1 0x0 32 read-write n 0x0 0x0 APC Apply Pull-up and pull-down configuration from CPU 4 1 LPMS Low Power Mode Selection 0 1 CR2 CR2 Power control register 2 0x4 32 read-write n 0x0 0x0 ENTS Enable Temperature Sensor 9 1 LSILPMUFEN LSI LPMU Force ENable 10 1 PVDE Programmable Voltage Detector Enable 0 1 PVDLS Programmable Voltage Detector Level selection 1 3 RAMRET1 RAM1 retention during low power mode 5 1 RAMRET2 RAM2 retention during low power mode 6 1 RAMRET3 RAM3 retention during low power mode 7 1 SCALEMR Voltage scaling Main Regulator Selection. 8 1 CR3 CR3 Power control register 3 0x8 32 read-write n 0x0 0x0 EIWL Enable internal WakeUp line 15 1 EWBLE Wakeup BLE Enable 12 1 EWBLEHCPU EWBLEHCPU Wakeup BLE Host CPU Enable 13 1 EWU0 Enable WakeUp line 0 0 1 EWU1 Enable WakeUp line 1 1 1 EWU10 Enable WakeUp line 10 10 1 EWU11 Enable WakeUp line 11 11 1 EWU2 Enable WakeUp line 2 2 1 EWU3 Enable WakeUp line 3 3 1 EWU4 Enable WakeUp line 4 4 1 EWU5 Enable WakeUp line 5 5 1 EWU6 Enable WakeUp line 6 6 1 EWU7 Enable WakeUp line 7 7 1 EWU8 Enable WakeUp line 8 8 1 EWU9 Enable WakeUp line 9 9 1 CR4 CR4 Power control register 4 0xC 32 read-write n 0x0 0x0 WUP0 Wakeup polarity for PB0 IO event. 0 1 WUP1 Wakeup polarity for PB1 IO event. 1 1 WUP10 Wakeup polarity for PA10 I/O. 10 1 WUP11 Wakeup polarity for PA11 I/O. 11 1 WUP2 Wakeup polarity for PB2 IO event. 2 1 WUP3 Wakeup polarity for PB3 IO event. 3 1 WUP4 Wakeup polarity for PB4 IO event. 4 1 WUP5 Wakeup polarity for PB5 IO event. 5 1 WUP6 Wakeup polarity for PB6 IO event. 6 1 WUP7 Wakeup polarity for PB7 IO event. 7 1 WUP8 Wakeup polarity for PA8 IO event. 8 1 WUP9 Wakeup polarity for PA9 IO event. 9 1 CR5 CR5 Power control register 5 0x1C 32 read-write n 0x0 0x0 CLKDETR_DISABLE disable the SMPS clock detection 12 1 NOSMPS No SMPS Mode 10 1 SMPSBOMSEL SMPS BOM Selection 4 2 SMPSFBYP Force SMPS Regulator in bypass mode 9 1 SMPSFRDY Force ready check 7 1 SMPSLPOPEN In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). 8 1 SMPSLVL SMPS Output Level Voltage Selection 0 4 SMPS_ENA_DCM Discontinuous conduction mode enable. 11 1 CR6 CR6 This register manages the selection of the wakeup sources to get out of DEEPSTOP mode 0x30 32 read-write n 0x0 0x0 EWU12 Enable wakeup on PA0 I/O event. 0 1 EWU13 Enable wakeup on PA1 I/O event. 1 1 EWU14 Enable wakeup on PA2 I/O event. 2 1 EWU15 Enable wakeup on PA3 I/O event. 3 1 EWU16 Enable wakeup on PA4 I/O event. 4 1 EWU17 Enable wakeup on PA5 I/O event. 5 1 EWU18 Enable wakeup on PA6 I/O event. 6 1 EWU19 Enable wakeup on PA7 I/O event. 7 1 EWU20 Enable wakeup on PB8 I/O event. 8 1 EWU21 Enable wakeup on PB9 I/O event. 9 1 EWU22 Enable wakeup on PB10 I/O event. 10 1 EWU23 Enable wakeup on PB11 I/O event. 11 1 EWU24 Enable wakeup on PA12 I/O event. 12 1 EWU25 Enable wakeup on PA13 I/O event. 13 1 EWU26 Enable wakeup on PA14 I/O event. 14 1 EWU27 Enable wakeup on PA15 I/O event. 15 1 CR7 CR7 This register manages the polarity for the I/Os wakeup sources to get out of DEEPSTOP 0x34 32 read-write n 0x0 0x0 WUP12 Wakeup polarity for PA0 IO event. 0 1 WUP13 Wakeup polarity for PA1 IO event. 1 1 WUP14 Wakeup polarity for PA2 IO event. 2 1 WUP15 Wakeup polarity for PA3 IO event. 3 1 WUP16 Wakeup polarity for PA4 IO event. 4 1 WUP17 Wakeup polarity for PA5 IO event. 5 1 WUP18 Wakeup polarity for PA6 IO event. 6 1 WUP19 Wakeup polarity for PA7 IO event. 7 1 WUP20 Wakeup polarity for PB8 IO event. 8 1 WUP21 Wakeup polarity for PB9 IO event. 9 1 WUP22 Wakeup polarity for PB10 I/O. 10 1 WUP23 Wakeup polarity for PB11 I/O. 11 1 WUP24 Wakeup polarity for PA12 I/O. 12 1 WUP25 Wakeup polarity for PA13 IO event. 13 1 WUP26 Wakeup polarity for PA14 I/O. 14 1 WUP27 Wakeup polarity for PA15 I/O. 15 1 DBG1 DBG1 This register shows the current states of the FLASH FSM and SMPS FSM. 0x98 32 read-only n 0x0 0x0 FLASH_FSM_STATE Indicates the current state of the FLASH FSM inside the PWRC 8 3 SMPS_FSM_STATE Indicates the current state of the SMPS FSM inside the PWRC. 0 3 DBG2 DBG2 This register shows the current states of the FLASH FSM and SMPS FSM. 0x9C 32 read-only n 0x0 0x0 PMU_FSM_STATE Indicates the current state of the PMU FSM inside the PWRC. 0 4 RAM_FSM_STATE Indicates the current state of the RAM FSM inside the PWRC 8 2 DBGR DBGR This register is used for debug features 0x84 32 read-write n 0x0 0x0 DEEPSTOP2 DEEPSTOP2 low power saving emulation enable. 0 1 DBGSMPS DBGSMPS This register drives some control signals for the SMPS 0x8C 32 read-write n 0x0 0x0 CTLRES_RAMP CTLRES_RAMP_3V3 SMPS control signal. 9 1 DIS_BIG_MOS DIS_BIG_MOS_3V3 SMPS control signal. 10 1 HOT_STUP HOT_STUP_3V3 SMPS control signal. 6 1 NO_STUP NO_STUP_3V3 SMPS control signal. 7 1 TESTDIG SMPS_TEST_DIG_3V3[3:0] control bus. 0 4 TESTILIM SMPS_TEST_ILIM_3V3 control signal. 8 1 TESTKEL SMPS_TEST_KEL_3V3[2:0] control bus. 4 2 TEST_OL TEST_OL_3V3 SMPS control signal. 11 1 ENGTRIM ENGTRIM This register allows the software overloading the hardware trimming flashed at EWS. 0x94 32 read-write n 0x0 0x0 SMPSTRIMEN SMPS_TRIM software overload enable. 10 1 SMPS_TRIM SMPS output voltage trimming chosen by the software. 11 4 TRIMLSILPMUEN TRIM_LSI_LPMU software overload enable. 0 1 TRIMMREN TRIM_MR software overload enable. 5 1 TRIM_LSI_LPMU LPMU low speed internal oscillator trimming chosen by the software. 1 4 TRIM_MR Main regulator voltage trimming chosen by the software. 6 4 EXTSRR EXTSRR Power status clear register 0x88 32 read-write n 0x0 0x0 DEEPSTOPF System DeepStop Flag 9 1 RFPHASEF RFPHAS Flag 10 1 IOxCFG IOxCFG IO DEEPSTOP drive configuration register 0x40 32 read-write n 0x0 0x0 IOCFG0 Drive configuration for PA8. 0 2 IOCFG1 Drive configuration for PA9. 2 2 IOCFG2 Drive configuration for PA10. 4 2 IOCFG3 Drive configuration for PA11. 6 2 IOCFG4 Drive configuration for PA4. 8 2 IOCFG5 Drive configuration for PA5. 10 2 IOCFG6 Drive configuration for PA6. 12 2 IOCFG7 Drive configuration for PA7. 14 2 PDCRA PDCRA Power Port A pull-down control register 0x24 32 read-write n 0x0 0x0 PDA0 Port A pull-down bit 0 0 1 PDA1 Port A pull-down bit 1 1 1 PDA10 Port A pull-down bit 10 10 1 PDA11 Port A pull-down bit 11 11 1 PDA12 Port A pull-down bit 12 12 1 PDA13 Port A pull-down bit 13 13 1 PDA14 Port A pull-down bit 14 14 1 PDA15 Port A pull-down bit 15 15 1 PDA2 Port A pull-down bit 2 2 1 PDA3 Port A pull-down bit 3 3 1 PDA4 Port A pull-down bit 4 4 1 PDA5 Port A pull-down bit 5 5 1 PDA6 Port A pull-down bit 6 6 1 PDA7 Port A pull-down bit 7 7 1 PDA8 Port A pull-down bit 8 8 1 PDA9 Port A pull-down bit 9 9 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 32 read-write n 0x0 0x0 PDB0 Port B pull-down bit 0 0 1 PDB1 Port B pull-down bit 1 1 1 PDB10 Port B pull-down bit 10 10 1 PDB11 Port B pull-down bit 11 11 1 PDB12 Port B pull-down bit 12 12 1 PDB13 Port B pull-down bit 13 13 1 PDB14 Port B pull-down bit 14 14 1 PDB15 Port B pull-down bit 15 15 1 PDB2 Port B pull-down bit 2 2 1 PDB3 Port B pull-down bit 3 3 1 PDB4 Port B pull-down bit 4 4 1 PDB5 Port B pull-down bit 5 5 1 PDB6 Port B pull-down bit 6 6 1 PDB7 Port B pull-down bit 7 7 1 PDB8 Port B pull-down bit 8 8 1 PDB9 Port B pull-down bit 9 9 1 PUCRA PUCRA Power Port A pull-up control register 0x20 32 read-write n 0x0 0x0 PUA0 Port A PAll-up bit 0 0 1 PUA1 Port A PAll-up bit 1 1 1 PUA10 Port A PAll-up bit 10 10 1 PUA11 Port A PAll-up bit 11 11 1 PUA12 Port A PAll-up bit 12 12 1 PUA13 Port A PAll-up bit 13 13 1 PUA14 Port A PAll-up bit 14 14 1 PUA15 Port A PAll-up bit 15 15 1 PUA2 Port A PAll-up bit 2 2 1 PUA3 Port A PAll-up bit 3 3 1 PUA4 Port A PAll-up bit 4 4 1 PUA5 Port A PAll-up bit 5 5 1 PUA6 Port A PAll-up bit 6 6 1 PUA7 Port A PAll-up bit 7 7 1 PUA8 Port A PAll-up bit 8 8 1 PUA9 Port A PAll-up bit 9 9 1 PUCRB PUCRB Power Port B pull-up control register 0x28 32 read-write n 0x0 0x0 PUB0 Port B PBll-up bit 0 0 1 PUB1 Port B PBll-up bit 1 1 1 PUB10 Port B PBll-up bit 10 10 1 PUB11 Port B PBll-up bit 11 11 1 PUB12 Port B PBll-up bit 12 12 1 PUB13 Port B PBll-up bit 13 13 1 PUB14 Port B PBll-up bit 14 14 1 PUB15 Port B PBll-up bit 15 15 1 PUB2 Port B PBll-up bit 2 2 1 PUB3 Port B PBll-up bit 3 3 1 PUB4 Port B PBll-up bit 4 4 1 PUB5 Port B PBll-up bit 5 5 1 PUB6 Port B PBll-up bit 6 6 1 PUB7 Port B PBll-up bit 7 7 1 PUB8 Port B PBll-up bit 8 8 1 PUB9 Port B PBll-up bit 9 9 1 SR1 SR1 Power status register 1 0x10 32 read-write n 0x0 0x0 IWUF WakeUp Flag Internal 15 1 WBLEF Wakeup BLE Flag 12 1 WBLEHCPUF Wakeup BLE HOST CPU Flag (cf. user manual) 13 1 WUF0 WakeUp Flag 0 0 1 WUF1 WakeUp Flag 1 1 1 WUF10 WakeUp Flag 10 10 1 WUF11 WakeUp Flag 11 11 1 WUF2 WakeUp Flag 2 2 1 WUF3 WakeUp Flag 3 3 1 WUF4 WakeUp Flag 4 4 1 WUF5 WakeUp Flag 5 5 1 WUF6 WakeUp Flag 6 6 1 WUF7 WakeUp Flag 7 7 1 WUF8 WakeUp Flag 8 8 1 WUF9 WakeUp Flag 9 9 1 SR2 SR2 Power status register 2 0x14 32 read-only n 0x0 0x0 IOBOOTVAL 12 4 PVDO Power Voltage Detector Output 11 1 REGLPS Regulator Low Power Started 8 1 REGMS Regulator Main LDO Started 9 1 SMPSBYPR SMPS Force Bypass Control Replica 0 1 SMPSENR SMPS Enable Control Replica 1 1 SMPSRDY SMPS Ready Status 2 1 SR3 SR3 This register provides the information concerning which source woke up the device after a DEEPSTOP. 0x38 32 read-write n 0x0 0x0 WUF12 PA0 I/O wakeup flag. 0 1 WUF13 PA1 I/O wakeup flag. 1 1 WUF14 PA2 I/O wakeup flag. 2 1 WUF15 PA3 I/O wakeup flag. 3 1 WUF16 PA4 I/O wakeup flag. 4 1 WUF17 PA5 I/O wakeup flag. 5 1 WUF18 PA6 I/O wakeup flag. 6 1 WUF19 PA7 I/O wakeup flag. 7 1 WUF20 PB8 I/O wakeup flag. 8 1 WUF21 PB9 I/O wakeup flag. 9 1 WUF22 PB10 I/O wakeup flag. 10 1 WUF23 PB11 I/O wakeup flag. 11 1 WUF24 PA12 I/O wakeup flag. 12 1 WUF25 PA13 I/O wakeup flag. 13 1 WUF26 PA14 I/O wakeup flag. 14 1 WUF27 PA15 I/O wakeup flag. 15 1 TRIMR TRIMR This register provides the trimming values applied by hardware according to the trimming done at EWS. 0x90 32 read-only n 0x0 0x0 RAM_SIZE Indicates the RAM size available in the device. 12 2 SMPS_TRIM SMPS_TRIM 8 4 TRIM_LSI_LPMU LPMU low speed internal oscillator trimming. 0 4 TRIM_MR Main regulator voltage trimming. 4 4 RADIO_CTRL Radio Controller RADIO_CTRL 0x0 0x0 0x400 registers n RADIO_CTRL_IRQn Radio Control interrupt 21 CLK32COUNT CLK32COUNT Window length register 0x4 32 read-write n 0x0 0x0 CLK32FREQUENCY CLK32FREQUENCY Slow clock frequency register 0xC 32 read-only n 0x0 0x0 CLK32PERIOD CLK32PERIOD Slow clock period register 0x8 32 read-only n 0x0 0x0 RADIO_CONTROL_ID RADIO_CONTROL_ID Radio Controller ID register 0x0 32 read-only n 0x0 0x0 IDENTIFICATION IDENTIFICATION 0 32 RADIO_CONTROL_IRQ_ENABLE RADIO_CONTROL_IRQ_ENABLE Radio Controller Interrupt Control register 0x14 32 read-write n 0x0 0x0 RADIO_FSM_IRQ_MASK RADIO_FSM_IRQ_MASK 8 6 SLOW_CLK_IRQ_MASK SLOW_CLK_IRQ_MASK 0 1 RADIO_CONTROL_IRQ_STATUS RADIO_CONTROL_IRQ_STATUS Radio Controller Interrupt Status register 0x10 32 read-write n 0x0 0x0 LOW_CLK_IRQ LOW_CLK_IRQ 0 1 RADIO_FSM_IRQ RADIO_FSM_IRQ 8 6 RADIO_CONTROL_SPARE_REG RADIO_CONTROL_SPARE_REG Radio ControllerSpare register 0x18 32 read-write n 0x0 0x0 RCC Reset and clock control RCC 0x0 0x0 0xFFFF registers n RCC RCC interrupt 1 AHBENR AHBENR AHB0 macro cells clock enable register 0x50 32 read-write n 0x0 0x0 CRCEN CRCEN: CRC enable 12 1 read-write DMAEN DMA and DMAMUX enable 0 1 read-write GPIOAEN IO controller for port A enable 2 1 read-write GPIOBEN IO controller for port B enable 3 1 read-write PKAEN PKAEN: PKA enable 16 1 read-write RNGEN RNG clock enable 18 1 read-write AHBRSTR AHBRSTR AHB0 macro cells reset register 0x30 32 read-write n 0x0 0x0 CRCRST CRC reset 12 1 read-write DMARST DMA and DMAMUX reset 0 1 read-write GPIOARST IO controller for port B reset 2 1 read-write GPIOBRST IO controller for port A reset 3 1 read-write PKARST PKA reset 16 1 read-write RNGRST RNG reset 18 1 read-write APB0ENR APB0ENR APB0 macro cells clock enable register 0x54 32 read-write n 0x0 0x0 RTCEN RTC enable. 12 1 read-write SYSCFGEN system controller enable. 8 1 read-write TIM1EN TIM1 enable. 0 1 read-write WDGEN Watchdog enable. 14 1 read-write APB0RSTR APB0RSTR APB0 macro cells reset register 0x34 32 read-write n 0x0 0x0 RTCRST RTC reset 12 1 SYSCFGRST system controller reset 8 1 TIM1RST TIM1 reset 0 1 WDGRST Watchdog reset 14 1 APB1ENR APB1ENR APB1ENR 0x58 32 read-write n 0x0 0x0 ADCANAEN ADCANAEN 5 1 ADCDIGEN ADCDIGEN 4 1 read-write I2C1EN CPU1 I2C1 clock enable 21 1 read-write I2C2EN I2C2 enable 23 1 read-write LPUARTEN LPUART enable 8 1 read-write SPI1EN SPI1 enable 0 1 read-write SPI2EN SPI2 enable 12 1 read-write SPI3EN CPU1 SPI3 clock enable 14 1 read-write USARTEN USART enable 10 1 read-write APB1RSTR APB1RSTR APB1 peripheral reset register 1 0x38 32 read-write n 0x0 0x0 ADCRST ADC reset 4 1 read-write I2C1RST I2C1 reset 21 1 read-write I2C2RST I2C2 reset 23 1 read-write LPUARTRST LPUART reset 8 1 read-write SPI1RST SPI1 reset 0 1 read-write SPI2RST SPI2 reset 12 1 read-write SPI3RST SPI3 reset 14 1 read-write USARTRST USARTRST: USART reset 10 1 read-write APB2ENR APB2ENR APB2ENR 0x60 32 read-write n 0x0 0x0 CLKBLEDIV MR_BLE (Bluetooth Low Energy radio) clock frequency selection when RCC_APB2ENR.MRBLEEN=1. 1 2 MRBLEEN MR_BLE (Bluetooth radio) enable. 0 1 APB2RSTR APB2RSTR APB2 peripheral reset register 2 0x40 32 read-write n 0x0 0x0 MRBLERST MR_BLE Bluetooth radio reset 0 1 read-write CFGR CFGR Clock configuration register 0x8 32 read-write n 0x0 0x0 ANADIV SMPS and ADC clock prescaling factor 10 2 read-write CCOPRE Configurable Clock Output Prescaler 29 3 read-write CLKSLOWSEL low speed clock source selection 15 2 read-write CLKSYSDIV system clock divided factor from HSI_64M 5 3 read-write DBGBYPHSI Used for debug mode only 20 1 read-write DBGHSIOFF Used for debug mode only 19 1 read-write DBGXOEXT Used for debug mode only 21 1 read-write HSESEL Clock source selection request. 1 1 IOBOOSTEN IO BOOSTER external clock enable 17 1 read-write LCOSEL Low speed Configurable Clock Output Selection 24 2 read-write MCOSEL Microcontroller clock output 26 3 read-write SMPSDIV SMPS clock prescaling factor 12 1 read-write SMPSINV control inversion of SMPS clock, versus ADC clock 0 1 read-write SPI2I2SCLKSEL Selection of I2S clock for SPI3 IP 23 1 read-write SPI3I2SCLKSEL Selection of I2S clock for SPI2 IP 22 1 read-write STOPHSI RC64MPLL clock source stop request 2 1 CIER CIER Clock interrupt enable register 0x18 32 read-write n 0x0 0x0 HSERDYIE HSE ready interrupt enable 4 1 read-write HSIPLLRDYIE HSI PLLSYS ready interrupt enable 5 1 read-write HSIPLLUNLOCKDETIE HSI PLL unlock detection interrupt enable. 6 1 HSIRDYIE HSI ready interrupt enable 3 1 read-write LSERDYIE LSE ready interrupt enable 1 1 read-write LSIRDYIE LSI1 ready interrupt enable 0 1 read-write RTCRSTIE RTC reset release interrupt enable. 7 1 WDGRSTIE Watchdog reset release interrupt enable. 8 1 CIFR CIFR Clock interrupt flag register 0x1C 32 read-write n 0x0 0x0 HSERDYF HSE ready interrupt flag 4 1 read-write HSIPLLRDYF HSI PLL ready flag 5 1 read-write HSIPLLUNLOCKDETF HSI PLL unlock detection flag. 6 1 HSIRDYF HSI ready interrupt flag 3 1 read-write LSERDYF LSE ready interrupt flag 1 1 read-write LSIRDYF LSI1 ready interrupt flag 0 1 read-write RTCRSTF RTC reset release flag. 7 1 WDGRSTF Watchdog reset release flag. 8 1 CR CR Clock control register 0x0 32 read-write n 0x0 0x0 FMRAT FMRAT 15 1 HSEON External High Speed clock enable. 16 1 read-write HSEPLLBUFON External high speed clock buffer for PLL RF2G4 enable. 12 1 HSERDY External High Speed clock flag. 17 1 read-only HSIPLLON Internal High Speed clock PLL enable 13 1 read-write HSIPLLRDY Internal High Speed clock PLL flag. This bit is set by hardware to indicate that the RC64MPLL pll is locked 14 1 HSIRDY HSI clock ready flag 10 1 read-only LOCKDET_NSTOP LOCKDET_NSTOP 7 3 LSEBYP External Low Speed clock bypass. 6 1 read-write LSEON External Low Speed clock enable 4 1 read-write LSERDY External Low Speed clock flag 5 1 read-only LSION Internal low speed RC clock enable 2 1 read-write LSIRDY Internal Low Speed clock flag 3 1 read-only CSCMDR CSCMDR This register allows switching the CPU system clock frequency safely while the MR_BLE is active. 0x20 32 read-write n 0x0 0x0 CLKSYSDIV_REQ System clock requested/targeted frequency. 1 3 EOFSEQ_IE End of sequence interrupt enable. 6 1 EOFSEQ_IRQ End of sequence flag. 7 1 REQUEST Request to switch the system clock frequency. 0 1 STATUS Status of the switching sequence. 4 2 CSR CSR CSR 0x94 32 read-write n 0x0 0x0 LOCKUPRSTF CPU lockup reset flag 30 1 read-only PADRSTF NRSTn pad reset flag. 26 1 read-only PORRSTF Power-On reset flag 27 1 read-only RMVF Remove Flag reset 23 1 read-write SFTRSTF Software reset flag 28 1 read-only WDGRSTF Watchdog reset flag 29 1 read-only CSSWCR CSSWCR Clocks Sources Software Calibration register 0xC 32 read-write n 0x0 0x0 HSISWTRIMEN High speed clock software trimming enable 23 1 read-write HSITRIMSW High speed clock trimming set by software 24 6 read-write LSEDRV external 32 kHz crystal GM 5 2 read-write LSISWBW Low speed internal RC trimming value set by software 1 4 read-write LSISWTRIMEN Low speed internal RC software trimming enable 0 1 read-write DBGR DBGR This register is planned for debug use-case only. 0x80 32 read-write n 0x0 0x0 DBGBYPHSI Used for debug mode only. 20 1 DBGHSIOFF Used for debug mode only. 19 1 DBGXOEXT Used for debug mode only. 21 1 ICSCR ICSCR Internal clock sources calibration register 0x4 32 read-write n 0x0 0x0 HSITRIM High speed clock trimming. 24 6 read-only LSIBW Low speed clock trimming. 2 4 read-only LSITRIMEN Low speed internal RC trimming enable. 0 1 read-write LSITRIMOK Low speed internal RC trimming value is OK. 1 1 read-only RFHSECR RFHSECR RF High Speed External register 0x9C 32 read-only n 0x0 0x0 XOTUNE RF-HSE capacitor bank tuning 0 6 RFSWHSECR RFSWHSECR RF Software High Speed External register 0x98 32 read-write n 0x0 0x0 GMC High speed external IO current control 4 3 SATRG Sense Amplifier Threshold 3 1 SWXOTUNE RF HSE capacitor bank tuning value set by software 8 6 SWXOTUNEEN RF HSE software capacitor bank tuning enable 7 1 RNG Random number generator RNG 0x0 0x0 0x400 registers n CR CR control register 0x0 32 read-write n 0x0 0x0 RNG_DIS Random number generator enable 2 1 TST_CLK TST_CLK 3 1 SR SR status register 0x4 32 read-write n 0x0 0x0 FAULT FAULT 2 1 read-only REVCLK REVCLK 1 1 read-only RNGRDY RNGRDY ready 0 1 read-only VAL VAL data register 0x8 32 read-only n 0x0 0x0 RANDOM_VALUE Random data 0 32 RRM Wakeup block version register RRM 0x0 0x0 0x400 registers n AA0_DIG_USR AA0_DIG_USR AA0_DIG_USR register 0x100 32 read-write n 0x0 0x0 AA_7_0 AA_7_0 0 8 AA1_DIG_USR AA1_DIG_USR AA1_DIG_USR register 0x104 32 read-write n 0x0 0x0 AA_15_8 AA_15_8 0 8 AA2_DIG_USR AA2_DIG_USR AA2_DIG_USR register 0x108 32 read-write n 0x0 0x0 AA_23_16 AA_23_16 0 8 AA3_DIG_USR AA3_DIG_USR AA3_DIG_USR register 0x10C 32 read-write n 0x0 0x0 AA_31_24 AA_31_24 0 8 AAC0_DIG_ENG AAC0_DIG_ENG AAC0_DIG_ENG register 0x15C 32 read-write n 0x0 0x0 AAC0_DIG_ENG_SPI AAC0_DIG_ENG_SPI 0 8 AAC1_DIG_ENG AAC1_DIG_ENG AAC1_DIG_ENG register 0x160 32 read-write n 0x0 0x0 AAC1_DIG_ENG_SPI AAC1_DIG_ENG_SPI 0 8 AFC0_DIG_ENG AFC0_DIG_ENG AFC0_DIG_ENG register 0x144 32 read-write n 0x0 0x0 AFC_GAIN_AFTER AFC_GAIN_AFTER 0 4 AFC_GAIN_BEFORE AFC_GAIN_BEFORE 4 4 AFC1_DIG_ENG AFC1_DIG_ENG AFC1_DIG_ENG register 0x148 32 read-write n 0x0 0x0 AFC_DELAY_AFTER AFC_DELAY_AFTER 0 4 AFC_DELAY_BEFORE AFC_DELAY_BEFORE 4 4 AFC2_DIG_ENG AFC2_DIG_ENG AFC2_DIG_ENG register 0x14C 32 read-write n 0x0 0x0 AFC_ENABLE AFC_ENABLE 7 1 AFC_FREQ_LIMIT AFC_FREQ_LIMIT 0 7 AFC3_DIG_ENG AFC3_DIG_ENG AFC3_DIG_ENG register 0x150 32 read-write n 0x0 0x0 AFC_MINMAX_LIMIT AFC_MINMAX_LIMIT 0 8 AGC0_ANA_TST AGC0_ANA_TST AGC0_ANA_TST register 0x2B4 32 read-write n 0x0 0x0 AGC0_ANA_TST_SEL AGC0_ANA_TST_SEL 0 1 AGC_ANT AGC_ANT 1 3 AGC_LNA AGC_LNA 4 1 AGC0_DIG_ENG AGC0_DIG_ENG AGC0_DIG_ENG register 0x2C0 32 read-write n 0x0 0x0 AGC_ENABLE AGC_ENABLE 6 1 AGC_THR_HIGH AGC_THR_HIGH 0 6 AGC10_DIG_ENG AGC10_DIG_ENG AGC10_DIG_ENG register 0x2E8 32 read-write n 0x0 0x0 ATT_0 ATT_0 0 6 AGC11_DIG_ENG AGC11_DIG_ENG AGC11_DIG_ENG register 0x2EC 32 read-write n 0x0 0x0 ATT_1 ATT_1 0 6 AGC12_DIG_ENG AGC12_DIG_ENG AGC12_DIG_ENG register 0x2F0 32 read-write n 0x0 0x0 ATT_2 ATT_2 0 6 AGC13_DIG_ENG AGC13_DIG_ENG AGC13_DIG_ENG register 0x2F4 32 read-write n 0x0 0x0 ATT_3 ATT_3 0 6 AGC14_DIG_ENG AGC14_DIG_ENG AGC14_DIG_ENG register 0x2F8 32 read-write n 0x0 0x0 ATT_4 ATT_4 0 6 AGC15_DIG_ENG AGC15_DIG_ENG AGC15_DIG_ENG register 0x2FC 32 read-write n 0x0 0x0 ATT_5 ATT_5 0 6 AGC16_DIG_ENG AGC16_DIG_ENG AGC16_DIG_ENG register 0x300 32 read-write n 0x0 0x0 ATT_6 ATT_6 0 6 AGC17_DIG_ENG AGC17_DIG_ENG AGC17_DIG_ENG register 0x304 32 read-write n 0x0 0x0 ATT_7 ATT_7 0 6 AGC18_DIG_ENG AGC18_DIG_ENG AGC18_DIG_ENG register 0x308 32 read-write n 0x0 0x0 ATT_8 ATT_8 0 6 AGC19_DIG_ENG AGC19_DIG_ENG AGC19_DIG_ENG register 0x30C 32 read-write n 0x0 0x0 ATT_9 ATT_9 0 6 AGC1_ANA_TST AGC1_ANA_TST AGC1_ANA_TST register 0x2B8 32 read-write n 0x0 0x0 AGC1_ANA_TST_SEL AGC1_ANA_TST_SEL 0 1 AGC_IFATT AGC_IFATT 1 5 AGC1_DIG_ENG AGC1_DIG_ENG AGC1_DIG_ENG register 0x2C4 32 read-write n 0x0 0x0 AGC_AUTOLOCK AGC_AUTOLOCK 6 1 AGC_LOCK_SYNC AGC_LOCK_SYNC 7 1 AGC_THR_LOW_6 AGC_THR_LOW_6 0 6 AGC20_DIG_ENG AGC20_DIG_ENG AGC20_DIG_ENG register 0x310 32 read-write n 0x0 0x0 I_GAIN_COMP I_GAIN_COMP 0 8 AGC2_ANA_TST AGC2_ANA_TST AGC2_ANA_TST register 0x2BC 32 read-write n 0x0 0x0 AGC2_ANA_TST_SEL AGC2_ANA_TST_SEL 0 1 AGC_ANTENNAE_USR_TRIM AGC_ANTENNAE_USR_TRIM 1 3 AGC2_DIG_ENG AGC2_DIG_ENG AGC2_DIG_ENG register 0x2C8 32 read-write n 0x0 0x0 AGC_THR_LOW_12 AGC_THR_LOW_12 0 6 AGC3_DIG_ENG AGC3_DIG_ENG AGC3_DIG_ENG register 0x2CC 32 read-write n 0x0 0x0 AUTOLOCK_THR AUTOLOCK_THR 0 6 AGC4_DIG_ENG AGC4_DIG_ENG AGC4_DIG_ENG register 0x2D0 32 read-write n 0x0 0x0 AGC_HOLD_TIME_FAST AGC_HOLD_TIME_FAST 0 4 AGC_HOLD_TIME_SLOW AGC_HOLD_TIME_SLOW 4 4 AGC5_DIG_ENG AGC5_DIG_ENG AGC5_DIG_ENG register 0x2D4 32 read-write n 0x0 0x0 T_INT T_INT 4 4 T_MEAS T_MEAS 0 4 AGC6_DIG_ENG AGC6_DIG_ENG AGC6_DIG_ENG register 0x2D8 32 read-write n 0x0 0x0 HOLD_TIME_SEL_10_4 HOLD_TIME_SEL_10_4 0 7 AGC7_DIG_ENG AGC7_DIG_ENG AGC7_DIG_ENG register 0x2DC 32 read-write n 0x0 0x0 TH_LOW_SEL_10_4 TH_LOW_SEL_10_4 0 7 AGC8_DIG_ENG AGC8_DIG_ENG AGC8_DIG_ENG register 0x2E0 32 read-write n 0x0 0x0 HOLD_TIME_SEL_3_0 HOLD_TIME_SEL_3_0 0 4 TH_LOW_SEL_3_0 TH_LOW_SEL_3_0 4 4 AGC9_DIG_ENG AGC9_DIG_ENG AGC9_DIG_ENG register 0x2E4 32 read-write n 0x0 0x0 MAX_SEQ MAX_SEQ 4 4 START_SEQ START_SEQ 0 4 AGC_DIG_OUT AGC_DIG_OUT AGC_DIG_OUT register 0x2AC 32 read-only n 0x0 0x0 AGC_ATT_OUT AGC_ATT_OUT 0 4 BLE_IRQ_ENABLE BLE_IRQ_ENABLE BLE_IRQ_ENABLE register 0x28 32 read-write n 0x0 0x0 PORT_CMD_END PORT_CMD_END 4 1 PORT_CMD_START PORT_CMD_START 3 1 PORT_GRANT PORT_GRANT 0 1 PORT_PREEMPT PORT_PREEMPT 2 1 PORT_RELEASE PORT_RELEASE 1 1 BLE_IRQ_STATUS BLE_IRQ_STATUS BLE_IRQ_STATUS register 0x2C 32 read-write n 0x0 0x0 CMD_END CMD_END 4 1 CMD_START CMD_START 3 1 PORT_GRANT PORT_GRANT 0 1 PORT_PREEMPT PORT_PREEMPT 2 1 PORT_RELEASE PORT_RELEASE 1 1 CAL_DIG_TST CAL_DIG_TST CAL_DIG_TST register 0x1B0 32 read-write n 0x0 0x0 CAL_DIG_TEST_SEL CAL_DIG_TEST_SEL 0 1 CBPCAL_START_CAL CBPCAL_START_CAL 3 1 EN_CALIB_KVCO EN_CALIB_KVCO 5 1 SYNTHCAL_CALREQ SYNTHCAL_CALREQ 2 1 SYNTHCAL_RESET SYNTHCAL_RESET 1 1 SYNTHCAL_SKIP SYNTHCAL_SKIP 4 1 CBIAS0_ANA_ENG CBIAS0_ANA_ENG CBIAS0_ANA_ENG register 0x274 32 read-write n 0x0 0x0 RFD_CBIAS_IBIAS_TRIM RFD_CBIAS_IBIAS_TRIM 0 4 RFD_CBIAS_IPTAT_TRIM RFD_CBIAS_IPTAT_TRIM 4 4 CBIAS0_HW_TRIM_OUT CBIAS0_HW_TRIM_OUT CBIAS0_HW_TRIM_OUT register 0x328 32 read-write n 0x0 0x0 HW_CBIAS_IBIAS_TRIM IPTAT current (provided by the HW trimming, automatically loaded on POR). 0 4 HW_CBIAS_IPTAT_TRIM IPTAT current (provided by the HW trimming, automatically loaded on POR). 4 4 CBIAS1_ANA_ENG CBIAS1_ANA_ENG CBIAS1_ANA_ENG register 0x278 32 read-write n 0x0 0x0 RFD_CBIAS_ENA_ATB_CURR RFD_CBIAS_ENA_ATB_CURR 4 1 RFD_CBIAS_VBG_TRIM RFD_CBIAS_VBG_TRIM 0 4 CBIAS1_HW_TRIM_OUT CBIAS1_HW_TRIM_OUT CBIAS1_HW_TRIM_OUT register 0x32C 32 read-write n 0x0 0x0 HW_CBIAS_VBG_TRIM VBG current (provided by the HW trimming, automatically loaded on POR). 0 3 CBIAS_ANA_TEST CBIAS_ANA_TEST CBIAS_ANA_TEST register 0x27C 32 read-write n 0x0 0x0 CBIAS_ANA_TST_SEL CBIAS_ANA_TST_SEL 0 1 RFD_CBIAS_ENA_CORE RFD_CBIAS_ENA_CORE 2 1 RFD_CBIAS_ENA_RX_CURR RFD_CBIAS_ENA_RX_CURR 3 1 RFD_CBIAS_ENA_TX_CURR RFD_CBIAS_ENA_TX_CURR 4 1 RFD_CBIAS_ENA_VBG RFD_CBIAS_ENA_VBG 7 1 RFD_CBIAS_ENA_VBG_BOOST RFD_CBIAS_ENA_VBG_BOOST 6 1 CR0_DIG_ENG CR0_DIG_ENG CR0_DIG_ENG register 0x154 32 read-write n 0x0 0x0 CR_GAIN_AFTER CR_GAIN_AFTER 0 4 CR_GAIN_BEFORE CR_GAIN_BEFORE 4 4 CR0_LR CR0_LR CR0_LR register 0x168 32 read-write n 0x0 0x0 CR_LR_GAIN_AFTER CR_LR_GAIN_AFTER 0 4 CR_LR_GAIN_BEFORE CR_LR_GAIN_BEFORE 4 4 CTRL RRM_CTRL RRM_CTRL register 0x4 32 read-write n 0x0 0x0 PRIORITY PRIORITY 0 2 DCF_RSSI_DIG_ENG DCF_RSSI_DIG_ENG DCF_RSSI_DIG_ENG register 0x158 32 read-write n 0x0 0x0 DCF_CTRL DCF_CTRL 0 4 RSSI_CTRL RSSI_CTRL 4 4 DEMOD_DIG_OUT DEMOD_DIG_OUT DEMOD_DIG_OUT register 0x2B0 32 read-only n 0x0 0x0 AAC_FOUND AAC_FOUND 2 1 CI_FIELD CI_FIELD 0 2 PD_FOUND PD_FOUND 3 1 RX_END RX_END 4 1 DEMOD_DIG_TST DEMOD_DIG_TST DEMOD_DIG_TST register 0x164 32 read-write n 0x0 0x0 TST_DUT TST_DUT 1 7 DEM_MOD_DIG_USR DEM_MOD_DIG_USR DEM_MOD_DIG_USR register 0x110 32 read-write n 0x0 0x0 CHANNEL_NUM CHANNEL_NUM 1 7 DTB0_DIG_ENG DTB0_DIG_ENG DTB0_DIG_ENG register 0x1DC 32 read-write n 0x0 0x0 DTB_CFG DTB_CFG 1 4 DTB_EN DTB_EN 0 1 DTB1_DIG_ENG DTB1_DIG_ENG DTB1_DIG_ENG register 0x1E0 32 read-write n 0x0 0x0 DTB1_CFG DTB1_CFG 0 7 DTB1_EN DTB1_EN 7 1 DTB2_DIG_ENG DTB2_DIG_ENG DTB2_DIG_ENG register 0x1E4 32 read-write n 0x0 0x0 DTB2_CFG DTB2_CFG 0 8 DTB3_DIG_ENG DTB3_DIG_ENG DTB3_DIG_ENG register 0x1E8 32 read-write n 0x0 0x0 DTB3_CFG DTB3_CFG 0 8 DTB4_DIG_ENG DTB4_DIG_ENG DTB4_DIG_ENG register 0x1EC 32 read-write n 0x0 0x0 DTB4_CFG DTB4_CFG 0 3 DTB5_DIG_ENG DTB5_DIG_ENG DTB5_DIG_ENG register 0x1F0 32 read-write n 0x0 0x0 INITIALIZE INITIALIZE 3 1 RXTX_START_SEL RXTX_START_SEL 0 1 RX_ACTIVE RX_ACTIVE 2 1 TX_ACTIVE TX_ACTIVE 1 1 DTB6_DIG_ENG DTB6_DIG_ENG DTB6_DIG_ENG register 0x1F4 32 read-write n 0x0 0x0 WKUP_DTB_CFG WKUP_DTB_CFG 0 2 WKUP_DTB_EN WKUP_DTB_EN 7 1 DTB7_DIG_ENG DTB7_DIG_ENG DTB7_DIG_ENG register 0x1F8 32 read-write n 0x0 0x0 TX_DTB_CFG TX_DTB_CFG 0 2 TX_DTB_EN TX_DTB_EN 7 1 DTB8_DIG_ENG DTB8_DIG_ENG DTB8_DIG_ENG register 0x1FC 32 read-write n 0x0 0x0 DTB8_CFG DTB8_CFG 0 8 DTB9_DIG_ENG DTB9_DIG_ENG DTB9_DIG_ENG register 0x200 32 read-write n 0x0 0x0 DTB9_CFG DTB9_CFG 0 8 DTBA_DIG_ENG DTBA_DIG_ENG DTBA_DIG_ENG register 0x204 32 read-write n 0x0 0x0 DTBA_CFG DTBA_CFG 0 8 FSM0_DIG_ENG FSM0_DIG_ENG FSM0_DIG_ENG register 0x1B8 32 read-write n 0x0 0x0 RX_TIMER RX_TIMER 0 8 FSM1_DIG_ENG FSM1_DIG_ENG FSM1_DIG_ENG register 0x1BC 32 read-write n 0x0 0x0 LDO_SHORT_TIMER LDO_SHORT_TIMER 0 8 FSM2_DIG_ENG FSM2_DIG_ENG FSM2_DIG_ENG register 0x1C0 32 read-write n 0x0 0x0 LDO_TIMER LDO_TIMER 0 8 FSM3_DIG_ENG FSM3_DIG_ENG FSM3_DIG_ENG register 0x1C4 32 read-write n 0x0 0x0 LOCK_TIMEOUT LOCK_TIMEOUT 0 8 FSM4_DIG_ENG FSM4_DIG_ENG FSM4_DIG_ENG register 0x1C8 32 read-write n 0x0 0x0 CBPCAL_TIMEOUT CBPCAL_TIMEOUT 0 8 FSM5_DIG_ENG FSM5_DIG_ENG FSM5_DIG_ENG register 0x1CC 32 read-write n 0x0 0x0 SYNTHCAL_TIMEOUT SYNTHCAL_TIMEOUT 0 8 FSM6_DIG_ENG FSM6_DIG_ENG FSM6_DIG_ENG register 0x1D0 32 read-write n 0x0 0x0 ENA_CURR_TIMEOUT ENA_CURR_TIMEOUT 0 8 FSM7_DIG_ENG FSM7_DIG_ENG FSM7_DIG_ENG register 0x1D4 32 read-write n 0x0 0x0 VBG_BOOST_TIMEOUT VBG_BOOST_TIMEOUT 0 8 FSM8_DIG_ENG FSM8_DIG_ENG FSM8_DIG_ENG register 0x1D8 32 read-write n 0x0 0x0 PA_DWN_ANA_TIMEOUT PA_DWN_ANA_TIMEOUT 0 8 FSM_STATUS_DIG_OUT FSM_STATUS_DIG_OUT FSM_STATUS_DIG_OUT register 0x298 32 read-only n 0x0 0x0 STATUS STATUS 0 5 SYNTH_CAL_ERROR SYNTH_CAL_ERROR 7 1 ID RRM_ID RRM_ID register 0x0 32 read-only n 0x0 0x0 IDENTIFICATION IDENTIFICATION 0 4 IRQ_STATUS_DIG_OUT IRQ_STATUS_DIG_OUT IRQ_STATUS_DIG_OUT register 0x29C 32 read-only n 0x0 0x0 LDO_ANA_ENG LDO_ANA_ENG LDO_ANA_ENG register 0x254 32 read-write n 0x0 0x0 RFD_LDO_RXADC_BYPASS RFD_LDO_RXADC_BYPASS 2 1 RFD_LDO_RX_TX_BYPASS RFD_LDO_RX_TX_BYPASS 3 1 RFD_LDO_TRANSFO_BYPASS RFD_LDO_TRANSFO_BYPASS 1 1 LDO_ANA_TST LDO_ANA_TST LDO_ANA_TST register 0x250 32 read-write n 0x0 0x0 LDO_ANA_TST_SEL LDO_ANA_TST_SEL 0 1 RFD_LDO_RXADC_ENA RFD_LDO_RXADC_ENA 3 1 RFD_LDO_RX_TX_ENA RFD_LDO_RX_TX_ENA 4 1 RFD_LDO_TRANSFO_ENA RFD_LDO_TRANSFO_ENA 2 1 LR_AAC_THR_DIG_ENG LR_AAC_THR_DIG_ENG LR_AAC_THR_DIG_ENG register 0x18C 32 read-write n 0x0 0x0 LR_AAC_THR LR_AAC_THR 0 8 LR_AAC_TIMEOUT_DIG_ENG LR_AAC_TIMEOUT_DIG_ENG LR_AAC_TIMEOUT_DIG_ENG register 0x194 32 read-write n 0x0 0x0 LR_AAC_TIMEOUT LR_AAC_TIMEOUT 0 8 LR_PD_THR_DIG_ENG LR_PD_THR_DIG_ENG LR_PD_THR_DIG_ENG register 0x184 32 read-write n 0x0 0x0 LR_PD_THR LR_PD_THR 0 8 LR_PD_TIMEOUT_DIG_ENG LR_PD_TIMEOUT_DIG_ENG LR_PD_TIMEOUT_DIG_ENG register 0x190 32 read-write n 0x0 0x0 LR_PD_TIMEOUT LR_PD_TIMEOUT 0 8 LR_RSSI_K_DIG_ENG LR_RSSI_K_DIG_ENG LR_RSSI_K_DIG_ENG register 0x180 32 read-write n 0x0 0x0 LR_RSSI_K LR_RSSI_K 0 8 LR_RSSI_THR_DIG_ENG LR_RSSI_THR_DIG_ENG LR_RSSI_THR_DIG_ENG register 0x188 32 read-write n 0x0 0x0 LR_RSSI_THR LR_RSSI_THR 0 8 MOD0_ANA_TST MOD0_ANA_TST MOD0_ANA_TST register 0x224 32 read-write n 0x0 0x0 MOD_ANA_TST_SEL MOD_ANA_TST_SEL 0 1 RFD_MOD_ENA_ANA RFD_MOD_ENA_ANA 1 1 MOD0_DIG_TST MOD0_DIG_TST MOD0_DIG_TST register 0x234 32 read-write n 0x0 0x0 KFORCE_3_0 KFORCE_3_0 4 4 MOD_DIG_TEST_SEL MOD_DIG_TEST_SEL 0 1 PMU_NO_MODULTATION PMU_NO_MODULTATION 3 1 MOD1_ANA_TST MOD1_ANA_TST MOD1_ANA_TST register 0x228 32 read-write n 0x0 0x0 TX_MOD_CALDAC TX_MOD_CALDAC 0 8 MOD1_DIG_TST MOD1_DIG_TST MOD1_DIG_TST register 0x238 32 read-write n 0x0 0x0 KFORCE_11_4 KFORCE_11_4 0 8 MOD2_DIG_TST MOD2_DIG_TST MOD2_DIG_TST register 0x23C 32 read-write n 0x0 0x0 KFORCE_19_12 KFORCE_19_12 0 8 MOD3_DIG_TST MOD3_DIG_TST MOD3_DIG_TST register 0x240 32 read-write n 0x0 0x0 AFORCE AFORCE 0 3 MFORCE MFORCE 3 5 MOD_ANA_ENG MOD_ANA_ENG MOD_ANA_ENG register 0x22C 32 read-write n 0x0 0x0 RFD_MOD_ENA_D8B RFD_MOD_ENA_D8B 0 1 RFD_MOD_ENA_RD6B RFD_MOD_ENA_RD6B 1 1 MOD_DIG_ENG MOD_DIG_ENG MOD_DIG_ENG register 0x230 32 read-write n 0x0 0x0 EN_DSM EN_DSM 4 1 FORCE_TX FORCE_TX 3 1 INT_MODE INT_MODE 0 1 MODDIG_161M_SEL_UPS MODDIG_161M_SEL_UPS 5 1 MOD_TYPE MOD_TYPE 6 2 TXMOD_802_DOUBLE TXMOD_802_DOUBLE 1 1 PA0_ANA_TST PA0_ANA_TST PA0_ANA_TST register 0x13C 32 read-write n 0x0 0x0 PA_ANA_TST_SEL PA_ANA_TST_SEL 0 1 RFD_LDO_TRANSFO_VCEL RFD_LDO_TRANSFO_VCEL 4 4 RFD_PA_MAXDBM_1V2 RFD_PA_MAXDBM_1V2 3 1 RFD_PA_PUP_DRV_1V2 RFD_PA_PUP_DRV_1V2 1 1 RFD_PA_PUP_PWCTRL_1V2 RFD_PA_PUP_PWCTRL_1V2 2 1 PA1_ANA_TST PA1_ANA_TST PA1_ANA_TST register 0x140 32 read-write n 0x0 0x0 PA_CODE PA_CODE 0 8 PA_CODE1_DIG_ENG PA_CODE1_DIG_ENG PA_CODE1_DIG_ENG register 0x11C 32 read-write n 0x0 0x0 PA_CODE_1 PA_CODE_1 0 8 PA_CODE2_DIG_ENG PA_CODE2_DIG_ENG PA_CODE2_DIG_ENG register 0x120 32 read-write n 0x0 0x0 PA_CODE_2 PA_CODE_2 0 8 PA_CODE3_DIG_ENG PA_CODE3_DIG_ENG PA_CODE3_DIG_ENG register 0x124 32 read-write n 0x0 0x0 PA_CODE_3 PA_CODE_3 0 8 PA_CODE4_DIG_ENG PA_CODE4_DIG_ENG PA_CODE4_DIG_ENG register 0x128 32 read-write n 0x0 0x0 PA_CODE_4 PA_CODE_4 0 8 PA_CODE5_DIG_ENG PA_CODE5_DIG_ENG PA_CODE5_DIG_ENG register 0x12C 32 read-write n 0x0 0x0 PA_CODE_5 PA_CODE_5 0 8 PA_CODE6_DIG_ENG PA_CODE6_DIG_ENG PA_CODE6_DIG_ENG register 0x130 32 read-write n 0x0 0x0 PA_CODE_6 PA_CODE_6 0 8 PA_CODE7_DIG_ENG PA_CODE7_DIG_ENG PA_CODE7_DIG_ENG register 0x134 32 read-write n 0x0 0x0 PA_CODE_7 PA_CODE_7 0 8 PA_DIG_ENG PA_DIG_ENG PA_DIG_ENG register 0x138 32 read-write n 0x0 0x0 CHECK_LOCK_PA_EXIT_N CHECK_LOCK_PA_EXIT_N 6 1 LOCK_FAIL_PA_DISABLE LOCK_FAIL_PA_DISABLE 5 1 PA_DWN_ANA_EN_N PA_DWN_ANA_EN_N 7 1 PA_RAMP_STEP_WIDTH PA_RAMP_STEP_WIDTH 1 2 PHYCTRL_DIG_USR PHYCTRL_DIG_USR PHYCTRL_DIG_USR register 0x118 32 read-write n 0x0 0x0 PD_DETECT_MODE PD_DETECT_MODE 4 1 RXTXPHY RXTXPHY 0 3 SUPPENA SUPPENA 3 1 RADIO_FSM_USR RADIO_FSM_USR RADIO_FSM_USR register 0x114 32 read-write n 0x0 0x0 EN_CALIB_CBP EN_CALIB_CBP 1 1 EN_CALIB_SYNTH EN_CALIB_SYNTH 2 1 PA_POWER PA_POWER 3 5 RF_ANA_ENG RF_ANA_ENG RF_ANA_ENG register 0x318 32 read-write n 0x0 0x0 FORCE_XO_READY FORCE_XO_READY 2 1 HSE2ON_TEST HSE2ON_TEST 0 1 RESETN_ATB RESETN_ATB 1 1 RSSI0_DIG_OUT RSSI0_DIG_OUT RSSI0_DIG_OUT register 0x2A4 32 read-only n 0x0 0x0 RSSI_MEAS_OUT_7_0 RSSI_MEAS_OUT_7_0 0 8 RSSI1_DIG_OUT RSSI1_DIG_OUT RSSI1_DIG_OUT register 0x2A8 32 read-only n 0x0 0x0 RSSI_MEAS_OUT_15_8 RSSI_MEAS_OUT_15_8 0 8 RX0_ANA_TST RX0_ANA_TST RX0_ANA_TST register 0x258 32 read-write n 0x0 0x0 RFD_RX_ENA RFD_RX_ENA 1 1 RFD_RX_ENA_CBPFILT RFD_RX_ENA_CBPFILT 4 1 RFD_RX_ENA_DIV2 RFD_RX_ENA_DIV2 6 1 RFD_RX_ENA_LNA RFD_RX_ENA_LNA 2 1 RFD_RX_ENA_MIXTIA RFD_RX_ENA_MIXTIA 5 1 RFD_RX_ENA_V2I RFD_RX_ENA_V2I 3 1 RFD_RX_TRANSFO_IN_RX RFD_RX_TRANSFO_IN_RX 7 1 RX0_ANA_TST_SEL RX0_ANA_TST_SEL 0 1 RX1_ANA_TST RX1_ANA_TST RX1_ANA_TST register 0x25C 32 read-write n 0x0 0x0 FD_RX_ENA_CBPCAL FD_RX_ENA_CBPCAL 1 1 RFD_RX_CBPCAL_RESET RFD_RX_CBPCAL_RESET 2 1 RFD_RX_CBPCAL_SWAP RFD_RX_CBPCAL_SWAP 3 1 RFD_RX_CBP_CAP_WORD RFD_RX_CBP_CAP_WORD 4 4 RX1_ANA_TST_SEL RX1_ANA_TST_SEL 0 1 RXADC_ANA_ENG RXADC_ANA_ENG RXADC_ANA_ENG register 0x24C 32 read-write n 0x0 0x0 RFD_RXADC_CAL_ENA_I RFD_RXADC_CAL_ENA_I 1 1 RFD_RXADC_CAL_ENA_Q RFD_RXADC_CAL_ENA_Q 2 1 RFD_RXADC_CAL_SOC RFD_RXADC_CAL_SOC 0 1 RXADC_CLK_INV RXADC_CLK_INV 3 1 RXADC_ANA_TST RXADC_ANA_TST RXADC_ANA_TST register 0x244 32 read-write n 0x0 0x0 RFD_RXADC_CLK_ENA RFD_RXADC_CLK_ENA 3 1 RFD_RXADC_EN_I RFD_RXADC_EN_I 1 1 RFD_RXADC_EN_Q RFD_RXADC_EN_Q 2 1 RXADC_ANA_TST_SEL RXADC_ANA_TST_SEL 0 1 RXADC_ANA_USR RXADC_ANA_USR RXADC_ANA_USR register 0x248 32 read-write n 0x0 0x0 RFD_RXADC_DELAYTRIM_I RFD_RXADC_DELAYTRIM_I 0 3 RFD_RXADC_DELAYTRIM_Q RFD_RXADC_DELAYTRIM_Q 3 3 RXADC_HW_TRIM_OUT RXADC_HW_TRIM_OUT RXADC_HW_TRIM_OUT register 0x324 32 read-write n 0x0 0x0 HW_RXADC_DELAYTRIM_I control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR). 0 2 HW_RXADC_DELAYTRIM_Q control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR). 3 3 SPARE SPARE 6 2 RX_ANA_ENG RX_ANA_ENG RX_ANA_ENG register 0x260 32 read-write n 0x0 0x0 RFD_RX_CBPF_GAIN_CTRL RFD_RX_CBPF_GAIN_CTRL 4 2 RFD_RX_LNA_HSENSI RFD_RX_LNA_HSENSI 2 1 RX_V2I_BOOST RX_V2I_BOOST 0 1 RX_DIG_ENG RX_DIG_ENG RX_DIG_ENG register 0x264 32 read-write n 0x0 0x0 INVERT_RXADC_MSB INVERT_RXADC_MSB 1 1 SWAP_RXADC_IQ SWAP_RXADC_IQ 0 1 SEMA_IRQ_ENABLE SEMA_IRQ_ENABLE SEMA_IRQ_ENABLE register 0x20 32 read-write n 0x0 0x0 LOCK LOCK 0 1 UNLOCK UNLOCK 1 1 SEMA_IRQ_STATUS SEMA_IRQ_STATUS SEMA_IRQ_STATUS register 0x24 32 read-only n 0x0 0x0 LOCK LOCK 0 1 UNLOCK UNLOCK 1 1 SPARE RRM_SPARE RRM_SPARE register 0x80 32 read-write n 0x0 0x0 SPARE_ANA_IN_ENG SPARE_ANA_IN_ENG SPARE_ANA_IN_ENG register 0x314 32 read-write n 0x0 0x0 SPARE_ANA_OUT SPARE_ANA_OUT SPARE_ANA_OUT register 0x2A0 32 read-only n 0x0 0x0 SYNTH0_ANA_ENG SYNTH0_ANA_ENG SYNTH0_ANA_ENG register 0x210 32 read-write n 0x0 0x0 RFD_PLL_CP_ISEL RFD_PLL_CP_ISEL 0 3 RFD_PLL_CP_LDO_BYP RFD_PLL_CP_LDO_BYP 3 1 RFD_PLL_CP_SPLIT RFD_PLL_CP_SPLIT 4 2 RFD_PLL_VCO_LDO_BYP RFD_PLL_VCO_LDO_BYP 6 1 RFD_PLL_VCO_LDO_VCEL RFD_PLL_VCO_LDO_VCEL 7 1 SYNTH0_ANA_TST SYNTH0_ANA_TST SYNTH0_ANA_TST register 0x208 32 read-write n 0x0 0x0 RFD_PLL_CP_LDO_PUP RFD_PLL_CP_LDO_PUP 2 1 RFD_PLL_CP_PUP RFD_PLL_CP_PUP 4 1 RFD_PLL_DIV2_PUP RFD_PLL_DIV2_PUP 5 1 RFD_PLL_DIV_LDO_PUP RFD_PLL_DIV_LDO_PUP 1 1 RFD_PLL_LORX_PUP RFD_PLL_LORX_PUP 6 1 RFD_PLL_LOTX_PUP RFD_PLL_LOTX_PUP 7 1 RFD_PLL_VCO_LDO_PUP RFD_PLL_VCO_LDO_PUP 3 1 SYNTH_ANA_TST_SEL SYNTH_ANA_TST_SEL 0 1 SYNTH1_ANA_ENG SYNTH1_ANA_ENG SYNTH1_ANA_ENG register 0x214 32 read-write n 0x0 0x0 RFD_DISCHBOOSTN RFD_DISCHBOOSTN 7 1 RFD_PLL_DIV_LDO_BYP RFD_PLL_DIV_LDO_BYP 6 1 RFD_PLL_FCOMP_EXT_SEL RFD_PLL_FCOMP_EXT_SEL 5 1 RFD_PLL_FORCE_CMOSDIV_XRST RFD_PLL_FORCE_CMOSDIV_XRST 0 1 RFD_PLL_FREF_EXT_SEL RFD_PLL_FREF_EXT_SEL 4 1 RFD_PLL_LF_BW_SEL RFD_PLL_LF_BW_SEL 1 2 RFD_PLL_LF_HIGH_C1 RFD_PLL_LF_HIGH_C1 3 1 SYNTH1_ANA_TST SYNTH1_ANA_TST SYNTH1_ANA_TST register 0x20C 32 read-write n 0x0 0x0 RFD_PLL_PFD_LD_EN RFD_PLL_PFD_LD_EN 6 1 RFD_PLL_PFD_PUP RFD_PLL_PFD_PUP 1 1 RFD_PLL_PIPELINE_PUP RFD_PLL_PIPELINE_PUP 2 1 RFD_PLL_VCO_BUF_PUP RFD_PLL_VCO_BUF_PUP 5 1 RFD_PLL_VCO_CORE_PUP RFD_PLL_VCO_CORE_PUP 4 1 RFD_PLL_VCO_VREF_PUP RFD_PLL_VCO_VREF_PUP 3 1 SYNTH2_ANA_ENG SYNTH2_ANA_ENG SYNTH2_ANA_ENG register 0x218 32 read-write n 0x0 0x0 SYNTH3_ANA_ENG SYNTH3_ANA_ENG SYNTH3_ANA_ENG register 0x21C 32 read-write n 0x0 0x0 PLL_BW_BOOST PLL_BW_BOOST 3 2 PMU_FORCE_TIMER PMU_FORCE_TIMER 7 1 RFD_PLL_VCO_ALC_AMP RFD_PLL_VCO_ALC_AMP 0 3 SYNTHCAL0_ANA_TST SYNTHCAL0_ANA_TST SYNTHCAL0_ANA_TST register 0x198 32 read-write n 0x0 0x0 VCO_CALFREQ_EXT VCO_CALFREQ_EXT 0 7 VCO_CALFREQ_EXT_SEL VCO_CALFREQ_EXT_SEL 7 1 SYNTHCAL0_DIG_ENG SYNTHCAL0_DIG_ENG SYNTHCAL0_DIG_ENG register 0x1A8 32 read-write n 0x0 0x0 SYNTHCAL_DEBUG_BUS_SEL SYNTHCAL_DEBUG_BUS_SEL 0 4 SYNTH_IF_FREQ_CAL SYNTH_IF_FREQ_CAL 6 1 VCO_ALC_FORCE_PUP VCO_ALC_FORCE_PUP 5 1 SYNTHCAL0_DIG_OUT SYNTHCAL0_DIG_OUT SYNTHCAL0_DIG_OUT register 0x280 32 read-only n 0x0 0x0 VCO_CALAMP_OUT_6_0 VCO_CALAMP_OUT_6_0 0 7 SYNTHCAL1_ANA_TST SYNTHCAL1_ANA_TST SYNTHCAL1_ANA_TST register 0x19C 32 read-write n 0x0 0x0 VCO_CALAMP_EXT_6_0 VCO_CALAMP_EXT_6_0 0 7 VCO_CALAMP_EXT_SEL VCO_CALAMP_EXT_SEL 7 1 SYNTHCAL1_DIG_ENG SYNTHCAL1_DIG_ENG SYNTHCAL1_DIG_ENG register 0x1AC 32 read-write n 0x0 0x0 DISABLE_LOCK_DET DISABLE_LOCK_DET 3 1 LOCK_DET LOCK_DET 4 1 LOCK_DETECT_STOP LOCK_DETECT_STOP 0 3 SYNTHCAL1_DIG_OUT SYNTHCAL1_DIG_OUT SYNTHCAL1_DIG_OUT register 0x284 32 read-only n 0x0 0x0 VCO_CALAMP_OUT_10_7 VCO_CALAMP_OUT_10_7 0 4 SYNTHCAL2_ANA_TST SYNTHCAL2_ANA_TST SYNTHCAL2_ANA_TST register 0x1A0 32 read-write n 0x0 0x0 VCO_CALAMP_EXT_10_7 VCO_CALAMP_EXT_10_7 0 4 SYNTHCAL2_DIG_ENG SYNTHCAL2_DIG_ENG SYNTHCAL2_DIG_ENG register 0x1B4 32 read-write n 0x0 0x0 RFSYNTH_RFCOUNTER_7_0 RFSYNTH_RFCOUNTER_7_0 0 8 SYNTHCAL2_DIG_OUT SYNTHCAL2_DIG_OUT SYNTHCAL2_DIG_OUT register 0x288 32 read-only n 0x0 0x0 VCO_CALFREQ_OUT VCO_CALFREQ_OUT 0 7 SYNTHCAL3_ANA_TST SYNTHCAL3_ANA_TST SYNTHCAL3_ANA_TST register 0x1A4 32 read-write n 0x0 0x0 CALKVCO_EXT_SEL CALKVCO_EXT_SEL 7 1 RFD_MOD_REF_DAC_WORD RFD_MOD_REF_DAC_WORD 0 6 SYNTHCAL3_DIG_OUT SYNTHCAL3_DIG_OUT SYNTHCAL3_DIG_OUT register 0x28C 32 read-only n 0x0 0x0 SYNTHCAL_DEBUG_BUS SYNTHCAL_DEBUG_BUS 0 4 SYNTHCAL4_DIG_OUT SYNTHCAL4_DIG_OUT SYNTHCAL4_DIG_OUT register 0x290 32 read-only n 0x0 0x0 MOD_REF_DAC_WORD_OUT MOD_REF_DAC_WORD_OUT 0 6 SYNTHCAL5_DIG_OUT SYNTHCAL5_DIG_OUT SYNTHCAL5_DIG_OUT register 0x294 32 read-only n 0x0 0x0 CBP_CALIB_WORD CBP_CALIB_WORD 0 4 SYNTH_DIG_TST SYNTH_DIG_TST SYNTH_DIG_TST register 0x220 32 read-write n 0x0 0x0 PMU_SYNTH_EN PMU_SYNTH_EN 1 1 SYNTH_DIG_TST_SEL SYNTH_DIG_TST_SEL 0 1 TCB0_ANA_ENG TCB0_ANA_ENG TCB0_ANA_ENG register 0x268 32 read-write n 0x0 0x0 RFD_TCB_7_0 RFD_TCB_7_0 0 8 TCB1_ANA_ENG TCB1_ANA_ENG TCB1_ANA_ENG register 0x26C 32 read-write n 0x0 0x0 RFD_TCB_8 RFD_TCB_8 0 1 TCB2_ANA_ENG TCB2_ANA_ENG TCB2_ANA_ENG register 0x270 32 read-write n 0x0 0x0 RFD_STM RFD_STM 6 1 RFD_TCB_V33 RFD_TCB_V33 0 6 TEST RRM_TEST RRM test register 0x8 32 read-write n 0x0 0x0 UDRA_CTRL0 UDRA_CTRL0 UDRA_CTRL0 register 0x10 32 read-write n 0x0 0x0 RELOAD_RDCFGPTR RELOAD_RDCFGPTR 0 1 UDRA_IRQ_ENABLE UDRA_IRQ_ENABLE UDRA_IRQ_ENABLE register 0x14 32 read-write n 0x0 0x0 CMD_END CMD_END 2 1 CMD_NUMBER_ERROR CMD_NUMBER_ERROR 3 1 CMD_START CMD_START 1 1 RADIO_CFG_PTR_RELOADED RADIO_CFG_PTR_RELOADED 0 1 UDRA_IRQ_STATUS UDRA_IRQ_STATUS UDRA_IRQ_STATUS register 0x18 32 read-write n 0x0 0x0 CMD_END CMD_END 2 1 CMD_NUMBER_ERROR CMD_NUMBER_ERROR 3 1 CMD_START CMD_START 1 1 RADIO_CFG_PTR_RELOADED RADIO_CFG_PTR_RELOADED 0 1 UDRA_RADIO_CFG_PTR UDRA_RADIO_CFG_PTR UDRA_RADIO_CFG_PTR register 0x1C 32 read-only n 0x0 0x0 RADIO_CONFIG_ADDRESS RADIO_CONFIG_ADDRESS 0 32 VIT_CONF_DIG_ENG VIT_CONF_DIG_ENG VIT_CONF_DIG_ENG register 0x16C 32 read-write n 0x0 0x0 VIT_CONF VIT_CONF 0 8 VIT_METR0_DIG_ENG VIT_METR0_DIG_ENG VIT_METR0_DIG_ENG register 0x170 32 read-write n 0x0 0x0 VIT_METR0 VIT_METR0 0 8 VIT_METR1_DIG_ENG VIT_METR1_DIG_ENG VIT_METR1_DIG_ENG register 0x174 32 read-write n 0x0 0x0 VIT_METR1 VIT_METR1 0 8 VIT_METR2_DIG_ENG VIT_METR2_DIG_ENG VIT_METR2_DIG_ENG register 0x178 32 read-write n 0x0 0x0 VIT_METR2 VIT_METR2 0 8 VIT_METR3_DIG_ENG VIT_METR3_DIG_ENG VIT_METR3_DIG_ENG register 0x17C 32 read-write n 0x0 0x0 VIT_METR3 VIT_METR3 0 8 VP_CPU_CMD_BUS VP_CPU_CMD_BUS VP_CPU_CMD_BUS register 0x60 32 read-write n 0x0 0x0 COMMAND COMMAND 0 3 COMMAND_REQ COMMAND_REQ 3 1 VP_CPU_IRQ_ENABLE VP_CPU_IRQ_ENABLE VP_CPU_IRQ_ENABLE register 0x68 32 read-write n 0x0 0x0 PORT_CMD_END PORT_CMD_END 4 1 PORT_CMD_START PORT_CMD_START 3 1 PORT_GRANT PORT_GRANT 0 1 PORT_PREEMPT PORT_PREEMPT 2 1 PORT_RELEASE PORT_RELEASE 1 1 VP_CPU_IRQ_STATUS VP_CPU_IRQ_STATUS VP_CPU_IRQ_STATUS register 0x6C 32 read-write n 0x0 0x0 CMD_END CMD_END 4 1 CMD_START CMD_START 3 1 PORT_GRANT PORT_GRANT 0 1 PORT_PREEMPT PORT_PREEMPT 2 1 PORT_RELEASE PORT_RELEASE 1 1 VP_CPU_SEMA_BUS VP_CPU_SEMA_BUS VP_CPU_SEMA_BUS register 0x64 32 read-write n 0x0 0x0 TAKE_PREEMPT TAKE_PREEMPT 4 1 TAKE_PRIO TAKE_PRIO 0 3 TAKE_REQ TAKE_REQ 3 1 XO32M_ANA_TST XO32M_ANA_TST XO32M_ANA_TST register 0x31C 32 read-write n 0x0 0x0 RFD_XO32M_XTCTRLPLL RFD_XO32M_XTCTRLPLL 1 1 XO32M_TST_SEL XO32M_TST_SEL 0 1