STMicroelectronics
STM32F100RE
2024.04.27
STM32F100RE
false
0
0
ADC1
Analog to digital converter
ADC
0x0
0x0
0x400
registers
n
ADC
ADC1 global interrupt
18
ADC_IRQ
ADC1 global interrupt
18
CR1
CR1
control register 1
0x4
32
read-write
n
0x0
0x0
AWDCH
Analog watchdog channel select bits
0
5
AWDEN
Analog watchdog enable on regular channels
23
1
AWDIE
Analog watchdog interrupt enable
6
1
AWDSGL
Enable the watchdog on a single channel in scan mode
9
1
DISCEN
Discontinuous mode on regular channels
11
1
DISCNUM
Discontinuous mode channel count
13
3
EOCIE
Interrupt enable for EOC
5
1
JAUTO
Automatic injected group conversion
10
1
JAWDEN
Analog watchdog enable on injected channels
22
1
JDISCEN
Discontinuous mode on injected channels
12
1
JEOCIE
Interrupt enable for injected channels
7
1
SCAN
Scan mode
8
1
CR2
CR2
control register 2
0x8
32
read-write
n
0x0
0x0
ADON
A/D converter ON / OFF
0
1
ALIGN
Data alignment
11
1
CAL
A/D calibration
2
1
CONT
Continuous conversion
1
1
DMA
Direct memory access mode
8
1
EXTSEL
External event select for regular group
17
3
EXTTRIG
External trigger conversion mode for regular channels
20
1
JEXTSEL
External event select for injected group
12
3
JEXTTRIG
External trigger conversion mode for injected channels
15
1
JSWSTART
Start conversion of injected channels
21
1
RSTCAL
Reset calibration
3
1
SWSTART
Start conversion of regular channels
22
1
TSVREFE
Temperature sensor and VREFINT enable
23
1
DR
DR
regular data register
0x4C
32
read-only
n
0x0
0x0
DATA
Regular data
0
16
HTR
HTR
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
HT
Analog watchdog higher threshold
0
12
JDR1
JDR1
injected data register x
0x3C
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR2
JDR2
injected data register x
0x40
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR3
JDR3
injected data register x
0x44
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR4
JDR4
injected data register x
0x48
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JOFR1
JOFR1
injected channel data offset register x
0x14
32
read-write
n
0x0
0x0
JOFFSET1
Data offset for injected channel 1
0
12
JOFR2
JOFR2
injected channel data offset register x
0x18
32
read-write
n
0x0
0x0
JOFFSET2
Data offset for injected channel 2
0
12
JOFR3
JOFR3
injected channel data offset register x
0x1C
32
read-write
n
0x0
0x0
JOFFSET3
Data offset for injected channel 3
0
12
JOFR4
JOFR4
injected channel data offset register x
0x20
32
read-write
n
0x0
0x0
JOFFSET4
Data offset for injected channel 4
0
12
JSQR
JSQR
injected sequence register
0x38
32
read-write
n
0x0
0x0
JL
Injected sequence length
20
2
JSQ1
1st conversion in injected sequence
0
5
JSQ2
2nd conversion in injected sequence
5
5
JSQ3
3rd conversion in injected sequence
10
5
JSQ4
4th conversion in injected sequence
15
5
LTR
LTR
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
LT
Analog watchdog lower threshold
0
12
SMPR1
SMPR1
sample time register 1
0xC
32
read-write
n
0x0
0x0
SMP10
Channel 10 sample time selection
0
3
SMP11
Channel 11 sample time selection
3
3
SMP12
Channel 12 sample time selection
6
3
SMP13
Channel 13 sample time selection
9
3
SMP14
Channel 14 sample time selection
12
3
SMP15
Channel 15 sample time selection
15
3
SMP16
Channel 16 sample time selection
18
3
SMP17
Channel 17 sample time selection
21
3
SMPR2
SMPR2
sample time register 2
0x10
32
read-write
n
0x0
0x0
SMP0
Channel 0 sample time selection
0
3
SMP1
Channel 1 sample time selection
3
3
SMP2
Channel 2 sample time selection
6
3
SMP3
Channel 3 sample time selection
9
3
SMP4
Channel 4 sample time selection
12
3
SMP5
Channel 5 sample time selection
15
3
SMP6
Channel 6 sample time selection
18
3
SMP7
Channel 7 sample time selection
21
3
SMP8
Channel 8 sample time selection
24
3
SMP9
Channel 9 sample time selection
27
3
SQR1
SQR1
regular sequence register 1
0x2C
32
read-write
n
0x0
0x0
L
Regular channel sequence length
20
4
SQ13
13th conversion in regular sequence
0
5
SQ14
14th conversion in regular sequence
5
5
SQ15
15th conversion in regular sequence
10
5
SQ16
16th conversion in regular sequence
15
5
SQR2
SQR2
regular sequence register 2
0x30
32
read-write
n
0x0
0x0
SQ10
10th conversion in regular sequence
15
5
SQ11
11th conversion in regular sequence
20
5
SQ12
12th conversion in regular sequence
25
5
SQ7
7th conversion in regular sequence
0
5
SQ8
8th conversion in regular sequence
5
5
SQ9
9th conversion in regular sequence
10
5
SQR3
SQR3
regular sequence register 3
0x34
32
read-write
n
0x0
0x0
SQ1
1st conversion in regular sequence
0
5
SQ2
2nd conversion in regular sequence
5
5
SQ3
3rd conversion in regular sequence
10
5
SQ4
4th conversion in regular sequence
15
5
SQ5
5th conversion in regular sequence
20
5
SQ6
6th conversion in regular sequence
25
5
SR
SR
status register
0x0
32
read-write
n
0x0
0x0
AWD
Analog watchdog flag
0
1
EOC
Regular channel end of conversion
1
1
JEOC
Injected channel end of conversion
2
1
JSTRT
Injected channel start flag
3
1
STRT
Regular channel start flag
4
1
AFIO
Alternate function I/O
AFIO
0x0
0x0
0x400
registers
n
EVCR
EVCR
Event Control Register (AFIO_EVCR)
0x0
32
read-write
n
0x0
0x0
EVOE
Event Output Enable
7
1
PIN
Pin selection
0
4
PORT
Port selection
4
3
EXTICR1
EXTICR1
External interrupt configuration register 1 (AFIO_EXTICR1)
0x8
32
read-write
n
0x0
0x0
EXTI0
EXTI0 configuration
0
4
EXTI1
EXTI1 configuration
4
4
EXTI2
EXTI2 configuration
8
4
EXTI3
EXTI3 configuration
12
4
EXTICR2
EXTICR2
External interrupt configuration register 2 (AFIO_EXTICR2)
0xC
32
read-write
n
0x0
0x0
EXTI4
EXTI4 configuration
0
4
EXTI5
EXTI5 configuration
4
4
EXTI6
EXTI6 configuration
8
4
EXTI7
EXTI7 configuration
12
4
EXTICR3
EXTICR3
External interrupt configuration register 3 (AFIO_EXTICR3)
0x10
32
read-write
n
0x0
0x0
EXTI10
EXTI10 configuration
8
4
EXTI11
EXTI11 configuration
12
4
EXTI8
EXTI8 configuration
0
4
EXTI9
EXTI9 configuration
4
4
EXTICR4
EXTICR4
External interrupt configuration register 4 (AFIO_EXTICR4)
0x14
32
read-write
n
0x0
0x0
EXTI12
EXTI12 configuration
0
4
EXTI13
EXTI13 configuration
4
4
EXTI14
EXTI14 configuration
8
4
EXTI15
EXTI15 configuration
12
4
MAPR
MAPR
AF remap and debug I/O configuration register (AFIO_MAPR)
0x4
32
read-write
n
0x0
0x0
I2C1_REMAP
I2C1 remapping
1
1
read-write
PD01_REMAP
Port D0/Port D1 mapping on OSCIN/OSCOUT
15
1
read-write
SPI1_REMAP
SPI1 remapping
0
1
read-write
SWJ_CFG
Serial wire JTAG configuration
24
3
write-only
TIM1_REMAP
TIM1 remapping
6
2
read-write
TIM2_REMAP
TIM2 remapping
8
2
read-write
TIM3_REMAP
TIM3 remapping
10
2
read-write
TIM4_REMAP
TIM4 remapping
12
1
read-write
TIM5CH4_IREMAP
Set and cleared by software
16
1
read-write
USART1_REMAP
USART1 remapping
2
1
read-write
USART2_REMAP
USART2 remapping
3
1
read-write
USART3_REMAP
USART3 remapping
4
2
read-write
MAPR2
MAPR2
AF remap and debug I/O configuration register
0x1C
32
read-write
n
0x0
0x0
CEC_REMAP
CEC remapping
3
1
FSMC_NADV
NADV connect/disconnect
10
1
MISC_REMAP
Miscellaneous features remapping
13
1
TIM12_REMAP
TIM12 remapping
12
1
TIM13_REMAP
TIM13 remapping
8
1
TIM14_REMAP
TIM14 remapping
9
1
TIM15_REMAP
TIM15 remapping
0
1
TIM16_REMAP
TIM16 remapping
1
1
TIM17_REMAP
TIM17 remapping
2
1
TIM1_DMA_REMAP
TIM1 DMA remapping
4
1
TIM67_DAC_DMA_REMAP
TIM67_DAC DMA remapping
11
1
BKP
Backup registers
BKP
0x0
0x0
0x400
registers
n
CR
CR
Backup control register (BKP_CR)
0x2C
32
read-write
n
0x0
0x0
TPAL
Tamper pin active level
1
1
TPE
Tamper pin enable
0
1
CSR
CSR
BKP_CSR control/status register (BKP_CSR)
0x30
32
read-write
n
0x0
0x0
CTE
Clear Tamper event
0
1
write-only
CTI
Clear Tamper Interrupt
1
1
write-only
TEF
Tamper Event Flag
8
1
read-only
TIF
Tamper Interrupt Flag
9
1
read-only
TPIE
Tamper Pin interrupt enable
2
1
read-write
DR1
DR1
Backup data register (BKP_DR)
0x0
32
read-write
n
0x0
0x0
D1
Backup data
0
16
DR10
DR10
Backup data register (BKP_DR)
0x24
32
read-write
n
0x0
0x0
D10
Backup data
0
16
DR11
DR11
Backup data register (BKP_DR)
0x3C
32
read-write
n
0x0
0x0
DR11
Backup data
0
16
DR12
DR12
Backup data register (BKP_DR)
0x40
32
read-write
n
0x0
0x0
DR12
Backup data
0
16
DR13
DR13
Backup data register (BKP_DR)
0x44
32
read-write
n
0x0
0x0
DR13
Backup data
0
16
DR14
DR14
Backup data register (BKP_DR)
0x48
32
read-write
n
0x0
0x0
D14
Backup data
0
16
DR15
DR15
Backup data register (BKP_DR)
0x4C
32
read-write
n
0x0
0x0
D15
Backup data
0
16
DR16
DR16
Backup data register (BKP_DR)
0x50
32
read-write
n
0x0
0x0
D16
Backup data
0
16
DR17
DR17
Backup data register (BKP_DR)
0x54
32
read-write
n
0x0
0x0
D17
Backup data
0
16
DR18
DR18
Backup data register (BKP_DR)
0x58
32
read-write
n
0x0
0x0
D18
Backup data
0
16
DR19
DR19
Backup data register (BKP_DR)
0x5C
32
read-write
n
0x0
0x0
D19
Backup data
0
16
DR2
DR2
Backup data register (BKP_DR)
0x4
32
read-write
n
0x0
0x0
D2
Backup data
0
16
DR20
DR20
Backup data register (BKP_DR)
0x60
32
read-write
n
0x0
0x0
D20
Backup data
0
16
DR21
DR21
Backup data register (BKP_DR)
0x64
32
read-write
n
0x0
0x0
D21
Backup data
0
16
DR22
DR22
Backup data register (BKP_DR)
0x68
32
read-write
n
0x0
0x0
D22
Backup data
0
16
DR23
DR23
Backup data register (BKP_DR)
0x6C
32
read-write
n
0x0
0x0
D23
Backup data
0
16
DR24
DR24
Backup data register (BKP_DR)
0x70
32
read-write
n
0x0
0x0
D24
Backup data
0
16
DR25
DR25
Backup data register (BKP_DR)
0x74
32
read-write
n
0x0
0x0
D25
Backup data
0
16
DR26
DR26
Backup data register (BKP_DR)
0x78
32
read-write
n
0x0
0x0
D26
Backup data
0
16
DR27
DR27
Backup data register (BKP_DR)
0x7C
32
read-write
n
0x0
0x0
D27
Backup data
0
16
DR28
DR28
Backup data register (BKP_DR)
0x80
32
read-write
n
0x0
0x0
D28
Backup data
0
16
DR29
DR29
Backup data register (BKP_DR)
0x84
32
read-write
n
0x0
0x0
D29
Backup data
0
16
DR3
DR3
Backup data register (BKP_DR)
0x8
32
read-write
n
0x0
0x0
D3
Backup data
0
16
DR30
DR30
Backup data register (BKP_DR)
0x88
32
read-write
n
0x0
0x0
D30
Backup data
0
16
DR31
DR31
Backup data register (BKP_DR)
0x8C
32
read-write
n
0x0
0x0
D31
Backup data
0
16
DR32
DR32
Backup data register (BKP_DR)
0x90
32
read-write
n
0x0
0x0
D32
Backup data
0
16
DR33
DR33
Backup data register (BKP_DR)
0x94
32
read-write
n
0x0
0x0
D33
Backup data
0
16
DR34
DR34
Backup data register (BKP_DR)
0x98
32
read-write
n
0x0
0x0
D34
Backup data
0
16
DR35
DR35
Backup data register (BKP_DR)
0x9C
32
read-write
n
0x0
0x0
D35
Backup data
0
16
DR36
DR36
Backup data register (BKP_DR)
0xA0
32
read-write
n
0x0
0x0
D36
Backup data
0
16
DR37
DR37
Backup data register (BKP_DR)
0xA4
32
read-write
n
0x0
0x0
D37
Backup data
0
16
DR38
DR38
Backup data register (BKP_DR)
0xA8
32
read-write
n
0x0
0x0
D38
Backup data
0
16
DR39
DR39
Backup data register (BKP_DR)
0xAC
32
read-write
n
0x0
0x0
D39
Backup data
0
16
DR4
DR4
Backup data register (BKP_DR)
0xC
32
read-write
n
0x0
0x0
D4
Backup data
0
16
DR40
DR40
Backup data register (BKP_DR)
0xB0
32
read-write
n
0x0
0x0
D40
Backup data
0
16
DR41
DR41
Backup data register (BKP_DR)
0xB4
32
read-write
n
0x0
0x0
D41
Backup data
0
16
DR42
DR42
Backup data register (BKP_DR)
0xB8
32
read-write
n
0x0
0x0
D42
Backup data
0
16
DR5
DR5
Backup data register (BKP_DR)
0x10
32
read-write
n
0x0
0x0
D5
Backup data
0
16
DR6
DR6
Backup data register (BKP_DR)
0x14
32
read-write
n
0x0
0x0
D6
Backup data
0
16
DR7
DR7
Backup data register (BKP_DR)
0x18
32
read-write
n
0x0
0x0
D7
Backup data
0
16
DR8
DR8
Backup data register (BKP_DR)
0x1C
32
read-write
n
0x0
0x0
D8
Backup data
0
16
DR9
DR9
Backup data register (BKP_DR)
0x20
32
read-write
n
0x0
0x0
D9
Backup data
0
16
RTCCR
RTCCR
RTC clock calibration register (BKP_RTCCR)
0x28
32
read-write
n
0x0
0x0
ASOE
Alarm or second output enable
8
1
ASOS
Alarm or second output selection
9
1
CAL
Calibration value
0
7
CCO
Calibration Clock Output
7
1
CEC
HDMI-CEC controller
CEC
0x0
0x0
0x400
registers
n
CEC_IRQ
CEC global interrupt
42
CEC
CEC global interrupt
42
CFGR
CFGR
configuration register
0x0
32
read-write
n
0x0
0x0
BPEM
Bit period error mode
3
1
BTEM
Bit timing error mode
2
1
IE
Interrupt enable
1
1
PE
Peripheral enable
0
1
CSR
CSR
CEC control and status register
0x10
32
read-write
n
0x0
0x0
RBTF
Rx byte/block transfer finished
7
1
REOM
Rx end of message
5
1
RERR
Rx error
6
1
RSOM
Rx start of message
4
1
TBTRF
Tx byte transfer request or block transfer finished
3
1
TEOM
Tx end of message
1
1
TERR
Tx error
2
1
TSOM
Tx start of message
0
1
ESR
ESR
CEC error status register
0xC
32
read-only
n
0x0
0x0
ACKE
Block acknowledge error
4
1
BPE
Bit period error
1
1
BTE
Bit timing error
0
1
LINE
Line error
5
1
RBTFE
Rx block transfer finished error
2
1
SBE
Start bit error
3
1
TBTFE
Tx block transfer finished error
6
1
OAR
OAR
CEC own address register
0x4
32
read-write
n
0x0
0x0
OA
Own address
0
4
PRES
PRES
Rx Data Register
0x8
32
read-write
n
0x0
0x0
PRESC
CEC Rx Data Register
0
14
RXD
RXD
CEC Rx data register
0x18
32
read-only
n
0x0
0x0
RXD
Rx data
0
8
TXD
TXD
CEC Tx data register
0x14
32
read-write
n
0x0
0x0
TXD
Tx Data register
0
8
CRC
CRC calculation unit
CRC
0x0
0x0
0x400
registers
n
CR
CR
Control register
0x8
32
write-only
n
0x0
0x0
RESET
Reset bit
0
1
DR
DR
Data register
0x0
32
read-write
n
0x0
0x0
DR
Data Register
0
32
IDR
IDR
Independent Data register
0x4
32
read-write
n
0x0
0x0
IDR
Independent Data register
0
8
DAC
Digital to analog converter
DAC
0x0
0x0
0x400
registers
n
TIM6_DAC_IRQ
TIM6 global and DAC underrun
interrupts
54
TIM6_DAC
TIM6 global and DAC underrun interrupts
54
CR
CR
Control register (DAC_CR)
0x0
32
read-write
n
0x0
0x0
BOFF1
DAC channel1 output buffer disable
1
1
BOFF2
DAC channel2 output buffer disable
17
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN2
DAC channel2 DMA enable
28
1
DMAUDRIE1
DAC channel1 DMA underrun interrupt enable
13
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt enable
29
1
EN1
DAC channel1 enable
0
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude selector
8
4
MAMP2
DAC channel2 mask/amplitude selector
24
4
TEN1
DAC channel1 trigger enable
2
1
TEN2
DAC channel2 trigger enable
18
1
TSEL1
DAC channel1 trigger selection
3
3
TSEL2
DAC channel2 trigger selection
19
3
WAVE1
DAC channel1 noise/triangle wave generation enable
6
2
WAVE2
DAC channel2 noise/triangle wave generation enable
22
2
DHR12L1
DHR12L1
DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
0xC
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12L2
DHR12L2
DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
0x18
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit left-aligned data
4
12
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
0x24
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DACC2DHR
DAC channel2 12-bit right-aligned data
20
12
DHR12R1
DHR12R1
DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
0x8
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR12R2
DHR12R2
DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
0x14
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit right-aligned data
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
0x20
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DACC2DHR
DAC channel2 12-bit right-aligned data
16
12
DHR8R1
DHR8R1
DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
0x10
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DHR8R2
DHR8R2
DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
0x1C
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 8-bit right-aligned data
0
8
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
0x28
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DACC2DHR
DAC channel2 8-bit right-aligned data
8
8
DOR1
DOR1
DAC channel1 data output register (DAC_DOR1)
0x2C
32
read-only
n
0x0
0x0
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
DAC channel2 data output register (DAC_DOR2)
0x30
32
read-only
n
0x0
0x0
DACC2DOR
DAC channel2 data output
0
12
SR
SR
DAC status register
0x34
32
read-write
n
0x0
0x0
DMAUDR1
DAC channel1 DMA underrun flag
13
1
DMAUDR2
DAC channel2 DMA underrun flag
29
1
SWTRIGR
SWTRIGR
DAC software trigger register (DAC_SWTRIGR)
0x4
32
write-only
n
0x0
0x0
SWTRIG1
DAC channel1 software trigger
0
1
SWTRIG2
DAC channel2 software trigger
1
1
DBG
Debug support
DBG
0x0
0x0
0x400
registers
n
CR
CR
DBGMCU_CR
0x4
32
read-write
n
0x0
0x0
DBG_I2C1_SMBUS_TIMEOUT
DBG_I2C1_SMBUS_TIMEOUT
15
1
DBG_I2C2_SMBUS_TIMEOUT
DBG_I2C2_SMBUS_TIMEOUT
16
1
DBG_IWDG_STOP
DBG_IWDG_STOP
8
1
DBG_SLEEP
DBG_SLEEP
0
1
DBG_STANDBY
DBG_STANDBY
2
1
DBG_STOP
DBG_STOP
1
1
DBG_TIM12_STOP
DBG_TIM12_STOP
25
1
DBG_TIM13_STOP
DBG_TIM13_STOP
26
1
DBG_TIM14_STOP
DBG_TIM14_STOP
27
1
DBG_TIM15_STOP
DBG_TIM15_STOP
22
1
DBG_TIM16_STOP
DBG_TIM16_STOP
23
1
DBG_TIM17_STOP
DBG_TIM17_STOP
24
1
DBG_TIM1_STOP
DBG_TIM1_STOP
10
1
DBG_TIM2_STOP
DBG_TIM2_STOP
11
1
DBG_TIM3_STOP
DBG_TIM3_STOP
12
1
DBG_TIM4_STOP
DBG_TIM4_STOP
13
1
DBG_TIM5_STOP
DBG_TIM5_STOP
18
1
DBG_TIM6_STOP
DBG_TIM6_STOP
19
1
DBG_TIM7_STOP
DBG_TIM7_STOP
20
1
DBG_WWDG_STOP
DBG_WWDG_STOP
9
1
TRACE_IOEN
TRACE_IOEN
5
1
TRACE_MODE
TRACE_MODE
6
2
IDCODE
IDCODE
DBGMCU_IDCODE
0x0
32
read-only
n
0x0
0x0
DEV_ID
DEV_ID
0
12
REV_ID
REV_ID
16
16
DMA1
DMA controller
DMA
0x0
0x0
0x400
registers
n
DMA1_Channel1_IRQ
DMA1 Channel1 global interrupt
11
DMA1_Channel1
DMA1 Channel1 global interrupt
11
DMA1_Channel2_IRQ
DMA1 Channel2 global interrupt
12
DMA1_Channel2
DMA1 Channel2 global interrupt
12
DMA1_Channel3_IRQ
DMA1 Channel3 global interrupt
13
DMA1_Channel3
DMA1 Channel3 global interrupt
13
DMA1_Channel4_IRQ
DMA1 Channel4 global interrupt
14
DMA1_Channel4
DMA1 Channel4 global interrupt
14
DMA1_Channel5_IRQ
DMA1 Channel5 global interrupt
15
DMA1_Channel5
DMA1 Channel5 global interrupt
15
DMA1_Channel6_IRQ
DMA1 Channel6 global interrupt
16
DMA1_Channel6
DMA1 Channel6 global interrupt
16
DMA1_Channel7_IRQ
DMA1 Channel7 global interrupt
17
DMA1_Channel7
DMA1 Channel7 global interrupt
17
CCR1
CCR1
DMA channel configuration register (DMA_CCR)
0x8
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR2
CCR2
DMA channel configuration register (DMA_CCR)
0x1C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR3
CCR3
DMA channel configuration register (DMA_CCR)
0x30
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR4
CCR4
DMA channel configuration register (DMA_CCR)
0x44
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR5
CCR5
DMA channel configuration register (DMA_CCR)
0x58
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR6
CCR6
DMA channel configuration register (DMA_CCR)
0x6C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR7
CCR7
DMA channel configuration register (DMA_CCR)
0x80
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CMAR1
CMAR1
DMA channel 1 memory address register
0x14
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR2
CMAR2
DMA channel 2 memory address register
0x28
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR3
CMAR3
DMA channel 3 memory address register
0x3C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR4
CMAR4
DMA channel 4 memory address register
0x50
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR5
CMAR5
DMA channel 5 memory address register
0x64
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR6
CMAR6
DMA channel 6 memory address register
0x78
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR7
CMAR7
DMA channel 7 memory address register
0x8C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CNDTR1
CNDTR1
DMA channel 1 number of data register
0xC
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR2
CNDTR2
DMA channel 2 number of data register
0x20
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR3
CNDTR3
DMA channel 3 number of data register
0x34
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR4
CNDTR4
DMA channel 4 number of data register
0x48
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR5
CNDTR5
DMA channel 5 number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR6
CNDTR6
DMA channel 6 number of data register
0x70
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR7
CNDTR7
DMA channel 7 number of data register
0x84
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CPAR1
CPAR1
DMA channel 1 peripheral address register
0x10
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR2
CPAR2
DMA channel 2 peripheral address register
0x24
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR3
CPAR3
DMA channel 3 peripheral address register
0x38
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR4
CPAR4
DMA channel 4 peripheral address register
0x4C
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR5
CPAR5
DMA channel 5 peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR6
CPAR6
DMA channel 6 peripheral address register
0x74
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR7
CPAR7
DMA channel 7 peripheral address register
0x88
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
IFCR
IFCR
DMA interrupt flag clear register (DMA_IFCR)
0x4
32
write-only
n
0x0
0x0
CGIF1
Channel 1 Global interrupt clear
0
1
CGIF2
Channel 2 Global interrupt clear
4
1
CGIF3
Channel 3 Global interrupt clear
8
1
CGIF4
Channel 4 Global interrupt clear
12
1
CGIF5
Channel 5 Global interrupt clear
16
1
CGIF6
Channel 6 Global interrupt clear
20
1
CGIF7
Channel 7 Global interrupt clear
24
1
CHTIF1
Channel 1 Half Transfer clear
2
1
CHTIF2
Channel 2 Half Transfer clear
6
1
CHTIF3
Channel 3 Half Transfer clear
10
1
CHTIF4
Channel 4 Half Transfer clear
14
1
CHTIF5
Channel 5 Half Transfer clear
18
1
CHTIF6
Channel 6 Half Transfer clear
22
1
CHTIF7
Channel 7 Half Transfer clear
26
1
CTCIF1
Channel 1 Transfer Complete clear
1
1
CTCIF2
Channel 2 Transfer Complete clear
5
1
CTCIF3
Channel 3 Transfer Complete clear
9
1
CTCIF4
Channel 4 Transfer Complete clear
13
1
CTCIF5
Channel 5 Transfer Complete clear
17
1
CTCIF6
Channel 6 Transfer Complete clear
21
1
CTCIF7
Channel 7 Transfer Complete clear
25
1
CTEIF1
Channel 1 Transfer Error clear
3
1
CTEIF2
Channel 2 Transfer Error clear
7
1
CTEIF3
Channel 3 Transfer Error clear
11
1
CTEIF4
Channel 4 Transfer Error clear
15
1
CTEIF5
Channel 5 Transfer Error clear
19
1
CTEIF6
Channel 6 Transfer Error clear
23
1
CTEIF7
Channel 7 Transfer Error clear
27
1
ISR
ISR
DMA interrupt status register (DMA_ISR)
0x0
32
read-only
n
0x0
0x0
GIF1
Channel 1 Global interrupt flag
0
1
GIF2
Channel 2 Global interrupt flag
4
1
GIF3
Channel 3 Global interrupt flag
8
1
GIF4
Channel 4 Global interrupt flag
12
1
GIF5
Channel 5 Global interrupt flag
16
1
GIF6
Channel 6 Global interrupt flag
20
1
GIF7
Channel 7 Global interrupt flag
24
1
HTIF1
Channel 1 Half Transfer Complete flag
2
1
HTIF2
Channel 2 Half Transfer Complete flag
6
1
HTIF3
Channel 3 Half Transfer Complete flag
10
1
HTIF4
Channel 4 Half Transfer Complete flag
14
1
HTIF5
Channel 5 Half Transfer Complete flag
18
1
HTIF6
Channel 6 Half Transfer Complete flag
22
1
HTIF7
Channel 7 Half Transfer Complete flag
26
1
TCIF1
Channel 1 Transfer Complete flag
1
1
TCIF2
Channel 2 Transfer Complete flag
5
1
TCIF3
Channel 3 Transfer Complete flag
9
1
TCIF4
Channel 4 Transfer Complete flag
13
1
TCIF5
Channel 5 Transfer Complete flag
17
1
TCIF6
Channel 6 Transfer Complete flag
21
1
TCIF7
Channel 7 Transfer Complete flag
25
1
TEIF1
Channel 1 Transfer Error flag
3
1
TEIF2
Channel 2 Transfer Error flag
7
1
TEIF3
Channel 3 Transfer Error flag
11
1
TEIF4
Channel 4 Transfer Error flag
15
1
TEIF5
Channel 5 Transfer Error flag
19
1
TEIF6
Channel 6 Transfer Error flag
23
1
TEIF7
Channel 7 Transfer Error flag
27
1
DMA2
DMA controller
DMA
0x0
0x0
0x400
registers
n
DMA2_Channel1_IRQ
DMA2 Channel1 global interrupt
56
DMA2_Channel1
DMA2 Channel1 global interrupt
56
DMA2_Channel2_IRQ
DMA2 Channel2 global interrupt
57
DMA2_Channel2
DMA2 Channel2 global interrupt
57
DMA2_Channel3_IRQ
DMA2 Channel3 global interrupt
58
DMA2_Channel3
DMA2 Channel3 global interrupt
58
DMA2_Channel4_5_IRQ
DMA2 Channel4 and DMA2 Channel5 global
interrupt
59
DMA2_Channel4_5
DMA2 Channel4 and DMA2 Channel5 global
interrupt
59
CCR1
CCR1
DMA channel configuration register (DMA_CCR)
0x8
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR2
CCR2
DMA channel configuration register (DMA_CCR)
0x1C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR3
CCR3
DMA channel configuration register (DMA_CCR)
0x30
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR4
CCR4
DMA channel configuration register (DMA_CCR)
0x44
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR5
CCR5
DMA channel configuration register (DMA_CCR)
0x58
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR6
CCR6
DMA channel configuration register (DMA_CCR)
0x6C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR7
CCR7
DMA channel configuration register (DMA_CCR)
0x80
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CMAR1
CMAR1
DMA channel 1 memory address register
0x14
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR2
CMAR2
DMA channel 2 memory address register
0x28
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR3
CMAR3
DMA channel 3 memory address register
0x3C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR4
CMAR4
DMA channel 4 memory address register
0x50
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR5
CMAR5
DMA channel 5 memory address register
0x64
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR6
CMAR6
DMA channel 6 memory address register
0x78
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR7
CMAR7
DMA channel 7 memory address register
0x8C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CNDTR1
CNDTR1
DMA channel 1 number of data register
0xC
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR2
CNDTR2
DMA channel 2 number of data register
0x20
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR3
CNDTR3
DMA channel 3 number of data register
0x34
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR4
CNDTR4
DMA channel 4 number of data register
0x48
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR5
CNDTR5
DMA channel 5 number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR6
CNDTR6
DMA channel 6 number of data register
0x70
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR7
CNDTR7
DMA channel 7 number of data register
0x84
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CPAR1
CPAR1
DMA channel 1 peripheral address register
0x10
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR2
CPAR2
DMA channel 2 peripheral address register
0x24
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR3
CPAR3
DMA channel 3 peripheral address register
0x38
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR4
CPAR4
DMA channel 4 peripheral address register
0x4C
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR5
CPAR5
DMA channel 5 peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR6
CPAR6
DMA channel 6 peripheral address register
0x74
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR7
CPAR7
DMA channel 7 peripheral address register
0x88
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
IFCR
IFCR
DMA interrupt flag clear register (DMA_IFCR)
0x4
32
write-only
n
0x0
0x0
CGIF1
Channel 1 Global interrupt clear
0
1
CGIF2
Channel 2 Global interrupt clear
4
1
CGIF3
Channel 3 Global interrupt clear
8
1
CGIF4
Channel 4 Global interrupt clear
12
1
CGIF5
Channel 5 Global interrupt clear
16
1
CGIF6
Channel 6 Global interrupt clear
20
1
CGIF7
Channel 7 Global interrupt clear
24
1
CHTIF1
Channel 1 Half Transfer clear
2
1
CHTIF2
Channel 2 Half Transfer clear
6
1
CHTIF3
Channel 3 Half Transfer clear
10
1
CHTIF4
Channel 4 Half Transfer clear
14
1
CHTIF5
Channel 5 Half Transfer clear
18
1
CHTIF6
Channel 6 Half Transfer clear
22
1
CHTIF7
Channel 7 Half Transfer clear
26
1
CTCIF1
Channel 1 Transfer Complete clear
1
1
CTCIF2
Channel 2 Transfer Complete clear
5
1
CTCIF3
Channel 3 Transfer Complete clear
9
1
CTCIF4
Channel 4 Transfer Complete clear
13
1
CTCIF5
Channel 5 Transfer Complete clear
17
1
CTCIF6
Channel 6 Transfer Complete clear
21
1
CTCIF7
Channel 7 Transfer Complete clear
25
1
CTEIF1
Channel 1 Transfer Error clear
3
1
CTEIF2
Channel 2 Transfer Error clear
7
1
CTEIF3
Channel 3 Transfer Error clear
11
1
CTEIF4
Channel 4 Transfer Error clear
15
1
CTEIF5
Channel 5 Transfer Error clear
19
1
CTEIF6
Channel 6 Transfer Error clear
23
1
CTEIF7
Channel 7 Transfer Error clear
27
1
ISR
ISR
DMA interrupt status register (DMA_ISR)
0x0
32
read-only
n
0x0
0x0
GIF1
Channel 1 Global interrupt flag
0
1
GIF2
Channel 2 Global interrupt flag
4
1
GIF3
Channel 3 Global interrupt flag
8
1
GIF4
Channel 4 Global interrupt flag
12
1
GIF5
Channel 5 Global interrupt flag
16
1
GIF6
Channel 6 Global interrupt flag
20
1
GIF7
Channel 7 Global interrupt flag
24
1
HTIF1
Channel 1 Half Transfer Complete flag
2
1
HTIF2
Channel 2 Half Transfer Complete flag
6
1
HTIF3
Channel 3 Half Transfer Complete flag
10
1
HTIF4
Channel 4 Half Transfer Complete flag
14
1
HTIF5
Channel 5 Half Transfer Complete flag
18
1
HTIF6
Channel 6 Half Transfer Complete flag
22
1
HTIF7
Channel 7 Half Transfer Complete flag
26
1
TCIF1
Channel 1 Transfer Complete flag
1
1
TCIF2
Channel 2 Transfer Complete flag
5
1
TCIF3
Channel 3 Transfer Complete flag
9
1
TCIF4
Channel 4 Transfer Complete flag
13
1
TCIF5
Channel 5 Transfer Complete flag
17
1
TCIF6
Channel 6 Transfer Complete flag
21
1
TCIF7
Channel 7 Transfer Complete flag
25
1
TEIF1
Channel 1 Transfer Error flag
3
1
TEIF2
Channel 2 Transfer Error flag
7
1
TEIF3
Channel 3 Transfer Error flag
11
1
TEIF4
Channel 4 Transfer Error flag
15
1
TEIF5
Channel 5 Transfer Error flag
19
1
TEIF6
Channel 6 Transfer Error flag
23
1
TEIF7
Channel 7 Transfer Error flag
27
1
EXTI
EXTI
EXTI
0x0
0x0
0x400
registers
n
TAMPER_STAMP_IRQ
Tamper and TimeStamp through EXTI line
interrupts
2
TAMPER_STAMP
Tamper and TimeStamp through EXTI line interrupts
2
EXTI0
EXTI Line0 interrupt
6
EXTI0_IRQ
EXTI Line0 interrupt
6
EXTI1
EXTI Line1 interrupt
7
EXTI1_IRQ
EXTI Line1 interrupt
7
EXTI2
EXTI Line2 interrupt
8
EXTI2_IRQ
EXTI Line2 interrupt
8
EXTI3
EXTI Line3 interrupt
9
EXTI3_IRQ
EXTI Line3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
EXTI4_IRQ
EXTI Line4 interrupt
10
EXTI9_5
EXTI Line[9:5] interrupts
23
EXTI9_5_IRQ
EXTI Line[9:5] interrupts
23
EXTI15_10
EXTI Line[15:10] interrupts
40
EXTI15_10_IRQ
EXTI Line[15:10] interrupts
40
EMR
EMR
Event mask register (EXTI_EMR)
0x4
32
read-write
n
0x0
0x0
MR0
Event Mask on line 0
0
1
MR1
Event Mask on line 1
1
1
MR10
Event Mask on line 10
10
1
MR11
Event Mask on line 11
11
1
MR12
Event Mask on line 12
12
1
MR13
Event Mask on line 13
13
1
MR14
Event Mask on line 14
14
1
MR15
Event Mask on line 15
15
1
MR16
Event Mask on line 16
16
1
MR17
Event Mask on line 17
17
1
MR2
Event Mask on line 2
2
1
MR3
Event Mask on line 3
3
1
MR4
Event Mask on line 4
4
1
MR5
Event Mask on line 5
5
1
MR6
Event Mask on line 6
6
1
MR7
Event Mask on line 7
7
1
MR8
Event Mask on line 8
8
1
MR9
Event Mask on line 9
9
1
FTSR
FTSR
Falling Trigger selection register (EXTI_FTSR)
0xC
32
read-write
n
0x0
0x0
TR0
Falling trigger event configuration of line 0
0
1
TR1
Falling trigger event configuration of line 1
1
1
TR10
Falling trigger event configuration of line 10
10
1
TR11
Falling trigger event configuration of line 11
11
1
TR12
Falling trigger event configuration of line 12
12
1
TR13
Falling trigger event configuration of line 13
13
1
TR14
Falling trigger event configuration of line 14
14
1
TR15
Falling trigger event configuration of line 15
15
1
TR16
Falling trigger event configuration of line 16
16
1
TR17
Falling trigger event configuration of line 17
17
1
TR2
Falling trigger event configuration of line 2
2
1
TR3
Falling trigger event configuration of line 3
3
1
TR4
Falling trigger event configuration of line 4
4
1
TR5
Falling trigger event configuration of line 5
5
1
TR6
Falling trigger event configuration of line 6
6
1
TR7
Falling trigger event configuration of line 7
7
1
TR8
Falling trigger event configuration of line 8
8
1
TR9
Falling trigger event configuration of line 9
9
1
IMR
IMR
Interrupt mask register (EXTI_IMR)
0x0
32
read-write
n
0x0
0x0
MR0
Interrupt Mask on line 0
0
1
MR1
Interrupt Mask on line 1
1
1
MR10
Interrupt Mask on line 10
10
1
MR11
Interrupt Mask on line 11
11
1
MR12
Interrupt Mask on line 12
12
1
MR13
Interrupt Mask on line 13
13
1
MR14
Interrupt Mask on line 14
14
1
MR15
Interrupt Mask on line 15
15
1
MR16
Interrupt Mask on line 16
16
1
MR17
Interrupt Mask on line 17
17
1
MR2
Interrupt Mask on line 2
2
1
MR3
Interrupt Mask on line 3
3
1
MR4
Interrupt Mask on line 4
4
1
MR5
Interrupt Mask on line 5
5
1
MR6
Interrupt Mask on line 6
6
1
MR7
Interrupt Mask on line 7
7
1
MR8
Interrupt Mask on line 8
8
1
MR9
Interrupt Mask on line 9
9
1
PR
PR
Pending register (EXTI_PR)
0x14
32
read-write
n
0x0
0x0
PR0
Pending bit 0
0
1
PR1
Pending bit 1
1
1
PR10
Pending bit 10
10
1
PR11
Pending bit 11
11
1
PR12
Pending bit 12
12
1
PR13
Pending bit 13
13
1
PR14
Pending bit 14
14
1
PR15
Pending bit 15
15
1
PR16
Pending bit 16
16
1
PR17
Pending bit 17
17
1
PR2
Pending bit 2
2
1
PR3
Pending bit 3
3
1
PR4
Pending bit 4
4
1
PR5
Pending bit 5
5
1
PR6
Pending bit 6
6
1
PR7
Pending bit 7
7
1
PR8
Pending bit 8
8
1
PR9
Pending bit 9
9
1
RTSR
RTSR
Rising Trigger selection register (EXTI_RTSR)
0x8
32
read-write
n
0x0
0x0
TR0
Rising trigger event configuration of line 0
0
1
TR1
Rising trigger event configuration of line 1
1
1
TR10
Rising trigger event configuration of line 10
10
1
TR11
Rising trigger event configuration of line 11
11
1
TR12
Rising trigger event configuration of line 12
12
1
TR13
Rising trigger event configuration of line 13
13
1
TR14
Rising trigger event configuration of line 14
14
1
TR15
Rising trigger event configuration of line 15
15
1
TR16
Rising trigger event configuration of line 16
16
1
TR17
Rising trigger event configuration of line 17
17
1
TR2
Rising trigger event configuration of line 2
2
1
TR3
Rising trigger event configuration of line 3
3
1
TR4
Rising trigger event configuration of line 4
4
1
TR5
Rising trigger event configuration of line 5
5
1
TR6
Rising trigger event configuration of line 6
6
1
TR7
Rising trigger event configuration of line 7
7
1
TR8
Rising trigger event configuration of line 8
8
1
TR9
Rising trigger event configuration of line 9
9
1
SWIER
SWIER
Software interrupt event register (EXTI_SWIER)
0x10
32
read-write
n
0x0
0x0
SWIER0
Software Interrupt on line 0
0
1
SWIER1
Software Interrupt on line 1
1
1
SWIER10
Software Interrupt on line 10
10
1
SWIER11
Software Interrupt on line 11
11
1
SWIER12
Software Interrupt on line 12
12
1
SWIER13
Software Interrupt on line 13
13
1
SWIER14
Software Interrupt on line 14
14
1
SWIER15
Software Interrupt on line 15
15
1
SWIER16
Software Interrupt on line 16
16
1
SWIER17
Software Interrupt on line 17
17
1
SWIER2
Software Interrupt on line 2
2
1
SWIER3
Software Interrupt on line 3
3
1
SWIER4
Software Interrupt on line 4
4
1
SWIER5
Software Interrupt on line 5
5
1
SWIER6
Software Interrupt on line 6
6
1
SWIER7
Software Interrupt on line 7
7
1
SWIER8
Software Interrupt on line 8
8
1
SWIER9
Software Interrupt on line 9
9
1
FLASH
FLASH
FLASH
0x0
0x0
0x400
registers
n
FLASH_IRQ
Flash global interrupt
4
FLASH
Flash global interrupt
4
ACR
ACR
Flash access control register
0x0
32
read-write
n
0x0
0x0
HLFCYA
Flash half cycle access enable
3
1
AR
AR
Flash address register
0x14
32
write-only
n
0x0
0x0
FAR
Flash Address
0
32
CR
CR
Control register
0x10
32
read-write
n
0x0
0x0
EOPIE
End of operation interrupt enable
12
1
ERRIE
Error interrupt enable
10
1
LOCK
Lock
7
1
MER
Mass Erase
2
1
OPTER
Option byte erase
5
1
OPTPG
Option byte programming
4
1
OPTWRE
Option bytes write enable
9
1
PER
Page Erase
1
1
PG
Programming
0
1
STRT
Start
6
1
KEYR
KEYR
Flash key register
0x4
32
write-only
n
0x0
0x0
KEY
FPEC key
0
32
OBR
OBR
Option byte register
0x1C
32
read-only
n
0x0
0x0
Data0
Data0
10
8
Data1
Data1
18
8
nRST_STDBY
nRST_STDBY
4
1
nRST_STOP
nRST_STOP
3
1
OPTERR
Option byte error
0
1
RDPRT
Read protection
1
1
WDG_SW
WDG_SW
2
1
OPTKEYR
OPTKEYR
Flash option key register
0x8
32
write-only
n
0x0
0x0
OPTKEY
Option byte key
0
32
SR
SR
Status register
0xC
32
read-write
n
0x0
0x0
BSY
Busy
0
1
read-only
EOP
End of operation
5
1
read-write
PGERR
Programming error
2
1
read-write
WRPRTERR
Write protection error
4
1
read-write
WRPR
WRPR
Write protection register
0x20
32
read-only
n
0x0
0x0
WRP
Write protect
0
32
FSMC
Flexible static memory controller
FSMC
0x0
0x0
0x1000
registers
n
0x1000
0xFFFFF400
reserved
n
FSMC
FSMC global interrupt
48
FSMC_IRQ
FSMC global interrupt
48
BCR1
BCR1
SRAM/NOR-Flash chip-select control register 1
0x0
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WREN
WREN
12
1
BCR2
BCR2
SRAM/NOR-Flash chip-select control register 2
0x8
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BCR3
BCR3
SRAM/NOR-Flash chip-select control register 3
0x10
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BCR4
BCR4
SRAM/NOR-Flash chip-select control register 4
0x18
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BTR1
BTR1
SRAM/NOR-Flash chip-select timing register 1
0x4
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR2
BTR2
SRAM/NOR-Flash chip-select timing register 2
0xC
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR3
BTR3
SRAM/NOR-Flash chip-select timing register 3
0x14
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR4
BTR4
SRAM/NOR-Flash chip-select timing register 4
0x1C
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR1
BWTR1
SRAM/NOR-Flash write timing registers 1
0x104
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR2
BWTR2
SRAM/NOR-Flash write timing registers 2
0x10C
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR3
BWTR3
SRAM/NOR-Flash write timing registers 3
0x114
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR4
BWTR4
SRAM/NOR-Flash write timing registers 4
0x11C
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
GPIOA
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BRR
BRR
Port bit reset register (GPIOn_BRR)
0x14
32
write-only
n
0x0
0x0
BR0
Reset bit 0
0
1
BR1
Reset bit 1
1
1
BR10
Reset bit 10
10
1
BR11
Reset bit 11
11
1
BR12
Reset bit 12
12
1
BR13
Reset bit 13
13
1
BR14
Reset bit 14
14
1
BR15
Reset bit 15
15
1
BR2
Reset bit 1
2
1
BR3
Reset bit 3
3
1
BR4
Reset bit 4
4
1
BR5
Reset bit 5
5
1
BR6
Reset bit 6
6
1
BR7
Reset bit 7
7
1
BR8
Reset bit 8
8
1
BR9
Reset bit 9
9
1
BSRR
BSRR
Port bit set/reset register (GPIOn_BSRR)
0x10
32
write-only
n
0x0
0x0
BR0
Reset bit 0
16
1
BR1
Reset bit 1
17
1
BR10
Reset bit 10
26
1
BR11
Reset bit 11
27
1
BR12
Reset bit 12
28
1
BR13
Reset bit 13
29
1
BR14
Reset bit 14
30
1
BR15
Reset bit 15
31
1
BR2
Reset bit 2
18
1
BR3
Reset bit 3
19
1
BR4
Reset bit 4
20
1
BR5
Reset bit 5
21
1
BR6
Reset bit 6
22
1
BR7
Reset bit 7
23
1
BR8
Reset bit 8
24
1
BR9
Reset bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CRH
CRH
Port configuration register high (GPIOn_CRL)
0x4
32
read-write
n
0x0
0x0
CNF10
Port n.10 configuration bits
10
2
CNF11
Port n.11 configuration bits
14
2
CNF12
Port n.12 configuration bits
18
2
CNF13
Port n.13 configuration bits
22
2
CNF14
Port n.14 configuration bits
26
2
CNF15
Port n.15 configuration bits
30
2
CNF8
Port n.8 configuration bits
2
2
CNF9
Port n.9 configuration bits
6
2
MODE10
Port n.10 mode bits
8
2
MODE11
Port n.11 mode bits
12
2
MODE12
Port n.12 mode bits
16
2
MODE13
Port n.13 mode bits
20
2
MODE14
Port n.14 mode bits
24
2
MODE15
Port n.15 mode bits
28
2
MODE8
Port n.8 mode bits
0
2
MODE9
Port n.9 mode bits
4
2
CRL
CRL
Port configuration register low (GPIOn_CRL)
0x0
32
read-write
n
0x0
0x0
CNF0
Port n.0 configuration bits
2
2
CNF1
Port n.1 configuration bits
6
2
CNF2
Port n.2 configuration bits
10
2
CNF3
Port n.3 configuration bits
14
2
CNF4
Port n.4 configuration bits
18
2
CNF5
Port n.5 configuration bits
22
2
CNF6
Port n.6 configuration bits
26
2
CNF7
Port n.7 configuration bits
30
2
MODE0
Port n.0 mode bits
0
2
MODE1
Port n.1 mode bits
4
2
MODE2
Port n.2 mode bits
8
2
MODE3
Port n.3 mode bits
12
2
MODE4
Port n.4 mode bits
16
2
MODE5
Port n.5 mode bits
20
2
MODE6
Port n.6 mode bits
24
2
MODE7
Port n.7 mode bits
28
2
IDR
IDR
Port input data register (GPIOn_IDR)
0x8
32
read-only
n
0x0
0x0
IDR0
Port input data
0
1
IDR1
Port input data
1
1
IDR10
Port input data
10
1
IDR11
Port input data
11
1
IDR12
Port input data
12
1
IDR13
Port input data
13
1
IDR14
Port input data
14
1
IDR15
Port input data
15
1
IDR2
Port input data
2
1
IDR3
Port input data
3
1
IDR4
Port input data
4
1
IDR5
Port input data
5
1
IDR6
Port input data
6
1
IDR7
Port input data
7
1
IDR8
Port input data
8
1
IDR9
Port input data
9
1
LCKR
LCKR
Port configuration lock register
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
ODR
ODR
Port output data register (GPIOn_ODR)
0xC
32
read-write
n
0x0
0x0
ODR0
Port output data
0
1
ODR1
Port output data
1
1
ODR10
Port output data
10
1
ODR11
Port output data
11
1
ODR12
Port output data
12
1
ODR13
Port output data
13
1
ODR14
Port output data
14
1
ODR15
Port output data
15
1
ODR2
Port output data
2
1
ODR3
Port output data
3
1
ODR4
Port output data
4
1
ODR5
Port output data
5
1
ODR6
Port output data
6
1
ODR7
Port output data
7
1
ODR8
Port output data
8
1
ODR9
Port output data
9
1
GPIOB
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BRR
BRR
Port bit reset register (GPIOn_BRR)
0x14
32
write-only
n
0x0
0x0
BR0
Reset bit 0
0
1
BR1
Reset bit 1
1
1
BR10
Reset bit 10
10
1
BR11
Reset bit 11
11
1
BR12
Reset bit 12
12
1
BR13
Reset bit 13
13
1
BR14
Reset bit 14
14
1
BR15
Reset bit 15
15
1
BR2
Reset bit 1
2
1
BR3
Reset bit 3
3
1
BR4
Reset bit 4
4
1
BR5
Reset bit 5
5
1
BR6
Reset bit 6
6
1
BR7
Reset bit 7
7
1
BR8
Reset bit 8
8
1
BR9
Reset bit 9
9
1
BSRR
BSRR
Port bit set/reset register (GPIOn_BSRR)
0x10
32
write-only
n
0x0
0x0
BR0
Reset bit 0
16
1
BR1
Reset bit 1
17
1
BR10
Reset bit 10
26
1
BR11
Reset bit 11
27
1
BR12
Reset bit 12
28
1
BR13
Reset bit 13
29
1
BR14
Reset bit 14
30
1
BR15
Reset bit 15
31
1
BR2
Reset bit 2
18
1
BR3
Reset bit 3
19
1
BR4
Reset bit 4
20
1
BR5
Reset bit 5
21
1
BR6
Reset bit 6
22
1
BR7
Reset bit 7
23
1
BR8
Reset bit 8
24
1
BR9
Reset bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CRH
CRH
Port configuration register high (GPIOn_CRL)
0x4
32
read-write
n
0x0
0x0
CNF10
Port n.10 configuration bits
10
2
CNF11
Port n.11 configuration bits
14
2
CNF12
Port n.12 configuration bits
18
2
CNF13
Port n.13 configuration bits
22
2
CNF14
Port n.14 configuration bits
26
2
CNF15
Port n.15 configuration bits
30
2
CNF8
Port n.8 configuration bits
2
2
CNF9
Port n.9 configuration bits
6
2
MODE10
Port n.10 mode bits
8
2
MODE11
Port n.11 mode bits
12
2
MODE12
Port n.12 mode bits
16
2
MODE13
Port n.13 mode bits
20
2
MODE14
Port n.14 mode bits
24
2
MODE15
Port n.15 mode bits
28
2
MODE8
Port n.8 mode bits
0
2
MODE9
Port n.9 mode bits
4
2
CRL
CRL
Port configuration register low (GPIOn_CRL)
0x0
32
read-write
n
0x0
0x0
CNF0
Port n.0 configuration bits
2
2
CNF1
Port n.1 configuration bits
6
2
CNF2
Port n.2 configuration bits
10
2
CNF3
Port n.3 configuration bits
14
2
CNF4
Port n.4 configuration bits
18
2
CNF5
Port n.5 configuration bits
22
2
CNF6
Port n.6 configuration bits
26
2
CNF7
Port n.7 configuration bits
30
2
MODE0
Port n.0 mode bits
0
2
MODE1
Port n.1 mode bits
4
2
MODE2
Port n.2 mode bits
8
2
MODE3
Port n.3 mode bits
12
2
MODE4
Port n.4 mode bits
16
2
MODE5
Port n.5 mode bits
20
2
MODE6
Port n.6 mode bits
24
2
MODE7
Port n.7 mode bits
28
2
IDR
IDR
Port input data register (GPIOn_IDR)
0x8
32
read-only
n
0x0
0x0
IDR0
Port input data
0
1
IDR1
Port input data
1
1
IDR10
Port input data
10
1
IDR11
Port input data
11
1
IDR12
Port input data
12
1
IDR13
Port input data
13
1
IDR14
Port input data
14
1
IDR15
Port input data
15
1
IDR2
Port input data
2
1
IDR3
Port input data
3
1
IDR4
Port input data
4
1
IDR5
Port input data
5
1
IDR6
Port input data
6
1
IDR7
Port input data
7
1
IDR8
Port input data
8
1
IDR9
Port input data
9
1
LCKR
LCKR
Port configuration lock register
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
ODR
ODR
Port output data register (GPIOn_ODR)
0xC
32
read-write
n
0x0
0x0
ODR0
Port output data
0
1
ODR1
Port output data
1
1
ODR10
Port output data
10
1
ODR11
Port output data
11
1
ODR12
Port output data
12
1
ODR13
Port output data
13
1
ODR14
Port output data
14
1
ODR15
Port output data
15
1
ODR2
Port output data
2
1
ODR3
Port output data
3
1
ODR4
Port output data
4
1
ODR5
Port output data
5
1
ODR6
Port output data
6
1
ODR7
Port output data
7
1
ODR8
Port output data
8
1
ODR9
Port output data
9
1
GPIOC
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BRR
BRR
Port bit reset register (GPIOn_BRR)
0x14
32
write-only
n
0x0
0x0
BR0
Reset bit 0
0
1
BR1
Reset bit 1
1
1
BR10
Reset bit 10
10
1
BR11
Reset bit 11
11
1
BR12
Reset bit 12
12
1
BR13
Reset bit 13
13
1
BR14
Reset bit 14
14
1
BR15
Reset bit 15
15
1
BR2
Reset bit 1
2
1
BR3
Reset bit 3
3
1
BR4
Reset bit 4
4
1
BR5
Reset bit 5
5
1
BR6
Reset bit 6
6
1
BR7
Reset bit 7
7
1
BR8
Reset bit 8
8
1
BR9
Reset bit 9
9
1
BSRR
BSRR
Port bit set/reset register (GPIOn_BSRR)
0x10
32
write-only
n
0x0
0x0
BR0
Reset bit 0
16
1
BR1
Reset bit 1
17
1
BR10
Reset bit 10
26
1
BR11
Reset bit 11
27
1
BR12
Reset bit 12
28
1
BR13
Reset bit 13
29
1
BR14
Reset bit 14
30
1
BR15
Reset bit 15
31
1
BR2
Reset bit 2
18
1
BR3
Reset bit 3
19
1
BR4
Reset bit 4
20
1
BR5
Reset bit 5
21
1
BR6
Reset bit 6
22
1
BR7
Reset bit 7
23
1
BR8
Reset bit 8
24
1
BR9
Reset bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CRH
CRH
Port configuration register high (GPIOn_CRL)
0x4
32
read-write
n
0x0
0x0
CNF10
Port n.10 configuration bits
10
2
CNF11
Port n.11 configuration bits
14
2
CNF12
Port n.12 configuration bits
18
2
CNF13
Port n.13 configuration bits
22
2
CNF14
Port n.14 configuration bits
26
2
CNF15
Port n.15 configuration bits
30
2
CNF8
Port n.8 configuration bits
2
2
CNF9
Port n.9 configuration bits
6
2
MODE10
Port n.10 mode bits
8
2
MODE11
Port n.11 mode bits
12
2
MODE12
Port n.12 mode bits
16
2
MODE13
Port n.13 mode bits
20
2
MODE14
Port n.14 mode bits
24
2
MODE15
Port n.15 mode bits
28
2
MODE8
Port n.8 mode bits
0
2
MODE9
Port n.9 mode bits
4
2
CRL
CRL
Port configuration register low (GPIOn_CRL)
0x0
32
read-write
n
0x0
0x0
CNF0
Port n.0 configuration bits
2
2
CNF1
Port n.1 configuration bits
6
2
CNF2
Port n.2 configuration bits
10
2
CNF3
Port n.3 configuration bits
14
2
CNF4
Port n.4 configuration bits
18
2
CNF5
Port n.5 configuration bits
22
2
CNF6
Port n.6 configuration bits
26
2
CNF7
Port n.7 configuration bits
30
2
MODE0
Port n.0 mode bits
0
2
MODE1
Port n.1 mode bits
4
2
MODE2
Port n.2 mode bits
8
2
MODE3
Port n.3 mode bits
12
2
MODE4
Port n.4 mode bits
16
2
MODE5
Port n.5 mode bits
20
2
MODE6
Port n.6 mode bits
24
2
MODE7
Port n.7 mode bits
28
2
IDR
IDR
Port input data register (GPIOn_IDR)
0x8
32
read-only
n
0x0
0x0
IDR0
Port input data
0
1
IDR1
Port input data
1
1
IDR10
Port input data
10
1
IDR11
Port input data
11
1
IDR12
Port input data
12
1
IDR13
Port input data
13
1
IDR14
Port input data
14
1
IDR15
Port input data
15
1
IDR2
Port input data
2
1
IDR3
Port input data
3
1
IDR4
Port input data
4
1
IDR5
Port input data
5
1
IDR6
Port input data
6
1
IDR7
Port input data
7
1
IDR8
Port input data
8
1
IDR9
Port input data
9
1
LCKR
LCKR
Port configuration lock register
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
ODR
ODR
Port output data register (GPIOn_ODR)
0xC
32
read-write
n
0x0
0x0
ODR0
Port output data
0
1
ODR1
Port output data
1
1
ODR10
Port output data
10
1
ODR11
Port output data
11
1
ODR12
Port output data
12
1
ODR13
Port output data
13
1
ODR14
Port output data
14
1
ODR15
Port output data
15
1
ODR2
Port output data
2
1
ODR3
Port output data
3
1
ODR4
Port output data
4
1
ODR5
Port output data
5
1
ODR6
Port output data
6
1
ODR7
Port output data
7
1
ODR8
Port output data
8
1
ODR9
Port output data
9
1
GPIOD
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BRR
BRR
Port bit reset register (GPIOn_BRR)
0x14
32
write-only
n
0x0
0x0
BR0
Reset bit 0
0
1
BR1
Reset bit 1
1
1
BR10
Reset bit 10
10
1
BR11
Reset bit 11
11
1
BR12
Reset bit 12
12
1
BR13
Reset bit 13
13
1
BR14
Reset bit 14
14
1
BR15
Reset bit 15
15
1
BR2
Reset bit 1
2
1
BR3
Reset bit 3
3
1
BR4
Reset bit 4
4
1
BR5
Reset bit 5
5
1
BR6
Reset bit 6
6
1
BR7
Reset bit 7
7
1
BR8
Reset bit 8
8
1
BR9
Reset bit 9
9
1
BSRR
BSRR
Port bit set/reset register (GPIOn_BSRR)
0x10
32
write-only
n
0x0
0x0
BR0
Reset bit 0
16
1
BR1
Reset bit 1
17
1
BR10
Reset bit 10
26
1
BR11
Reset bit 11
27
1
BR12
Reset bit 12
28
1
BR13
Reset bit 13
29
1
BR14
Reset bit 14
30
1
BR15
Reset bit 15
31
1
BR2
Reset bit 2
18
1
BR3
Reset bit 3
19
1
BR4
Reset bit 4
20
1
BR5
Reset bit 5
21
1
BR6
Reset bit 6
22
1
BR7
Reset bit 7
23
1
BR8
Reset bit 8
24
1
BR9
Reset bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CRH
CRH
Port configuration register high (GPIOn_CRL)
0x4
32
read-write
n
0x0
0x0
CNF10
Port n.10 configuration bits
10
2
CNF11
Port n.11 configuration bits
14
2
CNF12
Port n.12 configuration bits
18
2
CNF13
Port n.13 configuration bits
22
2
CNF14
Port n.14 configuration bits
26
2
CNF15
Port n.15 configuration bits
30
2
CNF8
Port n.8 configuration bits
2
2
CNF9
Port n.9 configuration bits
6
2
MODE10
Port n.10 mode bits
8
2
MODE11
Port n.11 mode bits
12
2
MODE12
Port n.12 mode bits
16
2
MODE13
Port n.13 mode bits
20
2
MODE14
Port n.14 mode bits
24
2
MODE15
Port n.15 mode bits
28
2
MODE8
Port n.8 mode bits
0
2
MODE9
Port n.9 mode bits
4
2
CRL
CRL
Port configuration register low (GPIOn_CRL)
0x0
32
read-write
n
0x0
0x0
CNF0
Port n.0 configuration bits
2
2
CNF1
Port n.1 configuration bits
6
2
CNF2
Port n.2 configuration bits
10
2
CNF3
Port n.3 configuration bits
14
2
CNF4
Port n.4 configuration bits
18
2
CNF5
Port n.5 configuration bits
22
2
CNF6
Port n.6 configuration bits
26
2
CNF7
Port n.7 configuration bits
30
2
MODE0
Port n.0 mode bits
0
2
MODE1
Port n.1 mode bits
4
2
MODE2
Port n.2 mode bits
8
2
MODE3
Port n.3 mode bits
12
2
MODE4
Port n.4 mode bits
16
2
MODE5
Port n.5 mode bits
20
2
MODE6
Port n.6 mode bits
24
2
MODE7
Port n.7 mode bits
28
2
IDR
IDR
Port input data register (GPIOn_IDR)
0x8
32
read-only
n
0x0
0x0
IDR0
Port input data
0
1
IDR1
Port input data
1
1
IDR10
Port input data
10
1
IDR11
Port input data
11
1
IDR12
Port input data
12
1
IDR13
Port input data
13
1
IDR14
Port input data
14
1
IDR15
Port input data
15
1
IDR2
Port input data
2
1
IDR3
Port input data
3
1
IDR4
Port input data
4
1
IDR5
Port input data
5
1
IDR6
Port input data
6
1
IDR7
Port input data
7
1
IDR8
Port input data
8
1
IDR9
Port input data
9
1
LCKR
LCKR
Port configuration lock register
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
ODR
ODR
Port output data register (GPIOn_ODR)
0xC
32
read-write
n
0x0
0x0
ODR0
Port output data
0
1
ODR1
Port output data
1
1
ODR10
Port output data
10
1
ODR11
Port output data
11
1
ODR12
Port output data
12
1
ODR13
Port output data
13
1
ODR14
Port output data
14
1
ODR15
Port output data
15
1
ODR2
Port output data
2
1
ODR3
Port output data
3
1
ODR4
Port output data
4
1
ODR5
Port output data
5
1
ODR6
Port output data
6
1
ODR7
Port output data
7
1
ODR8
Port output data
8
1
ODR9
Port output data
9
1
GPIOE
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BRR
BRR
Port bit reset register (GPIOn_BRR)
0x14
32
write-only
n
0x0
0x0
BR0
Reset bit 0
0
1
BR1
Reset bit 1
1
1
BR10
Reset bit 10
10
1
BR11
Reset bit 11
11
1
BR12
Reset bit 12
12
1
BR13
Reset bit 13
13
1
BR14
Reset bit 14
14
1
BR15
Reset bit 15
15
1
BR2
Reset bit 1
2
1
BR3
Reset bit 3
3
1
BR4
Reset bit 4
4
1
BR5
Reset bit 5
5
1
BR6
Reset bit 6
6
1
BR7
Reset bit 7
7
1
BR8
Reset bit 8
8
1
BR9
Reset bit 9
9
1
BSRR
BSRR
Port bit set/reset register (GPIOn_BSRR)
0x10
32
write-only
n
0x0
0x0
BR0
Reset bit 0
16
1
BR1
Reset bit 1
17
1
BR10
Reset bit 10
26
1
BR11
Reset bit 11
27
1
BR12
Reset bit 12
28
1
BR13
Reset bit 13
29
1
BR14
Reset bit 14
30
1
BR15
Reset bit 15
31
1
BR2
Reset bit 2
18
1
BR3
Reset bit 3
19
1
BR4
Reset bit 4
20
1
BR5
Reset bit 5
21
1
BR6
Reset bit 6
22
1
BR7
Reset bit 7
23
1
BR8
Reset bit 8
24
1
BR9
Reset bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CRH
CRH
Port configuration register high (GPIOn_CRL)
0x4
32
read-write
n
0x0
0x0
CNF10
Port n.10 configuration bits
10
2
CNF11
Port n.11 configuration bits
14
2
CNF12
Port n.12 configuration bits
18
2
CNF13
Port n.13 configuration bits
22
2
CNF14
Port n.14 configuration bits
26
2
CNF15
Port n.15 configuration bits
30
2
CNF8
Port n.8 configuration bits
2
2
CNF9
Port n.9 configuration bits
6
2
MODE10
Port n.10 mode bits
8
2
MODE11
Port n.11 mode bits
12
2
MODE12
Port n.12 mode bits
16
2
MODE13
Port n.13 mode bits
20
2
MODE14
Port n.14 mode bits
24
2
MODE15
Port n.15 mode bits
28
2
MODE8
Port n.8 mode bits
0
2
MODE9
Port n.9 mode bits
4
2
CRL
CRL
Port configuration register low (GPIOn_CRL)
0x0
32
read-write
n
0x0
0x0
CNF0
Port n.0 configuration bits
2
2
CNF1
Port n.1 configuration bits
6
2
CNF2
Port n.2 configuration bits
10
2
CNF3
Port n.3 configuration bits
14
2
CNF4
Port n.4 configuration bits
18
2
CNF5
Port n.5 configuration bits
22
2
CNF6
Port n.6 configuration bits
26
2
CNF7
Port n.7 configuration bits
30
2
MODE0
Port n.0 mode bits
0
2
MODE1
Port n.1 mode bits
4
2
MODE2
Port n.2 mode bits
8
2
MODE3
Port n.3 mode bits
12
2
MODE4
Port n.4 mode bits
16
2
MODE5
Port n.5 mode bits
20
2
MODE6
Port n.6 mode bits
24
2
MODE7
Port n.7 mode bits
28
2
IDR
IDR
Port input data register (GPIOn_IDR)
0x8
32
read-only
n
0x0
0x0
IDR0
Port input data
0
1
IDR1
Port input data
1
1
IDR10
Port input data
10
1
IDR11
Port input data
11
1
IDR12
Port input data
12
1
IDR13
Port input data
13
1
IDR14
Port input data
14
1
IDR15
Port input data
15
1
IDR2
Port input data
2
1
IDR3
Port input data
3
1
IDR4
Port input data
4
1
IDR5
Port input data
5
1
IDR6
Port input data
6
1
IDR7
Port input data
7
1
IDR8
Port input data
8
1
IDR9
Port input data
9
1
LCKR
LCKR
Port configuration lock register
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
ODR
ODR
Port output data register (GPIOn_ODR)
0xC
32
read-write
n
0x0
0x0
ODR0
Port output data
0
1
ODR1
Port output data
1
1
ODR10
Port output data
10
1
ODR11
Port output data
11
1
ODR12
Port output data
12
1
ODR13
Port output data
13
1
ODR14
Port output data
14
1
ODR15
Port output data
15
1
ODR2
Port output data
2
1
ODR3
Port output data
3
1
ODR4
Port output data
4
1
ODR5
Port output data
5
1
ODR6
Port output data
6
1
ODR7
Port output data
7
1
ODR8
Port output data
8
1
ODR9
Port output data
9
1
GPIOF
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BRR
BRR
Port bit reset register (GPIOn_BRR)
0x14
32
write-only
n
0x0
0x0
BR0
Reset bit 0
0
1
BR1
Reset bit 1
1
1
BR10
Reset bit 10
10
1
BR11
Reset bit 11
11
1
BR12
Reset bit 12
12
1
BR13
Reset bit 13
13
1
BR14
Reset bit 14
14
1
BR15
Reset bit 15
15
1
BR2
Reset bit 1
2
1
BR3
Reset bit 3
3
1
BR4
Reset bit 4
4
1
BR5
Reset bit 5
5
1
BR6
Reset bit 6
6
1
BR7
Reset bit 7
7
1
BR8
Reset bit 8
8
1
BR9
Reset bit 9
9
1
BSRR
BSRR
Port bit set/reset register (GPIOn_BSRR)
0x10
32
write-only
n
0x0
0x0
BR0
Reset bit 0
16
1
BR1
Reset bit 1
17
1
BR10
Reset bit 10
26
1
BR11
Reset bit 11
27
1
BR12
Reset bit 12
28
1
BR13
Reset bit 13
29
1
BR14
Reset bit 14
30
1
BR15
Reset bit 15
31
1
BR2
Reset bit 2
18
1
BR3
Reset bit 3
19
1
BR4
Reset bit 4
20
1
BR5
Reset bit 5
21
1
BR6
Reset bit 6
22
1
BR7
Reset bit 7
23
1
BR8
Reset bit 8
24
1
BR9
Reset bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CRH
CRH
Port configuration register high (GPIOn_CRL)
0x4
32
read-write
n
0x0
0x0
CNF10
Port n.10 configuration bits
10
2
CNF11
Port n.11 configuration bits
14
2
CNF12
Port n.12 configuration bits
18
2
CNF13
Port n.13 configuration bits
22
2
CNF14
Port n.14 configuration bits
26
2
CNF15
Port n.15 configuration bits
30
2
CNF8
Port n.8 configuration bits
2
2
CNF9
Port n.9 configuration bits
6
2
MODE10
Port n.10 mode bits
8
2
MODE11
Port n.11 mode bits
12
2
MODE12
Port n.12 mode bits
16
2
MODE13
Port n.13 mode bits
20
2
MODE14
Port n.14 mode bits
24
2
MODE15
Port n.15 mode bits
28
2
MODE8
Port n.8 mode bits
0
2
MODE9
Port n.9 mode bits
4
2
CRL
CRL
Port configuration register low (GPIOn_CRL)
0x0
32
read-write
n
0x0
0x0
CNF0
Port n.0 configuration bits
2
2
CNF1
Port n.1 configuration bits
6
2
CNF2
Port n.2 configuration bits
10
2
CNF3
Port n.3 configuration bits
14
2
CNF4
Port n.4 configuration bits
18
2
CNF5
Port n.5 configuration bits
22
2
CNF6
Port n.6 configuration bits
26
2
CNF7
Port n.7 configuration bits
30
2
MODE0
Port n.0 mode bits
0
2
MODE1
Port n.1 mode bits
4
2
MODE2
Port n.2 mode bits
8
2
MODE3
Port n.3 mode bits
12
2
MODE4
Port n.4 mode bits
16
2
MODE5
Port n.5 mode bits
20
2
MODE6
Port n.6 mode bits
24
2
MODE7
Port n.7 mode bits
28
2
IDR
IDR
Port input data register (GPIOn_IDR)
0x8
32
read-only
n
0x0
0x0
IDR0
Port input data
0
1
IDR1
Port input data
1
1
IDR10
Port input data
10
1
IDR11
Port input data
11
1
IDR12
Port input data
12
1
IDR13
Port input data
13
1
IDR14
Port input data
14
1
IDR15
Port input data
15
1
IDR2
Port input data
2
1
IDR3
Port input data
3
1
IDR4
Port input data
4
1
IDR5
Port input data
5
1
IDR6
Port input data
6
1
IDR7
Port input data
7
1
IDR8
Port input data
8
1
IDR9
Port input data
9
1
LCKR
LCKR
Port configuration lock register
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
ODR
ODR
Port output data register (GPIOn_ODR)
0xC
32
read-write
n
0x0
0x0
ODR0
Port output data
0
1
ODR1
Port output data
1
1
ODR10
Port output data
10
1
ODR11
Port output data
11
1
ODR12
Port output data
12
1
ODR13
Port output data
13
1
ODR14
Port output data
14
1
ODR15
Port output data
15
1
ODR2
Port output data
2
1
ODR3
Port output data
3
1
ODR4
Port output data
4
1
ODR5
Port output data
5
1
ODR6
Port output data
6
1
ODR7
Port output data
7
1
ODR8
Port output data
8
1
ODR9
Port output data
9
1
GPIOG
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BRR
BRR
Port bit reset register (GPIOn_BRR)
0x14
32
write-only
n
0x0
0x0
BR0
Reset bit 0
0
1
BR1
Reset bit 1
1
1
BR10
Reset bit 10
10
1
BR11
Reset bit 11
11
1
BR12
Reset bit 12
12
1
BR13
Reset bit 13
13
1
BR14
Reset bit 14
14
1
BR15
Reset bit 15
15
1
BR2
Reset bit 1
2
1
BR3
Reset bit 3
3
1
BR4
Reset bit 4
4
1
BR5
Reset bit 5
5
1
BR6
Reset bit 6
6
1
BR7
Reset bit 7
7
1
BR8
Reset bit 8
8
1
BR9
Reset bit 9
9
1
BSRR
BSRR
Port bit set/reset register (GPIOn_BSRR)
0x10
32
write-only
n
0x0
0x0
BR0
Reset bit 0
16
1
BR1
Reset bit 1
17
1
BR10
Reset bit 10
26
1
BR11
Reset bit 11
27
1
BR12
Reset bit 12
28
1
BR13
Reset bit 13
29
1
BR14
Reset bit 14
30
1
BR15
Reset bit 15
31
1
BR2
Reset bit 2
18
1
BR3
Reset bit 3
19
1
BR4
Reset bit 4
20
1
BR5
Reset bit 5
21
1
BR6
Reset bit 6
22
1
BR7
Reset bit 7
23
1
BR8
Reset bit 8
24
1
BR9
Reset bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CRH
CRH
Port configuration register high (GPIOn_CRL)
0x4
32
read-write
n
0x0
0x0
CNF10
Port n.10 configuration bits
10
2
CNF11
Port n.11 configuration bits
14
2
CNF12
Port n.12 configuration bits
18
2
CNF13
Port n.13 configuration bits
22
2
CNF14
Port n.14 configuration bits
26
2
CNF15
Port n.15 configuration bits
30
2
CNF8
Port n.8 configuration bits
2
2
CNF9
Port n.9 configuration bits
6
2
MODE10
Port n.10 mode bits
8
2
MODE11
Port n.11 mode bits
12
2
MODE12
Port n.12 mode bits
16
2
MODE13
Port n.13 mode bits
20
2
MODE14
Port n.14 mode bits
24
2
MODE15
Port n.15 mode bits
28
2
MODE8
Port n.8 mode bits
0
2
MODE9
Port n.9 mode bits
4
2
CRL
CRL
Port configuration register low (GPIOn_CRL)
0x0
32
read-write
n
0x0
0x0
CNF0
Port n.0 configuration bits
2
2
CNF1
Port n.1 configuration bits
6
2
CNF2
Port n.2 configuration bits
10
2
CNF3
Port n.3 configuration bits
14
2
CNF4
Port n.4 configuration bits
18
2
CNF5
Port n.5 configuration bits
22
2
CNF6
Port n.6 configuration bits
26
2
CNF7
Port n.7 configuration bits
30
2
MODE0
Port n.0 mode bits
0
2
MODE1
Port n.1 mode bits
4
2
MODE2
Port n.2 mode bits
8
2
MODE3
Port n.3 mode bits
12
2
MODE4
Port n.4 mode bits
16
2
MODE5
Port n.5 mode bits
20
2
MODE6
Port n.6 mode bits
24
2
MODE7
Port n.7 mode bits
28
2
IDR
IDR
Port input data register (GPIOn_IDR)
0x8
32
read-only
n
0x0
0x0
IDR0
Port input data
0
1
IDR1
Port input data
1
1
IDR10
Port input data
10
1
IDR11
Port input data
11
1
IDR12
Port input data
12
1
IDR13
Port input data
13
1
IDR14
Port input data
14
1
IDR15
Port input data
15
1
IDR2
Port input data
2
1
IDR3
Port input data
3
1
IDR4
Port input data
4
1
IDR5
Port input data
5
1
IDR6
Port input data
6
1
IDR7
Port input data
7
1
IDR8
Port input data
8
1
IDR9
Port input data
9
1
LCKR
LCKR
Port configuration lock register
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
ODR
ODR
Port output data register (GPIOn_ODR)
0xC
32
read-write
n
0x0
0x0
ODR0
Port output data
0
1
ODR1
Port output data
1
1
ODR10
Port output data
10
1
ODR11
Port output data
11
1
ODR12
Port output data
12
1
ODR13
Port output data
13
1
ODR14
Port output data
14
1
ODR15
Port output data
15
1
ODR2
Port output data
2
1
ODR3
Port output data
3
1
ODR4
Port output data
4
1
ODR5
Port output data
5
1
ODR6
Port output data
6
1
ODR7
Port output data
7
1
ODR8
Port output data
8
1
ODR9
Port output data
9
1
I2C1
Inter integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1_EV
I2C1 event interrupt
31
I2C1_EV_IRQ
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
I2C1_ER_IRQ
I2C1 error interrupt
32
CCR
CCR
Clock control register
0x1C
32
read-write
n
0x0
0x0
CCR
Clock control register in Fast/Standard mode (Master mode)
0
12
DUTY
Fast mode duty cycle
14
1
F_S
I2C master mode selection
15
1
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACK
Acknowledge enable
10
1
ALERT
SMBus alert
13
1
ENARP
ARP enable
4
1
ENGC
General call enable
6
1
ENPEC
PEC enable
5
1
NOSTRETCH
Clock stretching disable (Slave mode)
7
1
PE
Peripheral enable
0
1
PEC
Packet error checking
12
1
POS
Acknowledge/PEC Position (for data reception)
11
1
SMBTYPE
SMBus type
3
1
SMBUS
SMBus mode
1
1
START
Start generation
8
1
STOP
Stop generation
9
1
SWRST
Software reset
15
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
DMAEN
DMA requests enable
11
1
FREQ
Peripheral clock frequency
0
6
ITBUFEN
Buffer interrupt enable
10
1
ITERREN
Error interrupt enable
8
1
ITEVTEN
Event interrupt enable
9
1
LAST
DMA last transfer
12
1
DR
DR
Data register
0x10
32
read-write
n
0x0
0x0
DR
8-bit data register
0
8
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD10
Interface address
8
2
ADD7
Interface address
1
7
ADDMODE
Addressing mode (slave mode)
15
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
ENDUAL
Dual addressing mode enable
0
1
SR1
SR1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADD10
10-bit header sent (Master mode)
3
1
read-only
ADDR
Address sent (master mode)/matched (slave mode)
1
1
read-only
AF
Acknowledge failure
10
1
read-write
ARLO
Arbitration lost (master mode)
9
1
read-write
BERR
Bus error
8
1
read-write
BTF
Byte transfer finished
2
1
read-only
OVR
Overrun/Underrun
11
1
read-write
PECERR
PEC Error in reception
12
1
read-write
RxNE
Data register not empty (receivers)
6
1
read-only
SB
Start bit (Master mode)
0
1
read-only
SMBALERT
SMBus alert
15
1
read-write
STOPF
Stop detection (slave mode)
4
1
read-only
TIMEOUT
Timeout or Tlow error
14
1
read-write
TxE
Data register empty (transmitters)
7
1
read-only
SR2
SR2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSY
Bus busy
1
1
DUALF
Dual flag (Slave mode)
7
1
GENCALL
General call address (Slave mode)
4
1
MSL
Master/slave
0
1
PEC
acket error checking register
8
8
SMBDEFAULT
SMBus device default address (Slave mode)
5
1
SMBHOST
SMBus host header (Slave mode)
6
1
TRA
Transmitter/receiver
2
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
I2C2
Inter integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C2_EV
I2C2 event interrupt
33
I2C2_EV_IRQ
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
I2C2_ER_IRQ
I2C2 error interrupt
34
CCR
CCR
Clock control register
0x1C
32
read-write
n
0x0
0x0
CCR
Clock control register in Fast/Standard mode (Master mode)
0
12
DUTY
Fast mode duty cycle
14
1
F_S
I2C master mode selection
15
1
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACK
Acknowledge enable
10
1
ALERT
SMBus alert
13
1
ENARP
ARP enable
4
1
ENGC
General call enable
6
1
ENPEC
PEC enable
5
1
NOSTRETCH
Clock stretching disable (Slave mode)
7
1
PE
Peripheral enable
0
1
PEC
Packet error checking
12
1
POS
Acknowledge/PEC Position (for data reception)
11
1
SMBTYPE
SMBus type
3
1
SMBUS
SMBus mode
1
1
START
Start generation
8
1
STOP
Stop generation
9
1
SWRST
Software reset
15
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
DMAEN
DMA requests enable
11
1
FREQ
Peripheral clock frequency
0
6
ITBUFEN
Buffer interrupt enable
10
1
ITERREN
Error interrupt enable
8
1
ITEVTEN
Event interrupt enable
9
1
LAST
DMA last transfer
12
1
DR
DR
Data register
0x10
32
read-write
n
0x0
0x0
DR
8-bit data register
0
8
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD10
Interface address
8
2
ADD7
Interface address
1
7
ADDMODE
Addressing mode (slave mode)
15
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
ENDUAL
Dual addressing mode enable
0
1
SR1
SR1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADD10
10-bit header sent (Master mode)
3
1
read-only
ADDR
Address sent (master mode)/matched (slave mode)
1
1
read-only
AF
Acknowledge failure
10
1
read-write
ARLO
Arbitration lost (master mode)
9
1
read-write
BERR
Bus error
8
1
read-write
BTF
Byte transfer finished
2
1
read-only
OVR
Overrun/Underrun
11
1
read-write
PECERR
PEC Error in reception
12
1
read-write
RxNE
Data register not empty (receivers)
6
1
read-only
SB
Start bit (Master mode)
0
1
read-only
SMBALERT
SMBus alert
15
1
read-write
STOPF
Stop detection (slave mode)
4
1
read-only
TIMEOUT
Timeout or Tlow error
14
1
read-write
TxE
Data register empty (transmitters)
7
1
read-only
SR2
SR2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSY
Bus busy
1
1
DUALF
Dual flag (Slave mode)
7
1
GENCALL
General call address (Slave mode)
4
1
MSL
Master/slave
0
1
PEC
acket error checking register
8
8
SMBDEFAULT
SMBus device default address (Slave mode)
5
1
SMBHOST
SMBus host header (Slave mode)
6
1
TRA
Transmitter/receiver
2
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
IWDG
Independent watchdog
IWDG
0x0
0x0
0x400
registers
n
KR
KR
Key register (IWDG_KR)
0x0
32
write-only
n
0x0
0x0
KEY
Key value
0
16
PR
PR
Prescaler register (IWDG_PR)
0x4
32
read-write
n
0x0
0x0
PR
Prescaler divider
0
3
RLR
RLR
Reload register (IWDG_RLR)
0x8
32
read-write
n
0x0
0x0
RL
Watchdog counter reload value
0
12
SR
SR
Status register (IWDG_SR)
0xC
32
read-only
n
0x0
0x0
PVU
Watchdog prescaler value update
0
1
RVU
Watchdog counter reload value update
1
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x1001
registers
n
0x1001
0xFFFFF3FF
reserved
n
IABR0
IABR0
Interrupt Active Bit Register
0x300
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x304
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
ICER0
ICER0
Interrupt Clear-Enable Register
0x180
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable Register
0x184
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR0
ICPR0
Interrupt Clear-Pending Register
0x280
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending Register
0x284
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICTR
ICTR
Interrupt Controller Type Register
0x4
32
read-only
n
0x0
0x0
INTLINESNUM
Total number of interrupt lines in groups
0
4
IPR0
IPR0
Interrupt Priority Register
0x400
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x404
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x428
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x42C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x430
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x434
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x438
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x408
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x40C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x410
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x414
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x418
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x41C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x420
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x424
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
ISER0
ISER0
Interrupt Set-Enable Register
0x100
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x104
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x200
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x204
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
STIR
STIR
Software Triggered Interrupt Register
0xF00
32
write-only
n
0x0
0x0
INTID
interrupt to be triggered
0
9
PWR
Power control
PWR
0x0
0x0
0x400
registers
n
PVD
PVD through EXTI Line detection interrupt
1
PVD_IRQ
PVD through EXTI line detection
interrupt
1
CR
CR
Power control register (PWR_CR)
0x0
32
read-write
n
0x0
0x0
CSBF
Clear STANDBY Flag
3
1
CWUF
Clear Wake-up Flag
2
1
DBP
Disable Backup Domain write protection
8
1
LPDS
Low Power Deep Sleep
0
1
PDDS
Power Down Deep Sleep
1
1
PLS
PVD Level Selection
5
3
PVDE
Power Voltage Detector Enable
4
1
CSR
CSR
Power control register (PWR_CR)
0x4
32
read-write
n
0x0
0x0
EWUP
Enable WKUP pin
8
1
read-write
PVDO
PVD Output
2
1
read-only
SBF
STANDBY Flag
1
1
read-only
WUF
Wake-Up Flag
0
1
read-only
RCC
Reset and clock control
RCC
0x0
0x0
0x400
registers
n
RCC
RCC global interrupt
5
RCC_IRQ
RCC global interrupt
5
AHBENR
AHBENR
AHB Peripheral Clock enable register (RCC_AHBENR)
0x14
32
read-write
n
0x0
0x0
CRCEN
CRC clock enable
6
1
DMA1EN
DMA1 clock enable
0
1
DMA2EN
DMA2 clock enable
1
1
FLITFEN
FLITF clock enable
4
1
FSMCEN
FSMC clock enable
8
1
SRAMEN
SRAM interface clock enable
2
1
APB1ENR
APB1ENR
APB1 peripheral clock enable register (RCC_APB1ENR)
0x1C
32
read-write
n
0x0
0x0
BKPEN
Backup interface clock enable
27
1
CECEN
CEC clock enable
30
1
DACEN
DAC interface clock enable
29
1
I2C1EN
I2C 1 clock enable
21
1
I2C2EN
I2C 2 clock enable
22
1
PWREN
Power interface clock enable
28
1
SPI2EN
SPI 2 clock enable
14
1
SPI3EN
SPI 3 clock enable
15
1
TIM12EN
Timer 12 clock enable
6
1
TIM13EN
Timer 13 clock enable
7
1
TIM14EN
Timer 14 clock enable
8
1
TIM2EN
Timer 2 clock enable
0
1
TIM3EN
Timer 3 clock enable
1
1
TIM4EN
Timer 4 clock enable
2
1
TIM5EN
Timer 5 clock enable
3
1
TIM6EN
Timer 6 clock enable
4
1
TIM7EN
Timer 7 clock enable
5
1
UART4EN
UART 4 clock enable
19
1
UART5EN
UART 5 clock enable
20
1
USART2EN
USART 2 clock enable
17
1
USART3EN
USART 3 clock enable
18
1
WWDGEN
Window watchdog clock enable
11
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register (RCC_APB1RSTR)
0x10
32
read-write
n
0x0
0x0
BKPRST
Backup interface reset
27
1
CECRST
CEC reset
30
1
DACRST
DAC interface reset
29
1
I2C1RST
I2C1 reset
21
1
I2C2RST
I2C2 reset
22
1
PWRRST
Power interface reset
28
1
SPI2RST
SPI2 reset
14
1
SPI3RST
SPI3 reset
15
1
TIM12RST
Timer 12 reset
6
1
TIM13RST
Timer 13 reset
7
1
TIM14RST
Timer 14 reset
8
1
TIM2RST
Timer 2 reset
0
1
TIM3RST
Timer 3 reset
1
1
TIM4RST
Timer 4 reset
2
1
TIM5RST
Timer 5 reset
3
1
TIM6RST
Timer 6 reset
4
1
TIM7RST
Timer 7 reset
5
1
USART2RST
USART 2 reset
17
1
USART3RST
USART 3 reset
18
1
USART4RST
USART 4 reset
19
1
USART5RST
USART 5 reset
20
1
WWDGRST
Window watchdog reset
11
1
APB2ENR
APB2ENR
APB2 peripheral clock enable register (RCC_APB2ENR)
0x18
32
read-write
n
0x0
0x0
ADC1EN
ADC 1 interface clock enable
9
1
AFIOEN
Alternate function I/O clock enable
0
1
IOPAEN
I/O port A clock enable
2
1
IOPBEN
I/O port B clock enable
3
1
IOPCEN
I/O port C clock enable
4
1
IOPDEN
I/O port D clock enable
5
1
IOPEEN
I/O port E clock enable
6
1
IOPFEN
I/O port F clock enable
7
1
IOPGEN
I/O port G clock enable
8
1
SPI1EN
SPI 1 clock enable
12
1
TIM15EN
TIM15 Timer clock enable
16
1
TIM16EN
TIM16 Timer clock enable
17
1
TIM17EN
TIM17 Timer clock enable
18
1
TIM1EN
TIM1 Timer clock enable
11
1
USART1EN
USART1 clock enable
14
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register (RCC_APB2RSTR)
0xC
32
read-write
n
0x0
0x0
ADC1RST
ADC 1 interface reset
9
1
AFIORST
Alternate function I/O reset
0
1
IOPARST
IO port A reset
2
1
IOPBRST
IO port B reset
3
1
IOPCRST
IO port C reset
4
1
IOPDRST
IO port D reset
5
1
IOPERST
IO port E reset
6
1
IOPFRST
IO port F reset
7
1
IOPGRST
IO port G reset
8
1
SPI1RST
SPI 1 reset
12
1
TIM15RST
TIM15 timer reset
16
1
TIM16RST
TIM16 timer reset
17
1
TIM17RST
TIM17 timer reset
18
1
TIM1RST
TIM1 timer reset
11
1
USART1RST
USART1 reset
14
1
BDCR
BDCR
Backup domain control register (RCC_BDCR)
0x20
32
read-write
n
0x0
0x0
BDRST
Backup domain software reset
16
1
read-write
LSEBYP
External Low Speed oscillator bypass
2
1
read-write
LSEON
External Low Speed oscillator enable
0
1
read-write
LSERDY
External Low Speed oscillator ready
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSEL
RTC clock source selection
8
2
read-write
CFGR
CFGR
Clock configuration register (RCC_CFGR)
0x4
32
read-write
n
0x0
0x0
ADCPRE
ADC prescaler
14
2
read-write
HPRE
AHB prescaler
4
4
read-write
MCO
Microcontroller clock output
24
3
read-write
PLLMUL
PLL Multiplication Factor
18
4
read-write
PLLSRC
PLL entry clock source
16
1
read-write
PLLXTPRE
HSE divider for PLL entry
17
1
read-write
PPRE1
APB Low speed prescaler (APB1)
8
3
read-write
PPRE2
APB High speed prescaler (APB2)
11
3
read-write
SW
System clock Switch
0
2
read-write
SWS
System Clock Switch Status
2
2
read-only
CFGR2
CFGR2
Clock configuration register 2
0x2C
32
read-write
n
0x0
0x0
PREDIV1
PREDIV1 division factor
0
4
CIR
CIR
Clock interrupt register (RCC_CIR)
0x8
32
read-write
n
0x0
0x0
CSSC
Clock security system interrupt clear
23
1
write-only
CSSF
Clock Security System Interrupt flag
7
1
read-only
HSERDYC
HSE Ready Interrupt Clear
19
1
write-only
HSERDYF
HSE Ready Interrupt flag
3
1
read-only
HSERDYIE
HSE Ready Interrupt Enable
11
1
read-write
HSIRDYC
HSI Ready Interrupt Clear
18
1
write-only
HSIRDYF
HSI Ready Interrupt flag
2
1
read-only
HSIRDYIE
HSI Ready Interrupt Enable
10
1
read-write
LSERDYC
LSE Ready Interrupt Clear
17
1
write-only
LSERDYF
LSE Ready Interrupt flag
1
1
read-only
LSERDYIE
LSE Ready Interrupt Enable
9
1
read-write
LSIRDYC
LSI Ready Interrupt Clear
16
1
write-only
LSIRDYF
LSI Ready Interrupt flag
0
1
read-only
LSIRDYIE
LSI Ready Interrupt Enable
8
1
read-write
PLLRDYC
PLL Ready Interrupt Clear
20
1
write-only
PLLRDYF
PLL Ready Interrupt flag
4
1
read-only
PLLRDYIE
PLL Ready Interrupt Enable
12
1
read-write
CR
CR
Clock control register
0x0
32
read-write
n
0x0
0x0
CSSON
Clock Security System enable
19
1
read-write
HSEBYP
External High Speed clock Bypass
18
1
read-write
HSEON
External High Speed clock enable
16
1
read-write
HSERDY
External High Speed clock ready flag
17
1
read-only
HSICAL
Internal High Speed clock Calibration
8
8
read-only
HSION
Internal High Speed clock enable
0
1
read-write
HSIRDY
Internal High Speed clock ready flag
1
1
read-only
HSITRIM
Internal High Speed clock trimming
3
5
read-write
PLLON
PLL enable
24
1
read-write
PLLRDY
PLL clock ready flag
25
1
read-only
CSR
CSR
Control/status register (RCC_CSR)
0x24
32
read-write
n
0x0
0x0
IWDGRSTF
Independent watchdog reset flag
29
1
read-write
LPWRRSTF
Low-power reset flag
31
1
read-write
LSION
Internal low speed oscillator enable
0
1
read-write
LSIRDY
Internal low speed oscillator ready
1
1
read-only
PINRSTF
PIN reset flag
26
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
RMVF
Remove reset flag
24
1
read-write
SFTRSTF
Software reset flag
28
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
RTC
Real time clock
RTC
0x0
0x0
0x400
registers
n
RTC_WKUP_IRQ
RTC Wakeup through EXTI line
interrupt
3
RTC_WKUP
RTC Wakeup through EXTI line interrupt
3
RTCAlarm_IRQ
RTC Alarms through EXTI line
interrupt
41
RTCAlarm
RTC Alarms through EXTI line interrupt
41
ALRH
ALRH
RTC Alarm Register High
0x20
32
write-only
n
0x0
0x0
ALRH
RTC alarm register high
0
16
ALRL
ALRL
RTC Alarm Register Low
0x24
32
write-only
n
0x0
0x0
ALRL
RTC alarm register low
0
16
CNTH
CNTH
RTC Counter Register High
0x18
32
read-write
n
0x0
0x0
CNTH
RTC counter register high
0
16
CNTL
CNTL
RTC Counter Register Low
0x1C
32
read-write
n
0x0
0x0
CNTL
RTC counter register Low
0
16
CRH
CRH
RTC Control Register High
0x0
32
read-write
n
0x0
0x0
ALRIE
Alarm interrupt Enable
1
1
OWIE
Overflow interrupt Enable
2
1
SECIE
Second interrupt Enable
0
1
CRL
CRL
RTC Control Register Low
0x4
32
read-write
n
0x0
0x0
ALRF
Alarm Flag
1
1
read-write
CNF
Configuration Flag
4
1
read-write
OWF
Overflow Flag
2
1
read-write
RSF
Registers Synchronized Flag
3
1
read-write
RTOFF
RTC operation OFF
5
1
read-only
SECF
Second Flag
0
1
read-write
DIVH
DIVH
RTC Prescaler Divider Register High
0x10
32
read-only
n
0x0
0x0
DIVH
RTC prescaler divider register high
0
4
DIVL
DIVL
RTC Prescaler Divider Register Low
0x14
32
read-only
n
0x0
0x0
DIVL
RTC prescaler divider register Low
0
16
PRLH
PRLH
RTC Prescaler Load Register High
0x8
32
write-only
n
0x0
0x0
PRLH
RTC Prescaler Load Register High
0
4
PRLL
PRLL
RTC Prescaler Load Register Low
0xC
32
write-only
n
0x0
0x0
PRLL
RTC Prescaler Divider Register Low
0
16
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI1 global interrupt
35
SPI1_IRQ
SPI1 global interrupt
35
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TXE
Transmit buffer empty
1
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI2
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI2
SPI2 global interrupt
36
SPI2_IRQ
SPI2 global interrupt
36
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TXE
Transmit buffer empty
1
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI3
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI3
SPI3 global interrupt
51
SPI3_IRQ
SPI3 global interrupt
51
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TXE
Transmit buffer empty
1
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
TIM1
Advanced timer
TIM
0x0
0x0
0x400
registers
n
TIM1_BRK_TIM15_IRQ
TIM1 Break interrupt and TIM15 global
interrupt
24
TIM1_BRK_TIM15
TIM1 Break interrupt and TIM15 global interrupt
24
TIM1_UP_TIM16_IRQ
TIM1 Update interrupt and TIM16 global
interrupt
25
TIM1_UP_TIM16
TIM1 Update interrupt and TIM16 global interrupt
25
TIM1_TRG_COM_TIM17_IRQ
TIM1 Trigger and Commutation interrupts and
TIM17 global interrupt
26
TIM1_TRG_COM_TIM17
TIM1 Trigger and Commutation interrupts and TIM17 global interrupt
26
TIM1_CC
TIM1 Capture Compare interrupt
27
TIM1_CC_IRQ
TIM1 Capture Compare interrupt
27
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
15
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
15
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM12
General purpose timer
TIM
0x0
0x0
0x400
registers
n
TIM12_IRQ
TIM12 global interrupt
43
TIM12
TIM12 global interrupt
43
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
3
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
TIE
Trigger interrupt enable
6
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM13
General purpose timer
TIM
0x0
0x0
0x400
registers
n
TIM13_IRQ
TIM13 global interrupt
44
TIM13
TIM13 global interrupt
44
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
UDIS
Update disable
1
1
URS
Update request source
2
1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
UIF
Update interrupt flag
0
1
TIM14
General purpose timer
TIM
0x0
0x0
0x400
registers
n
TIM13_IRQ
TIM13 global interrupt
44
TIM13
TIM13 global interrupt
44
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
UDIS
Update disable
1
1
URS
Update request source
2
1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
UIF
Update interrupt flag
0
1
TIM15
General purpose timers
TIM
0x0
0x0
0x400
registers
n
TIM1_BRK_TIM15_IRQ
TIM1 Break interrupt and TIM15 global
interrupt
24
TIM1_BRK_TIM15
TIM1 Break interrupt and TIM15 global interrupt
24
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM16
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM1_UP_TIM16_IRQ
TIM1 Update interrupt and TIM16 global
interrupt
25
TIM1_UP_TIM16
TIM1 Update interrupt and TIM16 global interrupt
25
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM17
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM1_TRG_COM_TIM17_IRQ
TIM1 Trigger and Commutation interrupts and
TIM17 global interrupt
26
TIM1_TRG_COM_TIM17
TIM1 Trigger and Commutation interrupts and TIM17 global interrupt
26
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM2
General purpose timer
TIM
0x0
0x0
0x400
registers
n
TIM2
TIM2 global interrupt
28
TIM2_IRQ
TIM2 global interrupt
28
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM3
General purpose timer
TIM
0x0
0x0
0x400
registers
n
TIM3
TIM3 global interrupt
29
TIM3_IRQ
TIM3 global interrupt
29
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM4
General purpose timer
TIM
0x0
0x0
0x400
registers
n
TIM4
TIM4 global interrupt
30
TIM4_IRQ
TIM4 global interrupt
30
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM5
General purpose timer
TIM
0x0
0x0
0x400
registers
n
TIM5
TIM5 global interrupt
50
TIM5_IRQ
TIM5 global interrupt
50
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM6
Basic timer
TIM
0x0
0x0
0x400
registers
n
TIM6_DAC_IRQ
TIM6 global and DAC underrun
interrupts
54
TIM6_DAC
TIM6 global and DAC underrun interrupts
54
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
TIM7
Basic timer
TIM
0x0
0x0
0x400
registers
n
TIM7
TIM7 global interrupt
55
TIM7_IRQ
TIM7 global interrupt
55
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
UART4
Universal asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
UART4
Uart4 Interrupt
8
UART4_IRQ
UART4 global interrupt
52
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
DR
0
9
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NE
Noise error flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
UART5
Universal asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
UART5
UART5 global interrupt
53
UART5_IRQ
UART5 global interrupt
53
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLEIE
4
1
M
M
12
1
PCE
PCE
10
1
PEIE
PEIE
8
1
PS
PS
9
1
RE
RE
2
1
RWU
RWU
1
1
RXNEIE
RXNEIE
5
1
SBK
SBK
0
1
TCIE
TCIE
6
1
TE
TE
3
1
TXEIE
TXEIE
7
1
UE
UE
13
1
WAKE
WAKE
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
ADD
0
4
LBDIE
LBDIE
6
1
LBDL
LBDL
5
1
LINEN
LINEN
14
1
STOP
STOP
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
DR
0
9
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
FE
FE
1
1
read-only
IDLE
IDLE
4
1
read-only
LBD
LBD
8
1
read-write
NE
NE
2
1
read-only
ORE
ORE
3
1
read-only
PE
PE
0
1
read-only
RXNE
RXNE
5
1
read-write
TC
TC
6
1
read-write
TXE
TXE
7
1
read-only
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1
USART1 global interrupt
37
USART1_IRQ
USART1 global interrupt
37
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NE
Noise error flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART2
USART2 global interrupt
38
USART2_IRQ
USART2 global interrupt
38
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NE
Noise error flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART3
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART3
USART3 global interrupt
39
USART3_IRQ
USART3 global interrupt
39
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NE
Noise error flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
WWDG
Window watchdog
WWDG
0x0
0x0
0x400
registers
n
WWDG
Window Watchdog interrupt
0
WWDG_IRQ
Window Watchdog interrupt
0
CFR
CFR
Configuration register (WWDG_CFR)
0x4
32
read-write
n
0x0
0x0
EWI
Early Wakeup Interrupt
9
1
W
7-bit window value
0
7
WDGTB
Timer Base
7
2
CR
CR
Control register (WWDG_CR)
0x0
32
read-write
n
0x0
0x0
T
7-bit counter (MSB to LSB)
0
7
WDGA
Activation bit
7
1
SR
SR
Status register (WWDG_SR)
0x8
32
read-write
n
0x0
0x0
EWI
Early Wakeup Interrupt
0
1