STMicroelectronics
STM32F334x4
2024.05.08
STM32F334x4
false
ADC1
Analog-to-Digital Converter
ADC
0x0
0x0
0x100
registers
n
ADC1_2
ADC1 and ADC2 global interrupt
18
AWD2CR
AWD2CR
Analog Watchdog 2 Configuration Register
0xA0
32
read-write
n
0x0
0x0
AWD2CH
AWD2CH
1
18
AWD3CR
AWD3CR
Analog Watchdog 3 Configuration Register
0xA4
32
read-write
n
0x0
0x0
AWD3CH
AWD3CH
1
18
CALFACT
CALFACT
Calibration Factors
0xB4
32
read-write
n
0x0
0x0
CALFACT_D
CALFACT_D
16
7
CALFACT_S
CALFACT_S
0
7
CFGR
CFGR
configuration register
0xC
32
read-write
n
0x0
0x0
ALIGN
ALIGN
5
1
AUTDLY
AUTDLY
14
1
AUTOFF
AUTOFF
15
1
AWD1EN
AWD1EN
23
1
AWD1SGL
AWD1SGL
22
1
AWDCH1CH
AWDCH1CH
26
5
CONT
CONT
13
1
DISCEN
DISCEN
16
1
DISCNUM
DISCNUM
17
3
DMACFG
DMACFG
1
1
DMAEN
DMAEN
0
1
EXTEN
EXTEN
10
2
EXTSEL
EXTSEL
6
4
JAUTO
JAUTO
25
1
JAWD1EN
JAWD1EN
24
1
JDISCEN
JDISCEN
20
1
JQM
JQM
21
1
OVRMOD
OVRMOD
12
1
RES
RES
3
2
CR
CR
control register
0x8
32
read-write
n
0x0
0x0
ADCAL
ADCAL
31
1
ADCALDIF
ADCALDIF
30
1
ADDIS
ADDIS
1
1
ADEN
ADEN
0
1
ADSTART
ADSTART
2
1
ADSTP
ADSTP
4
1
ADVREGEN
ADVREGEN
28
1
DEEPPWD
DEEPPWD
29
1
JADSTART
JADSTART
3
1
JADSTP
JADSTP
5
1
DIFSEL
DIFSEL
Differential Mode Selection Register 2
0xB0
32
read-write
n
0x0
0x0
DIFSEL_16_18
Differential mode for channels 18 to 16
16
3
read-only
DIFSEL_1_15
Differential mode for channels 15 to 1
1
15
read-write
DR
DR
regular Data Register
0x40
32
read-only
n
0x0
0x0
regularDATA
regularDATA
0
16
IER
IER
interrupt enable register
0x4
32
read-write
n
0x0
0x0
ADRDYIE
ADRDYIE
0
1
AWD1IE
AWD1IE
7
1
AWD2IE
AWD2IE
8
1
AWD3IE
AWD3IE
9
1
EOCIE
EOCIE
2
1
EOSIE
EOSIE
3
1
EOSMPIE
EOSMPIE
1
1
JEOCIE
JEOCIE
5
1
JEOSIE
JEOSIE
6
1
JQOVFIE
JQOVFIE
10
1
OVRIE
OVRIE
4
1
ISR
ISR
interrupt and status register
0x0
32
read-write
n
0x0
0x0
ADRDY
ADRDY
0
1
AWD1
AWD1
7
1
AWD2
AWD2
8
1
AWD3
AWD3
9
1
EOC
EOC
2
1
EOS
EOS
3
1
EOSMP
EOSMP
1
1
JEOC
JEOC
5
1
JEOS
JEOS
6
1
JQOVF
JQOVF
10
1
OVR
OVR
4
1
JDR1
JDR1
injected data register 1
0x80
32
read-only
n
0x0
0x0
JDATA1
JDATA1
0
16
JDR2
JDR2
injected data register 2
0x84
32
read-only
n
0x0
0x0
JDATA2
JDATA2
0
16
JDR3
JDR3
injected data register 3
0x88
32
read-only
n
0x0
0x0
JDATA3
JDATA3
0
16
JDR4
JDR4
injected data register 4
0x8C
32
read-only
n
0x0
0x0
JDATA4
JDATA4
0
16
JSQR
JSQR
injected sequence register
0x4C
32
read-write
n
0x0
0x0
JEXTEN
JEXTEN
6
2
JEXTSEL
JEXTSEL
2
4
JL
JL
0
2
JSQ1
JSQ1
8
5
JSQ2
JSQ2
14
5
JSQ3
JSQ3
20
5
JSQ4
JSQ4
26
5
OFR1
OFR1
offset register 1
0x60
32
read-write
n
0x0
0x0
OFFSET1
OFFSET1
0
12
OFFSET1_CH
OFFSET1_CH
26
5
OFFSET1_EN
OFFSET1_EN
31
1
OFR2
OFR2
offset register 2
0x64
32
read-write
n
0x0
0x0
OFFSET2
OFFSET2
0
12
OFFSET2_CH
OFFSET2_CH
26
5
OFFSET2_EN
OFFSET2_EN
31
1
OFR3
OFR3
offset register 3
0x68
32
read-write
n
0x0
0x0
OFFSET3
OFFSET3
0
12
OFFSET3_CH
OFFSET3_CH
26
5
OFFSET3_EN
OFFSET3_EN
31
1
OFR4
OFR4
offset register 4
0x6C
32
read-write
n
0x0
0x0
OFFSET4
OFFSET4
0
12
OFFSET4_CH
OFFSET4_CH
26
5
OFFSET4_EN
OFFSET4_EN
31
1
SMPR1
SMPR1
sample time register 1
0x14
32
read-write
n
0x0
0x0
SMP1
SMP1
3
3
SMP2
SMP2
6
3
SMP3
SMP3
9
3
SMP4
SMP4
12
3
SMP5
SMP5
15
3
SMP6
SMP6
18
3
SMP7
SMP7
21
3
SMP8
SMP8
24
3
SMP9
SMP9
27
3
SMPR2
SMPR2
sample time register 2
0x18
32
read-write
n
0x0
0x0
SMP10
SMP10
0
3
SMP11
SMP11
3
3
SMP12
SMP12
6
3
SMP13
SMP13
9
3
SMP14
SMP14
12
3
SMP15
SMP15
15
3
SMP16
SMP16
18
3
SMP17
SMP17
21
3
SMP18
SMP18
24
3
SQR1
SQR1
regular sequence register 1
0x30
32
read-write
n
0x0
0x0
L3
L3
0
4
SQ1
SQ1
6
5
SQ2
SQ2
12
5
SQ3
SQ3
18
5
SQ4
SQ4
24
5
SQR2
SQR2
regular sequence register 2
0x34
32
read-write
n
0x0
0x0
SQ5
SQ5
0
5
SQ6
SQ6
6
5
SQ7
SQ7
12
5
SQ8
SQ8
18
5
SQ9
SQ9
24
5
SQR3
SQR3
regular sequence register 3
0x38
32
read-write
n
0x0
0x0
SQ10
SQ10
0
5
SQ11
SQ11
6
5
SQ12
SQ12
12
5
SQ13
SQ13
18
5
SQ14
SQ14
24
5
SQR4
SQR4
regular sequence register 4
0x3C
32
read-write
n
0x0
0x0
SQ15
SQ15
0
5
SQ16
SQ16
6
5
TR1
TR1
watchdog threshold register 1
0x20
32
read-write
n
0x0
0x0
HT1
HT1
16
12
LT1
LT1
0
12
TR2
TR2
watchdog threshold register
0x24
32
read-write
n
0x0
0x0
HT2
HT2
16
8
LT2
LT2
0
8
TR3
TR3
watchdog threshold register 3
0x28
32
read-write
n
0x0
0x0
HT3
HT3
16
8
LT3
LT3
0
8
ADC1_2
Analog-to-Digital Converter
ADC
0x0
0x0
0xD
registers
n
ADC1_2
ADC1 and ADC2 global interrupt
18
CCR
CCR
ADC common control register
0x8
32
read-write
n
0x0
0x0
CKMODE
ADC clock mode
16
2
DELAY
Delay between 2 sampling phases
8
4
DMACFG
DMA configuration (for multi-ADC mode)
13
1
MDMA
Direct memory access mode for multi ADC mode
14
2
MULT
Multi ADC mode selection
0
5
TSEN
Temperature sensor enable
23
1
VBATEN
VBAT enable
24
1
VREFEN
VREFINT enable
22
1
CDR
CDR
ADC common regular data register for dual and triple modes
0xC
32
read-only
n
0x0
0x0
RDATA_MST
Regular data of the master ADC
0
16
RDATA_SLV
Regular data of the slave ADC
16
16
CSR
CSR
ADC Common status register
0x0
32
read-only
n
0x0
0x0
ADDRDY_MST
ADDRDY_MST
0
1
ADRDY_SLV
ADRDY_SLV
16
1
AWD1_MST
AWD1_MST
7
1
AWD1_SLV
Analog watchdog 1 flag of the slave ADC
23
1
AWD2_MST
AWD2_MST
8
1
AWD2_SLV
Analog watchdog 2 flag of the slave ADC
24
1
AWD3_MST
AWD3_MST
9
1
AWD3_SLV
Analog watchdog 3 flag of the slave ADC
25
1
EOC_MST
EOC_MST
2
1
EOC_SLV
End of regular conversion of the slave ADC
18
1
EOSMP_MST
EOSMP_MST
1
1
EOSMP_SLV
EOSMP_SLV
17
1
EOS_MST
EOS_MST
3
1
EOS_SLV
End of regular sequence flag of the slave ADC
19
1
JEOC_MST
JEOC_MST
5
1
JEOC_SLV
End of injected conversion flag of the slave ADC
21
1
JEOS_MST
JEOS_MST
6
1
JEOS_SLV
End of injected sequence flag of the slave ADC
22
1
JQOVF_MST
JQOVF_MST
10
1
JQOVF_SLV
Injected Context Queue Overflow flag of the slave ADC
26
1
OVR_MST
OVR_MST
4
1
OVR_SLV
Overrun flag of the slave ADC
20
1
ADC2
Analog-to-Digital Converter
ADC
0x0
0x0
0x100
registers
n
ADC1_2
ADC1 and ADC2 global interrupt
18
AWD2CR
AWD2CR
Analog Watchdog 2 Configuration Register
0xA0
32
read-write
n
0x0
0x0
AWD2CH
AWD2CH
1
18
AWD3CR
AWD3CR
Analog Watchdog 3 Configuration Register
0xA4
32
read-write
n
0x0
0x0
AWD3CH
AWD3CH
1
18
CALFACT
CALFACT
Calibration Factors
0xB4
32
read-write
n
0x0
0x0
CALFACT_D
CALFACT_D
16
7
CALFACT_S
CALFACT_S
0
7
CFGR
CFGR
configuration register
0xC
32
read-write
n
0x0
0x0
ALIGN
ALIGN
5
1
AUTDLY
AUTDLY
14
1
AUTOFF
AUTOFF
15
1
AWD1EN
AWD1EN
23
1
AWD1SGL
AWD1SGL
22
1
AWDCH1CH
AWDCH1CH
26
5
CONT
CONT
13
1
DISCEN
DISCEN
16
1
DISCNUM
DISCNUM
17
3
DMACFG
DMACFG
1
1
DMAEN
DMAEN
0
1
EXTEN
EXTEN
10
2
EXTSEL
EXTSEL
6
4
JAUTO
JAUTO
25
1
JAWD1EN
JAWD1EN
24
1
JDISCEN
JDISCEN
20
1
JQM
JQM
21
1
OVRMOD
OVRMOD
12
1
RES
RES
3
2
CR
CR
control register
0x8
32
read-write
n
0x0
0x0
ADCAL
ADCAL
31
1
ADCALDIF
ADCALDIF
30
1
ADDIS
ADDIS
1
1
ADEN
ADEN
0
1
ADSTART
ADSTART
2
1
ADSTP
ADSTP
4
1
ADVREGEN
ADVREGEN
28
1
DEEPPWD
DEEPPWD
29
1
JADSTART
JADSTART
3
1
JADSTP
JADSTP
5
1
DIFSEL
DIFSEL
Differential Mode Selection Register 2
0xB0
32
read-write
n
0x0
0x0
DIFSEL_16_18
Differential mode for channels 18 to 16
16
3
read-only
DIFSEL_1_15
Differential mode for channels 15 to 1
1
15
read-write
DR
DR
regular Data Register
0x40
32
read-only
n
0x0
0x0
regularDATA
regularDATA
0
16
IER
IER
interrupt enable register
0x4
32
read-write
n
0x0
0x0
ADRDYIE
ADRDYIE
0
1
AWD1IE
AWD1IE
7
1
AWD2IE
AWD2IE
8
1
AWD3IE
AWD3IE
9
1
EOCIE
EOCIE
2
1
EOSIE
EOSIE
3
1
EOSMPIE
EOSMPIE
1
1
JEOCIE
JEOCIE
5
1
JEOSIE
JEOSIE
6
1
JQOVFIE
JQOVFIE
10
1
OVRIE
OVRIE
4
1
ISR
ISR
interrupt and status register
0x0
32
read-write
n
0x0
0x0
ADRDY
ADRDY
0
1
AWD1
AWD1
7
1
AWD2
AWD2
8
1
AWD3
AWD3
9
1
EOC
EOC
2
1
EOS
EOS
3
1
EOSMP
EOSMP
1
1
JEOC
JEOC
5
1
JEOS
JEOS
6
1
JQOVF
JQOVF
10
1
OVR
OVR
4
1
JDR1
JDR1
injected data register 1
0x80
32
read-only
n
0x0
0x0
JDATA1
JDATA1
0
16
JDR2
JDR2
injected data register 2
0x84
32
read-only
n
0x0
0x0
JDATA2
JDATA2
0
16
JDR3
JDR3
injected data register 3
0x88
32
read-only
n
0x0
0x0
JDATA3
JDATA3
0
16
JDR4
JDR4
injected data register 4
0x8C
32
read-only
n
0x0
0x0
JDATA4
JDATA4
0
16
JSQR
JSQR
injected sequence register
0x4C
32
read-write
n
0x0
0x0
JEXTEN
JEXTEN
6
2
JEXTSEL
JEXTSEL
2
4
JL
JL
0
2
JSQ1
JSQ1
8
5
JSQ2
JSQ2
14
5
JSQ3
JSQ3
20
5
JSQ4
JSQ4
26
5
OFR1
OFR1
offset register 1
0x60
32
read-write
n
0x0
0x0
OFFSET1
OFFSET1
0
12
OFFSET1_CH
OFFSET1_CH
26
5
OFFSET1_EN
OFFSET1_EN
31
1
OFR2
OFR2
offset register 2
0x64
32
read-write
n
0x0
0x0
OFFSET2
OFFSET2
0
12
OFFSET2_CH
OFFSET2_CH
26
5
OFFSET2_EN
OFFSET2_EN
31
1
OFR3
OFR3
offset register 3
0x68
32
read-write
n
0x0
0x0
OFFSET3
OFFSET3
0
12
OFFSET3_CH
OFFSET3_CH
26
5
OFFSET3_EN
OFFSET3_EN
31
1
OFR4
OFR4
offset register 4
0x6C
32
read-write
n
0x0
0x0
OFFSET4
OFFSET4
0
12
OFFSET4_CH
OFFSET4_CH
26
5
OFFSET4_EN
OFFSET4_EN
31
1
SMPR1
SMPR1
sample time register 1
0x14
32
read-write
n
0x0
0x0
SMP1
SMP1
3
3
SMP2
SMP2
6
3
SMP3
SMP3
9
3
SMP4
SMP4
12
3
SMP5
SMP5
15
3
SMP6
SMP6
18
3
SMP7
SMP7
21
3
SMP8
SMP8
24
3
SMP9
SMP9
27
3
SMPR2
SMPR2
sample time register 2
0x18
32
read-write
n
0x0
0x0
SMP10
SMP10
0
3
SMP11
SMP11
3
3
SMP12
SMP12
6
3
SMP13
SMP13
9
3
SMP14
SMP14
12
3
SMP15
SMP15
15
3
SMP16
SMP16
18
3
SMP17
SMP17
21
3
SMP18
SMP18
24
3
SQR1
SQR1
regular sequence register 1
0x30
32
read-write
n
0x0
0x0
L3
L3
0
4
SQ1
SQ1
6
5
SQ2
SQ2
12
5
SQ3
SQ3
18
5
SQ4
SQ4
24
5
SQR2
SQR2
regular sequence register 2
0x34
32
read-write
n
0x0
0x0
SQ5
SQ5
0
5
SQ6
SQ6
6
5
SQ7
SQ7
12
5
SQ8
SQ8
18
5
SQ9
SQ9
24
5
SQR3
SQR3
regular sequence register 3
0x38
32
read-write
n
0x0
0x0
SQ10
SQ10
0
5
SQ11
SQ11
6
5
SQ12
SQ12
12
5
SQ13
SQ13
18
5
SQ14
SQ14
24
5
SQR4
SQR4
regular sequence register 4
0x3C
32
read-write
n
0x0
0x0
SQ15
SQ15
0
5
SQ16
SQ16
6
5
TR1
TR1
watchdog threshold register 1
0x20
32
read-write
n
0x0
0x0
HT1
HT1
16
12
LT1
LT1
0
12
TR2
TR2
watchdog threshold register
0x24
32
read-write
n
0x0
0x0
HT2
HT2
16
8
LT2
LT2
0
8
TR3
TR3
watchdog threshold register 3
0x28
32
read-write
n
0x0
0x0
HT3
HT3
16
8
LT3
LT3
0
8
CAN
Controller area network
CAN
0x0
0x0
0x400
registers
n
USB_HP_CAN_TX
USB High Priority/CAN_TX interrupts
19
USB_LP_CAN_RX0
USB Low Priority/CAN_RX0 interrupts
20
CAN_RX1
CAN_RX1 interrupt
21
CAN_SCE
CAN_SCE interrupt
22
BTR
BTR
bit timing register
0x1C
32
read-write
n
0x0
0x0
BRP
BRP
0
10
LBKM
LBKM
30
1
SILM
SILM
31
1
SJW
SJW
24
2
TS1
TS1
16
4
TS2
TS2
20
3
ESR
ESR
error status register
0x18
32
read-write
n
0x0
0x0
BOFF
BOFF
2
1
read-only
EPVF
EPVF
1
1
read-only
EWGF
EWGF
0
1
read-only
LEC
LEC
4
3
read-write
REC
REC
24
8
read-only
TEC
TEC
16
8
read-only
F0R1
F0R1
Filter bank 0 register 1
0x240
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F0R2
F0R2
Filter bank 0 register 2
0x244
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R1
F1R1
Filter bank 1 register 1
0x248
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R2
F1R2
Filter bank 1 register 2
0x24C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R1
F27R1
Filter bank 27 register 1
0x318
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R2
F27R2
Filter bank 27 register 2
0x31C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
FA1R
FA1R
CAN filter activation register
0x21C
32
read-write
n
0x0
0x0
FACT0
Filter active
0
1
FACT1
Filter active
1
1
FACT10
Filter active
10
1
FACT11
Filter active
11
1
FACT12
Filter active
12
1
FACT13
Filter active
13
1
FACT14
Filter active
14
1
FACT15
Filter active
15
1
FACT16
Filter active
16
1
FACT17
Filter active
17
1
FACT18
Filter active
18
1
FACT19
Filter active
19
1
FACT2
Filter active
2
1
FACT20
Filter active
20
1
FACT21
Filter active
21
1
FACT22
Filter active
22
1
FACT23
Filter active
23
1
FACT24
Filter active
24
1
FACT25
Filter active
25
1
FACT26
Filter active
26
1
FACT27
Filter active
27
1
FACT3
Filter active
3
1
FACT4
Filter active
4
1
FACT5
Filter active
5
1
FACT6
Filter active
6
1
FACT7
Filter active
7
1
FACT8
Filter active
8
1
FACT9
Filter active
9
1
FFA1R
FFA1R
filter FIFO assignment register
0x214
32
read-write
n
0x0
0x0
FFA0
Filter FIFO assignment for filter 0
0
1
FFA1
Filter FIFO assignment for filter 1
1
1
FFA10
Filter FIFO assignment for filter 10
10
1
FFA11
Filter FIFO assignment for filter 11
11
1
FFA12
Filter FIFO assignment for filter 12
12
1
FFA13
Filter FIFO assignment for filter 13
13
1
FFA14
Filter FIFO assignment for filter 14
14
1
FFA15
Filter FIFO assignment for filter 15
15
1
FFA16
Filter FIFO assignment for filter 16
16
1
FFA17
Filter FIFO assignment for filter 17
17
1
FFA18
Filter FIFO assignment for filter 18
18
1
FFA19
Filter FIFO assignment for filter 19
19
1
FFA2
Filter FIFO assignment for filter 2
2
1
FFA20
Filter FIFO assignment for filter 20
20
1
FFA21
Filter FIFO assignment for filter 21
21
1
FFA22
Filter FIFO assignment for filter 22
22
1
FFA23
Filter FIFO assignment for filter 23
23
1
FFA24
Filter FIFO assignment for filter 24
24
1
FFA25
Filter FIFO assignment for filter 25
25
1
FFA26
Filter FIFO assignment for filter 26
26
1
FFA27
Filter FIFO assignment for filter 27
27
1
FFA3
Filter FIFO assignment for filter 3
3
1
FFA4
Filter FIFO assignment for filter 4
4
1
FFA5
Filter FIFO assignment for filter 5
5
1
FFA6
Filter FIFO assignment for filter 6
6
1
FFA7
Filter FIFO assignment for filter 7
7
1
FFA8
Filter FIFO assignment for filter 8
8
1
FFA9
Filter FIFO assignment for filter 9
9
1
FM1R
FM1R
filter mode register
0x204
32
read-write
n
0x0
0x0
FBM0
Filter mode
0
1
FBM1
Filter mode
1
1
FBM10
Filter mode
10
1
FBM11
Filter mode
11
1
FBM12
Filter mode
12
1
FBM13
Filter mode
13
1
FBM14
Filter mode
14
1
FBM15
Filter mode
15
1
FBM16
Filter mode
16
1
FBM17
Filter mode
17
1
FBM18
Filter mode
18
1
FBM19
Filter mode
19
1
FBM2
Filter mode
2
1
FBM20
Filter mode
20
1
FBM21
Filter mode
21
1
FBM22
Filter mode
22
1
FBM23
Filter mode
23
1
FBM24
Filter mode
24
1
FBM25
Filter mode
25
1
FBM26
Filter mode
26
1
FBM27
Filter mode
27
1
FBM3
Filter mode
3
1
FBM4
Filter mode
4
1
FBM5
Filter mode
5
1
FBM6
Filter mode
6
1
FBM7
Filter mode
7
1
FBM8
Filter mode
8
1
FBM9
Filter mode
9
1
FMR
FMR
filter master register
0x200
32
read-write
n
0x0
0x0
CAN2SB
CAN2 start bank
8
6
FINIT
Filter init mode
0
1
FS1R
FS1R
filter scale register
0x20C
32
read-write
n
0x0
0x0
FSC0
Filter scale configuration
0
1
FSC1
Filter scale configuration
1
1
FSC10
Filter scale configuration
10
1
FSC11
Filter scale configuration
11
1
FSC12
Filter scale configuration
12
1
FSC13
Filter scale configuration
13
1
FSC14
Filter scale configuration
14
1
FSC15
Filter scale configuration
15
1
FSC16
Filter scale configuration
16
1
FSC17
Filter scale configuration
17
1
FSC18
Filter scale configuration
18
1
FSC19
Filter scale configuration
19
1
FSC2
Filter scale configuration
2
1
FSC20
Filter scale configuration
20
1
FSC21
Filter scale configuration
21
1
FSC22
Filter scale configuration
22
1
FSC23
Filter scale configuration
23
1
FSC24
Filter scale configuration
24
1
FSC25
Filter scale configuration
25
1
FSC26
Filter scale configuration
26
1
FSC27
Filter scale configuration
27
1
FSC3
Filter scale configuration
3
1
FSC4
Filter scale configuration
4
1
FSC5
Filter scale configuration
5
1
FSC6
Filter scale configuration
6
1
FSC7
Filter scale configuration
7
1
FSC8
Filter scale configuration
8
1
FSC9
Filter scale configuration
9
1
IER
IER
interrupt enable register
0x14
32
read-write
n
0x0
0x0
BOFIE
BOFIE
10
1
EPVIE
EPVIE
9
1
ERRIE
ERRIE
15
1
EWGIE
EWGIE
8
1
FFIE0
FFIE0
2
1
FFIE1
FFIE1
5
1
FMPIE0
FMPIE0
1
1
FMPIE1
FMPIE1
4
1
FOVIE0
FOVIE0
3
1
FOVIE1
FOVIE1
6
1
LECIE
LECIE
11
1
SLKIE
SLKIE
17
1
TMEIE
TMEIE
0
1
WKUIE
WKUIE
16
1
MCR
MCR
master control register
0x0
32
read-write
n
0x0
0x0
ABOM
ABOM
6
1
AWUM
AWUM
5
1
DBF
DBF
16
1
INRQ
INRQ
0
1
NART
NART
4
1
RESET
RESET
15
1
RFLM
RFLM
3
1
SLEEP
SLEEP
1
1
TTCM
TTCM
7
1
TXFP
TXFP
2
1
MSR
MSR
master status register
0x4
32
read-write
n
0x0
0x0
ERRI
ERRI
2
1
read-write
INAK
INAK
0
1
read-only
RX
RX
11
1
read-only
RXM
RXM
9
1
read-only
SAMP
SAMP
10
1
read-only
SLAK
SLAK
1
1
read-only
SLAKI
SLAKI
4
1
read-write
TXM
TXM
8
1
read-only
WKUI
WKUI
3
1
read-write
RDH0R
RDH0R
receive FIFO mailbox data high register
0x1BC
32
read-only
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDH1R
RDH1R
receive FIFO mailbox data high register
0x1CC
32
read-only
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDL0R
RDL0R
receive FIFO mailbox data low register
0x1B8
32
read-only
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDL1R
RDL1R
receive FIFO mailbox data low register
0x1C8
32
read-only
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDT0R
RDT0R
receive FIFO mailbox data length control and time stamp register
0x1B4
32
read-only
n
0x0
0x0
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RDT1R
RDT1R
receive FIFO mailbox data length control and time stamp register
0x1C4
32
read-only
n
0x0
0x0
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RF0R
RF0R
receive FIFO 0 register
0xC
32
read-write
n
0x0
0x0
FMP0
FMP0
0
2
read-only
FOVR0
FOVR0
4
1
read-write
FULL0
FULL0
3
1
read-write
RFOM0
RFOM0
5
1
read-write
RF1R
RF1R
receive FIFO 1 register
0x10
32
read-write
n
0x0
0x0
FMP1
FMP1
0
2
read-only
FOVR1
FOVR1
4
1
read-write
FULL1
FULL1
3
1
read-write
RFOM1
RFOM1
5
1
read-write
RI0R
RI0R
receive FIFO mailbox identifier register
0x1B0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
RI1R
RI1R
receive FIFO mailbox identifier register
0x1C0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TDH0R
TDH0R
mailbox data high register
0x18C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH1R
TDH1R
mailbox data high register
0x19C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH2R
TDH2R
mailbox data high register
0x1AC
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDL0R
TDL0R
mailbox data low register
0x188
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL1R
TDL1R
mailbox data low register
0x198
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL2R
TDL2R
mailbox data low register
0x1A8
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDT0R
TDT0R
mailbox data length control and time stamp register
0x184
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT1R
TDT1R
mailbox data length control and time stamp register
0x194
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT2R
TDT2R
mailbox data length control and time stamp register
0x1A4
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TI0R
TI0R
TX mailbox identifier register
0x180
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI1R
TI1R
TX mailbox identifier register
0x190
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI2R
TI2R
TX mailbox identifier register
0x1A0
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TSR
TSR
transmit status register
0x8
32
read-write
n
0x0
0x0
ABRQ0
ABRQ0
7
1
read-write
ABRQ1
ABRQ1
15
1
read-write
ABRQ2
ABRQ2
23
1
read-write
ALST0
ALST0
2
1
read-write
ALST1
ALST1
10
1
read-write
ALST2
ALST2
18
1
read-write
CODE
CODE
24
2
read-only
LOW0
Lowest priority flag for mailbox 0
29
1
read-only
LOW1
Lowest priority flag for mailbox 1
30
1
read-only
LOW2
Lowest priority flag for mailbox 2
31
1
read-only
RQCP0
RQCP0
0
1
read-write
RQCP1
RQCP1
8
1
read-write
RQCP2
RQCP2
16
1
read-write
TERR0
TERR0
3
1
read-write
TERR1
TERR1
11
1
read-write
TERR2
TERR2
19
1
read-write
TME0
Lowest priority flag for mailbox 0
26
1
read-only
TME1
Lowest priority flag for mailbox 1
27
1
read-only
TME2
Lowest priority flag for mailbox 2
28
1
read-only
TXOK0
TXOK0
1
1
read-write
TXOK1
TXOK1
9
1
read-write
TXOK2
TXOK2
17
1
read-write
COMP
Comparator
COMP
0x0
0x0
0x19
registers
n
COMP123
COMP1 and COMP2 and COMP3 interrupts combined with EXTI Lines 21, 22 and 29 interrupts
64
COMP456
COMP4 and COMP5 and COMP6 interrupts combined with EXTI Lines 30, 31 and 32 interrupts
65
COMP7
COMP7 interrupt combined with EXTI Line 33 interrupt
66
COMP1_CSR
COMP1_CSR
control and status register
0x0
32
read-write
n
0x0
0x0
COMP1EN
Comparator 1 enable
0
1
read-write
COMP1HYST
Comparator 1 hysteresis
16
2
read-write
COMP1INSEL
Comparator 1 inverting input selection
4
3
read-write
COMP1LOCK
Comparator 1 lock
31
1
read-write
COMP1MODE
Comparator 1 mode
2
2
read-write
COMP1OUT
Comparator 1 output
30
1
read-only
COMP1POL
Comparator 1 output polarity
15
1
read-write
COMP1_BLANKING
Comparator 1 blanking source
18
3
read-write
COMP1_INP_DAC
COMP1_INP_DAC
1
1
read-write
COMP1_OUT_SEL
Comparator 1 output selection
10
4
read-write
COMP2_CSR
COMP2_CSR
control and status register
0x4
32
read-write
n
0x0
0x0
COMP2EN
Comparator 2 enable
0
1
read-write
COMP2HYST
Comparator 2 hysteresis
16
2
read-write
COMP2INMSEL
Comparator 1inverting input selection
9
1
read-write
COMP2INPSEL
Comparator 2 non inverted input selection
7
1
read-write
COMP2INSEL
Comparator 2 inverting input selection
4
3
read-write
COMP2LOCK
Comparator 2 lock
31
1
read-write
COMP2MODE
Comparator 2 mode
2
2
read-write
COMP2OUT
Comparator 2 output
30
1
read-only
COMP2POL
Comparator 2 output polarity
15
1
read-write
COMP2_BLANKING
Comparator 2 blanking source
18
3
read-write
COMP2_OUT_SEL
Comparator 2 output selection
10
4
read-write
COMP3_CSR
COMP3_CSR
control and status register
0x8
32
read-write
n
0x0
0x0
COMP3EN
Comparator 3 enable
0
1
read-write
COMP3HYST
Comparator 3 hysteresis
16
2
read-write
COMP3INPSEL
Comparator 3 non inverted input selection
7
1
read-write
COMP3INSEL
Comparator 3 inverting input selection
4
3
read-write
COMP3LOCK
Comparator 3 lock
31
1
read-write
COMP3MODE
Comparator 3 mode
2
2
read-write
COMP3OUT
Comparator 3 output
30
1
read-only
COMP3POL
Comparator 3 output polarity
15
1
read-write
COMP3_BLANKING
Comparator 3 blanking source
18
3
read-write
COMP3_OUT_SEL
Comparator 3 output selection
10
4
read-write
COMP4_CSR
COMP4_CSR
control and status register
0xC
32
read-write
n
0x0
0x0
COM4WINMODE
Comparator 4 window mode
9
1
read-write
COMP4EN
Comparator 4 enable
0
1
read-write
COMP4HYST
Comparator 4 hysteresis
16
2
read-write
COMP4INPSEL
Comparator 4 non inverted input selection
7
1
read-write
COMP4INSEL
Comparator 4 inverting input selection
4
3
read-write
COMP4LOCK
Comparator 4 lock
31
1
read-write
COMP4MODE
Comparator 4 mode
2
2
read-write
COMP4OUT
Comparator 4 output
30
1
read-only
COMP4POL
Comparator 4 output polarity
15
1
read-write
COMP4_BLANKING
Comparator 4 blanking source
18
3
read-write
COMP4_OUT_SEL
Comparator 4 output selection
10
4
read-write
COMP5_CSR
COMP5_CSR
control and status register
0x10
32
read-write
n
0x0
0x0
COMP5EN
Comparator 5 enable
0
1
read-write
COMP5HYST
Comparator 5 hysteresis
16
2
read-write
COMP5INPSEL
Comparator 5 non inverted input selection
7
1
read-write
COMP5INSEL
Comparator 5 inverting input selection
4
3
read-write
COMP5LOCK
Comparator 5 lock
31
1
read-write
COMP5MODE
Comparator 5 mode
2
2
read-write
COMP5OUT
Comparator51 output
30
1
read-only
COMP5POL
Comparator 5 output polarity
15
1
read-write
COMP5_BLANKING
Comparator 5 blanking source
18
3
read-write
COMP5_OUT_SEL
Comparator 5 output selection
10
4
read-write
COMP6_CSR
COMP6_CSR
control and status register
0x14
32
read-write
n
0x0
0x0
COM6WINMODE
Comparator 6 window mode
9
1
read-write
COMP6EN
Comparator 6 enable
0
1
read-write
COMP6HYST
Comparator 6 hysteresis
16
2
read-write
COMP6INPSEL
Comparator 6 non inverted input selection
7
1
read-write
COMP6INSEL
Comparator 6 inverting input selection
4
3
read-write
COMP6LOCK
Comparator 6 lock
31
1
read-write
COMP6MODE
Comparator 6 mode
2
2
read-write
COMP6OUT
Comparator 6 output
30
1
read-only
COMP6POL
Comparator 6 output polarity
15
1
read-write
COMP6_BLANKING
Comparator 6 blanking source
18
3
read-write
COMP6_OUT_SEL
Comparator 6 output selection
10
4
read-write
COMP7_CSR
COMP7_CSR
control and status register
0x18
32
read-write
n
0x0
0x0
COMP7EN
Comparator 7 enable
0
1
read-write
COMP7HYST
Comparator 7 hysteresis
16
2
read-write
COMP7INPSEL
Comparator 7 non inverted input selection
7
1
read-write
COMP7INSEL
Comparator 7 inverting input selection
4
3
read-write
COMP7LOCK
Comparator 7 lock
31
1
read-write
COMP7MODE
Comparator 7 mode
2
2
read-write
COMP7OUT
Comparator 7 output
30
1
read-only
COMP7POL
Comparator 7 output polarity
15
1
read-write
COMP7_BLANKING
Comparator 7 blanking source
18
3
read-write
COMP7_OUT_SEL
Comparator 7 output selection
10
4
read-write
CRC
cyclic redundancy check calculation unit
CRC
0x0
0x0
0x400
registers
n
CR
CR
Control register
0x8
32
read-write
n
0x0
0x0
POLYSIZE
Polynomial size
3
2
RESET
reset bit
0
1
REV_IN
Reverse input data
5
2
REV_OUT
Reverse output data
7
1
DR
DR
Data register
0x0
32
read-write
n
0x0
0x0
DR
Data register bits
0
32
IDR
IDR
Independent data register
0x4
32
read-write
n
0x0
0x0
IDR
General-purpose 8-bit data register bits
0
8
INIT
INIT
Initial CRC value
0x10
32
read-write
n
0x0
0x0
INIT
Programmable initial CRC value
0
32
POL
POL
CRC polynomial
0x14
32
read-write
n
0x0
0x0
POL
Programmable polynomial
0
32
DAC1
Digital-to-analog converter 1
DAC
0x0
0x0
0x400
registers
n
TIM6_DACUNDER
TIM6 global and DAC12 underrun interrupts
54
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
BOFF1
DAC channel1 output buffer disable
1
1
BOFF2
DAC channel2 output buffer disable
17
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN2
DAC channel2 DMA enable
28
1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt enable
13
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt enable
29
1
EN1
DAC channel1 enable
0
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude selector
8
4
MAMP2
DAC channel2 mask/amplitude selector
24
4
TEN1
DAC channel1 trigger enable
2
1
TEN2
DAC channel2 trigger enable
18
1
TSEL1
DAC channel1 trigger selection
3
3
TSEL2
DAC channel2 trigger selection
19
3
WAVE1
DAC channel1 noise/triangle wave generation enable
6
2
WAVE2
DAC channel2 noise/triangle wave generation enable
22
2
DHR12L1
DHR12L1
channel1 12-bit left aligned data holding register
0xC
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding register
0x18
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit left-aligned data
4
12
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DACC2DHR
DAC channel2 12-bit left-aligned data
20
12
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding register
0x14
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit right-aligned data
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DACC2DHR
DAC channel2 12-bit right-aligned data
16
12
DHR8R1
DHR8R1
channel1 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding register
0x1C
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 8-bit right-aligned data
0
8
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DACC2DHR
DAC channel2 8-bit right-aligned data
8
8
DOR1
DOR1
channel1 data output register
0x2C
32
read-only
n
0x0
0x0
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
channel2 data output register
0x30
32
read-only
n
0x0
0x0
DACC2DOR
DAC channel2 data output
0
12
SR
SR
status register
0x34
32
read-write
n
0x0
0x0
DMAUDR1
DAC channel1 DMA underrun flag
13
1
DMAUDR2
DAC channel2 DMA underrun flag
29
1
SWTRIGR
SWTRIGR
software trigger register
0x4
32
write-only
n
0x0
0x0
SWTRIG1
DAC channel1 software trigger
0
1
SWTRIG2
DAC channel2 software trigger
1
1
DAC2
Digital-to-analog converter 1
DAC
0x0
0x0
0x400
registers
n
TIM6_DACUNDER
TIM6 global and DAC12 underrun interrupts
54
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
BOFF1
DAC channel1 output buffer disable
1
1
BOFF2
DAC channel2 output buffer disable
17
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN2
DAC channel2 DMA enable
28
1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt enable
13
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt enable
29
1
EN1
DAC channel1 enable
0
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude selector
8
4
MAMP2
DAC channel2 mask/amplitude selector
24
4
TEN1
DAC channel1 trigger enable
2
1
TEN2
DAC channel2 trigger enable
18
1
TSEL1
DAC channel1 trigger selection
3
3
TSEL2
DAC channel2 trigger selection
19
3
WAVE1
DAC channel1 noise/triangle wave generation enable
6
2
WAVE2
DAC channel2 noise/triangle wave generation enable
22
2
DHR12L1
DHR12L1
channel1 12-bit left aligned data holding register
0xC
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding register
0x18
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit left-aligned data
4
12
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DACC2DHR
DAC channel2 12-bit left-aligned data
20
12
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding register
0x14
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit right-aligned data
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DACC2DHR
DAC channel2 12-bit right-aligned data
16
12
DHR8R1
DHR8R1
channel1 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding register
0x1C
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 8-bit right-aligned data
0
8
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DACC2DHR
DAC channel2 8-bit right-aligned data
8
8
DOR1
DOR1
channel1 data output register
0x2C
32
read-only
n
0x0
0x0
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
channel2 data output register
0x30
32
read-only
n
0x0
0x0
DACC2DOR
DAC channel2 data output
0
12
SR
SR
status register
0x34
32
read-write
n
0x0
0x0
DMAUDR1
DAC channel1 DMA underrun flag
13
1
DMAUDR2
DAC channel2 DMA underrun flag
29
1
SWTRIGR
SWTRIGR
software trigger register
0x4
32
write-only
n
0x0
0x0
SWTRIG1
DAC channel1 software trigger
0
1
SWTRIG2
DAC channel2 software trigger
1
1
DBGMCU
Debug support
DBGMCU
0x0
0x0
0x400
registers
n
APB1FZ
APB1FZ
APB Low Freeze Register
0x8
32
read-write
n
0x0
0x0
DBG_CAN_STOP
Debug CAN stopped when core is halted
25
1
DBG_IWDG_STOP
Debug Independent Wachdog stopped when Core is halted
12
1
DBG_RTC_STOP
Debug RTC stopped when Core is halted
10
1
DBG_TIM12_STOP
Debug Timer 12 stopped when Core is halted
6
1
DBG_TIM13_STOP
Debug Timer 13 stopped when Core is halted
7
1
DBG_TIM18_STOP
Debug Timer 18 stopped when Core is halted
9
1
DBG_TIM2_STOP
Debug Timer 2 stopped when Core is halted
0
1
DBG_TIM3_STOP
Debug Timer 3 stopped when Core is halted
1
1
DBG_TIM4_STOP
Debug Timer 4 stopped when Core is halted
2
1
DBG_TIM5_STOP
Debug Timer 5 stopped when Core is halted
3
1
DBG_TIM6_STOP
Debug Timer 6 stopped when Core is halted
4
1
DBG_TIM7_STOP
Debug Timer 7 stopped when Core is halted
5
1
DBG_TIMER14_STOP
Debug Timer 14 stopped when Core is halted
8
1
DBG_WWDG_STOP
Debug Window Wachdog stopped when Core is halted
11
1
I2C1_SMBUS_TIMEOUT
SMBUS timeout mode stopped when Core is halted
21
1
I2C2_SMBUS_TIMEOUT
SMBUS timeout mode stopped when Core is halted
22
1
APB2FZ
APB2FZ
APB High Freeze Register
0xC
32
read-write
n
0x0
0x0
DBG_TIM15_STOP
Debug Timer 15 stopped when Core is halted
2
1
DBG_TIM16_STOP
Debug Timer 16 stopped when Core is halted
3
1
DBG_TIM17_STO
Debug Timer 17 stopped when Core is halted
4
1
DBG_TIM19_STOP
Debug Timer 19 stopped when Core is halted
5
1
CR
CR
Debug MCU Configuration Register
0x4
32
read-write
n
0x0
0x0
DBG_SLEEP
Debug Sleep mode
0
1
DBG_STANDBY
Debug Standby Mode
2
1
DBG_STOP
Debug Stop Mode
1
1
TRACE_IOEN
Trace pin assignment control
5
1
TRACE_MODE
Trace pin assignment control
6
2
IDCODE
IDCODE
MCU Device ID Code Register
0x0
32
read-only
n
0x0
0x0
DEV_ID
Device Identifier
0
12
REV_ID
Revision Identifier
16
16
DMA1
DMA controller 1
DMA
0x0
0x0
0x400
registers
n
DMA1_CH1
DMA1 channel 1 interrupt
11
DMA1_CH2
DMA1 channel 2 interrupt
12
DMA1_CH3
DMA1 channel 3 interrupt
13
DMA1_CH4
DMA1 channel 4 interrupt
14
DMA1_CH5
DMA1 channel 5 interrupt
15
DMA1_CH6
DMA1 channel 6 interrupt
16
DMA1_CH7
DMA1 channel 7interrupt
17
CCR1
CCR1
DMA channel configuration register (DMA_CCR)
0x8
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR2
CCR2
DMA channel configuration register (DMA_CCR)
0x1C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR3
CCR3
DMA channel configuration register (DMA_CCR)
0x30
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR4
CCR4
DMA channel configuration register (DMA_CCR)
0x44
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR5
CCR5
DMA channel configuration register (DMA_CCR)
0x58
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR6
CCR6
DMA channel configuration register (DMA_CCR)
0x6C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR7
CCR7
DMA channel configuration register (DMA_CCR)
0x80
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half Transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel Priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CMAR1
CMAR1
DMA channel 1 memory address register
0x14
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR2
CMAR2
DMA channel 2 memory address register
0x28
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR3
CMAR3
DMA channel 3 memory address register
0x3C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR4
CMAR4
DMA channel 4 memory address register
0x50
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR5
CMAR5
DMA channel 5 memory address register
0x64
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR6
CMAR6
DMA channel 6 memory address register
0x78
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR7
CMAR7
DMA channel 7 memory address register
0x8C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CNDTR1
CNDTR1
DMA channel 1 number of data register
0xC
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR2
CNDTR2
DMA channel 2 number of data register
0x20
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR3
CNDTR3
DMA channel 3 number of data register
0x34
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR4
CNDTR4
DMA channel 4 number of data register
0x48
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR5
CNDTR5
DMA channel 5 number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR6
CNDTR6
DMA channel 6 number of data register
0x70
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR7
CNDTR7
DMA channel 7 number of data register
0x84
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CPAR1
CPAR1
DMA channel 1 peripheral address register
0x10
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR2
CPAR2
DMA channel 2 peripheral address register
0x24
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR3
CPAR3
DMA channel 3 peripheral address register
0x38
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR4
CPAR4
DMA channel 4 peripheral address register
0x4C
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR5
CPAR5
DMA channel 5 peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR6
CPAR6
DMA channel 6 peripheral address register
0x74
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR7
CPAR7
DMA channel 7 peripheral address register
0x88
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
IFCR
IFCR
DMA interrupt flag clear register (DMA_IFCR)
0x4
32
write-only
n
0x0
0x0
CGIF1
Channel 1 Global interrupt clear
0
1
CGIF2
Channel 2 Global interrupt clear
4
1
CGIF3
Channel 3 Global interrupt clear
8
1
CGIF4
Channel 4 Global interrupt clear
12
1
CGIF5
Channel 5 Global interrupt clear
16
1
CGIF6
Channel 6 Global interrupt clear
20
1
CGIF7
Channel 7 Global interrupt clear
24
1
CHTIF1
Channel 1 Half Transfer clear
2
1
CHTIF2
Channel 2 Half Transfer clear
6
1
CHTIF3
Channel 3 Half Transfer clear
10
1
CHTIF4
Channel 4 Half Transfer clear
14
1
CHTIF5
Channel 5 Half Transfer clear
18
1
CHTIF6
Channel 6 Half Transfer clear
22
1
CHTIF7
Channel 7 Half Transfer clear
26
1
CTCIF1
Channel 1 Transfer Complete clear
1
1
CTCIF2
Channel 2 Transfer Complete clear
5
1
CTCIF3
Channel 3 Transfer Complete clear
9
1
CTCIF4
Channel 4 Transfer Complete clear
13
1
CTCIF5
Channel 5 Transfer Complete clear
17
1
CTCIF6
Channel 6 Transfer Complete clear
21
1
CTCIF7
Channel 7 Transfer Complete clear
25
1
CTEIF1
Channel 1 Transfer Error clear
3
1
CTEIF2
Channel 2 Transfer Error clear
7
1
CTEIF3
Channel 3 Transfer Error clear
11
1
CTEIF4
Channel 4 Transfer Error clear
15
1
CTEIF5
Channel 5 Transfer Error clear
19
1
CTEIF6
Channel 6 Transfer Error clear
23
1
CTEIF7
Channel 7 Transfer Error clear
27
1
ISR
ISR
DMA interrupt status register (DMA_ISR)
0x0
32
read-only
n
0x0
0x0
GIF1
Channel 1 Global interrupt flag
0
1
GIF2
Channel 2 Global interrupt flag
4
1
GIF3
Channel 3 Global interrupt flag
8
1
GIF4
Channel 4 Global interrupt flag
12
1
GIF5
Channel 5 Global interrupt flag
16
1
GIF6
Channel 6 Global interrupt flag
20
1
GIF7
Channel 7 Global interrupt flag
24
1
HTIF1
Channel 1 Half Transfer Complete flag
2
1
HTIF2
Channel 2 Half Transfer Complete flag
6
1
HTIF3
Channel 3 Half Transfer Complete flag
10
1
HTIF4
Channel 4 Half Transfer Complete flag
14
1
HTIF5
Channel 5 Half Transfer Complete flag
18
1
HTIF6
Channel 6 Half Transfer Complete flag
22
1
HTIF7
Channel 7 Half Transfer Complete flag
26
1
TCIF1
Channel 1 Transfer Complete flag
1
1
TCIF2
Channel 2 Transfer Complete flag
5
1
TCIF3
Channel 3 Transfer Complete flag
9
1
TCIF4
Channel 4 Transfer Complete flag
13
1
TCIF5
Channel 5 Transfer Complete flag
17
1
TCIF6
Channel 6 Transfer Complete flag
21
1
TCIF7
Channel 7 Transfer Complete flag
25
1
TEIF1
Channel 1 Transfer Error flag
3
1
TEIF2
Channel 2 Transfer Error flag
7
1
TEIF3
Channel 3 Transfer Error flag
11
1
TEIF4
Channel 4 Transfer Error flag
15
1
TEIF5
Channel 5 Transfer Error flag
19
1
TEIF6
Channel 6 Transfer Error flag
23
1
TEIF7
Channel 7 Transfer Error flag
27
1
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
TAMP_STAMP
Tamper and TimeStamp interrupts
2
EXTI0
EXTI Line0 interrupt
6
EXTI1
EXTI Line3 interrupt
7
EXTI2_TSC
EXTI Line2 and Touch sensing interrupts
8
EXTI3
EXTI Line3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
EXTI9_5
EXTI Line5 to Line9 interrupts
23
I2C1_EV_EXTI23
I2C1 event interrupt and EXTI Line23 interrupt
31
USART1_EXTI25
USART1 global interrupt and EXTI Line 25 interrupt
37
USART2_EXTI26
USART2 global interrupt and EXTI Line 26 interrupt
38
USART3_EXTI28
USART3 global interrupt and EXTI Line 28 interrupt
39
EXTI15_10
EXTI Line15 to Line10 interrupts
40
UART4_EXTI34
UART4 global and EXTI Line 34 interrupts
52
UART5_EXTI35
UART5 global and EXTI Line 35 interrupts
53
USB_WKUP_EXTI
USB wakeup from Suspend and EXTI Line 18
76
EMR1
EMR1
Event mask register
0x4
32
read-write
n
0x0
0x0
MR0
Event Mask on line 0
0
1
MR1
Event Mask on line 1
1
1
MR10
Event Mask on line 10
10
1
MR11
Event Mask on line 11
11
1
MR12
Event Mask on line 12
12
1
MR13
Event Mask on line 13
13
1
MR14
Event Mask on line 14
14
1
MR15
Event Mask on line 15
15
1
MR16
Event Mask on line 16
16
1
MR17
Event Mask on line 17
17
1
MR18
Event Mask on line 18
18
1
MR19
Event Mask on line 19
19
1
MR2
Event Mask on line 2
2
1
MR20
Event Mask on line 20
20
1
MR21
Event Mask on line 21
21
1
MR22
Event Mask on line 22
22
1
MR23
Event Mask on line 23
23
1
MR24
Event Mask on line 24
24
1
MR25
Event Mask on line 25
25
1
MR26
Event Mask on line 26
26
1
MR27
Event Mask on line 27
27
1
MR28
Event Mask on line 28
28
1
MR29
Event Mask on line 29
29
1
MR3
Event Mask on line 3
3
1
MR30
Event Mask on line 30
30
1
MR31
Event Mask on line 31
31
1
MR4
Event Mask on line 4
4
1
MR5
Event Mask on line 5
5
1
MR6
Event Mask on line 6
6
1
MR7
Event Mask on line 7
7
1
MR8
Event Mask on line 8
8
1
MR9
Event Mask on line 9
9
1
EMR2
EMR2
Event mask register
0x1C
32
read-write
n
0x0
0x0
MR32
Event mask on external/internal line 32
0
1
MR33
Event mask on external/internal line 33
1
1
MR34
Event mask on external/internal line 34
2
1
MR35
Event mask on external/internal line 35
3
1
FTSR1
FTSR1
Falling Trigger selection register
0xC
32
read-write
n
0x0
0x0
TR0
Falling trigger event configuration of line 0
0
1
TR1
Falling trigger event configuration of line 1
1
1
TR10
Falling trigger event configuration of line 10
10
1
TR11
Falling trigger event configuration of line 11
11
1
TR12
Falling trigger event configuration of line 12
12
1
TR13
Falling trigger event configuration of line 13
13
1
TR14
Falling trigger event configuration of line 14
14
1
TR15
Falling trigger event configuration of line 15
15
1
TR16
Falling trigger event configuration of line 16
16
1
TR17
Falling trigger event configuration of line 17
17
1
TR18
Falling trigger event configuration of line 18
18
1
TR19
Falling trigger event configuration of line 19
19
1
TR2
Falling trigger event configuration of line 2
2
1
TR20
Falling trigger event configuration of line 20
20
1
TR21
Falling trigger event configuration of line 21
21
1
TR22
Falling trigger event configuration of line 22
22
1
TR29
Falling trigger event configuration of line 29
29
1
TR3
Falling trigger event configuration of line 3
3
1
TR30
Falling trigger event configuration of line 30.
30
1
TR31
Falling trigger event configuration of line 31
31
1
TR4
Falling trigger event configuration of line 4
4
1
TR5
Falling trigger event configuration of line 5
5
1
TR6
Falling trigger event configuration of line 6
6
1
TR7
Falling trigger event configuration of line 7
7
1
TR8
Falling trigger event configuration of line 8
8
1
TR9
Falling trigger event configuration of line 9
9
1
FTSR2
FTSR2
Falling Trigger selection register
0x24
32
read-write
n
0x0
0x0
TR32
Falling trigger event configuration bit of line 32
0
1
TR33
Falling trigger event configuration bit of line 33
1
1
IMR1
IMR1
Interrupt mask register
0x0
32
read-write
n
0x0
0x0
MR0
Interrupt Mask on line 0
0
1
MR1
Interrupt Mask on line 1
1
1
MR10
Interrupt Mask on line 10
10
1
MR11
Interrupt Mask on line 11
11
1
MR12
Interrupt Mask on line 12
12
1
MR13
Interrupt Mask on line 13
13
1
MR14
Interrupt Mask on line 14
14
1
MR15
Interrupt Mask on line 15
15
1
MR16
Interrupt Mask on line 16
16
1
MR17
Interrupt Mask on line 17
17
1
MR18
Interrupt Mask on line 18
18
1
MR19
Interrupt Mask on line 19
19
1
MR2
Interrupt Mask on line 2
2
1
MR20
Interrupt Mask on line 20
20
1
MR21
Interrupt Mask on line 21
21
1
MR22
Interrupt Mask on line 22
22
1
MR23
Interrupt Mask on line 23
23
1
MR24
Interrupt Mask on line 24
24
1
MR25
Interrupt Mask on line 25
25
1
MR26
Interrupt Mask on line 26
26
1
MR27
Interrupt Mask on line 27
27
1
MR28
Interrupt Mask on line 28
28
1
MR29
Interrupt Mask on line 29
29
1
MR3
Interrupt Mask on line 3
3
1
MR30
Interrupt Mask on line 30
30
1
MR31
Interrupt Mask on line 31
31
1
MR4
Interrupt Mask on line 4
4
1
MR5
Interrupt Mask on line 5
5
1
MR6
Interrupt Mask on line 6
6
1
MR7
Interrupt Mask on line 7
7
1
MR8
Interrupt Mask on line 8
8
1
MR9
Interrupt Mask on line 9
9
1
IMR2
IMR2
Interrupt mask register
0x18
32
read-write
n
0x0
0x0
MR32
Interrupt Mask on external/internal line 32
0
1
MR33
Interrupt Mask on external/internal line 33
1
1
MR34
Interrupt Mask on external/internal line 34
2
1
MR35
Interrupt Mask on external/internal line 35
3
1
PR1
PR1
Pending register
0x14
32
read-write
n
0x0
0x0
PR0
Pending bit 0
0
1
PR1
Pending bit 1
1
1
PR10
Pending bit 10
10
1
PR11
Pending bit 11
11
1
PR12
Pending bit 12
12
1
PR13
Pending bit 13
13
1
PR14
Pending bit 14
14
1
PR15
Pending bit 15
15
1
PR16
Pending bit 16
16
1
PR17
Pending bit 17
17
1
PR18
Pending bit 18
18
1
PR19
Pending bit 19
19
1
PR2
Pending bit 2
2
1
PR20
Pending bit 20
20
1
PR21
Pending bit 21
21
1
PR22
Pending bit 22
22
1
PR29
Pending bit 29
29
1
PR3
Pending bit 3
3
1
PR30
Pending bit 30
30
1
PR31
Pending bit 31
31
1
PR4
Pending bit 4
4
1
PR5
Pending bit 5
5
1
PR6
Pending bit 6
6
1
PR7
Pending bit 7
7
1
PR8
Pending bit 8
8
1
PR9
Pending bit 9
9
1
PR2
PR2
Pending register
0x2C
32
read-write
n
0x0
0x0
PR32
Pending bit on line 32
0
1
PR33
Pending bit on line 33
1
1
RTSR1
RTSR1
Rising Trigger selection register
0x8
32
read-write
n
0x0
0x0
TR0
Rising trigger event configuration of line 0
0
1
TR1
Rising trigger event configuration of line 1
1
1
TR10
Rising trigger event configuration of line 10
10
1
TR11
Rising trigger event configuration of line 11
11
1
TR12
Rising trigger event configuration of line 12
12
1
TR13
Rising trigger event configuration of line 13
13
1
TR14
Rising trigger event configuration of line 14
14
1
TR15
Rising trigger event configuration of line 15
15
1
TR16
Rising trigger event configuration of line 16
16
1
TR17
Rising trigger event configuration of line 17
17
1
TR18
Rising trigger event configuration of line 18
18
1
TR19
Rising trigger event configuration of line 19
19
1
TR2
Rising trigger event configuration of line 2
2
1
TR20
Rising trigger event configuration of line 20
20
1
TR21
Rising trigger event configuration of line 21
21
1
TR22
Rising trigger event configuration of line 22
22
1
TR29
Rising trigger event configuration of line 29
29
1
TR3
Rising trigger event configuration of line 3
3
1
TR30
Rising trigger event configuration of line 30
30
1
TR31
Rising trigger event configuration of line 31
31
1
TR4
Rising trigger event configuration of line 4
4
1
TR5
Rising trigger event configuration of line 5
5
1
TR6
Rising trigger event configuration of line 6
6
1
TR7
Rising trigger event configuration of line 7
7
1
TR8
Rising trigger event configuration of line 8
8
1
TR9
Rising trigger event configuration of line 9
9
1
RTSR2
RTSR2
Rising Trigger selection register
0x20
32
read-write
n
0x0
0x0
TR32
Rising trigger event configuration bit of line 32
0
1
TR33
Rising trigger event configuration bit of line 33
1
1
SWIER1
SWIER1
Software interrupt event register
0x10
32
read-write
n
0x0
0x0
SWIER0
Software Interrupt on line 0
0
1
SWIER1
Software Interrupt on line 1
1
1
SWIER10
Software Interrupt on line 10
10
1
SWIER11
Software Interrupt on line 11
11
1
SWIER12
Software Interrupt on line 12
12
1
SWIER13
Software Interrupt on line 13
13
1
SWIER14
Software Interrupt on line 14
14
1
SWIER15
Software Interrupt on line 15
15
1
SWIER16
Software Interrupt on line 16
16
1
SWIER17
Software Interrupt on line 17
17
1
SWIER18
Software Interrupt on line 18
18
1
SWIER19
Software Interrupt on line 19
19
1
SWIER2
Software Interrupt on line 2
2
1
SWIER20
Software Interrupt on line 20
20
1
SWIER21
Software Interrupt on line 21
21
1
SWIER22
Software Interrupt on line 22
22
1
SWIER29
Software Interrupt on line 29
29
1
SWIER3
Software Interrupt on line 3
3
1
SWIER30
Software Interrupt on line 309
30
1
SWIER31
Software Interrupt on line 319
31
1
SWIER4
Software Interrupt on line 4
4
1
SWIER5
Software Interrupt on line 5
5
1
SWIER6
Software Interrupt on line 6
6
1
SWIER7
Software Interrupt on line 7
7
1
SWIER8
Software Interrupt on line 8
8
1
SWIER9
Software Interrupt on line 9
9
1
SWIER2
SWIER2
Software interrupt event register
0x28
32
read-write
n
0x0
0x0
SWIER32
Software interrupt on line 32
0
1
SWIER33
Software interrupt on line 33
1
1
Flash
Flash
Flash
0x0
0x0
0x400
registers
n
FLASH
Flash global interrupt
4
ACR
ACR
Flash access control register
0x0
32
read-write
n
0x0
0x0
LATENCY
LATENCY
0
3
read-write
PRFTBE
PRFTBE
4
1
read-write
PRFTBS
PRFTBS
5
1
read-only
AR
AR
Flash address register
0x14
32
write-only
n
0x0
0x0
FAR
Flash address
0
32
CR
CR
Flash control register
0x10
32
read-write
n
0x0
0x0
EOPIE
End of operation interrupt enable
12
1
ERRIE
Error interrupt enable
10
1
FORCE_OPTLOAD
Force option byte loading
13
1
LOCK
Lock
7
1
MER
Mass erase
2
1
OPTER
Option byte erase
5
1
OPTPG
Option byte programming
4
1
OPTWRE
Option bytes write enable
9
1
PER
Page erase
1
1
PG
Programming
0
1
STRT
Start
6
1
KEYR
KEYR
Flash key register
0x4
32
write-only
n
0x0
0x0
FKEYR
Flash Key
0
32
OBR
OBR
Option byte register
0x1C
32
read-only
n
0x0
0x0
BOOT1
BOOT1
12
1
Data0
Data0
16
8
Data1
Data1
24
8
LEVEL1_PROT
Level 1 protection status
1
1
LEVEL2_PROT
Level 2 protection status
2
1
nRST_STDBY
nRST_STDBY
10
1
nRST_STOP
nRST_STOP
9
1
OPTERR
Option byte error
0
1
SRAM_PARITY_CHECK
SRAM_PARITY_CHECK
14
1
VDDA_MONITOR
VDDA_MONITOR
13
1
WDG_SW
WDG_SW
8
1
OPTKEYR
OPTKEYR
Flash option key register
0x8
32
write-only
n
0x0
0x0
OPTKEYR
Option byte key
0
32
SR
SR
Flash status register
0xC
32
read-write
n
0x0
0x0
BSY
Busy
0
1
read-only
EOP
End of operation
5
1
read-write
PGERR
Programming error
2
1
read-write
WRPRT
Write protection error
4
1
read-write
WRPR
WRPR
Write protection register
0x20
32
read-only
n
0x0
0x0
WRP
Write protect
0
32
FPU
Floting point unit
FPU
0x0
0x0
0x200
registers
n
FPU
Floating point interrupt
81
CPACR
CPACR
Coprocessor Access Control Register
0x0
32
read-write
n
0x0
0x0
CP0
Access privileges for coprocessor 0
0
1
CP1
Access privileges for coprocessor 1
2
1
CP10
Access privileges for coprocessor 10
20
1
CP11
Access privileges for coprocessor 11
22
1
CP2
Access privileges for coprocessor 2
4
1
CP3
Access privileges for coprocessor 3
6
1
CP4
Access privileges for coprocessor 4
8
1
CP5
Access privileges for coprocessor 5
10
1
CP6
Access privileges for coprocessor 6
12
2
CP7
Access privileges for coprocessor 7
14
1
FPCAR
FPCAR
FP Context Address Register
0x1B0
32
read-write
n
0x0
0x0
ADDRESS
ADDRESS
3
29
FPCCR
FPCCR
FP Context Control Register
0x1AC
32
read-write
n
0x0
0x0
ASPEN
ASPEN
31
1
BFRDY
BFRDY
6
1
HFRDY
HFRDY
4
1
LSPACT
LSPACT
0
1
LSPEN
LSPEN
30
1
MMRDY
MMRDY
5
1
MONRDY
MONRDY
8
1
THREAD
THREAD
3
1
USER
USER
1
1
FPDSCR
FPDSCR
FP Default Status Control Register
0x1B4
32
read-write
n
0x0
0x0
AHP
AHP
26
1
DN
DN
25
1
FZ
FZ
24
1
RMode
RMode
22
2
MVFR0
MVFR0
Media and VFP Feature Register 0
0x1B8
32
read-only
n
0x0
0x0
A_SIMD
A_SIMD registers
0
4
Divide
Divide
16
4
Double_precision
Double_precision
8
4
FP_exception_trapping
FP exception trapping
12
4
FP_rounding_modes
FP rounding modes
28
4
Short_vectors
Short vectors
24
4
Single_precision
Single_precision
4
4
Square_root
Square root
20
4
MVFR1
MVFR1
Media and VFP Feature Register 1
0x1BC
32
read-only
n
0x0
0x0
D_NaN_mode
D_NaN mode
4
4
FP_fused_MAC
FP fused MAC
28
4
FP_HPFP
FP HPFP
24
4
FtZ_mode
FtZ mode
0
4
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
Port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y
0
1
BR1
Port x Reset bit y
1
1
BR10
Port x Reset bit y
10
1
BR11
Port x Reset bit y
11
1
BR12
Port x Reset bit y
12
1
BR13
Port x Reset bit y
13
1
BR14
Port x Reset bit y
14
1
BR15
Port x Reset bit y
15
1
BR2
Port x Reset bit y
2
1
BR3
Port x Reset bit y
3
1
BR4
Port x Reset bit y
4
1
BR5
Port x Reset bit y
5
1
BR6
Port x Reset bit y
6
1
BR7
Port x Reset bit y
7
1
BR8
Port x Reset bit y
8
1
BR9
Port x Reset bit y
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Lok Key
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
Port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y
0
1
BR1
Port x Reset bit y
1
1
BR10
Port x Reset bit y
10
1
BR11
Port x Reset bit y
11
1
BR12
Port x Reset bit y
12
1
BR13
Port x Reset bit y
13
1
BR14
Port x Reset bit y
14
1
BR15
Port x Reset bit y
15
1
BR2
Port x Reset bit y
2
1
BR3
Port x Reset bit y
3
1
BR4
Port x Reset bit y
4
1
BR5
Port x Reset bit y
5
1
BR6
Port x Reset bit y
6
1
BR7
Port x Reset bit y
7
1
BR8
Port x Reset bit y
8
1
BR9
Port x Reset bit y
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Lok Key
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bit 0
0
1
OT1
Port x configuration bit 1
1
1
OT10
Port x configuration bit 10
10
1
OT11
Port x configuration bit 11
11
1
OT12
Port x configuration bit 12
12
1
OT13
Port x configuration bit 13
13
1
OT14
Port x configuration bit 14
14
1
OT15
Port x configuration bit 15
15
1
OT2
Port x configuration bit 2
2
1
OT3
Port x configuration bit 3
3
1
OT4
Port x configuration bit 4
4
1
OT5
Port x configuration bit 5
5
1
OT6
Port x configuration bit 6
6
1
OT7
Port x configuration bit 7
7
1
OT8
Port x configuration bit 8
8
1
OT9
Port x configuration bit 9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOC
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
Port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y
0
1
BR1
Port x Reset bit y
1
1
BR10
Port x Reset bit y
10
1
BR11
Port x Reset bit y
11
1
BR12
Port x Reset bit y
12
1
BR13
Port x Reset bit y
13
1
BR14
Port x Reset bit y
14
1
BR15
Port x Reset bit y
15
1
BR2
Port x Reset bit y
2
1
BR3
Port x Reset bit y
3
1
BR4
Port x Reset bit y
4
1
BR5
Port x Reset bit y
5
1
BR6
Port x Reset bit y
6
1
BR7
Port x Reset bit y
7
1
BR8
Port x Reset bit y
8
1
BR9
Port x Reset bit y
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Lok Key
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bit 0
0
1
OT1
Port x configuration bit 1
1
1
OT10
Port x configuration bit 10
10
1
OT11
Port x configuration bit 11
11
1
OT12
Port x configuration bit 12
12
1
OT13
Port x configuration bit 13
13
1
OT14
Port x configuration bit 14
14
1
OT15
Port x configuration bit 15
15
1
OT2
Port x configuration bit 2
2
1
OT3
Port x configuration bit 3
3
1
OT4
Port x configuration bit 4
4
1
OT5
Port x configuration bit 5
5
1
OT6
Port x configuration bit 6
6
1
OT7
Port x configuration bit 7
7
1
OT8
Port x configuration bit 8
8
1
OT9
Port x configuration bit 9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOD
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
Port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y
0
1
BR1
Port x Reset bit y
1
1
BR10
Port x Reset bit y
10
1
BR11
Port x Reset bit y
11
1
BR12
Port x Reset bit y
12
1
BR13
Port x Reset bit y
13
1
BR14
Port x Reset bit y
14
1
BR15
Port x Reset bit y
15
1
BR2
Port x Reset bit y
2
1
BR3
Port x Reset bit y
3
1
BR4
Port x Reset bit y
4
1
BR5
Port x Reset bit y
5
1
BR6
Port x Reset bit y
6
1
BR7
Port x Reset bit y
7
1
BR8
Port x Reset bit y
8
1
BR9
Port x Reset bit y
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Lok Key
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bit 0
0
1
OT1
Port x configuration bit 1
1
1
OT10
Port x configuration bit 10
10
1
OT11
Port x configuration bit 11
11
1
OT12
Port x configuration bit 12
12
1
OT13
Port x configuration bit 13
13
1
OT14
Port x configuration bit 14
14
1
OT15
Port x configuration bit 15
15
1
OT2
Port x configuration bit 2
2
1
OT3
Port x configuration bit 3
3
1
OT4
Port x configuration bit 4
4
1
OT5
Port x configuration bit 5
5
1
OT6
Port x configuration bit 6
6
1
OT7
Port x configuration bit 7
7
1
OT8
Port x configuration bit 8
8
1
OT9
Port x configuration bit 9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOF
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
Port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y
0
1
BR1
Port x Reset bit y
1
1
BR10
Port x Reset bit y
10
1
BR11
Port x Reset bit y
11
1
BR12
Port x Reset bit y
12
1
BR13
Port x Reset bit y
13
1
BR14
Port x Reset bit y
14
1
BR15
Port x Reset bit y
15
1
BR2
Port x Reset bit y
2
1
BR3
Port x Reset bit y
3
1
BR4
Port x Reset bit y
4
1
BR5
Port x Reset bit y
5
1
BR6
Port x Reset bit y
6
1
BR7
Port x Reset bit y
7
1
BR8
Port x Reset bit y
8
1
BR9
Port x Reset bit y
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Lok Key
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bit 0
0
1
OT1
Port x configuration bit 1
1
1
OT10
Port x configuration bit 10
10
1
OT11
Port x configuration bit 11
11
1
OT12
Port x configuration bit 12
12
1
OT13
Port x configuration bit 13
13
1
OT14
Port x configuration bit 14
14
1
OT15
Port x configuration bit 15
15
1
OT2
Port x configuration bit 2
2
1
OT3
Port x configuration bit 3
3
1
OT4
Port x configuration bit 4
4
1
OT5
Port x configuration bit 5
5
1
OT6
Port x configuration bit 6
6
1
OT7
Port x configuration bit 7
7
1
OT8
Port x configuration bit 8
8
1
OT9
Port x configuration bit 9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
HRTIM_Common
High Resolution Timer: Common functions
HRTIM
0x0
0x0
0x80
registers
n
ADC1R
ADC1R
ADC Trigger 1 Register
0x3C
32
read-write
n
0x0
0x0
AD1EEV1
ADC trigger 1 on External Event 1
5
1
AD1EEV2
ADC trigger 1 on External Event 2
6
1
AD1EEV3
ADC trigger 1 on External Event 3
7
1
AD1EEV4
ADC trigger 1 on External Event 4
8
1
AD1EEV5
ADC trigger 1 on External Event 5
9
1
AD1MC1
ADC trigger 1 on Master Compare 1
0
1
AD1MC2
ADC trigger 1 on Master Compare 2
1
1
AD1MC3
ADC trigger 1 on Master Compare 3
2
1
AD1MC4
ADC trigger 1 on Master Compare 4
3
1
AD1MPER
ADC trigger 1 on Master Period
4
1
AD1TAC2
ADC trigger 1 on Timer A compare 2
10
1
AD1TAC3
ADC trigger 1 on Timer A compare 3
11
1
AD1TAC4
ADC trigger 1 on Timer A compare 4
12
1
AD1TAPER
ADC trigger 1 on Timer A Period
13
1
AD1TARST
ADC trigger 1 on Timer A Reset
14
1
AD1TBC2
ADC trigger 1 on Timer B compare 2
15
1
AD1TBC3
ADC trigger 1 on Timer B compare 3
16
1
AD1TBC4
ADC trigger 1 on Timer B compare 4
17
1
AD1TBPER
ADC trigger 1 on Timer B Period
18
1
AD1TBRST
ADC trigger 1 on Timer B Reset
19
1
AD1TCC2
ADC trigger 1 on Timer C compare 2
20
1
AD1TCC3
ADC trigger 1 on Timer C compare 3
21
1
AD1TCC4
ADC trigger 1 on Timer C compare 4
22
1
AD1TCPER
ADC trigger 1 on Timer C Period
23
1
AD1TDC2
ADC trigger 1 on Timer D compare 2
24
1
AD1TDC3
ADC trigger 1 on Timer D compare 3
25
1
AD1TDC4
ADC trigger 1 on Timer D compare 4
26
1
AD1TDPER
ADC trigger 1 on Timer D Period
27
1
AD1TEC2
ADC trigger 1 on Timer E compare 2
28
1
AD1TEC3
ADC trigger 1 on Timer E compare 3
29
1
AD1TEC4
ADC trigger 1 on Timer E compare 4
30
1
AD1TEPER
ADC trigger 1 on Timer E Period
31
1
ADC2R
ADC2R
ADC Trigger 2 Register
0x40
32
read-write
n
0x0
0x0
AD2EEV10
ADC trigger 2 on External Event 10
9
1
AD2EEV6
ADC trigger 2 on External Event 6
5
1
AD2EEV7
ADC trigger 2 on External Event 7
6
1
AD2EEV8
ADC trigger 2 on External Event 8
7
1
AD2EEV9
ADC trigger 2 on External Event 9
8
1
AD2MC1
ADC trigger 2 on Master Compare 1
0
1
AD2MC2
ADC trigger 2 on Master Compare 2
1
1
AD2MC3
ADC trigger 2 on Master Compare 3
2
1
AD2MC4
ADC trigger 2 on Master Compare 4
3
1
AD2MPER
ADC trigger 2 on Master Period
4
1
AD2TAC2
ADC trigger 2 on Timer A compare 2
10
1
AD2TAC3
ADC trigger 2 on Timer A compare 3
11
1
AD2TAC4
ADC trigger 2 on Timer A compare 4
12
1
AD2TAPER
ADC trigger 2 on Timer A Period
13
1
AD2TBC2
ADC trigger 2 on Timer B compare 2
14
1
AD2TBC3
ADC trigger 2 on Timer B compare 3
15
1
AD2TBC4
ADC trigger 2 on Timer B compare 4
16
1
AD2TBPER
ADC trigger 2 on Timer B Period
17
1
AD2TCC2
ADC trigger 2 on Timer C compare 2
18
1
AD2TCC3
ADC trigger 2 on Timer C compare 3
19
1
AD2TCC4
ADC trigger 2 on Timer C compare 4
20
1
AD2TCPER
ADC trigger 2 on Timer C Period
21
1
AD2TCRST
ADC trigger 2 on Timer C Reset
22
1
AD2TDC2
ADC trigger 2 on Timer D compare 2
23
1
AD2TDC3
ADC trigger 2 on Timer D compare 3
24
1
AD2TDC4
ADC trigger 2 on Timer D compare 4
25
1
AD2TDPER
ADC trigger 2 on Timer D Period
26
1
AD2TDRST
ADC trigger 2 on Timer D Reset
27
1
AD2TEC2
ADC trigger 2 on Timer E compare 2
28
1
AD2TEC3
ADC trigger 2 on Timer E compare 3
29
1
AD2TEC4
ADC trigger 2 on Timer E compare 4
30
1
AD2TERST
ADC trigger 2 on Timer E Reset
31
1
ADC3R
ADC3R
ADC Trigger 3 Register
0x44
32
read-write
n
0x0
0x0
AD1EEV1
AD1EEV1
5
1
AD1EEV2
AD1EEV2
6
1
AD1EEV3
AD1EEV3
7
1
AD1EEV4
AD1EEV4
8
1
AD1EEV5
AD1EEV5
9
1
AD1MC1
AD1MC1
0
1
AD1MC2
AD1MC2
1
1
AD1MC3
AD1MC3
2
1
AD1MC4
AD1MC4
3
1
AD1MPER
AD1MPER
4
1
AD1TAC2
AD1TAC2
10
1
AD1TAC3
AD1TAC3
11
1
AD1TAC4
AD1TAC4
12
1
AD1TAPER
AD1TAPER
13
1
AD1TARST
AD1TARST
14
1
AD1TBC2
AD1TBC2
15
1
AD1TBC3
AD1TBC3
16
1
AD1TBC4
AD1TBC4
17
1
AD1TBPER
AD1TBPER
18
1
AD1TBRST
AD1TBRST
19
1
AD1TCC2
AD1TCC2
20
1
AD1TCC3
AD1TCC3
21
1
AD1TCC4
AD1TCC4
22
1
AD1TCPER
AD1TCPER
23
1
AD1TDC2
AD1TDC2
24
1
AD1TDC3
AD1TDC3
25
1
AD1TDC4
AD1TDC4
26
1
AD1TDPER
AD1TDPER
27
1
AD1TEC2
AD1TEC2
28
1
AD1TEC3
AD1TEC3
29
1
AD1TEC4
AD1TEC4
30
1
AD1TEPER
AD1TEPER
31
1
ADC4R
ADC4R
ADC Trigger 4 Register
0x48
32
read-write
n
0x0
0x0
AD2EEV10
AD2EEV10
9
1
AD2EEV6
AD2EEV6
5
1
AD2EEV7
AD2EEV7
6
1
AD2EEV8
AD2EEV8
7
1
AD2EEV9
AD2EEV9
8
1
AD2MC1
AD2MC1
0
1
AD2MC2
AD2MC2
1
1
AD2MC3
AD2MC3
2
1
AD2MC4
AD2MC4
3
1
AD2MPER
AD2MPER
4
1
AD2TAC2
AD2TAC2
10
1
AD2TAC3
AD2TAC3
11
1
AD2TAC4
AD2TAC4
12
1
AD2TAPER
AD2TAPER
13
1
AD2TBC2
AD2TBC2
14
1
AD2TBC3
AD2TBC3
15
1
AD2TBC4
AD2TBC4
16
1
AD2TBPER
AD2TBPER
17
1
AD2TCC2
AD2TCC2
18
1
AD2TCC3
AD2TCC3
19
1
AD2TCC4
AD2TCC4
20
1
AD2TCPER
AD2TCPER
21
1
AD2TCRST
AD2TCRST
22
1
AD2TDC2
AD2TDC2
23
1
AD2TDC3
AD2TDC3
24
1
AD2TDC4
AD2TDC4
25
1
AD2TDPER
AD2TDPER
26
1
AD2TDRST
AD2TDRST
27
1
AD2TEC2
AD2TEC2
28
1
AD2TEC3
AD2TEC3
29
1
AD2TEC4
AD2TEC4
30
1
AD2TERST
AD2TERST
31
1
BDMADR
BDMADR
Burst DMA Data Register
0x60
32
read-write
n
0x0
0x0
BDMADR
Burst DMA Data register
0
32
BDMUPDR
BDMUPDR
BDMUPDR
0x58
32
read-write
n
0x0
0x0
MCMP1
MCMP1
6
1
MCMP2
MCMP2
7
1
MCMP3
MCMP3
8
1
MCMP4
MCMP4
9
1
MCNT
MCNT
3
1
MCR
MCR
0
1
MDIER
MDIER
2
1
MICR
MICR
1
1
MPER
MPER
4
1
MREP
MREP
5
1
BDTxUPR
BDTxUPR
Burst DMA Timerx update Register
0x5C
32
read-write
n
0x0
0x0
TIMxCHPR
HRTIM_CHPxR register update enable
18
1
TIMxCMP1
HRTIM_CMP1xR register update enable
6
1
TIMxCMP2
HRTIM_CMP2xR register update enable
7
1
TIMxCMP3
HRTIM_CMP3xR register update enable
8
1
TIMxCMP4
HRTIM_CMP4xR register update enable
9
1
TIMxCNT
HRTIM_CNTxR register update enable
3
1
TIMxCR
HRTIM_TIMxCR register update enable
0
1
TIMxDIER
HRTIM_TIMxDIER register update enable
2
1
TIMxEEFR1
HRTIM_EEFxR1 register update enable
15
1
TIMxEEFR2
HRTIM_EEFxR2 register update enable
16
1
TIMxFLTR
HRTIM_FLTxR register update enable
20
1
TIMxICR
HRTIM_TIMxICR register update enable
1
1
TIMxOUTR
HRTIM_OUTxR register update enable
19
1
TIMxPER
HRTIM_PERxR register update enable
4
1
TIMxREP
HRTIM_REPxR register update enable
5
1
TIMxRST1R
HRTIM_RST1xR register update enable
12
1
TIMxRST2R
HRTIM_RST2xR register update enable
14
1
TIMxRSTR
HRTIM_RSTxR register update enable
17
1
TIMxSET1R
HRTIM_SET1xR register update enable
11
1
TIMxSET2R
HRTIM_SET2xR register update enable
13
1
TIMx_DTxR
HRTIM_DTxR register update enable
10
1
BMCMPR6
BMCMPR6
BMCMPR6
0x28
32
read-write
n
0x0
0x0
BMCMP
BMCMP
0
16
BMCR
BMCR
Burst Mode Control Register
0x20
32
read-write
n
0x0
0x0
BMCLK
Burst Mode Clock source
2
4
BME
Burst Mode enable
0
1
BMOM
Burst Mode operating mode
1
1
BMPREN
Burst Mode Preload Enable
10
1
BMPRSC
Burst Mode Prescaler
6
4
BMSTAT
Burst Mode Status
31
1
MTBM
Master Timer Burst Mode
16
1
TABM
Timer A Burst Mode
17
1
TBBM
Timer B Burst Mode
18
1
TCBM
Timer C Burst Mode
19
1
TDBM
Timer D Burst Mode
20
1
TEBM
Timer E Burst Mode
21
1
BMPER
BMPER
Burst Mode Period Register
0x2C
32
read-write
n
0x0
0x0
BMPER
Burst mode Period
0
16
BMTRG
BMTRG
BMTRG
0x24
32
read-write
n
0x0
0x0
MSTCMP1
MSTCMP1
3
1
MSTCMP2
MSTCMP2
4
1
MSTCMP3
MSTCMP3
5
1
MSTCMP4
MSTCMP4
6
1
MSTREP
MSTREP
2
1
MSTRST
MSTRST
1
1
OCHPEV
OCHPEV
31
1
SW
SW
0
1
TACMP1
TACMP1
9
1
TACMP2
TACMP2
10
1
TAREP
TAREP
8
1
TARST
TARST
7
1
TBCMP1
TBCMP1
13
1
TBCMP2
TBCMP2
14
1
TBREP
TBREP
12
1
TBRST
TBRST
11
1
TCCMP1
TCCMP1
17
1
TCCMP2
TCCMP2
18
1
TCREP
TCREP
16
1
TCRST
TCRST
15
1
TDCMP1
TDCMP1
21
1
TDCMP2
TDCMP2
22
1
TDREP
TDREP
20
1
TDRST
TDRST
19
1
TECMP1
TECMP1
25
1
TECMP2
TECMP2
26
1
TEREP
TEREP
24
1
TERST
TERST
23
1
CR1
CR1
Control Register 1
0x0
32
read-write
n
0x0
0x0
AD1USRC
ADC Trigger 1 Update Source
16
3
AD2USRC
ADC Trigger 2 Update Source
19
3
AD3USRC
ADC Trigger 3 Update Source
22
3
AD4USRC
ADC Trigger 4 Update Source
25
3
MUDIS
Master Update Disable
0
1
TAUDIS
Timer A Update Disable
1
1
TBUDIS
Timer B Update Disable
2
1
TCUDIS
Timer C Update Disable
3
1
TDUDIS
Timer D Update Disable
4
1
TEUDIS
Timer E Update Disable
5
1
CR2
CR2
Control Register 2
0x4
32
read-write
n
0x0
0x0
MRST
Master Counter software reset
8
1
MSWU
Master Timer Software update
0
1
TARST
Timer A counter software reset
9
1
TASWU
Timer A Software update
1
1
TBRST
Timer B counter software reset
10
1
TBSWU
Timer B Software Update
2
1
TCRST
Timer C counter software reset
11
1
TCSWU
Timer C Software Update
3
1
TDRST
Timer D counter software reset
12
1
TDSWU
Timer D Software Update
4
1
TERST
Timer E counter software reset
13
1
TESWU
Timer E Software Update
5
1
DISR
DISR
DISR
0x18
32
read-write
n
0x0
0x0
TA1ODIS
TA1ODIS
0
1
TA2ODIS
TA2ODIS
1
1
TB1ODIS
TB1ODIS
2
1
TB2ODIS
TB2ODIS
3
1
TC1ODIS
TC1ODIS
4
1
TC2ODIS
TC2ODIS
5
1
TD1ODIS
TD1ODIS
6
1
TD2ODIS
TD2ODIS
7
1
TE1ODIS
TE1ODIS
8
1
TE2ODIS
TE2ODIS
9
1
DLLCR
DLLCR
DLL Control Register
0x4C
32
read-write
n
0x0
0x0
CAL
DLL Calibration Start
0
1
CALEN
DLL Calibration Enable
1
1
CALRTE
DLL Calibration rate
2
2
EECR1
EECR1
Timer External Event Control Register 1
0x30
32
read-write
n
0x0
0x0
EE1FAST
External Event 1 Fast mode
5
1
EE1POL
External Event 1 Polarity
2
1
EE1SNS
External Event 1 Sensitivity
3
2
EE1SRC
External Event 1 Source
0
2
EE2FAST
External Event 2 Fast mode
11
1
EE2POL
External Event 2 Polarity
8
1
EE2SNS
External Event 2 Sensitivity
9
2
EE2SRC
External Event 2 Source
6
2
EE3FAST
External Event 3 Fast mode
17
1
EE3POL
External Event 3 Polarity
14
1
EE3SNS
External Event 3 Sensitivity
15
2
EE3SRC
External Event 3 Source
12
2
EE4FAST
External Event 4 Fast mode
23
1
EE4POL
External Event 4 Polarity
20
1
EE4SNS
External Event 4 Sensitivity
21
2
EE4SRC
External Event 4 Source
18
2
EE5FAST
External Event 5 Fast mode
29
1
EE5POL
External Event 5 Polarity
26
1
EE5SNS
External Event 5 Sensitivity
27
2
EE5SRC
External Event 5 Source
24
2
EECR2
EECR2
Timer External Event Control Register 2
0x34
32
read-write
n
0x0
0x0
EE10POL
External Event 10 Polarity
26
1
EE10SNS
External Event 10 Sensitivity
27
2
EE10SRC
External Event 10 Source
24
2
EE6POL
External Event 6 Polarity
2
1
EE6SNS
External Event 6 Sensitivity
3
2
EE6SRC
External Event 6 Source
0
2
EE7POL
External Event 7 Polarity
8
1
EE7SNS
External Event 7 Sensitivity
9
2
EE7SRC
External Event 7 Source
6
2
EE8POL
External Event 8 Polarity
14
1
EE8SNS
External Event 8 Sensitivity
15
2
EE8SRC
External Event 8 Source
12
2
EE9POL
External Event 9 Polarity
20
1
EE9SNS
External Event 9 Sensitivity
21
2
EE9SRC
External Event 9 Source
18
2
EECR3
EECR3
Timer External Event Control Register 3
0x38
32
read-write
n
0x0
0x0
EE10POL
EE10POL
26
1
EE10SNS
EE10SNS
27
2
EE10SRC
EE10SRC
24
2
EE6POL
EE6POL
2
1
EE6SNS
Reserved
3
2
EE6SRC
EE6SRC
0
2
EE7POL
EE7POL
8
1
EE7SNS
EE7SNS
9
2
EE7SRC
EE7SRC
6
2
EE8POL
EE8POL
14
1
EE8SNS
EE8SNS
15
2
EE8SRC
EE8SRC
12
2
EE9POL
EE9POL
20
1
EE9SNS
EE9SNS
21
2
EE9SRC
EE9SRC
18
2
FLTINR1
FLTINR1
HRTIM Fault Input Register 1
0x50
32
read-write
n
0x0
0x0
FLT1E
FLT1E
0
1
FLT1F
FLT1F
3
4
FLT1LCK
FLT1LCK
7
1
FLT1P
FLT1P
1
1
FLT1SRC
FLT1SRC
2
1
FLT2E
FLT2E
8
1
FLT2F
FLT2F
11
4
FLT2LCK
FLT2LCK
15
1
FLT2P
FLT2P
9
1
FLT2SRC
FLT2SRC
10
1
FLT3E
FLT3E
16
1
FLT3F
FLT3F
19
4
FLT3LCK
FLT3LCK
23
1
FLT3P
FLT3P
17
1
FLT3SRC
FLT3SRC
18
1
FLT4E
FLT4E
24
1
FLT4F
FLT4F
27
4
FLT4LCK
FLT4LCK
31
1
FLT4P
FLT4P
25
1
FLT4SRC
FLT4SRC
26
1
FLTINR2
FLTINR2
HRTIM Fault Input Register 2
0x54
32
read-write
n
0x0
0x0
FLT5E
FLT5E
0
1
FLT5F
FLT5F
3
4
FLT5LCK
FLT5LCK
7
1
FLT5P
FLT5P
1
1
FLT5SRC
FLT5SRC
2
1
FLTSD
FLTSD
24
2
ICR
ICR
Interrupt Clear Register
0xC
32
read-write
n
0x0
0x0
BMPERC
Burst mode period flag Clear
17
1
write-only
DLLRDYC
DLL Ready Interrupt flag Clear
16
1
write-only
FLT1C
Fault 1 Interrupt Flag Clear
0
1
write-only
FLT2C
Fault 2 Interrupt Flag Clear
1
1
write-only
FLT3C
Fault 3 Interrupt Flag Clear
2
1
write-only
FLT4C
Fault 4 Interrupt Flag Clear
3
1
write-only
FLT5C
Fault 5 Interrupt Flag Clear
4
1
write-only
SYSFLTC
System Fault Interrupt Flag Clear
5
1
read-write
IER
IER
Interrupt Enable Register
0x10
32
read-write
n
0x0
0x0
BMPERIE
Burst mode period Interrupt Enable
17
1
DLLRDYIE
DLL Ready Interrupt Enable
16
1
FLT1IE
Fault 1 Interrupt Enable
0
1
FLT2IE
Fault 2 Interrupt Enable
1
1
FLT3IE
Fault 3 Interrupt Enable
2
1
FLT4IE
Fault 4 Interrupt Enable
3
1
FLT5IE
Fault 5 Interrupt Enable
4
1
SYSFLTE
System Fault Interrupt Enable
5
1
ISR
ISR
Interrupt Status Register
0x8
32
read-write
n
0x0
0x0
BMPER
Burst mode Period Interrupt Flag
17
1
read-only
DLLRDY
DLL Ready Interrupt Flag
16
1
read-only
FLT1
Fault 1 Interrupt Flag
0
1
read-only
FLT2
Fault 2 Interrupt Flag
1
1
read-only
FLT3
Fault 3 Interrupt Flag
2
1
read-only
FLT4
Fault 4 Interrupt Flag
3
1
read-only
FLT5
Fault 5 Interrupt Flag
4
1
read-only
SYSFLT
System Fault Interrupt Flag
5
1
read-write
ODSR
ODSR
Output Disable Status Register
0x1C
32
read-only
n
0x0
0x0
TA1ODS
Timer A Output 1 disable status
0
1
TA2ODS
Timer A Output 2 disable status
1
1
TB1ODS
Timer B Output 1 disable status
2
1
TB2ODS
Timer B Output 2 disable status
3
1
TC1ODS
Timer C Output 1 disable status
4
1
TC2ODS
Timer C Output 2 disable status
5
1
TD1ODS
Timer D Output 1 disable status
6
1
TD2ODS
Timer D Output 2 disable status
7
1
TE1ODS
Timer E Output 1 disable status
8
1
TE2ODS
Timer E Output 2 disable status
9
1
OENR
OENR
Output Enable Register
0x14
32
write-only
n
0x0
0x0
TA1OEN
Timer A Output 1 Enable
0
1
TA2OEN
Timer A Output 2 Enable
1
1
TB1OEN
Timer B Output 1 Enable
2
1
TB2OEN
Timer B Output 2 Enable
3
1
TC1OEN
Timer C Output 1 Enable
4
1
TC2OEN
Timer C Output 2 Enable
5
1
TD1OEN
Timer D Output 1 Enable
6
1
TD2OEN
Timer D Output 2 Enable
7
1
TE1OEN
Timer E Output 1 Enable
8
1
TE2OEN
Timer E Output 2 Enable
9
1
HRTIM_Master
High Resolution Timer: Master Timers
HRTIM
0x0
0x0
0x80
registers
n
MCMP1R
MCMP1R
Master Timer Compare 1 Register
0x1C
32
read-write
n
0x0
0x0
MCMP1
Master Timer Compare 1 value
0
16
MCMP2R
MCMP2R
Master Timer Compare 2 Register
0x24
32
read-write
n
0x0
0x0
MCMP2
Master Timer Compare 2 value
0
16
MCMP3R
MCMP3R
Master Timer Compare 3 Register
0x28
32
read-write
n
0x0
0x0
MCMP3
Master Timer Compare 3 value
0
16
MCMP4R
MCMP4R
Master Timer Compare 4 Register
0x2C
32
read-write
n
0x0
0x0
MCMP4
Master Timer Compare 4 value
0
16
MCNTR
MCNTR
Master Timer Counter Register
0x10
32
read-write
n
0x0
0x0
MCNT
Counter value
0
16
MCR
MCR
Master Timer Control Register
0x0
32
read-write
n
0x0
0x0
BRSTDMA
Burst DMA Update
30
2
CK_PSC
HRTIM Master Clock prescaler
0
3
CONT
Master Continuous mode
3
1
DACSYNC
AC Synchronization
25
2
HALF
Half mode enable
5
1
MCEN
Master Counter enable
16
1
MREPU
Master Timer Repetition update
29
1
PREEN
Preload enable
27
1
RETRIG
Master Re-triggerable mode
4
1
SYNCRSTM
Synchronization Resets Master
10
1
SYNCSTRTM
Synchronization Starts Master
11
1
SYNC_IN
ynchronization input
8
2
SYNC_OUT
Synchronization output
12
2
SYNC_SRC
Synchronization source
14
2
TACEN
Timer A counter enable
17
1
TBCEN
Timer B counter enable
18
1
TCCEN
Timer C counter enable
19
1
TDCEN
Timer D counter enable
20
1
TECEN
Timer E counter enable
21
1
MDIER4
MDIER4
MDIER4
0xC
32
read-write
n
0x0
0x0
MCMP1DE
MCMP1DE
16
1
MCMP1IE
MCMP1IE
0
1
MCMP2DE
MCMP2DE
17
1
MCMP2IE
MCMP2IE
1
1
MCMP3DE
MCMP3DE
18
1
MCMP3IE
MCMP3IE
2
1
MCMP4DE
MCMP4DE
19
1
MCMP4IE
MCMP4IE
3
1
MREPDE
MREPDE
20
1
MREPIE
MREPIE
4
1
MUPDDE
MUPDDE
22
1
MUPDIE
MUPDIE
6
1
SYNCDE
SYNCDE
21
1
SYNCIE
SYNCIE
5
1
MICR
MICR
Master Timer Interrupt Clear Register
0x8
32
write-only
n
0x0
0x0
MCMP1C
Master Compare 1 Interrupt flag clear
0
1
MCMP2C
Master Compare 2 Interrupt flag clear
1
1
MCMP3C
Master Compare 3 Interrupt flag clear
2
1
MCMP4C
Master Compare 4 Interrupt flag clear
3
1
MREPC
Repetition Interrupt flag clear
4
1
MUPDC
Master update Interrupt flag clear
6
1
SYNCC
Sync Input Interrupt flag clear
5
1
MISR
MISR
Master Timer Interrupt Status Register
0x4
32
read-only
n
0x0
0x0
MCMP1
Master Compare 1 Interrupt Flag
0
1
MCMP2
Master Compare 2 Interrupt Flag
1
1
MCMP3
Master Compare 3 Interrupt Flag
2
1
MCMP4
Master Compare 4 Interrupt Flag
3
1
MREP
Master Repetition Interrupt Flag
4
1
MUPD
Master Update Interrupt Flag
6
1
SYNC
Sync Input Interrupt Flag
5
1
MPER
MPER
Master Timer Period Register
0x14
32
read-write
n
0x0
0x0
MPER
Master Timer Period value
0
16
MREP
MREP
Master Timer Repetition Register
0x18
32
read-write
n
0x0
0x0
MREP
Master Timer Repetition counter value
0
8
HRTIM_TIMA
High Resolution Timer: TIMA
HRTIM
0x0
0x0
0x80
registers
n
CHPAR
CHPAR
Timerx Chopper Register
0x58
32
read-write
n
0x0
0x0
CHPDTY
Timerx chopper duty cycle value
4
3
CHPFRQ
Timerx carrier frequency value
0
4
STRTPW
STRTPW
7
4
CMP1AR
CMP1AR
Timerx Compare 1 Register
0x1C
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
CMP1CAR
CMP1CAR
Timerx Compare 1 Compound Register
0x20
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
REPx
Timerx Repetition value (aliased from HRTIM_REPx register)
16
8
CMP2AR
CMP2AR
Timerx Compare 2 Register
0x24
32
read-write
n
0x0
0x0
CMP2x
Timerx Compare 2 value
0
16
CMP3AR
CMP3AR
Timerx Compare 3 Register
0x28
32
read-write
n
0x0
0x0
CMP3x
Timerx Compare 3 value
0
16
CMP4AR
CMP4AR
Timerx Compare 4 Register
0x2C
32
read-write
n
0x0
0x0
CMP4x
Timerx Compare 4 value
0
16
CNTAR
CNTAR
Timerx Counter Register
0x10
32
read-write
n
0x0
0x0
CNTx
Timerx Counter value
0
16
CPT1ACR
CPT1ACR
Timerx Capture 2 Control Register
0x5C
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT1AR
CPT1AR
Timerx Capture 1 Register
0x30
32
read-only
n
0x0
0x0
CPT1x
Timerx Capture 1 value
0
16
CPT2ACR
CPT2ACR
CPT2xCR
0x60
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT2AR
CPT2AR
Timerx Capture 2 Register
0x34
32
read-only
n
0x0
0x0
CPT2x
Timerx Capture 2 value
0
16
DTAR
DTAR
Timerx Deadtime Register
0x38
32
read-write
n
0x0
0x0
DTFLKx
Deadtime Falling Lock
31
1
DTFSLKx
Deadtime Falling Sign Lock
30
1
DTFx
Deadtime Falling value
16
9
DTPRSC
Deadtime Prescaler
10
3
DTRLKx
Deadtime Rising Lock
15
1
DTRSLKx
Deadtime Rising Sign Lock
14
1
DTRx
Deadtime Rising value
0
9
SDTFx
Sign Deadtime Falling value
25
1
SDTRx
Sign Deadtime Rising value
9
1
EEFAR1
EEFAR1
Timerx External Event Filtering Register 1
0x4C
32
read-write
n
0x0
0x0
EE1FLTR
External Event 1 filter
1
4
EE1LTCH
External Event 1 latch
0
1
EE2FLTR
External Event 2 filter
7
4
EE2LTCH
External Event 2 latch
6
1
EE3FLTR
External Event 3 filter
13
4
EE3LTCH
External Event 3 latch
12
1
EE4FLTR
External Event 4 filter
19
4
EE4LTCH
External Event 4 latch
18
1
EE5FLTR
External Event 5 filter
25
4
EE5LTCH
External Event 5 latch
24
1
EEFAR2
EEFAR2
Timerx External Event Filtering Register 2
0x50
32
read-write
n
0x0
0x0
EE10FLTR
External Event 10 filter
25
4
EE10LTCH
External Event 10 latch
24
1
EE6FLTR
External Event 6 filter
1
4
EE6LTCH
External Event 6 latch
0
1
EE7FLTR
External Event 7 filter
7
4
EE7LTCH
External Event 7 latch
6
1
EE8FLTR
External Event 8 filter
13
4
EE8LTCH
External Event 8 latch
12
1
EE9FLTR
External Event 9 filter
19
4
EE9LTCH
External Event 9 latch
18
1
FLTAR
FLTAR
Timerx Fault Register
0x68
32
read-write
n
0x0
0x0
FLT1EN
Fault 1 enable
0
1
FLT2EN
Fault 2 enable
1
1
FLT3EN
Fault 3 enable
2
1
FLT4EN
Fault 4 enable
3
1
FLT5EN
Fault 5 enable
4
1
FLTLCK
Fault sources Lock
31
1
OUTAR
OUTAR
Timerx Output Register
0x64
32
read-write
n
0x0
0x0
CHP1
Output 1 Chopper enable
6
1
CHP2
Output 2 Chopper enable
22
1
DIDL1
Output 1 Deadtime upon burst mode Idle entry
7
1
DIDL2
Output 2 Deadtime upon burst mode Idle entry
23
1
DLYPRT
Delayed Protection
10
3
DLYPRTEN
Delayed Protection Enable
9
1
DTEN
Deadtime enable
8
1
FAULT1
Output 1 Fault state
4
2
FAULT2
Output 2 Fault state
20
2
IDLEM1
Output 1 Idle mode
2
1
IDLEM2
Output 2 Idle mode
18
1
IDLES1
Output 1 Idle State
3
1
IDLES2
Output 2 Idle State
19
1
POL1
Output 1 polarity
1
1
POL2
Output 2 polarity
17
1
PERAR
PERAR
Timerx Period Register
0x14
32
read-write
n
0x0
0x0
PERx
Timerx Period value
0
16
REPAR
REPAR
Timerx Repetition Register
0x18
32
read-write
n
0x0
0x0
REPx
Timerx Repetition counter value
0
8
RSTA1R
RSTA1R
Timerx Output1 Reset Register
0x40
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTA2R
RSTA2R
Timerx Output2 Reset Register
0x48
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTAR
RSTAR
TimerA Reset Register
0x54
32
read-write
n
0x0
0x0
CMP2
Timer A compare 2 reset
2
1
CMP4
Timer A compare 4 reset
3
1
EXTEVNT1
External Event 1
9
1
EXTEVNT10
External Event 10
18
1
EXTEVNT2
External Event 2
10
1
EXTEVNT3
External Event 3
11
1
EXTEVNT4
External Event 4
12
1
EXTEVNT5
External Event 5
13
1
EXTEVNT6
External Event 6
14
1
EXTEVNT7
External Event 7
15
1
EXTEVNT8
External Event 8
16
1
EXTEVNT9
External Event 9
17
1
MSTCMP1
Master compare 1
5
1
MSTCMP2
Master compare 2
6
1
MSTCMP3
Master compare 3
7
1
MSTCMP4
Master compare 4
8
1
MSTPER
Master timer Period
4
1
TIMBCMP1
Timer B Compare 1
19
1
TIMBCMP2
Timer B Compare 2
20
1
TIMBCMP4
Timer B Compare 4
21
1
TIMCCMP1
Timer C Compare 1
22
1
TIMCCMP2
Timer C Compare 2
23
1
TIMCCMP4
Timer C Compare 4
24
1
TIMDCMP1
Timer D Compare 1
25
1
TIMDCMP2
Timer D Compare 2
26
1
TIMDCMP4
Timer D Compare 4
27
1
TIMECMP1
Timer E Compare 1
28
1
TIMECMP2
Timer E Compare 2
29
1
TIMECMP4
Timer E Compare 4
30
1
UPDT
Timer A Update reset
1
1
SETA1R
SETA1R
Timerx Output1 Set Register
0x3C
32
read-write
n
0x0
0x0
CMP1
Timer A compare 1
3
1
CMP2
Timer A compare 2
4
1
CMP3
Timer A compare 3
5
1
CMP4
Timer A compare 4
6
1
EXTEVNT1
External Event 1
21
1
EXTEVNT10
External Event 10
30
1
EXTEVNT2
External Event 2
22
1
EXTEVNT3
External Event 3
23
1
EXTEVNT4
External Event 4
24
1
EXTEVNT5
External Event 5
25
1
EXTEVNT6
External Event 6
26
1
EXTEVNT7
External Event 7
27
1
EXTEVNT8
External Event 8
28
1
EXTEVNT9
External Event 9
29
1
MSTCMP1
Master Compare 1
8
1
MSTCMP2
Master Compare 2
9
1
MSTCMP3
Master Compare 3
10
1
MSTCMP4
Master Compare 4
11
1
MSTPER
Master Period
7
1
PER
Timer A Period
2
1
RESYNC
Timer A resynchronizaton
1
1
SST
Software Set trigger
0
1
TIMEVNT1
Timer Event 1
12
1
TIMEVNT2
Timer Event 2
13
1
TIMEVNT3
Timer Event 3
14
1
TIMEVNT4
Timer Event 4
15
1
TIMEVNT5
Timer Event 5
16
1
TIMEVNT6
Timer Event 6
17
1
TIMEVNT7
Timer Event 7
18
1
TIMEVNT8
Timer Event 8
19
1
TIMEVNT9
Timer Event 9
20
1
UPDATE
Registers update (transfer preload to active)
31
1
SETA2R
SETA2R
Timerx Output2 Set Register
0x44
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SST
SST
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
TIMACR
TIMACR
Timerx Control Register
0x0
32
read-write
n
0x0
0x0
CK_PSCx
HRTIM Timer x Clock prescaler
0
3
CONT
Continuous mode
3
1
DACSYNC
AC Synchronization
25
2
DELCMP2
Delayed CMP2 mode
12
2
DELCMP4
Delayed CMP4 mode
14
2
HALF
Half mode enable
5
1
MSTU
Master Timer update
24
1
PREEN
Preload enable
27
1
PSHPLL
Push-Pull mode enable
6
1
RETRIG
Re-triggerable mode
4
1
SYNCRSTx
Synchronization Resets Timer x
10
1
SYNCSTRTx
Synchronization Starts Timer x
11
1
TBU
TBU
20
1
TCU
TCU
21
1
TDU
TDU
22
1
TEU
TEU
23
1
TxREPU
Timer x Repetition update
17
1
TxRSTU
Timerx reset update
18
1
UPDGAT
Update Gating
28
4
TIMADIER5
TIMADIER5
TIMxDIER5
0xC
32
read-write
n
0x0
0x0
CMP1DE
CMP1DE
16
1
CMP1IE
CMP1IE
0
1
CMP2DE
CMP2DE
17
1
CMP2IE
CMP2IE
1
1
CMP3DE
CMP3DE
18
1
CMP3IE
CMP3IE
2
1
CMP4DE
CMP4DE
19
1
CMP4IE
CMP4IE
3
1
CPT1DE
CPT1DE
23
1
CPT1IE
CPT1IE
7
1
CPT2DE
CPT2DE
24
1
CPT2IE
CPT2IE
8
1
DLYPRTDE
DLYPRTDE
30
1
DLYPRTIE
DLYPRTIE
14
1
REPDE
REPDE
20
1
REPIE
REPIE
4
1
RSTDE
RSTDE
29
1
RSTIE
RSTIE
13
1
RSTx1DE
RSTx1DE
26
1
RSTx1IE
RSTx1IE
10
1
RSTx2DE
RSTx2DE
28
1
RSTx2IE
RSTx2IE
12
1
SET1xDE
SET1xDE
25
1
SET1xIE
SET1xIE
9
1
SETx2DE
SETx2DE
27
1
SETx2IE
SETx2IE
11
1
UPDDE
UPDDE
22
1
UPDIE
UPDIE
6
1
TIMAICR
TIMAICR
Timerx Interrupt Clear Register
0x8
32
write-only
n
0x0
0x0
CMP1C
Compare 1 Interrupt flag Clear
0
1
CMP2C
Compare 2 Interrupt flag Clear
1
1
CMP3C
Compare 3 Interrupt flag Clear
2
1
CMP4C
Compare 4 Interrupt flag Clear
3
1
CPT1C
Capture1 Interrupt flag Clear
7
1
CPT2C
Capture2 Interrupt flag Clear
8
1
DLYPRTC
Delayed Protection Flag Clear
14
1
REPC
Repetition Interrupt flag Clear
4
1
RSTC
Reset Interrupt flag Clear
13
1
RSTx1C
Output 1 Reset flag Clear
10
1
RSTx2C
Output 2 Reset flag Clear
12
1
SET1xC
Output 1 Set flag Clear
9
1
SET2xC
Output 2 Set flag Clear
11
1
UPDC
Update Interrupt flag Clear
6
1
TIMAISR
TIMAISR
Timerx Interrupt Status Register
0x4
32
read-only
n
0x0
0x0
CMP1
Compare 1 Interrupt Flag
0
1
CMP2
Compare 2 Interrupt Flag
1
1
CMP3
Compare 3 Interrupt Flag
2
1
CMP4
Compare 4 Interrupt Flag
3
1
CPPSTAT
Current Push Pull Status
16
1
CPT1
Capture1 Interrupt Flag
7
1
CPT2
Capture2 Interrupt Flag
8
1
DLYPRT
Delayed Protection Flag
14
1
IPPSTAT
Idle Push Pull Status
17
1
O1STAT
Output 1 State
18
1
O2STAT
Output 2 State
19
1
REP
Repetition Interrupt Flag
4
1
RST
Reset Interrupt Flag
13
1
RSTx1
Output 1 Reset Interrupt Flag
10
1
RSTx2
Output 2 Reset Interrupt Flag
12
1
SETx1
Output 1 Set Interrupt Flag
9
1
SETx2
Output 2 Set Interrupt Flag
11
1
UPD
Update Interrupt Flag
6
1
HRTIM_TIMB
High Resolution Timer: TIMB
HRTIM
0x0
0x0
0x80
registers
n
CHPBR
CHPBR
Timerx Chopper Register
0x58
32
read-write
n
0x0
0x0
CHPDTY
Timerx chopper duty cycle value
4
3
CHPFRQ
Timerx carrier frequency value
0
4
STRTPW
STRTPW
7
4
CMP1BR
CMP1BR
Timerx Compare 1 Register
0x1C
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
CMP1CBR
CMP1CBR
Timerx Compare 1 Compound Register
0x20
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
REPx
Timerx Repetition value (aliased from HRTIM_REPx register)
16
8
CMP2BR
CMP2BR
Timerx Compare 2 Register
0x24
32
read-write
n
0x0
0x0
CMP2x
Timerx Compare 2 value
0
16
CMP3BR
CMP3BR
Timerx Compare 3 Register
0x28
32
read-write
n
0x0
0x0
CMP3x
Timerx Compare 3 value
0
16
CMP4BR
CMP4BR
Timerx Compare 4 Register
0x2C
32
read-write
n
0x0
0x0
CMP4x
Timerx Compare 4 value
0
16
CNTR
CNTR
Timerx Counter Register
0x10
32
read-write
n
0x0
0x0
CNTx
Timerx Counter value
0
16
CPT1BCR
CPT1BCR
Timerx Capture 2 Control Register
0x5C
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT1BR
CPT1BR
Timerx Capture 1 Register
0x30
32
read-only
n
0x0
0x0
CPT1x
Timerx Capture 1 value
0
16
CPT2BCR
CPT2BCR
CPT2xCR
0x60
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT2BR
CPT2BR
Timerx Capture 2 Register
0x34
32
read-only
n
0x0
0x0
CPT2x
Timerx Capture 2 value
0
16
DTBR
DTBR
Timerx Deadtime Register
0x38
32
read-write
n
0x0
0x0
DTFLKx
Deadtime Falling Lock
31
1
DTFSLKx
Deadtime Falling Sign Lock
30
1
DTFx
Deadtime Falling value
16
9
DTPRSC
Deadtime Prescaler
10
3
DTRLKx
Deadtime Rising Lock
15
1
DTRSLKx
Deadtime Rising Sign Lock
14
1
DTRx
Deadtime Rising value
0
9
SDTFx
Sign Deadtime Falling value
25
1
SDTRx
Sign Deadtime Rising value
9
1
EEFBR1
EEFBR1
Timerx External Event Filtering Register 1
0x4C
32
read-write
n
0x0
0x0
EE1FLTR
External Event 1 filter
1
4
EE1LTCH
External Event 1 latch
0
1
EE2FLTR
External Event 2 filter
7
4
EE2LTCH
External Event 2 latch
6
1
EE3FLTR
External Event 3 filter
13
4
EE3LTCH
External Event 3 latch
12
1
EE4FLTR
External Event 4 filter
19
4
EE4LTCH
External Event 4 latch
18
1
EE5FLTR
External Event 5 filter
25
4
EE5LTCH
External Event 5 latch
24
1
EEFBR2
EEFBR2
Timerx External Event Filtering Register 2
0x50
32
read-write
n
0x0
0x0
EE10FLTR
External Event 10 filter
25
4
EE10LTCH
External Event 10 latch
24
1
EE6FLTR
External Event 6 filter
1
4
EE6LTCH
External Event 6 latch
0
1
EE7FLTR
External Event 7 filter
7
4
EE7LTCH
External Event 7 latch
6
1
EE8FLTR
External Event 8 filter
13
4
EE8LTCH
External Event 8 latch
12
1
EE9FLTR
External Event 9 filter
19
4
EE9LTCH
External Event 9 latch
18
1
FLTBR
FLTBR
Timerx Fault Register
0x68
32
read-write
n
0x0
0x0
FLT1EN
Fault 1 enable
0
1
FLT2EN
Fault 2 enable
1
1
FLT3EN
Fault 3 enable
2
1
FLT4EN
Fault 4 enable
3
1
FLT5EN
Fault 5 enable
4
1
FLTLCK
Fault sources Lock
31
1
OUTBR
OUTBR
Timerx Output Register
0x64
32
read-write
n
0x0
0x0
CHP1
Output 1 Chopper enable
6
1
CHP2
Output 2 Chopper enable
22
1
DIDL1
Output 1 Deadtime upon burst mode Idle entry
7
1
DIDL2
Output 2 Deadtime upon burst mode Idle entry
23
1
DLYPRT
Delayed Protection
10
3
DLYPRTEN
Delayed Protection Enable
9
1
DTEN
Deadtime enable
8
1
FAULT1
Output 1 Fault state
4
2
FAULT2
Output 2 Fault state
20
2
IDLEM1
Output 1 Idle mode
2
1
IDLEM2
Output 2 Idle mode
18
1
IDLES1
Output 1 Idle State
3
1
IDLES2
Output 2 Idle State
19
1
POL1
Output 1 polarity
1
1
POL2
Output 2 polarity
17
1
PERBR
PERBR
Timerx Period Register
0x14
32
read-write
n
0x0
0x0
PERx
Timerx Period value
0
16
REPBR
REPBR
Timerx Repetition Register
0x18
32
read-write
n
0x0
0x0
REPx
Timerx Repetition counter value
0
8
RSTB1R
RSTB1R
Timerx Output1 Reset Register
0x40
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTB2R
RSTB2R
Timerx Output2 Reset Register
0x48
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTBR
RSTBR
TimerA Reset Register
0x54
32
read-write
n
0x0
0x0
CMP2
Timer A compare 2 reset
2
1
CMP4
Timer A compare 4 reset
3
1
EXTEVNT1
External Event 1
9
1
EXTEVNT10
External Event 10
18
1
EXTEVNT2
External Event 2
10
1
EXTEVNT3
External Event 3
11
1
EXTEVNT4
External Event 4
12
1
EXTEVNT5
External Event 5
13
1
EXTEVNT6
External Event 6
14
1
EXTEVNT7
External Event 7
15
1
EXTEVNT8
External Event 8
16
1
EXTEVNT9
External Event 9
17
1
MSTCMP1
Master compare 1
5
1
MSTCMP2
Master compare 2
6
1
MSTCMP3
Master compare 3
7
1
MSTCMP4
Master compare 4
8
1
MSTPER
Master timer Period
4
1
TIMACMP1
Timer A Compare 1
19
1
TIMACMP2
Timer A Compare 2
20
1
TIMACMP4
Timer A Compare 4
21
1
TIMCCMP1
Timer C Compare 1
22
1
TIMCCMP2
Timer C Compare 2
23
1
TIMCCMP4
Timer C Compare 4
24
1
TIMDCMP1
Timer D Compare 1
25
1
TIMDCMP2
Timer D Compare 2
26
1
TIMDCMP4
Timer D Compare 4
27
1
TIMECMP1
Timer E Compare 1
28
1
TIMECMP2
Timer E Compare 2
29
1
TIMECMP4
Timer E Compare 4
30
1
UPDT
Timer A Update reset
1
1
SETB1R
SETB1R
Timerx Output1 Set Register
0x3C
32
read-write
n
0x0
0x0
CMP1
Timer A compare 1
3
1
CMP2
Timer A compare 2
4
1
CMP3
Timer A compare 3
5
1
CMP4
Timer A compare 4
6
1
EXTEVNT1
External Event 1
21
1
EXTEVNT10
External Event 10
30
1
EXTEVNT2
External Event 2
22
1
EXTEVNT3
External Event 3
23
1
EXTEVNT4
External Event 4
24
1
EXTEVNT5
External Event 5
25
1
EXTEVNT6
External Event 6
26
1
EXTEVNT7
External Event 7
27
1
EXTEVNT8
External Event 8
28
1
EXTEVNT9
External Event 9
29
1
MSTCMP1
Master Compare 1
8
1
MSTCMP2
Master Compare 2
9
1
MSTCMP3
Master Compare 3
10
1
MSTCMP4
Master Compare 4
11
1
MSTPER
Master Period
7
1
PER
Timer A Period
2
1
RESYNC
Timer A resynchronizaton
1
1
SST
Software Set trigger
0
1
TIMEVNT1
Timer Event 1
12
1
TIMEVNT2
Timer Event 2
13
1
TIMEVNT3
Timer Event 3
14
1
TIMEVNT4
Timer Event 4
15
1
TIMEVNT5
Timer Event 5
16
1
TIMEVNT6
Timer Event 6
17
1
TIMEVNT7
Timer Event 7
18
1
TIMEVNT8
Timer Event 8
19
1
TIMEVNT9
Timer Event 9
20
1
UPDATE
Registers update (transfer preload to active)
31
1
SETB2R
SETB2R
Timerx Output2 Set Register
0x44
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SST
SST
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
TIMBCR
TIMBCR
Timerx Control Register
0x0
32
read-write
n
0x0
0x0
CK_PSCx
HRTIM Timer x Clock prescaler
0
3
CONT
Continuous mode
3
1
DACSYNC
AC Synchronization
25
2
DELCMP2
Delayed CMP2 mode
12
2
DELCMP4
Delayed CMP4 mode
14
2
HALF
Half mode enable
5
1
MSTU
Master Timer update
24
1
PREEN
Preload enable
27
1
PSHPLL
Push-Pull mode enable
6
1
RETRIG
Re-triggerable mode
4
1
SYNCRSTx
Synchronization Resets Timer x
10
1
SYNCSTRTx
Synchronization Starts Timer x
11
1
TBU
TBU
20
1
TCU
TCU
21
1
TDU
TDU
22
1
TEU
TEU
23
1
TxREPU
Timer x Repetition update
17
1
TxRSTU
Timerx reset update
18
1
UPDGAT
Update Gating
28
4
TIMBDIER5
TIMBDIER5
TIMxDIER5
0xC
32
read-write
n
0x0
0x0
CMP1DE
CMP1DE
16
1
CMP1IE
CMP1IE
0
1
CMP2DE
CMP2DE
17
1
CMP2IE
CMP2IE
1
1
CMP3DE
CMP3DE
18
1
CMP3IE
CMP3IE
2
1
CMP4DE
CMP4DE
19
1
CMP4IE
CMP4IE
3
1
CPT1DE
CPT1DE
23
1
CPT1IE
CPT1IE
7
1
CPT2DE
CPT2DE
24
1
CPT2IE
CPT2IE
8
1
DLYPRTDE
DLYPRTDE
30
1
DLYPRTIE
DLYPRTIE
14
1
REPDE
REPDE
20
1
REPIE
REPIE
4
1
RSTDE
RSTDE
29
1
RSTIE
RSTIE
13
1
RSTx1DE
RSTx1DE
26
1
RSTx1IE
RSTx1IE
10
1
RSTx2DE
RSTx2DE
28
1
RSTx2IE
RSTx2IE
12
1
SET1xDE
SET1xDE
25
1
SET1xIE
SET1xIE
9
1
SETx2DE
SETx2DE
27
1
SETx2IE
SETx2IE
11
1
UPDDE
UPDDE
22
1
UPDIE
UPDIE
6
1
TIMBICR
TIMBICR
Timerx Interrupt Clear Register
0x8
32
write-only
n
0x0
0x0
CMP1C
Compare 1 Interrupt flag Clear
0
1
CMP2C
Compare 2 Interrupt flag Clear
1
1
CMP3C
Compare 3 Interrupt flag Clear
2
1
CMP4C
Compare 4 Interrupt flag Clear
3
1
CPT1C
Capture1 Interrupt flag Clear
7
1
CPT2C
Capture2 Interrupt flag Clear
8
1
DLYPRTC
Delayed Protection Flag Clear
14
1
REPC
Repetition Interrupt flag Clear
4
1
RSTC
Reset Interrupt flag Clear
13
1
RSTx1C
Output 1 Reset flag Clear
10
1
RSTx2C
Output 2 Reset flag Clear
12
1
SET1xC
Output 1 Set flag Clear
9
1
SET2xC
Output 2 Set flag Clear
11
1
UPDC
Update Interrupt flag Clear
6
1
TIMBISR
TIMBISR
Timerx Interrupt Status Register
0x4
32
read-only
n
0x0
0x0
CMP1
Compare 1 Interrupt Flag
0
1
CMP2
Compare 2 Interrupt Flag
1
1
CMP3
Compare 3 Interrupt Flag
2
1
CMP4
Compare 4 Interrupt Flag
3
1
CPPSTAT
Current Push Pull Status
16
1
CPT1
Capture1 Interrupt Flag
7
1
CPT2
Capture2 Interrupt Flag
8
1
DLYPRT
Delayed Protection Flag
14
1
IPPSTAT
Idle Push Pull Status
17
1
O1STAT
Output 1 State
18
1
O2STAT
Output 2 State
19
1
REP
Repetition Interrupt Flag
4
1
RST
Reset Interrupt Flag
13
1
RSTx1
Output 1 Reset Interrupt Flag
10
1
RSTx2
Output 2 Reset Interrupt Flag
12
1
SETx1
Output 1 Set Interrupt Flag
9
1
SETx2
Output 2 Set Interrupt Flag
11
1
UPD
Update Interrupt Flag
6
1
HRTIM_TIMC
High Resolution Timer: TIMC
HRTIM
0x0
0x0
0x80
registers
n
CHPCR
CHPCR
Timerx Chopper Register
0x58
32
read-write
n
0x0
0x0
CHPDTY
Timerx chopper duty cycle value
4
3
CHPFRQ
Timerx carrier frequency value
0
4
STRTPW
STRTPW
7
4
CMP1CCR
CMP1CCR
Timerx Compare 1 Compound Register
0x20
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
REPx
Timerx Repetition value (aliased from HRTIM_REPx register)
16
8
CMP1CR
CMP1CR
Timerx Compare 1 Register
0x1C
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
CMP2CR
CMP2CR
Timerx Compare 2 Register
0x24
32
read-write
n
0x0
0x0
CMP2x
Timerx Compare 2 value
0
16
CMP3CR
CMP3CR
Timerx Compare 3 Register
0x28
32
read-write
n
0x0
0x0
CMP3x
Timerx Compare 3 value
0
16
CMP4CR
CMP4CR
Timerx Compare 4 Register
0x2C
32
read-write
n
0x0
0x0
CMP4x
Timerx Compare 4 value
0
16
CNTCR
CNTCR
Timerx Counter Register
0x10
32
read-write
n
0x0
0x0
CNTx
Timerx Counter value
0
16
CPT1CCR
CPT1CCR
Timerx Capture 2 Control Register
0x5C
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT1CR
CPT1CR
Timerx Capture 1 Register
0x30
32
read-only
n
0x0
0x0
CPT1x
Timerx Capture 1 value
0
16
CPT2CCR
CPT2CCR
CPT2xCR
0x60
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT2CR
CPT2CR
Timerx Capture 2 Register
0x34
32
read-only
n
0x0
0x0
CPT2x
Timerx Capture 2 value
0
16
DTCR
DTCR
Timerx Deadtime Register
0x38
32
read-write
n
0x0
0x0
DTFLKx
Deadtime Falling Lock
31
1
DTFSLKx
Deadtime Falling Sign Lock
30
1
DTFx
Deadtime Falling value
16
9
DTPRSC
Deadtime Prescaler
10
3
DTRLKx
Deadtime Rising Lock
15
1
DTRSLKx
Deadtime Rising Sign Lock
14
1
DTRx
Deadtime Rising value
0
9
SDTFx
Sign Deadtime Falling value
25
1
SDTRx
Sign Deadtime Rising value
9
1
EEFCR1
EEFCR1
Timerx External Event Filtering Register 1
0x4C
32
read-write
n
0x0
0x0
EE1FLTR
External Event 1 filter
1
4
EE1LTCH
External Event 1 latch
0
1
EE2FLTR
External Event 2 filter
7
4
EE2LTCH
External Event 2 latch
6
1
EE3FLTR
External Event 3 filter
13
4
EE3LTCH
External Event 3 latch
12
1
EE4FLTR
External Event 4 filter
19
4
EE4LTCH
External Event 4 latch
18
1
EE5FLTR
External Event 5 filter
25
4
EE5LTCH
External Event 5 latch
24
1
EEFCR2
EEFCR2
Timerx External Event Filtering Register 2
0x50
32
read-write
n
0x0
0x0
EE10FLTR
External Event 10 filter
25
4
EE10LTCH
External Event 10 latch
24
1
EE6FLTR
External Event 6 filter
1
4
EE6LTCH
External Event 6 latch
0
1
EE7FLTR
External Event 7 filter
7
4
EE7LTCH
External Event 7 latch
6
1
EE8FLTR
External Event 8 filter
13
4
EE8LTCH
External Event 8 latch
12
1
EE9FLTR
External Event 9 filter
19
4
EE9LTCH
External Event 9 latch
18
1
FLTCR
FLTCR
Timerx Fault Register
0x68
32
read-write
n
0x0
0x0
FLT1EN
Fault 1 enable
0
1
FLT2EN
Fault 2 enable
1
1
FLT3EN
Fault 3 enable
2
1
FLT4EN
Fault 4 enable
3
1
FLT5EN
Fault 5 enable
4
1
FLTLCK
Fault sources Lock
31
1
OUTCR
OUTCR
Timerx Output Register
0x64
32
read-write
n
0x0
0x0
CHP1
Output 1 Chopper enable
6
1
CHP2
Output 2 Chopper enable
22
1
DIDL1
Output 1 Deadtime upon burst mode Idle entry
7
1
DIDL2
Output 2 Deadtime upon burst mode Idle entry
23
1
DLYPRT
Delayed Protection
10
3
DLYPRTEN
Delayed Protection Enable
9
1
DTEN
Deadtime enable
8
1
FAULT1
Output 1 Fault state
4
2
FAULT2
Output 2 Fault state
20
2
IDLEM1
Output 1 Idle mode
2
1
IDLEM2
Output 2 Idle mode
18
1
IDLES1
Output 1 Idle State
3
1
IDLES2
Output 2 Idle State
19
1
POL1
Output 1 polarity
1
1
POL2
Output 2 polarity
17
1
PERCR
PERCR
Timerx Period Register
0x14
32
read-write
n
0x0
0x0
PERx
Timerx Period value
0
16
REPCR
REPCR
Timerx Repetition Register
0x18
32
read-write
n
0x0
0x0
REPx
Timerx Repetition counter value
0
8
RSTC1R
RSTC1R
Timerx Output1 Reset Register
0x40
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTC2R
RSTC2R
Timerx Output2 Reset Register
0x48
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTCR
RSTCR
TimerA Reset Register
0x54
32
read-write
n
0x0
0x0
CMP2
Timer A compare 2 reset
2
1
CMP4
Timer A compare 4 reset
3
1
EXTEVNT1
External Event 1
9
1
EXTEVNT10
External Event 10
18
1
EXTEVNT2
External Event 2
10
1
EXTEVNT3
External Event 3
11
1
EXTEVNT4
External Event 4
12
1
EXTEVNT5
External Event 5
13
1
EXTEVNT6
External Event 6
14
1
EXTEVNT7
External Event 7
15
1
EXTEVNT8
External Event 8
16
1
EXTEVNT9
External Event 9
17
1
MSTCMP1
Master compare 1
5
1
MSTCMP2
Master compare 2
6
1
MSTCMP3
Master compare 3
7
1
MSTCMP4
Master compare 4
8
1
MSTPER
Master timer Period
4
1
TIMACMP1
Timer A Compare 1
19
1
TIMACMP2
Timer A Compare 2
20
1
TIMACMP4
Timer A Compare 4
21
1
TIMBCMP1
Timer B Compare 1
22
1
TIMBCMP2
Timer B Compare 2
23
1
TIMBCMP4
Timer B Compare 4
24
1
TIMDCMP1
Timer D Compare 1
25
1
TIMDCMP2
Timer D Compare 2
26
1
TIMDCMP4
Timer D Compare 4
27
1
TIMECMP1
Timer E Compare 1
28
1
TIMECMP2
Timer E Compare 2
29
1
TIMECMP4
Timer E Compare 4
30
1
UPDT
Timer A Update reset
1
1
SETC1R
SETC1R
Timerx Output1 Set Register
0x3C
32
read-write
n
0x0
0x0
CMP1
Timer A compare 1
3
1
CMP2
Timer A compare 2
4
1
CMP3
Timer A compare 3
5
1
CMP4
Timer A compare 4
6
1
EXTEVNT1
External Event 1
21
1
EXTEVNT10
External Event 10
30
1
EXTEVNT2
External Event 2
22
1
EXTEVNT3
External Event 3
23
1
EXTEVNT4
External Event 4
24
1
EXTEVNT5
External Event 5
25
1
EXTEVNT6
External Event 6
26
1
EXTEVNT7
External Event 7
27
1
EXTEVNT8
External Event 8
28
1
EXTEVNT9
External Event 9
29
1
MSTCMP1
Master Compare 1
8
1
MSTCMP2
Master Compare 2
9
1
MSTCMP3
Master Compare 3
10
1
MSTCMP4
Master Compare 4
11
1
MSTPER
Master Period
7
1
PER
Timer A Period
2
1
RESYNC
Timer A resynchronizaton
1
1
SST
Software Set trigger
0
1
TIMEVNT1
Timer Event 1
12
1
TIMEVNT2
Timer Event 2
13
1
TIMEVNT3
Timer Event 3
14
1
TIMEVNT4
Timer Event 4
15
1
TIMEVNT5
Timer Event 5
16
1
TIMEVNT6
Timer Event 6
17
1
TIMEVNT7
Timer Event 7
18
1
TIMEVNT8
Timer Event 8
19
1
TIMEVNT9
Timer Event 9
20
1
UPDATE
Registers update (transfer preload to active)
31
1
SETC2R
SETC2R
Timerx Output2 Set Register
0x44
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SST
SST
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
TIMCCR
TIMCCR
Timerx Control Register
0x0
32
read-write
n
0x0
0x0
CK_PSCx
HRTIM Timer x Clock prescaler
0
3
CONT
Continuous mode
3
1
DACSYNC
AC Synchronization
25
2
DELCMP2
Delayed CMP2 mode
12
2
DELCMP4
Delayed CMP4 mode
14
2
HALF
Half mode enable
5
1
MSTU
Master Timer update
24
1
PREEN
Preload enable
27
1
PSHPLL
Push-Pull mode enable
6
1
RETRIG
Re-triggerable mode
4
1
SYNCRSTx
Synchronization Resets Timer x
10
1
SYNCSTRTx
Synchronization Starts Timer x
11
1
TBU
TBU
20
1
TCU
TCU
21
1
TDU
TDU
22
1
TEU
TEU
23
1
TxREPU
Timer x Repetition update
17
1
TxRSTU
Timerx reset update
18
1
UPDGAT
Update Gating
28
4
TIMCDIER5
TIMCDIER5
TIMxDIER5
0xC
32
read-write
n
0x0
0x0
CMP1DE
CMP1DE
16
1
CMP1IE
CMP1IE
0
1
CMP2DE
CMP2DE
17
1
CMP2IE
CMP2IE
1
1
CMP3DE
CMP3DE
18
1
CMP3IE
CMP3IE
2
1
CMP4DE
CMP4DE
19
1
CMP4IE
CMP4IE
3
1
CPT1DE
CPT1DE
23
1
CPT1IE
CPT1IE
7
1
CPT2DE
CPT2DE
24
1
CPT2IE
CPT2IE
8
1
DLYPRTDE
DLYPRTDE
30
1
DLYPRTIE
DLYPRTIE
14
1
REPDE
REPDE
20
1
REPIE
REPIE
4
1
RSTDE
RSTDE
29
1
RSTIE
RSTIE
13
1
RSTx1DE
RSTx1DE
26
1
RSTx1IE
RSTx1IE
10
1
RSTx2DE
RSTx2DE
28
1
RSTx2IE
RSTx2IE
12
1
SET1xDE
SET1xDE
25
1
SET1xIE
SET1xIE
9
1
SETx2DE
SETx2DE
27
1
SETx2IE
SETx2IE
11
1
UPDDE
UPDDE
22
1
UPDIE
UPDIE
6
1
TIMCICR
TIMCICR
Timerx Interrupt Clear Register
0x8
32
write-only
n
0x0
0x0
CMP1C
Compare 1 Interrupt flag Clear
0
1
CMP2C
Compare 2 Interrupt flag Clear
1
1
CMP3C
Compare 3 Interrupt flag Clear
2
1
CMP4C
Compare 4 Interrupt flag Clear
3
1
CPT1C
Capture1 Interrupt flag Clear
7
1
CPT2C
Capture2 Interrupt flag Clear
8
1
DLYPRTC
Delayed Protection Flag Clear
14
1
REPC
Repetition Interrupt flag Clear
4
1
RSTC
Reset Interrupt flag Clear
13
1
RSTx1C
Output 1 Reset flag Clear
10
1
RSTx2C
Output 2 Reset flag Clear
12
1
SET1xC
Output 1 Set flag Clear
9
1
SET2xC
Output 2 Set flag Clear
11
1
UPDC
Update Interrupt flag Clear
6
1
TIMCISR
TIMCISR
Timerx Interrupt Status Register
0x4
32
read-only
n
0x0
0x0
CMP1
Compare 1 Interrupt Flag
0
1
CMP2
Compare 2 Interrupt Flag
1
1
CMP3
Compare 3 Interrupt Flag
2
1
CMP4
Compare 4 Interrupt Flag
3
1
CPPSTAT
Current Push Pull Status
16
1
CPT1
Capture1 Interrupt Flag
7
1
CPT2
Capture2 Interrupt Flag
8
1
DLYPRT
Delayed Protection Flag
14
1
IPPSTAT
Idle Push Pull Status
17
1
O1STAT
Output 1 State
18
1
O2STAT
Output 2 State
19
1
REP
Repetition Interrupt Flag
4
1
RST
Reset Interrupt Flag
13
1
RSTx1
Output 1 Reset Interrupt Flag
10
1
RSTx2
Output 2 Reset Interrupt Flag
12
1
SETx1
Output 1 Set Interrupt Flag
9
1
SETx2
Output 2 Set Interrupt Flag
11
1
UPD
Update Interrupt Flag
6
1
HRTIM_TIMD
High Resolution Timer: TIMD
HRTIM
0x0
0x0
0x80
registers
n
CHPDR
CHPDR
Timerx Chopper Register
0x58
32
read-write
n
0x0
0x0
CHPDTY
Timerx chopper duty cycle value
4
3
CHPFRQ
Timerx carrier frequency value
0
4
STRTPW
STRTPW
7
4
CMP1CDR
CMP1CDR
Timerx Compare 1 Compound Register
0x20
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
REPx
Timerx Repetition value (aliased from HRTIM_REPx register)
16
8
CMP1DR
CMP1DR
Timerx Compare 1 Register
0x1C
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
CMP2DR
CMP2DR
Timerx Compare 2 Register
0x24
32
read-write
n
0x0
0x0
CMP2x
Timerx Compare 2 value
0
16
CMP3DR
CMP3DR
Timerx Compare 3 Register
0x28
32
read-write
n
0x0
0x0
CMP3x
Timerx Compare 3 value
0
16
CMP4DR
CMP4DR
Timerx Compare 4 Register
0x2C
32
read-write
n
0x0
0x0
CMP4x
Timerx Compare 4 value
0
16
CNTDR
CNTDR
Timerx Counter Register
0x10
32
read-write
n
0x0
0x0
CNTx
Timerx Counter value
0
16
CPT1DCR
CPT1DCR
Timerx Capture 2 Control Register
0x5C
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT1DR
CPT1DR
Timerx Capture 1 Register
0x30
32
read-only
n
0x0
0x0
CPT1x
Timerx Capture 1 value
0
16
CPT2DCR
CPT2DCR
CPT2xCR
0x60
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TE1RST
Timer E output 1 Reset
29
1
TE1SET
Timer E output 1 Set
28
1
TECMP1
Timer E Compare 1
30
1
TECMP2
Timer E Compare 2
31
1
UDPCPT
Update Capture
1
1
CPT2DR
CPT2DR
Timerx Capture 2 Register
0x34
32
read-only
n
0x0
0x0
CPT2x
Timerx Capture 2 value
0
16
DTDR
DTDR
Timerx Deadtime Register
0x38
32
read-write
n
0x0
0x0
DTFLKx
Deadtime Falling Lock
31
1
DTFSLKx
Deadtime Falling Sign Lock
30
1
DTFx
Deadtime Falling value
16
9
DTPRSC
Deadtime Prescaler
10
3
DTRLKx
Deadtime Rising Lock
15
1
DTRSLKx
Deadtime Rising Sign Lock
14
1
DTRx
Deadtime Rising value
0
9
SDTFx
Sign Deadtime Falling value
25
1
SDTRx
Sign Deadtime Rising value
9
1
EEFDR1
EEFDR1
Timerx External Event Filtering Register 1
0x4C
32
read-write
n
0x0
0x0
EE1FLTR
External Event 1 filter
1
4
EE1LTCH
External Event 1 latch
0
1
EE2FLTR
External Event 2 filter
7
4
EE2LTCH
External Event 2 latch
6
1
EE3FLTR
External Event 3 filter
13
4
EE3LTCH
External Event 3 latch
12
1
EE4FLTR
External Event 4 filter
19
4
EE4LTCH
External Event 4 latch
18
1
EE5FLTR
External Event 5 filter
25
4
EE5LTCH
External Event 5 latch
24
1
EEFDR2
EEFDR2
Timerx External Event Filtering Register 2
0x50
32
read-write
n
0x0
0x0
EE10FLTR
External Event 10 filter
25
4
EE10LTCH
External Event 10 latch
24
1
EE6FLTR
External Event 6 filter
1
4
EE6LTCH
External Event 6 latch
0
1
EE7FLTR
External Event 7 filter
7
4
EE7LTCH
External Event 7 latch
6
1
EE8FLTR
External Event 8 filter
13
4
EE8LTCH
External Event 8 latch
12
1
EE9FLTR
External Event 9 filter
19
4
EE9LTCH
External Event 9 latch
18
1
FLTDR
FLTDR
Timerx Fault Register
0x68
32
read-write
n
0x0
0x0
FLT1EN
Fault 1 enable
0
1
FLT2EN
Fault 2 enable
1
1
FLT3EN
Fault 3 enable
2
1
FLT4EN
Fault 4 enable
3
1
FLT5EN
Fault 5 enable
4
1
FLTLCK
Fault sources Lock
31
1
OUTDR
OUTDR
Timerx Output Register
0x64
32
read-write
n
0x0
0x0
CHP1
Output 1 Chopper enable
6
1
CHP2
Output 2 Chopper enable
22
1
DIDL1
Output 1 Deadtime upon burst mode Idle entry
7
1
DIDL2
Output 2 Deadtime upon burst mode Idle entry
23
1
DLYPRT
Delayed Protection
10
3
DLYPRTEN
Delayed Protection Enable
9
1
DTEN
Deadtime enable
8
1
FAULT1
Output 1 Fault state
4
2
FAULT2
Output 2 Fault state
20
2
IDLEM1
Output 1 Idle mode
2
1
IDLEM2
Output 2 Idle mode
18
1
IDLES1
Output 1 Idle State
3
1
IDLES2
Output 2 Idle State
19
1
POL1
Output 1 polarity
1
1
POL2
Output 2 polarity
17
1
PERDR
PERDR
Timerx Period Register
0x14
32
read-write
n
0x0
0x0
PERx
Timerx Period value
0
16
REPDR
REPDR
Timerx Repetition Register
0x18
32
read-write
n
0x0
0x0
REPx
Timerx Repetition counter value
0
8
RSTD1R
RSTD1R
Timerx Output1 Reset Register
0x40
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTD2R
RSTD2R
Timerx Output2 Reset Register
0x48
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTDR
RSTDR
TimerA Reset Register
0x54
32
read-write
n
0x0
0x0
CMP2
Timer A compare 2 reset
2
1
CMP4
Timer A compare 4 reset
3
1
EXTEVNT1
External Event 1
9
1
EXTEVNT10
External Event 10
18
1
EXTEVNT2
External Event 2
10
1
EXTEVNT3
External Event 3
11
1
EXTEVNT4
External Event 4
12
1
EXTEVNT5
External Event 5
13
1
EXTEVNT6
External Event 6
14
1
EXTEVNT7
External Event 7
15
1
EXTEVNT8
External Event 8
16
1
EXTEVNT9
External Event 9
17
1
MSTCMP1
Master compare 1
5
1
MSTCMP2
Master compare 2
6
1
MSTCMP3
Master compare 3
7
1
MSTCMP4
Master compare 4
8
1
MSTPER
Master timer Period
4
1
TIMACMP1
Timer A Compare 1
19
1
TIMACMP2
Timer A Compare 2
20
1
TIMACMP4
Timer A Compare 4
21
1
TIMBCMP1
Timer B Compare 1
22
1
TIMBCMP2
Timer B Compare 2
23
1
TIMBCMP4
Timer B Compare 4
24
1
TIMCCMP1
Timer C Compare 1
25
1
TIMCCMP2
Timer C Compare 2
26
1
TIMCCMP4
Timer C Compare 4
27
1
TIMECMP1
Timer E Compare 1
28
1
TIMECMP2
Timer E Compare 2
29
1
TIMECMP4
Timer E Compare 4
30
1
UPDT
Timer A Update reset
1
1
SETD1R
SETD1R
Timerx Output1 Set Register
0x3C
32
read-write
n
0x0
0x0
CMP1
Timer A compare 1
3
1
CMP2
Timer A compare 2
4
1
CMP3
Timer A compare 3
5
1
CMP4
Timer A compare 4
6
1
EXTEVNT1
External Event 1
21
1
EXTEVNT10
External Event 10
30
1
EXTEVNT2
External Event 2
22
1
EXTEVNT3
External Event 3
23
1
EXTEVNT4
External Event 4
24
1
EXTEVNT5
External Event 5
25
1
EXTEVNT6
External Event 6
26
1
EXTEVNT7
External Event 7
27
1
EXTEVNT8
External Event 8
28
1
EXTEVNT9
External Event 9
29
1
MSTCMP1
Master Compare 1
8
1
MSTCMP2
Master Compare 2
9
1
MSTCMP3
Master Compare 3
10
1
MSTCMP4
Master Compare 4
11
1
MSTPER
Master Period
7
1
PER
Timer A Period
2
1
RESYNC
Timer A resynchronizaton
1
1
SST
Software Set trigger
0
1
TIMEVNT1
Timer Event 1
12
1
TIMEVNT2
Timer Event 2
13
1
TIMEVNT3
Timer Event 3
14
1
TIMEVNT4
Timer Event 4
15
1
TIMEVNT5
Timer Event 5
16
1
TIMEVNT6
Timer Event 6
17
1
TIMEVNT7
Timer Event 7
18
1
TIMEVNT8
Timer Event 8
19
1
TIMEVNT9
Timer Event 9
20
1
UPDATE
Registers update (transfer preload to active)
31
1
SETD2R
SETD2R
Timerx Output2 Set Register
0x44
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SST
SST
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
TIMDCR
TIMDCR
Timerx Control Register
0x0
32
read-write
n
0x0
0x0
CK_PSCx
HRTIM Timer x Clock prescaler
0
3
CONT
Continuous mode
3
1
DACSYNC
AC Synchronization
25
2
DELCMP2
Delayed CMP2 mode
12
2
DELCMP4
Delayed CMP4 mode
14
2
HALF
Half mode enable
5
1
MSTU
Master Timer update
24
1
PREEN
Preload enable
27
1
PSHPLL
Push-Pull mode enable
6
1
RETRIG
Re-triggerable mode
4
1
SYNCRSTx
Synchronization Resets Timer x
10
1
SYNCSTRTx
Synchronization Starts Timer x
11
1
TBU
TBU
20
1
TCU
TCU
21
1
TDU
TDU
22
1
TEU
TEU
23
1
TxREPU
Timer x Repetition update
17
1
TxRSTU
Timerx reset update
18
1
UPDGAT
Update Gating
28
4
TIMDDIER5
TIMDDIER5
TIMxDIER5
0xC
32
read-write
n
0x0
0x0
CMP1DE
CMP1DE
16
1
CMP1IE
CMP1IE
0
1
CMP2DE
CMP2DE
17
1
CMP2IE
CMP2IE
1
1
CMP3DE
CMP3DE
18
1
CMP3IE
CMP3IE
2
1
CMP4DE
CMP4DE
19
1
CMP4IE
CMP4IE
3
1
CPT1DE
CPT1DE
23
1
CPT1IE
CPT1IE
7
1
CPT2DE
CPT2DE
24
1
CPT2IE
CPT2IE
8
1
DLYPRTDE
DLYPRTDE
30
1
DLYPRTIE
DLYPRTIE
14
1
REPDE
REPDE
20
1
REPIE
REPIE
4
1
RSTDE
RSTDE
29
1
RSTIE
RSTIE
13
1
RSTx1DE
RSTx1DE
26
1
RSTx1IE
RSTx1IE
10
1
RSTx2DE
RSTx2DE
28
1
RSTx2IE
RSTx2IE
12
1
SET1xDE
SET1xDE
25
1
SET1xIE
SET1xIE
9
1
SETx2DE
SETx2DE
27
1
SETx2IE
SETx2IE
11
1
UPDDE
UPDDE
22
1
UPDIE
UPDIE
6
1
TIMDICR
TIMDICR
Timerx Interrupt Clear Register
0x8
32
write-only
n
0x0
0x0
CMP1C
Compare 1 Interrupt flag Clear
0
1
CMP2C
Compare 2 Interrupt flag Clear
1
1
CMP3C
Compare 3 Interrupt flag Clear
2
1
CMP4C
Compare 4 Interrupt flag Clear
3
1
CPT1C
Capture1 Interrupt flag Clear
7
1
CPT2C
Capture2 Interrupt flag Clear
8
1
DLYPRTC
Delayed Protection Flag Clear
14
1
REPC
Repetition Interrupt flag Clear
4
1
RSTC
Reset Interrupt flag Clear
13
1
RSTx1C
Output 1 Reset flag Clear
10
1
RSTx2C
Output 2 Reset flag Clear
12
1
SET1xC
Output 1 Set flag Clear
9
1
SET2xC
Output 2 Set flag Clear
11
1
UPDC
Update Interrupt flag Clear
6
1
TIMDISR
TIMDISR
Timerx Interrupt Status Register
0x4
32
read-only
n
0x0
0x0
CMP1
Compare 1 Interrupt Flag
0
1
CMP2
Compare 2 Interrupt Flag
1
1
CMP3
Compare 3 Interrupt Flag
2
1
CMP4
Compare 4 Interrupt Flag
3
1
CPPSTAT
Current Push Pull Status
16
1
CPT1
Capture1 Interrupt Flag
7
1
CPT2
Capture2 Interrupt Flag
8
1
DLYPRT
Delayed Protection Flag
14
1
IPPSTAT
Idle Push Pull Status
17
1
O1STAT
Output 1 State
18
1
O2STAT
Output 2 State
19
1
REP
Repetition Interrupt Flag
4
1
RST
Reset Interrupt Flag
13
1
RSTx1
Output 1 Reset Interrupt Flag
10
1
RSTx2
Output 2 Reset Interrupt Flag
12
1
SETx1
Output 1 Set Interrupt Flag
9
1
SETx2
Output 2 Set Interrupt Flag
11
1
UPD
Update Interrupt Flag
6
1
HRTIM_TIME
High Resolution Timer: TIME
HRTIM
0x0
0x0
0x80
registers
n
CHPER
CHPER
Timerx Chopper Register
0x58
32
read-write
n
0x0
0x0
CHPDTY
Timerx chopper duty cycle value
4
3
CHPFRQ
Timerx carrier frequency value
0
4
STRTPW
STRTPW
7
4
CMP1CER
CMP1CER
Timerx Compare 1 Compound Register
0x20
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
REPx
Timerx Repetition value (aliased from HRTIM_REPx register)
16
8
CMP1ER
CMP1ER
Timerx Compare 1 Register
0x1C
32
read-write
n
0x0
0x0
CMP1x
Timerx Compare 1 value
0
16
CMP2ER
CMP2ER
Timerx Compare 2 Register
0x24
32
read-write
n
0x0
0x0
CMP2x
Timerx Compare 2 value
0
16
CMP3ER
CMP3ER
Timerx Compare 3 Register
0x28
32
read-write
n
0x0
0x0
CMP3x
Timerx Compare 3 value
0
16
CMP4ER
CMP4ER
Timerx Compare 4 Register
0x2C
32
read-write
n
0x0
0x0
CMP4x
Timerx Compare 4 value
0
16
CNTER
CNTER
Timerx Counter Register
0x10
32
read-write
n
0x0
0x0
CNTx
Timerx Counter value
0
16
CPT1ECR
CPT1ECR
Timerx Capture 2 Control Register
0x5C
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
UDPCPT
Update Capture
1
1
CPT1ER
CPT1ER
Timerx Capture 1 Register
0x30
32
read-only
n
0x0
0x0
CPT1x
Timerx Capture 1 value
0
16
CPT2ECR
CPT2ECR
CPT2xCR
0x60
32
read-write
n
0x0
0x0
EXEV10CPT
External Event 10 Capture
11
1
EXEV1CPT
External Event 1 Capture
2
1
EXEV2CPT
External Event 2 Capture
3
1
EXEV3CPT
External Event 3 Capture
4
1
EXEV4CPT
External Event 4 Capture
5
1
EXEV5CPT
External Event 5 Capture
6
1
EXEV6CPT
External Event 6 Capture
7
1
EXEV7CPT
External Event 7 Capture
8
1
EXEV8CPT
External Event 8 Capture
9
1
EXEV9CPT
External Event 9 Capture
10
1
SWCPT
Software Capture
0
1
TA1RST
Timer A output 1 Reset
13
1
TA1SET
Timer A output 1 Set
12
1
TACMP1
Timer A Compare 1
14
1
TACMP2
Timer A Compare 2
15
1
TB1RST
Timer B output 1 Reset
17
1
TB1SET
Timer B output 1 Set
16
1
TBCMP1
Timer B Compare 1
18
1
TBCMP2
Timer B Compare 2
19
1
TC1RST
Timer C output 1 Reset
21
1
TC1SET
Timer C output 1 Set
20
1
TCCMP1
Timer C Compare 1
22
1
TCCMP2
Timer C Compare 2
23
1
TD1RST
Timer D output 1 Reset
25
1
TD1SET
Timer D output 1 Set
24
1
TDCMP1
Timer D Compare 1
26
1
TDCMP2
Timer D Compare 2
27
1
UDPCPT
Update Capture
1
1
CPT2ER
CPT2ER
Timerx Capture 2 Register
0x34
32
read-only
n
0x0
0x0
CPT2x
Timerx Capture 2 value
0
16
DTER
DTER
Timerx Deadtime Register
0x38
32
read-write
n
0x0
0x0
DTFLKx
Deadtime Falling Lock
31
1
DTFSLKx
Deadtime Falling Sign Lock
30
1
DTFx
Deadtime Falling value
16
9
DTPRSC
Deadtime Prescaler
10
3
DTRLKx
Deadtime Rising Lock
15
1
DTRSLKx
Deadtime Rising Sign Lock
14
1
DTRx
Deadtime Rising value
0
9
SDTFx
Sign Deadtime Falling value
25
1
SDTRx
Sign Deadtime Rising value
9
1
EEFER1
EEFER1
Timerx External Event Filtering Register 1
0x4C
32
read-write
n
0x0
0x0
EE1FLTR
External Event 1 filter
1
4
EE1LTCH
External Event 1 latch
0
1
EE2FLTR
External Event 2 filter
7
4
EE2LTCH
External Event 2 latch
6
1
EE3FLTR
External Event 3 filter
13
4
EE3LTCH
External Event 3 latch
12
1
EE4FLTR
External Event 4 filter
19
4
EE4LTCH
External Event 4 latch
18
1
EE5FLTR
External Event 5 filter
25
4
EE5LTCH
External Event 5 latch
24
1
EEFER2
EEFER2
Timerx External Event Filtering Register 2
0x50
32
read-write
n
0x0
0x0
EE10FLTR
External Event 10 filter
25
4
EE10LTCH
External Event 10 latch
24
1
EE6FLTR
External Event 6 filter
1
4
EE6LTCH
External Event 6 latch
0
1
EE7FLTR
External Event 7 filter
7
4
EE7LTCH
External Event 7 latch
6
1
EE8FLTR
External Event 8 filter
13
4
EE8LTCH
External Event 8 latch
12
1
EE9FLTR
External Event 9 filter
19
4
EE9LTCH
External Event 9 latch
18
1
FLTER
FLTER
Timerx Fault Register
0x68
32
read-write
n
0x0
0x0
FLT1EN
Fault 1 enable
0
1
FLT2EN
Fault 2 enable
1
1
FLT3EN
Fault 3 enable
2
1
FLT4EN
Fault 4 enable
3
1
FLT5EN
Fault 5 enable
4
1
FLTLCK
Fault sources Lock
31
1
OUTER
OUTER
Timerx Output Register
0x64
32
read-write
n
0x0
0x0
CHP1
Output 1 Chopper enable
6
1
CHP2
Output 2 Chopper enable
22
1
DIDL1
Output 1 Deadtime upon burst mode Idle entry
7
1
DIDL2
Output 2 Deadtime upon burst mode Idle entry
23
1
DLYPRT
Delayed Protection
10
3
DLYPRTEN
Delayed Protection Enable
9
1
DTEN
Deadtime enable
8
1
FAULT1
Output 1 Fault state
4
2
FAULT2
Output 2 Fault state
20
2
IDLEM1
Output 1 Idle mode
2
1
IDLEM2
Output 2 Idle mode
18
1
IDLES1
Output 1 Idle State
3
1
IDLES2
Output 2 Idle State
19
1
POL1
Output 1 polarity
1
1
POL2
Output 2 polarity
17
1
PERER
PERER
Timerx Period Register
0x14
32
read-write
n
0x0
0x0
PERx
Timerx Period value
0
16
REPER
REPER
Timerx Repetition Register
0x18
32
read-write
n
0x0
0x0
REPx
Timerx Repetition counter value
0
8
RSTE1R
RSTE1R
Timerx Output1 Reset Register
0x40
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTE2R
RSTE2R
Timerx Output2 Reset Register
0x48
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SRT
SRT
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
RSTER
RSTER
TimerA Reset Register
0x54
32
read-write
n
0x0
0x0
CMP2
Timer A compare 2 reset
2
1
CMP4
Timer A compare 4 reset
3
1
EXTEVNT1
External Event 1
9
1
EXTEVNT10
External Event 10
18
1
EXTEVNT2
External Event 2
10
1
EXTEVNT3
External Event 3
11
1
EXTEVNT4
External Event 4
12
1
EXTEVNT5
External Event 5
13
1
EXTEVNT6
External Event 6
14
1
EXTEVNT7
External Event 7
15
1
EXTEVNT8
External Event 8
16
1
EXTEVNT9
External Event 9
17
1
MSTCMP1
Master compare 1
5
1
MSTCMP2
Master compare 2
6
1
MSTCMP3
Master compare 3
7
1
MSTCMP4
Master compare 4
8
1
MSTPER
Master timer Period
4
1
TIMACMP1
Timer A Compare 1
19
1
TIMACMP2
Timer A Compare 2
20
1
TIMACMP4
Timer A Compare 4
21
1
TIMBCMP1
Timer B Compare 1
22
1
TIMBCMP2
Timer B Compare 2
23
1
TIMBCMP4
Timer B Compare 4
24
1
TIMCCMP1
Timer C Compare 1
25
1
TIMCCMP2
Timer C Compare 2
26
1
TIMCCMP4
Timer C Compare 4
27
1
TIMDCMP1
Timer D Compare 1
28
1
TIMDCMP2
Timer D Compare 2
29
1
TIMDCMP4
Timer D Compare 4
30
1
UPDT
Timer A Update reset
1
1
SETE1R
SETE1R
Timerx Output1 Set Register
0x3C
32
read-write
n
0x0
0x0
CMP1
Timer A compare 1
3
1
CMP2
Timer A compare 2
4
1
CMP3
Timer A compare 3
5
1
CMP4
Timer A compare 4
6
1
EXTEVNT1
External Event 1
21
1
EXTEVNT10
External Event 10
30
1
EXTEVNT2
External Event 2
22
1
EXTEVNT3
External Event 3
23
1
EXTEVNT4
External Event 4
24
1
EXTEVNT5
External Event 5
25
1
EXTEVNT6
External Event 6
26
1
EXTEVNT7
External Event 7
27
1
EXTEVNT8
External Event 8
28
1
EXTEVNT9
External Event 9
29
1
MSTCMP1
Master Compare 1
8
1
MSTCMP2
Master Compare 2
9
1
MSTCMP3
Master Compare 3
10
1
MSTCMP4
Master Compare 4
11
1
MSTPER
Master Period
7
1
PER
Timer A Period
2
1
RESYNC
Timer A resynchronizaton
1
1
SST
Software Set trigger
0
1
TIMEVNT1
Timer Event 1
12
1
TIMEVNT2
Timer Event 2
13
1
TIMEVNT3
Timer Event 3
14
1
TIMEVNT4
Timer Event 4
15
1
TIMEVNT5
Timer Event 5
16
1
TIMEVNT6
Timer Event 6
17
1
TIMEVNT7
Timer Event 7
18
1
TIMEVNT8
Timer Event 8
19
1
TIMEVNT9
Timer Event 9
20
1
UPDATE
Registers update (transfer preload to active)
31
1
SETE2R
SETE2R
Timerx Output2 Set Register
0x44
32
read-write
n
0x0
0x0
CMP1
CMP1
3
1
CMP2
CMP2
4
1
CMP3
CMP3
5
1
CMP4
CMP4
6
1
EXTEVNT1
EXTEVNT1
21
1
EXTEVNT10
EXTEVNT10
30
1
EXTEVNT2
EXTEVNT2
22
1
EXTEVNT3
EXTEVNT3
23
1
EXTEVNT4
EXTEVNT4
24
1
EXTEVNT5
EXTEVNT5
25
1
EXTEVNT6
EXTEVNT6
26
1
EXTEVNT7
EXTEVNT7
27
1
EXTEVNT8
EXTEVNT8
28
1
EXTEVNT9
EXTEVNT9
29
1
MSTCMP1
MSTCMP1
8
1
MSTCMP2
MSTCMP2
9
1
MSTCMP3
MSTCMP3
10
1
MSTCMP4
MSTCMP4
11
1
MSTPER
MSTPER
7
1
PER
PER
2
1
RESYNC
RESYNC
1
1
SST
SST
0
1
TIMEVNT1
TIMEVNT1
12
1
TIMEVNT2
TIMEVNT2
13
1
TIMEVNT3
TIMEVNT3
14
1
TIMEVNT4
TIMEVNT4
15
1
TIMEVNT5
TIMEVNT5
16
1
TIMEVNT6
TIMEVNT6
17
1
TIMEVNT7
TIMEVNT7
18
1
TIMEVNT8
TIMEVNT8
19
1
TIMEVNT9
TIMEVNT9
20
1
UPDATE
UPDATE
31
1
TIMECR
TIMECR
Timerx Control Register
0x0
32
read-write
n
0x0
0x0
CK_PSCx
HRTIM Timer x Clock prescaler
0
3
CONT
Continuous mode
3
1
DACSYNC
AC Synchronization
25
2
DELCMP2
Delayed CMP2 mode
12
2
DELCMP4
Delayed CMP4 mode
14
2
HALF
Half mode enable
5
1
MSTU
Master Timer update
24
1
PREEN
Preload enable
27
1
PSHPLL
Push-Pull mode enable
6
1
RETRIG
Re-triggerable mode
4
1
SYNCRSTx
Synchronization Resets Timer x
10
1
SYNCSTRTx
Synchronization Starts Timer x
11
1
TBU
TBU
20
1
TCU
TCU
21
1
TDU
TDU
22
1
TEU
TEU
23
1
TxREPU
Timer x Repetition update
17
1
TxRSTU
Timerx reset update
18
1
UPDGAT
Update Gating
28
4
TIMEDIER5
TIMEDIER5
TIMxDIER5
0xC
32
read-write
n
0x0
0x0
CMP1DE
CMP1DE
16
1
CMP1IE
CMP1IE
0
1
CMP2DE
CMP2DE
17
1
CMP2IE
CMP2IE
1
1
CMP3DE
CMP3DE
18
1
CMP3IE
CMP3IE
2
1
CMP4DE
CMP4DE
19
1
CMP4IE
CMP4IE
3
1
CPT1DE
CPT1DE
23
1
CPT1IE
CPT1IE
7
1
CPT2DE
CPT2DE
24
1
CPT2IE
CPT2IE
8
1
DLYPRTDE
DLYPRTDE
30
1
DLYPRTIE
DLYPRTIE
14
1
REPDE
REPDE
20
1
REPIE
REPIE
4
1
RSTDE
RSTDE
29
1
RSTIE
RSTIE
13
1
RSTx1DE
RSTx1DE
26
1
RSTx1IE
RSTx1IE
10
1
RSTx2DE
RSTx2DE
28
1
RSTx2IE
RSTx2IE
12
1
SET1xDE
SET1xDE
25
1
SET1xIE
SET1xIE
9
1
SETx2DE
SETx2DE
27
1
SETx2IE
SETx2IE
11
1
UPDDE
UPDDE
22
1
UPDIE
UPDIE
6
1
TIMEICR
TIMEICR
Timerx Interrupt Clear Register
0x8
32
write-only
n
0x0
0x0
CMP1C
Compare 1 Interrupt flag Clear
0
1
CMP2C
Compare 2 Interrupt flag Clear
1
1
CMP3C
Compare 3 Interrupt flag Clear
2
1
CMP4C
Compare 4 Interrupt flag Clear
3
1
CPT1C
Capture1 Interrupt flag Clear
7
1
CPT2C
Capture2 Interrupt flag Clear
8
1
DLYPRTC
Delayed Protection Flag Clear
14
1
REPC
Repetition Interrupt flag Clear
4
1
RSTC
Reset Interrupt flag Clear
13
1
RSTx1C
Output 1 Reset flag Clear
10
1
RSTx2C
Output 2 Reset flag Clear
12
1
SET1xC
Output 1 Set flag Clear
9
1
SET2xC
Output 2 Set flag Clear
11
1
UPDC
Update Interrupt flag Clear
6
1
TIMEISR
TIMEISR
Timerx Interrupt Status Register
0x4
32
read-only
n
0x0
0x0
CMP1
Compare 1 Interrupt Flag
0
1
CMP2
Compare 2 Interrupt Flag
1
1
CMP3
Compare 3 Interrupt Flag
2
1
CMP4
Compare 4 Interrupt Flag
3
1
CPPSTAT
Current Push Pull Status
16
1
CPT1
Capture1 Interrupt Flag
7
1
CPT2
Capture2 Interrupt Flag
8
1
DLYPRT
Delayed Protection Flag
14
1
IPPSTAT
Idle Push Pull Status
17
1
O1STAT
Output 1 State
18
1
O2STAT
Output 2 State
19
1
REP
Repetition Interrupt Flag
4
1
RST
Reset Interrupt Flag
13
1
RSTx1
Output 1 Reset Interrupt Flag
10
1
RSTx2
Output 2 Reset Interrupt Flag
12
1
SETx1
Output 1 Set Interrupt Flag
9
1
SETx2
Output 2 Set Interrupt Flag
11
1
UPD
Update Interrupt Flag
6
1
I2C1
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1_EV_EXTI23
I2C1 event interrupt and EXTI Line23 interrupt
31
I2C1_ER
I2C1 error interrupt
32
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
read-write
ALERTEN
SMBUS alert enable
22
1
read-write
ANFOFF
Analog noise filter OFF
12
1
read-write
DNF
Digital noise filter
8
4
read-write
ERRIE
Error interrupts enable
7
1
read-write
GCEN
General call enable
19
1
read-write
NACKIE
Not acknowledge received interrupt enable
4
1
read-write
NOSTRETCH
Clock stretching disable
17
1
read-write
PE
Peripheral enable
0
1
read-write
PECEN
PEC enable
23
1
read-write
RXDMAEN
DMA reception requests enable
15
1
read-write
RXIE
RX Interrupt enable
2
1
read-write
SBC
Slave byte control
16
1
read-write
SMBDEN
SMBus Device Default address enable
21
1
read-write
SMBHEN
SMBus Host address enable
20
1
read-write
STOPIE
STOP detection Interrupt enable
5
1
read-write
SWRST
Software reset
13
1
write-only
TCIE
Transfer Complete interrupt enable
6
1
read-write
TXDMAEN
DMA transmission requests enable
14
1
read-write
TXIE
TX Interrupt enable
1
1
read-write
WUPEN
Wakeup from STOP enable
18
1
read-write
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD0
Slave address bit 0 (master mode)
0
1
SADD1
Slave address bit 7:1 (master mode)
1
7
SADD8
Slave address bit 9:8 (master mode)
8
2
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OA1_0
Interface address
0
1
OA1_1
Interface address
1
7
OA1_8
Interface address
8
2
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
IWDG
Independent watchdog
IWDG
0x0
0x0
0x400
registers
n
KR
KR
Key register
0x0
32
write-only
n
0x0
0x0
KEY
Key value
0
16
PR
PR
Prescaler register
0x4
32
read-write
n
0x0
0x0
PR
Prescaler divider
0
3
RLR
RLR
Reload register
0x8
32
read-write
n
0x0
0x0
RL
Watchdog counter reload value
0
12
SR
SR
Status register
0xC
32
read-only
n
0x0
0x0
PVU
Watchdog prescaler value update
0
1
RVU
Watchdog counter reload value update
1
1
WVU
Watchdog counter window value update
2
1
WINR
WINR
Window register
0x10
32
read-write
n
0x0
0x0
WIN
Watchdog counter window value
0
12
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x1001
registers
n
IABR0
IABR0
Interrupt Active Bit Register
0x300
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x304
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR2
IABR2
Interrupt Active Bit Register
0x308
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
ICER0
ICER0
Interrupt Clear-Enable Register
0x180
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable Register
0x184
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER2
ICER2
Interrupt Clear-Enable Register
0x188
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR0
ICPR0
Interrupt Clear-Pending Register
0x280
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending Register
0x284
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR2
ICPR2
Interrupt Clear-Pending Register
0x288
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICTR
ICTR
Interrupt Controller Type Register
0x4
32
read-only
n
0x0
0x0
INTLINESNUM
Total number of interrupt lines in groups
0
4
IPR0
IPR0
Interrupt Priority Register
0x400
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x404
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x428
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x42C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x430
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x434
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x438
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR15
IPR15
Interrupt Priority Register
0x43C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR16
IPR16
Interrupt Priority Register
0x440
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR17
IPR17
Interrupt Priority Register
0x444
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR18
IPR18
Interrupt Priority Register
0x448
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR19
IPR19
Interrupt Priority Register
0x44C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x408
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR20
IPR20
Interrupt Priority Register
0x450
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x40C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x410
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x414
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x418
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x41C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x420
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x424
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
ISER0
ISER0
Interrupt Set-Enable Register
0x100
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x104
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER2
ISER2
Interrupt Set-Enable Register
0x108
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x200
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x204
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR2
ISPR2
Interrupt Set-Pending Register
0x208
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
STIR
STIR
Software Triggered Interrupt Register
0xF00
32
write-only
n
0x0
0x0
INTID
interrupt to be triggered
0
9
OPAMP
Operational amplifier
OPAMP
0x0
0x0
0x3C8
registers
n
OPAMP1_CR
OPAMP1_CR
OPAMP1 control register
0x0
32
read-write
n
0x0
0x0
CALON
Calibration mode enable
11
1
read-write
CALSEL
Calibration selection
12
2
read-write
FORCE_VP
FORCE_VP
1
1
read-write
LOCK
OPAMP 1 lock
31
1
read-write
OPAMP1_EN
OPAMP1 enable
0
1
read-write
OUTCAL
OPAMP 1 ouput status flag
30
1
read-only
PGA_GAIN
Gain in PGA mode
14
4
read-write
TCM_EN
Timer controlled Mux mode enable
7
1
read-write
TRIMOFFSETN
Offset trimming value (NMOS)
24
5
read-write
TRIMOFFSETP
Offset trimming value (PMOS)
19
5
read-write
TSTREF
TSTREF
29
1
read-write
USER_TRIM
User trimming enable
18
1
read-write
VMS_SEL
OPAMP1 inverting input secondary selection
8
1
read-write
VM_SEL
OPAMP1 inverting input selection
5
2
read-write
VPS_SEL
OPAMP1 Non inverting input secondary selection
9
2
read-write
VP_SEL
OPAMP1 Non inverting input selection
2
2
read-write
OPAMP2_CR
OPAMP2_CR
OPAMP2 control register
0x4
32
read-write
n
0x0
0x0
CALON
Calibration mode enable
11
1
read-write
CAL_SEL
Calibration selection
12
2
read-write
FORCE_VP
FORCE_VP
1
1
read-write
LOCK
OPAMP 2 lock
31
1
read-write
OPAMP2EN
OPAMP2 enable
0
1
read-write
OUTCAL
OPAMP 2 ouput status flag
30
1
read-only
PGA_GAIN
Gain in PGA mode
14
4
read-write
TCM_EN
Timer controlled Mux mode enable
7
1
read-write
TRIMOFFSETN
Offset trimming value (NMOS)
24
5
read-write
TRIMOFFSETP
Offset trimming value (PMOS)
19
5
read-write
TSTREF
TSTREF
29
1
read-write
USER_TRIM
User trimming enable
18
1
read-write
VMS_SEL
OPAMP2 inverting input secondary selection
8
1
read-write
VM_SEL
OPAMP2 inverting input selection
5
2
read-write
VPS_SEL
OPAMP2 Non inverting input secondary selection
9
2
read-write
VP_SEL
OPAMP2 Non inverting input selection
2
2
read-write
OPAMP3_CR
OPAMP3_CR
OPAMP3 control register
0x8
32
read-write
n
0x0
0x0
CALON
Calibration mode enable
11
1
read-write
CALSEL
Calibration selection
12
2
read-write
FORCE_VP
FORCE_VP
1
1
read-write
LOCK
OPAMP 3 lock
31
1
read-write
OPAMP3EN
OPAMP3 enable
0
1
read-write
OUTCAL
OPAMP 3 ouput status flag
30
1
read-only
PGA_GAIN
Gain in PGA mode
14
4
read-write
TCM_EN
Timer controlled Mux mode enable
7
1
read-write
TRIMOFFSETN
Offset trimming value (NMOS)
24
5
read-write
TRIMOFFSETP
Offset trimming value (PMOS)
19
5
read-write
TSTREF
TSTREF
29
1
read-write
USER_TRIM
User trimming enable
18
1
read-write
VMS_SEL
OPAMP3 inverting input secondary selection
8
1
read-write
VM_SEL
OPAMP3 inverting input selection
5
2
read-write
VPS_SEL
OPAMP3 Non inverting input secondary selection
9
2
read-write
VP_SEL
OPAMP3 Non inverting input selection
2
2
read-write
OPAMP4_CR
OPAMP4_CR
OPAMP4 control register
0xC
32
read-write
n
0x0
0x0
CALON
Calibration mode enable
11
1
read-write
CALSEL
Calibration selection
12
2
read-write
FORCE_VP
FORCE_VP
1
1
read-write
LOCK
OPAMP 4 lock
31
1
read-write
OPAMP4EN
OPAMP4 enable
0
1
read-write
OUTCAL
OPAMP 4 ouput status flag
30
1
read-only
PGA_GAIN
Gain in PGA mode
14
4
read-write
TCM_EN
Timer controlled Mux mode enable
7
1
read-write
TRIMOFFSETN
Offset trimming value (NMOS)
24
5
read-write
TRIMOFFSETP
Offset trimming value (PMOS)
19
5
read-write
TSTREF
TSTREF
29
1
read-write
USER_TRIM
User trimming enable
18
1
read-write
VMS_SEL
OPAMP4 inverting input secondary selection
8
1
read-write
VM_SEL
OPAMP4 inverting input selection
5
2
read-write
VPS_SEL
OPAMP4 Non inverting input secondary selection
9
2
read-write
VP_SEL
OPAMP4 Non inverting input selection
2
2
read-write
PWR
Power control
PWR
0x0
0x0
0x400
registers
n
PVD
PVD through EXTI line detection interrupt
1
CR
CR
power control register
0x0
32
read-write
n
0x0
0x0
CSBF
Clear standby flag
3
1
CWUF
Clear wakeup flag
2
1
DBP
Disable backup domain write protection
8
1
LPDS
Low-power deep sleep
0
1
PDDS
Power down deepsleep
1
1
PLS
PVD level selection
5
3
PVDE
Power voltage detector enable
4
1
CSR
CSR
power control/status register
0x4
32
read-write
n
0x0
0x0
EWUP1
Enable WKUP1 pin
8
1
read-write
EWUP2
Enable WKUP2 pin
9
1
read-write
PVDO
PVD output
2
1
read-only
SBF
Standby flag
1
1
read-only
WUF
Wakeup flag
0
1
read-only
RCC
Reset and clock control
RCC
0x0
0x0
0x400
registers
n
RCC
RCC global interrupt
5
AHBENR
AHBENR
AHB Peripheral Clock enable register (RCC_AHBENR)
0x14
32
read-write
n
0x0
0x0
ADC12EN
ADC1 and ADC2 clock enable
28
1
CRCEN
CRC clock enable
6
1
DMAEN
DMA1 clock enable
0
1
FLITFEN
FLITF clock enable
4
1
IOPAEN
I/O port A clock enable
17
1
IOPBEN
I/O port B clock enable
18
1
IOPCEN
I/O port C clock enable
19
1
IOPDEN
I/O port D clock enable
20
1
IOPFEN
I/O port F clock enable
22
1
SRAMEN
SRAM interface clock enable
2
1
TSCEN
Touch sensing controller clock enable
24
1
AHBRSTR
AHBRSTR
AHB peripheral reset register
0x28
32
read-write
n
0x0
0x0
ADC12RST
ADC1 and ADC2 reset
28
1
IOPARST
I/O port A reset
17
1
IOPBRST
I/O port B reset
18
1
IOPCRST
I/O port C reset
19
1
IOPDRST
I/O port D reset
20
1
IOPFRST
I/O port F reset
22
1
TSCRST
Touch sensing controller reset
24
1
APB1ENR
APB1ENR
APB1 peripheral clock enable register (RCC_APB1ENR)
0x1C
32
read-write
n
0x0
0x0
CANEN
CAN clock enable
25
1
DAC1EN
DAC1 interface clock enable
29
1
DAC2EN
DAC2 clock enable
26
1
I2C1EN
I2C 1 clock enable
21
1
PWREN
Power interface clock enable
28
1
TIM2EN
Timer 2 clock enable
0
1
TIM3EN
Timer 3 clock enable
1
1
TIM6EN
Timer 6 clock enable
4
1
TIM7EN
Timer 7 clock enable
5
1
USART2EN
USART 2 clock enable
17
1
USART3EN
USART 3 clock enable
18
1
WWDGEN
Window watchdog clock enable
11
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register (RCC_APB1RSTR)
0x10
32
read-write
n
0x0
0x0
CANRST
CAN reset
25
1
DAC1RST
DAC1 interface reset
29
1
DAC2RST
DAC2 interface reset
26
1
I2C1RST
I2C1 reset
21
1
PWRRST
Power interface reset
28
1
TIM2RST
Timer 2 reset
0
1
TIM3RST
Timer 3 reset
1
1
TIM6RST
Timer 6 reset
4
1
TIM7RST
Timer 7 reset
5
1
USART2RST
USART 2 reset
17
1
USART3RST
USART3 reset
18
1
USBRST
USB reset
23
1
WWDGRST
Window watchdog reset
11
1
APB2ENR
APB2ENR
APB2 peripheral clock enable register (RCC_APB2ENR)
0x18
32
read-write
n
0x0
0x0
HRTIM1EN
HRTIM1 clock enable
29
1
SPI1EN
SPI 1 clock enable
12
1
SYSCFGEN
SYSCFG clock enable
0
1
TIM15EN
TIM15 timer clock enable
16
1
TIM16EN
TIM16 timer clock enable
17
1
TIM17EN
TIM17 timer clock enable
18
1
TIM1EN
TIM1 Timer clock enable
11
1
USART1EN
USART1 clock enable
14
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register (RCC_APB2RSTR)
0xC
32
read-write
n
0x0
0x0
HRTIM1RST
HRTIM1 reset
29
1
SPI1RST
SPI 1 reset
12
1
SYSCFGRST
SYSCFG and COMP reset
0
1
TIM15RST
TIM15 timer reset
16
1
TIM16RST
TIM16 timer reset
17
1
TIM17RST
TIM17 timer reset
18
1
TIM1RST
TIM1 timer reset
11
1
USART1RST
USART1 reset
14
1
BDCR
BDCR
Backup domain control register (RCC_BDCR)
0x20
32
read-write
n
0x0
0x0
BDRST
Backup domain software reset
16
1
read-write
LSEBYP
External Low Speed oscillator bypass
2
1
read-write
LSEDRV
LSE oscillator drive capability
3
2
read-write
LSEON
External Low Speed oscillator enable
0
1
read-write
LSERDY
External Low Speed oscillator ready
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSEL
RTC clock source selection
8
2
read-write
CFGR
CFGR
Clock configuration register (RCC_CFGR)
0x4
32
read-write
n
0x0
0x0
HPRE
AHB prescaler
4
4
read-write
I2SSRC
I2S external clock source selection
23
1
read-write
MCO
Microcontroller clock output
24
3
read-write
MCOPRE
MCOPRE
28
3
read-only
PLLMUL
PLL Multiplication Factor
18
4
read-write
PLLNODIV
PLLNODIV
31
1
read-write
PLLSRC
PLL entry clock source
16
1
read-write
PLLXTPRE
HSE divider for PLL entry
17
1
read-write
PPRE1
APB Low speed prescaler (APB1)
8
3
read-write
PPRE2
APB high speed prescaler (APB2)
11
3
read-write
SW
System clock Switch
0
2
read-write
SWS
System Clock Switch Status
2
2
read-only
USBPRES
USB prescaler
22
1
read-write
CFGR2
CFGR2
Clock configuration register 2
0x2C
32
read-write
n
0x0
0x0
ADC12PRES
ADC1 and ADC2 prescaler
4
5
PREDIV
PREDIV division factor
0
4
CFGR3
CFGR3
Clock configuration register 3
0x30
32
read-write
n
0x0
0x0
HRTIM1SW
HRTIM1 clock selection
12
1
I2C1SW
I2C1 clock source selection
4
1
TIM1SW
Timer1 clock source selection
8
1
USART1SW
USART1 clock source selection
0
2
CIR
CIR
Clock interrupt register (RCC_CIR)
0x8
32
read-write
n
0x0
0x0
CSSC
Clock security system interrupt clear
23
1
write-only
CSSF
Clock Security System Interrupt flag
7
1
read-only
HSERDYC
HSE Ready Interrupt Clear
19
1
write-only
HSERDYF
HSE Ready Interrupt flag
3
1
read-only
HSERDYIE
HSE Ready Interrupt Enable
11
1
read-write
HSIRDYC
HSI Ready Interrupt Clear
18
1
write-only
HSIRDYF
HSI Ready Interrupt flag
2
1
read-only
HSIRDYIE
HSI Ready Interrupt Enable
10
1
read-write
LSERDYC
LSE Ready Interrupt Clear
17
1
write-only
LSERDYF
LSE Ready Interrupt flag
1
1
read-only
LSERDYIE
LSE Ready Interrupt Enable
9
1
read-write
LSIRDYC
LSI Ready Interrupt Clear
16
1
write-only
LSIRDYF
LSI Ready Interrupt flag
0
1
read-only
LSIRDYIE
LSI Ready Interrupt Enable
8
1
read-write
PLLRDYC
PLL Ready Interrupt Clear
20
1
write-only
PLLRDYF
PLL Ready Interrupt flag
4
1
read-only
PLLRDYIE
PLL Ready Interrupt Enable
12
1
read-write
CR
CR
Clock control register
0x0
32
read-write
n
0x0
0x0
CSSON
Clock Security System enable
19
1
read-write
HSEBYP
External High Speed clock Bypass
18
1
read-write
HSEON
External High Speed clock enable
16
1
read-write
HSERDY
External High Speed clock ready flag
17
1
read-only
HSICAL
Internal High Speed clock Calibration
8
8
read-only
HSION
Internal High Speed clock enable
0
1
read-write
HSIRDY
Internal High Speed clock ready flag
1
1
read-only
HSITRIM
Internal High Speed clock trimming
3
5
read-write
PLLON
PLL enable
24
1
read-write
PLLRDY
PLL clock ready flag
25
1
read-only
CSR
CSR
Control/status register (RCC_CSR)
0x24
32
read-write
n
0x0
0x0
IWDGRSTF
Independent watchdog reset flag
29
1
read-write
LPWRRSTF
Low-power reset flag
31
1
read-write
LSION
Internal low speed oscillator enable
0
1
read-write
LSIRDY
Internal low speed oscillator ready
1
1
read-only
OBLRSTF
Option byte loader reset flag
25
1
read-write
PINRSTF
PIN reset flag
26
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
RMVF
Remove reset flag
24
1
read-write
SFTRSTF
Software reset flag
28
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
RTC_WKUP
RTC Wakeup interrupt through the EXTI line
3
RTCAlarm
RTC alarm interrupt
41
ALRMAR
ALRMAR
alarm A register
0x1C
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm A seconds mask
7
1
MSK2
Alarm A minutes mask
15
1
MSK3
Alarm A hours mask
23
1
MSK4
Alarm A date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMASSR
ALRMASSR
alarm A sub second register
0x44
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
ALRMBR
ALRMBR
alarm B register
0x20
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm B seconds mask
7
1
MSK2
Alarm B minutes mask
15
1
MSK3
Alarm B hours mask
23
1
MSK4
Alarm B date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMBSSR
ALRMBSSR
alarm B sub second register
0x48
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
BKP0R
BKP0R
backup register
0x50
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP10R
BKP10R
backup register
0x78
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP11R
BKP11R
backup register
0x7C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP12R
BKP12R
backup register
0x80
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP13R
BKP13R
backup register
0x84
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP14R
BKP14R
backup register
0x88
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP15R
BKP15R
backup register
0x8C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP16R
BKP16R
backup register
0x90
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP17R
BKP17R
backup register
0x94
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP18R
BKP18R
backup register
0x98
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP19R
BKP19R
backup register
0x9C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP1R
BKP1R
backup register
0x54
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP20R
BKP20R
backup register
0xA0
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP21R
BKP21R
backup register
0xA4
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP22R
BKP22R
backup register
0xA8
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP23R
BKP23R
backup register
0xAC
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP24R
BKP24R
backup register
0xB0
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP25R
BKP25R
backup register
0xB4
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP26R
BKP26R
backup register
0xB8
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP27R
BKP27R
backup register
0xBC
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP28R
BKP28R
backup register
0xC0
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP29R
BKP29R
backup register
0xC4
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP2R
BKP2R
backup register
0x58
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP30R
BKP30R
backup register
0xC8
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP31R
BKP31R
backup register
0xCC
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP3R
BKP3R
backup register
0x5C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP4R
BKP4R
backup register
0x60
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP5R
BKP5R
backup register
0x64
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP6R
BKP6R
backup register
0x68
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP7R
BKP7R
backup register
0x6C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP8R
BKP8R
backup register
0x70
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP9R
BKP9R
backup register
0x74
32
read-write
n
0x0
0x0
BKP
BKP
0
32
CALR
CALR
calibration register
0x3C
32
read-write
n
0x0
0x0
CALM
Calibration minus
0
9
CALP
Increase frequency of RTC by 488.5 ppm
15
1
CALW16
Use a 16-second calibration cycle period
13
1
CALW8
Use an 8-second calibration cycle period
14
1
CR
CR
control register
0x8
32
read-write
n
0x0
0x0
ADD1H
Add 1 hour (summer time change)
16
1
ALRAE
Alarm A enable
8
1
ALRAIE
Alarm A interrupt enable
12
1
ALRBE
Alarm B enable
9
1
ALRBIE
Alarm B interrupt enable
13
1
BKP
Backup
18
1
BYPSHAD
Bypass the shadow registers
5
1
COE
Calibration output enable
23
1
COSEL
Calibration output selection
19
1
FMT
Hour format
6
1
OSEL
Output selection
21
2
POL
Output polarity
20
1
REFCKON
Reference clock detection enable (50 or 60 Hz)
4
1
SUB1H
Subtract 1 hour (winter time change)
17
1
TSE
Time stamp enable
11
1
TSEDGE
Time-stamp event active edge
3
1
TSIE
Time-stamp interrupt enable
15
1
WCKSEL
Wakeup clock selection
0
3
WUTE
Wakeup timer enable
10
1
WUTIE
Wakeup timer interrupt enable
14
1
DR
DR
date register
0x4
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
ISR
ISR
initialization and status register
0xC
32
read-write
n
0x0
0x0
ALRAF
Alarm A flag
8
1
read-write
ALRAWF
Alarm A write flag
0
1
read-only
ALRBF
Alarm B flag
9
1
read-write
ALRBWF
Alarm B write flag
1
1
read-only
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-only
INITS
Initialization status flag
4
1
read-only
RECALPF
Recalibration pending Flag
16
1
read-only
RSF
Registers synchronization flag
5
1
read-write
SHPF
Shift operation pending
3
1
read-write
TAMP1F
Tamper detection flag
13
1
read-write
TAMP2F
RTC_TAMP2 detection flag
14
1
read-write
TAMP3F
RTC_TAMP3 detection flag
15
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVF
Time-stamp overflow flag
12
1
read-write
WUTF
Wakeup timer flag
10
1
read-write
WUTWF
Wakeup timer write flag
2
1
read-only
PRER
PRER
prescaler register
0x10
32
read-write
n
0x0
0x0
PREDIV_A
Asynchronous prescaler factor
16
7
PREDIV_S
Synchronous prescaler factor
0
15
SHIFTR
SHIFTR
shift control register
0x2C
32
write-only
n
0x0
0x0
ADD1S
Add one second
31
1
SUBFS
Subtract a fraction of a second
0
15
SSR
SSR
sub second register
0x28
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TAFCR
TAFCR
tamper and alternate function configuration register
0x40
32
read-write
n
0x0
0x0
PC13MODE
PC13 mode
19
1
PC13VALUE
PC13 value
18
1
PC14MODE
PC 14 mode
21
1
PC14VALUE
PC14 value
20
1
PC15MODE
PC15 mode
23
1
PC15VALUE
PC15 value
22
1
TAMP1E
Tamper 1 detection enable
0
1
TAMP1TRG
Active level for tamper 1
1
1
TAMP2E
Tamper 2 detection enable
3
1
TAMP2TRG
Active level for tamper 2
4
1
TAMP3E
Tamper 3 detection enable
5
1
TAMP3TRG
Active level for tamper 3
6
1
TAMPFLT
Tamper filter count
11
2
TAMPFREQ
Tamper sampling frequency
8
3
TAMPIE
Tamper interrupt enable
2
1
TAMPPRCH
Tamper precharge duration
13
2
TAMPPUDIS
TAMPER pull-up disable
15
1
TAMPTS
Activate timestamp on tamper detection event
7
1
TR
TR
time register
0x0
32
read-write
n
0x0
0x0
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
TSDR
TSDR
time stamp date register
0x34
32
read-only
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
TSSSR
TSSSR
timestamp sub second register
0x38
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TSTR
TSTR
time stamp time register
0x30
32
read-only
n
0x0
0x0
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WPR
WPR
write protection register
0x24
32
write-only
n
0x0
0x0
KEY
Write protection key
0
8
WUTR
WUTR
wakeup timer register
0x14
32
read-write
n
0x0
0x0
WUT
Wakeup auto-reload value bits
0
16
SPI1
Serial peripheral interface/Inter-IC sound
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI1 global interrupt
35
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
DS
Data size
8
4
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for reception
13
1
LDMA_TX
Last DMA transfer for transmission
14
1
NSSP
NSS pulse management
3
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SYSCFG
System configuration controller
SYSCFG
0x0
0x0
0x19
registers
n
CFGR1
CFGR1
configuration register 1
0x0
32
read-write
n
0x0
0x0
ADC24_DMA_RMP
ADC24 DMA remapping bit
8
1
DAC_TRIG_RMP
DAC trigger remap (when TSEL = 001)
7
1
ENCODER_MODE
Encoder mode
22
2
FPU_IT
Interrupt enable bits from FPU
26
6
I2C1_FM
I2C1 Fast Mode Plus
20
1
I2C2_FM
I2C2 Fast Mode Plus
21
1
I2C_PB6_FM
Fast Mode Plus (FM+) driving capability activation bits.
16
1
I2C_PB7_FM
Fast Mode Plus (FM+) driving capability activation bits.
17
1
I2C_PB8_FM
Fast Mode Plus (FM+) driving capability activation bits.
18
1
I2C_PB9_FM
Fast Mode Plus (FM+) driving capability activation bits.
19
1
MEM_MODE
Memory mapping selection bits
0
2
TIM16_DMA_RMP
TIM16 DMA request remapping bit
11
1
TIM17_DMA_RMP
TIM17 DMA request remapping bit
12
1
TIM1_ITR_RMP
Timer 1 ITR3 selection
6
1
TIM6_DAC1_DMA_RMP
TIM6 and DAC1 DMA request remapping bit
13
1
TIM7_DAC2_DMA_RMP
TIM7 and DAC2 DMA request remapping bit
14
1
USB_IT_RMP
USB interrupt remap
5
1
CFGR2
CFGR2
configuration register 2
0x18
32
read-write
n
0x0
0x0
BYP_ADD_PAR
Bypass address bit 29 in parity calculation
4
1
LOCUP_LOCK
Cortex-M0 LOCKUP bit enable bit
0
1
PVD_LOCK
PVD lock enable bit
2
1
SRAM_PARITY_LOCK
SRAM parity lock bit
1
1
SRAM_PEF
SRAM parity flag
8
1
EXTICR1
EXTICR1
external interrupt configuration register 1
0x8
32
read-write
n
0x0
0x0
EXTI0
EXTI 0 configuration bits
0
4
EXTI1
EXTI 1 configuration bits
4
4
EXTI2
EXTI 2 configuration bits
8
4
EXTI3
EXTI 3 configuration bits
12
4
EXTICR2
EXTICR2
external interrupt configuration register 2
0xC
32
read-write
n
0x0
0x0
EXTI4
EXTI 4 configuration bits
0
4
EXTI5
EXTI 5 configuration bits
4
4
EXTI6
EXTI 6 configuration bits
8
4
EXTI7
EXTI 7 configuration bits
12
4
EXTICR3
EXTICR3
external interrupt configuration register 3
0x10
32
read-write
n
0x0
0x0
EXTI10
EXTI 10 configuration bits
8
4
EXTI11
EXTI 11 configuration bits
12
4
EXTI8
EXTI 8 configuration bits
0
4
EXTI9
EXTI 9 configuration bits
4
4
EXTICR4
EXTICR4
external interrupt configuration register 4
0x14
32
read-write
n
0x0
0x0
EXTI12
EXTI 12 configuration bits
0
4
EXTI13
EXTI 13 configuration bits
4
4
EXTI14
EXTI 14 configuration bits
8
4
EXTI15
EXTI 15 configuration bits
12
4
RCR
RCR
CCM SRAM protection register
0x4
32
read-write
n
0x0
0x0
PAGE0_WP
CCM SRAM page write protection bit
0
1
PAGE1_WP
CCM SRAM page write protection bit
1
1
PAGE2_WP
CCM SRAM page write protection bit
2
1
PAGE3_WP
CCM SRAM page write protection bit
3
1
PAGE4_WP
CCM SRAM page write protection bit
4
1
PAGE5_WP
CCM SRAM page write protection bit
5
1
PAGE6_WP
CCM SRAM page write protection bit
6
1
PAGE7_WP
CCM SRAM page write protection bit
7
1
TIM1
Advanced timer
TIMs
0x0
0x0
0x400
registers
n
TIM1_CC
TIM1 capture compare interrupt
27
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BK2E
Break 2 enable
24
1
BK2F
Break 2 filter
20
4
BK2P
Break 2 polarity
25
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CC5E
Capture/Compare 5 output enable
16
1
CC5P
Capture/Compare 5 output Polarity
17
1
CC6E
Capture/Compare 6 output enable
20
1
CC6P
Capture/Compare 6 output Polarity
21
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PCS
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1M_3
Output Compare 1 mode bit 3
16
1
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2M_3
Output Compare 2 mode bit 3
24
1
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3M_3
Output Compare 3 mode bit 3
16
1
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4M_3
Output Compare 4 mode bit 3
24
1
OC4PE
Output compare 4 preload enable
11
1
CCMR3_Output
CCMR3_Output
capture/compare mode register 3 (output mode)
0x54
32
read-write
n
0x0
0x0
OC5CE
Output compare 5 clear enable
7
1
OC5FE
Output compare 5 fast enable
2
1
OC5M
Output compare 5 mode
4
3
OC5M_3
Outout Compare 5 mode bit 3
16
1
OC5PE
Output compare 5 preload enable
3
1
OC6CE
Output compare 6 clear enable
15
1
OC6FE
Output compare 6 fast enable
10
1
OC6M
Output compare 6 mode
12
3
OC6M_3
Outout Compare 6 mode bit 3
24
1
OC6PE
Output compare 6 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare 3 value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare 3 value
0
16
CCR5
CCR5
capture/compare register 5
0x58
32
read-write
n
0x0
0x0
CCR5
Capture/Compare 5 value
0
16
GC5C1
Group Channel 5 and Channel 1
29
1
GC5C2
Group Channel 5 and Channel 2
30
1
GC5C3
Group Channel 5 and Channel 3
31
1
CCR6
CCR6
capture/compare register 6
0x5C
32
read-write
n
0x0
0x0
CCR6
Capture/Compare 6 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
read-write
UIFCPY
UIF copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
MMS2
Master mode selection 2
20
4
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
OIS5
Output Idle state 5
16
1
OIS6
Output Idle state 6
18
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
Reserved
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
B2G
Break 2 generation
8
1
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
option registers
0x60
32
read-write
n
0x0
0x0
TIM1_ETR_ADC1_RMP
TIM1_ETR_ADC1 remapping capability
0
2
TIM1_ETR_ADC4_RMP
TIM1_ETR_ADC4 remapping capability
2
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
SMS3
Slave mode selection bit 3
16
1
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
B2IF
Break 2 interrupt flag
8
1
BIF
Break interrupt flag
7
1
C5IF
Capture/Compare 5 interrupt flag
16
1
C6IF
Capture/Compare 6 interrupt flag
17
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM15
General purpose timers
TIMs
0x0
0x0
0x400
registers
n
TIM1_BRK_TIM15
TIM1 Break/TIM15 global interruts
24
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1M_3
Output Compare 1 mode bit 3
16
1
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2M_3
Output Compare 2 mode bit 3
24
1
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
read-write
UIFCPY
UIF copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
SMS_3
Slave mode selection bit 3
16
1
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM16
General-purpose-timers
TIMs
0x0
0x0
0x400
registers
n
TIM1_UP_TIM16
TIM1 Update/TIM16 global interrupts
25
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1M_3
Output Compare 1 mode
16
1
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
option register
0x50
32
read-write
n
0x0
0x0
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM17
General purpose timer
TIMs
0x0
0x0
0x400
registers
n
TIM1_TRG_COM_TIM17
TIM1 trigger and commutation/TIM17 interrupts
26
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1M_3
Output Compare 1 mode
16
1
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM2
General purpose timer
TIMs
0x0
0x0
0x400
registers
n
TIM2
TIM2 global interrupt
28
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARRH
High Auto-reload value
16
16
ARRL
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 3 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1M_3
Output compare 1 mode bit 3
16
1
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2M_3
Output compare 2 mode bit 3
24
1
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
O24CE
Output compare 4 clear enable
15
1
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3M_3
Output compare 3 mode bit3
16
1
OC3PE
Output compare 3 preload enable
3
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4M_3
Output compare 4 mode bit3
24
1
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1H
High Capture/Compare 1 value (on TIM2)
16
16
CCR1L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2H
High Capture/Compare 2 value (on TIM2)
16
16
CCR2L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3H
High Capture/Compare value (on TIM2)
16
16
CCR3L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4H
High Capture/Compare value (on TIM2)
16
16
CCR4L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNTH
High counter value
16
15
CNTL
Low counter value
0
16
CNT_or_UIFCPY
if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
31
1
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
SMS_3
Slave mode selection bit3
16
1
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM3
General purpose timer
TIMs
0x0
0x0
0x400
registers
n
TIM3
TIM3 global interrupt
29
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARRH
High Auto-reload value
16
16
ARRL
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 3 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1M_3
Output compare 1 mode bit 3
16
1
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2M_3
Output compare 2 mode bit 3
24
1
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
O24CE
Output compare 4 clear enable
15
1
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3M_3
Output compare 3 mode bit3
16
1
OC3PE
Output compare 3 preload enable
3
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4M_3
Output compare 4 mode bit3
24
1
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1H
High Capture/Compare 1 value (on TIM2)
16
16
CCR1L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2H
High Capture/Compare 2 value (on TIM2)
16
16
CCR2L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3H
High Capture/Compare value (on TIM2)
16
16
CCR3L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4H
High Capture/Compare value (on TIM2)
16
16
CCR4L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNTH
High counter value
16
15
CNTL
Low counter value
0
16
CNT_or_UIFCPY
if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
31
1
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
SMS_3
Slave mode selection bit3
16
1
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM6
Basic timers
TIMs
0x0
0x0
0x400
registers
n
TIM6_DACUNDER
TIM6 global and DAC12 underrun interrupts
54
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
TIM7
Basic timers
TIMs
0x0
0x0
0x400
registers
n
TIM7
TIM7 global interrupt
55
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
TSC
Touch sensing controller
TSC
0x0
0x0
0x400
registers
n
EXTI2_TSC
EXTI Line2 and Touch sensing interrupts
8
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
AM
Acquisition mode
2
1
CTPH
Charge transfer pulse high
28
4
CTPL
Charge transfer pulse low
24
4
IODEF
I/O Default mode
4
1
MCV
Max count value
5
3
PGPSC
pulse generator prescaler
12
3
SSD
Spread spectrum deviation
17
7
SSE
Spread spectrum enable
16
1
SSPSC
Spread spectrum prescaler
15
1
START
Start a new acquisition
1
1
SYNCPOL
Synchronization pin polarity
3
1
TSCE
Touch sensing controller enable
0
1
ICR
ICR
interrupt clear register
0x8
32
read-write
n
0x0
0x0
EOAIC
End of acquisition interrupt clear
0
1
MCEIC
Max count error interrupt clear
1
1
IER
IER
interrupt enable register
0x4
32
read-write
n
0x0
0x0
EOAIE
End of acquisition interrupt enable
0
1
MCEIE
Max count error interrupt enable
1
1
IOASCR
IOASCR
I/O analog switch control register
0x18
32
read-write
n
0x0
0x0
G1_IO1
G1_IO1 analog switch enable
0
1
G1_IO2
G1_IO2 analog switch enable
1
1
G1_IO3
G1_IO3 analog switch enable
2
1
G1_IO4
G1_IO4 analog switch enable
3
1
G2_IO1
G2_IO1 analog switch enable
4
1
G2_IO2
G2_IO2 analog switch enable
5
1
G2_IO3
G2_IO3 analog switch enable
6
1
G2_IO4
G2_IO4 analog switch enable
7
1
G3_IO1
G3_IO1 analog switch enable
8
1
G3_IO2
G3_IO2 analog switch enable
9
1
G3_IO3
G3_IO3 analog switch enable
10
1
G3_IO4
G3_IO4 analog switch enable
11
1
G4_IO1
G4_IO1 analog switch enable
12
1
G4_IO2
G4_IO2 analog switch enable
13
1
G4_IO3
G4_IO3 analog switch enable
14
1
G4_IO4
G4_IO4 analog switch enable
15
1
G5_IO1
G5_IO1 analog switch enable
16
1
G5_IO2
G5_IO2 analog switch enable
17
1
G5_IO3
G5_IO3 analog switch enable
18
1
G5_IO4
G5_IO4 analog switch enable
19
1
G6_IO1
G6_IO1 analog switch enable
20
1
G6_IO2
G6_IO2 analog switch enable
21
1
G6_IO3
G6_IO3 analog switch enable
22
1
G6_IO4
G6_IO4 analog switch enable
23
1
G7_IO1
G7_IO1 analog switch enable
24
1
G7_IO2
G7_IO2 analog switch enable
25
1
G7_IO3
G7_IO3 analog switch enable
26
1
G7_IO4
G7_IO4 analog switch enable
27
1
G8_IO1
G8_IO1 analog switch enable
28
1
G8_IO2
G8_IO2 analog switch enable
29
1
G8_IO3
G8_IO3 analog switch enable
30
1
G8_IO4
G8_IO4 analog switch enable
31
1
IOCCR
IOCCR
I/O channel control register
0x28
32
read-write
n
0x0
0x0
G1_IO1
G1_IO1 channel mode
0
1
G1_IO2
G1_IO2 channel mode
1
1
G1_IO3
G1_IO3 channel mode
2
1
G1_IO4
G1_IO4 channel mode
3
1
G2_IO1
G2_IO1 channel mode
4
1
G2_IO2
G2_IO2 channel mode
5
1
G2_IO3
G2_IO3 channel mode
6
1
G2_IO4
G2_IO4 channel mode
7
1
G3_IO1
G3_IO1 channel mode
8
1
G3_IO2
G3_IO2 channel mode
9
1
G3_IO3
G3_IO3 channel mode
10
1
G3_IO4
G3_IO4 channel mode
11
1
G4_IO1
G4_IO1 channel mode
12
1
G4_IO2
G4_IO2 channel mode
13
1
G4_IO3
G4_IO3 channel mode
14
1
G4_IO4
G4_IO4 channel mode
15
1
G5_IO1
G5_IO1 channel mode
16
1
G5_IO2
G5_IO2 channel mode
17
1
G5_IO3
G5_IO3 channel mode
18
1
G5_IO4
G5_IO4 channel mode
19
1
G6_IO1
G6_IO1 channel mode
20
1
G6_IO2
G6_IO2 channel mode
21
1
G6_IO3
G6_IO3 channel mode
22
1
G6_IO4
G6_IO4 channel mode
23
1
G7_IO1
G7_IO1 channel mode
24
1
G7_IO2
G7_IO2 channel mode
25
1
G7_IO3
G7_IO3 channel mode
26
1
G7_IO4
G7_IO4 channel mode
27
1
G8_IO1
G8_IO1 channel mode
28
1
G8_IO2
G8_IO2 channel mode
29
1
G8_IO3
G8_IO3 channel mode
30
1
G8_IO4
G8_IO4 channel mode
31
1
IOG1CR
IOG1CR
I/O group x counter register
0x34
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOG2CR
IOG2CR
I/O group x counter register
0x38
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOG3CR
IOG3CR
I/O group x counter register
0x3C
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOG4CR
IOG4CR
I/O group x counter register
0x40
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOG5CR
IOG5CR
I/O group x counter register
0x44
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOG6CR
IOG6CR
I/O group x counter register
0x48
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOG7CR
IOG7CR
I/O group x counter register
0x4C
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOG8CR
IOG8CR
I/O group x counter register
0x50
32
read-only
n
0x0
0x0
CNT
Counter value
0
14
IOGCSR
IOGCSR
I/O group control status register
0x30
32
read-write
n
0x0
0x0
G1E
Analog I/O group x enable
0
1
read-write
G1S
Analog I/O group x status
16
1
read-only
G2E
Analog I/O group x enable
1
1
read-write
G2S
Analog I/O group x status
17
1
read-only
G3E
Analog I/O group x enable
2
1
read-write
G3S
Analog I/O group x status
18
1
read-only
G4E
Analog I/O group x enable
3
1
read-write
G4S
Analog I/O group x status
19
1
read-only
G5E
Analog I/O group x enable
4
1
read-write
G5S
Analog I/O group x status
20
1
read-only
G6E
Analog I/O group x enable
5
1
read-write
G6S
Analog I/O group x status
21
1
read-only
G7E
Analog I/O group x enable
6
1
read-write
G7S
Analog I/O group x status
22
1
read-write
G8E
Analog I/O group x enable
7
1
read-write
G8S
Analog I/O group x status
23
1
read-write
IOHCR
IOHCR
I/O hysteresis control register
0x10
32
read-write
n
0x0
0x0
G1_IO1
G1_IO1 Schmitt trigger hysteresis mode
0
1
G1_IO2
G1_IO2 Schmitt trigger hysteresis mode
1
1
G1_IO3
G1_IO3 Schmitt trigger hysteresis mode
2
1
G1_IO4
G1_IO4 Schmitt trigger hysteresis mode
3
1
G2_IO1
G2_IO1 Schmitt trigger hysteresis mode
4
1
G2_IO2
G2_IO2 Schmitt trigger hysteresis mode
5
1
G2_IO3
G2_IO3 Schmitt trigger hysteresis mode
6
1
G2_IO4
G2_IO4 Schmitt trigger hysteresis mode
7
1
G3_IO1
G3_IO1 Schmitt trigger hysteresis mode
8
1
G3_IO2
G3_IO2 Schmitt trigger hysteresis mode
9
1
G3_IO3
G3_IO3 Schmitt trigger hysteresis mode
10
1
G3_IO4
G3_IO4 Schmitt trigger hysteresis mode
11
1
G4_IO1
G4_IO1 Schmitt trigger hysteresis mode
12
1
G4_IO2
G4_IO2 Schmitt trigger hysteresis mode
13
1
G4_IO3
G4_IO3 Schmitt trigger hysteresis mode
14
1
G4_IO4
G4_IO4 Schmitt trigger hysteresis mode
15
1
G5_IO1
G5_IO1 Schmitt trigger hysteresis mode
16
1
G5_IO2
G5_IO2 Schmitt trigger hysteresis mode
17
1
G5_IO3
G5_IO3 Schmitt trigger hysteresis mode
18
1
G5_IO4
G5_IO4 Schmitt trigger hysteresis mode
19
1
G6_IO1
G6_IO1 Schmitt trigger hysteresis mode
20
1
G6_IO2
G6_IO2 Schmitt trigger hysteresis mode
21
1
G6_IO3
G6_IO3 Schmitt trigger hysteresis mode
22
1
G6_IO4
G6_IO4 Schmitt trigger hysteresis mode
23
1
G7_IO1
G7_IO1 Schmitt trigger hysteresis mode
24
1
G7_IO2
G7_IO2 Schmitt trigger hysteresis mode
25
1
G7_IO3
G7_IO3 Schmitt trigger hysteresis mode
26
1
G7_IO4
G7_IO4 Schmitt trigger hysteresis mode
27
1
G8_IO1
G8_IO1 Schmitt trigger hysteresis mode
28
1
G8_IO2
G8_IO2 Schmitt trigger hysteresis mode
29
1
G8_IO3
G8_IO3 Schmitt trigger hysteresis mode
30
1
G8_IO4
G8_IO4 Schmitt trigger hysteresis mode
31
1
IOSCR
IOSCR
I/O sampling control register
0x20
32
read-write
n
0x0
0x0
G1_IO1
G1_IO1 sampling mode
0
1
G1_IO2
G1_IO2 sampling mode
1
1
G1_IO3
G1_IO3 sampling mode
2
1
G1_IO4
G1_IO4 sampling mode
3
1
G2_IO1
G2_IO1 sampling mode
4
1
G2_IO2
G2_IO2 sampling mode
5
1
G2_IO3
G2_IO3 sampling mode
6
1
G2_IO4
G2_IO4 sampling mode
7
1
G3_IO1
G3_IO1 sampling mode
8
1
G3_IO2
G3_IO2 sampling mode
9
1
G3_IO3
G3_IO3 sampling mode
10
1
G3_IO4
G3_IO4 sampling mode
11
1
G4_IO1
G4_IO1 sampling mode
12
1
G4_IO2
G4_IO2 sampling mode
13
1
G4_IO3
G4_IO3 sampling mode
14
1
G4_IO4
G4_IO4 sampling mode
15
1
G5_IO1
G5_IO1 sampling mode
16
1
G5_IO2
G5_IO2 sampling mode
17
1
G5_IO3
G5_IO3 sampling mode
18
1
G5_IO4
G5_IO4 sampling mode
19
1
G6_IO1
G6_IO1 sampling mode
20
1
G6_IO2
G6_IO2 sampling mode
21
1
G6_IO3
G6_IO3 sampling mode
22
1
G6_IO4
G6_IO4 sampling mode
23
1
G7_IO1
G7_IO1 sampling mode
24
1
G7_IO2
G7_IO2 sampling mode
25
1
G7_IO3
G7_IO3 sampling mode
26
1
G7_IO4
G7_IO4 sampling mode
27
1
G8_IO1
G8_IO1 sampling mode
28
1
G8_IO2
G8_IO2 sampling mode
29
1
G8_IO3
G8_IO3 sampling mode
30
1
G8_IO4
G8_IO4 sampling mode
31
1
ISR
ISR
interrupt status register
0xC
32
read-write
n
0x0
0x0
EOAF
End of acquisition flag
0
1
MCEF
Max count error flag
1
1
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1_EXTI25
USART1 global interrupt and EXTI Line 25 interrupt
37
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT
Driver Enable assertion time
21
5
DEDT
Driver Enable deassertion time
16
5
EOBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD
Auto baud rate mode
21
2
ADD0
Address of the USART node
24
4
ADD4
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DATAINV
Binary data inversion
18
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
read-write
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of timeout clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
Auto baud rate error
14
1
ABRF
Auto baud rate flag
15
1
BUSY
Busy flag
16
1
CMF
character match flag
17
1
CTS
CTS flag
10
1
CTSIF
CTS interrupt flag
9
1
EOBF
End of block flag
12
1
FE
Framing error
1
1
IDLE
Idle line detected
4
1
LBDF
LIN break detection flag
8
1
NF
Noise detected flag
2
1
ORE
Overrun error
3
1
PE
Parity error
0
1
REACK
Receive enable acknowledge flag
22
1
RTOF
Receiver timeout
11
1
RWU
Receiver wakeup from Mute mode
19
1
RXNE
Read data register not empty
5
1
SBKF
Send break flag
18
1
TC
Transmission complete
6
1
TEACK
Transmit enable acknowledge flag
21
1
TXE
Transmit data register empty
7
1
WUF
Wakeup from Stop mode flag
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
read-write
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART2_EXTI26
USART2 global interrupt and EXTI Line 26 interrupt
38
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT
Driver Enable assertion time
21
5
DEDT
Driver Enable deassertion time
16
5
EOBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD
Auto baud rate mode
21
2
ADD0
Address of the USART node
24
4
ADD4
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DATAINV
Binary data inversion
18
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
read-write
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of timeout clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
Auto baud rate error
14
1
ABRF
Auto baud rate flag
15
1
BUSY
Busy flag
16
1
CMF
character match flag
17
1
CTS
CTS flag
10
1
CTSIF
CTS interrupt flag
9
1
EOBF
End of block flag
12
1
FE
Framing error
1
1
IDLE
Idle line detected
4
1
LBDF
LIN break detection flag
8
1
NF
Noise detected flag
2
1
ORE
Overrun error
3
1
PE
Parity error
0
1
REACK
Receive enable acknowledge flag
22
1
RTOF
Receiver timeout
11
1
RWU
Receiver wakeup from Mute mode
19
1
RXNE
Read data register not empty
5
1
SBKF
Send break flag
18
1
TC
Transmission complete
6
1
TEACK
Transmit enable acknowledge flag
21
1
TXE
Transmit data register empty
7
1
WUF
Wakeup from Stop mode flag
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
read-write
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
USART3
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART3_EXTI28
USART3 global interrupt and EXTI Line 28 interrupt
39
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT
Driver Enable assertion time
21
5
DEDT
Driver Enable deassertion time
16
5
EOBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD
Auto baud rate mode
21
2
ADD0
Address of the USART node
24
4
ADD4
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DATAINV
Binary data inversion
18
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
read-write
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of timeout clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
Auto baud rate error
14
1
ABRF
Auto baud rate flag
15
1
BUSY
Busy flag
16
1
CMF
character match flag
17
1
CTS
CTS flag
10
1
CTSIF
CTS interrupt flag
9
1
EOBF
End of block flag
12
1
FE
Framing error
1
1
IDLE
Idle line detected
4
1
LBDF
LIN break detection flag
8
1
NF
Noise detected flag
2
1
ORE
Overrun error
3
1
PE
Parity error
0
1
REACK
Receive enable acknowledge flag
22
1
RTOF
Receiver timeout
11
1
RWU
Receiver wakeup from Mute mode
19
1
RXNE
Read data register not empty
5
1
SBKF
Send break flag
18
1
TC
Transmission complete
6
1
TEACK
Transmit enable acknowledge flag
21
1
TXE
Transmit data register empty
7
1
WUF
Wakeup from Stop mode flag
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
read-write
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
WWDG
Window watchdog
WWDG
0x0
0x0
0x400
registers
n
WWDG
Window Watchdog interrupt
0
CFR
CFR
Configuration register
0x4
32
read-write
n
0x0
0x0
EWI
Early wakeup interrupt
9
1
W
7-bit window value
0
7
WDGTB
Timer base
7
2
CR
CR
Control register
0x0
32
read-write
n
0x0
0x0
T
7-bit counter
0
7
WDGA
Activation bit
7
1
SR
SR
Status register
0x8
32
read-write
n
0x0
0x0
EWIF
Early wakeup interrupt flag
0
1