STMicroelectronics
STM32F417VG
2024.05.06
STM32F417VG
false
0
0
ADC1
Analog-to-digital converter
ADC
0x0
0x0
0x51
registers
n
ADC
ADC1 global interrupt
18
CR1
CR1
control register 1
0x4
32
read-write
n
0x0
0x0
AWDCH
Analog watchdog channel select bits
0
5
AWDEN
Analog watchdog enable on regular channels
23
1
AWDIE
Analog watchdog interrupt enable
6
1
AWDSGL
Enable the watchdog on a single channel in scan mode
9
1
DISCEN
Discontinuous mode on regular channels
11
1
DISCNUM
Discontinuous mode channel count
13
3
EOCIE
Interrupt enable for EOC
5
1
JAUTO
Automatic injected group conversion
10
1
JAWDEN
Analog watchdog enable on injected channels
22
1
JDISCEN
Discontinuous mode on injected channels
12
1
JEOCIE
Interrupt enable for injected channels
7
1
OVRIE
Overrun interrupt enable
26
1
RES
Resolution
24
2
SCAN
Scan mode
8
1
CR2
CR2
control register 2
0x8
32
read-write
n
0x0
0x0
ADON
A/D Converter ON / OFF
0
1
ALIGN
Data alignment
11
1
CONT
Continuous conversion
1
1
DDS
DMA disable selection (for single ADC mode)
9
1
DMA
Direct memory access mode (for single ADC mode)
8
1
EOCS
End of conversion selection
10
1
EXTEN
External trigger enable for regular channels
28
2
EXTSEL
External event select for regular group
24
4
JEXTEN
External trigger enable for injected channels
20
2
JEXTSEL
External event select for injected group
16
4
JSWSTART
Start conversion of injected channels
22
1
SWSTART
Start conversion of regular channels
30
1
DR
DR
regular data register
0x4C
32
read-only
n
0x0
0x0
DATA
Regular data
0
16
HTR
HTR
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
HT
Analog watchdog higher threshold
0
12
JDR1
JDR1
injected data register x
0x3C
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR2
JDR2
injected data register x
0x40
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR3
JDR3
injected data register x
0x44
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR4
JDR4
injected data register x
0x48
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JOFR1
JOFR1
injected channel data offset register x
0x14
32
read-write
n
0x0
0x0
JOFFSET1
Data offset for injected channel x
0
12
JOFR2
JOFR2
injected channel data offset register x
0x18
32
read-write
n
0x0
0x0
JOFFSET2
Data offset for injected channel x
0
12
JOFR3
JOFR3
injected channel data offset register x
0x1C
32
read-write
n
0x0
0x0
JOFFSET3
Data offset for injected channel x
0
12
JOFR4
JOFR4
injected channel data offset register x
0x20
32
read-write
n
0x0
0x0
JOFFSET4
Data offset for injected channel x
0
12
JSQR
JSQR
injected sequence register
0x38
32
read-write
n
0x0
0x0
JL
Injected sequence length
20
2
JSQ1
1st conversion in injected sequence
0
5
JSQ2
2nd conversion in injected sequence
5
5
JSQ3
3rd conversion in injected sequence
10
5
JSQ4
4th conversion in injected sequence
15
5
LTR
LTR
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
LT
Analog watchdog lower threshold
0
12
SMPR1
SMPR1
sample time register 1
0xC
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SMPR2
SMPR2
sample time register 2
0x10
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SQR1
SQR1
regular sequence register 1
0x2C
32
read-write
n
0x0
0x0
L
Regular channel sequence length
20
4
SQ13
13th conversion in regular sequence
0
5
SQ14
14th conversion in regular sequence
5
5
SQ15
15th conversion in regular sequence
10
5
SQ16
16th conversion in regular sequence
15
5
SQR2
SQR2
regular sequence register 2
0x30
32
read-write
n
0x0
0x0
SQ10
10th conversion in regular sequence
15
5
SQ11
11th conversion in regular sequence
20
5
SQ12
12th conversion in regular sequence
25
5
SQ7
7th conversion in regular sequence
0
5
SQ8
8th conversion in regular sequence
5
5
SQ9
9th conversion in regular sequence
10
5
SQR3
SQR3
regular sequence register 3
0x34
32
read-write
n
0x0
0x0
SQ1
1st conversion in regular sequence
0
5
SQ2
2nd conversion in regular sequence
5
5
SQ3
3rd conversion in regular sequence
10
5
SQ4
4th conversion in regular sequence
15
5
SQ5
5th conversion in regular sequence
20
5
SQ6
6th conversion in regular sequence
25
5
SR
SR
status register
0x0
32
read-write
n
0x0
0x0
AWD
Analog watchdog flag
0
1
EOC
Regular channel end of conversion
1
1
JEOC
Injected channel end of conversion
2
1
JSTRT
Injected channel start flag
3
1
OVR
Overrun
5
1
STRT
Regular channel start flag
4
1
ADC_Common
ADC common registers
ADC
0x0
0x0
0x9
registers
n
CCR
CCR
ADC common control register
0x4
32
read-write
n
0x0
0x0
ADCPRE
ADC prescaler
16
2
DDS
DMA disable selection for multi-ADC mode
13
1
DELAY
Delay between 2 sampling phases
8
4
DMA
Direct memory access mode for multi ADC mode
14
2
TSVREFE
Temperature sensor and VREFINT enable
23
1
VBATE
VBAT enable
22
1
CSR
CSR
ADC Common status register
0x0
32
read-only
n
0x0
0x0
AWD1
Analog watchdog flag of ADC 1
0
1
AWD2
Analog watchdog flag of ADC 2
8
1
AWD3
Analog watchdog flag of ADC 3
16
1
EOC1
End of conversion of ADC 1
1
1
EOC2
End of conversion of ADC 2
9
1
EOC3
End of conversion of ADC 3
17
1
JEOC1
Injected channel end of conversion of ADC 1
2
1
JEOC2
Injected channel end of conversion of ADC 2
10
1
JEOC3
Injected channel end of conversion of ADC 3
18
1
JSTRT1
Injected channel Start flag of ADC 1
3
1
JSTRT2
Injected channel Start flag of ADC 2
11
1
JSTRT3
Injected channel Start flag of ADC 3
19
1
OVR1
Overrun flag of ADC 1
5
1
OVR2
Overrun flag of ADC 2
13
1
OVR3
Overrun flag of ADC3
21
1
STRT1
Regular channel Start flag of ADC 1
4
1
STRT2
Regular channel Start flag of ADC 2
12
1
STRT3
Regular channel Start flag of ADC 3
20
1
CRC
Cryptographic processor
CRC
0x0
0x0
0x400
registers
n
CR
CR
Control register
0x8
32
write-only
n
0x0
0x0
CR
Control regidter
0
1
DR
DR
Data register
0x0
32
read-write
n
0x0
0x0
DR
Data Register
0
32
IDR
IDR
Independent Data register
0x4
32
read-write
n
0x0
0x0
IDR
Independent Data register
0
8
DAC
Digital-to-analog converter
DAC
0x0
0x0
0x400
registers
n
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
BOFF1
DAC channel1 output buffer disable
1
1
BOFF2
DAC channel2 output buffer disable
17
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN2
DAC channel2 DMA enable
28
1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt enable
13
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt enable
29
1
EN1
DAC channel1 enable
0
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude selector
8
4
MAMP2
DAC channel2 mask/amplitude selector
24
4
TEN1
DAC channel1 trigger enable
2
1
TEN2
DAC channel2 trigger enable
18
1
TSEL1
DAC channel1 trigger selection
3
3
TSEL2
DAC channel2 trigger selection
19
3
WAVE1
DAC channel1 noise/triangle wave generation enable
6
2
WAVE2
DAC channel2 noise/triangle wave generation enable
22
2
DHR12L1
DHR12L1
channel1 12-bit left aligned data holding register
0xC
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding register
0x18
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit left-aligned data
4
12
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DACC2DHR
DAC channel2 12-bit left-aligned data
20
12
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding register
0x14
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit right-aligned data
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DACC2DHR
DAC channel2 12-bit right-aligned data
16
12
DHR8R1
DHR8R1
channel1 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding register
0x1C
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 8-bit right-aligned data
0
8
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DACC2DHR
DAC channel2 8-bit right-aligned data
8
8
DOR1
DOR1
channel1 data output register
0x2C
32
read-only
n
0x0
0x0
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
channel2 data output register
0x30
32
read-only
n
0x0
0x0
DACC2DOR
DAC channel2 data output
0
12
SR
SR
status register
0x34
32
read-write
n
0x0
0x0
DMAUDR1
DAC channel1 DMA underrun flag
13
1
DMAUDR2
DAC channel2 DMA underrun flag
29
1
SWTRIGR
SWTRIGR
software trigger register
0x4
32
write-only
n
0x0
0x0
SWTRIG1
DAC channel1 software trigger
0
1
SWTRIG2
DAC channel2 software trigger
1
1
DBG
Debug support
DBG
0x0
0x0
0x400
registers
n
DBGMCU_APB1_FZ
DBGMCU_APB1_FZ
Debug MCU APB1 Freeze registe
0x8
32
read-write
n
0x0
0x0
DBG_I2C1_SMBUS_TIMEOUT
DBG_J2C1_SMBUS_TIMEOUT
21
1
DBG_I2C2_SMBUS_TIMEOUT
DBG_J2C2_SMBUS_TIMEOUT
22
1
DBG_I2C3SMBUS_TIMEOUT
DBG_J2C3SMBUS_TIMEOUT
23
1
DBG_IWDEG_STOP
DBG_IWDEG_STOP
12
1
DBG_RTC_Stop
RTC stopped when Core is halted
10
1
DBG_TIM2_STOP
DBG_TIM2_STOP
0
1
DBG_TIM3_STOP
DBG_TIM3 _STOP
1
1
DBG_TIM4_STOP
DBG_TIM4_STOP
2
1
DBG_TIM5_STOP
DBG_TIM5_STOP
3
1
DBG_WWDG_STOP
DBG_WWDG_STOP
11
1
DBGMCU_APB2_FZ
DBGMCU_APB2_FZ
Debug MCU APB2 Freeze registe
0xC
32
read-write
n
0x0
0x0
DBG_TIM10_STOP
TIM10 counter stopped when core is halted
17
1
DBG_TIM11_STOP
TIM11 counter stopped when core is halted
18
1
DBG_TIM1_STOP
TIM1 counter stopped when core is halted
0
1
DBG_TIM9_STOP
TIM9 counter stopped when core is halted
16
1
DBGMCU_CR
DBGMCU_CR
Control Register
0x4
32
read-write
n
0x0
0x0
DBG_SLEEP
DBG_SLEEP
0
1
DBG_STANDBY
DBG_STANDBY
2
1
DBG_STOP
DBG_STOP
1
1
TRACE_IOEN
TRACE_IOEN
5
1
TRACE_MODE
TRACE_MODE
6
2
DBGMCU_IDCODE
DBGMCU_IDCODE
IDCODE
0x0
32
read-only
n
0x0
0x0
DEV_ID
DEV_ID
0
12
REV_ID
REV_ID
16
16
DMA1
DMA controller
DMA
0x0
0x0
0x400
registers
n
RTC_Alarm
RTC Alarms (A and B) through EXTI line interrupt
41
HIFCR
HIFCR
high interrupt flag clear register
0xC
32
write-only
n
0x0
0x0
CDMEIF4
Stream x clear direct mode error interrupt flag (x = 7..4)
2
1
CDMEIF5
Stream x clear direct mode error interrupt flag (x = 7..4)
8
1
CDMEIF6
Stream x clear direct mode error interrupt flag (x = 7..4)
18
1
CDMEIF7
Stream x clear direct mode error interrupt flag (x = 7..4)
24
1
CFEIF4
Stream x clear FIFO error interrupt flag (x = 7..4)
0
1
CFEIF5
Stream x clear FIFO error interrupt flag (x = 7..4)
6
1
CFEIF6
Stream x clear FIFO error interrupt flag (x = 7..4)
16
1
CFEIF7
Stream x clear FIFO error interrupt flag (x = 7..4)
22
1
CHTIF4
Stream x clear half transfer interrupt flag (x = 7..4)
4
1
CHTIF5
Stream x clear half transfer interrupt flag (x = 7..4)
10
1
CHTIF6
Stream x clear half transfer interrupt flag (x = 7..4)
20
1
CHTIF7
Stream x clear half transfer interrupt flag (x = 7..4)
26
1
CTCIF4
Stream x clear transfer complete interrupt flag (x = 7..4)
5
1
CTCIF5
Stream x clear transfer complete interrupt flag (x = 7..4)
11
1
CTCIF6
Stream x clear transfer complete interrupt flag (x = 7..4)
21
1
CTCIF7
Stream x clear transfer complete interrupt flag (x = 7..4)
27
1
CTEIF4
Stream x clear transfer error interrupt flag (x = 7..4)
3
1
CTEIF5
Stream x clear transfer error interrupt flag (x = 7..4)
9
1
CTEIF6
Stream x clear transfer error interrupt flag (x = 7..4)
19
1
CTEIF7
Stream x clear transfer error interrupt flag (x = 7..4)
25
1
HISR
HISR
high interrupt status register
0x4
32
read-only
n
0x0
0x0
DMEIF4
Stream x direct mode error interrupt flag (x=7..4)
2
1
DMEIF5
Stream x direct mode error interrupt flag (x=7..4)
8
1
DMEIF6
Stream x direct mode error interrupt flag (x=7..4)
18
1
DMEIF7
Stream x direct mode error interrupt flag (x=7..4)
24
1
FEIF4
Stream x FIFO error interrupt flag (x=7..4)
0
1
FEIF5
Stream x FIFO error interrupt flag (x=7..4)
6
1
FEIF6
Stream x FIFO error interrupt flag (x=7..4)
16
1
FEIF7
Stream x FIFO error interrupt flag (x=7..4)
22
1
HTIF4
Stream x half transfer interrupt flag (x=7..4)
4
1
HTIF5
Stream x half transfer interrupt flag (x=7..4)
10
1
HTIF6
Stream x half transfer interrupt flag (x=7..4)
20
1
HTIF7
Stream x half transfer interrupt flag (x=7..4)
26
1
TCIF4
Stream x transfer complete interrupt flag (x=7..4)
5
1
TCIF5
Stream x transfer complete interrupt flag (x=7..4)
11
1
TCIF6
Stream x transfer complete interrupt flag (x=7..4)
21
1
TCIF7
Stream x transfer complete interrupt flag (x=7..4)
27
1
TEIF4
Stream x transfer error interrupt flag (x=7..4)
3
1
TEIF5
Stream x transfer error interrupt flag (x=7..4)
9
1
TEIF6
Stream x transfer error interrupt flag (x=7..4)
19
1
TEIF7
Stream x transfer error interrupt flag (x=7..4)
25
1
LIFCR
LIFCR
low interrupt flag clear register
0x8
32
write-only
n
0x0
0x0
CDMEIF0
Stream x clear direct mode error interrupt flag (x = 3..0)
2
1
CDMEIF1
Stream x clear direct mode error interrupt flag (x = 3..0)
8
1
CDMEIF2
Stream x clear direct mode error interrupt flag (x = 3..0)
18
1
CDMEIF3
Stream x clear direct mode error interrupt flag (x = 3..0)
24
1
CFEIF0
Stream x clear FIFO error interrupt flag (x = 3..0)
0
1
CFEIF1
Stream x clear FIFO error interrupt flag (x = 3..0)
6
1
CFEIF2
Stream x clear FIFO error interrupt flag (x = 3..0)
16
1
CFEIF3
Stream x clear FIFO error interrupt flag (x = 3..0)
22
1
CHTIF0
Stream x clear half transfer interrupt flag (x = 3..0)
4
1
CHTIF1
Stream x clear half transfer interrupt flag (x = 3..0)
10
1
CHTIF2
Stream x clear half transfer interrupt flag (x = 3..0)
20
1
CHTIF3
Stream x clear half transfer interrupt flag (x = 3..0)
26
1
CTCIF0
Stream x clear transfer complete interrupt flag (x = 3..0)
5
1
CTCIF1
Stream x clear transfer complete interrupt flag (x = 3..0)
11
1
CTCIF2
Stream x clear transfer complete interrupt flag (x = 3..0)
21
1
CTCIF3
Stream x clear transfer complete interrupt flag (x = 3..0)
27
1
CTEIF0
Stream x clear transfer error interrupt flag (x = 3..0)
3
1
CTEIF1
Stream x clear transfer error interrupt flag (x = 3..0)
9
1
CTEIF2
Stream x clear transfer error interrupt flag (x = 3..0)
19
1
CTEIF3
Stream x clear transfer error interrupt flag (x = 3..0)
25
1
LISR
LISR
low interrupt status register
0x0
32
read-only
n
0x0
0x0
DMEIF0
Stream x direct mode error interrupt flag (x=3..0)
2
1
DMEIF1
Stream x direct mode error interrupt flag (x=3..0)
8
1
DMEIF2
Stream x direct mode error interrupt flag (x=3..0)
18
1
DMEIF3
Stream x direct mode error interrupt flag (x=3..0)
24
1
FEIF0
Stream x FIFO error interrupt flag (x=3..0)
0
1
FEIF1
Stream x FIFO error interrupt flag (x=3..0)
6
1
FEIF2
Stream x FIFO error interrupt flag (x=3..0)
16
1
FEIF3
Stream x FIFO error interrupt flag (x=3..0)
22
1
HTIF0
Stream x half transfer interrupt flag (x=3..0)
4
1
HTIF1
Stream x half transfer interrupt flag (x=3..0)
10
1
HTIF2
Stream x half transfer interrupt flag (x=3..0)
20
1
HTIF3
Stream x half transfer interrupt flag (x=3..0)
26
1
TCIF0
Stream x transfer complete interrupt flag (x = 3..0)
5
1
TCIF1
Stream x transfer complete interrupt flag (x = 3..0)
11
1
TCIF2
Stream x transfer complete interrupt flag (x = 3..0)
21
1
TCIF3
Stream x transfer complete interrupt flag (x = 3..0)
27
1
TEIF0
Stream x transfer error interrupt flag (x=3..0)
3
1
TEIF1
Stream x transfer error interrupt flag (x=3..0)
9
1
TEIF2
Stream x transfer error interrupt flag (x=3..0)
19
1
TEIF3
Stream x transfer error interrupt flag (x=3..0)
25
1
S0CR
S0CR
stream x configuration register
0x10
32
read-write
n
0x0
0x0
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S0FCR
S0FCR
stream x FIFO control register
0x24
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S0M0AR
S0M0AR
stream x memory 0 address register
0x1C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S0M1AR
S0M1AR
stream x memory 1 address register
0x20
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S0NDTR
S0NDTR
stream x number of data register
0x14
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S0PAR
S0PAR
stream x peripheral address register
0x18
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S1CR
S1CR
stream x configuration register
0x28
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S1FCR
S1FCR
stream x FIFO control register
0x3C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S1M0AR
S1M0AR
stream x memory 0 address register
0x34
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S1M1AR
S1M1AR
stream x memory 1 address register
0x38
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S1NDTR
S1NDTR
stream x number of data register
0x2C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S1PAR
S1PAR
stream x peripheral address register
0x30
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S2CR
S2CR
stream x configuration register
0x40
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S2FCR
S2FCR
stream x FIFO control register
0x54
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S2M0AR
S2M0AR
stream x memory 0 address register
0x4C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S2M1AR
S2M1AR
stream x memory 1 address register
0x50
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S2NDTR
S2NDTR
stream x number of data register
0x44
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S2PAR
S2PAR
stream x peripheral address register
0x48
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S3CR
S3CR
stream x configuration register
0x58
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S3FCR
S3FCR
stream x FIFO control register
0x6C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S3M0AR
S3M0AR
stream x memory 0 address register
0x64
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S3M1AR
S3M1AR
stream x memory 1 address register
0x68
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S3NDTR
S3NDTR
stream x number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S3PAR
S3PAR
stream x peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S4CR
S4CR
stream x configuration register
0x70
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S4FCR
S4FCR
stream x FIFO control register
0x84
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S4M0AR
S4M0AR
stream x memory 0 address register
0x7C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S4M1AR
S4M1AR
stream x memory 1 address register
0x80
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S4NDTR
S4NDTR
stream x number of data register
0x74
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S4PAR
S4PAR
stream x peripheral address register
0x78
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S5CR
S5CR
stream x configuration register
0x88
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S5FCR
S5FCR
stream x FIFO control register
0x9C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S5M0AR
S5M0AR
stream x memory 0 address register
0x94
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S5M1AR
S5M1AR
stream x memory 1 address register
0x98
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S5NDTR
S5NDTR
stream x number of data register
0x8C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S5PAR
S5PAR
stream x peripheral address register
0x90
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S6CR
S6CR
stream x configuration register
0xA0
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S6FCR
S6FCR
stream x FIFO control register
0xB4
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S6M0AR
S6M0AR
stream x memory 0 address register
0xAC
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S6M1AR
S6M1AR
stream x memory 1 address register
0xB0
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S6NDTR
S6NDTR
stream x number of data register
0xA4
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S6PAR
S6PAR
stream x peripheral address register
0xA8
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S7CR
S7CR
stream x configuration register
0xB8
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S7FCR
S7FCR
stream x FIFO control register
0xCC
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S7M0AR
S7M0AR
stream x memory 0 address register
0xC4
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S7M1AR
S7M1AR
stream x memory 1 address register
0xC8
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S7NDTR
S7NDTR
stream x number of data register
0xBC
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S7PAR
S7PAR
stream x peripheral address register
0xC0
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
DMA2
DMA controller
DMA
0x0
0x0
0x400
registers
n
HIFCR
HIFCR
high interrupt flag clear register
0xC
32
write-only
n
0x0
0x0
CDMEIF4
Stream x clear direct mode error interrupt flag (x = 7..4)
2
1
CDMEIF5
Stream x clear direct mode error interrupt flag (x = 7..4)
8
1
CDMEIF6
Stream x clear direct mode error interrupt flag (x = 7..4)
18
1
CDMEIF7
Stream x clear direct mode error interrupt flag (x = 7..4)
24
1
CFEIF4
Stream x clear FIFO error interrupt flag (x = 7..4)
0
1
CFEIF5
Stream x clear FIFO error interrupt flag (x = 7..4)
6
1
CFEIF6
Stream x clear FIFO error interrupt flag (x = 7..4)
16
1
CFEIF7
Stream x clear FIFO error interrupt flag (x = 7..4)
22
1
CHTIF4
Stream x clear half transfer interrupt flag (x = 7..4)
4
1
CHTIF5
Stream x clear half transfer interrupt flag (x = 7..4)
10
1
CHTIF6
Stream x clear half transfer interrupt flag (x = 7..4)
20
1
CHTIF7
Stream x clear half transfer interrupt flag (x = 7..4)
26
1
CTCIF4
Stream x clear transfer complete interrupt flag (x = 7..4)
5
1
CTCIF5
Stream x clear transfer complete interrupt flag (x = 7..4)
11
1
CTCIF6
Stream x clear transfer complete interrupt flag (x = 7..4)
21
1
CTCIF7
Stream x clear transfer complete interrupt flag (x = 7..4)
27
1
CTEIF4
Stream x clear transfer error interrupt flag (x = 7..4)
3
1
CTEIF5
Stream x clear transfer error interrupt flag (x = 7..4)
9
1
CTEIF6
Stream x clear transfer error interrupt flag (x = 7..4)
19
1
CTEIF7
Stream x clear transfer error interrupt flag (x = 7..4)
25
1
HISR
HISR
high interrupt status register
0x4
32
read-only
n
0x0
0x0
DMEIF4
Stream x direct mode error interrupt flag (x=7..4)
2
1
DMEIF5
Stream x direct mode error interrupt flag (x=7..4)
8
1
DMEIF6
Stream x direct mode error interrupt flag (x=7..4)
18
1
DMEIF7
Stream x direct mode error interrupt flag (x=7..4)
24
1
FEIF4
Stream x FIFO error interrupt flag (x=7..4)
0
1
FEIF5
Stream x FIFO error interrupt flag (x=7..4)
6
1
FEIF6
Stream x FIFO error interrupt flag (x=7..4)
16
1
FEIF7
Stream x FIFO error interrupt flag (x=7..4)
22
1
HTIF4
Stream x half transfer interrupt flag (x=7..4)
4
1
HTIF5
Stream x half transfer interrupt flag (x=7..4)
10
1
HTIF6
Stream x half transfer interrupt flag (x=7..4)
20
1
HTIF7
Stream x half transfer interrupt flag (x=7..4)
26
1
TCIF4
Stream x transfer complete interrupt flag (x=7..4)
5
1
TCIF5
Stream x transfer complete interrupt flag (x=7..4)
11
1
TCIF6
Stream x transfer complete interrupt flag (x=7..4)
21
1
TCIF7
Stream x transfer complete interrupt flag (x=7..4)
27
1
TEIF4
Stream x transfer error interrupt flag (x=7..4)
3
1
TEIF5
Stream x transfer error interrupt flag (x=7..4)
9
1
TEIF6
Stream x transfer error interrupt flag (x=7..4)
19
1
TEIF7
Stream x transfer error interrupt flag (x=7..4)
25
1
LIFCR
LIFCR
low interrupt flag clear register
0x8
32
write-only
n
0x0
0x0
CDMEIF0
Stream x clear direct mode error interrupt flag (x = 3..0)
2
1
CDMEIF1
Stream x clear direct mode error interrupt flag (x = 3..0)
8
1
CDMEIF2
Stream x clear direct mode error interrupt flag (x = 3..0)
18
1
CDMEIF3
Stream x clear direct mode error interrupt flag (x = 3..0)
24
1
CFEIF0
Stream x clear FIFO error interrupt flag (x = 3..0)
0
1
CFEIF1
Stream x clear FIFO error interrupt flag (x = 3..0)
6
1
CFEIF2
Stream x clear FIFO error interrupt flag (x = 3..0)
16
1
CFEIF3
Stream x clear FIFO error interrupt flag (x = 3..0)
22
1
CHTIF0
Stream x clear half transfer interrupt flag (x = 3..0)
4
1
CHTIF1
Stream x clear half transfer interrupt flag (x = 3..0)
10
1
CHTIF2
Stream x clear half transfer interrupt flag (x = 3..0)
20
1
CHTIF3
Stream x clear half transfer interrupt flag (x = 3..0)
26
1
CTCIF0
Stream x clear transfer complete interrupt flag (x = 3..0)
5
1
CTCIF1
Stream x clear transfer complete interrupt flag (x = 3..0)
11
1
CTCIF2
Stream x clear transfer complete interrupt flag (x = 3..0)
21
1
CTCIF3
Stream x clear transfer complete interrupt flag (x = 3..0)
27
1
CTEIF0
Stream x clear transfer error interrupt flag (x = 3..0)
3
1
CTEIF1
Stream x clear transfer error interrupt flag (x = 3..0)
9
1
CTEIF2
Stream x clear transfer error interrupt flag (x = 3..0)
19
1
CTEIF3
Stream x clear transfer error interrupt flag (x = 3..0)
25
1
LISR
LISR
low interrupt status register
0x0
32
read-only
n
0x0
0x0
DMEIF0
Stream x direct mode error interrupt flag (x=3..0)
2
1
DMEIF1
Stream x direct mode error interrupt flag (x=3..0)
8
1
DMEIF2
Stream x direct mode error interrupt flag (x=3..0)
18
1
DMEIF3
Stream x direct mode error interrupt flag (x=3..0)
24
1
FEIF0
Stream x FIFO error interrupt flag (x=3..0)
0
1
FEIF1
Stream x FIFO error interrupt flag (x=3..0)
6
1
FEIF2
Stream x FIFO error interrupt flag (x=3..0)
16
1
FEIF3
Stream x FIFO error interrupt flag (x=3..0)
22
1
HTIF0
Stream x half transfer interrupt flag (x=3..0)
4
1
HTIF1
Stream x half transfer interrupt flag (x=3..0)
10
1
HTIF2
Stream x half transfer interrupt flag (x=3..0)
20
1
HTIF3
Stream x half transfer interrupt flag (x=3..0)
26
1
TCIF0
Stream x transfer complete interrupt flag (x = 3..0)
5
1
TCIF1
Stream x transfer complete interrupt flag (x = 3..0)
11
1
TCIF2
Stream x transfer complete interrupt flag (x = 3..0)
21
1
TCIF3
Stream x transfer complete interrupt flag (x = 3..0)
27
1
TEIF0
Stream x transfer error interrupt flag (x=3..0)
3
1
TEIF1
Stream x transfer error interrupt flag (x=3..0)
9
1
TEIF2
Stream x transfer error interrupt flag (x=3..0)
19
1
TEIF3
Stream x transfer error interrupt flag (x=3..0)
25
1
S0CR
S0CR
stream x configuration register
0x10
32
read-write
n
0x0
0x0
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S0FCR
S0FCR
stream x FIFO control register
0x24
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S0M0AR
S0M0AR
stream x memory 0 address register
0x1C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S0M1AR
S0M1AR
stream x memory 1 address register
0x20
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S0NDTR
S0NDTR
stream x number of data register
0x14
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S0PAR
S0PAR
stream x peripheral address register
0x18
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S1CR
S1CR
stream x configuration register
0x28
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S1FCR
S1FCR
stream x FIFO control register
0x3C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S1M0AR
S1M0AR
stream x memory 0 address register
0x34
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S1M1AR
S1M1AR
stream x memory 1 address register
0x38
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S1NDTR
S1NDTR
stream x number of data register
0x2C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S1PAR
S1PAR
stream x peripheral address register
0x30
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S2CR
S2CR
stream x configuration register
0x40
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S2FCR
S2FCR
stream x FIFO control register
0x54
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S2M0AR
S2M0AR
stream x memory 0 address register
0x4C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S2M1AR
S2M1AR
stream x memory 1 address register
0x50
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S2NDTR
S2NDTR
stream x number of data register
0x44
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S2PAR
S2PAR
stream x peripheral address register
0x48
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S3CR
S3CR
stream x configuration register
0x58
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S3FCR
S3FCR
stream x FIFO control register
0x6C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S3M0AR
S3M0AR
stream x memory 0 address register
0x64
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S3M1AR
S3M1AR
stream x memory 1 address register
0x68
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S3NDTR
S3NDTR
stream x number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S3PAR
S3PAR
stream x peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S4CR
S4CR
stream x configuration register
0x70
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S4FCR
S4FCR
stream x FIFO control register
0x84
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S4M0AR
S4M0AR
stream x memory 0 address register
0x7C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S4M1AR
S4M1AR
stream x memory 1 address register
0x80
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S4NDTR
S4NDTR
stream x number of data register
0x74
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S4PAR
S4PAR
stream x peripheral address register
0x78
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S5CR
S5CR
stream x configuration register
0x88
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S5FCR
S5FCR
stream x FIFO control register
0x9C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S5M0AR
S5M0AR
stream x memory 0 address register
0x94
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S5M1AR
S5M1AR
stream x memory 1 address register
0x98
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S5NDTR
S5NDTR
stream x number of data register
0x8C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S5PAR
S5PAR
stream x peripheral address register
0x90
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S6CR
S6CR
stream x configuration register
0xA0
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S6FCR
S6FCR
stream x FIFO control register
0xB4
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S6M0AR
S6M0AR
stream x memory 0 address register
0xAC
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S6M1AR
S6M1AR
stream x memory 1 address register
0xB0
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S6NDTR
S6NDTR
stream x number of data register
0xA4
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S6PAR
S6PAR
stream x peripheral address register
0xA8
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S7CR
S7CR
stream x configuration register
0xB8
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S7FCR
S7FCR
stream x FIFO control register
0xCC
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S7M0AR
S7M0AR
stream x memory 0 address register
0xC4
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S7M1AR
S7M1AR
stream x memory 1 address register
0xC8
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S7NDTR
S7NDTR
stream x number of data register
0xBC
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S7PAR
S7PAR
stream x peripheral address register
0xC0
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
TAMP_STAMP
Tamper and TimeStamp interrupts through the EXTI line
2
EXTI0
EXTI Line0 interrupt
6
EXTI1
EXTI Line1 interrupt
7
EXTI2
EXTI Line2 interrupt
8
EXTI3
EXTI Line3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
EXTI9_5
EXTI Line[9:5] interrupts
23
EXTI15_10
EXTI Line[15:10] interrupts
40
EMR
EMR
Event mask register (EXTI_EMR)
0x4
32
read-write
n
0x0
0x0
MR0
Event Mask on line 0
0
1
MR1
Event Mask on line 1
1
1
MR10
Event Mask on line 10
10
1
MR11
Event Mask on line 11
11
1
MR12
Event Mask on line 12
12
1
MR13
Event Mask on line 13
13
1
MR14
Event Mask on line 14
14
1
MR15
Event Mask on line 15
15
1
MR16
Event Mask on line 16
16
1
MR17
Event Mask on line 17
17
1
MR18
Event Mask on line 18
18
1
MR19
Event Mask on line 19
19
1
MR2
Event Mask on line 2
2
1
MR20
Event Mask on line 20
20
1
MR21
Event Mask on line 21
21
1
MR22
Event Mask on line 22
22
1
MR3
Event Mask on line 3
3
1
MR4
Event Mask on line 4
4
1
MR5
Event Mask on line 5
5
1
MR6
Event Mask on line 6
6
1
MR7
Event Mask on line 7
7
1
MR8
Event Mask on line 8
8
1
MR9
Event Mask on line 9
9
1
FTSR
FTSR
Falling Trigger selection register (EXTI_FTSR)
0xC
32
read-write
n
0x0
0x0
TR0
Falling trigger event configuration of line 0
0
1
TR1
Falling trigger event configuration of line 1
1
1
TR10
Falling trigger event configuration of line 10
10
1
TR11
Falling trigger event configuration of line 11
11
1
TR12
Falling trigger event configuration of line 12
12
1
TR13
Falling trigger event configuration of line 13
13
1
TR14
Falling trigger event configuration of line 14
14
1
TR15
Falling trigger event configuration of line 15
15
1
TR16
Falling trigger event configuration of line 16
16
1
TR17
Falling trigger event configuration of line 17
17
1
TR18
Falling trigger event configuration of line 18
18
1
TR19
Falling trigger event configuration of line 19
19
1
TR2
Falling trigger event configuration of line 2
2
1
TR20
Falling trigger event configuration of line 20
20
1
TR21
Falling trigger event configuration of line 21
21
1
TR22
Falling trigger event configuration of line 22
22
1
TR3
Falling trigger event configuration of line 3
3
1
TR4
Falling trigger event configuration of line 4
4
1
TR5
Falling trigger event configuration of line 5
5
1
TR6
Falling trigger event configuration of line 6
6
1
TR7
Falling trigger event configuration of line 7
7
1
TR8
Falling trigger event configuration of line 8
8
1
TR9
Falling trigger event configuration of line 9
9
1
IMR
IMR
Interrupt mask register (EXTI_IMR)
0x0
32
read-write
n
0x0
0x0
MR0
Interrupt Mask on line 0
0
1
MR1
Interrupt Mask on line 1
1
1
MR10
Interrupt Mask on line 10
10
1
MR11
Interrupt Mask on line 11
11
1
MR12
Interrupt Mask on line 12
12
1
MR13
Interrupt Mask on line 13
13
1
MR14
Interrupt Mask on line 14
14
1
MR15
Interrupt Mask on line 15
15
1
MR16
Interrupt Mask on line 16
16
1
MR17
Interrupt Mask on line 17
17
1
MR18
Interrupt Mask on line 18
18
1
MR19
Interrupt Mask on line 19
19
1
MR2
Interrupt Mask on line 2
2
1
MR20
Interrupt Mask on line 20
20
1
MR21
Interrupt Mask on line 21
21
1
MR22
Interrupt Mask on line 22
22
1
MR3
Interrupt Mask on line 3
3
1
MR4
Interrupt Mask on line 4
4
1
MR5
Interrupt Mask on line 5
5
1
MR6
Interrupt Mask on line 6
6
1
MR7
Interrupt Mask on line 7
7
1
MR8
Interrupt Mask on line 8
8
1
MR9
Interrupt Mask on line 9
9
1
PR
PR
Pending register (EXTI_PR)
0x14
32
read-write
n
0x0
0x0
PR0
Pending bit 0
0
1
PR1
Pending bit 1
1
1
PR10
Pending bit 10
10
1
PR11
Pending bit 11
11
1
PR12
Pending bit 12
12
1
PR13
Pending bit 13
13
1
PR14
Pending bit 14
14
1
PR15
Pending bit 15
15
1
PR16
Pending bit 16
16
1
PR17
Pending bit 17
17
1
PR18
Pending bit 18
18
1
PR19
Pending bit 19
19
1
PR2
Pending bit 2
2
1
PR20
Pending bit 20
20
1
PR21
Pending bit 21
21
1
PR22
Pending bit 22
22
1
PR3
Pending bit 3
3
1
PR4
Pending bit 4
4
1
PR5
Pending bit 5
5
1
PR6
Pending bit 6
6
1
PR7
Pending bit 7
7
1
PR8
Pending bit 8
8
1
PR9
Pending bit 9
9
1
RTSR
RTSR
Rising Trigger selection register (EXTI_RTSR)
0x8
32
read-write
n
0x0
0x0
TR0
Rising trigger event configuration of line 0
0
1
TR1
Rising trigger event configuration of line 1
1
1
TR10
Rising trigger event configuration of line 10
10
1
TR11
Rising trigger event configuration of line 11
11
1
TR12
Rising trigger event configuration of line 12
12
1
TR13
Rising trigger event configuration of line 13
13
1
TR14
Rising trigger event configuration of line 14
14
1
TR15
Rising trigger event configuration of line 15
15
1
TR16
Rising trigger event configuration of line 16
16
1
TR17
Rising trigger event configuration of line 17
17
1
TR18
Rising trigger event configuration of line 18
18
1
TR19
Rising trigger event configuration of line 19
19
1
TR2
Rising trigger event configuration of line 2
2
1
TR20
Rising trigger event configuration of line 20
20
1
TR21
Rising trigger event configuration of line 21
21
1
TR22
Rising trigger event configuration of line 22
22
1
TR3
Rising trigger event configuration of line 3
3
1
TR4
Rising trigger event configuration of line 4
4
1
TR5
Rising trigger event configuration of line 5
5
1
TR6
Rising trigger event configuration of line 6
6
1
TR7
Rising trigger event configuration of line 7
7
1
TR8
Rising trigger event configuration of line 8
8
1
TR9
Rising trigger event configuration of line 9
9
1
SWIER
SWIER
Software interrupt event register (EXTI_SWIER)
0x10
32
read-write
n
0x0
0x0
SWIER0
Software Interrupt on line 0
0
1
SWIER1
Software Interrupt on line 1
1
1
SWIER10
Software Interrupt on line 10
10
1
SWIER11
Software Interrupt on line 11
11
1
SWIER12
Software Interrupt on line 12
12
1
SWIER13
Software Interrupt on line 13
13
1
SWIER14
Software Interrupt on line 14
14
1
SWIER15
Software Interrupt on line 15
15
1
SWIER16
Software Interrupt on line 16
16
1
SWIER17
Software Interrupt on line 17
17
1
SWIER18
Software Interrupt on line 18
18
1
SWIER19
Software Interrupt on line 19
19
1
SWIER2
Software Interrupt on line 2
2
1
SWIER20
Software Interrupt on line 20
20
1
SWIER21
Software Interrupt on line 21
21
1
SWIER22
Software Interrupt on line 22
22
1
SWIER3
Software Interrupt on line 3
3
1
SWIER4
Software Interrupt on line 4
4
1
SWIER5
Software Interrupt on line 5
5
1
SWIER6
Software Interrupt on line 6
6
1
SWIER7
Software Interrupt on line 7
7
1
SWIER8
Software Interrupt on line 8
8
1
SWIER9
Software Interrupt on line 9
9
1
FLASH
FLASH
FLASH
0x0
0x0
0x400
registers
n
FLASH
Flash global interrupt
4
ACR
ACR
Flash access control register
0x0
32
read-write
n
0x0
0x0
DCEN
Data cache enable
10
1
read-write
DCRST
Data cache reset
12
1
read-write
ICEN
Instruction cache enable
9
1
read-write
ICRST
Instruction cache reset
11
1
write-only
LATENCY
Latency
0
3
read-write
PRFTEN
Prefetch enable
8
1
read-write
CR
CR
Control register
0x10
32
read-write
n
0x0
0x0
EOPIE
End of operation interrupt enable
24
1
ERRIE
Error interrupt enable
25
1
LOCK
Lock
31
1
MER
Mass Erase
2
1
PG
Programming
0
1
PSIZE
Program size
8
2
SER
Sector Erase
1
1
SNB
Sector number
3
4
STRT
Start
16
1
KEYR
KEYR
Flash key register
0x4
32
write-only
n
0x0
0x0
KEY
FPEC key
0
32
OPTCR
OPTCR
Flash option control register
0x14
32
read-write
n
0x0
0x0
BOR_LEV
BOR reset Level
2
2
nRST_STDBY
nRST_STDBY User option bytes
7
1
nRST_STOP
nRST_STOP User option bytes
6
1
nWRP
Not write protect
16
5
OPTLOCK
Option lock
0
1
OPTSTRT
Option start
1
1
RDP
Read protect
8
8
SPRMOD
SPRMOD
31
1
WDG_SW
WDG_SW User option bytes
5
1
OPTKEYR
OPTKEYR
Flash option key register
0x8
32
write-only
n
0x0
0x0
OPTKEY
Option byte key
0
32
SR
SR
Status register
0xC
32
read-write
n
0x0
0x0
BSY
Busy
16
1
read-only
EOP
End of operation
0
1
read-write
OPERR
Operation error
1
1
read-write
PGAERR
Programming alignment error
5
1
read-write
PGPERR
Programming parallelism error
6
1
read-write
PGSERR
Programming sequence error
7
1
read-write
WRPERR
Write protection error
4
1
read-write
FPU
Floting point unit
FPU
0x0
0x0
0xD
registers
n
FPU
Floating point interrupt
81
FPU
Floating point interrupt
81
FPCAR
FPCAR
Floating-point context address register
0x4
32
read-write
n
0x0
0x0
ADDRESS
Location of unpopulated floating-point
3
29
FPCCR
FPCCR
Floating-point context control register
0x0
32
read-write
n
0x0
0x0
ASPEN
ASPEN
31
1
BFRDY
BFRDY
6
1
HFRDY
HFRDY
4
1
LSPACT
LSPACT
0
1
LSPEN
LSPEN
30
1
MMRDY
MMRDY
5
1
MONRDY
MONRDY
8
1
THREAD
THREAD
3
1
USER
USER
1
1
FPSCR
FPSCR
Floating-point status control register
0x8
32
read-write
n
0x0
0x0
AHP
Alternative half-precision control bit
26
1
C
Carry condition code flag
29
1
DN
Default NaN mode control bit
25
1
DZC
Division by zero cumulative exception bit.
1
1
FZ
Flush-to-zero mode control bit:
24
1
IDC
Input denormal cumulative exception bit.
7
1
IOC
Invalid operation cumulative exception bit
0
1
IXC
Inexact cumulative exception bit
4
1
N
Negative condition code flag
31
1
OFC
Overflow cumulative exception bit
2
1
RMode
Rounding Mode control field
22
2
UFC
Underflow cumulative exception bit
3
1
V
Overflow condition code flag
28
1
Z
Zero condition code flag
30
1
FPU_CPACR
Floating point unit CPACR
FPU
0x0
0x0
0x5
registers
n
CPACR
CPACR
Coprocessor access control register
0x0
32
read-write
n
0x0
0x0
CP
CP
20
4
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOC
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOH
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
I2C1
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
CCR
CCR
Clock control register
0x1C
32
read-write
n
0x0
0x0
CCR
Clock control register in Fast/Standard mode (Master mode)
0
12
DUTY
Fast mode duty cycle
14
1
F_S
I2C master mode selection
15
1
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACK
Acknowledge enable
10
1
ALERT
SMBus alert
13
1
ENARP
ARP enable
4
1
ENGC
General call enable
6
1
ENPEC
PEC enable
5
1
NOSTRETCH
Clock stretching disable (Slave mode)
7
1
PE
Peripheral enable
0
1
PEC
Packet error checking
12
1
POS
Acknowledge/PEC Position (for data reception)
11
1
SMBTYPE
SMBus type
3
1
SMBUS
SMBus mode
1
1
START
Start generation
8
1
STOP
Stop generation
9
1
SWRST
Software reset
15
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
DMAEN
DMA requests enable
11
1
FREQ
Peripheral clock frequency
0
6
ITBUFEN
Buffer interrupt enable
10
1
ITERREN
Error interrupt enable
8
1
ITEVTEN
Event interrupt enable
9
1
LAST
DMA last transfer
12
1
DR
DR
Data register
0x10
32
read-write
n
0x0
0x0
DR
8-bit data register
0
8
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD10
Interface address
8
2
ADD7
Interface address
1
7
ADDMODE
Addressing mode (slave mode)
15
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
ENDUAL
Dual addressing mode enable
0
1
SR1
SR1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADD10
10-bit header sent (Master mode)
3
1
read-only
ADDR
Address sent (master mode)/matched (slave mode)
1
1
read-only
AF
Acknowledge failure
10
1
read-write
ARLO
Arbitration lost (master mode)
9
1
read-write
BERR
Bus error
8
1
read-write
BTF
Byte transfer finished
2
1
read-only
OVR
Overrun/Underrun
11
1
read-write
PECERR
PEC Error in reception
12
1
read-write
RxNE
Data register not empty (receivers)
6
1
read-only
SB
Start bit (Master mode)
0
1
read-only
SMBALERT
SMBus alert
15
1
read-write
STOPF
Stop detection (slave mode)
4
1
read-only
TIMEOUT
Timeout or Tlow error
14
1
read-write
TxE
Data register empty (transmitters)
7
1
read-only
SR2
SR2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSY
Bus busy
1
1
DUALF
Dual flag (Slave mode)
7
1
GENCALL
General call address (Slave mode)
4
1
MSL
Master/slave
0
1
PEC
acket error checking register
8
8
SMBDEFAULT
SMBus device default address (Slave mode)
5
1
SMBHOST
SMBus host header (Slave mode)
6
1
TRA
Transmitter/receiver
2
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
I2C2
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
CCR
CCR
Clock control register
0x1C
32
read-write
n
0x0
0x0
CCR
Clock control register in Fast/Standard mode (Master mode)
0
12
DUTY
Fast mode duty cycle
14
1
F_S
I2C master mode selection
15
1
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACK
Acknowledge enable
10
1
ALERT
SMBus alert
13
1
ENARP
ARP enable
4
1
ENGC
General call enable
6
1
ENPEC
PEC enable
5
1
NOSTRETCH
Clock stretching disable (Slave mode)
7
1
PE
Peripheral enable
0
1
PEC
Packet error checking
12
1
POS
Acknowledge/PEC Position (for data reception)
11
1
SMBTYPE
SMBus type
3
1
SMBUS
SMBus mode
1
1
START
Start generation
8
1
STOP
Stop generation
9
1
SWRST
Software reset
15
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
DMAEN
DMA requests enable
11
1
FREQ
Peripheral clock frequency
0
6
ITBUFEN
Buffer interrupt enable
10
1
ITERREN
Error interrupt enable
8
1
ITEVTEN
Event interrupt enable
9
1
LAST
DMA last transfer
12
1
DR
DR
Data register
0x10
32
read-write
n
0x0
0x0
DR
8-bit data register
0
8
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD10
Interface address
8
2
ADD7
Interface address
1
7
ADDMODE
Addressing mode (slave mode)
15
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
ENDUAL
Dual addressing mode enable
0
1
SR1
SR1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADD10
10-bit header sent (Master mode)
3
1
read-only
ADDR
Address sent (master mode)/matched (slave mode)
1
1
read-only
AF
Acknowledge failure
10
1
read-write
ARLO
Arbitration lost (master mode)
9
1
read-write
BERR
Bus error
8
1
read-write
BTF
Byte transfer finished
2
1
read-only
OVR
Overrun/Underrun
11
1
read-write
PECERR
PEC Error in reception
12
1
read-write
RxNE
Data register not empty (receivers)
6
1
read-only
SB
Start bit (Master mode)
0
1
read-only
SMBALERT
SMBus alert
15
1
read-write
STOPF
Stop detection (slave mode)
4
1
read-only
TIMEOUT
Timeout or Tlow error
14
1
read-write
TxE
Data register empty (transmitters)
7
1
read-only
SR2
SR2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSY
Bus busy
1
1
DUALF
Dual flag (Slave mode)
7
1
GENCALL
General call address (Slave mode)
4
1
MSL
Master/slave
0
1
PEC
acket error checking register
8
8
SMBDEFAULT
SMBus device default address (Slave mode)
5
1
SMBHOST
SMBus host header (Slave mode)
6
1
TRA
Transmitter/receiver
2
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
I2C4
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C4_EV
I2C4 event interrupt
95
I2C4_ER
I2C2 error interrupt
96
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
IWDG
Independent watchdog
IWDG
0x0
0x0
0x400
registers
n
KR
KR
Key register
0x0
32
write-only
n
0x0
0x0
KEY
Key value
0
16
PR
PR
Prescaler register
0x4
32
read-write
n
0x0
0x0
PR
Prescaler divider
0
3
RLR
RLR
Reload register
0x8
32
read-write
n
0x0
0x0
RL
Watchdog counter reload value
0
12
SR
SR
Status register
0xC
32
read-only
n
0x0
0x0
PVU
Watchdog prescaler value update
0
1
RVU
Watchdog counter reload value update
1
1
LPTIM1
Low power timer
LPTIM
0x0
0x0
0x400
registers
n
LPTIM1
LPTimer global interrupt
97
ARR
ARR
Autoreload Register
0x18
32
read-write
n
0x0
0x0
ARR
Auto reload value
0
16
CFGR
CFGR
Configuration Register
0xC
32
read-write
n
0x0
0x0
CKFLT
Configurable digital filter for external clock
3
2
CKPOL
Clock Polarity
1
2
CKSEL
Clock selector
0
1
COUNTMODE
counter mode enabled
23
1
ENC
Encoder mode enable
24
1
PRELOAD
Registers update mode
22
1
PRESC
Clock prescaler
9
3
TIMOUT
Timeout enable
19
1
TRGFLT
Configurable digital filter for trigger
6
2
TRIGEN
Trigger enable and polarity
17
2
TRIGSEL
Trigger selector
13
3
WAVE
Waveform shape
20
1
WAVPOL
Waveform shape polarity
21
1
CMP
CMP
Compare Register
0x14
32
read-write
n
0x0
0x0
CMP
Compare value
0
16
CNT
CNT
Counter Register
0x1C
32
read-only
n
0x0
0x0
CNT
Counter value
0
16
CR
CR
Control Register
0x10
32
read-write
n
0x0
0x0
CNTSTRT
Timer start in continuous mode
2
1
ENABLE
LPTIM Enable
0
1
SNGSTRT
LPTIM start in single mode
1
1
ICR
ICR
Interrupt Clear Register
0x4
32
write-only
n
0x0
0x0
ARRMCF
Autoreload match Clear Flag
1
1
ARROKCF
Autoreload register update OK Clear Flag
4
1
CMPMCF
compare match Clear Flag
0
1
CMPOKCF
Compare register update OK Clear Flag
3
1
DOWNCF
Direction change to down Clear Flag
6
1
EXTTRIGCF
External trigger valid edge Clear Flag
2
1
UPCF
Direction change to UP Clear Flag
5
1
IER
IER
Interrupt Enable Register
0x8
32
read-write
n
0x0
0x0
ARRMIE
Autoreload match Interrupt Enable
1
1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
CMPMIE
Compare match Interrupt Enable
0
1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
DOWNIE
Direction change to down Interrupt Enable
6
1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
UPIE
Direction change to UP Interrupt Enable
5
1
ISR
ISR
Interrupt and Status Register
0x0
32
read-only
n
0x0
0x0
ARRM
Autoreload match
1
1
ARROK
Autoreload register update OK
4
1
CMPM
Compare match
0
1
CMPOK
Compare register update OK
3
1
DOWN
Counter direction change up to down
6
1
EXTTRIG
External trigger edge event
2
1
UP
Counter direction change down to up
5
1
OPTR
OPTR
Option Register
0x20
32
read-write
n
0x0
0x0
OR
OR
0
2
MPU
Memory protection unit
MPU
0x0
0x0
0x15
registers
n
CTRL
MPU_CTRL
MPU control register
0x4
32
read-only
n
0x0
0x0
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard fault
1
1
PRIVDEFENA
Enable priviliged software access to default memory map
2
1
RASR
MPU_RASR
MPU region attribute and size register
0x10
32
read-write
n
0x0
0x0
AP
Access permission
24
3
B
memory attribute
16
1
C
memory attribute
17
1
ENABLE
Region enable bit.
0
1
S
Shareable memory attribute
18
1
SIZE
Size of the MPU protection region
1
5
SRD
Subregion disable bits
8
8
TEX
memory attribute
19
3
XN
Instruction access disable bit
28
1
RBAR
MPU_RBAR
MPU region base address register
0xC
32
read-write
n
0x0
0x0
ADDR
Region base address field
5
27
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
RNR
MPU_RNR
MPU region number register
0x8
32
read-write
n
0x0
0x0
REGION
MPU region
0
8
TYPER
MPU_TYPER
MPU type register
0x0
32
read-only
n
0x0
0x0
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction regions
16
8
SEPARATE
Separate flag
0
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x351
registers
n
IABR0
IABR0
Interrupt Active Bit Register
0x200
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x204
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR2
IABR2
Interrupt Active Bit Register
0x208
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
ICER0
ICER0
Interrupt Clear-Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable Register
0x84
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER2
ICER2
Interrupt Clear-Enable Register
0x88
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR0
ICPR0
Interrupt Clear-Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending Register
0x184
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR2
ICPR2
Interrupt Clear-Pending Register
0x188
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
IPR0
IPR0
Interrupt Priority Register
0x300
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x304
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x328
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x32C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x330
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x334
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x338
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR15
IPR15
Interrupt Priority Register
0x33C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR16
IPR16
Interrupt Priority Register
0x340
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR17
IPR17
Interrupt Priority Register
0x344
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR18
IPR18
Interrupt Priority Register
0x348
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR19
IPR19
Interrupt Priority Register
0x34C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x308
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x30C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x310
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x314
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x318
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x31C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x320
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x324
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
ISER0
ISER0
Interrupt Set-Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x4
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER2
ISER2
Interrupt Set-Enable Register
0x8
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x104
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR2
ISPR2
Interrupt Set-Pending Register
0x108
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
NVIC_STIR
Nested vectored interrupt controller
NVIC
0x0
0x0
0x5
registers
n
STIR
STIR
Software trigger interrupt register
0x0
32
read-write
n
0x0
0x0
INTID
Software generated interrupt ID
0
9
PWR
Power control
PWR
0x0
0x0
0x400
registers
n
PVD
PVD through EXTI Line detection interrupt
1
CR
CR
power control register
0x0
32
read-write
n
0x0
0x0
ADCDC1
ADCDC1
13
1
CSBF
Clear standby flag
3
1
CWUF
Clear wakeup flag
2
1
DBP
Disable backup domain write protection
8
1
FPDS
Flash power down in Stop mode
9
1
LPDS
Low-power deep sleep
0
1
PDDS
Power down deepsleep
1
1
PLS
PVD level selection
5
3
PVDE
Power voltage detector enable
4
1
VOS
Regulator voltage scaling output selection
14
2
CSR
CSR
power control/status register
0x4
32
read-write
n
0x0
0x0
BRE
Backup regulator enable
9
1
read-write
BRR
Backup regulator ready
3
1
read-only
EWUP1
Enable WKUP1 pin
8
1
read-write
EWUP2
Enable WKUP2 pin
7
1
read-write
EWUP3
Enable WKUP3 pin
6
1
read-write
PVDO
PVD output
2
1
read-only
SBF
Standby flag
1
1
read-only
VOSRDY
Regulator voltage scaling output selection ready bit
14
1
read-write
WUF
Wakeup flag
0
1
read-only
RCC
Reset and clock control
RCC
0x0
0x0
0x400
registers
n
RCC
RCC global interrupt
5
AHB1ENR
AHB1ENR
AHB1 peripheral clock register
0x30
32
read-write
n
0x0
0x0
CRCEN
CRC clock enable
12
1
DMA1EN
DMA1 clock enable
21
1
DMA2EN
DMA2 clock enable
22
1
GPIOAEN
IO port A clock enable
0
1
GPIOBEN
IO port B clock enable
1
1
GPIOCEN
IO port C clock enable
2
1
GPIOHEN
IO port H clock enable
7
1
RNGEN
RNG clock enable
31
1
AHB1LPENR
AHB1LPENR
AHB1 peripheral clock enable in low power mode register
0x50
32
read-write
n
0x0
0x0
CRCLPEN
CRC clock enable during Sleep mode
12
1
DMA1LPEN
DMA1 clock enable during Sleep mode
21
1
DMA2LPEN
DMA2 clock enable during Sleep mode
22
1
FLITFLPEN
Flash interface clock enable during Sleep mode
15
1
GPIOALPEN
IO port A clock enable during sleep mode
0
1
GPIOBLPEN
IO port B clock enable during Sleep mode
1
1
GPIOCLPEN
IO port C clock enable during Sleep mode
2
1
GPIOHLPEN
IO port H clock enable during Sleep mode
7
1
RNGLPEN
RNG clock enable during sleep mode
31
1
SRAM1LPEN
SRAM 1interface clock enable during Sleep mode
16
1
AHB1RSTR
AHB1RSTR
AHB1 peripheral reset register
0x10
32
read-write
n
0x0
0x0
CRCRST
CRC reset
12
1
DMA1RST
DMA2 reset
21
1
DMA2RST
DMA2 reset
22
1
GPIOARST
IO port A reset
0
1
GPIOBRST
IO port B reset
1
1
GPIOCRST
IO port C reset
2
1
GPIOHRST
IO port H reset
7
1
RNGRST
RNGRST
31
1
APB1ENR
APB1ENR
APB1 peripheral clock enable register
0x40
32
read-write
n
0x0
0x0
DACEN
DAC interface clock enable
29
1
I2C1EN
I2C1 clock enable
21
1
I2C2EN
I2C2 clock enable
22
1
I2C4EN
I2C4 clock enable
24
1
LPTIM1EN
LPTIM1 clock enable
9
1
PWREN
Power interface clock enable
28
1
RTCAPBEN
RTC APB clock enable
10
1
SPI2EN
SPI2 clock enable
14
1
TIM5EN
TIM5 clock enable
3
1
TIM6EN
TIM6 clock enable
4
1
USART2EN
USART 2 clock enable
17
1
WWDGEN
Window watchdog clock enable
11
1
APB1LPENR
APB1LPENR
APB1 peripheral clock enable in low power mode register
0x60
32
read-write
n
0x0
0x0
DACLPEN
DAC interface clock enable during sleep mode
29
1
I2C1LPEN
I2C1 clock enable during Sleep mode
21
1
I2C2LPEN
I2C2 clock enable during Sleep mode
22
1
I2C4LPEN
I2C4 clock enable during Sleep mode
24
1
LPTIM1LPEN
LPTIM1 clock enable during sleep mode
9
1
PWRLPEN
Power interface clock enable during Sleep mode
28
1
RTCAPBLPEN
RTC APB clock enable during sleep mode
10
1
SPI2LPEN
SPI2 clock enable during Sleep mode
14
1
TIM5LPEN
TIM5 clock enable during Sleep mode
3
1
TIM6LPEN
TIM6 clock enable during Sleep mode
4
1
USART2LPEN
USART2 clock enable during Sleep mode
17
1
WWDGLPEN
Window watchdog clock enable during Sleep mode
11
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register
0x20
32
read-write
n
0x0
0x0
DACRST
DAC reset
29
1
I2C1RST
I2C 1 reset
21
1
I2C2RST
I2C 2 reset
22
1
I2C4RST
I2C4 reset
24
1
LPTIM1RST
LPTIM1 reset
9
1
PWRRST
Power interface reset
28
1
SPI2RST
SPI 2 reset
14
1
TIM5RST
TIM5 reset
3
1
TIM6RST
TIM6 reset
4
1
UART2RST
USART 2 reset
17
1
WWDGRST
Window watchdog reset
11
1
APB2ENR
APB2ENR
APB2 peripheral clock enable register
0x44
32
read-write
n
0x0
0x0
ADC1EN
ADC1 clock enable
8
1
EXTITEN
EXTI ans external IT clock enable
15
1
SPI1EN
SPI1 clock enable
12
1
SPI5EN
SPI5 clock enable
20
1
SYSCFGEN
System configuration controller clock enable
14
1
TIM11EN
TIM11 clock enable
18
1
TIM1EN
TIM1 clock enable
0
1
TIM9EN
TIM9 clock enable
16
1
USART1EN
USART1 clock enable
4
1
USART6EN
USART6 clock enable
5
1
APB2LPENR
APB2LPENR
APB2 peripheral clock enabled in low power mode register
0x64
32
read-write
n
0x0
0x0
ADC1LPEN
ADC1 clock enable during Sleep mode
8
1
EXTITLPEN
EXTI and External IT clock enable during sleep mode
15
1
SDIOLPEN
SDIO clock enable during Sleep mode
11
1
SPI1LPEN
SPI 1 clock enable during Sleep mode
12
1
SYSCFGLPEN
System configuration controller clock enable during Sleep mode
14
1
TIM11LPEN
TIM11 clock enable during Sleep mode
18
1
TIM1LPEN
TIM1 clock enable during Sleep mode
0
1
TIM9LPEN
TIM9 clock enable during sleep mode
16
1
USART1LPEN
USART1 clock enable during Sleep mode
4
1
USART6LPEN
USART6 clock enable during Sleep mode
5
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x24
32
read-write
n
0x0
0x0
ADCRST
ADC interface reset (common to all ADCs)
8
1
SPI1RST
SPI 1 reset
12
1
SYSCFGRST
System configuration controller reset
14
1
TIM11RST
TIM11 reset
18
1
TIM1RST
TIM1 reset
0
1
TIM9RST
TIM9 reset
16
1
USART1RST
USART1 reset
4
1
USART6RST
USART6 reset
5
1
BDCR
BDCR
Backup domain control register
0x70
32
read-write
n
0x0
0x0
BDRST
Backup domain software reset
16
1
read-write
LSEBYP
External low-speed oscillator bypass
2
1
read-write
LSEON
External low-speed oscillator enable
0
1
read-write
LSERDY
External low-speed oscillator ready
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSEL0
RTC clock source selection
8
1
read-write
RTCSEL1
RTC clock source selection
9
1
read-write
CFGR
CFGR
clock configuration register
0x8
32
read-write
n
0x0
0x0
HPRE
AHB prescaler
4
4
read-write
MCO1
Microcontroller clock output 1
21
2
read-write
MCO1EN
MCO output enable
8
1
read-write
MCO1PRE
MCO1 prescaler
24
3
read-write
MCO2
Microcontroller clock output 2
30
2
read-write
MCO2EN
MCO output enable
9
1
read-write
MCO2PRE
MCO2 prescaler
27
3
read-write
PPRE1
APB Low speed prescaler (APB1)
10
3
read-write
PPRE2
APB high-speed prescaler (APB2)
13
3
read-write
RTCPRE
HSE division factor for RTC clock
16
5
read-write
SW0
System clock switch
0
1
read-write
SW1
System clock switch
1
1
read-write
SWS0
System clock switch status
2
1
read-only
SWS1
System clock switch status
3
1
read-only
CIR
CIR
clock interrupt register
0xC
32
read-write
n
0x0
0x0
CSSC
Clock security system interrupt clear
23
1
write-only
CSSF
Clock security system interrupt flag
7
1
read-only
HSERDYC
HSE ready interrupt clear
19
1
write-only
HSERDYF
HSE ready interrupt flag
3
1
read-only
HSERDYIE
HSE ready interrupt enable
11
1
read-write
HSIRDYC
HSI ready interrupt clear
18
1
write-only
HSIRDYF
HSI ready interrupt flag
2
1
read-only
HSIRDYIE
HSI ready interrupt enable
10
1
read-write
LSERDYC
LSE ready interrupt clear
17
1
write-only
LSERDYF
LSE ready interrupt flag
1
1
read-only
LSERDYIE
LSE ready interrupt enable
9
1
read-write
LSIRDYC
LSI ready interrupt clear
16
1
write-only
LSIRDYF
LSI ready interrupt flag
0
1
read-only
LSIRDYIE
LSI ready interrupt enable
8
1
read-write
PLLI2SRDYC
PLLI2S ready interrupt clear
21
1
write-only
PLLRDYC
Main PLL(PLL) ready interrupt clear
20
1
write-only
PLLRDYF
Main PLL (PLL) ready interrupt flag
4
1
read-only
PLLRDYIE
Main PLL (PLL) ready interrupt enable
12
1
read-write
CR
CR
clock control register
0x0
32
read-write
n
0x0
0x0
CSSON
Clock security system enable
19
1
read-write
HSEBYP
HSE clock bypass
18
1
read-write
HSEON
HSE clock enable
16
1
read-write
HSERDY
HSE clock ready flag
17
1
read-only
HSICAL
Internal high-speed clock calibration
8
8
read-only
HSION
Internal high-speed clock enable
0
1
read-write
HSIRDY
Internal high-speed clock ready flag
1
1
read-only
HSITRIM
Internal high-speed clock trimming
3
5
read-write
PLLON
Main PLL (PLL) enable
24
1
read-write
PLLRDY
Main PLL (PLL) clock ready flag
25
1
read-only
CSR
CSR
clock control and status register
0x74
32
read-write
n
0x0
0x0
BORRSTF
BOR reset flag
25
1
read-write
LPWRRSTF
Low-power reset flag
31
1
read-write
LSION
Internal low-speed oscillator enable
0
1
read-write
LSIRDY
Internal low-speed oscillator ready
1
1
read-only
PADRSTF
PIN reset flag
26
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
RMVF
Remove reset flag
24
1
read-write
SFTRSTF
Software reset flag
28
1
read-write
WDGRSTF
Independent watchdog reset flag
29
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
DCKCFGR
DCKCFGR
DCKCFGR register
0x8C
32
read-write
n
0x0
0x0
I2SSRC
I2SSRC
25
2
TIMPRE
TIMPRE
24
1
DCKCFGR2
DCKCFGR2
DCKCFGR2 register
0x94
32
read-write
n
0x0
0x0
I2C4SEL
I2C4SEL
22
2
LPTIM1SEL
LPTIM1SEL
30
2
PLLCFGR
PLLCFGR
PLL configuration register
0x4
32
read-write
n
0x0
0x0
PLLM0
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
0
1
PLLM1
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
1
1
PLLM2
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
2
1
PLLM3
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
3
1
PLLM4
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
4
1
PLLM5
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
5
1
PLLN0
Main PLL (PLL) multiplication factor for VCO
6
1
PLLN1
Main PLL (PLL) multiplication factor for VCO
7
1
PLLN2
Main PLL (PLL) multiplication factor for VCO
8
1
PLLN3
Main PLL (PLL) multiplication factor for VCO
9
1
PLLN4
Main PLL (PLL) multiplication factor for VCO
10
1
PLLN5
Main PLL (PLL) multiplication factor for VCO
11
1
PLLN6
Main PLL (PLL) multiplication factor for VCO
12
1
PLLN7
Main PLL (PLL) multiplication factor for VCO
13
1
PLLN8
Main PLL (PLL) multiplication factor for VCO
14
1
PLLP0
Main PLL (PLL) division factor for main system clock
16
1
PLLP1
Main PLL (PLL) division factor for main system clock
17
1
PLLQ0
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
24
1
PLLQ1
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
25
1
PLLQ2
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
26
1
PLLQ3
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
27
1
PLLR1
PLLR1
28
1
PLLR2
PLLR2
29
1
PLLR3
PLLR3
30
1
PLLSRC
Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
22
1
SSCGR
SSCGR
spread spectrum clock generation register
0x80
32
read-write
n
0x0
0x0
INCSTEP
Incrementation step
13
15
MODPER
Modulation period
0
13
SPREADSEL
Spread Select
30
1
SSCGEN
Spread spectrum modulation enable
31
1
RNG
Random number generator
RNG
0x0
0x0
0x400
registers
n
RNG
RNG global interrupt
80
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
IE
Interrupt enable
3
1
RNGEN
Random number generator enable
2
1
DR
DR
data register
0x8
32
read-only
n
0x0
0x0
RNDATA
Random data
0
32
SR
SR
status register
0x4
32
read-write
n
0x0
0x0
CECS
Clock error current status
1
1
read-only
CEIS
Clock error interrupt status
5
1
read-write
DRDY
Data ready
0
1
read-only
SECS
Seed error current status
2
1
read-only
SEIS
Seed error interrupt status
6
1
read-write
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
RTC_WKUP
RTC Wakeup interrupt through the EXTI line
3
ALRMAR
ALRMAR
alarm A register
0x1C
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm A seconds mask
7
1
MSK2
Alarm A minutes mask
15
1
MSK3
Alarm A hours mask
23
1
MSK4
Alarm A date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMASSR
ALRMASSR
alarm A sub second register
0x44
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
ALRMBR
ALRMBR
alarm B register
0x20
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm B seconds mask
7
1
MSK2
Alarm B minutes mask
15
1
MSK3
Alarm B hours mask
23
1
MSK4
Alarm B date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMBSSR
ALRMBSSR
alarm B sub second register
0x48
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
BKP0R
BKP0R
backup register
0x50
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP10R
BKP10R
backup register
0x78
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP11R
BKP11R
backup register
0x7C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP12R
BKP12R
backup register
0x80
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP13R
BKP13R
backup register
0x84
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP14R
BKP14R
backup register
0x88
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP15R
BKP15R
backup register
0x8C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP16R
BKP16R
backup register
0x90
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP17R
BKP17R
backup register
0x94
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP18R
BKP18R
backup register
0x98
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP19R
BKP19R
backup register
0x9C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP1R
BKP1R
backup register
0x54
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP2R
BKP2R
backup register
0x58
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP3R
BKP3R
backup register
0x5C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP4R
BKP4R
backup register
0x60
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP5R
BKP5R
backup register
0x64
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP6R
BKP6R
backup register
0x68
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP7R
BKP7R
backup register
0x6C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP8R
BKP8R
backup register
0x70
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP9R
BKP9R
backup register
0x74
32
read-write
n
0x0
0x0
BKP
BKP
0
32
CALIBR
CALIBR
calibration register
0x18
32
read-write
n
0x0
0x0
DC
Digital calibration
0
5
DCS
Digital calibration sign
7
1
CALR
CALR
calibration register
0x3C
32
read-write
n
0x0
0x0
CALM
Calibration minus
0
9
CALP
Increase frequency of RTC by 488.5 ppm
15
1
CALW16
Use a 16-second calibration cycle period
13
1
CALW8
Use an 8-second calibration cycle period
14
1
CR
CR
control register
0x8
32
read-write
n
0x0
0x0
ADD1H
Add 1 hour (summer time change)
16
1
ALRAE
Alarm A enable
8
1
ALRAIE
Alarm A interrupt enable
12
1
ALRBE
Alarm B enable
9
1
ALRBIE
Alarm B interrupt enable
13
1
BKP
Backup
18
1
BYPSHAD
Bypass the shadow registers
5
1
COE
Calibration output enable
23
1
COSEL
Calibration Output selection
19
1
DCE
Coarse digital calibration enable
7
1
FMT
Hour format
6
1
OSEL
Output selection
21
2
POL
Output polarity
20
1
REFCKON
Reference clock detection enable (50 or 60 Hz)
4
1
SUB1H
Subtract 1 hour (winter time change)
17
1
TSE
Time stamp enable
11
1
TSEDGE
Time-stamp event active edge
3
1
TSIE
Time-stamp interrupt enable
15
1
WCKSEL
Wakeup clock selection
0
3
WUTE
Wakeup timer enable
10
1
WUTIE
Wakeup timer interrupt enable
14
1
DR
DR
date register
0x4
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
ISR
ISR
initialization and status register
0xC
32
read-write
n
0x0
0x0
ALRAF
Alarm A flag
8
1
read-write
ALRAWF
Alarm A write flag
0
1
read-only
ALRBF
Alarm B flag
9
1
read-write
ALRBWF
Alarm B write flag
1
1
read-only
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-only
INITS
Initialization status flag
4
1
read-only
RECALPF
Recalibration pending Flag
16
1
read-only
RSF
Registers synchronization flag
5
1
read-write
SHPF
Shift operation pending
3
1
read-write
TAMP1F
Tamper detection flag
13
1
read-write
TAMP2F
TAMPER2 detection flag
14
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVF
Time-stamp overflow flag
12
1
read-write
WUTF
Wakeup timer flag
10
1
read-write
WUTWF
Wakeup timer write flag
2
1
read-only
PRER
PRER
prescaler register
0x10
32
read-write
n
0x0
0x0
PREDIV_A
Asynchronous prescaler factor
16
7
PREDIV_S
Synchronous prescaler factor
0
15
SHIFTR
SHIFTR
shift control register
0x2C
32
write-only
n
0x0
0x0
ADD1S
Add one second
31
1
SUBFS
Subtract a fraction of a second
0
15
SSR
SSR
sub second register
0x28
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TAFCR
TAFCR
tamper and alternate function configuration register
0x40
32
read-write
n
0x0
0x0
ALARMOUTTYPE
AFO_ALARM output type
18
1
TAMP1E
Tamper 1 detection enable
0
1
TAMP1INSEL
TAMPER1 mapping
16
1
TAMP1TRG
Active level for tamper 1
1
1
TAMP2E
Tamper 2 detection enable
3
1
TAMP2TRG
Active level for tamper 2
4
1
TAMPFLT
Tamper filter count
11
2
TAMPFREQ
Tamper sampling frequency
8
3
TAMPIE
Tamper interrupt enable
2
1
TAMPPRCH
Tamper precharge duration
13
2
TAMPPUDIS
TAMPER pull-up disable
15
1
TAMPTS
Activate timestamp on tamper detection event
7
1
TSINSEL
TIMESTAMP mapping
17
1
TR
TR
time register
0x0
32
read-write
n
0x0
0x0
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
TSDR
TSDR
time stamp date register
0x34
32
read-only
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
TSSSR
TSSSR
timestamp sub second register
0x38
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TSTR
TSTR
time stamp time register
0x30
32
read-only
n
0x0
0x0
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WPR
WPR
write protection register
0x24
32
write-only
n
0x0
0x0
KEY
Write protection key
0
8
WUTR
WUTR
wakeup timer register
0x14
32
read-write
n
0x0
0x0
WUT
Wakeup auto-reload value bits
0
16
SCB
System control block
SCB
0x0
0x0
0x41
registers
n
AFSR
AFSR
Auxiliary fault status register
0x3C
32
read-write
n
0x0
0x0
IMPDEF
Implementation defined
0
32
AIRCR
AIRCR
Application interrupt and reset control register
0xC
32
read-write
n
0x0
0x0
ENDIANESS
ENDIANESS
15
1
PRIGROUP
PRIGROUP
8
3
SYSRESETREQ
SYSRESETREQ
2
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
VECTKEYSTAT
Register key
16
16
VECTRESET
VECTRESET
0
1
BFAR
BFAR
Bus fault address register
0x38
32
read-write
n
0x0
0x0
BFAR
Bus fault address
0
32
CCR
CCR
Configuration and control register
0x14
32
read-write
n
0x0
0x0
BFHFNMIGN
BFHFNMIGN
8
1
DIV_0_TRP
DIV_0_TRP
4
1
NONBASETHRDENA
Configures how the processor enters Thread mode
0
1
STKALIGN
STKALIGN
9
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
USERSETMPEND
USERSETMPEND
1
1
CFSR_UFSR_BFSR_MMFSR
CFSR_UFSR_BFSR_MMFSR
Configurable fault status register
0x28
32
read-write
n
0x0
0x0
BFARVALID
Bus Fault Address Register (BFAR) valid flag
15
1
DIVBYZERO
Divide by zero usage fault
25
1
IACCVIOL
Instruction access violation flag
1
1
IBUSERR
Instruction bus error
8
1
IMPRECISERR
Imprecise data bus error
10
1
INVPC
Invalid PC load usage fault
18
1
INVSTATE
Invalid state usage fault
17
1
LSPERR
Bus fault on floating-point lazy state preservation
13
1
MLSPERR
MLSPERR
5
1
MMARVALID
Memory Management Fault Address Register (MMAR) valid flag
7
1
MSTKERR
Memory manager fault on stacking for exception entry.
4
1
MUNSTKERR
Memory manager fault on unstacking for a return from exception
3
1
NOCP
No coprocessor usage fault.
19
1
PRECISERR
Precise data bus error
9
1
STKERR
Bus fault on stacking for exception entry
12
1
UNALIGNED
Unaligned access usage fault
24
1
UNDEFINSTR
Undefined instruction usage fault
16
1
UNSTKERR
Bus fault on unstacking for a return from exception
11
1
CPUID
CPUID
CPUID base register
0x0
32
read-only
n
0x0
0x0
Constant
Reads as 0xF
16
4
Implementer
Implementer code
24
8
PartNo
Part number of the processor
4
12
Revision
Revision number
0
4
Variant
Variant number
20
4
HFSR
HFSR
Hard fault status register
0x2C
32
read-write
n
0x0
0x0
DEBUG_VT
Reserved for Debug use
31
1
FORCED
Forced hard fault
30
1
VECTTBL
Vector table hard fault
1
1
ICSR
ICSR
Interrupt control and state register
0x4
32
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag
22
1
NMIPENDSET
NMI set-pending bit.
31
1
PENDSTCLR
SysTick exception clear-pending bit
25
1
PENDSTSET
SysTick exception set-pending bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
RETTOBASE
Return to base level
11
1
VECTACTIVE
Active vector
0
9
VECTPENDING
Pending vector
12
7
MMFAR
MMFAR
Memory management fault address register
0x34
32
read-write
n
0x0
0x0
MMFAR
Memory management fault address
0
32
SCR
SCR
System control register
0x10
32
read-write
n
0x0
0x0
SEVEONPEND
Send Event on Pending bit
4
1
SLEEPDEEP
SLEEPDEEP
2
1
SLEEPONEXIT
SLEEPONEXIT
1
1
SHCRS
SHCRS
System handler control and state register
0x24
32
read-write
n
0x0
0x0
BUSFAULTACT
Bus fault exception active bit
1
1
BUSFAULTENA
Bus fault enable bit
17
1
BUSFAULTPENDED
Bus fault exception pending bit
14
1
MEMFAULTACT
Memory management fault exception active bit
0
1
MEMFAULTENA
Memory management fault enable bit
16
1
MEMFAULTPENDED
Memory management fault exception pending bit
13
1
MONITORACT
Debug monitor active bit
8
1
PENDSVACT
PendSV exception active bit
10
1
SVCALLACT
SVC call active bit
7
1
SVCALLPENDED
SVC call pending bit
15
1
SYSTICKACT
SysTick exception active bit
11
1
USGFAULTACT
Usage fault exception active bit
3
1
USGFAULTENA
Usage fault enable bit
18
1
USGFAULTPENDED
Usage fault exception pending bit
12
1
SHPR1
SHPR1
System handler priority registers
0x18
32
read-write
n
0x0
0x0
PRI_4
Priority of system handler 4
0
8
PRI_5
Priority of system handler 5
8
8
PRI_6
Priority of system handler 6
16
8
SHPR2
SHPR2
System handler priority registers
0x1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11
24
8
SHPR3
SHPR3
System handler priority registers
0x20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14
16
8
PRI_15
Priority of system handler 15
24
8
VTOR
VTOR
Vector table offset register
0x8
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset field
9
21
SCB_ACTRL
System control block ACTLR
SCB
0x0
0x0
0x5
registers
n
ACTRL
ACTRL
Auxiliary control register
0x0
32
read-write
n
0x0
0x0
DISDEFWBUF
DISDEFWBUF
1
1
DISFOLD
DISFOLD
2
1
DISFPCA
DISFPCA
8
1
DISMCYCINT
DISMCYCINT
0
1
DISOOFP
DISOOFP
9
1
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI1 global interrupt
35
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI2
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI2
SPI2 global interrupt
36
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI5
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
STK
SysTick timer
STK
0x0
0x0
0x11
registers
n
CALIB
CALIB
SysTick calibration value register
0xC
32
read-write
n
0x0
0x0
NOREF
NOREF flag. Reads as zero
31
1
SKEW
SKEW flag: Indicates whether the TENMS value is exact
30
1
TENMS
Calibration value
0
24
CTRL
CTRL
SysTick control and status register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request enable
1
1
LOAD
LOAD
SysTick reload value register
0x4
32
read-write
n
0x0
0x0
RELOAD
RELOAD value
0
24
VAL
VAL
SysTick current value register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current counter value
0
24
SYSCFG
System configuration controller
SYSCFG
0x0
0x0
0x400
registers
n
CFGR
CFGR
Configuration register
0x2C
32
read-write
n
0x0
0x0
FMPI2C1_SCL
FMPI2C1_SCL
0
1
FMPI2C1_SDA
FMPI2C1_SDA
1
1
CMPCR
CMPCR
Compensation cell control register
0x20
32
read-only
n
0x0
0x0
CMP_PD
Compensation cell power-down
0
1
READY
READY
8
1
EXTICR1
EXTICR1
external interrupt configuration register 1
0x8
32
read-write
n
0x0
0x0
EXTI0
EXTI x configuration (x = 0 to 3)
0
4
EXTI1
EXTI x configuration (x = 0 to 3)
4
4
EXTI2
EXTI x configuration (x = 0 to 3)
8
4
EXTI3
EXTI x configuration (x = 0 to 3)
12
4
EXTICR2
EXTICR2
external interrupt configuration register 2
0xC
32
read-write
n
0x0
0x0
EXTI4
EXTI x configuration (x = 4 to 7)
0
4
EXTI5
EXTI x configuration (x = 4 to 7)
4
4
EXTI6
EXTI x configuration (x = 4 to 7)
8
4
EXTI7
EXTI x configuration (x = 4 to 7)
12
4
EXTICR3
EXTICR3
external interrupt configuration register 3
0x10
32
read-write
n
0x0
0x0
EXTI10
EXTI10
8
4
EXTI11
EXTI x configuration (x = 8 to 11)
12
4
EXTI8
EXTI x configuration (x = 8 to 11)
0
4
EXTI9
EXTI x configuration (x = 8 to 11)
4
4
EXTICR4
EXTICR4
external interrupt configuration register 4
0x14
32
read-write
n
0x0
0x0
EXTI12
EXTI x configuration (x = 12 to 15)
0
4
EXTI13
EXTI x configuration (x = 12 to 15)
4
4
EXTI14
EXTI x configuration (x = 12 to 15)
8
4
EXTI15
EXTI x configuration (x = 12 to 15)
12
4
MEMRM
MEMRM
memory remap register
0x0
32
read-write
n
0x0
0x0
MEM_MODE
MEM_MODE
0
2
PMC
PMC
peripheral mode configuration register
0x4
32
read-write
n
0x0
0x0
ADC1DC2
ADC1DC2
16
1
TIM1
Advanced-timers
TIM
0x0
0x0
0x400
registers
n
TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9 global interrupt
24
PWM1_UP
Timer1 Update interrupt
25
TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
26
TIM1_CC
TIM1 Capture Compare interrupt
27
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM11
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
UDIS
Update disable
1
1
URS
Update request source
2
1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
UG
Update generation
0
1
OR
OR
option register
0x50
32
read-write
n
0x0
0x0
RMP
Input 1 remapping capability
0
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
UIF
Update interrupt flag
0
1
TIM5
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
CC2S
CC2S
8
2
OC1CE
OC1CE
7
1
OC1FE
OC1FE
2
1
OC1M
OC1M
4
3
OC1PE
OC1PE
3
1
OC2CE
OC2CE
15
1
OC2FE
OC2FE
10
1
OC2M
OC2M
12
3
OC2PE
OC2PE
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
CC3S
0
2
CC4S
CC4S
8
2
O24CE
O24CE
15
1
OC3CE
OC3CE
7
1
OC3FE
OC3FE
2
1
OC3M
OC3M
4
3
OC3PE
OC3PE
3
1
OC4FE
OC4FE
10
1
OC4M
OC4M
12
3
OC4PE
OC4PE
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM5 option register
0x50
32
read-write
n
0x0
0x0
IT4_RMP
Timer Input 4 remap
6
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM6
Basic timers
TIM
0x0
0x0
0x400
registers
n
TIM6_DAC1
Timer6 and DAC1 global interrupt
54
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
TIM8
Advanced-timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM9
General purpose timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
3
IC2F
Input capture 2 filter
12
3
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
TIE
Trigger interrupt enable
6
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART6
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
WWDG
Window watchdog
WWDG
0x0
0x0
0x400
registers
n
CFR
CFR
Configuration register
0x4
32
read-write
n
0x0
0x0
EWI
Early wakeup interrupt
9
1
W
7-bit window value
0
7
WDGTB0
Timer base
7
1
WDGTB1
Timer base
8
1
CR
CR
Control register
0x0
32
read-write
n
0x0
0x0
T
7-bit counter (MSB to LSB)
0
7
WDGA
Activation bit
7
1
SR
SR
Status register
0x8
32
read-write
n
0x0
0x0
EWIF
Early wakeup interrupt flag
0
1