STMicroelectronics
STM32F427VG
2024.05.03
STM32F427VG
false
0
0
ADC1
Analog-to-digital converter
ADC
0x0
0x0
0x51
registers
n
CR1
CR1
control register 1
0x4
32
read-write
n
0x0
0x0
AWDCH
Analog watchdog channel select bits
0
5
AWDEN
Analog watchdog enable on regular channels
23
1
AWDIE
Analog watchdog interrupt enable
6
1
AWDSGL
Enable the watchdog on a single channel in scan mode
9
1
DISCEN
Discontinuous mode on regular channels
11
1
DISCNUM
Discontinuous mode channel count
13
3
EOCIE
Interrupt enable for EOC
5
1
JAUTO
Automatic injected group conversion
10
1
JAWDEN
Analog watchdog enable on injected channels
22
1
JDISCEN
Discontinuous mode on injected channels
12
1
JEOCIE
Interrupt enable for injected channels
7
1
OVRIE
Overrun interrupt enable
26
1
RES
Resolution
24
2
SCAN
Scan mode
8
1
CR2
CR2
control register 2
0x8
32
read-write
n
0x0
0x0
ADON
A/D Converter ON / OFF
0
1
ALIGN
Data alignment
11
1
CONT
Continuous conversion
1
1
DDS
DMA disable selection (for single ADC mode)
9
1
DMA
Direct memory access mode (for single ADC mode)
8
1
EOCS
End of conversion selection
10
1
EXTEN
External trigger enable for regular channels
28
2
EXTSEL
External event select for regular group
24
4
JEXTEN
External trigger enable for injected channels
20
2
JEXTSEL
External event select for injected group
16
4
JSWSTART
Start conversion of injected channels
22
1
SWSTART
Start conversion of regular channels
30
1
DR
DR
regular data register
0x4C
32
read-only
n
0x0
0x0
DATA
Regular data
0
16
HTR
HTR
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
HT
Analog watchdog higher threshold
0
12
JDR1
JDR1
injected data register x
0x3C
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR2
JDR2
injected data register x
0x40
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR3
JDR3
injected data register x
0x44
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR4
JDR4
injected data register x
0x48
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JOFR1
JOFR1
injected channel data offset register x
0x14
32
read-write
n
0x0
0x0
JOFFSET1
Data offset for injected channel x
0
12
JOFR2
JOFR2
injected channel data offset register x
0x18
32
read-write
n
0x0
0x0
JOFFSET2
Data offset for injected channel x
0
12
JOFR3
JOFR3
injected channel data offset register x
0x1C
32
read-write
n
0x0
0x0
JOFFSET3
Data offset for injected channel x
0
12
JOFR4
JOFR4
injected channel data offset register x
0x20
32
read-write
n
0x0
0x0
JOFFSET4
Data offset for injected channel x
0
12
JSQR
JSQR
injected sequence register
0x38
32
read-write
n
0x0
0x0
JL
Injected sequence length
20
2
JSQ1
1st conversion in injected sequence
0
5
JSQ2
2nd conversion in injected sequence
5
5
JSQ3
3rd conversion in injected sequence
10
5
JSQ4
4th conversion in injected sequence
15
5
LTR
LTR
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
LT
Analog watchdog lower threshold
0
12
SMPR1
SMPR1
sample time register 1
0xC
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SMPR2
SMPR2
sample time register 2
0x10
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SQR1
SQR1
regular sequence register 1
0x2C
32
read-write
n
0x0
0x0
L
Regular channel sequence length
20
4
SQ13
13th conversion in regular sequence
0
5
SQ14
14th conversion in regular sequence
5
5
SQ15
15th conversion in regular sequence
10
5
SQ16
16th conversion in regular sequence
15
5
SQR2
SQR2
regular sequence register 2
0x30
32
read-write
n
0x0
0x0
SQ10
10th conversion in regular sequence
15
5
SQ11
11th conversion in regular sequence
20
5
SQ12
12th conversion in regular sequence
25
5
SQ7
7th conversion in regular sequence
0
5
SQ8
8th conversion in regular sequence
5
5
SQ9
9th conversion in regular sequence
10
5
SQR3
SQR3
regular sequence register 3
0x34
32
read-write
n
0x0
0x0
SQ1
1st conversion in regular sequence
0
5
SQ2
2nd conversion in regular sequence
5
5
SQ3
3rd conversion in regular sequence
10
5
SQ4
4th conversion in regular sequence
15
5
SQ5
5th conversion in regular sequence
20
5
SQ6
6th conversion in regular sequence
25
5
SR
SR
status register
0x0
32
read-write
n
0x0
0x0
AWD
Analog watchdog flag
0
1
EOC
Regular channel end of conversion
1
1
JEOC
Injected channel end of conversion
2
1
JSTRT
Injected channel start flag
3
1
OVR
Overrun
5
1
STRT
Regular channel start flag
4
1
ADC2
Analog-to-digital converter
ADC
0x0
0x0
0x51
registers
n
CR1
CR1
control register 1
0x4
32
read-write
n
0x0
0x0
AWDCH
Analog watchdog channel select bits
0
5
AWDEN
Analog watchdog enable on regular channels
23
1
AWDIE
Analog watchdog interrupt enable
6
1
AWDSGL
Enable the watchdog on a single channel in scan mode
9
1
DISCEN
Discontinuous mode on regular channels
11
1
DISCNUM
Discontinuous mode channel count
13
3
EOCIE
Interrupt enable for EOC
5
1
JAUTO
Automatic injected group conversion
10
1
JAWDEN
Analog watchdog enable on injected channels
22
1
JDISCEN
Discontinuous mode on injected channels
12
1
JEOCIE
Interrupt enable for injected channels
7
1
OVRIE
Overrun interrupt enable
26
1
RES
Resolution
24
2
SCAN
Scan mode
8
1
CR2
CR2
control register 2
0x8
32
read-write
n
0x0
0x0
ADON
A/D Converter ON / OFF
0
1
ALIGN
Data alignment
11
1
CONT
Continuous conversion
1
1
DDS
DMA disable selection (for single ADC mode)
9
1
DMA
Direct memory access mode (for single ADC mode)
8
1
EOCS
End of conversion selection
10
1
EXTEN
External trigger enable for regular channels
28
2
EXTSEL
External event select for regular group
24
4
JEXTEN
External trigger enable for injected channels
20
2
JEXTSEL
External event select for injected group
16
4
JSWSTART
Start conversion of injected channels
22
1
SWSTART
Start conversion of regular channels
30
1
DR
DR
regular data register
0x4C
32
read-only
n
0x0
0x0
DATA
Regular data
0
16
HTR
HTR
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
HT
Analog watchdog higher threshold
0
12
JDR1
JDR1
injected data register x
0x3C
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR2
JDR2
injected data register x
0x40
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR3
JDR3
injected data register x
0x44
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR4
JDR4
injected data register x
0x48
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JOFR1
JOFR1
injected channel data offset register x
0x14
32
read-write
n
0x0
0x0
JOFFSET1
Data offset for injected channel x
0
12
JOFR2
JOFR2
injected channel data offset register x
0x18
32
read-write
n
0x0
0x0
JOFFSET2
Data offset for injected channel x
0
12
JOFR3
JOFR3
injected channel data offset register x
0x1C
32
read-write
n
0x0
0x0
JOFFSET3
Data offset for injected channel x
0
12
JOFR4
JOFR4
injected channel data offset register x
0x20
32
read-write
n
0x0
0x0
JOFFSET4
Data offset for injected channel x
0
12
JSQR
JSQR
injected sequence register
0x38
32
read-write
n
0x0
0x0
JL
Injected sequence length
20
2
JSQ1
1st conversion in injected sequence
0
5
JSQ2
2nd conversion in injected sequence
5
5
JSQ3
3rd conversion in injected sequence
10
5
JSQ4
4th conversion in injected sequence
15
5
LTR
LTR
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
LT
Analog watchdog lower threshold
0
12
SMPR1
SMPR1
sample time register 1
0xC
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SMPR2
SMPR2
sample time register 2
0x10
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SQR1
SQR1
regular sequence register 1
0x2C
32
read-write
n
0x0
0x0
L
Regular channel sequence length
20
4
SQ13
13th conversion in regular sequence
0
5
SQ14
14th conversion in regular sequence
5
5
SQ15
15th conversion in regular sequence
10
5
SQ16
16th conversion in regular sequence
15
5
SQR2
SQR2
regular sequence register 2
0x30
32
read-write
n
0x0
0x0
SQ10
10th conversion in regular sequence
15
5
SQ11
11th conversion in regular sequence
20
5
SQ12
12th conversion in regular sequence
25
5
SQ7
7th conversion in regular sequence
0
5
SQ8
8th conversion in regular sequence
5
5
SQ9
9th conversion in regular sequence
10
5
SQR3
SQR3
regular sequence register 3
0x34
32
read-write
n
0x0
0x0
SQ1
1st conversion in regular sequence
0
5
SQ2
2nd conversion in regular sequence
5
5
SQ3
3rd conversion in regular sequence
10
5
SQ4
4th conversion in regular sequence
15
5
SQ5
5th conversion in regular sequence
20
5
SQ6
6th conversion in regular sequence
25
5
SR
SR
status register
0x0
32
read-write
n
0x0
0x0
AWD
Analog watchdog flag
0
1
EOC
Regular channel end of conversion
1
1
JEOC
Injected channel end of conversion
2
1
JSTRT
Injected channel start flag
3
1
OVR
Overrun
5
1
STRT
Regular channel start flag
4
1
ADC3
Analog-to-digital converter
ADC
0x0
0x0
0x51
registers
n
ADC
ADC1 global interrupt
18
CR1
CR1
control register 1
0x4
32
read-write
n
0x0
0x0
AWDCH
Analog watchdog channel select bits
0
5
AWDEN
Analog watchdog enable on regular channels
23
1
AWDIE
Analog watchdog interrupt enable
6
1
AWDSGL
Enable the watchdog on a single channel in scan mode
9
1
DISCEN
Discontinuous mode on regular channels
11
1
DISCNUM
Discontinuous mode channel count
13
3
EOCIE
Interrupt enable for EOC
5
1
JAUTO
Automatic injected group conversion
10
1
JAWDEN
Analog watchdog enable on injected channels
22
1
JDISCEN
Discontinuous mode on injected channels
12
1
JEOCIE
Interrupt enable for injected channels
7
1
OVRIE
Overrun interrupt enable
26
1
RES
Resolution
24
2
SCAN
Scan mode
8
1
CR2
CR2
control register 2
0x8
32
read-write
n
0x0
0x0
ADON
A/D Converter ON / OFF
0
1
ALIGN
Data alignment
11
1
CONT
Continuous conversion
1
1
DDS
DMA disable selection (for single ADC mode)
9
1
DMA
Direct memory access mode (for single ADC mode)
8
1
EOCS
End of conversion selection
10
1
EXTEN
External trigger enable for regular channels
28
2
EXTSEL
External event select for regular group
24
4
JEXTEN
External trigger enable for injected channels
20
2
JEXTSEL
External event select for injected group
16
4
JSWSTART
Start conversion of injected channels
22
1
SWSTART
Start conversion of regular channels
30
1
DR
DR
regular data register
0x4C
32
read-only
n
0x0
0x0
DATA
Regular data
0
16
HTR
HTR
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
HT
Analog watchdog higher threshold
0
12
JDR1
JDR1
injected data register x
0x3C
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR2
JDR2
injected data register x
0x40
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR3
JDR3
injected data register x
0x44
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JDR4
JDR4
injected data register x
0x48
32
read-only
n
0x0
0x0
JDATA
Injected data
0
16
JOFR1
JOFR1
injected channel data offset register x
0x14
32
read-write
n
0x0
0x0
JOFFSET1
Data offset for injected channel x
0
12
JOFR2
JOFR2
injected channel data offset register x
0x18
32
read-write
n
0x0
0x0
JOFFSET2
Data offset for injected channel x
0
12
JOFR3
JOFR3
injected channel data offset register x
0x1C
32
read-write
n
0x0
0x0
JOFFSET3
Data offset for injected channel x
0
12
JOFR4
JOFR4
injected channel data offset register x
0x20
32
read-write
n
0x0
0x0
JOFFSET4
Data offset for injected channel x
0
12
JSQR
JSQR
injected sequence register
0x38
32
read-write
n
0x0
0x0
JL
Injected sequence length
20
2
JSQ1
1st conversion in injected sequence
0
5
JSQ2
2nd conversion in injected sequence
5
5
JSQ3
3rd conversion in injected sequence
10
5
JSQ4
4th conversion in injected sequence
15
5
LTR
LTR
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
LT
Analog watchdog lower threshold
0
12
SMPR1
SMPR1
sample time register 1
0xC
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SMPR2
SMPR2
sample time register 2
0x10
32
read-write
n
0x0
0x0
SMPx_x
Sample time bits
0
32
SQR1
SQR1
regular sequence register 1
0x2C
32
read-write
n
0x0
0x0
L
Regular channel sequence length
20
4
SQ13
13th conversion in regular sequence
0
5
SQ14
14th conversion in regular sequence
5
5
SQ15
15th conversion in regular sequence
10
5
SQ16
16th conversion in regular sequence
15
5
SQR2
SQR2
regular sequence register 2
0x30
32
read-write
n
0x0
0x0
SQ10
10th conversion in regular sequence
15
5
SQ11
11th conversion in regular sequence
20
5
SQ12
12th conversion in regular sequence
25
5
SQ7
7th conversion in regular sequence
0
5
SQ8
8th conversion in regular sequence
5
5
SQ9
9th conversion in regular sequence
10
5
SQR3
SQR3
regular sequence register 3
0x34
32
read-write
n
0x0
0x0
SQ1
1st conversion in regular sequence
0
5
SQ2
2nd conversion in regular sequence
5
5
SQ3
3rd conversion in regular sequence
10
5
SQ4
4th conversion in regular sequence
15
5
SQ5
5th conversion in regular sequence
20
5
SQ6
6th conversion in regular sequence
25
5
SR
SR
status register
0x0
32
read-write
n
0x0
0x0
AWD
Analog watchdog flag
0
1
EOC
Regular channel end of conversion
1
1
JEOC
Injected channel end of conversion
2
1
JSTRT
Injected channel start flag
3
1
OVR
Overrun
5
1
STRT
Regular channel start flag
4
1
CAN1
Controller area network
CAN
0x0
0x0
0x400
registers
n
CAN1_TX
CAN1 TX interrupts
19
CAN1_RX0
CAN1 RX0 interrupts
20
CAN1_RX1
CAN1 RX1 interrupts
21
CAN1_SCE
CAN1 SCE interrupt
22
BTR
BTR
bit timing register
0x1C
32
read-write
n
0x0
0x0
BRP
BRP
0
10
LBKM
LBKM
30
1
SILM
SILM
31
1
SJW
SJW
24
2
TS1
TS1
16
4
TS2
TS2
20
3
ESR
ESR
interrupt enable register
0x18
32
read-write
n
0x0
0x0
BOFF
BOFF
2
1
read-only
EPVF
EPVF
1
1
read-only
EWGF
EWGF
0
1
read-only
LEC
LEC
4
3
read-write
REC
REC
24
8
read-only
TEC
TEC
16
8
read-only
F0R1
F0R1
Filter bank 0 register 1
0x240
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F0R2
F0R2
Filter bank 0 register 2
0x244
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F10R1
F10R1
Filter bank 10 register 1
0x290
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F10R2
F10R2
Filter bank 10 register 2
0x294
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F11R1
F11R1
Filter bank 11 register 1
0x298
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F11R2
F11R2
Filter bank 11 register 2
0x29C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F12R1
F12R1
Filter bank 4 register 1
0x2A0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F12R2
F12R2
Filter bank 12 register 2
0x2A4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F13R1
F13R1
Filter bank 13 register 1
0x2A8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F13R2
F13R2
Filter bank 13 register 2
0x2AC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F14R1
F14R1
Filter bank 14 register 1
0x2B0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F14R2
F14R2
Filter bank 14 register 2
0x2B4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F15R1
F15R1
Filter bank 15 register 1
0x2B8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F15R2
F15R2
Filter bank 15 register 2
0x2BC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F16R1
F16R1
Filter bank 16 register 1
0x2C0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F16R2
F16R2
Filter bank 16 register 2
0x2C4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F17R1
F17R1
Filter bank 17 register 1
0x2C8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F17R2
F17R2
Filter bank 17 register 2
0x2CC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F18R1
F18R1
Filter bank 18 register 1
0x2D0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F18R2
F18R2
Filter bank 18 register 2
0x2D4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F19R1
F19R1
Filter bank 19 register 1
0x2D8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F19R2
F19R2
Filter bank 19 register 2
0x2DC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R1
F1R1
Filter bank 1 register 1
0x248
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R2
F1R2
Filter bank 1 register 2
0x24C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F20R1
F20R1
Filter bank 20 register 1
0x2E0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F20R2
F20R2
Filter bank 20 register 2
0x2E4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F21R1
F21R1
Filter bank 21 register 1
0x2E8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F21R2
F21R2
Filter bank 21 register 2
0x2EC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F22R1
F22R1
Filter bank 22 register 1
0x2F0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F22R2
F22R2
Filter bank 22 register 2
0x2F4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F23R1
F23R1
Filter bank 23 register 1
0x2F8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F23R2
F23R2
Filter bank 23 register 2
0x2FC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F24R1
F24R1
Filter bank 24 register 1
0x300
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F24R2
F24R2
Filter bank 24 register 2
0x304
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F25R1
F25R1
Filter bank 25 register 1
0x308
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F25R2
F25R2
Filter bank 25 register 2
0x30C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F26R1
F26R1
Filter bank 26 register 1
0x310
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F26R2
F26R2
Filter bank 26 register 2
0x314
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R1
F27R1
Filter bank 27 register 1
0x318
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R2
F27R2
Filter bank 27 register 2
0x31C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F2R1
F2R1
Filter bank 2 register 1
0x250
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F2R2
F2R2
Filter bank 2 register 2
0x254
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F3R1
F3R1
Filter bank 3 register 1
0x258
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F3R2
F3R2
Filter bank 3 register 2
0x25C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F4R1
F4R1
Filter bank 4 register 1
0x260
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F4R2
F4R2
Filter bank 4 register 2
0x264
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F5R1
F5R1
Filter bank 5 register 1
0x268
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F5R2
F5R2
Filter bank 5 register 2
0x26C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F6R1
F6R1
Filter bank 6 register 1
0x270
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F6R2
F6R2
Filter bank 6 register 2
0x274
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F7R1
F7R1
Filter bank 7 register 1
0x278
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F7R2
F7R2
Filter bank 7 register 2
0x27C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F8R1
F8R1
Filter bank 8 register 1
0x280
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F8R2
F8R2
Filter bank 8 register 2
0x284
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F9R1
F9R1
Filter bank 9 register 1
0x288
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F9R2
F9R2
Filter bank 9 register 2
0x28C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
FA1R
FA1R
filter activation register
0x21C
32
read-write
n
0x0
0x0
FACT0
Filter active
0
1
FACT1
Filter active
1
1
FACT10
Filter active
10
1
FACT11
Filter active
11
1
FACT12
Filter active
12
1
FACT13
Filter active
13
1
FACT14
Filter active
14
1
FACT15
Filter active
15
1
FACT16
Filter active
16
1
FACT17
Filter active
17
1
FACT18
Filter active
18
1
FACT19
Filter active
19
1
FACT2
Filter active
2
1
FACT20
Filter active
20
1
FACT21
Filter active
21
1
FACT22
Filter active
22
1
FACT23
Filter active
23
1
FACT24
Filter active
24
1
FACT25
Filter active
25
1
FACT26
Filter active
26
1
FACT27
Filter active
27
1
FACT3
Filter active
3
1
FACT4
Filter active
4
1
FACT5
Filter active
5
1
FACT6
Filter active
6
1
FACT7
Filter active
7
1
FACT8
Filter active
8
1
FACT9
Filter active
9
1
FFA1R
FFA1R
filter FIFO assignment register
0x214
32
read-write
n
0x0
0x0
FFA0
Filter FIFO assignment for filter 0
0
1
FFA1
Filter FIFO assignment for filter 1
1
1
FFA10
Filter FIFO assignment for filter 10
10
1
FFA11
Filter FIFO assignment for filter 11
11
1
FFA12
Filter FIFO assignment for filter 12
12
1
FFA13
Filter FIFO assignment for filter 13
13
1
FFA14
Filter FIFO assignment for filter 14
14
1
FFA15
Filter FIFO assignment for filter 15
15
1
FFA16
Filter FIFO assignment for filter 16
16
1
FFA17
Filter FIFO assignment for filter 17
17
1
FFA18
Filter FIFO assignment for filter 18
18
1
FFA19
Filter FIFO assignment for filter 19
19
1
FFA2
Filter FIFO assignment for filter 2
2
1
FFA20
Filter FIFO assignment for filter 20
20
1
FFA21
Filter FIFO assignment for filter 21
21
1
FFA22
Filter FIFO assignment for filter 22
22
1
FFA23
Filter FIFO assignment for filter 23
23
1
FFA24
Filter FIFO assignment for filter 24
24
1
FFA25
Filter FIFO assignment for filter 25
25
1
FFA26
Filter FIFO assignment for filter 26
26
1
FFA27
Filter FIFO assignment for filter 27
27
1
FFA3
Filter FIFO assignment for filter 3
3
1
FFA4
Filter FIFO assignment for filter 4
4
1
FFA5
Filter FIFO assignment for filter 5
5
1
FFA6
Filter FIFO assignment for filter 6
6
1
FFA7
Filter FIFO assignment for filter 7
7
1
FFA8
Filter FIFO assignment for filter 8
8
1
FFA9
Filter FIFO assignment for filter 9
9
1
FM1R
FM1R
filter mode register
0x204
32
read-write
n
0x0
0x0
FBM0
Filter mode
0
1
FBM1
Filter mode
1
1
FBM10
Filter mode
10
1
FBM11
Filter mode
11
1
FBM12
Filter mode
12
1
FBM13
Filter mode
13
1
FBM14
Filter mode
14
1
FBM15
Filter mode
15
1
FBM16
Filter mode
16
1
FBM17
Filter mode
17
1
FBM18
Filter mode
18
1
FBM19
Filter mode
19
1
FBM2
Filter mode
2
1
FBM20
Filter mode
20
1
FBM21
Filter mode
21
1
FBM22
Filter mode
22
1
FBM23
Filter mode
23
1
FBM24
Filter mode
24
1
FBM25
Filter mode
25
1
FBM26
Filter mode
26
1
FBM27
Filter mode
27
1
FBM3
Filter mode
3
1
FBM4
Filter mode
4
1
FBM5
Filter mode
5
1
FBM6
Filter mode
6
1
FBM7
Filter mode
7
1
FBM8
Filter mode
8
1
FBM9
Filter mode
9
1
FMR
FMR
filter master register
0x200
32
read-write
n
0x0
0x0
CAN2SB
CAN2SB
8
6
FINIT
FINIT
0
1
FS1R
FS1R
filter scale register
0x20C
32
read-write
n
0x0
0x0
FSC0
Filter scale configuration
0
1
FSC1
Filter scale configuration
1
1
FSC10
Filter scale configuration
10
1
FSC11
Filter scale configuration
11
1
FSC12
Filter scale configuration
12
1
FSC13
Filter scale configuration
13
1
FSC14
Filter scale configuration
14
1
FSC15
Filter scale configuration
15
1
FSC16
Filter scale configuration
16
1
FSC17
Filter scale configuration
17
1
FSC18
Filter scale configuration
18
1
FSC19
Filter scale configuration
19
1
FSC2
Filter scale configuration
2
1
FSC20
Filter scale configuration
20
1
FSC21
Filter scale configuration
21
1
FSC22
Filter scale configuration
22
1
FSC23
Filter scale configuration
23
1
FSC24
Filter scale configuration
24
1
FSC25
Filter scale configuration
25
1
FSC26
Filter scale configuration
26
1
FSC27
Filter scale configuration
27
1
FSC3
Filter scale configuration
3
1
FSC4
Filter scale configuration
4
1
FSC5
Filter scale configuration
5
1
FSC6
Filter scale configuration
6
1
FSC7
Filter scale configuration
7
1
FSC8
Filter scale configuration
8
1
FSC9
Filter scale configuration
9
1
IER
IER
interrupt enable register
0x14
32
read-write
n
0x0
0x0
BOFIE
BOFIE
10
1
EPVIE
EPVIE
9
1
ERRIE
ERRIE
15
1
EWGIE
EWGIE
8
1
FFIE0
FFIE0
2
1
FFIE1
FFIE1
5
1
FMPIE0
FMPIE0
1
1
FMPIE1
FMPIE1
4
1
FOVIE0
FOVIE0
3
1
FOVIE1
FOVIE1
6
1
LECIE
LECIE
11
1
SLKIE
SLKIE
17
1
TMEIE
TMEIE
0
1
WKUIE
WKUIE
16
1
MCR
MCR
master control register
0x0
32
read-write
n
0x0
0x0
ABOM
ABOM
6
1
AWUM
AWUM
5
1
DBF
DBF
16
1
INRQ
INRQ
0
1
NART
NART
4
1
RESET
RESET
15
1
RFLM
RFLM
3
1
SLEEP
SLEEP
1
1
TTCM
TTCM
7
1
TXFP
TXFP
2
1
MSR
MSR
master status register
0x4
32
read-write
n
0x0
0x0
ERRI
ERRI
2
1
read-write
INAK
INAK
0
1
read-only
RX
RX
11
1
read-only
RXM
RXM
9
1
read-only
SAMP
SAMP
10
1
read-only
SLAK
SLAK
1
1
read-only
SLAKI
SLAKI
4
1
read-write
TXM
TXM
8
1
read-only
WKUI
WKUI
3
1
read-write
RDH0R
RDH0R
receive FIFO mailbox data high register
0x1BC
32
read-only
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDH1R
RDH1R
mailbox data high register
0x1CC
32
read-only
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDL0R
RDL0R
mailbox data high register
0x1B8
32
read-only
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDL1R
RDL1R
mailbox data high register
0x1C8
32
read-only
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDT0R
RDT0R
mailbox data high register
0x1B4
32
read-only
n
0x0
0x0
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RDT1R
RDT1R
mailbox data high register
0x1C4
32
read-only
n
0x0
0x0
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RF0R
RF0R
receive FIFO 0 register
0xC
32
read-write
n
0x0
0x0
FMP0
FMP0
0
2
read-only
FOVR0
FOVR0
4
1
read-write
FULL0
FULL0
3
1
read-write
RFOM0
RFOM0
5
1
read-write
RF1R
RF1R
receive FIFO 1 register
0x10
32
read-write
n
0x0
0x0
FMP1
FMP1
0
2
read-only
FOVR1
FOVR1
4
1
read-write
FULL1
FULL1
3
1
read-write
RFOM1
RFOM1
5
1
read-write
RI0R
RI0R
receive FIFO mailbox identifier register
0x1B0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
RI1R
RI1R
mailbox data high register
0x1C0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TDH0R
TDH0R
mailbox data high register
0x18C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH1R
TDH1R
mailbox data high register
0x19C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH2R
TDH2R
mailbox data high register
0x1AC
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDL0R
TDL0R
mailbox data low register
0x188
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL1R
TDL1R
mailbox data low register
0x198
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL2R
TDL2R
mailbox data low register
0x1A8
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDT0R
TDT0R
mailbox data length control and time stamp register
0x184
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT1R
TDT1R
mailbox data length control and time stamp register
0x194
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT2R
TDT2R
mailbox data length control and time stamp register
0x1A4
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TI0R
TI0R
TX mailbox identifier register
0x180
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI1R
TI1R
mailbox identifier register
0x190
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI2R
TI2R
mailbox identifier register
0x1A0
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TSR
TSR
transmit status register
0x8
32
read-write
n
0x0
0x0
ABRQ0
ABRQ0
7
1
read-write
ABRQ1
ABRQ1
15
1
read-write
ABRQ2
ABRQ2
23
1
read-write
ALST0
ALST0
2
1
read-write
ALST1
ALST1
10
1
read-write
ALST2
ALST2
18
1
read-write
CODE
CODE
24
2
read-only
LOW0
Lowest priority flag for mailbox 0
29
1
read-only
LOW1
Lowest priority flag for mailbox 1
30
1
read-only
LOW2
Lowest priority flag for mailbox 2
31
1
read-only
RQCP0
RQCP0
0
1
read-write
RQCP1
RQCP1
8
1
read-write
RQCP2
RQCP2
16
1
read-write
TERR0
TERR0
3
1
read-write
TERR1
TERR1
11
1
read-write
TERR2
TERR2
19
1
read-write
TME0
Lowest priority flag for mailbox 0
26
1
read-only
TME1
Lowest priority flag for mailbox 1
27
1
read-only
TME2
Lowest priority flag for mailbox 2
28
1
read-only
TXOK0
TXOK0
1
1
read-write
TXOK1
TXOK1
9
1
read-write
TXOK2
TXOK2
17
1
read-write
CAN2
Controller area network
CAN
0x0
0x0
0x400
registers
n
CAN2_TX
CAN2 TX interrupts
63
CAN2_RX0
CAN2 RX0 interrupts
64
CAN2_RX1
CAN2 RX1 interrupts
65
CAN2_SCE
CAN2 SCE interrupt
66
BTR
BTR
bit timing register
0x1C
32
read-write
n
0x0
0x0
BRP
BRP
0
10
LBKM
LBKM
30
1
SILM
SILM
31
1
SJW
SJW
24
2
TS1
TS1
16
4
TS2
TS2
20
3
ESR
ESR
interrupt enable register
0x18
32
read-write
n
0x0
0x0
BOFF
BOFF
2
1
read-only
EPVF
EPVF
1
1
read-only
EWGF
EWGF
0
1
read-only
LEC
LEC
4
3
read-write
REC
REC
24
8
read-only
TEC
TEC
16
8
read-only
F0R1
F0R1
Filter bank 0 register 1
0x240
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F0R2
F0R2
Filter bank 0 register 2
0x244
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F10R1
F10R1
Filter bank 10 register 1
0x290
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F10R2
F10R2
Filter bank 10 register 2
0x294
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F11R1
F11R1
Filter bank 11 register 1
0x298
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F11R2
F11R2
Filter bank 11 register 2
0x29C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F12R1
F12R1
Filter bank 4 register 1
0x2A0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F12R2
F12R2
Filter bank 12 register 2
0x2A4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F13R1
F13R1
Filter bank 13 register 1
0x2A8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F13R2
F13R2
Filter bank 13 register 2
0x2AC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F14R1
F14R1
Filter bank 14 register 1
0x2B0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F14R2
F14R2
Filter bank 14 register 2
0x2B4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F15R1
F15R1
Filter bank 15 register 1
0x2B8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F15R2
F15R2
Filter bank 15 register 2
0x2BC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F16R1
F16R1
Filter bank 16 register 1
0x2C0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F16R2
F16R2
Filter bank 16 register 2
0x2C4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F17R1
F17R1
Filter bank 17 register 1
0x2C8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F17R2
F17R2
Filter bank 17 register 2
0x2CC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F18R1
F18R1
Filter bank 18 register 1
0x2D0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F18R2
F18R2
Filter bank 18 register 2
0x2D4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F19R1
F19R1
Filter bank 19 register 1
0x2D8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F19R2
F19R2
Filter bank 19 register 2
0x2DC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R1
F1R1
Filter bank 1 register 1
0x248
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R2
F1R2
Filter bank 1 register 2
0x24C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F20R1
F20R1
Filter bank 20 register 1
0x2E0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F20R2
F20R2
Filter bank 20 register 2
0x2E4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F21R1
F21R1
Filter bank 21 register 1
0x2E8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F21R2
F21R2
Filter bank 21 register 2
0x2EC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F22R1
F22R1
Filter bank 22 register 1
0x2F0
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F22R2
F22R2
Filter bank 22 register 2
0x2F4
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F23R1
F23R1
Filter bank 23 register 1
0x2F8
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F23R2
F23R2
Filter bank 23 register 2
0x2FC
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F24R1
F24R1
Filter bank 24 register 1
0x300
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F24R2
F24R2
Filter bank 24 register 2
0x304
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F25R1
F25R1
Filter bank 25 register 1
0x308
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F25R2
F25R2
Filter bank 25 register 2
0x30C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F26R1
F26R1
Filter bank 26 register 1
0x310
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F26R2
F26R2
Filter bank 26 register 2
0x314
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R1
F27R1
Filter bank 27 register 1
0x318
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R2
F27R2
Filter bank 27 register 2
0x31C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F2R1
F2R1
Filter bank 2 register 1
0x250
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F2R2
F2R2
Filter bank 2 register 2
0x254
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F3R1
F3R1
Filter bank 3 register 1
0x258
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F3R2
F3R2
Filter bank 3 register 2
0x25C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F4R1
F4R1
Filter bank 4 register 1
0x260
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F4R2
F4R2
Filter bank 4 register 2
0x264
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F5R1
F5R1
Filter bank 5 register 1
0x268
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F5R2
F5R2
Filter bank 5 register 2
0x26C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F6R1
F6R1
Filter bank 6 register 1
0x270
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F6R2
F6R2
Filter bank 6 register 2
0x274
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F7R1
F7R1
Filter bank 7 register 1
0x278
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F7R2
F7R2
Filter bank 7 register 2
0x27C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F8R1
F8R1
Filter bank 8 register 1
0x280
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F8R2
F8R2
Filter bank 8 register 2
0x284
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F9R1
F9R1
Filter bank 9 register 1
0x288
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F9R2
F9R2
Filter bank 9 register 2
0x28C
32
read-write
n
0x0
0x0
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
FA1R
FA1R
filter activation register
0x21C
32
read-write
n
0x0
0x0
FACT0
Filter active
0
1
FACT1
Filter active
1
1
FACT10
Filter active
10
1
FACT11
Filter active
11
1
FACT12
Filter active
12
1
FACT13
Filter active
13
1
FACT14
Filter active
14
1
FACT15
Filter active
15
1
FACT16
Filter active
16
1
FACT17
Filter active
17
1
FACT18
Filter active
18
1
FACT19
Filter active
19
1
FACT2
Filter active
2
1
FACT20
Filter active
20
1
FACT21
Filter active
21
1
FACT22
Filter active
22
1
FACT23
Filter active
23
1
FACT24
Filter active
24
1
FACT25
Filter active
25
1
FACT26
Filter active
26
1
FACT27
Filter active
27
1
FACT3
Filter active
3
1
FACT4
Filter active
4
1
FACT5
Filter active
5
1
FACT6
Filter active
6
1
FACT7
Filter active
7
1
FACT8
Filter active
8
1
FACT9
Filter active
9
1
FFA1R
FFA1R
filter FIFO assignment register
0x214
32
read-write
n
0x0
0x0
FFA0
Filter FIFO assignment for filter 0
0
1
FFA1
Filter FIFO assignment for filter 1
1
1
FFA10
Filter FIFO assignment for filter 10
10
1
FFA11
Filter FIFO assignment for filter 11
11
1
FFA12
Filter FIFO assignment for filter 12
12
1
FFA13
Filter FIFO assignment for filter 13
13
1
FFA14
Filter FIFO assignment for filter 14
14
1
FFA15
Filter FIFO assignment for filter 15
15
1
FFA16
Filter FIFO assignment for filter 16
16
1
FFA17
Filter FIFO assignment for filter 17
17
1
FFA18
Filter FIFO assignment for filter 18
18
1
FFA19
Filter FIFO assignment for filter 19
19
1
FFA2
Filter FIFO assignment for filter 2
2
1
FFA20
Filter FIFO assignment for filter 20
20
1
FFA21
Filter FIFO assignment for filter 21
21
1
FFA22
Filter FIFO assignment for filter 22
22
1
FFA23
Filter FIFO assignment for filter 23
23
1
FFA24
Filter FIFO assignment for filter 24
24
1
FFA25
Filter FIFO assignment for filter 25
25
1
FFA26
Filter FIFO assignment for filter 26
26
1
FFA27
Filter FIFO assignment for filter 27
27
1
FFA3
Filter FIFO assignment for filter 3
3
1
FFA4
Filter FIFO assignment for filter 4
4
1
FFA5
Filter FIFO assignment for filter 5
5
1
FFA6
Filter FIFO assignment for filter 6
6
1
FFA7
Filter FIFO assignment for filter 7
7
1
FFA8
Filter FIFO assignment for filter 8
8
1
FFA9
Filter FIFO assignment for filter 9
9
1
FM1R
FM1R
filter mode register
0x204
32
read-write
n
0x0
0x0
FBM0
Filter mode
0
1
FBM1
Filter mode
1
1
FBM10
Filter mode
10
1
FBM11
Filter mode
11
1
FBM12
Filter mode
12
1
FBM13
Filter mode
13
1
FBM14
Filter mode
14
1
FBM15
Filter mode
15
1
FBM16
Filter mode
16
1
FBM17
Filter mode
17
1
FBM18
Filter mode
18
1
FBM19
Filter mode
19
1
FBM2
Filter mode
2
1
FBM20
Filter mode
20
1
FBM21
Filter mode
21
1
FBM22
Filter mode
22
1
FBM23
Filter mode
23
1
FBM24
Filter mode
24
1
FBM25
Filter mode
25
1
FBM26
Filter mode
26
1
FBM27
Filter mode
27
1
FBM3
Filter mode
3
1
FBM4
Filter mode
4
1
FBM5
Filter mode
5
1
FBM6
Filter mode
6
1
FBM7
Filter mode
7
1
FBM8
Filter mode
8
1
FBM9
Filter mode
9
1
FMR
FMR
filter master register
0x200
32
read-write
n
0x0
0x0
CAN2SB
CAN2SB
8
6
FINIT
FINIT
0
1
FS1R
FS1R
filter scale register
0x20C
32
read-write
n
0x0
0x0
FSC0
Filter scale configuration
0
1
FSC1
Filter scale configuration
1
1
FSC10
Filter scale configuration
10
1
FSC11
Filter scale configuration
11
1
FSC12
Filter scale configuration
12
1
FSC13
Filter scale configuration
13
1
FSC14
Filter scale configuration
14
1
FSC15
Filter scale configuration
15
1
FSC16
Filter scale configuration
16
1
FSC17
Filter scale configuration
17
1
FSC18
Filter scale configuration
18
1
FSC19
Filter scale configuration
19
1
FSC2
Filter scale configuration
2
1
FSC20
Filter scale configuration
20
1
FSC21
Filter scale configuration
21
1
FSC22
Filter scale configuration
22
1
FSC23
Filter scale configuration
23
1
FSC24
Filter scale configuration
24
1
FSC25
Filter scale configuration
25
1
FSC26
Filter scale configuration
26
1
FSC27
Filter scale configuration
27
1
FSC3
Filter scale configuration
3
1
FSC4
Filter scale configuration
4
1
FSC5
Filter scale configuration
5
1
FSC6
Filter scale configuration
6
1
FSC7
Filter scale configuration
7
1
FSC8
Filter scale configuration
8
1
FSC9
Filter scale configuration
9
1
IER
IER
interrupt enable register
0x14
32
read-write
n
0x0
0x0
BOFIE
BOFIE
10
1
EPVIE
EPVIE
9
1
ERRIE
ERRIE
15
1
EWGIE
EWGIE
8
1
FFIE0
FFIE0
2
1
FFIE1
FFIE1
5
1
FMPIE0
FMPIE0
1
1
FMPIE1
FMPIE1
4
1
FOVIE0
FOVIE0
3
1
FOVIE1
FOVIE1
6
1
LECIE
LECIE
11
1
SLKIE
SLKIE
17
1
TMEIE
TMEIE
0
1
WKUIE
WKUIE
16
1
MCR
MCR
master control register
0x0
32
read-write
n
0x0
0x0
ABOM
ABOM
6
1
AWUM
AWUM
5
1
DBF
DBF
16
1
INRQ
INRQ
0
1
NART
NART
4
1
RESET
RESET
15
1
RFLM
RFLM
3
1
SLEEP
SLEEP
1
1
TTCM
TTCM
7
1
TXFP
TXFP
2
1
MSR
MSR
master status register
0x4
32
read-write
n
0x0
0x0
ERRI
ERRI
2
1
read-write
INAK
INAK
0
1
read-only
RX
RX
11
1
read-only
RXM
RXM
9
1
read-only
SAMP
SAMP
10
1
read-only
SLAK
SLAK
1
1
read-only
SLAKI
SLAKI
4
1
read-write
TXM
TXM
8
1
read-only
WKUI
WKUI
3
1
read-write
RDH0R
RDH0R
receive FIFO mailbox data high register
0x1BC
32
read-only
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDH1R
RDH1R
mailbox data high register
0x1CC
32
read-only
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDL0R
RDL0R
mailbox data high register
0x1B8
32
read-only
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDL1R
RDL1R
mailbox data high register
0x1C8
32
read-only
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDT0R
RDT0R
mailbox data high register
0x1B4
32
read-only
n
0x0
0x0
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RDT1R
RDT1R
mailbox data high register
0x1C4
32
read-only
n
0x0
0x0
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RF0R
RF0R
receive FIFO 0 register
0xC
32
read-write
n
0x0
0x0
FMP0
FMP0
0
2
read-only
FOVR0
FOVR0
4
1
read-write
FULL0
FULL0
3
1
read-write
RFOM0
RFOM0
5
1
read-write
RF1R
RF1R
receive FIFO 1 register
0x10
32
read-write
n
0x0
0x0
FMP1
FMP1
0
2
read-only
FOVR1
FOVR1
4
1
read-write
FULL1
FULL1
3
1
read-write
RFOM1
RFOM1
5
1
read-write
RI0R
RI0R
receive FIFO mailbox identifier register
0x1B0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
RI1R
RI1R
mailbox data high register
0x1C0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TDH0R
TDH0R
mailbox data high register
0x18C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH1R
TDH1R
mailbox data high register
0x19C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH2R
TDH2R
mailbox data high register
0x1AC
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDL0R
TDL0R
mailbox data low register
0x188
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL1R
TDL1R
mailbox data low register
0x198
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL2R
TDL2R
mailbox data low register
0x1A8
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDT0R
TDT0R
mailbox data length control and time stamp register
0x184
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT1R
TDT1R
mailbox data length control and time stamp register
0x194
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT2R
TDT2R
mailbox data length control and time stamp register
0x1A4
32
read-write
n
0x0
0x0
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TI0R
TI0R
TX mailbox identifier register
0x180
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI1R
TI1R
mailbox identifier register
0x190
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI2R
TI2R
mailbox identifier register
0x1A0
32
read-write
n
0x0
0x0
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TSR
TSR
transmit status register
0x8
32
read-write
n
0x0
0x0
ABRQ0
ABRQ0
7
1
read-write
ABRQ1
ABRQ1
15
1
read-write
ABRQ2
ABRQ2
23
1
read-write
ALST0
ALST0
2
1
read-write
ALST1
ALST1
10
1
read-write
ALST2
ALST2
18
1
read-write
CODE
CODE
24
2
read-only
LOW0
Lowest priority flag for mailbox 0
29
1
read-only
LOW1
Lowest priority flag for mailbox 1
30
1
read-only
LOW2
Lowest priority flag for mailbox 2
31
1
read-only
RQCP0
RQCP0
0
1
read-write
RQCP1
RQCP1
8
1
read-write
RQCP2
RQCP2
16
1
read-write
TERR0
TERR0
3
1
read-write
TERR1
TERR1
11
1
read-write
TERR2
TERR2
19
1
read-write
TME0
Lowest priority flag for mailbox 0
26
1
read-only
TME1
Lowest priority flag for mailbox 1
27
1
read-only
TME2
Lowest priority flag for mailbox 2
28
1
read-only
TXOK0
TXOK0
1
1
read-write
TXOK1
TXOK1
9
1
read-write
TXOK2
TXOK2
17
1
read-write
CRC
Cryptographic processor
CRC
0x0
0x0
0x400
registers
n
CR
CR
Control register
0x8
32
write-only
n
0x0
0x0
CR
Control regidter
0
1
DR
DR
Data register
0x0
32
read-write
n
0x0
0x0
DR
Data Register
0
32
IDR
IDR
Independent Data register
0x4
32
read-write
n
0x0
0x0
IDR
Independent Data register
0
8
CRYP
Cryptographic processor
CRYP
0x0
0x0
0x400
registers
n
CRYP
CRYP crypto global interrupt
79
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
ALGODIR
Algorithm direction
2
1
read-write
ALGOMODE0
Algorithm mode
3
3
read-write
ALGOMODE3
ALGOMODE
19
1
read-write
CRYPEN
Cryptographic processor enable
15
1
read-write
DATATYPE
Data type selection
6
2
read-write
FFLUSH
FIFO flush
14
1
write-only
GCM_CCMPH
GCM_CCMPH
16
2
read-write
KEYSIZE
Key size selection (AES mode only)
8
2
read-write
CSGCM0R
CSGCM0R
context swap register
0x70
32
read-write
n
0x0
0x0
CSGCM0R
CSGCM0R
0
32
CSGCM1R
CSGCM1R
context swap register
0x74
32
read-write
n
0x0
0x0
CSGCM1R
CSGCM1R
0
32
CSGCM2R
CSGCM2R
context swap register
0x78
32
read-write
n
0x0
0x0
CSGCM2R
CSGCM2R
0
32
CSGCM3R
CSGCM3R
context swap register
0x7C
32
read-write
n
0x0
0x0
CSGCM3R
CSGCM3R
0
32
CSGCM4R
CSGCM4R
context swap register
0x80
32
read-write
n
0x0
0x0
CSGCM4R
CSGCM4R
0
32
CSGCM5R
CSGCM5R
context swap register
0x84
32
read-write
n
0x0
0x0
CSGCM5R
CSGCM5R
0
32
CSGCM6R
CSGCM6R
context swap register
0x88
32
read-write
n
0x0
0x0
CSGCM6R
CSGCM6R
0
32
CSGCM7R
CSGCM7R
context swap register
0x8C
32
read-write
n
0x0
0x0
CSGCM7R
CSGCM7R
0
32
CSGCMCCM0R
CSGCMCCM0R
context swap register
0x50
32
read-write
n
0x0
0x0
CSGCMCCM0R
CSGCMCCM0R
0
32
CSGCMCCM1R
CSGCMCCM1R
context swap register
0x54
32
read-write
n
0x0
0x0
CSGCMCCM1R
CSGCMCCM1R
0
32
CSGCMCCM2R
CSGCMCCM2R
context swap register
0x58
32
read-write
n
0x0
0x0
CSGCMCCM2R
CSGCMCCM2R
0
32
CSGCMCCM3R
CSGCMCCM3R
context swap register
0x5C
32
read-write
n
0x0
0x0
CSGCMCCM3R
CSGCMCCM3R
0
32
CSGCMCCM4R
CSGCMCCM4R
context swap register
0x60
32
read-write
n
0x0
0x0
CSGCMCCM4R
CSGCMCCM4R
0
32
CSGCMCCM5R
CSGCMCCM5R
context swap register
0x64
32
read-write
n
0x0
0x0
CSGCMCCM5R
CSGCMCCM5R
0
32
CSGCMCCM6R
CSGCMCCM6R
context swap register
0x68
32
read-write
n
0x0
0x0
CSGCMCCM6R
CSGCMCCM6R
0
32
CSGCMCCM7R
CSGCMCCM7R
context swap register
0x6C
32
read-write
n
0x0
0x0
CSGCMCCM7R
CSGCMCCM7R
0
32
DIN
DIN
data input register
0x8
32
read-write
n
0x0
0x0
DATAIN
Data input
0
32
DMACR
DMACR
DMA control register
0x10
32
read-write
n
0x0
0x0
DIEN
DMA input enable
0
1
DOEN
DMA output enable
1
1
DOUT
DOUT
data output register
0xC
32
read-only
n
0x0
0x0
DATAOUT
Data output
0
32
IMSCR
IMSCR
interrupt mask set/clear register
0x14
32
read-write
n
0x0
0x0
INIM
Input FIFO service interrupt mask
0
1
OUTIM
Output FIFO service interrupt mask
1
1
IV0LR
IV0LR
initialization vector registers
0x40
32
read-write
n
0x0
0x0
IV0
IV0
31
1
IV1
IV1
30
1
IV10
IV10
21
1
IV11
IV11
20
1
IV12
IV12
19
1
IV13
IV13
18
1
IV14
IV14
17
1
IV15
IV15
16
1
IV16
IV16
15
1
IV17
IV17
14
1
IV18
IV18
13
1
IV19
IV19
12
1
IV2
IV2
29
1
IV20
IV20
11
1
IV21
IV21
10
1
IV22
IV22
9
1
IV23
IV23
8
1
IV24
IV24
7
1
IV25
IV25
6
1
IV26
IV26
5
1
IV27
IV27
4
1
IV28
IV28
3
1
IV29
IV29
2
1
IV3
IV3
28
1
IV30
IV30
1
1
IV31
IV31
0
1
IV4
IV4
27
1
IV5
IV5
26
1
IV6
IV6
25
1
IV7
IV7
24
1
IV8
IV8
23
1
IV9
IV9
22
1
IV0RR
IV0RR
initialization vector registers
0x44
32
read-write
n
0x0
0x0
IV32
IV32
31
1
IV33
IV33
30
1
IV34
IV34
29
1
IV35
IV35
28
1
IV36
IV36
27
1
IV37
IV37
26
1
IV38
IV38
25
1
IV39
IV39
24
1
IV40
IV40
23
1
IV41
IV41
22
1
IV42
IV42
21
1
IV43
IV43
20
1
IV44
IV44
19
1
IV45
IV45
18
1
IV46
IV46
17
1
IV47
IV47
16
1
IV48
IV48
15
1
IV49
IV49
14
1
IV50
IV50
13
1
IV51
IV51
12
1
IV52
IV52
11
1
IV53
IV53
10
1
IV54
IV54
9
1
IV55
IV55
8
1
IV56
IV56
7
1
IV57
IV57
6
1
IV58
IV58
5
1
IV59
IV59
4
1
IV60
IV60
3
1
IV61
IV61
2
1
IV62
IV62
1
1
IV63
IV63
0
1
IV1LR
IV1LR
initialization vector registers
0x48
32
read-write
n
0x0
0x0
IV64
IV64
31
1
IV65
IV65
30
1
IV66
IV66
29
1
IV67
IV67
28
1
IV68
IV68
27
1
IV69
IV69
26
1
IV70
IV70
25
1
IV71
IV71
24
1
IV72
IV72
23
1
IV73
IV73
22
1
IV74
IV74
21
1
IV75
IV75
20
1
IV76
IV76
19
1
IV77
IV77
18
1
IV78
IV78
17
1
IV79
IV79
16
1
IV80
IV80
15
1
IV81
IV81
14
1
IV82
IV82
13
1
IV83
IV83
12
1
IV84
IV84
11
1
IV85
IV85
10
1
IV86
IV86
9
1
IV87
IV87
8
1
IV88
IV88
7
1
IV89
IV89
6
1
IV90
IV90
5
1
IV91
IV91
4
1
IV92
IV92
3
1
IV93
IV93
2
1
IV94
IV94
1
1
IV95
IV95
0
1
IV1RR
IV1RR
initialization vector registers
0x4C
32
read-write
n
0x0
0x0
IV100
IV100
27
1
IV101
IV101
26
1
IV102
IV102
25
1
IV103
IV103
24
1
IV104
IV104
23
1
IV105
IV105
22
1
IV106
IV106
21
1
IV107
IV107
20
1
IV108
IV108
19
1
IV109
IV109
18
1
IV110
IV110
17
1
IV111
IV111
16
1
IV112
IV112
15
1
IV113
IV113
14
1
IV114
IV114
13
1
IV115
IV115
12
1
IV116
IV116
11
1
IV117
IV117
10
1
IV118
IV118
9
1
IV119
IV119
8
1
IV120
IV120
7
1
IV121
IV121
6
1
IV122
IV122
5
1
IV123
IV123
4
1
IV124
IV124
3
1
IV125
IV125
2
1
IV126
IV126
1
1
IV127
IV127
0
1
IV96
IV96
31
1
IV97
IV97
30
1
IV98
IV98
29
1
IV99
IV99
28
1
K0LR
K0LR
key registers
0x20
32
write-only
n
0x0
0x0
b224
b224
0
1
b225
b225
1
1
b226
b226
2
1
b227
b227
3
1
b228
b228
4
1
b229
b229
5
1
b230
b230
6
1
b231
b231
7
1
b232
b232
8
1
b233
b233
9
1
b234
b234
10
1
b235
b235
11
1
b236
b236
12
1
b237
b237
13
1
b238
b238
14
1
b239
b239
15
1
b240
b240
16
1
b241
b241
17
1
b242
b242
18
1
b243
b243
19
1
b244
b244
20
1
b245
b245
21
1
b246
b246
22
1
b247
b247
23
1
b248
b248
24
1
b249
b249
25
1
b250
b250
26
1
b251
b251
27
1
b252
b252
28
1
b253
b253
29
1
b254
b254
30
1
b255
b255
31
1
K0RR
K0RR
key registers
0x24
32
write-only
n
0x0
0x0
b192
b192
0
1
b193
b193
1
1
b194
b194
2
1
b195
b195
3
1
b196
b196
4
1
b197
b197
5
1
b198
b198
6
1
b199
b199
7
1
b200
b200
8
1
b201
b201
9
1
b202
b202
10
1
b203
b203
11
1
b204
b204
12
1
b205
b205
13
1
b206
b206
14
1
b207
b207
15
1
b208
b208
16
1
b209
b209
17
1
b210
b210
18
1
b211
b211
19
1
b212
b212
20
1
b213
b213
21
1
b214
b214
22
1
b215
b215
23
1
b216
b216
24
1
b217
b217
25
1
b218
b218
26
1
b219
b219
27
1
b220
b220
28
1
b221
b221
29
1
b222
b222
30
1
b223
b223
31
1
K1LR
K1LR
key registers
0x28
32
write-only
n
0x0
0x0
b160
b160
0
1
b161
b161
1
1
b162
b162
2
1
b163
b163
3
1
b164
b164
4
1
b165
b165
5
1
b166
b166
6
1
b167
b167
7
1
b168
b168
8
1
b169
b169
9
1
b170
b170
10
1
b171
b171
11
1
b172
b172
12
1
b173
b173
13
1
b174
b174
14
1
b175
b175
15
1
b176
b176
16
1
b177
b177
17
1
b178
b178
18
1
b179
b179
19
1
b180
b180
20
1
b181
b181
21
1
b182
b182
22
1
b183
b183
23
1
b184
b184
24
1
b185
b185
25
1
b186
b186
26
1
b187
b187
27
1
b188
b188
28
1
b189
b189
29
1
b190
b190
30
1
b191
b191
31
1
K1RR
K1RR
key registers
0x2C
32
write-only
n
0x0
0x0
b128
b128
0
1
b129
b129
1
1
b130
b130
2
1
b131
b131
3
1
b132
b132
4
1
b133
b133
5
1
b134
b134
6
1
b135
b135
7
1
b136
b136
8
1
b137
b137
9
1
b138
b138
10
1
b139
b139
11
1
b140
b140
12
1
b141
b141
13
1
b142
b142
14
1
b143
b143
15
1
b144
b144
16
1
b145
b145
17
1
b146
b146
18
1
b147
b147
19
1
b148
b148
20
1
b149
b149
21
1
b150
b150
22
1
b151
b151
23
1
b152
b152
24
1
b153
b153
25
1
b154
b154
26
1
b155
b155
27
1
b156
b156
28
1
b157
b157
29
1
b158
b158
30
1
b159
b159
31
1
K2LR
K2LR
key registers
0x30
32
write-only
n
0x0
0x0
b100
b100
4
1
b101
b101
5
1
b102
b102
6
1
b103
b103
7
1
b104
b104
8
1
b105
b105
9
1
b106
b106
10
1
b107
b107
11
1
b108
b108
12
1
b109
b109
13
1
b110
b110
14
1
b111
b111
15
1
b112
b112
16
1
b113
b113
17
1
b114
b114
18
1
b115
b115
19
1
b116
b116
20
1
b117
b117
21
1
b118
b118
22
1
b119
b119
23
1
b120
b120
24
1
b121
b121
25
1
b122
b122
26
1
b123
b123
27
1
b124
b124
28
1
b125
b125
29
1
b126
b126
30
1
b127
b127
31
1
b96
b96
0
1
b97
b97
1
1
b98
b98
2
1
b99
b99
3
1
K2RR
K2RR
key registers
0x34
32
write-only
n
0x0
0x0
b64
b64
0
1
b65
b65
1
1
b66
b66
2
1
b67
b67
3
1
b68
b68
4
1
b69
b69
5
1
b70
b70
6
1
b71
b71
7
1
b72
b72
8
1
b73
b73
9
1
b74
b74
10
1
b75
b75
11
1
b76
b76
12
1
b77
b77
13
1
b78
b78
14
1
b79
b79
15
1
b80
b80
16
1
b81
b81
17
1
b82
b82
18
1
b83
b83
19
1
b84
b84
20
1
b85
b85
21
1
b86
b86
22
1
b87
b87
23
1
b88
b88
24
1
b89
b89
25
1
b90
b90
26
1
b91
b91
27
1
b92
b92
28
1
b93
b93
29
1
b94
b94
30
1
b95
b95
31
1
K3LR
K3LR
key registers
0x38
32
write-only
n
0x0
0x0
b32
b32
0
1
b33
b33
1
1
b34
b34
2
1
b35
b35
3
1
b36
b36
4
1
b37
b37
5
1
b38
b38
6
1
b39
b39
7
1
b40
b40
8
1
b41
b41
9
1
b42
b42
10
1
b43
b43
11
1
b44
b44
12
1
b45
b45
13
1
b46
b46
14
1
b47
b47
15
1
b48
b48
16
1
b49
b49
17
1
b50
b50
18
1
b51
b51
19
1
b52
b52
20
1
b53
b53
21
1
b54
b54
22
1
b55
b55
23
1
b56
b56
24
1
b57
b57
25
1
b58
b58
26
1
b59
b59
27
1
b60
b60
28
1
b61
b61
29
1
b62
b62
30
1
b63
b63
31
1
K3RR
K3RR
key registers
0x3C
32
write-only
n
0x0
0x0
b0
b0
0
1
b1
b1
1
1
b10
b10
10
1
b11
b11
11
1
b12
b12
12
1
b13
b13
13
1
b14
b14
14
1
b15
b15
15
1
b16
b16
16
1
b17
b17
17
1
b18
b18
18
1
b19
b19
19
1
b2
b2
2
1
b20
b20
20
1
b21
b21
21
1
b22
b22
22
1
b23
b23
23
1
b24
b24
24
1
b25
b25
25
1
b26
b26
26
1
b27
b27
27
1
b28
b28
28
1
b29
b29
29
1
b3
b3
3
1
b30
b30
30
1
b31
b31
31
1
b4
b4
4
1
b5
b5
5
1
b6
b6
6
1
b7
b7
7
1
b8
b8
8
1
b9
b9
9
1
MISR
MISR
masked interrupt status register
0x1C
32
read-only
n
0x0
0x0
INMIS
Input FIFO service masked interrupt status
0
1
OUTMIS
Output FIFO service masked interrupt status
1
1
RISR
RISR
raw interrupt status register
0x18
32
read-only
n
0x0
0x0
INRIS
Input FIFO service raw interrupt status
0
1
OUTRIS
Output FIFO service raw interrupt status
1
1
SR
SR
status register
0x4
32
read-only
n
0x0
0x0
BUSY
Busy bit
4
1
IFEM
Input FIFO empty
0
1
IFNF
Input FIFO not full
1
1
OFFU
Output FIFO full
3
1
OFNE
Output FIFO not empty
2
1
C_ADC
Common ADC registers
ADC
0x0
0x0
0xD
registers
n
CCR
CCR
ADC common control register
0x4
32
read-write
n
0x0
0x0
ADCPRE
ADC prescaler
16
2
DDS
DMA disable selection for multi-ADC mode
13
1
DELAY
Delay between 2 sampling phases
8
4
DMA
Direct memory access mode for multi ADC mode
14
2
MULT
Multi ADC mode selection
0
5
TSVREFE
Temperature sensor and VREFINT enable
23
1
VBATE
VBAT enable
22
1
CDR
CDR
ADC common regular data register for dual and triple modes
0x8
32
read-only
n
0x0
0x0
DATA1
1st data item of a pair of regular conversions
0
16
DATA2
2nd data item of a pair of regular conversions
16
16
CSR
CSR
ADC Common status register
0x0
32
read-only
n
0x0
0x0
AWD1
Analog watchdog flag of ADC 1
0
1
AWD2
Analog watchdog flag of ADC 2
8
1
AWD3
Analog watchdog flag of ADC 3
16
1
EOC1
End of conversion of ADC 1
1
1
EOC2
End of conversion of ADC 2
9
1
EOC3
End of conversion of ADC 3
17
1
JEOC1
Injected channel end of conversion of ADC 1
2
1
JEOC2
Injected channel end of conversion of ADC 2
10
1
JEOC3
Injected channel end of conversion of ADC 3
18
1
JSTRT1
Injected channel Start flag of ADC 1
3
1
JSTRT2
Injected channel Start flag of ADC 2
11
1
JSTRT3
Injected channel Start flag of ADC 3
19
1
OVR1
Overrun flag of ADC 1
5
1
OVR2
Overrun flag of ADC 2
13
1
OVR3
Overrun flag of ADC3
21
1
STRT1
Regular channel Start flag of ADC 1
4
1
STRT2
Regular channel Start flag of ADC 2
12
1
STRT3
Regular channel Start flag of ADC 3
20
1
DAC
Digital-to-analog converter
DAC
0x0
0x0
0x400
registers
n
TIM6_DAC
TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
54
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
BOFF1
DAC channel1 output buffer disable
1
1
BOFF2
DAC channel2 output buffer disable
17
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN2
DAC channel2 DMA enable
28
1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt enable
13
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt enable
29
1
EN1
DAC channel1 enable
0
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude selector
8
4
MAMP2
DAC channel2 mask/amplitude selector
24
4
TEN1
DAC channel1 trigger enable
2
1
TEN2
DAC channel2 trigger enable
18
1
TSEL1
DAC channel1 trigger selection
3
3
TSEL2
DAC channel2 trigger selection
19
3
WAVE1
DAC channel1 noise/triangle wave generation enable
6
2
WAVE2
DAC channel2 noise/triangle wave generation enable
22
2
DHR12L1
DHR12L1
channel1 12-bit left aligned data holding register
0xC
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding register
0x18
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit left-aligned data
4
12
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DACC2DHR
DAC channel2 12-bit left-aligned data
20
12
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding register
0x14
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 12-bit right-aligned data
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DACC2DHR
DAC channel2 12-bit right-aligned data
16
12
DHR8R1
DHR8R1
channel1 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding register
0x1C
32
read-write
n
0x0
0x0
DACC2DHR
DAC channel2 8-bit right-aligned data
0
8
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DACC2DHR
DAC channel2 8-bit right-aligned data
8
8
DOR1
DOR1
channel1 data output register
0x2C
32
read-only
n
0x0
0x0
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
channel2 data output register
0x30
32
read-only
n
0x0
0x0
DACC2DOR
DAC channel2 data output
0
12
SR
SR
status register
0x34
32
read-write
n
0x0
0x0
DMAUDR1
DAC channel1 DMA underrun flag
13
1
DMAUDR2
DAC channel2 DMA underrun flag
29
1
SWTRIGR
SWTRIGR
software trigger register
0x4
32
write-only
n
0x0
0x0
SWTRIG1
DAC channel1 software trigger
0
1
SWTRIG2
DAC channel2 software trigger
1
1
DBG
Debug support
DBG
0x0
0x0
0x400
registers
n
DBGMCU_APB1_FZ
DBGMCU_APB1_FZ
Debug MCU APB1 Freeze registe
0x8
32
read-write
n
0x0
0x0
DBG_CAN1_STOP
DBG_CAN1_STOP
25
1
DBG_CAN2_STOP
DBG_CAN2_STOP
26
1
DBG_IWDEG_STOP
DBG_IWDEG_STOP
12
1
DBG_J2C1_SMBUS_TIMEOUT
DBG_J2C1_SMBUS_TIMEOUT
21
1
DBG_J2C2_SMBUS_TIMEOUT
DBG_J2C2_SMBUS_TIMEOUT
22
1
DBG_J2C3SMBUS_TIMEOUT
DBG_J2C3SMBUS_TIMEOUT
23
1
DBG_TIM12_STOP
DBG_TIM12_STOP
6
1
DBG_TIM13_STOP
DBG_TIM13_STOP
7
1
DBG_TIM14_STOP
DBG_TIM14_STOP
8
1
DBG_TIM2_STOP
DBG_TIM2_STOP
0
1
DBG_TIM3_STOP
DBG_TIM3 _STOP
1
1
DBG_TIM4_STOP
DBG_TIM4_STOP
2
1
DBG_TIM5_STOP
DBG_TIM5_STOP
3
1
DBG_TIM6_STOP
DBG_TIM6_STOP
4
1
DBG_TIM7_STOP
DBG_TIM7_STOP
5
1
DBG_WWDG_STOP
DBG_WWDG_STOP
11
1
DBGMCU_APB2_FZ
DBGMCU_APB2_FZ
Debug MCU APB2 Freeze registe
0xC
32
read-write
n
0x0
0x0
DBG_TIM10_STOP
TIM10 counter stopped when core is halted
17
1
DBG_TIM11_STOP
TIM11 counter stopped when core is halted
18
1
DBG_TIM1_STOP
TIM1 counter stopped when core is halted
0
1
DBG_TIM8_STOP
TIM8 counter stopped when core is halted
1
1
DBG_TIM9_STOP
TIM9 counter stopped when core is halted
16
1
DBGMCU_CR
DBGMCU_CR
Control Register
0x4
32
read-write
n
0x0
0x0
DBG_SLEEP
DBG_SLEEP
0
1
DBG_STANDBY
DBG_STANDBY
2
1
DBG_STOP
DBG_STOP
1
1
TRACE_IOEN
TRACE_IOEN
5
1
TRACE_MODE
TRACE_MODE
6
2
DBGMCU_IDCODE
DBGMCU_IDCODE
IDCODE
0x0
32
read-only
n
0x0
0x0
DEV_ID
DEV_ID
0
12
REV_ID
REV_ID
16
16
DCMI
Digital camera interface
DCMI
0x0
0x0
0x400
registers
n
DCMI
DCMI global interrupt
78
CR
CR
control register 1
0x0
32
read-write
n
0x0
0x0
CAPTURE
Capture enable
0
1
CM
Capture mode
1
1
CROP
Crop feature
2
1
EDM
Extended data mode
10
2
ENABLE
DCMI enable
14
1
ESS
Embedded synchronization select
4
1
FCRC
Frame capture rate control
8
2
HSPOL
Horizontal synchronization polarity
6
1
JPEG
JPEG format
3
1
PCKPOL
Pixel clock polarity
5
1
VSPOL
Vertical synchronization polarity
7
1
CWSIZE
CWSIZE
crop window size
0x24
32
read-write
n
0x0
0x0
CAPCNT
Capture count
0
14
VLINE
Vertical line count
16
14
CWSTRT
CWSTRT
crop window start
0x20
32
read-write
n
0x0
0x0
HOFFCNT
Horizontal offset count
0
14
VST
Vertical start line count
16
13
DR
DR
data register
0x28
32
read-only
n
0x0
0x0
Byte0
Data byte 0
0
8
Byte1
Data byte 1
8
8
Byte2
Data byte 2
16
8
Byte3
Data byte 3
24
8
ESCR
ESCR
embedded synchronization code register
0x18
32
read-write
n
0x0
0x0
FEC
Frame end delimiter code
24
8
FSC
Frame start delimiter code
0
8
LEC
Line end delimiter code
16
8
LSC
Line start delimiter code
8
8
ESUR
ESUR
embedded synchronization unmask register
0x1C
32
read-write
n
0x0
0x0
FEU
Frame end delimiter unmask
24
8
FSU
Frame start delimiter unmask
0
8
LEU
Line end delimiter unmask
16
8
LSU
Line start delimiter unmask
8
8
ICR
ICR
interrupt clear register
0x14
32
write-only
n
0x0
0x0
ERR_ISC
Synchronization error interrupt status clear
2
1
FRAME_ISC
Capture complete interrupt status clear
0
1
LINE_ISC
line interrupt status clear
4
1
OVR_ISC
Overrun interrupt status clear
1
1
VSYNC_ISC
Vertical synch interrupt status clear
3
1
IER
IER
interrupt enable register
0xC
32
read-write
n
0x0
0x0
ERR_IE
Synchronization error interrupt enable
2
1
FRAME_IE
Capture complete interrupt enable
0
1
LINE_IE
Line interrupt enable
4
1
OVR_IE
Overrun interrupt enable
1
1
VSYNC_IE
VSYNC interrupt enable
3
1
MIS
MIS
masked interrupt status register
0x10
32
read-only
n
0x0
0x0
ERR_MIS
Synchronization error masked interrupt status
2
1
FRAME_MIS
Capture complete masked interrupt status
0
1
LINE_MIS
Line masked interrupt status
4
1
OVR_MIS
Overrun masked interrupt status
1
1
VSYNC_MIS
VSYNC masked interrupt status
3
1
RIS
RIS
raw interrupt status register
0x8
32
read-only
n
0x0
0x0
ERR_RIS
Synchronization error raw interrupt status
2
1
FRAME_RIS
Capture complete raw interrupt status
0
1
LINE_RIS
Line raw interrupt status
4
1
OVR_RIS
Overrun raw interrupt status
1
1
VSYNC_RIS
VSYNC raw interrupt status
3
1
SR
SR
status register
0x4
32
read-only
n
0x0
0x0
FNE
FIFO not empty
2
1
HSYNC
HSYNC
0
1
VSYNC
VSYNC
1
1
DMA1
DMA controller
DMA
0x0
0x0
0x400
registers
n
DMA1_Stream0
DMA1 Stream0 global interrupt
11
DMA1_Stream1
DMA1 Stream1 global interrupt
12
DMA1_Stream2
DMA1 Stream2 global interrupt
13
DMA1_Stream3
DMA1 Stream3 global interrupt
14
DMA1_Stream4
DMA1 Stream4 global interrupt
15
DMA1_Stream5
DMA1 Stream5 global interrupt
16
DMA1_Stream6
DMA1 Stream6 global interrupt
17
DMA1_Stream7
DMA1 Stream7 global interrupt
47
HIFCR
HIFCR
high interrupt flag clear register
0xC
32
read-write
n
0x0
0x0
CDMEIF4
Stream x clear direct mode error interrupt flag (x = 7..4)
2
1
CDMEIF5
Stream x clear direct mode error interrupt flag (x = 7..4)
8
1
CDMEIF6
Stream x clear direct mode error interrupt flag (x = 7..4)
18
1
CDMEIF7
Stream x clear direct mode error interrupt flag (x = 7..4)
24
1
CFEIF4
Stream x clear FIFO error interrupt flag (x = 7..4)
0
1
CFEIF5
Stream x clear FIFO error interrupt flag (x = 7..4)
6
1
CFEIF6
Stream x clear FIFO error interrupt flag (x = 7..4)
16
1
CFEIF7
Stream x clear FIFO error interrupt flag (x = 7..4)
22
1
CHTIF4
Stream x clear half transfer interrupt flag (x = 7..4)
4
1
CHTIF5
Stream x clear half transfer interrupt flag (x = 7..4)
10
1
CHTIF6
Stream x clear half transfer interrupt flag (x = 7..4)
20
1
CHTIF7
Stream x clear half transfer interrupt flag (x = 7..4)
26
1
CTCIF4
Stream x clear transfer complete interrupt flag (x = 7..4)
5
1
CTCIF5
Stream x clear transfer complete interrupt flag (x = 7..4)
11
1
CTCIF6
Stream x clear transfer complete interrupt flag (x = 7..4)
21
1
CTCIF7
Stream x clear transfer complete interrupt flag (x = 7..4)
27
1
CTEIF4
Stream x clear transfer error interrupt flag (x = 7..4)
3
1
CTEIF5
Stream x clear transfer error interrupt flag (x = 7..4)
9
1
CTEIF6
Stream x clear transfer error interrupt flag (x = 7..4)
19
1
CTEIF7
Stream x clear transfer error interrupt flag (x = 7..4)
25
1
HISR
HISR
high interrupt status register
0x4
32
read-only
n
0x0
0x0
DMEIF4
Stream x direct mode error interrupt flag (x=7..4)
2
1
DMEIF5
Stream x direct mode error interrupt flag (x=7..4)
8
1
DMEIF6
Stream x direct mode error interrupt flag (x=7..4)
18
1
DMEIF7
Stream x direct mode error interrupt flag (x=7..4)
24
1
FEIF4
Stream x FIFO error interrupt flag (x=7..4)
0
1
FEIF5
Stream x FIFO error interrupt flag (x=7..4)
6
1
FEIF6
Stream x FIFO error interrupt flag (x=7..4)
16
1
FEIF7
Stream x FIFO error interrupt flag (x=7..4)
22
1
HTIF4
Stream x half transfer interrupt flag (x=7..4)
4
1
HTIF5
Stream x half transfer interrupt flag (x=7..4)
10
1
HTIF6
Stream x half transfer interrupt flag (x=7..4)
20
1
HTIF7
Stream x half transfer interrupt flag (x=7..4)
26
1
TCIF4
Stream x transfer complete interrupt flag (x=7..4)
5
1
TCIF5
Stream x transfer complete interrupt flag (x=7..4)
11
1
TCIF6
Stream x transfer complete interrupt flag (x=7..4)
21
1
TCIF7
Stream x transfer complete interrupt flag (x=7..4)
27
1
TEIF4
Stream x transfer error interrupt flag (x=7..4)
3
1
TEIF5
Stream x transfer error interrupt flag (x=7..4)
9
1
TEIF6
Stream x transfer error interrupt flag (x=7..4)
19
1
TEIF7
Stream x transfer error interrupt flag (x=7..4)
25
1
LIFCR
LIFCR
low interrupt flag clear register
0x8
32
read-write
n
0x0
0x0
CDMEIF0
Stream x clear direct mode error interrupt flag (x = 3..0)
2
1
CDMEIF1
Stream x clear direct mode error interrupt flag (x = 3..0)
8
1
CDMEIF2
Stream x clear direct mode error interrupt flag (x = 3..0)
18
1
CDMEIF3
Stream x clear direct mode error interrupt flag (x = 3..0)
24
1
CFEIF0
Stream x clear FIFO error interrupt flag (x = 3..0)
0
1
CFEIF1
Stream x clear FIFO error interrupt flag (x = 3..0)
6
1
CFEIF2
Stream x clear FIFO error interrupt flag (x = 3..0)
16
1
CFEIF3
Stream x clear FIFO error interrupt flag (x = 3..0)
22
1
CHTIF0
Stream x clear half transfer interrupt flag (x = 3..0)
4
1
CHTIF1
Stream x clear half transfer interrupt flag (x = 3..0)
10
1
CHTIF2
Stream x clear half transfer interrupt flag (x = 3..0)
20
1
CHTIF3
Stream x clear half transfer interrupt flag (x = 3..0)
26
1
CTCIF0
Stream x clear transfer complete interrupt flag (x = 3..0)
5
1
CTCIF1
Stream x clear transfer complete interrupt flag (x = 3..0)
11
1
CTCIF2
Stream x clear transfer complete interrupt flag (x = 3..0)
21
1
CTCIF3
Stream x clear transfer complete interrupt flag (x = 3..0)
27
1
CTEIF0
Stream x clear transfer error interrupt flag (x = 3..0)
3
1
CTEIF1
Stream x clear transfer error interrupt flag (x = 3..0)
9
1
CTEIF2
Stream x clear transfer error interrupt flag (x = 3..0)
19
1
CTEIF3
Stream x clear transfer error interrupt flag (x = 3..0)
25
1
LISR
LISR
low interrupt status register
0x0
32
read-only
n
0x0
0x0
DMEIF0
Stream x direct mode error interrupt flag (x=3..0)
2
1
DMEIF1
Stream x direct mode error interrupt flag (x=3..0)
8
1
DMEIF2
Stream x direct mode error interrupt flag (x=3..0)
18
1
DMEIF3
Stream x direct mode error interrupt flag (x=3..0)
24
1
FEIF0
Stream x FIFO error interrupt flag (x=3..0)
0
1
FEIF1
Stream x FIFO error interrupt flag (x=3..0)
6
1
FEIF2
Stream x FIFO error interrupt flag (x=3..0)
16
1
FEIF3
Stream x FIFO error interrupt flag (x=3..0)
22
1
HTIF0
Stream x half transfer interrupt flag (x=3..0)
4
1
HTIF1
Stream x half transfer interrupt flag (x=3..0)
10
1
HTIF2
Stream x half transfer interrupt flag (x=3..0)
20
1
HTIF3
Stream x half transfer interrupt flag (x=3..0)
26
1
TCIF0
Stream x transfer complete interrupt flag (x = 3..0)
5
1
TCIF1
Stream x transfer complete interrupt flag (x = 3..0)
11
1
TCIF2
Stream x transfer complete interrupt flag (x = 3..0)
21
1
TCIF3
Stream x transfer complete interrupt flag (x = 3..0)
27
1
TEIF0
Stream x transfer error interrupt flag (x=3..0)
3
1
TEIF1
Stream x transfer error interrupt flag (x=3..0)
9
1
TEIF2
Stream x transfer error interrupt flag (x=3..0)
19
1
TEIF3
Stream x transfer error interrupt flag (x=3..0)
25
1
S0CR
S0CR
stream x configuration register
0x10
32
read-write
n
0x0
0x0
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S0FCR
S0FCR
stream x FIFO control register
0x24
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S0M0AR
S0M0AR
stream x memory 0 address register
0x1C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S0M1AR
S0M1AR
stream x memory 1 address register
0x20
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S0NDTR
S0NDTR
stream x number of data register
0x14
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S0PAR
S0PAR
stream x peripheral address register
0x18
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S1CR
S1CR
stream x configuration register
0x28
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S1FCR
S1FCR
stream x FIFO control register
0x3C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S1M0AR
S1M0AR
stream x memory 0 address register
0x34
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S1M1AR
S1M1AR
stream x memory 1 address register
0x38
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S1NDTR
S1NDTR
stream x number of data register
0x2C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S1PAR
S1PAR
stream x peripheral address register
0x30
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S2CR
S2CR
stream x configuration register
0x40
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S2FCR
S2FCR
stream x FIFO control register
0x54
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S2M0AR
S2M0AR
stream x memory 0 address register
0x4C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S2M1AR
S2M1AR
stream x memory 1 address register
0x50
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S2NDTR
S2NDTR
stream x number of data register
0x44
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S2PAR
S2PAR
stream x peripheral address register
0x48
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S3CR
S3CR
stream x configuration register
0x58
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S3FCR
S3FCR
stream x FIFO control register
0x6C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S3M0AR
S3M0AR
stream x memory 0 address register
0x64
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S3M1AR
S3M1AR
stream x memory 1 address register
0x68
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S3NDTR
S3NDTR
stream x number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S3PAR
S3PAR
stream x peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S4CR
S4CR
stream x configuration register
0x70
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S4FCR
S4FCR
stream x FIFO control register
0x84
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S4M0AR
S4M0AR
stream x memory 0 address register
0x7C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S4M1AR
S4M1AR
stream x memory 1 address register
0x80
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S4NDTR
S4NDTR
stream x number of data register
0x74
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S4PAR
S4PAR
stream x peripheral address register
0x78
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S5CR
S5CR
stream x configuration register
0x88
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S5FCR
S5FCR
stream x FIFO control register
0x9C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S5M0AR
S5M0AR
stream x memory 0 address register
0x94
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S5M1AR
S5M1AR
stream x memory 1 address register
0x98
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S5NDTR
S5NDTR
stream x number of data register
0x8C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S5PAR
S5PAR
stream x peripheral address register
0x90
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S6CR
S6CR
stream x configuration register
0xA0
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S6FCR
S6FCR
stream x FIFO control register
0xB4
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S6M0AR
S6M0AR
stream x memory 0 address register
0xAC
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S6M1AR
S6M1AR
stream x memory 1 address register
0xB0
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S6NDTR
S6NDTR
stream x number of data register
0xA4
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S6PAR
S6PAR
stream x peripheral address register
0xA8
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S7CR
S7CR
stream x configuration register
0xB8
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S7FCR
S7FCR
stream x FIFO control register
0xCC
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S7M0AR
S7M0AR
stream x memory 0 address register
0xC4
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S7M1AR
S7M1AR
stream x memory 1 address register
0xC8
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S7NDTR
S7NDTR
stream x number of data register
0xBC
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S7PAR
S7PAR
stream x peripheral address register
0xC0
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
DMA2
DMA controller
DMA
0x0
0x0
0x400
registers
n
DMA2_Stream0
DMA2 Stream0 global interrupt
56
DMA2_Stream1
DMA2 Stream1 global interrupt
57
DMA2_Stream2
DMA2 Stream2 global interrupt
58
DMA2_Stream3
DMA2 Stream3 global interrupt
59
DMA2_Stream4
DMA2 Stream4 global interrupt
60
DMA2_Stream5
DMA2 Stream5 global interrupt
68
DMA2_Stream6
DMA2 Stream6 global interrupt
69
DMA2_Stream7
DMA2 Stream7 global interrupt
70
HIFCR
HIFCR
high interrupt flag clear register
0xC
32
read-write
n
0x0
0x0
CDMEIF4
Stream x clear direct mode error interrupt flag (x = 7..4)
2
1
CDMEIF5
Stream x clear direct mode error interrupt flag (x = 7..4)
8
1
CDMEIF6
Stream x clear direct mode error interrupt flag (x = 7..4)
18
1
CDMEIF7
Stream x clear direct mode error interrupt flag (x = 7..4)
24
1
CFEIF4
Stream x clear FIFO error interrupt flag (x = 7..4)
0
1
CFEIF5
Stream x clear FIFO error interrupt flag (x = 7..4)
6
1
CFEIF6
Stream x clear FIFO error interrupt flag (x = 7..4)
16
1
CFEIF7
Stream x clear FIFO error interrupt flag (x = 7..4)
22
1
CHTIF4
Stream x clear half transfer interrupt flag (x = 7..4)
4
1
CHTIF5
Stream x clear half transfer interrupt flag (x = 7..4)
10
1
CHTIF6
Stream x clear half transfer interrupt flag (x = 7..4)
20
1
CHTIF7
Stream x clear half transfer interrupt flag (x = 7..4)
26
1
CTCIF4
Stream x clear transfer complete interrupt flag (x = 7..4)
5
1
CTCIF5
Stream x clear transfer complete interrupt flag (x = 7..4)
11
1
CTCIF6
Stream x clear transfer complete interrupt flag (x = 7..4)
21
1
CTCIF7
Stream x clear transfer complete interrupt flag (x = 7..4)
27
1
CTEIF4
Stream x clear transfer error interrupt flag (x = 7..4)
3
1
CTEIF5
Stream x clear transfer error interrupt flag (x = 7..4)
9
1
CTEIF6
Stream x clear transfer error interrupt flag (x = 7..4)
19
1
CTEIF7
Stream x clear transfer error interrupt flag (x = 7..4)
25
1
HISR
HISR
high interrupt status register
0x4
32
read-only
n
0x0
0x0
DMEIF4
Stream x direct mode error interrupt flag (x=7..4)
2
1
DMEIF5
Stream x direct mode error interrupt flag (x=7..4)
8
1
DMEIF6
Stream x direct mode error interrupt flag (x=7..4)
18
1
DMEIF7
Stream x direct mode error interrupt flag (x=7..4)
24
1
FEIF4
Stream x FIFO error interrupt flag (x=7..4)
0
1
FEIF5
Stream x FIFO error interrupt flag (x=7..4)
6
1
FEIF6
Stream x FIFO error interrupt flag (x=7..4)
16
1
FEIF7
Stream x FIFO error interrupt flag (x=7..4)
22
1
HTIF4
Stream x half transfer interrupt flag (x=7..4)
4
1
HTIF5
Stream x half transfer interrupt flag (x=7..4)
10
1
HTIF6
Stream x half transfer interrupt flag (x=7..4)
20
1
HTIF7
Stream x half transfer interrupt flag (x=7..4)
26
1
TCIF4
Stream x transfer complete interrupt flag (x=7..4)
5
1
TCIF5
Stream x transfer complete interrupt flag (x=7..4)
11
1
TCIF6
Stream x transfer complete interrupt flag (x=7..4)
21
1
TCIF7
Stream x transfer complete interrupt flag (x=7..4)
27
1
TEIF4
Stream x transfer error interrupt flag (x=7..4)
3
1
TEIF5
Stream x transfer error interrupt flag (x=7..4)
9
1
TEIF6
Stream x transfer error interrupt flag (x=7..4)
19
1
TEIF7
Stream x transfer error interrupt flag (x=7..4)
25
1
LIFCR
LIFCR
low interrupt flag clear register
0x8
32
read-write
n
0x0
0x0
CDMEIF0
Stream x clear direct mode error interrupt flag (x = 3..0)
2
1
CDMEIF1
Stream x clear direct mode error interrupt flag (x = 3..0)
8
1
CDMEIF2
Stream x clear direct mode error interrupt flag (x = 3..0)
18
1
CDMEIF3
Stream x clear direct mode error interrupt flag (x = 3..0)
24
1
CFEIF0
Stream x clear FIFO error interrupt flag (x = 3..0)
0
1
CFEIF1
Stream x clear FIFO error interrupt flag (x = 3..0)
6
1
CFEIF2
Stream x clear FIFO error interrupt flag (x = 3..0)
16
1
CFEIF3
Stream x clear FIFO error interrupt flag (x = 3..0)
22
1
CHTIF0
Stream x clear half transfer interrupt flag (x = 3..0)
4
1
CHTIF1
Stream x clear half transfer interrupt flag (x = 3..0)
10
1
CHTIF2
Stream x clear half transfer interrupt flag (x = 3..0)
20
1
CHTIF3
Stream x clear half transfer interrupt flag (x = 3..0)
26
1
CTCIF0
Stream x clear transfer complete interrupt flag (x = 3..0)
5
1
CTCIF1
Stream x clear transfer complete interrupt flag (x = 3..0)
11
1
CTCIF2
Stream x clear transfer complete interrupt flag (x = 3..0)
21
1
CTCIF3
Stream x clear transfer complete interrupt flag (x = 3..0)
27
1
CTEIF0
Stream x clear transfer error interrupt flag (x = 3..0)
3
1
CTEIF1
Stream x clear transfer error interrupt flag (x = 3..0)
9
1
CTEIF2
Stream x clear transfer error interrupt flag (x = 3..0)
19
1
CTEIF3
Stream x clear transfer error interrupt flag (x = 3..0)
25
1
LISR
LISR
low interrupt status register
0x0
32
read-only
n
0x0
0x0
DMEIF0
Stream x direct mode error interrupt flag (x=3..0)
2
1
DMEIF1
Stream x direct mode error interrupt flag (x=3..0)
8
1
DMEIF2
Stream x direct mode error interrupt flag (x=3..0)
18
1
DMEIF3
Stream x direct mode error interrupt flag (x=3..0)
24
1
FEIF0
Stream x FIFO error interrupt flag (x=3..0)
0
1
FEIF1
Stream x FIFO error interrupt flag (x=3..0)
6
1
FEIF2
Stream x FIFO error interrupt flag (x=3..0)
16
1
FEIF3
Stream x FIFO error interrupt flag (x=3..0)
22
1
HTIF0
Stream x half transfer interrupt flag (x=3..0)
4
1
HTIF1
Stream x half transfer interrupt flag (x=3..0)
10
1
HTIF2
Stream x half transfer interrupt flag (x=3..0)
20
1
HTIF3
Stream x half transfer interrupt flag (x=3..0)
26
1
TCIF0
Stream x transfer complete interrupt flag (x = 3..0)
5
1
TCIF1
Stream x transfer complete interrupt flag (x = 3..0)
11
1
TCIF2
Stream x transfer complete interrupt flag (x = 3..0)
21
1
TCIF3
Stream x transfer complete interrupt flag (x = 3..0)
27
1
TEIF0
Stream x transfer error interrupt flag (x=3..0)
3
1
TEIF1
Stream x transfer error interrupt flag (x=3..0)
9
1
TEIF2
Stream x transfer error interrupt flag (x=3..0)
19
1
TEIF3
Stream x transfer error interrupt flag (x=3..0)
25
1
S0CR
S0CR
stream x configuration register
0x10
32
read-write
n
0x0
0x0
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S0FCR
S0FCR
stream x FIFO control register
0x24
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S0M0AR
S0M0AR
stream x memory 0 address register
0x1C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S0M1AR
S0M1AR
stream x memory 1 address register
0x20
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S0NDTR
S0NDTR
stream x number of data register
0x14
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S0PAR
S0PAR
stream x peripheral address register
0x18
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S1CR
S1CR
stream x configuration register
0x28
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S1FCR
S1FCR
stream x FIFO control register
0x3C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S1M0AR
S1M0AR
stream x memory 0 address register
0x34
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S1M1AR
S1M1AR
stream x memory 1 address register
0x38
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S1NDTR
S1NDTR
stream x number of data register
0x2C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S1PAR
S1PAR
stream x peripheral address register
0x30
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S2CR
S2CR
stream x configuration register
0x40
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S2FCR
S2FCR
stream x FIFO control register
0x54
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S2M0AR
S2M0AR
stream x memory 0 address register
0x4C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S2M1AR
S2M1AR
stream x memory 1 address register
0x50
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S2NDTR
S2NDTR
stream x number of data register
0x44
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S2PAR
S2PAR
stream x peripheral address register
0x48
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S3CR
S3CR
stream x configuration register
0x58
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S3FCR
S3FCR
stream x FIFO control register
0x6C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S3M0AR
S3M0AR
stream x memory 0 address register
0x64
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S3M1AR
S3M1AR
stream x memory 1 address register
0x68
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S3NDTR
S3NDTR
stream x number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S3PAR
S3PAR
stream x peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S4CR
S4CR
stream x configuration register
0x70
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S4FCR
S4FCR
stream x FIFO control register
0x84
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S4M0AR
S4M0AR
stream x memory 0 address register
0x7C
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S4M1AR
S4M1AR
stream x memory 1 address register
0x80
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S4NDTR
S4NDTR
stream x number of data register
0x74
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S4PAR
S4PAR
stream x peripheral address register
0x78
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S5CR
S5CR
stream x configuration register
0x88
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S5FCR
S5FCR
stream x FIFO control register
0x9C
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S5M0AR
S5M0AR
stream x memory 0 address register
0x94
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S5M1AR
S5M1AR
stream x memory 1 address register
0x98
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S5NDTR
S5NDTR
stream x number of data register
0x8C
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S5PAR
S5PAR
stream x peripheral address register
0x90
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S6CR
S6CR
stream x configuration register
0xA0
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S6FCR
S6FCR
stream x FIFO control register
0xB4
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S6M0AR
S6M0AR
stream x memory 0 address register
0xAC
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S6M1AR
S6M1AR
stream x memory 1 address register
0xB0
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S6NDTR
S6NDTR
stream x number of data register
0xA4
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S6PAR
S6PAR
stream x peripheral address register
0xA8
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
S7CR
S7CR
stream x configuration register
0xB8
32
read-write
n
0x0
0x0
ACK
ACK
20
1
CHSEL
Channel selection
25
3
CIRC
Circular mode
8
1
CT
Current target (only in double buffer mode)
19
1
DBM
Double buffer mode
18
1
DIR
Data transfer direction
6
2
DMEIE
Direct mode error interrupt enable
1
1
EN
Stream enable / flag stream ready when read low
0
1
HTIE
Half transfer interrupt enable
3
1
MBURST
Memory burst transfer configuration
23
2
MINC
Memory increment mode
10
1
MSIZE
Memory data size
13
2
PBURST
Peripheral burst transfer configuration
21
2
PFCTRL
Peripheral flow controller
5
1
PINC
Peripheral increment mode
9
1
PINCOS
Peripheral increment offset size
15
1
PL
Priority level
16
2
PSIZE
Peripheral data size
11
2
TCIE
Transfer complete interrupt enable
4
1
TEIE
Transfer error interrupt enable
2
1
S7FCR
S7FCR
stream x FIFO control register
0xCC
32
read-write
n
0x0
0x0
DMDIS
Direct mode disable
2
1
read-write
FEIE
FIFO error interrupt enable
7
1
read-write
FS
FIFO status
3
3
read-only
FTH
FIFO threshold selection
0
2
read-write
S7M0AR
S7M0AR
stream x memory 0 address register
0xC4
32
read-write
n
0x0
0x0
M0A
Memory 0 address
0
32
S7M1AR
S7M1AR
stream x memory 1 address register
0xC8
32
read-write
n
0x0
0x0
M1A
Memory 1 address (used in case of Double buffer mode)
0
32
S7NDTR
S7NDTR
stream x number of data register
0xBC
32
read-write
n
0x0
0x0
NDT
Number of data items to transfer
0
16
S7PAR
S7PAR
stream x peripheral address register
0xC0
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
DMA2D
DMA2D
DMA2D
0x0
0x0
0xC00
registers
n
AMTCR
DMA2D_AMTCR
DMA2D AXI master timer configuration register
0x4C
32
read-write
n
0x0
0x0
DT
Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses.
8
8
EN
Enable Enables the dead time functionality.
0
1
BGCMAR
DMA2D_BGCMAR
DMA2D background CLUT memory address register
0x30
32
read-write
n
0x0
0x0
MA
Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned.
0
32
BGCOLR
DMA2D_BGCOLR
DMA2D background color register
0x28
32
read-write
n
0x0
0x0
BLUE
Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
0
8
GREEN
Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
8
8
RED
Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
16
8
BGMAR
DMA2D_BGMAR
DMA2D background memory address register
0x14
32
read-write
n
0x0
0x0
MA
Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
0
32
BGOR
DMA2D_BGOR
DMA2D background offset register
0x18
32
read-write
n
0x0
0x0
LO
Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.
0
14
BGPFCCR
DMA2D_BGPFCCR
DMA2D background PFC control register
0x24
32
read-write
n
0x0
0x0
AI
Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
20
1
ALPHA
Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
24
8
AM
Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless
16
2
CCM
CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
4
1
CM
Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless
0
4
CS
CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.
8
8
RBS
Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
21
1
START
Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer).
5
1
CR
DMA2D_CR
DMA2D control register
0x0
32
read-write
n
0x0
0x0
ABORT
Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset.
2
1
CAEIE
CLUT access error interrupt enable This bit is set and cleared by software.
11
1
CEIE
Configuration Error Interrupt Enable This bit is set and cleared by software.
13
1
CTCIE
CLUT transfer complete interrupt enable This bit is set and cleared by software.
12
1
MODE
DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing.
16
2
START
Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers. This bit is automatically reset by the following events: ** At the end of the transfer ** When the data transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** When a data transfer error occurs ** When the data transfer has not started due to a configuration error or another transfer operation already ongoing (automatic CLUT loading).
0
1
SUSP
Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset.
1
1
TCIE
Transfer complete interrupt enable This bit is set and cleared by software.
9
1
TEIE
Transfer error interrupt enable This bit is set and cleared by software.
8
1
TWIE
Transfer watermark interrupt enable This bit is set and cleared by software.
10
1
FGCMAR
DMA2D_FGCMAR
DMA2D foreground CLUT memory address register
0x2C
32
read-write
n
0x0
0x0
MA
Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.
0
32
FGCOLR
DMA2D_FGCOLR
DMA2D foreground color register
0x20
32
read-write
n
0x0
0x0
BLUE
Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.
0
8
GREEN
Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.
8
8
RED
Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
16
8
FGMAR
DMA2D_FGMAR
DMA2D foreground memory address register
0xC
32
read-write
n
0x0
0x0
MA
Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
0
32
FGOR
DMA2D_FGOR
DMA2D foreground offset register
0x10
32
read-write
n
0x0
0x0
LO
Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.
0
14
FGPFCCR
DMA2D_FGPFCCR
DMA2D foreground PFC control register
0x1C
32
read-write
n
0x0
0x0
AI
Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
20
1
ALPHA
Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only.
24
8
AM
Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless
16
2
CCM
CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
4
1
CM
Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless
0
4
CS
CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.
8
8
CSS
Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless
18
2
RBS
Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
21
1
START
Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer).
5
1
IFCR
DMA2D_IFCR
DMA2D interrupt flag clear register
0x8
32
read-write
n
0x0
0x0
CAECIF
Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
3
1
CCEIF
Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
5
1
CCTCIF
Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
4
1
CTCIF
Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
1
1
CTEIF
Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
0
1
CTWIF
Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
2
1
ISR
DMA2D_ISR
DMA2D Interrupt Status Register
0x4
32
read-only
n
0x0
0x0
CAEIF
CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D.
3
1
CEIF
Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed.
5
1
CTCIF
CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete.
4
1
TCIF
Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only).
1
1
TEIF
Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading).
0
1
TWIF
Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred.
2
1
LWR
DMA2D_LWR
DMA2D line watermark register
0x48
32
read-write
n
0x0
0x0
LW
Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
0
16
NLR
DMA2D_NLR
DMA2D number of line register
0x44
32
read-write
n
0x0
0x0
NL
Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
0
16
PL
Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even.
16
14
OCOLR
DMA2D_OCOLR
DMA2D output color register
0x38
32
read-write
n
0x0
0x0
ALPHA
Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
24
8
BLUE
Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
0
8
GREEN
Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
8
8
RED
Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
16
8
OMAR
DMA2D_OMAR
DMA2D output memory address register
0x3C
32
read-write
n
0x0
0x0
MA
Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.
0
32
OOR
DMA2D_OOR
DMA2D output offset register
0x40
32
read-write
n
0x0
0x0
LO
Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.
0
14
OPFCCR
DMA2D_OPFCCR
DMA2D output PFC control register
0x34
32
read-write
n
0x0
0x0
AI
Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
20
1
CM
Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless
0
3
RBS
Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.
21
1
Ethernet_DMA
Ethernet: DMA controller operation
Ethernet
0x0
0x0
0x400
registers
n
DMABMR
DMABMR
Ethernet DMA bus mode register
0x0
32
read-write
n
0x0
0x0
AAB
AAB
25
1
DA
DA
1
1
DSL
DSL
2
5
EDFE
EDFE
7
1
FB
FB
16
1
FPM
FPM
24
1
MB
MB
26
1
PBL
PBL
8
6
RDP
RDP
17
6
RTPR
RTPR
14
2
SR
SR
0
1
USP
USP
23
1
DMACHRBAR
DMACHRBAR
Ethernet DMA current host receive buffer address register
0x54
32
read-only
n
0x0
0x0
HRBAP
HRBAP
0
32
DMACHRDR
DMACHRDR
Ethernet DMA current host receive descriptor register
0x4C
32
read-only
n
0x0
0x0
HRDAP
HRDAP
0
32
DMACHTBAR
DMACHTBAR
Ethernet DMA current host transmit buffer address register
0x50
32
read-only
n
0x0
0x0
HTBAP
HTBAP
0
32
DMACHTDR
DMACHTDR
Ethernet DMA current host transmit descriptor register
0x48
32
read-only
n
0x0
0x0
HTDAP
HTDAP
0
32
DMAIER
DMAIER
Ethernet DMA interrupt enable register
0x1C
32
read-write
n
0x0
0x0
AISE
AISE
15
1
ERIE
ERIE
14
1
ETIE
ETIE
10
1
FBEIE
FBEIE
13
1
NISE
NISE
16
1
RBUIE
RBUIE
7
1
RIE
RIE
6
1
ROIE
ROIE
4
1
RPSIE
RPSIE
8
1
RWTIE
RWTIE
9
1
TBUIE
TBUIE
2
1
TIE
TIE
0
1
TJTIE
TJTIE
3
1
TPSIE
TPSIE
1
1
TUIE
TUIE
5
1
DMAMFBOCR
DMAMFBOCR
Ethernet DMA missed frame and buffer overflow counter register
0x20
32
read-write
n
0x0
0x0
MFA
MFA
17
11
MFC
MFC
0
16
OFOC
OFOC
28
1
OMFC
OMFC
16
1
DMAOMR
DMAOMR
Ethernet DMA operation mode register
0x18
32
read-write
n
0x0
0x0
DFRF
DFRF
24
1
DTCEFD
DTCEFD
26
1
FEF
FEF
7
1
FTF
FTF
20
1
FUGF
FUGF
6
1
OSF
OSF
2
1
RSF
RSF
25
1
RTC
RTC
3
2
SR
SR
1
1
ST
ST
13
1
TSF
TSF
21
1
TTC
TTC
14
3
DMARDLAR
DMARDLAR
Ethernet DMA receive descriptor list address register
0xC
32
read-write
n
0x0
0x0
SRL
SRL
0
32
DMARPDR
DMARPDR
EHERNET DMA receive poll demand register
0x8
32
read-write
n
0x0
0x0
RPD
RPD
0
32
DMARSWTR
DMARSWTR
Ethernet DMA receive status watchdog timer register
0x24
32
read-write
n
0x0
0x0
RSWTC
RSWTC
0
8
DMASR
DMASR
Ethernet DMA status register
0x14
32
read-write
n
0x0
0x0
AIS
AIS
15
1
read-write
EBS
EBS
23
3
read-only
ERS
ERS
14
1
read-write
ETS
ETS
10
1
read-write
FBES
FBES
13
1
read-write
MMCS
MMCS
27
1
read-only
NIS
NIS
16
1
read-write
PMTS
PMTS
28
1
read-only
PWTS
PWTS
9
1
read-write
RBUS
RBUS
7
1
read-write
ROS
ROS
4
1
read-write
RPS
RPS
17
3
read-only
RPSS
RPSS
8
1
read-write
RS
RS
6
1
read-write
TBUS
TBUS
2
1
read-write
TJTS
TJTS
3
1
read-write
TPS
TPS
20
3
read-only
TPSS
TPSS
1
1
read-write
TS
TS
0
1
read-write
TSTS
TSTS
29
1
read-only
TUS
TUS
5
1
read-write
DMATDLAR
DMATDLAR
Ethernet DMA transmit descriptor list address register
0x10
32
read-write
n
0x0
0x0
STL
STL
0
32
DMATPDR
DMATPDR
Ethernet DMA transmit poll demand register
0x4
32
read-write
n
0x0
0x0
TPD
TPD
0
32
Ethernet_MAC
Ethernet: media access control (MAC)
Ethernet
0x0
0x0
0x61
registers
n
ETH
Ethernet global interrupt
61
ETH_WKUP
Ethernet Wakeup through EXTI line interrupt
62
MACA0HR
MACA0HR
Ethernet MAC address 0 high register
0x40
32
read-write
n
0x0
0x0
MACA0H
MAC address0 high
0
16
read-write
MO
Always 1
31
1
read-only
MACA0LR
MACA0LR
Ethernet MAC address 0 low register
0x44
32
read-write
n
0x0
0x0
MACA0L
0
0
32
MACA1HR
MACA1HR
Ethernet MAC address 1 high register
0x48
32
read-write
n
0x0
0x0
AE
AE
31
1
MACA1H
MACA1H
0
16
MBC
MBC
24
6
SA
SA
30
1
MACA1LR
MACA1LR
Ethernet MAC address1 low register
0x4C
32
read-write
n
0x0
0x0
MACA1LR
MACA1LR
0
32
MACA2HR
MACA2HR
Ethernet MAC address 2 high register
0x50
32
read-write
n
0x0
0x0
AE
AE
31
1
MAC2AH
MAC2AH
0
16
MBC
MBC
24
6
SA
SA
30
1
MACA2LR
MACA2LR
Ethernet MAC address 2 low register
0x54
32
read-write
n
0x0
0x0
MACA2L
MACA2L
0
31
MACA3HR
MACA3HR
Ethernet MAC address 3 high register
0x58
32
read-write
n
0x0
0x0
AE
AE
31
1
MACA3H
MACA3H
0
16
MBC
MBC
24
6
SA
SA
30
1
MACA3LR
MACA3LR
Ethernet MAC address 3 low register
0x5C
32
read-write
n
0x0
0x0
MBCA3L
MBCA3L
0
32
MACCR
MACCR
Ethernet MAC configuration register
0x0
32
read-write
n
0x0
0x0
APCS
APCS
7
1
BL
BL
5
2
CSD
CSD
16
1
CSTF
CSTF
25
1
DC
DC
4
1
DM
DM
11
1
FES
FES
14
1
IFG
IFG
17
3
IPCO
IPCO
10
1
JD
JD
22
1
LM
LM
12
1
RD
RD
9
1
RE
RE
2
1
ROD
ROD
13
1
TE
TE
3
1
WD
WD
23
1
MACDBGR
MACDBGR
Ethernet MAC debug register
0x34
32
read-only
n
0x0
0x0
CR
CR
0
1
CSR
CSR
1
1
MCF
MCF
3
1
MCFHP
MCFHP
5
1
MCP
MCP
4
1
ROR
ROR
2
1
MACFCR
MACFCR
Ethernet MAC flow control register
0x18
32
read-write
n
0x0
0x0
FCB
FCB
0
1
PLT
PLT
4
2
PT
PT
16
16
RFCE
RFCE
2
1
TFCE
TFCE
1
1
UPFD
UPFD
3
1
ZQPD
ZQPD
7
1
MACFFR
MACFFR
Ethernet MAC frame filter register
0x4
32
read-write
n
0x0
0x0
BFD
BFD
5
1
DAIF
DAIF
3
1
HM
HM
2
1
HPF
HPF
9
1
HU
HU
1
1
PCF
PCF
6
1
PM
PM
0
1
RA
RA
31
1
RAM
RAM
4
1
SAF
SAF
8
1
SAIF
SAIF
7
1
MACHTHR
MACHTHR
Ethernet MAC hash table high register
0x8
32
read-write
n
0x0
0x0
HTH
HTH
0
32
MACHTLR
MACHTLR
Ethernet MAC hash table low register
0xC
32
read-write
n
0x0
0x0
HTL
HTL
0
32
MACIMR
MACIMR
Ethernet MAC interrupt mask register
0x3C
32
read-write
n
0x0
0x0
PMTIM
PMTIM
3
1
TSTIM
TSTIM
9
1
MACMIIAR
MACMIIAR
Ethernet MAC MII address register
0x10
32
read-write
n
0x0
0x0
CR
CR
2
3
MB
MB
0
1
MR
MR
6
5
MW
MW
1
1
PA
PA
11
5
MACMIIDR
MACMIIDR
Ethernet MAC MII data register
0x14
32
read-write
n
0x0
0x0
TD
TD
0
16
MACPMTCSR
MACPMTCSR
Ethernet MAC PMT control and status register
0x2C
32
read-write
n
0x0
0x0
GU
GU
9
1
MPE
MPE
1
1
MPR
MPR
5
1
PD
PD
0
1
WFE
WFE
2
1
WFFRPR
WFFRPR
31
1
WFR
WFR
6
1
MACSR
MACSR
Ethernet MAC interrupt status register
0x38
32
read-write
n
0x0
0x0
MMCRS
MMCRS
5
1
read-only
MMCS
MMCS
4
1
read-only
MMCTS
MMCTS
6
1
read-only
PMTS
PMTS
3
1
read-only
TSTS
TSTS
9
1
read-write
MACVLANTR
MACVLANTR
Ethernet MAC VLAN tag register
0x1C
32
read-write
n
0x0
0x0
VLANTC
VLANTC
16
1
VLANTI
VLANTI
0
16
Ethernet_MMC
Ethernet: MAC management counters
Ethernet
0x0
0x0
0x400
registers
n
MMCCR
MMCCR
Ethernet MMC control register
0x0
32
read-write
n
0x0
0x0
CR
CR
0
1
CSR
CSR
1
1
MCF
MCF
3
1
MCFHP
MCFHP
5
1
MCP
MCP
4
1
ROR
ROR
2
1
MMCRFAECR
MMCRFAECR
Ethernet MMC received frames with alignment error counter register
0x98
32
read-only
n
0x0
0x0
RFAEC
RFAEC
0
32
MMCRFCECR
MMCRFCECR
Ethernet MMC received frames with CRC error counter register
0x94
32
read-only
n
0x0
0x0
RFCFC
RFCFC
0
32
MMCRGUFCR
MMCRGUFCR
MMC received good unicast frames counter register
0xC4
32
read-only
n
0x0
0x0
RGUFC
RGUFC
0
32
MMCRIMR
MMCRIMR
Ethernet MMC receive interrupt mask register
0xC
32
read-write
n
0x0
0x0
RFAEM
RFAEM
6
1
RFCEM
RFCEM
5
1
RGUFM
RGUFM
17
1
MMCRIR
MMCRIR
Ethernet MMC receive interrupt register
0x4
32
read-write
n
0x0
0x0
RFAES
RFAES
6
1
RFCES
RFCES
5
1
RGUFS
RGUFS
17
1
MMCTGFCR
MMCTGFCR
Ethernet MMC transmitted good frames counter register
0x68
32
read-only
n
0x0
0x0
TGFC
HTL
0
32
MMCTGFMSCCR
MMCTGFMSCCR
Ethernet MMC transmitted good frames after more than a single collision
0x50
32
read-only
n
0x0
0x0
TGFMSCC
TGFMSCC
0
32
MMCTGFSCCR
MMCTGFSCCR
Ethernet MMC transmitted good frames after a single collision counter
0x4C
32
read-only
n
0x0
0x0
TGFSCC
TGFSCC
0
32
MMCTIMR
MMCTIMR
Ethernet MMC transmit interrupt mask register
0x10
32
read-write
n
0x0
0x0
TGFM
TGFM
16
1
TGFMSCM
TGFMSCM
15
1
TGFSCM
TGFSCM
14
1
MMCTIR
MMCTIR
Ethernet MMC transmit interrupt register
0x8
32
read-only
n
0x0
0x0
TGFMSCS
TGFMSCS
15
1
TGFS
TGFS
21
1
TGFSCS
TGFSCS
14
1
Ethernet_PTP
Ethernet: Precision time protocol
Ethernet
0x0
0x0
0x400
registers
n
PTPPPSCR
PTPPPSCR
Ethernet PTP PPS control register
0x2C
32
read-only
n
0x0
0x0
TSSO
TSSO
0
1
TSTTR
TSTTR
1
1
PTPSSIR
PTPSSIR
Ethernet PTP subsecond increment register
0x4
32
read-write
n
0x0
0x0
STSSI
STSSI
0
8
PTPTSAR
PTPTSAR
Ethernet PTP time stamp addend register
0x18
32
read-write
n
0x0
0x0
TSA
TSA
0
32
PTPTSCR
PTPTSCR
Ethernet PTP time stamp control register
0x0
32
read-write
n
0x0
0x0
TSCNT
TSCNT
16
2
TSE
TSE
0
1
TSFCU
TSFCU
1
1
TSITE
TSITE
4
1
TSPFFMAE
TSPFFMAE
18
1
TSPTPPSV2E
TSPTPPSV2E
10
1
TSSARFE
TSSARFE
8
1
TSSEME
TSSEME
14
1
TSSIPV4FE
TSSIPV4FE
13
1
TSSIPV6FE
TSSIPV6FE
12
1
TSSMRME
TSSMRME
15
1
TSSPTPOEFE
TSSPTPOEFE
11
1
TSSSR
TSSSR
9
1
TSSTI
TSSTI
2
1
TSSTU
TSSTU
3
1
TTSARU
TTSARU
5
1
PTPTSHR
PTPTSHR
Ethernet PTP time stamp high register
0x8
32
read-only
n
0x0
0x0
STS
STS
0
32
PTPTSHUR
PTPTSHUR
Ethernet PTP time stamp high update register
0x10
32
read-write
n
0x0
0x0
TSUS
TSUS
0
32
PTPTSLR
PTPTSLR
Ethernet PTP time stamp low register
0xC
32
read-only
n
0x0
0x0
STPNS
STPNS
31
1
STSS
STSS
0
31
PTPTSLUR
PTPTSLUR
Ethernet PTP time stamp low update register
0x14
32
read-write
n
0x0
0x0
TSUPNS
TSUPNS
31
1
TSUSS
TSUSS
0
31
PTPTSSR
PTPTSSR
Ethernet PTP time stamp status register
0x28
32
read-only
n
0x0
0x0
TSSO
TSSO
0
1
TSTTR
TSTTR
1
1
PTPTTHR
PTPTTHR
Ethernet PTP target time high register
0x1C
32
read-write
n
0x0
0x0
TTSH
0
0
32
PTPTTLR
PTPTTLR
Ethernet PTP target time low register
0x20
32
read-write
n
0x0
0x0
TTSL
TTSL
0
32
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
TAMP_STAMP
Tamper and TimeStamp interrupts through the EXTI line
2
EXTI0
EXTI Line0 interrupt
6
EXTI1
EXTI Line1 interrupt
7
EXTI2
EXTI Line2 interrupt
8
EXTI3
EXTI Line3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
EXTI9_5
EXTI Line[9:5] interrupts
23
EXTI15_10
EXTI Line[15:10] interrupts
40
EMR
EMR
Event mask register (EXTI_EMR)
0x4
32
read-write
n
0x0
0x0
MR0
Event Mask on line 0
0
1
MR1
Event Mask on line 1
1
1
MR10
Event Mask on line 10
10
1
MR11
Event Mask on line 11
11
1
MR12
Event Mask on line 12
12
1
MR13
Event Mask on line 13
13
1
MR14
Event Mask on line 14
14
1
MR15
Event Mask on line 15
15
1
MR16
Event Mask on line 16
16
1
MR17
Event Mask on line 17
17
1
MR18
Event Mask on line 18
18
1
MR19
Event Mask on line 19
19
1
MR2
Event Mask on line 2
2
1
MR20
Event Mask on line 20
20
1
MR21
Event Mask on line 21
21
1
MR22
Event Mask on line 22
22
1
MR3
Event Mask on line 3
3
1
MR4
Event Mask on line 4
4
1
MR5
Event Mask on line 5
5
1
MR6
Event Mask on line 6
6
1
MR7
Event Mask on line 7
7
1
MR8
Event Mask on line 8
8
1
MR9
Event Mask on line 9
9
1
FTSR
FTSR
Falling Trigger selection register (EXTI_FTSR)
0xC
32
read-write
n
0x0
0x0
TR0
Falling trigger event configuration of line 0
0
1
TR1
Falling trigger event configuration of line 1
1
1
TR10
Falling trigger event configuration of line 10
10
1
TR11
Falling trigger event configuration of line 11
11
1
TR12
Falling trigger event configuration of line 12
12
1
TR13
Falling trigger event configuration of line 13
13
1
TR14
Falling trigger event configuration of line 14
14
1
TR15
Falling trigger event configuration of line 15
15
1
TR16
Falling trigger event configuration of line 16
16
1
TR17
Falling trigger event configuration of line 17
17
1
TR18
Falling trigger event configuration of line 18
18
1
TR19
Falling trigger event configuration of line 19
19
1
TR2
Falling trigger event configuration of line 2
2
1
TR20
Falling trigger event configuration of line 20
20
1
TR21
Falling trigger event configuration of line 21
21
1
TR22
Falling trigger event configuration of line 22
22
1
TR3
Falling trigger event configuration of line 3
3
1
TR4
Falling trigger event configuration of line 4
4
1
TR5
Falling trigger event configuration of line 5
5
1
TR6
Falling trigger event configuration of line 6
6
1
TR7
Falling trigger event configuration of line 7
7
1
TR8
Falling trigger event configuration of line 8
8
1
TR9
Falling trigger event configuration of line 9
9
1
IMR
IMR
Interrupt mask register (EXTI_IMR)
0x0
32
read-write
n
0x0
0x0
MR0
Interrupt Mask on line 0
0
1
MR1
Interrupt Mask on line 1
1
1
MR10
Interrupt Mask on line 10
10
1
MR11
Interrupt Mask on line 11
11
1
MR12
Interrupt Mask on line 12
12
1
MR13
Interrupt Mask on line 13
13
1
MR14
Interrupt Mask on line 14
14
1
MR15
Interrupt Mask on line 15
15
1
MR16
Interrupt Mask on line 16
16
1
MR17
Interrupt Mask on line 17
17
1
MR18
Interrupt Mask on line 18
18
1
MR19
Interrupt Mask on line 19
19
1
MR2
Interrupt Mask on line 2
2
1
MR20
Interrupt Mask on line 20
20
1
MR21
Interrupt Mask on line 21
21
1
MR22
Interrupt Mask on line 22
22
1
MR3
Interrupt Mask on line 3
3
1
MR4
Interrupt Mask on line 4
4
1
MR5
Interrupt Mask on line 5
5
1
MR6
Interrupt Mask on line 6
6
1
MR7
Interrupt Mask on line 7
7
1
MR8
Interrupt Mask on line 8
8
1
MR9
Interrupt Mask on line 9
9
1
PR
PR
Pending register (EXTI_PR)
0x14
32
read-write
n
0x0
0x0
PR0
Pending bit 0
0
1
PR1
Pending bit 1
1
1
PR10
Pending bit 10
10
1
PR11
Pending bit 11
11
1
PR12
Pending bit 12
12
1
PR13
Pending bit 13
13
1
PR14
Pending bit 14
14
1
PR15
Pending bit 15
15
1
PR16
Pending bit 16
16
1
PR17
Pending bit 17
17
1
PR18
Pending bit 18
18
1
PR19
Pending bit 19
19
1
PR2
Pending bit 2
2
1
PR20
Pending bit 20
20
1
PR21
Pending bit 21
21
1
PR22
Pending bit 22
22
1
PR3
Pending bit 3
3
1
PR4
Pending bit 4
4
1
PR5
Pending bit 5
5
1
PR6
Pending bit 6
6
1
PR7
Pending bit 7
7
1
PR8
Pending bit 8
8
1
PR9
Pending bit 9
9
1
RTSR
RTSR
Rising Trigger selection register (EXTI_RTSR)
0x8
32
read-write
n
0x0
0x0
TR0
Rising trigger event configuration of line 0
0
1
TR1
Rising trigger event configuration of line 1
1
1
TR10
Rising trigger event configuration of line 10
10
1
TR11
Rising trigger event configuration of line 11
11
1
TR12
Rising trigger event configuration of line 12
12
1
TR13
Rising trigger event configuration of line 13
13
1
TR14
Rising trigger event configuration of line 14
14
1
TR15
Rising trigger event configuration of line 15
15
1
TR16
Rising trigger event configuration of line 16
16
1
TR17
Rising trigger event configuration of line 17
17
1
TR18
Rising trigger event configuration of line 18
18
1
TR19
Rising trigger event configuration of line 19
19
1
TR2
Rising trigger event configuration of line 2
2
1
TR20
Rising trigger event configuration of line 20
20
1
TR21
Rising trigger event configuration of line 21
21
1
TR22
Rising trigger event configuration of line 22
22
1
TR3
Rising trigger event configuration of line 3
3
1
TR4
Rising trigger event configuration of line 4
4
1
TR5
Rising trigger event configuration of line 5
5
1
TR6
Rising trigger event configuration of line 6
6
1
TR7
Rising trigger event configuration of line 7
7
1
TR8
Rising trigger event configuration of line 8
8
1
TR9
Rising trigger event configuration of line 9
9
1
SWIER
SWIER
Software interrupt event register (EXTI_SWIER)
0x10
32
read-write
n
0x0
0x0
SWIER0
Software Interrupt on line 0
0
1
SWIER1
Software Interrupt on line 1
1
1
SWIER10
Software Interrupt on line 10
10
1
SWIER11
Software Interrupt on line 11
11
1
SWIER12
Software Interrupt on line 12
12
1
SWIER13
Software Interrupt on line 13
13
1
SWIER14
Software Interrupt on line 14
14
1
SWIER15
Software Interrupt on line 15
15
1
SWIER16
Software Interrupt on line 16
16
1
SWIER17
Software Interrupt on line 17
17
1
SWIER18
Software Interrupt on line 18
18
1
SWIER19
Software Interrupt on line 19
19
1
SWIER2
Software Interrupt on line 2
2
1
SWIER20
Software Interrupt on line 20
20
1
SWIER21
Software Interrupt on line 21
21
1
SWIER22
Software Interrupt on line 22
22
1
SWIER3
Software Interrupt on line 3
3
1
SWIER4
Software Interrupt on line 4
4
1
SWIER5
Software Interrupt on line 5
5
1
SWIER6
Software Interrupt on line 6
6
1
SWIER7
Software Interrupt on line 7
7
1
SWIER8
Software Interrupt on line 8
8
1
SWIER9
Software Interrupt on line 9
9
1
FLASH
FLASH
FLASH
0x0
0x0
0x400
registers
n
FLASH
Flash global interrupt
4
ACR
ACR
Flash access control register
0x0
32
read-write
n
0x0
0x0
DCEN
Data cache enable
10
1
read-write
DCRST
Data cache reset
12
1
read-write
ICEN
Instruction cache enable
9
1
read-write
ICRST
Instruction cache reset
11
1
write-only
LATENCY
Latency
0
3
read-write
PRFTEN
Prefetch enable
8
1
read-write
CR
CR
Control register
0x10
32
read-write
n
0x0
0x0
EOPIE
End of operation interrupt enable
24
1
ERRIE
Error interrupt enable
25
1
LOCK
Lock
31
1
MER
Mass Erase of sectors 0 to 11
2
1
MER1
Mass Erase of sectors 12 to 23
15
1
PG
Programming
0
1
PSIZE
Program size
8
2
SER
Sector Erase
1
1
SNB
Sector number
3
5
STRT
Start
16
1
KEYR
KEYR
Flash key register
0x4
32
write-only
n
0x0
0x0
KEY
FPEC key
0
32
OPTCR
OPTCR
Flash option control register
0x14
32
read-write
n
0x0
0x0
BOR_LEV
BOR reset Level
2
2
nRST_STDBY
nRST_STDBY User option bytes
7
1
nRST_STOP
nRST_STOP User option bytes
6
1
nWRP
Not write protect
16
12
OPTLOCK
Option lock
0
1
OPTSTRT
Option start
1
1
RDP
Read protect
8
8
WDG_SW
WDG_SW User option bytes
5
1
OPTCR1
OPTCR1
Flash option control register 1
0x18
32
read-write
n
0x0
0x0
nWRP
Not write protect
16
12
OPTKEYR
OPTKEYR
Flash option key register
0x8
32
write-only
n
0x0
0x0
OPTKEY
Option byte key
0
32
SR
SR
Status register
0xC
32
read-write
n
0x0
0x0
BSY
Busy
16
1
read-only
EOP
End of operation
0
1
read-write
OPERR
Operation error
1
1
read-write
PGAERR
Programming alignment error
5
1
read-write
PGPERR
Programming parallelism error
6
1
read-write
PGSERR
Programming sequence error
7
1
read-write
WRPERR
Write protection error
4
1
read-write
FMC
Flexible memory controller
FSMC
0x0
0x0
0x400
registers
n
FMC
FSMC global interrupt
48
BCR1
BCR1
SRAM/NOR-Flash chip-select control register 1
0x0
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
CCLKEN
CCLKEN
20
1
CPSIZE
CPSIZE
16
3
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BCR2
BCR2
SRAM/NOR-Flash chip-select control register 2
0x8
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
CPSIZE
CPSIZE
16
3
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BCR3
BCR3
SRAM/NOR-Flash chip-select control register 3
0x10
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
CPSIZE
CPSIZE
16
3
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BCR4
BCR4
SRAM/NOR-Flash chip-select control register 4
0x18
32
read-write
n
0x0
0x0
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
CPSIZE
CPSIZE
16
3
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BTR1
BTR1
SRAM/NOR-Flash chip-select timing register 1
0x4
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR2
BTR2
SRAM/NOR-Flash chip-select timing register 2
0xC
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR3
BTR3
SRAM/NOR-Flash chip-select timing register 3
0x14
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR4
BTR4
SRAM/NOR-Flash chip-select timing register 4
0x1C
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR1
BWTR1
SRAM/NOR-Flash write timing registers 1
0x104
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
BWTR2
BWTR2
SRAM/NOR-Flash write timing registers 2
0x10C
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
BWTR3
BWTR3
SRAM/NOR-Flash write timing registers 3
BWTR1
0x104
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
BWTR4
BWTR4
SRAM/NOR-Flash write timing registers 4
BWTR2
0x10C
32
read-write
n
0x0
0x0
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
ECCR2
ECCR2
ECC result register 2
0x74
32
read-only
n
0x0
0x0
ECCx
ECCx
0
32
ECCR3
ECCR3
ECC result register 3
0x94
32
read-only
n
0x0
0x0
ECCx
ECCx
0
32
PATT2
PATT2
Attribute memory space timing register 2
0x6C
32
read-write
n
0x0
0x0
ATTHIZx
ATTHIZx
24
8
ATTHOLDx
ATTHOLDx
16
8
ATTSETx
ATTSETx
0
8
ATTWAITx
ATTWAITx
8
8
PATT3
PATT3
Attribute memory space timing register 3
0x8C
32
read-write
n
0x0
0x0
ATTHIZx
ATTHIZx
24
8
ATTHOLDx
ATTHOLDx
16
8
ATTSETx
ATTSETx
0
8
ATTWAITx
ATTWAITx
8
8
PATT4
PATT4
Attribute memory space timing register 4
0xAC
32
read-write
n
0x0
0x0
ATTHIZx
ATTHIZx
24
8
ATTHOLDx
ATTHOLDx
16
8
ATTSETx
ATTSETx
0
8
ATTWAITx
ATTWAITx
8
8
PCR2
PCR2
PC Card/NAND Flash control register 2
0x60
32
read-write
n
0x0
0x0
ECCEN
ECCEN
6
1
ECCPS
ECCPS
17
3
PBKEN
PBKEN
2
1
PTYP
PTYP
3
1
PWAITEN
PWAITEN
1
1
PWID
PWID
4
2
TAR
TAR
13
4
TCLR
TCLR
9
4
PCR3
PCR3
PC Card/NAND Flash control register 3
0x80
32
read-write
n
0x0
0x0
ECCEN
ECCEN
6
1
ECCPS
ECCPS
17
3
PBKEN
PBKEN
2
1
PTYP
PTYP
3
1
PWAITEN
PWAITEN
1
1
PWID
PWID
4
2
TAR
TAR
13
4
TCLR
TCLR
9
4
PCR4
PCR4
PC Card/NAND Flash control register 4
0xA0
32
read-write
n
0x0
0x0
ECCEN
ECCEN
6
1
ECCPS
ECCPS
17
3
PBKEN
PBKEN
2
1
PTYP
PTYP
3
1
PWAITEN
PWAITEN
1
1
PWID
PWID
4
2
TAR
TAR
13
4
TCLR
TCLR
9
4
PIO4
PIO4
I/O space timing register 4
0xB0
32
read-write
n
0x0
0x0
IOHIZx
IOHIZx
24
8
IOHOLDx
IOHOLDx
16
8
IOSETx
IOSETx
0
8
IOWAITx
IOWAITx
8
8
PMEM2
PMEM2
Common memory space timing register 2
0x68
32
read-write
n
0x0
0x0
MEMHIZx
MEMHIZx
24
8
MEMHOLDx
MEMHOLDx
16
8
MEMSETx
MEMSETx
0
8
MEMWAITx
MEMWAITx
8
8
PMEM3
PMEM3
Common memory space timing register 3
0x88
32
read-write
n
0x0
0x0
MEMHIZx
MEMHIZx
24
8
MEMHOLDx
MEMHOLDx
16
8
MEMSETx
MEMSETx
0
8
MEMWAITx
MEMWAITx
8
8
PMEM4
PMEM4
Common memory space timing register 4
0xA8
32
read-write
n
0x0
0x0
MEMHIZx
MEMHIZx
24
8
MEMHOLDx
MEMHOLDx
16
8
MEMSETx
MEMSETx
0
8
MEMWAITx
MEMWAITx
8
8
SDCMR
SDCMR
SDRAM Command Mode register
0x150
32
read-write
n
0x0
0x0
CTB1
Command target bank 1
4
1
write-only
CTB2
Command target bank 2
3
1
write-only
MODE
Command mode
0
3
write-only
MRD
Mode Register definition
9
13
read-write
NRFS
Number of Auto-refresh
5
4
read-write
SDCR1
SDCR1
SDRAM Control Register 1
0x140
32
read-write
n
0x0
0x0
CAS
CAS latency
7
2
MWID
Memory data bus width
4
2
NB
Number of internal banks
6
1
NC
Number of column address bits
0
2
NR
Number of row address bits
2
2
RBURST
Burst read
12
1
RPIPE
Read pipe
13
2
SDCLK
SDRAM clock configuration
10
2
WP
Write protection
9
1
SDCR2
SDCR2
SDRAM Control Register 2
0x144
32
read-write
n
0x0
0x0
CAS
CAS latency
7
2
MWID
Memory data bus width
4
2
NB
Number of internal banks
6
1
NC
Number of column address bits
0
2
NR
Number of row address bits
2
2
SDCLK
SDRAM clock configuration
10
2
WP
Write protection
9
1
SDRTR
SDRTR
SDRAM Refresh Timer register
0x154
32
read-write
n
0x0
0x0
COUNT
Refresh Timer Count
1
13
read-write
CRE
Clear Refresh error flag
0
1
write-only
REIE
RES Interrupt Enable
14
1
read-write
SDSR
SDSR
SDRAM Status register
0x158
32
read-only
n
0x0
0x0
BUSY
Busy status
5
1
MODES1
Status Mode for Bank 1
1
2
MODES2
Status Mode for Bank 2
3
2
RE
Refresh error flag
0
1
SDTR1
SDTR1
SDRAM Timing register 1
0x148
32
read-write
n
0x0
0x0
TMRD
Load Mode Register to Active
0
4
TRAS
Self refresh time
8
4
TRC
Row cycle delay
12
4
TRCD
Row to column delay
24
4
TRP
Row precharge delay
20
4
TWR
Recovery delay
16
4
TXSR
Exit self-refresh delay
4
4
SDTR2
SDTR2
SDRAM Timing register 2
0x14C
32
read-write
n
0x0
0x0
TMRD
Load Mode Register to Active
0
4
TRAS
Self refresh time
8
4
TRC
Row cycle delay
12
4
TRCD
Row to column delay
24
4
TRP
Row precharge delay
20
4
TWR
Recovery delay
16
4
TXSR
Exit self-refresh delay
4
4
SR2
SR2
FIFO status and interrupt register 2
0x64
32
read-write
n
0x0
0x0
FEMPT
FEMPT
6
1
read-only
IFEN
IFEN
5
1
read-write
IFS
IFS
2
1
read-write
ILEN
ILEN
4
1
read-write
ILS
ILS
1
1
read-write
IREN
IREN
3
1
read-write
IRS
IRS
0
1
read-write
SR3
SR3
FIFO status and interrupt register 3
0x84
32
read-write
n
0x0
0x0
FEMPT
FEMPT
6
1
read-only
IFEN
IFEN
5
1
read-write
IFS
IFS
2
1
read-write
ILEN
ILEN
4
1
read-write
ILS
ILS
1
1
read-write
IREN
IREN
3
1
read-write
IRS
IRS
0
1
read-write
SR4
SR4
FIFO status and interrupt register 4
0xA4
32
read-write
n
0x0
0x0
FEMPT
FEMPT
6
1
read-only
IFEN
IFEN
5
1
read-write
IFS
IFS
2
1
read-write
ILEN
ILEN
4
1
read-write
ILS
ILS
1
1
read-write
IREN
IREN
3
1
read-write
IRS
IRS
0
1
read-write
FPU
Floting point unit
FPU
0x0
0x0
0xD
registers
n
FPU
Floating point interrupt
81
FPU
Floating point interrupt
81
FPCAR
FPCAR
Floating-point context address register
0x4
32
read-write
n
0x0
0x0
ADDRESS
Location of unpopulated floating-point
3
29
FPCCR
FPCCR
Floating-point context control register
0x0
32
read-write
n
0x0
0x0
ASPEN
ASPEN
31
1
BFRDY
BFRDY
6
1
HFRDY
HFRDY
4
1
LSPACT
LSPACT
0
1
LSPEN
LSPEN
30
1
MMRDY
MMRDY
5
1
MONRDY
MONRDY
8
1
THREAD
THREAD
3
1
USER
USER
1
1
FPSCR
FPSCR
Floating-point status control register
0x8
32
read-write
n
0x0
0x0
AHP
Alternative half-precision control bit
26
1
C
Carry condition code flag
29
1
DN
Default NaN mode control bit
25
1
DZC
Division by zero cumulative exception bit.
1
1
FZ
Flush-to-zero mode control bit:
24
1
IDC
Input denormal cumulative exception bit.
7
1
IOC
Invalid operation cumulative exception bit
0
1
IXC
Inexact cumulative exception bit
4
1
N
Negative condition code flag
31
1
OFC
Overflow cumulative exception bit
2
1
RMode
Rounding Mode control field
22
2
UFC
Underflow cumulative exception bit
3
1
V
Overflow condition code flag
28
1
Z
Zero condition code flag
30
1
FPU_CPACR
Floating point unit CPACR
FPU
0x0
0x0
0x5
registers
n
CPACR
CPACR
Coprocessor access control register
0x0
32
read-write
n
0x0
0x0
CP
CP
20
4
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOC
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOD
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOE
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOF
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOG
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOH
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOI
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOJ
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOK
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
HASH
Hash processor
HASH
0x0
0x0
0x400
registers
n
HASH_RNG
Hash and Rng global interrupt
80
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
ALGO0
Algorithm selection
7
1
read-write
ALGO1
ALGO
18
1
read-write
DATATYPE
Data type selection
4
2
read-write
DINNE
DIN not empty
12
1
read-only
DMAE
DMA enable
3
1
read-write
INIT
Initialize message digest calculation
2
1
write-only
LKEY
Long key selection
16
1
read-write
MDMAT
Multiple DMA Transfers
13
1
read-write
MODE
Mode selection
6
1
read-write
NBW
Number of words already pushed
8
4
read-only
CSR0
CSR0
context swap registers
0xF8
32
read-write
n
0x0
0x0
CSR0
CSR0
0
32
CSR1
CSR1
context swap registers
0xFC
32
read-write
n
0x0
0x0
CSR1
CSR1
0
32
CSR10
CSR10
context swap registers
0x120
32
read-write
n
0x0
0x0
CSR10
CSR10
0
32
CSR11
CSR11
context swap registers
0x124
32
read-write
n
0x0
0x0
CSR11
CSR11
0
32
CSR12
CSR12
context swap registers
0x128
32
read-write
n
0x0
0x0
CSR12
CSR12
0
32
CSR13
CSR13
context swap registers
0x12C
32
read-write
n
0x0
0x0
CSR13
CSR13
0
32
CSR14
CSR14
context swap registers
0x130
32
read-write
n
0x0
0x0
CSR14
CSR14
0
32
CSR15
CSR15
context swap registers
0x134
32
read-write
n
0x0
0x0
CSR15
CSR15
0
32
CSR16
CSR16
context swap registers
0x138
32
read-write
n
0x0
0x0
CSR16
CSR16
0
32
CSR17
CSR17
context swap registers
0x13C
32
read-write
n
0x0
0x0
CSR17
CSR17
0
32
CSR18
CSR18
context swap registers
0x140
32
read-write
n
0x0
0x0
CSR18
CSR18
0
32
CSR19
CSR19
context swap registers
0x144
32
read-write
n
0x0
0x0
CSR19
CSR19
0
32
CSR2
CSR2
context swap registers
0x100
32
read-write
n
0x0
0x0
CSR2
CSR2
0
32
CSR20
CSR20
context swap registers
0x148
32
read-write
n
0x0
0x0
CSR20
CSR20
0
32
CSR21
CSR21
context swap registers
0x14C
32
read-write
n
0x0
0x0
CSR21
CSR21
0
32
CSR22
CSR22
context swap registers
0x150
32
read-write
n
0x0
0x0
CSR22
CSR22
0
32
CSR23
CSR23
context swap registers
0x154
32
read-write
n
0x0
0x0
CSR23
CSR23
0
32
CSR24
CSR24
context swap registers
0x158
32
read-write
n
0x0
0x0
CSR24
CSR24
0
32
CSR25
CSR25
context swap registers
0x15C
32
read-write
n
0x0
0x0
CSR25
CSR25
0
32
CSR26
CSR26
context swap registers
0x160
32
read-write
n
0x0
0x0
CSR26
CSR26
0
32
CSR27
CSR27
context swap registers
0x164
32
read-write
n
0x0
0x0
CSR27
CSR27
0
32
CSR28
CSR28
context swap registers
0x168
32
read-write
n
0x0
0x0
CSR28
CSR28
0
32
CSR29
CSR29
context swap registers
0x16C
32
read-write
n
0x0
0x0
CSR29
CSR29
0
32
CSR3
CSR3
context swap registers
0x104
32
read-write
n
0x0
0x0
CSR3
CSR3
0
32
CSR30
CSR30
context swap registers
0x170
32
read-write
n
0x0
0x0
CSR30
CSR30
0
32
CSR31
CSR31
context swap registers
0x174
32
read-write
n
0x0
0x0
CSR31
CSR31
0
32
CSR32
CSR32
context swap registers
0x178
32
read-write
n
0x0
0x0
CSR32
CSR32
0
32
CSR33
CSR33
context swap registers
0x17C
32
read-write
n
0x0
0x0
CSR33
CSR33
0
32
CSR34
CSR34
context swap registers
0x180
32
read-write
n
0x0
0x0
CSR34
CSR34
0
32
CSR35
CSR35
context swap registers
0x184
32
read-write
n
0x0
0x0
CSR35
CSR35
0
32
CSR36
CSR36
context swap registers
0x188
32
read-write
n
0x0
0x0
CSR36
CSR36
0
32
CSR37
CSR37
context swap registers
0x18C
32
read-write
n
0x0
0x0
CSR37
CSR37
0
32
CSR38
CSR38
context swap registers
0x190
32
read-write
n
0x0
0x0
CSR38
CSR38
0
32
CSR39
CSR39
context swap registers
0x194
32
read-write
n
0x0
0x0
CSR39
CSR39
0
32
CSR4
CSR4
context swap registers
0x108
32
read-write
n
0x0
0x0
CSR4
CSR4
0
32
CSR40
CSR40
context swap registers
0x198
32
read-write
n
0x0
0x0
CSR40
CSR40
0
32
CSR41
CSR41
context swap registers
0x19C
32
read-write
n
0x0
0x0
CSR41
CSR41
0
32
CSR42
CSR42
context swap registers
0x1A0
32
read-write
n
0x0
0x0
CSR42
CSR42
0
32
CSR43
CSR43
context swap registers
0x1A4
32
read-write
n
0x0
0x0
CSR43
CSR43
0
32
CSR44
CSR44
context swap registers
0x1A8
32
read-write
n
0x0
0x0
CSR44
CSR44
0
32
CSR45
CSR45
context swap registers
0x1AC
32
read-write
n
0x0
0x0
CSR45
CSR45
0
32
CSR46
CSR46
context swap registers
0x1B0
32
read-write
n
0x0
0x0
CSR46
CSR46
0
32
CSR47
CSR47
context swap registers
0x1B4
32
read-write
n
0x0
0x0
CSR47
CSR47
0
32
CSR48
CSR48
context swap registers
0x1B8
32
read-write
n
0x0
0x0
CSR48
CSR48
0
32
CSR49
CSR49
context swap registers
0x1BC
32
read-write
n
0x0
0x0
CSR49
CSR49
0
32
CSR5
CSR5
context swap registers
0x10C
32
read-write
n
0x0
0x0
CSR5
CSR5
0
32
CSR50
CSR50
context swap registers
0x1C0
32
read-write
n
0x0
0x0
CSR50
CSR50
0
32
CSR51
CSR51
context swap registers
0x1C4
32
read-write
n
0x0
0x0
CSR51
CSR51
0
32
CSR52
CSR52
context swap registers
0x1C8
32
read-write
n
0x0
0x0
CSR52
CSR52
0
32
CSR53
CSR53
context swap registers
0x1CC
32
read-write
n
0x0
0x0
CSR53
CSR53
0
32
CSR6
CSR6
context swap registers
0x110
32
read-write
n
0x0
0x0
CSR6
CSR6
0
32
CSR7
CSR7
context swap registers
0x114
32
read-write
n
0x0
0x0
CSR7
CSR7
0
32
CSR8
CSR8
context swap registers
0x118
32
read-write
n
0x0
0x0
CSR8
CSR8
0
32
CSR9
CSR9
context swap registers
0x11C
32
read-write
n
0x0
0x0
CSR9
CSR9
0
32
DIN
DIN
data input register
0x4
32
read-write
n
0x0
0x0
DATAIN
Data input
0
32
HR0
HR0
digest registers
0xC
32
read-only
n
0x0
0x0
H0
H0
0
32
HR1
HR1
digest registers
0x10
32
read-only
n
0x0
0x0
H1
H1
0
32
HR2
HR2
digest registers
0x14
32
read-only
n
0x0
0x0
H2
H2
0
32
HR3
HR3
digest registers
0x18
32
read-only
n
0x0
0x0
H3
H3
0
32
HR4
HR4
digest registers
0x1C
32
read-only
n
0x0
0x0
H4
H4
0
32
HR5
HASH_HR5
read-only
0x324
32
read-only
n
0x0
0x0
H5
H5
0
32
HR6
HASH_HR6
read-only
0x328
32
read-only
n
0x0
0x0
H6
H6
0
32
HR7
HASH_HR7
read-only
0x32C
32
read-only
n
0x0
0x0
H7
H7
0
32
IMR
IMR
interrupt enable register
0x20
32
read-write
n
0x0
0x0
DCIE
Digest calculation completion interrupt enable
1
1
DINIE
Data input interrupt enable
0
1
SR
SR
status register
0x24
32
read-write
n
0x0
0x0
BUSY
Busy bit
3
1
read-only
DCIS
Digest calculation completion interrupt status
1
1
read-write
DINIS
Data input interrupt status
0
1
read-write
DMAS
DMA Status
2
1
read-only
STR
STR
start register
0x8
32
read-write
n
0x0
0x0
DCAL
Digest calculation
8
1
write-only
NBLW
Number of valid bits in the last word of the message
0
5
read-write
I2C1
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
CCR
CCR
Clock control register
0x1C
32
read-write
n
0x0
0x0
CCR
Clock control register in Fast/Standard mode (Master mode)
0
12
DUTY
Fast mode duty cycle
14
1
F_S
I2C master mode selection
15
1
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACK
Acknowledge enable
10
1
ALERT
SMBus alert
13
1
ENARP
ARP enable
4
1
ENGC
General call enable
6
1
ENPEC
PEC enable
5
1
NOSTRETCH
Clock stretching disable (Slave mode)
7
1
PE
Peripheral enable
0
1
PEC
Packet error checking
12
1
POS
Acknowledge/PEC Position (for data reception)
11
1
SMBTYPE
SMBus type
3
1
SMBUS
SMBus mode
1
1
START
Start generation
8
1
STOP
Stop generation
9
1
SWRST
Software reset
15
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
DMAEN
DMA requests enable
11
1
FREQ
Peripheral clock frequency
0
6
ITBUFEN
Buffer interrupt enable
10
1
ITERREN
Error interrupt enable
8
1
ITEVTEN
Event interrupt enable
9
1
LAST
DMA last transfer
12
1
DR
DR
Data register
0x10
32
read-write
n
0x0
0x0
DR
8-bit data register
0
8
FLTR
FLTR
I2C FLTR register
0x24
32
read-write
n
0x0
0x0
ANOFF
Analog noise filter OFF
4
1
DNF
Digital noise filter
0
4
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD10
Interface address
8
2
ADD7
Interface address
1
7
ADDMODE
Addressing mode (slave mode)
15
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
ENDUAL
Dual addressing mode enable
0
1
SR1
SR1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADD10
10-bit header sent (Master mode)
3
1
read-only
ADDR
Address sent (master mode)/matched (slave mode)
1
1
read-only
AF
Acknowledge failure
10
1
read-write
ARLO
Arbitration lost (master mode)
9
1
read-write
BERR
Bus error
8
1
read-write
BTF
Byte transfer finished
2
1
read-only
OVR
Overrun/Underrun
11
1
read-write
PECERR
PEC Error in reception
12
1
read-write
RxNE
Data register not empty (receivers)
6
1
read-only
SB
Start bit (Master mode)
0
1
read-only
SMBALERT
SMBus alert
15
1
read-write
STOPF
Stop detection (slave mode)
4
1
read-only
TIMEOUT
Timeout or Tlow error
14
1
read-write
TxE
Data register empty (transmitters)
7
1
read-only
SR2
SR2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSY
Bus busy
1
1
DUALF
Dual flag (Slave mode)
7
1
GENCALL
General call address (Slave mode)
4
1
MSL
Master/slave
0
1
PEC
acket error checking register
8
8
SMBDEFAULT
SMBus device default address (Slave mode)
5
1
SMBHOST
SMBus host header (Slave mode)
6
1
TRA
Transmitter/receiver
2
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
I2C2
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
CCR
CCR
Clock control register
0x1C
32
read-write
n
0x0
0x0
CCR
Clock control register in Fast/Standard mode (Master mode)
0
12
DUTY
Fast mode duty cycle
14
1
F_S
I2C master mode selection
15
1
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACK
Acknowledge enable
10
1
ALERT
SMBus alert
13
1
ENARP
ARP enable
4
1
ENGC
General call enable
6
1
ENPEC
PEC enable
5
1
NOSTRETCH
Clock stretching disable (Slave mode)
7
1
PE
Peripheral enable
0
1
PEC
Packet error checking
12
1
POS
Acknowledge/PEC Position (for data reception)
11
1
SMBTYPE
SMBus type
3
1
SMBUS
SMBus mode
1
1
START
Start generation
8
1
STOP
Stop generation
9
1
SWRST
Software reset
15
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
DMAEN
DMA requests enable
11
1
FREQ
Peripheral clock frequency
0
6
ITBUFEN
Buffer interrupt enable
10
1
ITERREN
Error interrupt enable
8
1
ITEVTEN
Event interrupt enable
9
1
LAST
DMA last transfer
12
1
DR
DR
Data register
0x10
32
read-write
n
0x0
0x0
DR
8-bit data register
0
8
FLTR
FLTR
I2C FLTR register
0x24
32
read-write
n
0x0
0x0
ANOFF
Analog noise filter OFF
4
1
DNF
Digital noise filter
0
4
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD10
Interface address
8
2
ADD7
Interface address
1
7
ADDMODE
Addressing mode (slave mode)
15
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
ENDUAL
Dual addressing mode enable
0
1
SR1
SR1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADD10
10-bit header sent (Master mode)
3
1
read-only
ADDR
Address sent (master mode)/matched (slave mode)
1
1
read-only
AF
Acknowledge failure
10
1
read-write
ARLO
Arbitration lost (master mode)
9
1
read-write
BERR
Bus error
8
1
read-write
BTF
Byte transfer finished
2
1
read-only
OVR
Overrun/Underrun
11
1
read-write
PECERR
PEC Error in reception
12
1
read-write
RxNE
Data register not empty (receivers)
6
1
read-only
SB
Start bit (Master mode)
0
1
read-only
SMBALERT
SMBus alert
15
1
read-write
STOPF
Stop detection (slave mode)
4
1
read-only
TIMEOUT
Timeout or Tlow error
14
1
read-write
TxE
Data register empty (transmitters)
7
1
read-only
SR2
SR2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSY
Bus busy
1
1
DUALF
Dual flag (Slave mode)
7
1
GENCALL
General call address (Slave mode)
4
1
MSL
Master/slave
0
1
PEC
acket error checking register
8
8
SMBDEFAULT
SMBus device default address (Slave mode)
5
1
SMBHOST
SMBus host header (Slave mode)
6
1
TRA
Transmitter/receiver
2
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
I2C3
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C3_EV
I2C3 event interrupt
72
I2C3_ER
I2C3 error interrupt
73
CCR
CCR
Clock control register
0x1C
32
read-write
n
0x0
0x0
CCR
Clock control register in Fast/Standard mode (Master mode)
0
12
DUTY
Fast mode duty cycle
14
1
F_S
I2C master mode selection
15
1
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACK
Acknowledge enable
10
1
ALERT
SMBus alert
13
1
ENARP
ARP enable
4
1
ENGC
General call enable
6
1
ENPEC
PEC enable
5
1
NOSTRETCH
Clock stretching disable (Slave mode)
7
1
PE
Peripheral enable
0
1
PEC
Packet error checking
12
1
POS
Acknowledge/PEC Position (for data reception)
11
1
SMBTYPE
SMBus type
3
1
SMBUS
SMBus mode
1
1
START
Start generation
8
1
STOP
Stop generation
9
1
SWRST
Software reset
15
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
DMAEN
DMA requests enable
11
1
FREQ
Peripheral clock frequency
0
6
ITBUFEN
Buffer interrupt enable
10
1
ITERREN
Error interrupt enable
8
1
ITEVTEN
Event interrupt enable
9
1
LAST
DMA last transfer
12
1
DR
DR
Data register
0x10
32
read-write
n
0x0
0x0
DR
8-bit data register
0
8
FLTR
FLTR
I2C FLTR register
0x24
32
read-write
n
0x0
0x0
ANOFF
Analog noise filter OFF
4
1
DNF
Digital noise filter
0
4
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD10
Interface address
8
2
ADD7
Interface address
1
7
ADDMODE
Addressing mode (slave mode)
15
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
ENDUAL
Dual addressing mode enable
0
1
SR1
SR1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADD10
10-bit header sent (Master mode)
3
1
read-only
ADDR
Address sent (master mode)/matched (slave mode)
1
1
read-only
AF
Acknowledge failure
10
1
read-write
ARLO
Arbitration lost (master mode)
9
1
read-write
BERR
Bus error
8
1
read-write
BTF
Byte transfer finished
2
1
read-only
OVR
Overrun/Underrun
11
1
read-write
PECERR
PEC Error in reception
12
1
read-write
RxNE
Data register not empty (receivers)
6
1
read-only
SB
Start bit (Master mode)
0
1
read-only
SMBALERT
SMBus alert
15
1
read-write
STOPF
Stop detection (slave mode)
4
1
read-only
TIMEOUT
Timeout or Tlow error
14
1
read-write
TxE
Data register empty (transmitters)
7
1
read-only
SR2
SR2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSY
Bus busy
1
1
DUALF
Dual flag (Slave mode)
7
1
GENCALL
General call address (Slave mode)
4
1
MSL
Master/slave
0
1
PEC
acket error checking register
8
8
SMBDEFAULT
SMBus device default address (Slave mode)
5
1
SMBHOST
SMBus host header (Slave mode)
6
1
TRA
Transmitter/receiver
2
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
I2S2ext
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
I2S3ext
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
IWDG
Independent watchdog
IWDG
0x0
0x0
0x400
registers
n
KR
KR
Key register
0x0
32
write-only
n
0x0
0x0
KEY
Key value (write only, read 0000h)
0
16
PR
PR
Prescaler register
0x4
32
read-write
n
0x0
0x0
PR
Prescaler divider
0
3
RLR
RLR
Reload register
0x8
32
read-write
n
0x0
0x0
RL
Watchdog counter reload value
0
12
SR
SR
Status register
0xC
32
read-only
n
0x0
0x0
PVU
Watchdog prescaler value update
0
1
RVU
Watchdog counter reload value update
1
1
LTDC
LCD-TFT Controller
LTDC
0x0
0x0
0x400
registers
n
LCD_TFT
LTDC global interrupt
88
LCD_TFT_1
LTDC global error interrupt
89
AWCR
AWCR
Active Width Configuration Register
0x10
32
read-write
n
0x0
0x0
AAH
Accumulated Active Height (in units of horizontal scan line)
0
11
AAV
AAV
16
10
BCCR
BCCR
Background Color Configuration Register
0x2C
32
read-write
n
0x0
0x0
BC
Background Color Red value
0
24
BPCR
BPCR
Back Porch Configuration Register
0xC
32
read-write
n
0x0
0x0
AHBP
Accumulated Horizontal back porch (in units of pixel clock period)
16
10
AVBP
Accumulated Vertical back porch (in units of horizontal scan line)
0
11
CDSR
CDSR
Current Display Status Register
0x48
32
read-only
n
0x0
0x0
HDES
Horizontal Data Enable display Status
1
1
HSYNCS
Horizontal Synchronization display Status
3
1
VDES
Vertical Data Enable display Status
0
1
VSYNCS
Vertical Synchronization display Status
2
1
CPSR
CPSR
Current Position Status Register
0x44
32
read-only
n
0x0
0x0
CXPOS
Current X Position
16
16
CYPOS
Current Y Position
0
16
GCR
GCR
Global Control Register
0x18
32
read-write
n
0x0
0x0
DBW
Dither Blue Width
4
3
read-only
DEN
Dither Enable
16
1
read-write
DEPOL
Data Enable Polarity
29
1
read-write
DGW
Dither Green Width
8
3
read-only
DRW
Dither Red Width
12
3
read-only
HSPOL
Horizontal Synchronization Polarity
31
1
read-write
LTDCEN
LCD-TFT controller enable bit
0
1
read-write
PCPOL
Pixel Clock Polarity
28
1
read-write
VSPOL
Vertical Synchronization Polarity
30
1
read-write
ICR
ICR
Interrupt Clear Register
0x3C
32
write-only
n
0x0
0x0
CFUIF
Clears the FIFO Underrun Interrupt flag
1
1
CLIF
Clears the Line Interrupt Flag
0
1
CRRIF
Clears Register Reload Interrupt Flag
3
1
CTERRIF
Clears the Transfer Error Interrupt Flag
2
1
IER
IER
Interrupt Enable Register
0x34
32
read-write
n
0x0
0x0
FUIE
FIFO Underrun Interrupt Enable
1
1
LIE
Line Interrupt Enable
0
1
RRIE
Register Reload interrupt enable
3
1
TERRIE
Transfer Error Interrupt Enable
2
1
ISR
ISR
Interrupt Status Register
0x38
32
read-only
n
0x0
0x0
FUIF
FIFO Underrun Interrupt flag
1
1
LIF
Line Interrupt flag
0
1
RRIF
Register Reload Interrupt Flag
3
1
TERRIF
Transfer Error interrupt flag
2
1
L1BFCR
L1BFCR
Layerx Blending Factors Configuration Register
0xA0
32
read-write
n
0x0
0x0
BF1
Blending Factor 1
8
3
BF2
Blending Factor 2
0
3
L1CACR
L1CACR
Layerx Constant Alpha Configuration Register
0x98
32
read-write
n
0x0
0x0
CONSTA
Constant Alpha
0
8
L1CFBAR
L1CFBAR
Layerx Color Frame Buffer Address Register
0xAC
32
read-write
n
0x0
0x0
CFBADD
Color Frame Buffer Start Address
0
32
L1CFBLNR
L1CFBLNR
Layerx ColorFrame Buffer Line Number Register
0xB4
32
read-write
n
0x0
0x0
CFBLNBR
Frame Buffer Line Number
0
11
L1CFBLR
L1CFBLR
Layerx Color Frame Buffer Length Register
0xB0
32
read-write
n
0x0
0x0
CFBLL
Color Frame Buffer Line Length
0
13
CFBP
Color Frame Buffer Pitch in bytes
16
13
L1CKCR
L1CKCR
Layerx Color Keying Configuration Register
0x90
32
read-write
n
0x0
0x0
CKBLUE
Color Key Blue value
0
8
CKGREEN
Color Key Green value
8
8
CKRED
Color Key Red value
16
8
L1CLUTWR
L1CLUTWR
Layerx CLUT Write Register
0xC4
32
write-only
n
0x0
0x0
BLUE
Blue value
0
8
CLUTADD
CLUT Address
24
8
GREEN
Green value
8
8
RED
Red value
16
8
L1CR
L1CR
Layerx Control Register
0x84
32
read-write
n
0x0
0x0
CLUTEN
Color Look-Up Table Enable
4
1
COLKEN
Color Keying Enable
1
1
LEN
Layer Enable
0
1
L1DCCR
L1DCCR
Layerx Default Color Configuration Register
0x9C
32
read-write
n
0x0
0x0
DCALPHA
Default Color Alpha
24
8
DCBLUE
Default Color Blue
0
8
DCGREEN
Default Color Green
8
8
DCRED
Default Color Red
16
8
L1PFCR
L1PFCR
Layerx Pixel Format Configuration Register
0x94
32
read-write
n
0x0
0x0
PF
Pixel Format
0
3
L1WHPCR
L1WHPCR
Layerx Window Horizontal Position Configuration Register
0x88
32
read-write
n
0x0
0x0
WHSPPOS
Window Horizontal Stop Position
16
12
WHSTPOS
Window Horizontal Start Position
0
12
L1WVPCR
L1WVPCR
Layerx Window Vertical Position Configuration Register
0x8C
32
read-write
n
0x0
0x0
WVSPPOS
Window Vertical Stop Position
16
11
WVSTPOS
Window Vertical Start Position
0
11
L2BFCR
L2BFCR
Layerx Blending Factors Configuration Register
0x120
32
read-write
n
0x0
0x0
BF1
Blending Factor 1
8
3
BF2
Blending Factor 2
0
3
L2CACR
L2CACR
Layerx Constant Alpha Configuration Register
0x118
32
read-write
n
0x0
0x0
CONSTA
Constant Alpha
0
8
L2CFBAR
L2CFBAR
Layerx Color Frame Buffer Address Register
0x12C
32
read-write
n
0x0
0x0
CFBADD
Color Frame Buffer Start Address
0
32
L2CFBLNR
L2CFBLNR
Layerx ColorFrame Buffer Line Number Register
0x134
32
read-write
n
0x0
0x0
CFBLNBR
Frame Buffer Line Number
0
11
L2CFBLR
L2CFBLR
Layerx Color Frame Buffer Length Register
0x130
32
read-write
n
0x0
0x0
CFBLL
Color Frame Buffer Line Length
0
13
CFBP
Color Frame Buffer Pitch in bytes
16
13
L2CKCR
L2CKCR
Layerx Color Keying Configuration Register
0x110
32
read-write
n
0x0
0x0
CKBLUE
Color Key Blue value
0
8
CKGREEN
Color Key Green value
8
7
CKRED
Color Key Red value
15
9
L2CLUTWR
L2CLUTWR
Layerx CLUT Write Register
0x144
32
write-only
n
0x0
0x0
BLUE
Blue value
0
8
CLUTADD
CLUT Address
24
8
GREEN
Green value
8
8
RED
Red value
16
8
L2CR
L2CR
Layerx Control Register
0x104
32
read-write
n
0x0
0x0
CLUTEN
Color Look-Up Table Enable
4
1
COLKEN
Color Keying Enable
1
1
LEN
Layer Enable
0
1
L2DCCR
L2DCCR
Layerx Default Color Configuration Register
0x11C
32
read-write
n
0x0
0x0
DCALPHA
Default Color Alpha
24
8
DCBLUE
Default Color Blue
0
8
DCGREEN
Default Color Green
8
8
DCRED
Default Color Red
16
8
L2PFCR
L2PFCR
Layerx Pixel Format Configuration Register
0x114
32
read-write
n
0x0
0x0
PF
Pixel Format
0
3
L2WHPCR
L2WHPCR
Layerx Window Horizontal Position Configuration Register
0x108
32
read-write
n
0x0
0x0
WHSPPOS
Window Horizontal Stop Position
16
12
WHSTPOS
Window Horizontal Start Position
0
12
L2WVPCR
L2WVPCR
Layerx Window Vertical Position Configuration Register
0x10C
32
read-write
n
0x0
0x0
WVSPPOS
Window Vertical Stop Position
16
11
WVSTPOS
Window Vertical Start Position
0
11
LIPCR
LIPCR
Line Interrupt Position Configuration Register
0x40
32
read-write
n
0x0
0x0
LIPOS
Line Interrupt Position
0
11
SRCR
SRCR
Shadow Reload Configuration Register
0x24
32
read-write
n
0x0
0x0
IMR
Immediate Reload
0
1
VBR
Vertical Blanking Reload
1
1
SSCR
SSCR
Synchronization Size Configuration Register
0x8
32
read-write
n
0x0
0x0
HSW
Horizontal Synchronization Width (in units of pixel clock period)
16
10
VSH
Vertical Synchronization Height (in units of horizontal scan line)
0
11
TWCR
TWCR
Total Width Configuration Register
0x14
32
read-write
n
0x0
0x0
TOTALH
Total Height (in units of horizontal scan line)
0
11
TOTALW
Total Width (in units of pixel clock period)
16
10
MPU
Memory protection unit
MPU
0x0
0x0
0x15
registers
n
CTRL
MPU_CTRL
MPU control register
0x4
32
read-only
n
0x0
0x0
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard fault
1
1
PRIVDEFENA
Enable priviliged software access to default memory map
2
1
RASR
MPU_RASR
MPU region attribute and size register
0x10
32
read-write
n
0x0
0x0
AP
Access permission
24
3
B
memory attribute
16
1
C
memory attribute
17
1
ENABLE
Region enable bit.
0
1
S
Shareable memory attribute
18
1
SIZE
Size of the MPU protection region
1
5
SRD
Subregion disable bits
8
8
TEX
memory attribute
19
3
XN
Instruction access disable bit
28
1
RBAR
MPU_RBAR
MPU region base address register
0xC
32
read-write
n
0x0
0x0
ADDR
Region base address field
5
27
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
RNR
MPU_RNR
MPU region number register
0x8
32
read-write
n
0x0
0x0
REGION
MPU region
0
8
TYPER
MPU_TYPER
MPU type register
0x0
32
read-only
n
0x0
0x0
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction regions
16
8
SEPARATE
Separate flag
0
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x355
registers
n
IABR0
IABR0
Interrupt Active Bit Register
0x200
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x204
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR2
IABR2
Interrupt Active Bit Register
0x208
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
ICER0
ICER0
Interrupt Clear-Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable Register
0x84
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER2
ICER2
Interrupt Clear-Enable Register
0x88
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR0
ICPR0
Interrupt Clear-Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending Register
0x184
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR2
ICPR2
Interrupt Clear-Pending Register
0x188
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
IPR0
IPR0
Interrupt Priority Register
0x300
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x304
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x328
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x32C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x330
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x334
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x338
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR15
IPR15
Interrupt Priority Register
0x33C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR16
IPR16
Interrupt Priority Register
0x340
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR17
IPR17
Interrupt Priority Register
0x344
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR18
IPR18
Interrupt Priority Register
0x348
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR19
IPR19
Interrupt Priority Register
0x34C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x308
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR20
IPR20
Interrupt Priority Register
0x350
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x30C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x310
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x314
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x318
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x31C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x320
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x324
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
ISER0
ISER0
Interrupt Set-Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x4
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER2
ISER2
Interrupt Set-Enable Register
0x8
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x104
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR2
ISPR2
Interrupt Set-Pending Register
0x108
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
NVIC_STIR
Nested vectored interrupt controller
NVIC
0x0
0x0
0x5
registers
n
STIR
STIR
Software trigger interrupt register
0x0
32
read-write
n
0x0
0x0
INTID
Software generated interrupt ID
0
9
OTG_FS_DEVICE
USB on the go full speed
USB_OTG_FS
0x0
0x0
0x400
registers
n
DIEPCTL1
DIEPCTL1
OTG device endpoint-1 control register
0x120
32
read-write
n
0x0
0x0
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SODDFRM_SD1PID
SODDFRM/SD1PID
29
1
write-only
Stall
Stall
21
1
read-write
TXFNUM
TXFNUM
22
4
read-write
USBAEP
USBAEP
15
1
read-write
DIEPCTL2
DIEPCTL2
OTG device endpoint-2 control register
0x140
32
read-write
n
0x0
0x0
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
TXFNUM
TXFNUM
22
4
read-write
USBAEP
USBAEP
15
1
read-write
DIEPCTL3
DIEPCTL3
OTG device endpoint-3 control register
0x160
32
read-write
n
0x0
0x0
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
TXFNUM
TXFNUM
22
4
read-write
USBAEP
USBAEP
15
1
read-write
DIEPEMPMSK
DIEPEMPMSK
OTG_FS device IN endpoint FIFO empty interrupt mask register
0x34
32
read-write
n
0x0
0x0
INEPTXFEM
IN EP Tx FIFO empty interrupt mask bits
0
16
DIEPINT0
DIEPINT0
device endpoint-x interrupt register
0x108
32
read-write
n
0x0
0x0
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPINT1
DIEPINT1
device endpoint-1 interrupt register
0x128
32
read-write
n
0x0
0x0
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPINT2
DIEPINT2
device endpoint-2 interrupt register
0x148
32
read-write
n
0x0
0x0
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPINT3
DIEPINT3
device endpoint-3 interrupt register
0x168
32
read-write
n
0x0
0x0
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPTSIZ0
DIEPTSIZ0
device endpoint-0 transfer size register
0x110
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
2
XFRSIZ
Transfer size
0
7
DIEPTSIZ1
DIEPTSIZ1
device endpoint-1 transfer size register
0x130
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
DIEPTSIZ2
DIEPTSIZ2
device endpoint-2 transfer size register
0x150
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
DIEPTSIZ3
DIEPTSIZ3
device endpoint-3 transfer size register
0x170
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
DOEPCTL0
DOEPCTL0
device endpoint-0 control register
0x300
32
read-write
n
0x0
0x0
CNAK
CNAK
26
1
write-only
EPDIS
EPDIS
30
1
read-only
EPENA
EPENA
31
1
write-only
EPTYP
EPTYP
18
2
read-only
MPSIZ
MPSIZ
0
2
read-only
NAKSTS
NAKSTS
17
1
read-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-only
DOEPCTL1
DOEPCTL1
device endpoint-1 control register
0x320
32
read-write
n
0x0
0x0
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-write
DOEPCTL2
DOEPCTL2
device endpoint-2 control register
0x340
32
read-write
n
0x0
0x0
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-write
DOEPCTL3
DOEPCTL3
device endpoint-3 control register
0x360
32
read-write
n
0x0
0x0
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-write
DOEPINT0
DOEPINT0
device endpoint-0 interrupt register
0x308
32
read-write
n
0x0
0x0
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPINT1
DOEPINT1
device endpoint-1 interrupt register
0x328
32
read-write
n
0x0
0x0
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPINT2
DOEPINT2
device endpoint-2 interrupt register
0x348
32
read-write
n
0x0
0x0
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPINT3
DOEPINT3
device endpoint-3 interrupt register
0x368
32
read-write
n
0x0
0x0
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPTSIZ0
DOEPTSIZ0
device OUT endpoint-0 transfer size register
0x310
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
1
STUPCNT
SETUP packet count
29
2
XFRSIZ
Transfer size
0
7
DOEPTSIZ1
DOEPTSIZ1
device OUT endpoint-1 transfer size register
0x330
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
DOEPTSIZ2
DOEPTSIZ2
device OUT endpoint-2 transfer size register
0x350
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
DOEPTSIZ3
DOEPTSIZ3
device OUT endpoint-3 transfer size register
0x370
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
DTXFSTS0
DTXFSTS0
OTG_FS device IN endpoint transmit FIFO status register
0x118
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DTXFSTS1
DTXFSTS1
OTG_FS device IN endpoint transmit FIFO status register
0x138
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DTXFSTS2
DTXFSTS2
OTG_FS device IN endpoint transmit FIFO status register
0x158
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DTXFSTS3
DTXFSTS3
OTG_FS device IN endpoint transmit FIFO status register
0x178
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DVBUSDIS
DVBUSDIS
OTG_FS device VBUS discharge time register
0x28
32
read-write
n
0x0
0x0
VBUSDT
Device VBUS discharge time
0
16
DVBUSPULSE
DVBUSPULSE
OTG_FS device VBUS pulsing time register
0x2C
32
read-write
n
0x0
0x0
DVBUSP
Device VBUS pulsing time
0
12
FS_DAINT
FS_DAINT
OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
0x18
32
read-only
n
0x0
0x0
IEPINT
IN endpoint interrupt bits
0
16
OEPINT
OUT endpoint interrupt bits
16
16
FS_DAINTMSK
FS_DAINTMSK
OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
0x1C
32
read-write
n
0x0
0x0
IEPM
IN EP interrupt mask bits
0
16
OEPINT
OUT endpoint interrupt bits
16
16
FS_DCFG
FS_DCFG
OTG_FS device configuration register (OTG_FS_DCFG)
0x0
32
read-write
n
0x0
0x0
DAD
Device address
4
7
DSPD
Device speed
0
2
NZLSOHSK
Non-zero-length status OUT handshake
2
1
PFIVL
Periodic frame interval
11
2
FS_DCTL
FS_DCTL
OTG_FS device control register (OTG_FS_DCTL)
0x4
32
read-write
n
0x0
0x0
CGINAK
Clear global IN NAK
8
1
read-write
CGONAK
Clear global OUT NAK
10
1
read-write
GINSTS
Global IN NAK status
2
1
read-only
GONSTS
Global OUT NAK status
3
1
read-only
POPRGDNE
Power-on programming done
11
1
read-write
RWUSIG
Remote wakeup signaling
0
1
read-write
SDIS
Soft disconnect
1
1
read-write
SGINAK
Set global IN NAK
7
1
read-write
SGONAK
Set global OUT NAK
9
1
read-write
TCTL
Test control
4
3
read-write
FS_DIEPCTL0
FS_DIEPCTL0
OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
0x100
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EPDIS
Endpoint disable
30
1
read-only
EPENA
Endpoint enable
31
1
read-only
EPTYP
Endpoint type
18
2
read-only
MPSIZ
Maximum packet size
0
2
read-write
NAKSTS
NAK status
17
1
read-only
SNAK
Set NAK
27
1
write-only
STALL
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-only
FS_DIEPMSK
FS_DIEPMSK
OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
0x10
32
read-write
n
0x0
0x0
EPDM
Endpoint disabled interrupt mask
1
1
INEPNEM
IN endpoint NAK effective mask
6
1
INEPNMM
IN token received with EP mismatch mask
5
1
ITTXFEMSK
IN token received when TxFIFO empty mask
4
1
TOM
Timeout condition mask (Non-isochronous endpoints)
3
1
XFRCM
Transfer completed interrupt mask
0
1
FS_DOEPMSK
FS_DOEPMSK
OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
0x14
32
read-write
n
0x0
0x0
EPDM
Endpoint disabled interrupt mask
1
1
OTEPDM
OUT token received when endpoint disabled mask
4
1
STUPM
SETUP phase done mask
3
1
XFRCM
Transfer completed interrupt mask
0
1
FS_DSTS
FS_DSTS
OTG_FS device status register (OTG_FS_DSTS)
0x8
32
read-only
n
0x0
0x0
EERR
Erratic error
3
1
ENUMSPD
Enumerated speed
1
2
FNSOF
Frame number of the received SOF
8
14
SUSPSTS
Suspend status
0
1
OTG_FS_GLOBAL
USB on the go full speed
USB_OTG_FS
0x0
0x0
0x400
registers
n
OTG_FS_WKUP
USB On-The-Go FS Wakeup through EXTI line interrupt
42
OTG_FS
USB On The Go FS global interrupt
67
FS_CID
FS_CID
core ID register
0x3C
32
read-write
n
0x0
0x0
PRODUCT_ID
Product ID field
0
32
FS_DIEPTXF1
FS_DIEPTXF1
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
0x104
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFO2 transmit RAM start address
0
16
FS_DIEPTXF2
FS_DIEPTXF2
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
0x108
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFO3 transmit RAM start address
0
16
FS_DIEPTXF3
FS_DIEPTXF3
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
0x10C
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFO4 transmit RAM start address
0
16
FS_GAHBCFG
FS_GAHBCFG
OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
0x8
32
read-write
n
0x0
0x0
GINT
Global interrupt mask
0
1
PTXFELVL
Periodic TxFIFO empty level
8
1
TXFELVL
TxFIFO empty level
7
1
FS_GCCFG
FS_GCCFG
OTG_FS general core configuration register (OTG_FS_GCCFG)
0x38
32
read-write
n
0x0
0x0
PWRDWN
Power down
16
1
SOFOUTEN
SOF output enable
20
1
VBUSASEN
Enable the VBUS sensing device
18
1
VBUSBSEN
Enable the VBUS sensing device
19
1
FS_GINTMSK
FS_GINTMSK
OTG_FS interrupt mask register (OTG_FS_GINTMSK)
0x18
32
read-write
n
0x0
0x0
CIDSCHGM
Connector ID status change mask
28
1
read-write
DISCINT
Disconnect detected interrupt mask
29
1
read-write
ENUMDNEM
Enumeration done mask
13
1
read-write
EOPFM
End of periodic frame interrupt mask
15
1
read-write
EPMISM
Endpoint mismatch interrupt mask
17
1
read-write
ESUSPM
Early suspend mask
10
1
read-write
GINAKEFFM
Global non-periodic IN NAK effective mask
6
1
read-write
GONAKEFFM
Global OUT NAK effective mask
7
1
read-write
HCIM
Host channels interrupt mask
25
1
read-write
IEPINT
IN endpoints interrupt mask
18
1
read-write
IISOIXFRM
Incomplete isochronous IN transfer mask
20
1
read-write
IPXFRM_IISOOXFRM
Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
21
1
read-write
ISOODRPM
Isochronous OUT packet dropped interrupt mask
14
1
read-write
MMISM
Mode mismatch interrupt mask
1
1
read-write
NPTXFEM
Non-periodic TxFIFO empty mask
5
1
read-write
OEPINT
OUT endpoints interrupt mask
19
1
read-write
OTGINT
OTG interrupt mask
2
1
read-write
PRTIM
Host port interrupt mask
24
1
read-only
PTXFEM
Periodic TxFIFO empty mask
26
1
read-write
RXFLVLM
Receive FIFO non-empty mask
4
1
read-write
SOFM
Start of frame mask
3
1
read-write
SRQIM
Session request/new session detected interrupt mask
30
1
read-write
USBRST
USB reset mask
12
1
read-write
USBSUSPM
USB suspend mask
11
1
read-write
WUIM
Resume/remote wakeup detected interrupt mask
31
1
read-write
FS_GINTSTS
FS_GINTSTS
OTG_FS core interrupt register (OTG_FS_GINTSTS)
0x14
32
read-write
n
0x0
0x0
CIDSCHG
Connector ID status change
28
1
read-write
CMOD
Current mode of operation
0
1
read-only
DISCINT
Disconnect detected interrupt
29
1
read-write
ENUMDNE
Enumeration done
13
1
read-write
EOPF
End of periodic frame interrupt
15
1
read-write
ESUSP
Early suspend
10
1
read-write
GINAKEFF
Global IN non-periodic NAK effective
6
1
read-only
GOUTNAKEFF
Global OUT NAK effective
7
1
read-only
HCINT
Host channels interrupt
25
1
read-only
HPRTINT
Host port interrupt
24
1
read-only
IEPINT
IN endpoint interrupt
18
1
read-only
IISOIXFR
Incomplete isochronous IN transfer
20
1
read-write
IPXFR_INCOMPISOOUT
Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
21
1
read-write
ISOODRP
Isochronous OUT packet dropped interrupt
14
1
read-write
MMIS
Mode mismatch interrupt
1
1
read-write
NPTXFE
Non-periodic TxFIFO empty
5
1
read-only
OEPINT
OUT endpoint interrupt
19
1
read-only
OTGINT
OTG interrupt
2
1
read-only
PTXFE
Periodic TxFIFO empty
26
1
read-only
RXFLVL
RxFIFO non-empty
4
1
read-only
SOF
Start of frame
3
1
read-write
SRQINT
Session request/new session detected interrupt
30
1
read-write
USBRST
USB reset
12
1
read-write
USBSUSP
USB suspend
11
1
read-write
WKUPINT
Resume/remote wakeup detected interrupt
31
1
read-write
FS_GNPTXFSIZ_Device
FS_GNPTXFSIZ_Device
OTG_FS non-periodic transmit FIFO size register (Device mode)
0x28
32
read-write
n
0x0
0x0
TX0FD
Endpoint 0 TxFIFO depth
16
16
TX0FSA
Endpoint 0 transmit RAM start address
0
16
FS_GNPTXFSIZ_Host
FS_GNPTXFSIZ_Host
OTG_FS non-periodic transmit FIFO size register (Host mode)
FS_GNPTXFSIZ_Device
0x28
32
read-write
n
0x0
0x0
NPTXFD
Non-periodic TxFIFO depth
16
16
NPTXFSA
Non-periodic transmit RAM start address
0
16
FS_GNPTXSTS
FS_GNPTXSTS
OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
0x2C
32
read-only
n
0x0
0x0
NPTQXSAV
Non-periodic transmit request queue space available
16
8
NPTXFSAV
Non-periodic TxFIFO space available
0
16
NPTXQTOP
Top of the non-periodic transmit request queue
24
7
FS_GOTGCTL
FS_GOTGCTL
OTG_FS control and status register (OTG_FS_GOTGCTL)
0x0
32
read-write
n
0x0
0x0
ASVLD
A-session valid
18
1
read-only
BSVLD
B-session valid
19
1
read-only
CIDSTS
Connector ID status
16
1
read-only
DBCT
Long/short debounce time
17
1
read-only
DHNPEN
Device HNP enabled
11
1
read-write
HNGSCS
Host negotiation success
8
1
read-only
HNPRQ
HNP request
9
1
read-write
HSHNPEN
Host set HNP enable
10
1
read-write
SRQ
Session request
1
1
read-write
SRQSCS
Session request success
0
1
read-only
FS_GOTGINT
FS_GOTGINT
OTG_FS interrupt register (OTG_FS_GOTGINT)
0x4
32
read-write
n
0x0
0x0
ADTOCHG
A-device timeout change
18
1
DBCDNE
Debounce done
19
1
HNGDET
Host negotiation detected
17
1
HNSSCHG
Host negotiation success status change
9
1
SEDET
Session end detected
2
1
SRSSCHG
Session request success status change
8
1
FS_GRSTCTL
FS_GRSTCTL
OTG_FS reset register (OTG_FS_GRSTCTL)
0x10
32
read-write
n
0x0
0x0
AHBIDL
AHB master idle
31
1
read-only
CSRST
Core soft reset
0
1
read-write
FCRST
Host frame counter reset
2
1
read-write
HSRST
HCLK soft reset
1
1
read-write
RXFFLSH
RxFIFO flush
4
1
read-write
TXFFLSH
TxFIFO flush
5
1
read-write
TXFNUM
TxFIFO number
6
5
read-write
FS_GRXFSIZ
FS_GRXFSIZ
OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
0x24
32
read-write
n
0x0
0x0
RXFD
RxFIFO depth
0
16
FS_GRXSTSR_Device
FS_GRXSTSR_Device
OTG_FS Receive status debug read(Device mode)
0x1C
32
read-only
n
0x0
0x0
BCNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
FRMNUM
Frame number
21
4
PKTSTS
Packet status
17
4
FS_GRXSTSR_Host
FS_GRXSTSR_Host
OTG_FS Receive status debug read(Host mode)
FS_GRXSTSR_Device
0x1C
32
read-only
n
0x0
0x0
BCNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
FRMNUM
Frame number
21
4
PKTSTS
Packet status
17
4
FS_GUSBCFG
FS_GUSBCFG
OTG_FS USB configuration register (OTG_FS_GUSBCFG)
0xC
32
read-write
n
0x0
0x0
CTXPKT
Corrupt Tx packet
31
1
read-write
FDMOD
Force device mode
30
1
read-write
FHMOD
Force host mode
29
1
read-write
HNPCAP
HNP-capable
9
1
read-write
PHYSEL
Full Speed serial transceiver select
6
1
write-only
SRPCAP
SRP-capable
8
1
read-write
TOCAL
FS timeout calibration
0
3
read-write
TRDT
USB turnaround time
10
4
read-write
FS_HPTXFSIZ
FS_HPTXFSIZ
OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
0x100
32
read-write
n
0x0
0x0
PTXFSIZ
Host periodic TxFIFO depth
16
16
PTXSA
Host periodic TxFIFO start address
0
16
OTG_FS_HOST
USB on the go full speed
USB_OTG_FS
0x0
0x0
0x400
registers
n
FS_HCCHAR0
FS_HCCHAR0
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
0x100
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR1
FS_HCCHAR1
OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
0x120
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR2
FS_HCCHAR2
OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
0x140
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR3
FS_HCCHAR3
OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
0x160
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR4
FS_HCCHAR4
OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
0x180
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR5
FS_HCCHAR5
OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
0x1A0
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR6
FS_HCCHAR6
OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
0x1C0
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR7
FS_HCCHAR7
OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
0x1E0
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCFG
FS_HCFG
OTG_FS host configuration register (OTG_FS_HCFG)
0x0
32
read-write
n
0x0
0x0
FSLSPCS
FS/LS PHY clock select
0
2
read-write
FSLSS
FS- and LS-only support
2
1
read-only
FS_HCINT0
FS_HCINT0
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
0x108
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT1
FS_HCINT1
OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
0x128
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT2
FS_HCINT2
OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
0x148
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT3
FS_HCINT3
OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
0x168
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT4
FS_HCINT4
OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
0x188
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT5
FS_HCINT5
OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
0x1A8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT6
FS_HCINT6
OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
0x1C8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT7
FS_HCINT7
OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
0x1E8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINTMSK0
FS_HCINTMSK0
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
0x10C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK1
FS_HCINTMSK1
OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
0x12C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK2
FS_HCINTMSK2
OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
0x14C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK3
FS_HCINTMSK3
OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
0x16C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK4
FS_HCINTMSK4
OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
0x18C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK5
FS_HCINTMSK5
OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
0x1AC
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK6
FS_HCINTMSK6
OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
0x1CC
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK7
FS_HCINTMSK7
OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
0x1EC
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCTSIZ0
FS_HCTSIZ0
OTG_FS host channel-0 transfer size register
0x110
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ1
FS_HCTSIZ1
OTG_FS host channel-1 transfer size register
0x130
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ2
FS_HCTSIZ2
OTG_FS host channel-2 transfer size register
0x150
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ3
FS_HCTSIZ3
OTG_FS host channel-3 transfer size register
0x170
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ4
FS_HCTSIZ4
OTG_FS host channel-x transfer size register
0x190
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ5
FS_HCTSIZ5
OTG_FS host channel-5 transfer size register
0x1B0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ6
FS_HCTSIZ6
OTG_FS host channel-6 transfer size register
0x1D0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ7
FS_HCTSIZ7
OTG_FS host channel-7 transfer size register
0x1F0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HFNUM
FS_HFNUM
OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
0x8
32
read-only
n
0x0
0x0
FRNUM
Frame number
0
16
FTREM
Frame time remaining
16
16
FS_HPRT
FS_HPRT
OTG_FS host port control and status register (OTG_FS_HPRT)
0x40
32
read-write
n
0x0
0x0
PCDET
Port connect detected
1
1
read-write
PCSTS
Port connect status
0
1
read-only
PENA
Port enable
2
1
read-write
PENCHNG
Port enable/disable change
3
1
read-write
PLSTS
Port line status
10
2
read-only
POCA
Port overcurrent active
4
1
read-only
POCCHNG
Port overcurrent change
5
1
read-write
PPWR
Port power
12
1
read-write
PRES
Port resume
6
1
read-write
PRST
Port reset
8
1
read-write
PSPD
Port speed
17
2
read-only
PSUSP
Port suspend
7
1
read-write
PTCTL
Port test control
13
4
read-write
FS_HPTXSTS
FS_HPTXSTS
OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
0x10
32
read-write
n
0x0
0x0
PTXFSAVL
Periodic transmit data FIFO space available
0
16
read-write
PTXQSAV
Periodic transmit request queue space available
16
8
read-only
PTXQTOP
Top of the periodic transmit request queue
24
8
read-only
HAINT
HAINT
OTG_FS Host all channels interrupt register
0x14
32
read-only
n
0x0
0x0
HAINT
Channel interrupts
0
16
HAINTMSK
HAINTMSK
OTG_FS host all channels interrupt mask register
0x18
32
read-write
n
0x0
0x0
HAINTM
Channel interrupt mask
0
16
HFIR
HFIR
OTG_FS Host frame interval register
0x4
32
read-write
n
0x0
0x0
FRIVL
Frame interval
0
16
OTG_FS_PWRCLK
USB on the go full speed
USB_OTG_FS
0x0
0x0
0x400
registers
n
FS_PCGCCTL
FS_PCGCCTL
OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)
0x0
32
read-write
n
0x0
0x0
GATEHCLK
Gate HCLK
1
1
PHYSUSP
PHY Suspended
4
1
STPPCLK
Stop PHY clock
0
1
OTG_HS_DEVICE
USB on the go high speed
USB_OTG_HS
0x0
0x0
0x400
registers
n
OTG_HS_DAINT
OTG_HS_DAINT
OTG_HS device all endpoints interrupt register
0x18
32
read-only
n
0x0
0x0
IEPINT
IN endpoint interrupt bits
0
16
OEPINT
OUT endpoint interrupt bits
16
16
OTG_HS_DAINTMSK
OTG_HS_DAINTMSK
OTG_HS all endpoints interrupt mask register
0x1C
32
read-write
n
0x0
0x0
IEPM
IN EP interrupt mask bits
0
16
OEPM
OUT EP interrupt mask bits
16
16
OTG_HS_DCFG
OTG_HS_DCFG
OTG_HS device configuration register
0x0
32
read-write
n
0x0
0x0
DAD
Device address
4
7
DSPD
Device speed
0
2
NZLSOHSK
Nonzero-length status OUT handshake
2
1
PERSCHIVL
Periodic scheduling interval
24
2
PFIVL
Periodic (micro)frame interval
11
2
OTG_HS_DCTL
OTG_HS_DCTL
OTG_HS device control register
0x4
32
read-write
n
0x0
0x0
CGINAK
Clear global IN NAK
8
1
write-only
CGONAK
Clear global OUT NAK
10
1
write-only
GINSTS
Global IN NAK status
2
1
read-only
GONSTS
Global OUT NAK status
3
1
read-only
POPRGDNE
Power-on programming done
11
1
read-write
RWUSIG
Remote wakeup signaling
0
1
read-write
SDIS
Soft disconnect
1
1
read-write
SGINAK
Set global IN NAK
7
1
write-only
SGONAK
Set global OUT NAK
9
1
write-only
TCTL
Test control
4
3
read-write
OTG_HS_DEACHINT
OTG_HS_DEACHINT
OTG_HS device each endpoint interrupt register
0x38
32
read-write
n
0x0
0x0
IEP1INT
IN endpoint 1interrupt bit
1
1
OEP1INT
OUT endpoint 1 interrupt bit
17
1
OTG_HS_DEACHINTMSK
OTG_HS_DEACHINTMSK
OTG_HS device each endpoint interrupt register mask
0x3C
32
read-write
n
0x0
0x0
IEP1INTM
IN Endpoint 1 interrupt mask bit
1
1
OEP1INTM
OUT Endpoint 1 interrupt mask bit
17
1
OTG_HS_DIEPCTL0
OTG_HS_DIEPCTL0
OTG device endpoint-0 control register
0x100
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPCTL1
OTG_HS_DIEPCTL1
OTG device endpoint-1 control register
0x120
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPCTL2
OTG_HS_DIEPCTL2
OTG device endpoint-2 control register
0x140
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPCTL3
OTG_HS_DIEPCTL3
OTG device endpoint-3 control register
0x160
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPCTL4
OTG_HS_DIEPCTL4
OTG device endpoint-4 control register
0x180
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPCTL5
OTG_HS_DIEPCTL5
OTG device endpoint-5 control register
0x1A0
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPCTL6
OTG_HS_DIEPCTL6
OTG device endpoint-6 control register
0x1C0
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPCTL7
OTG_HS_DIEPCTL7
OTG device endpoint-7 control register
0x1E0
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even/odd frame
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SNAK
Set NAK
27
1
write-only
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DIEPDMA1
OTG_HS_DIEPDMA1
OTG_HS device endpoint-1 DMA address register
0x114
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_DIEPDMA2
OTG_HS_DIEPDMA2
OTG_HS device endpoint-2 DMA address register
0x134
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_DIEPDMA3
OTG_HS_DIEPDMA3
OTG_HS device endpoint-3 DMA address register
0x154
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_DIEPDMA4
OTG_HS_DIEPDMA4
OTG_HS device endpoint-4 DMA address register
0x174
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_DIEPDMA5
OTG_HS_DIEPDMA5
OTG_HS device endpoint-5 DMA address register
0x194
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_DIEPEACHMSK1
OTG_HS_DIEPEACHMSK1
OTG_HS device each in endpoint-1 interrupt register
0x40
32
read-write
n
0x0
0x0
BIM
BNA interrupt mask
9
1
EPDM
Endpoint disabled interrupt mask
1
1
INEPNEM
IN endpoint NAK effective mask
6
1
INEPNMM
IN token received with EP mismatch mask
5
1
ITTXFEMSK
IN token received when TxFIFO empty mask
4
1
NAKM
NAK interrupt mask
13
1
TOM
Timeout condition mask (nonisochronous endpoints)
3
1
TXFURM
FIFO underrun mask
8
1
XFRCM
Transfer completed interrupt mask
0
1
OTG_HS_DIEPEMPMSK
OTG_HS_DIEPEMPMSK
OTG_HS device IN endpoint FIFO empty interrupt mask register
0x34
32
read-write
n
0x0
0x0
INEPTXFEM
IN EP Tx FIFO empty interrupt mask bits
0
16
OTG_HS_DIEPINT0
OTG_HS_DIEPINT0
OTG device endpoint-0 interrupt register
0x108
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPINT1
OTG_HS_DIEPINT1
OTG device endpoint-1 interrupt register
0x128
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPINT2
OTG_HS_DIEPINT2
OTG device endpoint-2 interrupt register
0x148
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPINT3
OTG_HS_DIEPINT3
OTG device endpoint-3 interrupt register
0x168
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPINT4
OTG_HS_DIEPINT4
OTG device endpoint-4 interrupt register
0x188
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPINT5
OTG_HS_DIEPINT5
OTG device endpoint-5 interrupt register
0x1A8
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPINT6
OTG_HS_DIEPINT6
OTG device endpoint-6 interrupt register
0x1C8
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPINT7
OTG_HS_DIEPINT7
OTG device endpoint-7 interrupt register
0x1E8
32
read-write
n
0x0
0x0
BERR
Babble error interrupt
12
1
read-write
BNA
Buffer not available interrupt
9
1
read-write
EPDISD
Endpoint disabled interrupt
1
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
ITTXFE
IN token received when TxFIFO is empty
4
1
read-write
NAK
NAK interrupt
13
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
TOC
Timeout condition
3
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
XFRC
Transfer completed interrupt
0
1
read-write
OTG_HS_DIEPMSK
OTG_HS_DIEPMSK
OTG_HS device IN endpoint common interrupt mask register
0x10
32
read-write
n
0x0
0x0
BIM
BNA interrupt mask
9
1
EPDM
Endpoint disabled interrupt mask
1
1
INEPNEM
IN endpoint NAK effective mask
6
1
INEPNMM
IN token received with EP mismatch mask
5
1
ITTXFEMSK
IN token received when TxFIFO empty mask
4
1
TOM
Timeout condition mask (nonisochronous endpoints)
3
1
TXFURM
FIFO underrun mask
8
1
XFRCM
Transfer completed interrupt mask
0
1
OTG_HS_DIEPTSIZ0
OTG_HS_DIEPTSIZ0
OTG_HS device IN endpoint 0 transfer size register
0x110
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
2
XFRSIZ
Transfer size
0
7
OTG_HS_DIEPTSIZ1
OTG_HS_DIEPTSIZ1
OTG_HS device endpoint transfer size register
0x130
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_DIEPTSIZ2
OTG_HS_DIEPTSIZ2
OTG_HS device endpoint transfer size register
0x150
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_DIEPTSIZ3
OTG_HS_DIEPTSIZ3
OTG_HS device endpoint transfer size register
0x170
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_DIEPTSIZ4
OTG_HS_DIEPTSIZ4
OTG_HS device endpoint transfer size register
0x190
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_DIEPTSIZ5
OTG_HS_DIEPTSIZ5
OTG_HS device endpoint transfer size register
0x1B0
32
read-write
n
0x0
0x0
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_DOEPCTL0
OTG_HS_DOEPCTL0
OTG_HS device control OUT endpoint 0 control register
0x300
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EPDIS
Endpoint disable
30
1
read-only
EPENA
Endpoint enable
31
1
write-only
EPTYP
Endpoint type
18
2
read-only
MPSIZ
Maximum packet size
0
2
read-only
NAKSTS
NAK status
17
1
read-only
SNAK
Set NAK
27
1
write-only
SNPM
Snoop mode
20
1
read-write
Stall
STALL handshake
21
1
read-write
USBAEP
USB active endpoint
15
1
read-only
OTG_HS_DOEPCTL1
OTG_HS_DOEPCTL1
OTG device endpoint-1 control register
0x320
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even odd frame/Endpoint data PID
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID/Set even frame
28
1
write-only
SNAK
Set NAK
27
1
write-only
SNPM
Snoop mode
20
1
read-write
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DOEPCTL2
OTG_HS_DOEPCTL2
OTG device endpoint-2 control register
0x340
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even odd frame/Endpoint data PID
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID/Set even frame
28
1
write-only
SNAK
Set NAK
27
1
write-only
SNPM
Snoop mode
20
1
read-write
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DOEPCTL3
OTG_HS_DOEPCTL3
OTG device endpoint-3 control register
0x360
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EONUM_DPID
Even odd frame/Endpoint data PID
16
1
read-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
EPTYP
Endpoint type
18
2
read-write
MPSIZ
Maximum packet size
0
11
read-write
NAKSTS
NAK status
17
1
read-only
SD0PID_SEVNFRM
Set DATA0 PID/Set even frame
28
1
write-only
SNAK
Set NAK
27
1
write-only
SNPM
Snoop mode
20
1
read-write
SODDFRM
Set odd frame
29
1
write-only
Stall
STALL handshake
21
1
read-write
USBAEP
USB active endpoint
15
1
read-write
OTG_HS_DOEPEACHMSK1
OTG_HS_DOEPEACHMSK1
OTG_HS device each OUT endpoint-1 interrupt register
0x80
32
read-write
n
0x0
0x0
BERRM
Bubble error interrupt mask
12
1
BIM
BNA interrupt mask
9
1
EPDM
Endpoint disabled interrupt mask
1
1
INEPNEM
IN endpoint NAK effective mask
6
1
INEPNMM
IN token received with EP mismatch mask
5
1
ITTXFEMSK
IN token received when TxFIFO empty mask
4
1
NAKM
NAK interrupt mask
13
1
NYETM
NYET interrupt mask
14
1
TOM
Timeout condition mask
3
1
TXFURM
OUT packet error mask
8
1
XFRCM
Transfer completed interrupt mask
0
1
OTG_HS_DOEPINT0
OTG_HS_DOEPINT0
OTG_HS device endpoint-0 interrupt register
0x308
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPINT1
OTG_HS_DOEPINT1
OTG_HS device endpoint-1 interrupt register
0x328
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPINT2
OTG_HS_DOEPINT2
OTG_HS device endpoint-2 interrupt register
0x348
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPINT3
OTG_HS_DOEPINT3
OTG_HS device endpoint-3 interrupt register
0x368
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPINT4
OTG_HS_DOEPINT4
OTG_HS device endpoint-4 interrupt register
0x388
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPINT5
OTG_HS_DOEPINT5
OTG_HS device endpoint-5 interrupt register
0x3A8
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPINT6
OTG_HS_DOEPINT6
OTG_HS device endpoint-6 interrupt register
0x3C8
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPINT7
OTG_HS_DOEPINT7
OTG_HS device endpoint-7 interrupt register
0x3E8
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received
6
1
EPDISD
Endpoint disabled interrupt
1
1
NYET
NYET interrupt
14
1
OTEPDIS
OUT token received when endpoint disabled
4
1
STUP
SETUP phase done
3
1
XFRC
Transfer completed interrupt
0
1
OTG_HS_DOEPMSK
OTG_HS_DOEPMSK
OTG_HS device OUT endpoint common interrupt mask register
0x14
32
read-write
n
0x0
0x0
B2BSTUP
Back-to-back SETUP packets received mask
6
1
BOIM
BNA interrupt mask
9
1
EPDM
Endpoint disabled interrupt mask
1
1
OPEM
OUT packet error mask
8
1
OTEPDM
OUT token received when endpoint disabled mask
4
1
STUPM
SETUP phase done mask
3
1
XFRCM
Transfer completed interrupt mask
0
1
OTG_HS_DOEPTSIZ0
OTG_HS_DOEPTSIZ0
OTG_HS device endpoint-1 transfer size register
0x310
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
1
STUPCNT
SETUP packet count
29
2
XFRSIZ
Transfer size
0
7
OTG_HS_DOEPTSIZ1
OTG_HS_DOEPTSIZ1
OTG_HS device endpoint-2 transfer size register
0x330
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
OTG_HS_DOEPTSIZ2
OTG_HS_DOEPTSIZ2
OTG_HS device endpoint-3 transfer size register
0x350
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
OTG_HS_DOEPTSIZ3
OTG_HS_DOEPTSIZ3
OTG_HS device endpoint-4 transfer size register
0x370
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
OTG_HS_DOEPTSIZ4
OTG_HS_DOEPTSIZ4
OTG_HS device endpoint-5 transfer size register
0x390
32
read-write
n
0x0
0x0
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
OTG_HS_DSTS
OTG_HS_DSTS
OTG_HS device status register
0x8
32
read-only
n
0x0
0x0
EERR
Erratic error
3
1
ENUMSPD
Enumerated speed
1
2
FNSOF
Frame number of the received SOF
8
14
SUSPSTS
Suspend status
0
1
OTG_HS_DTHRCTL
OTG_HS_DTHRCTL
OTG_HS Device threshold control register
0x30
32
read-write
n
0x0
0x0
ARPEN
Arbiter parking enable
27
1
ISOTHREN
ISO IN endpoint threshold enable
1
1
NONISOTHREN
Nonisochronous IN endpoints threshold enable
0
1
RXTHREN
Receive threshold enable
16
1
RXTHRLEN
Receive threshold length
17
9
TXTHRLEN
Transmit threshold length
2
9
OTG_HS_DTXFSTS0
OTG_HS_DTXFSTS0
OTG_HS device IN endpoint transmit FIFO status register
0x118
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space avail
0
16
OTG_HS_DTXFSTS1
OTG_HS_DTXFSTS1
OTG_HS device IN endpoint transmit FIFO status register
0x138
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space avail
0
16
OTG_HS_DTXFSTS2
OTG_HS_DTXFSTS2
OTG_HS device IN endpoint transmit FIFO status register
0x158
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space avail
0
16
OTG_HS_DTXFSTS3
OTG_HS_DTXFSTS3
OTG_HS device IN endpoint transmit FIFO status register
0x178
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space avail
0
16
OTG_HS_DTXFSTS4
OTG_HS_DTXFSTS4
OTG_HS device IN endpoint transmit FIFO status register
0x198
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space avail
0
16
OTG_HS_DTXFSTS5
OTG_HS_DTXFSTS5
OTG_HS device IN endpoint transmit FIFO status register
0x1B8
32
read-only
n
0x0
0x0
INEPTFSAV
IN endpoint TxFIFO space avail
0
16
OTG_HS_DVBUSDIS
OTG_HS_DVBUSDIS
OTG_HS device VBUS discharge time register
0x28
32
read-write
n
0x0
0x0
VBUSDT
Device VBUS discharge time
0
16
OTG_HS_DVBUSPULSE
OTG_HS_DVBUSPULSE
OTG_HS device VBUS pulsing time register
0x2C
32
read-write
n
0x0
0x0
DVBUSP
Device VBUS pulsing time
0
12
OTG_HS_GLOBAL
USB on the go high speed
USB_OTG_HS
0x0
0x0
0x400
registers
n
OTG_HS_EP1_OUT
USB On The Go HS End Point 1 Out global interrupt
74
OTG_HS_EP1_IN
USB On The Go HS End Point 1 In global interrupt
75
OTG_HS_WKUP
USB On The Go HS Wakeup through EXTI interrupt
76
OTG_HS
USB On The Go HS global interrupt
77
OTG_HS_CID
OTG_HS_CID
OTG_HS core ID register
0x3C
32
read-write
n
0x0
0x0
PRODUCT_ID
Product ID field
0
32
OTG_HS_DIEPTXF1
OTG_HS_DIEPTXF1
OTG_HS device IN endpoint transmit FIFO size register
0x104
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFOx transmit RAM start address
0
16
OTG_HS_DIEPTXF2
OTG_HS_DIEPTXF2
OTG_HS device IN endpoint transmit FIFO size register
0x108
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFOx transmit RAM start address
0
16
OTG_HS_DIEPTXF3
OTG_HS_DIEPTXF3
OTG_HS device IN endpoint transmit FIFO size register
0x11C
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFOx transmit RAM start address
0
16
OTG_HS_DIEPTXF4
OTG_HS_DIEPTXF4
OTG_HS device IN endpoint transmit FIFO size register
0x120
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFOx transmit RAM start address
0
16
OTG_HS_DIEPTXF5
OTG_HS_DIEPTXF5
OTG_HS device IN endpoint transmit FIFO size register
0x124
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFOx transmit RAM start address
0
16
OTG_HS_DIEPTXF6
OTG_HS_DIEPTXF6
OTG_HS device IN endpoint transmit FIFO size register
0x128
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFOx transmit RAM start address
0
16
OTG_HS_DIEPTXF7
OTG_HS_DIEPTXF7
OTG_HS device IN endpoint transmit FIFO size register
0x12C
32
read-write
n
0x0
0x0
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFOx transmit RAM start address
0
16
OTG_HS_GAHBCFG
OTG_HS_GAHBCFG
OTG_HS AHB configuration register
0x8
32
read-write
n
0x0
0x0
DMAEN
DMA enable
5
1
GINT
Global interrupt mask
0
1
HBSTLEN
Burst length/type
1
4
PTXFELVL
Periodic TxFIFO empty level
8
1
TXFELVL
TxFIFO empty level
7
1
OTG_HS_GCCFG
OTG_HS_GCCFG
OTG_HS general core configuration register
0x38
32
read-write
n
0x0
0x0
I2CPADEN
Enable I2C bus connection for the external I2C PHY interface
17
1
NOVBUSSENS
VBUS sensing disable option
21
1
PWRDWN
Power down
16
1
SOFOUTEN
SOF output enable
20
1
VBUSASEN
Enable the VBUS sensing device
18
1
VBUSBSEN
Enable the VBUS sensing device
19
1
OTG_HS_GINTMSK
OTG_HS_GINTMSK
OTG_HS interrupt mask register
0x18
32
read-write
n
0x0
0x0
CIDSCHGM
Connector ID status change mask
28
1
read-write
DISCINT
Disconnect detected interrupt mask
29
1
read-write
ENUMDNEM
Enumeration done mask
13
1
read-write
EOPFM
End of periodic frame interrupt mask
15
1
read-write
EPMISM
Endpoint mismatch interrupt mask
17
1
read-write
ESUSPM
Early suspend mask
10
1
read-write
FSUSPM
Data fetch suspended mask
22
1
read-write
GINAKEFFM
Global nonperiodic IN NAK effective mask
6
1
read-write
GONAKEFFM
Global OUT NAK effective mask
7
1
read-write
HCIM
Host channels interrupt mask
25
1
read-write
IEPINT
IN endpoints interrupt mask
18
1
read-write
IISOIXFRM
Incomplete isochronous IN transfer mask
20
1
read-write
ISOODRPM
Isochronous OUT packet dropped interrupt mask
14
1
read-write
MMISM
Mode mismatch interrupt mask
1
1
read-write
NPTXFEM
Nonperiodic TxFIFO empty mask
5
1
read-write
OEPINT
OUT endpoints interrupt mask
19
1
read-write
OTGINT
OTG interrupt mask
2
1
read-write
PRTIM
Host port interrupt mask
24
1
read-only
PTXFEM
Periodic TxFIFO empty mask
26
1
read-write
PXFRM_IISOOXFRM
Incomplete periodic transfer mask
21
1
read-write
RXFLVLM
Receive FIFO nonempty mask
4
1
read-write
SOFM
Start of frame mask
3
1
read-write
SRQIM
Session request/new session detected interrupt mask
30
1
read-write
USBRST
USB reset mask
12
1
read-write
USBSUSPM
USB suspend mask
11
1
read-write
WUIM
Resume/remote wakeup detected interrupt mask
31
1
read-write
OTG_HS_GINTSTS
OTG_HS_GINTSTS
OTG_HS core interrupt register
0x14
32
read-write
n
0x0
0x0
BOUTNAKEFF
Global OUT NAK effective
7
1
read-only
CIDSCHG
Connector ID status change
28
1
read-write
CMOD
Current mode of operation
0
1
read-only
DATAFSUSP
Data fetch suspended
22
1
read-write
DISCINT
Disconnect detected interrupt
29
1
read-write
ENUMDNE
Enumeration done
13
1
read-write
EOPF
End of periodic frame interrupt
15
1
read-write
ESUSP
Early suspend
10
1
read-write
GINAKEFF
Global IN nonperiodic NAK effective
6
1
read-only
HCINT
Host channels interrupt
25
1
read-only
HPRTINT
Host port interrupt
24
1
read-only
IEPINT
IN endpoint interrupt
18
1
read-only
IISOIXFR
Incomplete isochronous IN transfer
20
1
read-write
ISOODRP
Isochronous OUT packet dropped interrupt
14
1
read-write
MMIS
Mode mismatch interrupt
1
1
read-write
NPTXFE
Nonperiodic TxFIFO empty
5
1
read-only
OEPINT
OUT endpoint interrupt
19
1
read-only
OTGINT
OTG interrupt
2
1
read-only
PTXFE
Periodic TxFIFO empty
26
1
read-only
PXFR_INCOMPISOOUT
Incomplete periodic transfer
21
1
read-write
RXFLVL
RxFIFO nonempty
4
1
read-only
SOF
Start of frame
3
1
read-write
SRQINT
Session request/new session detected interrupt
30
1
read-write
USBRST
USB reset
12
1
read-write
USBSUSP
USB suspend
11
1
read-write
WKUINT
Resume/remote wakeup detected interrupt
31
1
read-write
OTG_HS_GNPTXFSIZ_Host
OTG_HS_GNPTXFSIZ_Host
OTG_HS nonperiodic transmit FIFO size register (host mode)
0x28
32
read-write
n
0x0
0x0
NPTXFD
Nonperiodic TxFIFO depth
16
16
NPTXFSA
Nonperiodic transmit RAM start address
0
16
OTG_HS_GNPTXSTS
OTG_HS_GNPTXSTS
OTG_HS nonperiodic transmit FIFO/queue status register
0x2C
32
read-only
n
0x0
0x0
NPTQXSAV
Nonperiodic transmit request queue space available
16
8
NPTXFSAV
Nonperiodic TxFIFO space available
0
16
NPTXQTOP
Top of the nonperiodic transmit request queue
24
7
OTG_HS_GOTGCTL
OTG_HS_GOTGCTL
OTG_HS control and status register
0x0
32
read-write
n
0x0
0x0
ASVLD
A-session valid
18
1
read-only
BSVLD
B-session valid
19
1
read-only
CIDSTS
Connector ID status
16
1
read-only
DBCT
Long/short debounce time
17
1
read-only
DHNPEN
Device HNP enabled
11
1
read-write
HNGSCS
Host negotiation success
8
1
read-only
HNPRQ
HNP request
9
1
read-write
HSHNPEN
Host set HNP enable
10
1
read-write
SRQ
Session request
1
1
read-write
SRQSCS
Session request success
0
1
read-only
OTG_HS_GOTGINT
OTG_HS_GOTGINT
OTG_HS interrupt register
0x4
32
read-write
n
0x0
0x0
ADTOCHG
A-device timeout change
18
1
DBCDNE
Debounce done
19
1
HNGDET
Host negotiation detected
17
1
HNSSCHG
Host negotiation success status change
9
1
SEDET
Session end detected
2
1
SRSSCHG
Session request success status change
8
1
OTG_HS_GRSTCTL
OTG_HS_GRSTCTL
OTG_HS reset register
0x10
32
read-write
n
0x0
0x0
AHBIDL
AHB master idle
31
1
read-only
CSRST
Core soft reset
0
1
read-write
DMAREQ
DMA request signal
30
1
read-only
FCRST
Host frame counter reset
2
1
read-write
HSRST
HCLK soft reset
1
1
read-write
RXFFLSH
RxFIFO flush
4
1
read-write
TXFFLSH
TxFIFO flush
5
1
read-write
TXFNUM
TxFIFO number
6
5
read-write
OTG_HS_GRXFSIZ
OTG_HS_GRXFSIZ
OTG_HS Receive FIFO size register
0x24
32
read-write
n
0x0
0x0
RXFD
RxFIFO depth
0
16
OTG_HS_GRXSTSP_Host
OTG_HS_GRXSTSP_Host
OTG_HS status read and pop register (host mode)
0x20
32
read-only
n
0x0
0x0
BCNT
Byte count
4
11
CHNUM
Channel number
0
4
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
OTG_HS_GRXSTSP_Peripheral
OTG_HS_GRXSTSP_Peripheral
OTG_HS status read and pop register (peripheral mode)
OTG_HS_GRXSTSP_Host
0x20
32
read-only
n
0x0
0x0
BCNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
FRMNUM
Frame number
21
4
PKTSTS
Packet status
17
4
OTG_HS_GRXSTSR_Host
OTG_HS_GRXSTSR_Host
OTG_HS Receive status debug read register (host mode)
0x1C
32
read-only
n
0x0
0x0
BCNT
Byte count
4
11
CHNUM
Channel number
0
4
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
OTG_HS_GRXSTSR_Peripheral
OTG_HS_GRXSTSR_Peripheral
OTG_HS Receive status debug read register (peripheral mode mode)
OTG_HS_GRXSTSR_Host
0x1C
32
read-only
n
0x0
0x0
BCNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
FRMNUM
Frame number
21
4
PKTSTS
Packet status
17
4
OTG_HS_GUSBCFG
OTG_HS_GUSBCFG
OTG_HS USB configuration register
0xC
32
read-write
n
0x0
0x0
CTXPKT
Corrupt Tx packet
31
1
read-write
FDMOD
Forced peripheral mode
30
1
read-write
FHMOD
Forced host mode
29
1
read-write
HNPCAP
HNP-capable
9
1
read-write
PCCI
Indicator complement
23
1
read-write
PHYLPCS
PHY Low-power clock select
15
1
read-write
PHYSEL
USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
6
1
write-only
PTCI
Indicator pass through
24
1
read-write
SRPCAP
SRP-capable
8
1
read-write
TOCAL
FS timeout calibration
0
3
read-write
TRDT
USB turnaround time
10
4
read-write
TSDPS
TermSel DLine pulsing selection
22
1
read-write
ULPIAR
ULPI Auto-resume
18
1
read-write
ULPICSM
ULPI Clock SuspendM
19
1
read-write
ULPIEVBUSD
ULPI External VBUS Drive
20
1
read-write
ULPIEVBUSI
ULPI external VBUS indicator
21
1
read-write
ULPIFSLS
ULPI FS/LS select
17
1
read-write
ULPIIPD
ULPI interface protect disable
25
1
read-write
OTG_HS_HPTXFSIZ
OTG_HS_HPTXFSIZ
OTG_HS Host periodic transmit FIFO size register
0x100
32
read-write
n
0x0
0x0
PTXFD
Host periodic TxFIFO depth
16
16
PTXSA
Host periodic TxFIFO start address
0
16
OTG_HS_TX0FSIZ_Peripheral
OTG_HS_TX0FSIZ_Peripheral
Endpoint 0 transmit FIFO size (peripheral mode)
OTG_HS_GNPTXFSIZ_Host
0x28
32
read-write
n
0x0
0x0
TX0FD
Endpoint 0 TxFIFO depth
16
16
TX0FSA
Endpoint 0 transmit RAM start address
0
16
OTG_HS_HOST
USB on the go high speed
USB_OTG_HS
0x0
0x0
0x400
registers
n
OTG_HS_HAINT
OTG_HS_HAINT
OTG_HS Host all channels interrupt register
0x14
32
read-only
n
0x0
0x0
HAINT
Channel interrupts
0
16
OTG_HS_HAINTMSK
OTG_HS_HAINTMSK
OTG_HS host all channels interrupt mask register
0x18
32
read-write
n
0x0
0x0
HAINTM
Channel interrupt mask
0
16
OTG_HS_HCCHAR0
OTG_HS_HCCHAR0
OTG_HS host channel-0 characteristics register
0x100
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR1
OTG_HS_HCCHAR1
OTG_HS host channel-1 characteristics register
0x120
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR10
OTG_HS_HCCHAR10
OTG_HS host channel-10 characteristics register
0x240
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR11
OTG_HS_HCCHAR11
OTG_HS host channel-11 characteristics register
0x260
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR2
OTG_HS_HCCHAR2
OTG_HS host channel-2 characteristics register
0x140
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR3
OTG_HS_HCCHAR3
OTG_HS host channel-3 characteristics register
0x160
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR4
OTG_HS_HCCHAR4
OTG_HS host channel-4 characteristics register
0x180
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR5
OTG_HS_HCCHAR5
OTG_HS host channel-5 characteristics register
0x1A0
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR6
OTG_HS_HCCHAR6
OTG_HS host channel-6 characteristics register
0x1C0
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR7
OTG_HS_HCCHAR7
OTG_HS host channel-7 characteristics register
0x1E0
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR8
OTG_HS_HCCHAR8
OTG_HS host channel-8 characteristics register
0x200
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCCHAR9
OTG_HS_HCCHAR9
OTG_HS host channel-9 characteristics register
0x220
32
read-write
n
0x0
0x0
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MC
Multi Count (MC) / Error Count (EC)
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
OTG_HS_HCDMA0
OTG_HS_HCDMA0
OTG_HS host channel-0 DMA address register
0x114
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA1
OTG_HS_HCDMA1
OTG_HS host channel-1 DMA address register
0x134
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA10
OTG_HS_HCDMA10
OTG_HS host channel-10 DMA address register
0x254
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA11
OTG_HS_HCDMA11
OTG_HS host channel-11 DMA address register
0x274
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA2
OTG_HS_HCDMA2
OTG_HS host channel-2 DMA address register
0x154
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA3
OTG_HS_HCDMA3
OTG_HS host channel-3 DMA address register
0x174
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA4
OTG_HS_HCDMA4
OTG_HS host channel-4 DMA address register
0x194
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA5
OTG_HS_HCDMA5
OTG_HS host channel-5 DMA address register
0x1B4
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA6
OTG_HS_HCDMA6
OTG_HS host channel-6 DMA address register
0x1D4
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA7
OTG_HS_HCDMA7
OTG_HS host channel-7 DMA address register
0x1F4
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA8
OTG_HS_HCDMA8
OTG_HS host channel-8 DMA address register
0x214
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCDMA9
OTG_HS_HCDMA9
OTG_HS host channel-9 DMA address register
0x234
32
read-write
n
0x0
0x0
DMAADDR
DMA address
0
32
OTG_HS_HCFG
OTG_HS_HCFG
OTG_HS host configuration register
0x0
32
read-write
n
0x0
0x0
FSLSPCS
FS/LS PHY clock select
0
2
read-write
FSLSS
FS- and LS-only support
2
1
read-only
OTG_HS_HCINT0
OTG_HS_HCINT0
OTG_HS host channel-11 interrupt register
0x108
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT1
OTG_HS_HCINT1
OTG_HS host channel-1 interrupt register
0x128
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT10
OTG_HS_HCINT10
OTG_HS host channel-10 interrupt register
0x248
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT11
OTG_HS_HCINT11
OTG_HS host channel-11 interrupt register
0x268
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT2
OTG_HS_HCINT2
OTG_HS host channel-2 interrupt register
0x148
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT3
OTG_HS_HCINT3
OTG_HS host channel-3 interrupt register
0x168
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT4
OTG_HS_HCINT4
OTG_HS host channel-4 interrupt register
0x188
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT5
OTG_HS_HCINT5
OTG_HS host channel-5 interrupt register
0x1A8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT6
OTG_HS_HCINT6
OTG_HS host channel-6 interrupt register
0x1C8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT7
OTG_HS_HCINT7
OTG_HS host channel-7 interrupt register
0x1E8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT8
OTG_HS_HCINT8
OTG_HS host channel-8 interrupt register
0x208
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINT9
OTG_HS_HCINT9
OTG_HS host channel-9 interrupt register
0x228
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
AHBERR
AHB error
2
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
NYET
Response received interrupt
6
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
OTG_HS_HCINTMSK0
OTG_HS_HCINTMSK0
OTG_HS host channel-11 interrupt mask register
0x10C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK1
OTG_HS_HCINTMSK1
OTG_HS host channel-1 interrupt mask register
0x12C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK10
OTG_HS_HCINTMSK10
OTG_HS host channel-10 interrupt mask register
0x24C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK11
OTG_HS_HCINTMSK11
OTG_HS host channel-11 interrupt mask register
0x26C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK2
OTG_HS_HCINTMSK2
OTG_HS host channel-2 interrupt mask register
0x14C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK3
OTG_HS_HCINTMSK3
OTG_HS host channel-3 interrupt mask register
0x16C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK4
OTG_HS_HCINTMSK4
OTG_HS host channel-4 interrupt mask register
0x18C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK5
OTG_HS_HCINTMSK5
OTG_HS host channel-5 interrupt mask register
0x1AC
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK6
OTG_HS_HCINTMSK6
OTG_HS host channel-6 interrupt mask register
0x1CC
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK7
OTG_HS_HCINTMSK7
OTG_HS host channel-7 interrupt mask register
0x1EC
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK8
OTG_HS_HCINTMSK8
OTG_HS host channel-8 interrupt mask register
0x20C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCINTMSK9
OTG_HS_HCINTMSK9
OTG_HS host channel-9 interrupt mask register
0x22C
32
read-write
n
0x0
0x0
ACKM
ACK response received/transmitted interrupt mask
5
1
AHBERR
AHB error
2
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
OTG_HS_HCSPLT0
OTG_HS_HCSPLT0
OTG_HS host channel-0 split control register
0x104
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT1
OTG_HS_HCSPLT1
OTG_HS host channel-1 split control register
0x124
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT10
OTG_HS_HCSPLT10
OTG_HS host channel-10 split control register
0x244
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT11
OTG_HS_HCSPLT11
OTG_HS host channel-11 split control register
0x264
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT2
OTG_HS_HCSPLT2
OTG_HS host channel-2 split control register
0x144
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT3
OTG_HS_HCSPLT3
OTG_HS host channel-3 split control register
0x164
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT4
OTG_HS_HCSPLT4
OTG_HS host channel-4 split control register
0x184
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT5
OTG_HS_HCSPLT5
OTG_HS host channel-5 split control register
0x1A4
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT6
OTG_HS_HCSPLT6
OTG_HS host channel-6 split control register
0x1C4
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT7
OTG_HS_HCSPLT7
OTG_HS host channel-7 split control register
0x1E4
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT8
OTG_HS_HCSPLT8
OTG_HS host channel-8 split control register
0x204
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCSPLT9
OTG_HS_HCSPLT9
OTG_HS host channel-9 split control register
0x224
32
read-write
n
0x0
0x0
COMPLSPLT
Do complete split
16
1
HUBADDR
Hub address
7
7
PRTADDR
Port address
0
7
SPLITEN
Split enable
31
1
XACTPOS
XACTPOS
14
2
OTG_HS_HCTSIZ0
OTG_HS_HCTSIZ0
OTG_HS host channel-11 transfer size register
0x110
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ1
OTG_HS_HCTSIZ1
OTG_HS host channel-1 transfer size register
0x130
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ10
OTG_HS_HCTSIZ10
OTG_HS host channel-10 transfer size register
0x250
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ11
OTG_HS_HCTSIZ11
OTG_HS host channel-11 transfer size register
0x270
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ2
OTG_HS_HCTSIZ2
OTG_HS host channel-2 transfer size register
0x150
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ3
OTG_HS_HCTSIZ3
OTG_HS host channel-3 transfer size register
0x170
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ4
OTG_HS_HCTSIZ4
OTG_HS host channel-4 transfer size register
0x190
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ5
OTG_HS_HCTSIZ5
OTG_HS host channel-5 transfer size register
0x1B0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ6
OTG_HS_HCTSIZ6
OTG_HS host channel-6 transfer size register
0x1D0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ7
OTG_HS_HCTSIZ7
OTG_HS host channel-7 transfer size register
0x1F0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ8
OTG_HS_HCTSIZ8
OTG_HS host channel-8 transfer size register
0x210
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HCTSIZ9
OTG_HS_HCTSIZ9
OTG_HS host channel-9 transfer size register
0x230
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_HS_HFIR
OTG_HS_HFIR
OTG_HS Host frame interval register
0x4
32
read-write
n
0x0
0x0
FRIVL
Frame interval
0
16
OTG_HS_HFNUM
OTG_HS_HFNUM
OTG_HS host frame number/frame time remaining register
0x8
32
read-only
n
0x0
0x0
FRNUM
Frame number
0
16
FTREM
Frame time remaining
16
16
OTG_HS_HPRT
OTG_HS_HPRT
OTG_HS host port control and status register
0x40
32
read-write
n
0x0
0x0
PCDET
Port connect detected
1
1
read-write
PCSTS
Port connect status
0
1
read-only
PENA
Port enable
2
1
read-write
PENCHNG
Port enable/disable change
3
1
read-write
PLSTS
Port line status
10
2
read-only
POCA
Port overcurrent active
4
1
read-only
POCCHNG
Port overcurrent change
5
1
read-write
PPWR
Port power
12
1
read-write
PRES
Port resume
6
1
read-write
PRST
Port reset
8
1
read-write
PSPD
Port speed
17
2
read-only
PSUSP
Port suspend
7
1
read-write
PTCTL
Port test control
13
4
read-write
OTG_HS_HPTXSTS
OTG_HS_HPTXSTS
OTG_HS_Host periodic transmit FIFO/queue status register
0x10
32
read-write
n
0x0
0x0
PTXFSAVL
Periodic transmit data FIFO space available
0
16
read-write
PTXQSAV
Periodic transmit request queue space available
16
8
read-only
PTXQTOP
Top of the periodic transmit request queue
24
8
read-only
OTG_HS_PWRCLK
USB on the go high speed
USB_OTG_HS
0x0
0x0
0x3F200
registers
n
OTG_HS_PCGCR
OTG_HS_PCGCR
Power and clock gating control register
0x0
32
read-write
n
0x0
0x0
GATEHCLK
Gate HCLK
1
1
PHYSUSP
PHY suspended
4
1
STPPCLK
Stop PHY clock
0
1
PWR
Power control
PWR
0x0
0x0
0x400
registers
n
PVD
PVD through EXTI Line detection interrupt
1
CR
CR
power control register
0x0
32
read-write
n
0x0
0x0
ADCDC1
Main regulator low voltage in deepsleep mode
13
1
CSBF
Clear standby flag
3
1
CWUF
Clear wakeup flag
2
1
DBP
Disable backup domain write protection
8
1
FPDS
Flash power down in Stop mode
9
1
LPDS
Low-power deep sleep
0
1
LPLVDS
Low-Power Regulator Low Voltage in deepsleep
10
1
MRLVDS
Main regulator low voltage in deepsleep mode
11
1
ODEN
Over-drive enable
16
1
ODSWEN
Over-drive switching enabled
17
1
PDDS
Power down deepsleep
1
1
PLS
PVD level selection
5
3
PVDE
Power voltage detector enable
4
1
UDEN
Under-drive enable in stop mode
18
2
VOS
Regulator voltage scaling output selection
14
2
CSR
CSR
power control/status register
0x4
32
read-write
n
0x0
0x0
BRE
Backup regulator enable
9
1
read-write
BRR
Backup regulator ready
3
1
read-only
EWUP
Enable WKUP pin
8
1
read-write
ODRDY
Over-drive mode ready
16
1
read-only
ODSWRDY
Over-drive mode switching ready
17
1
read-only
PVDO
PVD output
2
1
read-only
SBF
Standby flag
1
1
read-only
UDRDY
Under-drive ready flag
18
2
read-write
VOSRDY
Regulator voltage scaling output selection ready bit
14
1
read-write
WUF
Wakeup flag
0
1
read-only
RCC
Reset and clock control
RCC
0x0
0x0
0x400
registers
n
RCC
RCC global interrupt
5
AHB1ENR
AHB1ENR
AHB1 peripheral clock register
0x30
32
read-write
n
0x0
0x0
BKPSRAMEN
Backup SRAM interface clock enable
18
1
CRCEN
CRC clock enable
12
1
DMA1EN
DMA1 clock enable
21
1
DMA2EN
DMA2 clock enable
22
1
ETHMACEN
Ethernet MAC clock enable
25
1
ETHMACPTPEN
Ethernet PTP clock enable
28
1
ETHMACRXEN
Ethernet Reception clock enable
27
1
ETHMACTXEN
Ethernet Transmission clock enable
26
1
GPIOAEN
IO port A clock enable
0
1
GPIOBEN
IO port B clock enable
1
1
GPIOCEN
IO port C clock enable
2
1
GPIODEN
IO port D clock enable
3
1
GPIOEEN
IO port E clock enable
4
1
GPIOFEN
IO port F clock enable
5
1
GPIOGEN
IO port G clock enable
6
1
GPIOHEN
IO port H clock enable
7
1
GPIOIEN
IO port I clock enable
8
1
OTGHSEN
USB OTG HS clock enable
29
1
OTGHSULPIEN
USB OTG HSULPI clock enable
30
1
AHB1LPENR
AHB1LPENR
AHB1 peripheral clock enable in low power mode register
0x50
32
read-write
n
0x0
0x0
BKPSRAMLPEN
Backup SRAM interface clock enable during Sleep mode
18
1
CRCLPEN
CRC clock enable during Sleep mode
12
1
DMA1LPEN
DMA1 clock enable during Sleep mode
21
1
DMA2LPEN
DMA2 clock enable during Sleep mode
22
1
ETHMACLPEN
Ethernet MAC clock enable during Sleep mode
25
1
ETHMACPTPLPEN
Ethernet PTP clock enable during Sleep mode
28
1
ETHMACRXLPEN
Ethernet reception clock enable during Sleep mode
27
1
ETHMACTXLPEN
Ethernet transmission clock enable during Sleep mode
26
1
FLITFLPEN
Flash interface clock enable during Sleep mode
15
1
GPIOALPEN
IO port A clock enable during sleep mode
0
1
GPIOBLPEN
IO port B clock enable during Sleep mode
1
1
GPIOCLPEN
IO port C clock enable during Sleep mode
2
1
GPIODLPEN
IO port D clock enable during Sleep mode
3
1
GPIOELPEN
IO port E clock enable during Sleep mode
4
1
GPIOFLPEN
IO port F clock enable during Sleep mode
5
1
GPIOGLPEN
IO port G clock enable during Sleep mode
6
1
GPIOHLPEN
IO port H clock enable during Sleep mode
7
1
GPIOILPEN
IO port I clock enable during Sleep mode
8
1
OTGHSLPEN
USB OTG HS clock enable during Sleep mode
29
1
OTGHSULPILPEN
USB OTG HS ULPI clock enable during Sleep mode
30
1
SRAM1LPEN
SRAM 1interface clock enable during Sleep mode
16
1
SRAM2LPEN
SRAM 2 interface clock enable during Sleep mode
17
1
SRAM3LPEN
SRAM 3 interface clock enable during Sleep mode
19
1
AHB1RSTR
AHB1RSTR
AHB1 peripheral reset register
0x10
32
read-write
n
0x0
0x0
CRCRST
CRC reset
12
1
DMA1RST
DMA2 reset
21
1
DMA2RST
DMA2 reset
22
1
ETHMACRST
Ethernet MAC reset
25
1
GPIOARST
IO port A reset
0
1
GPIOBRST
IO port B reset
1
1
GPIOCRST
IO port C reset
2
1
GPIODRST
IO port D reset
3
1
GPIOERST
IO port E reset
4
1
GPIOFRST
IO port F reset
5
1
GPIOGRST
IO port G reset
6
1
GPIOHRST
IO port H reset
7
1
GPIOIRST
IO port I reset
8
1
OTGHSRST
USB OTG HS module reset
29
1
AHB2ENR
AHB2ENR
AHB2 peripheral clock enable register
0x34
32
read-write
n
0x0
0x0
CRYPEN
Cryptographic modules clock enable
4
1
DCMIEN
Camera interface enable
0
1
HASHEN
Hash modules clock enable
5
1
OTGFSEN
USB OTG FS clock enable
7
1
RNGEN
Random number generator clock enable
6
1
AHB2LPENR
AHB2LPENR
AHB2 peripheral clock enable in low power mode register
0x54
32
read-write
n
0x0
0x0
CRYPLPEN
Cryptography modules clock enable during Sleep mode
4
1
DCMILPEN
Camera interface enable during Sleep mode
0
1
HASHLPEN
Hash modules clock enable during Sleep mode
5
1
OTGFSLPEN
USB OTG FS clock enable during Sleep mode
7
1
RNGLPEN
Random number generator clock enable during Sleep mode
6
1
AHB2RSTR
AHB2RSTR
AHB2 peripheral reset register
0x14
32
read-write
n
0x0
0x0
CRYPRST
Cryptographic module reset
4
1
DCMIRST
Camera interface reset
0
1
HSAHRST
Hash module reset
5
1
OTGFSRST
USB OTG FS module reset
7
1
RNGRST
Random number generator module reset
6
1
AHB3ENR
AHB3ENR
AHB3 peripheral clock enable register
0x38
32
read-write
n
0x0
0x0
FMCEN
Flexible static memory controller module clock enable
0
1
AHB3LPENR
AHB3LPENR
AHB3 peripheral clock enable in low power mode register
0x58
32
read-write
n
0x0
0x0
FMCLPEN
Flexible static memory controller module clock enable during Sleep mode
0
1
AHB3RSTR
AHB3RSTR
AHB3 peripheral reset register
0x18
32
read-write
n
0x0
0x0
FMCRST
Flexible static memory controller module reset
0
1
APB1ENR
APB1ENR
APB1 peripheral clock enable register
0x40
32
read-write
n
0x0
0x0
CAN1EN
CAN 1 clock enable
25
1
CAN2EN
CAN 2 clock enable
26
1
DACEN
DAC interface clock enable
29
1
I2C1EN
I2C1 clock enable
21
1
I2C2EN
I2C2 clock enable
22
1
I2C3EN
I2C3 clock enable
23
1
PWREN
Power interface clock enable
28
1
SPI2EN
SPI2 clock enable
14
1
SPI3EN
SPI3 clock enable
15
1
TIM12EN
TIM12 clock enable
6
1
TIM13EN
TIM13 clock enable
7
1
TIM14EN
TIM14 clock enable
8
1
TIM2EN
TIM2 clock enable
0
1
TIM3EN
TIM3 clock enable
1
1
TIM4EN
TIM4 clock enable
2
1
TIM5EN
TIM5 clock enable
3
1
TIM6EN
TIM6 clock enable
4
1
TIM7EN
TIM7 clock enable
5
1
UART4EN
UART4 clock enable
19
1
UART5EN
UART5 clock enable
20
1
UART7ENR
UART7 clock enable
30
1
UART8ENR
UART8 clock enable
31
1
USART2EN
USART 2 clock enable
17
1
USART3EN
USART3 clock enable
18
1
WWDGEN
Window watchdog clock enable
11
1
APB1LPENR
APB1LPENR
APB1 peripheral clock enable in low power mode register
0x60
32
read-write
n
0x0
0x0
CAN1LPEN
CAN 1 clock enable during Sleep mode
25
1
CAN2LPEN
CAN 2 clock enable during Sleep mode
26
1
DACLPEN
DAC interface clock enable during Sleep mode
29
1
I2C1LPEN
I2C1 clock enable during Sleep mode
21
1
I2C2LPEN
I2C2 clock enable during Sleep mode
22
1
I2C3LPEN
I2C3 clock enable during Sleep mode
23
1
PWRLPEN
Power interface clock enable during Sleep mode
28
1
SPI2LPEN
SPI2 clock enable during Sleep mode
14
1
SPI3LPEN
SPI3 clock enable during Sleep mode
15
1
TIM12LPEN
TIM12 clock enable during Sleep mode
6
1
TIM13LPEN
TIM13 clock enable during Sleep mode
7
1
TIM14LPEN
TIM14 clock enable during Sleep mode
8
1
TIM2LPEN
TIM2 clock enable during Sleep mode
0
1
TIM3LPEN
TIM3 clock enable during Sleep mode
1
1
TIM4LPEN
TIM4 clock enable during Sleep mode
2
1
TIM5LPEN
TIM5 clock enable during Sleep mode
3
1
TIM6LPEN
TIM6 clock enable during Sleep mode
4
1
TIM7LPEN
TIM7 clock enable during Sleep mode
5
1
UART4LPEN
UART4 clock enable during Sleep mode
19
1
UART5LPEN
UART5 clock enable during Sleep mode
20
1
UART7LPEN
UART7 clock enable during Sleep mode
30
1
UART8LPEN
UART8 clock enable during Sleep mode
31
1
USART2LPEN
USART2 clock enable during Sleep mode
17
1
USART3LPEN
USART3 clock enable during Sleep mode
18
1
WWDGLPEN
Window watchdog clock enable during Sleep mode
11
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register
0x20
32
read-write
n
0x0
0x0
CAN1RST
CAN1 reset
25
1
CAN2RST
CAN2 reset
26
1
DACRST
DAC reset
29
1
I2C1RST
I2C 1 reset
21
1
I2C2RST
I2C 2 reset
22
1
I2C3RST
I2C3 reset
23
1
PWRRST
Power interface reset
28
1
SPI2RST
SPI 2 reset
14
1
SPI3RST
SPI 3 reset
15
1
TIM12RST
TIM12 reset
6
1
TIM13RST
TIM13 reset
7
1
TIM14RST
TIM14 reset
8
1
TIM2RST
TIM2 reset
0
1
TIM3RST
TIM3 reset
1
1
TIM4RST
TIM4 reset
2
1
TIM5RST
TIM5 reset
3
1
TIM6RST
TIM6 reset
4
1
TIM7RST
TIM7 reset
5
1
UART2RST
USART 2 reset
17
1
UART3RST
USART 3 reset
18
1
UART4RST
USART 4 reset
19
1
UART5RST
USART 5 reset
20
1
UART7RST
UART7 reset
30
1
UART8RST
UART8 reset
31
1
WWDGRST
Window watchdog reset
11
1
APB2ENR
APB2ENR
APB2 peripheral clock enable register
0x44
32
read-write
n
0x0
0x0
ADC1EN
ADC1 clock enable
8
1
ADC2EN
ADC2 clock enable
9
1
ADC3EN
ADC3 clock enable
10
1
SDIOEN
SDIO clock enable
11
1
SPI1EN
SPI1 clock enable
12
1
SPI4ENR
SPI4 clock enable
13
1
SPI5ENR
SPI5 clock enable
20
1
SPI6ENR
SPI6 clock enable
21
1
SYSCFGEN
System configuration controller clock enable
14
1
TIM10EN
TIM10 clock enable
17
1
TIM11EN
TIM11 clock enable
18
1
TIM1EN
TIM1 clock enable
0
1
TIM8EN
TIM8 clock enable
1
1
TIM9EN
TIM9 clock enable
16
1
USART1EN
USART1 clock enable
4
1
USART6EN
USART6 clock enable
5
1
APB2LPENR
APB2LPENR
APB2 peripheral clock enabled in low power mode register
0x64
32
read-write
n
0x0
0x0
ADC1LPEN
ADC1 clock enable during Sleep mode
8
1
ADC2LPEN
ADC2 clock enable during Sleep mode
9
1
ADC3LPEN
ADC 3 clock enable during Sleep mode
10
1
SDIOLPEN
SDIO clock enable during Sleep mode
11
1
SPI1LPEN
SPI 1 clock enable during Sleep mode
12
1
SPI4LPEN
SPI 4 clock enable during Sleep mode
13
1
SPI5LPEN
SPI 5 clock enable during Sleep mode
20
1
SPI6LPEN
SPI 6 clock enable during Sleep mode
21
1
SYSCFGLPEN
System configuration controller clock enable during Sleep mode
14
1
TIM10LPEN
TIM10 clock enable during Sleep mode
17
1
TIM11LPEN
TIM11 clock enable during Sleep mode
18
1
TIM1LPEN
TIM1 clock enable during Sleep mode
0
1
TIM8LPEN
TIM8 clock enable during Sleep mode
1
1
TIM9LPEN
TIM9 clock enable during sleep mode
16
1
USART1LPEN
USART1 clock enable during Sleep mode
4
1
USART6LPEN
USART6 clock enable during Sleep mode
5
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x24
32
read-write
n
0x0
0x0
ADCRST
ADC interface reset (common to all ADCs)
8
1
SDIORST
SDIO reset
11
1
SPI1RST
SPI 1 reset
12
1
SPI4RST
SPI4 reset
13
1
SPI5RST
SPI5 reset
20
1
SPI6RST
SPI6 reset
21
1
SYSCFGRST
System configuration controller reset
14
1
TIM10RST
TIM10 reset
17
1
TIM11RST
TIM11 reset
18
1
TIM1RST
TIM1 reset
0
1
TIM8RST
TIM8 reset
1
1
TIM9RST
TIM9 reset
16
1
USART1RST
USART1 reset
4
1
USART6RST
USART6 reset
5
1
BDCR
BDCR
Backup domain control register
0x70
32
read-write
n
0x0
0x0
BDRST
Backup domain software reset
16
1
read-write
LSEBYP
External low-speed oscillator bypass
2
1
read-write
LSEON
External low-speed oscillator enable
0
1
read-write
LSERDY
External low-speed oscillator ready
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSEL0
RTC clock source selection
8
1
read-write
RTCSEL1
RTC clock source selection
9
1
read-write
CFGR
CFGR
clock configuration register
0x8
32
read-write
n
0x0
0x0
HPRE
AHB prescaler
4
4
read-write
I2SSRC
I2S clock selection
23
1
read-write
MCO1
Microcontroller clock output 1
21
2
read-write
MCO1PRE
MCO1 prescaler
24
3
read-write
MCO2
Microcontroller clock output 2
30
2
read-write
MCO2PRE
MCO2 prescaler
27
3
read-write
PPRE1
APB Low speed prescaler (APB1)
10
3
read-write
PPRE2
APB high-speed prescaler (APB2)
13
3
read-write
RTCPRE
HSE division factor for RTC clock
16
5
read-write
SW0
System clock switch
0
1
read-write
SW1
System clock switch
1
1
read-write
SWS0
System clock switch status
2
1
read-only
SWS1
System clock switch status
3
1
read-only
CIR
CIR
clock interrupt register
0xC
32
read-write
n
0x0
0x0
CSSC
Clock security system interrupt clear
23
1
write-only
CSSF
Clock security system interrupt flag
7
1
read-only
HSERDYC
HSE ready interrupt clear
19
1
write-only
HSERDYF
HSE ready interrupt flag
3
1
read-only
HSERDYIE
HSE ready interrupt enable
11
1
read-write
HSIRDYC
HSI ready interrupt clear
18
1
write-only
HSIRDYF
HSI ready interrupt flag
2
1
read-only
HSIRDYIE
HSI ready interrupt enable
10
1
read-write
LSERDYC
LSE ready interrupt clear
17
1
write-only
LSERDYF
LSE ready interrupt flag
1
1
read-only
LSERDYIE
LSE ready interrupt enable
9
1
read-write
LSIRDYC
LSI ready interrupt clear
16
1
write-only
LSIRDYF
LSI ready interrupt flag
0
1
read-only
LSIRDYIE
LSI ready interrupt enable
8
1
read-write
PLLI2SRDYC
PLLI2S ready interrupt clear
21
1
write-only
PLLI2SRDYF
PLLI2S ready interrupt flag
5
1
read-only
PLLI2SRDYIE
PLLI2S ready interrupt enable
13
1
read-write
PLLRDYC
Main PLL(PLL) ready interrupt clear
20
1
write-only
PLLRDYF
Main PLL (PLL) ready interrupt flag
4
1
read-only
PLLRDYIE
Main PLL (PLL) ready interrupt enable
12
1
read-write
CR
CR
clock control register
0x0
32
read-write
n
0x0
0x0
CSSON
Clock security system enable
19
1
read-write
HSEBYP
HSE clock bypass
18
1
read-write
HSEON
HSE clock enable
16
1
read-write
HSERDY
HSE clock ready flag
17
1
read-only
HSICAL
Internal high-speed clock calibration
8
8
read-only
HSION
Internal high-speed clock enable
0
1
read-write
HSIRDY
Internal high-speed clock ready flag
1
1
read-only
HSITRIM
Internal high-speed clock trimming
3
5
read-write
PLLI2SON
PLLI2S enable
26
1
read-write
PLLI2SRDY
PLLI2S clock ready flag
27
1
read-only
PLLON
Main PLL (PLL) enable
24
1
read-write
PLLRDY
Main PLL (PLL) clock ready flag
25
1
read-only
CSR
CSR
clock control and status register
0x74
32
read-write
n
0x0
0x0
BORRSTF
BOR reset flag
25
1
read-write
LPWRRSTF
Low-power reset flag
31
1
read-write
LSION
Internal low-speed oscillator enable
0
1
read-write
LSIRDY
Internal low-speed oscillator ready
1
1
read-only
PADRSTF
PIN reset flag
26
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
RMVF
Remove reset flag
24
1
read-write
SFTRSTF
Software reset flag
28
1
read-write
WDGRSTF
Independent watchdog reset flag
29
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
PLLCFGR
PLLCFGR
PLL configuration register
0x4
32
read-write
n
0x0
0x0
PLLM0
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
0
1
PLLM1
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
1
1
PLLM2
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
2
1
PLLM3
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
3
1
PLLM4
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
4
1
PLLM5
Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
5
1
PLLN0
Main PLL (PLL) multiplication factor for VCO
6
1
PLLN1
Main PLL (PLL) multiplication factor for VCO
7
1
PLLN2
Main PLL (PLL) multiplication factor for VCO
8
1
PLLN3
Main PLL (PLL) multiplication factor for VCO
9
1
PLLN4
Main PLL (PLL) multiplication factor for VCO
10
1
PLLN5
Main PLL (PLL) multiplication factor for VCO
11
1
PLLN6
Main PLL (PLL) multiplication factor for VCO
12
1
PLLN7
Main PLL (PLL) multiplication factor for VCO
13
1
PLLN8
Main PLL (PLL) multiplication factor for VCO
14
1
PLLP0
Main PLL (PLL) division factor for main system clock
16
1
PLLP1
Main PLL (PLL) division factor for main system clock
17
1
PLLQ0
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
24
1
PLLQ1
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
25
1
PLLQ2
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
26
1
PLLQ3
Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
27
1
PLLSRC
Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
22
1
PLLI2SCFGR
PLLI2SCFGR
PLLI2S configuration register
0x84
32
read-write
n
0x0
0x0
PLLI2SNx
PLLI2S multiplication factor for VCO
6
9
PLLI2SRx
PLLI2S division factor for I2S clocks
28
3
SSCGR
SSCGR
spread spectrum clock generation register
0x80
32
read-write
n
0x0
0x0
INCSTEP
Incrementation step
13
15
MODPER
Modulation period
0
13
SPREADSEL
Spread Select
30
1
SSCGEN
Spread spectrum modulation enable
31
1
RNG
Random number generator
RNG
0x0
0x0
0x400
registers
n
FPU
FPU interrupt
81
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
IE
Interrupt enable
3
1
RNGEN
Random number generator enable
2
1
DR
DR
data register
0x8
32
read-only
n
0x0
0x0
RNDATA
Random data
0
32
SR
SR
status register
0x4
32
read-write
n
0x0
0x0
CECS
Clock error current status
1
1
read-only
CEIS
Clock error interrupt status
5
1
read-write
DRDY
Data ready
0
1
read-only
SECS
Seed error current status
2
1
read-only
SEIS
Seed error interrupt status
6
1
read-write
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
RTC_WKUP
RTC Wakeup interrupt through the EXTI line
3
RTC_Alarm
RTC Alarms (A and B) through EXTI line interrupt
41
ALRMAR
ALRMAR
alarm A register
0x1C
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm A seconds mask
7
1
MSK2
Alarm A minutes mask
15
1
MSK3
Alarm A hours mask
23
1
MSK4
Alarm A date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMASSR
ALRMASSR
alarm A sub second register
0x44
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
ALRMBR
ALRMBR
alarm B register
0x20
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm B seconds mask
7
1
MSK2
Alarm B minutes mask
15
1
MSK3
Alarm B hours mask
23
1
MSK4
Alarm B date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMBSSR
ALRMBSSR
alarm B sub second register
0x48
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
BKP0R
BKP0R
backup register
0x50
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP10R
BKP10R
backup register
0x78
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP11R
BKP11R
backup register
0x7C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP12R
BKP12R
backup register
0x80
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP13R
BKP13R
backup register
0x84
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP14R
BKP14R
backup register
0x88
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP15R
BKP15R
backup register
0x8C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP16R
BKP16R
backup register
0x90
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP17R
BKP17R
backup register
0x94
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP18R
BKP18R
backup register
0x98
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP19R
BKP19R
backup register
0x9C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP1R
BKP1R
backup register
0x54
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP2R
BKP2R
backup register
0x58
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP3R
BKP3R
backup register
0x5C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP4R
BKP4R
backup register
0x60
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP5R
BKP5R
backup register
0x64
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP6R
BKP6R
backup register
0x68
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP7R
BKP7R
backup register
0x6C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP8R
BKP8R
backup register
0x70
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP9R
BKP9R
backup register
0x74
32
read-write
n
0x0
0x0
BKP
BKP
0
32
CALIBR
CALIBR
calibration register
0x18
32
read-write
n
0x0
0x0
DC
Digital calibration
0
5
DCS
Digital calibration sign
7
1
CALR
CALR
calibration register
0x3C
32
read-write
n
0x0
0x0
CALM
Calibration minus
0
9
CALP
Increase frequency of RTC by 488.5 ppm
15
1
CALW16
Use a 16-second calibration cycle period
13
1
CALW8
Use an 8-second calibration cycle period
14
1
CR
CR
control register
0x8
32
read-write
n
0x0
0x0
ADD1H
Add 1 hour (summer time change)
16
1
ALRAE
Alarm A enable
8
1
ALRAIE
Alarm A interrupt enable
12
1
ALRBE
Alarm B enable
9
1
ALRBIE
Alarm B interrupt enable
13
1
BKP
Backup
18
1
COE
Calibration output enable
23
1
DCE
Coarse digital calibration enable
7
1
FMT
Hour format
6
1
OSEL
Output selection
21
2
POL
Output polarity
20
1
REFCKON
Reference clock detection enable (50 or 60 Hz)
4
1
SUB1H
Subtract 1 hour (winter time change)
17
1
TSE
Time stamp enable
11
1
TSEDGE
Time-stamp event active edge
3
1
TSIE
Time-stamp interrupt enable
15
1
WCKSEL
Wakeup clock selection
0
3
WUTE
Wakeup timer enable
10
1
WUTIE
Wakeup timer interrupt enable
14
1
DR
DR
date register
0x4
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
ISR
ISR
initialization and status register
0xC
32
read-write
n
0x0
0x0
ALRAF
Alarm A flag
8
1
read-write
ALRAWF
Alarm A write flag
0
1
read-only
ALRBF
Alarm B flag
9
1
read-write
ALRBWF
Alarm B write flag
1
1
read-only
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-only
INITS
Initialization status flag
4
1
read-only
RECALPF
Recalibration pending Flag
16
1
read-only
RSF
Registers synchronization flag
5
1
read-write
SHPF
Shift operation pending
3
1
read-write
TAMP1F
Tamper detection flag
13
1
read-write
TAMP2F
TAMPER2 detection flag
14
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVF
Time-stamp overflow flag
12
1
read-write
WUTF
Wakeup timer flag
10
1
read-write
WUTWF
Wakeup timer write flag
2
1
read-only
PRER
PRER
prescaler register
0x10
32
read-write
n
0x0
0x0
PREDIV_A
Asynchronous prescaler factor
16
7
PREDIV_S
Synchronous prescaler factor
0
15
SHIFTR
SHIFTR
shift control register
0x2C
32
write-only
n
0x0
0x0
ADD1S
Add one second
31
1
SUBFS
Subtract a fraction of a second
0
15
SSR
SSR
sub second register
0x28
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TAFCR
TAFCR
tamper and alternate function configuration register
0x40
32
read-write
n
0x0
0x0
ALARMOUTTYPE
AFO_ALARM output type
18
1
TAMP1E
Tamper 1 detection enable
0
1
TAMP1INSEL
TAMPER1 mapping
16
1
TAMP1TRG
Active level for tamper 1
1
1
TAMP2E
Tamper 2 detection enable
3
1
TAMP2TRG
Active level for tamper 2
4
1
TAMPFLT
Tamper filter count
11
2
TAMPFREQ
Tamper sampling frequency
8
3
TAMPIE
Tamper interrupt enable
2
1
TAMPPRCH
Tamper precharge duration
13
2
TAMPPUDIS
TAMPER pull-up disable
15
1
TAMPTS
Activate timestamp on tamper detection event
7
1
TSINSEL
TIMESTAMP mapping
17
1
TR
TR
time register
0x0
32
read-write
n
0x0
0x0
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
TSDR
TSDR
time stamp date register
0x34
32
read-only
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
TSSSR
TSSSR
timestamp sub second register
0x38
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TSTR
TSTR
time stamp time register
0x30
32
read-only
n
0x0
0x0
ALARMOUTTYPE
AFO_ALARM output type
18
1
TAMP1E
Tamper 1 detection enable
0
1
TAMP1INSEL
TAMPER1 mapping
16
1
TAMP1TRG
Active level for tamper 1
1
1
TAMPIE
Tamper interrupt enable
2
1
TSINSEL
TIMESTAMP mapping
17
1
WPR
WPR
write protection register
0x24
32
write-only
n
0x0
0x0
KEY
Write protection key
0
8
WUTR
WUTR
wakeup timer register
0x14
32
read-write
n
0x0
0x0
WUT
Wakeup auto-reload value bits
0
16
SAI1
Serial audio interface
SAI
0x0
0x0
0x400
registers
n
ACLRFR
ACLRFR
AClear flag register
0x1C
32
read-write
n
0x0
0x0
CAFSDET
Clear anticipated frame synchronization detection flag.
5
1
CNRDY
Clear codec not ready flag
4
1
LFSDET
Clear late frame synchronization detection flag
6
1
MUTEDET
Mute detection flag
1
1
OVRUDR
Clear overrun / underrun
0
1
WCKCFG
Clear wrong clock configuration flag
2
1
ACR1
ACR1
AConfiguration register 1
0x4
32
read-write
n
0x0
0x0
CKSTR
Clock strobing edge
9
1
DMAEN
DMA enable
17
1
DS
Data size
5
3
LSBFIRST
Least significant bit first
8
1
MCJDIV
Master clock divider
20
4
MODE
Audio block mode
0
2
MONO
Mono mode
12
1
NODIV
No divider
19
1
OutDri
Output drive
13
1
PRTCFG
Protocol configuration
2
2
SAIAEN
Audio block A enable
16
1
SYNCEN
Synchronization enable
10
2
ACR2
ACR2
AConfiguration register 2
0x8
32
read-write
n
0x0
0x0
COMP
Companding mode
14
2
CPL
Complement bit
13
1
FFLUS
FIFO flush
3
1
FTH
FIFO threshold
0
3
MUTE
Mute
5
1
MUTECN
Mute counter
7
6
MUTEVAL
Mute value
6
1
TRIS
Tristate management on data line
4
1
ADR
ADR
AData register
0x20
32
read-write
n
0x0
0x0
DATA
Data
0
32
AFRCR
AFRCR
AFRCR
0xC
32
read-write
n
0x0
0x0
FRL
Frame length
0
8
FSALL
Frame synchronization active level length
8
7
FSDEF
Frame synchronization definition
16
1
FSOFF
Frame synchronization offset
18
1
FSPOL
Frame synchronization polarity
17
1
AIM
AIM
AInterrupt mask register2
0x14
32
read-write
n
0x0
0x0
AFSDETIE
Anticipated frame synchronization detection interrupt enable
5
1
CNRDYIE
Codec not ready interrupt enable
4
1
FREQIE
FIFO request interrupt enable
3
1
LFSDET
Late frame synchronization detection interrupt enable
6
1
MUTEDET
Mute detection interrupt enable
1
1
OVRUDRIE
Overrun/underrun interrupt enable
0
1
WCKCFG
Wrong clock configuration interrupt enable
2
1
ASLOTR
ASLOTR
ASlot register
0x10
32
read-write
n
0x0
0x0
FBOFF
First bit offset
0
5
NBSLOT
Number of slots in an audio frame
8
4
SLOTEN
Slot enable
16
16
SLOTSZ
Slot size
6
2
ASR
ASR
AStatus register
0x18
32
read-write
n
0x0
0x0
AFSDET
Anticipated frame synchronization detection
5
1
CNRDY
Codec not ready
4
1
FLVL
FIFO level threshold
16
3
FREQ
FIFO request
3
1
LFSDET
Late frame synchronization detection
6
1
MUTEDET
Mute detection
1
1
OVRUDR
Overrun / underrun
0
1
WCKCFG
Wrong clock configuration flag. This bit is read only.
2
1
BCLRFR
BCLRFR
BClear flag register
0x3C
32
write-only
n
0x0
0x0
CAFSDET
Clear anticipated frame synchronization detection flag
5
1
CNRDY
Clear codec not ready flag
4
1
LFSDET
Clear late frame synchronization detection flag
6
1
MUTEDET
Mute detection flag
1
1
OVRUDR
Clear overrun / underrun
0
1
WCKCFG
Clear wrong clock configuration flag
2
1
BCR1
BCR1
BConfiguration register 1
0x24
32
read-write
n
0x0
0x0
CKSTR
Clock strobing edge
9
1
DMAEN
DMA enable
17
1
DS
Data size
5
3
LSBFIRST
Least significant bit first
8
1
MCJDIV
Master clock divider
20
4
MODE
Audio block mode
0
2
MONO
Mono mode
12
1
NODIV
No divider
19
1
OutDri
Output drive
13
1
PRTCFG
Protocol configuration
2
2
SAIBEN
Audio block B enable
16
1
SYNCEN
Synchronization enable
10
2
BCR2
BCR2
BConfiguration register 2
0x28
32
read-write
n
0x0
0x0
COMP
Companding mode
14
2
CPL
Complement bit
13
1
FFLUS
FIFO flush
3
1
FTH
FIFO threshold
0
3
MUTE
Mute
5
1
MUTECN
Mute counter
7
6
MUTEVAL
Mute value
6
1
TRIS
Tristate management on data line
4
1
BDR
BDR
BData register
0x40
32
read-write
n
0x0
0x0
DATA
Data
0
32
BFRCR
BFRCR
BFRCR
0x2C
32
read-write
n
0x0
0x0
FRL
Frame length
0
8
FSALL
Frame synchronization active level length
8
7
FSDEF
Frame synchronization definition
16
1
FSOFF
Frame synchronization offset
18
1
FSPOL
Frame synchronization polarity
17
1
BIM
BIM
BInterrupt mask register2
0x34
32
read-write
n
0x0
0x0
AFSDETIE
Anticipated frame synchronization detection interrupt enable
5
1
CNRDYIE
Codec not ready interrupt enable
4
1
FREQIE
FIFO request interrupt enable
3
1
LFSDETIE
Late frame synchronization detection interrupt enable
6
1
MUTEDET
Mute detection interrupt enable
1
1
OVRUDRIE
Overrun/underrun interrupt enable
0
1
WCKCFG
Wrong clock configuration interrupt enable
2
1
BSLOTR
BSLOTR
BSlot register
0x30
32
read-write
n
0x0
0x0
FBOFF
First bit offset
0
5
NBSLOT
Number of slots in an audio frame
8
4
SLOTEN
Slot enable
16
16
SLOTSZ
Slot size
6
2
BSR
BSR
BStatus register
0x38
32
read-only
n
0x0
0x0
AFSDET
Anticipated frame synchronization detection
5
1
CNRDY
Codec not ready
4
1
FLVL
FIFO level threshold
16
3
FREQ
FIFO request
3
1
LFSDET
Late frame synchronization detection
6
1
MUTEDET
Mute detection
1
1
OVRUDR
Overrun / underrun
0
1
WCKCFG
Wrong clock configuration flag
2
1
SCB
System control block
SCB
0x0
0x0
0x41
registers
n
AFSR
AFSR
Auxiliary fault status register
0x3C
32
read-write
n
0x0
0x0
IMPDEF
Implementation defined
0
32
AIRCR
AIRCR
Application interrupt and reset control register
0xC
32
read-write
n
0x0
0x0
ENDIANESS
ENDIANESS
15
1
PRIGROUP
PRIGROUP
8
3
SYSRESETREQ
SYSRESETREQ
2
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
VECTKEYSTAT
Register key
16
16
VECTRESET
VECTRESET
0
1
BFAR
BFAR
Bus fault address register
0x38
32
read-write
n
0x0
0x0
BFAR
Bus fault address
0
32
CCR
CCR
Configuration and control register
0x14
32
read-write
n
0x0
0x0
BFHFNMIGN
BFHFNMIGN
8
1
DIV_0_TRP
DIV_0_TRP
4
1
NONBASETHRDENA
Configures how the processor enters Thread mode
0
1
STKALIGN
STKALIGN
9
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
USERSETMPEND
USERSETMPEND
1
1
CFSR_UFSR_BFSR_MMFSR
CFSR_UFSR_BFSR_MMFSR
Configurable fault status register
0x28
32
read-write
n
0x0
0x0
BFARVALID
Bus Fault Address Register (BFAR) valid flag
15
1
DIVBYZERO
Divide by zero usage fault
25
1
IACCVIOL
Instruction access violation flag
1
1
IBUSERR
Instruction bus error
8
1
IMPRECISERR
Imprecise data bus error
10
1
INVPC
Invalid PC load usage fault
18
1
INVSTATE
Invalid state usage fault
17
1
LSPERR
Bus fault on floating-point lazy state preservation
13
1
MLSPERR
MLSPERR
5
1
MMARVALID
Memory Management Fault Address Register (MMAR) valid flag
7
1
MSTKERR
Memory manager fault on stacking for exception entry.
4
1
MUNSTKERR
Memory manager fault on unstacking for a return from exception
3
1
NOCP
No coprocessor usage fault.
19
1
PRECISERR
Precise data bus error
9
1
STKERR
Bus fault on stacking for exception entry
12
1
UNALIGNED
Unaligned access usage fault
24
1
UNDEFINSTR
Undefined instruction usage fault
16
1
UNSTKERR
Bus fault on unstacking for a return from exception
11
1
CPUID
CPUID
CPUID base register
0x0
32
read-only
n
0x0
0x0
Constant
Reads as 0xF
16
4
Implementer
Implementer code
24
8
PartNo
Part number of the processor
4
12
Revision
Revision number
0
4
Variant
Variant number
20
4
HFSR
HFSR
Hard fault status register
0x2C
32
read-write
n
0x0
0x0
DEBUG_VT
Reserved for Debug use
31
1
FORCED
Forced hard fault
30
1
VECTTBL
Vector table hard fault
1
1
ICSR
ICSR
Interrupt control and state register
0x4
32
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag
22
1
NMIPENDSET
NMI set-pending bit.
31
1
PENDSTCLR
SysTick exception clear-pending bit
25
1
PENDSTSET
SysTick exception set-pending bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
RETTOBASE
Return to base level
11
1
VECTACTIVE
Active vector
0
9
VECTPENDING
Pending vector
12
7
MMFAR
MMFAR
Memory management fault address register
0x34
32
read-write
n
0x0
0x0
MMFAR
Memory management fault address
0
32
SCR
SCR
System control register
0x10
32
read-write
n
0x0
0x0
SEVEONPEND
Send Event on Pending bit
4
1
SLEEPDEEP
SLEEPDEEP
2
1
SLEEPONEXIT
SLEEPONEXIT
1
1
SHCRS
SHCRS
System handler control and state register
0x24
32
read-write
n
0x0
0x0
BUSFAULTACT
Bus fault exception active bit
1
1
BUSFAULTENA
Bus fault enable bit
17
1
BUSFAULTPENDED
Bus fault exception pending bit
14
1
MEMFAULTACT
Memory management fault exception active bit
0
1
MEMFAULTENA
Memory management fault enable bit
16
1
MEMFAULTPENDED
Memory management fault exception pending bit
13
1
MONITORACT
Debug monitor active bit
8
1
PENDSVACT
PendSV exception active bit
10
1
SVCALLACT
SVC call active bit
7
1
SVCALLPENDED
SVC call pending bit
15
1
SYSTICKACT
SysTick exception active bit
11
1
USGFAULTACT
Usage fault exception active bit
3
1
USGFAULTENA
Usage fault enable bit
18
1
USGFAULTPENDED
Usage fault exception pending bit
12
1
SHPR1
SHPR1
System handler priority registers
0x18
32
read-write
n
0x0
0x0
PRI_4
Priority of system handler 4
0
8
PRI_5
Priority of system handler 5
8
8
PRI_6
Priority of system handler 6
16
8
SHPR2
SHPR2
System handler priority registers
0x1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11
24
8
SHPR3
SHPR3
System handler priority registers
0x20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14
16
8
PRI_15
Priority of system handler 15
24
8
VTOR
VTOR
Vector table offset register
0x8
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset field
9
21
SCB_ACTRL
System control block ACTLR
SCB
0x0
0x0
0x5
registers
n
ACTRL
ACTRL
Auxiliary control register
0x0
32
read-write
n
0x0
0x0
DISDEFWBUF
DISDEFWBUF
1
1
DISFOLD
DISFOLD
2
1
DISFPCA
DISFPCA
8
1
DISMCYCINT
DISMCYCINT
0
1
DISOOFP
DISOOFP
9
1
SDIO
Secure digital input/output interface
SDIO
0x0
0x0
0x400
registers
n
SDIO
SDIO global interrupt
49
ARG
ARG
argument register
0x8
32
read-write
n
0x0
0x0
CMDARG
Command argument
0
32
CLKCR
CLKCR
SDI clock control register
0x4
32
read-write
n
0x0
0x0
BYPASS
Clock divider bypass enable bit
10
1
CLKDIV
Clock divide factor
0
8
CLKEN
Clock enable bit
8
1
HWFC_EN
HW Flow Control enable
14
1
NEGEDGE
SDIO_CK dephasing selection bit
13
1
PWRSAV
Power saving configuration bit
9
1
WIDBUS
Wide bus mode enable bit
11
2
CMD
CMD
command register
0xC
32
read-write
n
0x0
0x0
CE_ATACMD
CE-ATA command
14
1
CMDINDEX
Command index
0
6
CPSMEN
Command path state machine (CPSM) Enable bit
10
1
ENCMDcompl
Enable CMD completion
12
1
nIEN
not Interrupt Enable
13
1
SDIOSuspend
SD I/O suspend command
11
1
WAITINT
CPSM waits for interrupt request
8
1
WAITPEND
CPSM Waits for ends of data transfer (CmdPend internal signal).
9
1
WAITRESP
Wait for response bits
6
2
DCOUNT
DCOUNT
data counter register
0x30
32
read-only
n
0x0
0x0
DATACOUNT
Data count value
0
25
DCTRL
DCTRL
data control register
0x2C
32
read-write
n
0x0
0x0
DBLOCKSIZE
Data block size
4
4
DMAEN
DMA enable bit
3
1
DTDIR
Data transfer direction selection
1
1
DTEN
DTEN
0
1
DTMODE
Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
2
1
RWMOD
Read wait mode
10
1
RWSTART
Read wait start
8
1
RWSTOP
Read wait stop
9
1
SDIOEN
SD I/O enable functions
11
1
DLEN
DLEN
data length register
0x28
32
read-write
n
0x0
0x0
DATALENGTH
Data length value
0
25
DTIMER
DTIMER
data timer register
0x24
32
read-write
n
0x0
0x0
DATATIME
Data timeout period
0
32
FIFO
FIFO
data FIFO register
0x80
32
read-write
n
0x0
0x0
FIFOData
Receive and transmit FIFO data
0
32
FIFOCNT
FIFOCNT
FIFO counter register
0x48
32
read-only
n
0x0
0x0
FIFOCOUNT
Remaining number of words to be written to or read from the FIFO.
0
24
ICR
ICR
interrupt clear register
0x38
32
read-write
n
0x0
0x0
CCRCFAILC
CCRCFAIL flag clear bit
0
1
CEATAENDC
CEATAEND flag clear bit
23
1
CMDRENDC
CMDREND flag clear bit
6
1
CMDSENTC
CMDSENT flag clear bit
7
1
CTIMEOUTC
CTIMEOUT flag clear bit
2
1
DATAENDC
DATAEND flag clear bit
8
1
DBCKENDC
DBCKEND flag clear bit
10
1
DCRCFAILC
DCRCFAIL flag clear bit
1
1
DTIMEOUTC
DTIMEOUT flag clear bit
3
1
RXOVERRC
RXOVERR flag clear bit
5
1
SDIOITC
SDIOIT flag clear bit
22
1
STBITERRC
STBITERR flag clear bit
9
1
TXUNDERRC
TXUNDERR flag clear bit
4
1
MASK
MASK
mask register
0x3C
32
read-write
n
0x0
0x0
CCRCFAILIE
Command CRC fail interrupt enable
0
1
CEATAENDIE
CE-ATA command completion signal received interrupt enable
23
1
CMDACTIE
Command acting interrupt enable
11
1
CMDRENDIE
Command response received interrupt enable
6
1
CMDSENTIE
Command sent interrupt enable
7
1
CTIMEOUTIE
Command timeout interrupt enable
2
1
DATAENDIE
Data end interrupt enable
8
1
DBCKENDIE
Data block end interrupt enable
10
1
DCRCFAILIE
Data CRC fail interrupt enable
1
1
DTIMEOUTIE
Data timeout interrupt enable
3
1
RXACTIE
Data receive acting interrupt enable
13
1
RXDAVLIE
Data available in Rx FIFO interrupt enable
21
1
RXFIFOEIE
Rx FIFO empty interrupt enable
19
1
RXFIFOFIE
Rx FIFO full interrupt enable
17
1
RXFIFOHFIE
Rx FIFO half full interrupt enable
15
1
RXOVERRIE
Rx FIFO overrun error interrupt enable
5
1
SDIOITIE
SDIO mode interrupt received interrupt enable
22
1
STBITERRIE
Start bit error interrupt enable
9
1
TXACTIE
Data transmit acting interrupt enable
12
1
TXDAVLIE
Data available in Tx FIFO interrupt enable
20
1
TXFIFOEIE
Tx FIFO empty interrupt enable
18
1
TXFIFOFIE
Tx FIFO full interrupt enable
16
1
TXFIFOHEIE
Tx FIFO half empty interrupt enable
14
1
TXUNDERRIE
Tx FIFO underrun error interrupt enable
4
1
POWER
POWER
power control register
0x0
32
read-write
n
0x0
0x0
PWRCTRL
PWRCTRL
0
2
RESP1
RESP1
response 1..4 register
0x14
32
read-only
n
0x0
0x0
CARDSTATUS1
see Table 132.
0
32
RESP2
RESP2
response 1..4 register
0x18
32
read-only
n
0x0
0x0
CARDSTATUS2
see Table 132.
0
32
RESP3
RESP3
response 1..4 register
0x1C
32
read-only
n
0x0
0x0
CARDSTATUS3
see Table 132.
0
32
RESP4
RESP4
response 1..4 register
0x20
32
read-only
n
0x0
0x0
CARDSTATUS4
see Table 132.
0
32
RESPCMD
RESPCMD
command response register
0x10
32
read-only
n
0x0
0x0
RESPCMD
Response command index
0
6
STA
STA
status register
0x34
32
read-only
n
0x0
0x0
CCRCFAIL
Command response received (CRC check failed)
0
1
CEATAEND
CE-ATA command completion signal received for CMD61
23
1
CMDACT
Command transfer in progress
11
1
CMDREND
Command response received (CRC check passed)
6
1
CMDSENT
Command sent (no response required)
7
1
CTIMEOUT
Command response timeout
2
1
DATAEND
Data end (data counter, SDIDCOUNT, is zero)
8
1
DBCKEND
Data block sent/received (CRC check passed)
10
1
DCRCFAIL
Data block sent/received (CRC check failed)
1
1
DTIMEOUT
Data timeout
3
1
RXACT
Data receive in progress
13
1
RXDAVL
Data available in receive FIFO
21
1
RXFIFOE
Receive FIFO empty
19
1
RXFIFOF
Receive FIFO full
17
1
RXFIFOHF
Receive FIFO half full: there are at least 8 words in the FIFO
15
1
RXOVERR
Received FIFO overrun error
5
1
SDIOIT
SDIO interrupt received
22
1
STBITERR
Start bit not detected on all data signals in wide bus mode
9
1
TXACT
Data transmit in progress
12
1
TXDAVL
Data available in transmit FIFO
20
1
TXFIFOE
Transmit FIFO empty
18
1
TXFIFOF
Transmit FIFO full
16
1
TXFIFOHE
Transmit FIFO half empty: at least 8 words can be written into the FIFO
14
1
TXUNDERR
Transmit FIFO underrun error
4
1
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI1 global interrupt
35
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI2
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI2
SPI2 global interrupt
36
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI3
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI3
SPI3 global interrupt
51
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI4
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI4
SPI 4 global interrupt
84
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI5
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI5
SPI 5 global interrupt
85
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI6
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI6
SPI 6 global interrupt
86
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
STK
SysTick timer
STK
0x0
0x0
0x11
registers
n
CALIB
CALIB
SysTick calibration value register
0xC
32
read-write
n
0x0
0x0
NOREF
NOREF flag. Reads as zero
31
1
SKEW
SKEW flag: Indicates whether the TENMS value is exact
30
1
TENMS
Calibration value
0
24
CTRL
CTRL
SysTick control and status register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request enable
1
1
LOAD
LOAD
SysTick reload value register
0x4
32
read-write
n
0x0
0x0
RELOAD
RELOAD value
0
24
VAL
VAL
SysTick current value register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current counter value
0
24
SYSCFG
System configuration controller
SYSCFG
0x0
0x0
0x400
registers
n
CMPCR
CMPCR
Compensation cell control register
0x20
32
read-only
n
0x0
0x0
CMP_PD
Compensation cell power-down
0
1
READY
READY
8
1
EXTICR1
EXTICR1
external interrupt configuration register 1
0x8
32
read-write
n
0x0
0x0
EXTI0
EXTI x configuration (x = 0 to 3)
0
4
EXTI1
EXTI x configuration (x = 0 to 3)
4
4
EXTI2
EXTI x configuration (x = 0 to 3)
8
4
EXTI3
EXTI x configuration (x = 0 to 3)
12
4
EXTICR2
EXTICR2
external interrupt configuration register 2
0xC
32
read-write
n
0x0
0x0
EXTI4
EXTI x configuration (x = 4 to 7)
0
4
EXTI5
EXTI x configuration (x = 4 to 7)
4
4
EXTI6
EXTI x configuration (x = 4 to 7)
8
4
EXTI7
EXTI x configuration (x = 4 to 7)
12
4
EXTICR3
EXTICR3
external interrupt configuration register 3
0x10
32
read-write
n
0x0
0x0
EXTI10
EXTI10
8
4
EXTI11
EXTI x configuration (x = 8 to 11)
12
4
EXTI8
EXTI x configuration (x = 8 to 11)
0
4
EXTI9
EXTI x configuration (x = 8 to 11)
4
4
EXTICR4
EXTICR4
external interrupt configuration register 4
0x14
32
read-write
n
0x0
0x0
EXTI12
EXTI x configuration (x = 12 to 15)
0
4
EXTI13
EXTI x configuration (x = 12 to 15)
4
4
EXTI14
EXTI x configuration (x = 12 to 15)
8
4
EXTI15
EXTI x configuration (x = 12 to 15)
12
4
MEMRM
MEMRM
memory remap register
0x0
32
read-write
n
0x0
0x0
MEM_MODE
MEM_MODE
0
2
PMC
PMC
peripheral mode configuration register
0x4
32
read-write
n
0x0
0x0
ADC1DC2
ADC1DC2
16
1
ADC2DC2
ADC2DC2
17
1
ADC3DC2
ADC3DC2
18
1
MII_RMII_SEL
Ethernet PHY interface selection
23
1
TIM1
Advanced-timers
TIM
0x0
0x0
0x400
registers
n
TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9 global interrupt
24
TIM1_UP_TIM10
TIM1 Update interrupt and TIM10 global interrupt
25
TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
26
TIM1_CC
TIM1 Capture Compare interrupt
27
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM10
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
UDIS
Update disable
1
1
URS
Update request source
2
1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
UIF
Update interrupt flag
0
1
TIM11
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (inputmode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
UDIS
Update disable
1
1
URS
Update request source
2
1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
UG
Update generation
0
1
OR
OR
option register
0x50
32
read-write
n
0x0
0x0
RMP
Input 1 remapping capability
0
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
UIF
Update interrupt flag
0
1
TIM12
General purpose timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
3
IC2F
Input capture 2 filter
12
3
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
TIE
Trigger interrupt enable
6
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM13
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM8_UP_TIM13
TIM8 Update interrupt and TIM13 global
interrupt
44
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
UDIS
Update disable
1
1
URS
Update request source
2
1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
UIF
Update interrupt flag
0
1
TIM14
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM8_TRG_COM_TIM14
TIM8 Trigger and Commutation interrupts and
TIM14 global interrupt
45
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
UDIS
Update disable
1
1
URS
Update request source
2
1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
UIF
Update interrupt flag
0
1
TIM2
General purpose timers
TIM
0x0
0x0
0x400
registers
n
TIM2
TIM2 global interrupt
28
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
CC2S
CC2S
8
2
OC1CE
OC1CE
7
1
OC1FE
OC1FE
2
1
OC1M
OC1M
4
3
OC1PE
OC1PE
3
1
OC2CE
OC2CE
15
1
OC2FE
OC2FE
10
1
OC2M
OC2M
12
3
OC2PE
OC2PE
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
CC3S
0
2
CC4S
CC4S
8
2
O24CE
O24CE
15
1
OC3CE
OC3CE
7
1
OC3FE
OC3FE
2
1
OC3M
OC3M
4
3
OC3PE
OC3PE
3
1
OC4FE
OC4FE
10
1
OC4M
OC4M
12
3
OC4PE
OC4PE
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM5 option register
0x50
32
read-write
n
0x0
0x0
ITR1_RMP
Timer Input 4 remap
10
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM3
General purpose timers
TIM
0x0
0x0
0x400
registers
n
TIM3
TIM3 global interrupt
29
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
CC2S
CC2S
8
2
OC1CE
OC1CE
7
1
OC1FE
OC1FE
2
1
OC1M
OC1M
4
3
OC1PE
OC1PE
3
1
OC2CE
OC2CE
15
1
OC2FE
OC2FE
10
1
OC2M
OC2M
12
3
OC2PE
OC2PE
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
CC3S
0
2
CC4S
CC4S
8
2
O24CE
O24CE
15
1
OC3CE
OC3CE
7
1
OC3FE
OC3FE
2
1
OC3M
OC3M
4
3
OC3PE
OC3PE
3
1
OC4FE
OC4FE
10
1
OC4M
OC4M
12
3
OC4PE
OC4PE
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM4
General purpose timers
TIM
0x0
0x0
0x400
registers
n
TIM4
TIM4 global interrupt
30
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
CC2S
CC2S
8
2
OC1CE
OC1CE
7
1
OC1FE
OC1FE
2
1
OC1M
OC1M
4
3
OC1PE
OC1PE
3
1
OC2CE
OC2CE
15
1
OC2FE
OC2FE
10
1
OC2M
OC2M
12
3
OC2PE
OC2PE
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
CC3S
0
2
CC4S
CC4S
8
2
O24CE
O24CE
15
1
OC3CE
OC3CE
7
1
OC3FE
OC3FE
2
1
OC3M
OC3M
4
3
OC3PE
OC3PE
3
1
OC4FE
OC4FE
10
1
OC4M
OC4M
12
3
OC4PE
OC4PE
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM5
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM5
TIM5 global interrupt
50
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
CC2S
CC2S
8
2
OC1CE
OC1CE
7
1
OC1FE
OC1FE
2
1
OC1M
OC1M
4
3
OC1PE
OC1PE
3
1
OC2CE
OC2CE
15
1
OC2FE
OC2FE
10
1
OC2M
OC2M
12
3
OC2PE
OC2PE
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
CC3S
0
2
CC4S
CC4S
8
2
O24CE
O24CE
15
1
OC3CE
OC3CE
7
1
OC3FE
OC3FE
2
1
OC3M
OC3M
4
3
OC3PE
OC3PE
3
1
OC4FE
OC4FE
10
1
OC4M
OC4M
12
3
OC4PE
OC4PE
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM5 option register
0x50
32
read-write
n
0x0
0x0
IT4_RMP
Timer Input 4 remap
6
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM6
Basic timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
TIM7
Basic timers
TIM
0x0
0x0
0x400
registers
n
TIM7
TIM7 global interrupt
55
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
TIM8
Advanced-timers
TIM
0x0
0x0
0x400
registers
n
TIM8_BRK_TIM12
TIM8 Break interrupt and TIM12 global
interrupt
43
TIM8_CC
TIM8 Capture Compare Interrupt
46
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM9
General purpose timers
TIM
0x0
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
3
IC2F
Input capture 2 filter
12
3
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
TIE
Trigger interrupt enable
6
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
UART4
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
UART4
Uart4 Interrupt
8
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
ONEBIT
One sample bit method enable
11
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
UART5
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
UART5
UART5 global interrupt
53
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
ONEBIT
One sample bit method enable
11
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
UART7
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
UART7
UART 7 global interrupt
82
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
UART8
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
UART8
UART 8 global interrupt
83
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1
USART1 global interrupt
37
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART2
USART2 global interrupt
38
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART3
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART3
USART3 global interrupt
39
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
USART6
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART6
USART6 global interrupt
71
BRR
BRR
Baud rate register
0x8
32
read-write
n
0x0
0x0
DIV_Fraction
fraction of USARTDIV
0
4
DIV_Mantissa
mantissa of USARTDIV
4
12
CR1
CR1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RWU
Receiver wakeup
1
1
RXNEIE
RXNE interrupt enable
5
1
SBK
Send break
0
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
TXE interrupt enable
7
1
UE
USART enable
13
1
WAKE
Wakeup method
11
1
CR2
CR2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADD
Address of the USART node
0
4
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOP
STOP bits
12
2
CR3
CR3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
RTSE
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DR
DR
Data register
0x4
32
read-write
n
0x0
0x0
DR
Data value
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
SR
SR
Status register
0x0
32
read-write
n
0x0
0x0
CTS
CTS flag
9
1
read-write
FE
Framing error
1
1
read-only
IDLE
IDLE line detected
4
1
read-only
LBD
LIN break detection flag
8
1
read-write
NF
Noise detected flag
2
1
read-only
ORE
Overrun error
3
1
read-only
PE
Parity error
0
1
read-only
RXNE
Read data register not empty
5
1
read-write
TC
Transmission complete
6
1
read-write
TXE
Transmit data register empty
7
1
read-only
WWDG
Window watchdog
WWDG
0x0
0x0
0x400
registers
n
WWDG
Window Watchdog interrupt
0
CFR
CFR
Configuration register
0x4
32
read-write
n
0x0
0x0
EWI
Early wakeup interrupt
9
1
W
7-bit window value
0
7
WDGTB0
Timer base
7
1
WDGTB1
Timer base
8
1
CR
CR
Control register
0x0
32
read-write
n
0x0
0x0
T
7-bit counter (MSB to LSB)
0
7
WDGA
Activation bit
7
1
SR
SR
Status register
0x8
32
read-write
n
0x0
0x0
EWIF
Early wakeup interrupt flag
0
1