STMicroelectronics
STM32G061K4Tx
2024.09.21
STM32G061K4Tx
Cortex-M0
r1p0
little
3
false
ADC
ADC address block description
ADC
0x40012400
0x0
0x400
registers
n
AWD1TR
ADC_AWD1TR
ADC watchdog threshold register
0x20
32
read-write
n
0xFFF0000
0xFFFFFFFF
HT1
Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
16
12
read-write
LT1
Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0
12
read-write
AWD2CR
ADC_AWD2CR
ADC Analog Watchdog 2 Configuration register
0xA0
32
read-write
n
0x0
0xFFFFFFFF
AWD2CH0
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH1
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
1
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH10
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
10
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH11
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
11
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH12
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
12
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH13
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
13
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH14
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
14
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH15
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
15
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH16
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
16
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH17
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
17
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH18
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
18
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH2
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
2
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH3
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
3
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH4
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
4
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH5
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
5
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH6
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
6
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH7
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
7
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH8
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
8
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2CH9
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
9
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD2
0x0
B_0x1
ADC analog channel-x is monitored by AWD2
0x1
AWD2TR
ADC_AWD2TR
ADC watchdog threshold register
0x24
32
read-write
n
0xFFF0000
0xFFFFFFFF
HT2
Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
16
12
read-write
LT2
Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0
12
read-write
AWD3CR
ADC_AWD3CR
ADC Analog Watchdog 3 Configuration register
0xA4
32
read-write
n
0x0
0xFFFFFFFF
AWD3CH0
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH1
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
1
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH10
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
10
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH11
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
11
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH12
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
12
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH13
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
13
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH14
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
14
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH15
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
15
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH16
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
16
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH17
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
17
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH18
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
18
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH2
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
2
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH3
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
3
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH4
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
4
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH5
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
5
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH6
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
6
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH7
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
7
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH8
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
8
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3CH9
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
9
1
read-write
B_0x0
ADC analog channel-x is not monitored by AWD3
0x0
B_0x1
ADC analog channel-x is monitored by AWD3
0x1
AWD3TR
ADC_AWD3TR
ADC watchdog threshold register
0x2C
32
read-write
n
0xFFF0000
0xFFFFFFFF
HT3
Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
16
12
read-write
LT3
Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0
12
read-write
CALFACT
ADC_CALFACT
ADC Calibration factor
0xB4
32
read-write
n
0x0
0xFFFFFFFF
CALFACT
Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.
0
7
read-write
CCR
ADC_CCR
ADC common configuration register
0x308
32
read-write
n
0x0
0xFFFFFFFF
PRESC
ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
18
4
read-write
B_0x0
input ADC clock not divided
0x0
B_0x1
input ADC clock divided by 2
0x1
B_0x2
input ADC clock divided by 4
0x2
B_0x3
input ADC clock divided by 6
0x3
B_0x4
input ADC clock divided by 8
0x4
B_0x5
input ADC clock divided by 10
0x5
B_0x6
input ADC clock divided by 12
0x6
B_0x7
input ADC clock divided by 16
0x7
B_0x8
input ADC clock divided by 32
0x8
B_0x9
input ADC clock divided by 64
0x9
B_0xA
input ADC clock divided by 128
0xA
B_0xB
input ADC clock divided by 256
0xB
TSEN
Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
23
1
read-write
B_0x0
Temperature sensor disabled, DAC_OUT1 connected to ADC channel 12
0x0
B_0x1
Temperature sensor enabled
0x1
VBATEN
VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)
24
1
read-write
B_0x0
VBAT channel disabled, DAC_OUT2 connected to ADC channel 14
0x0
B_0x1
VBAT channel enabled
0x1
VREFEN
VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
22
1
read-write
B_0x0
VREFINT disabled
0x0
B_0x1
VREFINT enabled
0x1
CFGR1
ADC_CFGR1
ADC configuration register 1
0xC
32
read-write
n
0x0
0xFFFFFFFF
ALIGN
Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 389 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
5
1
read-write
B_0x0
Right alignment
0x0
B_0x1
Left alignment
0x1
AUTOFF
Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
15
1
read-write
B_0x0
Auto-off mode disabled
0x0
B_0x1
Auto-off mode enabled
0x1
AWD1CH
Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
26
5
read-write
B_0x0
ADC analog input Channel 0 monitored by AWD
0x0
B_0x1
ADC analog input Channel 1 monitored by AWD
0x1
B_0x11
ADC analog input Channel 17 monitored by AWD
0x11
B_0x12
ADC analog input Channel 18 monitored by AWD
0x12
AWD1EN
Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
23
1
read-write
B_0x0
Analog watchdog 1 disabled
0x0
B_0x1
Analog watchdog 1 enabled
0x1
AWD1SGL
Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
22
1
read-write
B_0x0
Analog watchdog 1 enabled on all channels
0x0
B_0x1
Analog watchdog 1 enabled on a single channel
0x1
CHSELRMOD
Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
21
1
read-write
B_0x0
Each bit of the ADC_CHSELR register enables an input
0x0
B_0x1
ADC_CHSELR register is able to sequence up to 8 channels
0x1
CONT
Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
13
1
read-write
B_0x0
Single conversion mode
0x0
B_0x1
Continuous conversion mode
0x1
DISCEN
Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
16
1
read-write
B_0x0
Discontinuous mode disabled
0x0
B_0x1
Discontinuous mode enabled
0x1
DMACFG
Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 391 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
1
1
read-write
B_0x0
DMA one shot mode selected
0x0
B_0x1
DMA circular mode selected
0x1
DMAEN
Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0
1
read-write
B_0x0
DMA disabled
0x0
B_0x1
DMA enabled
0x1
EXTEN
External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
10
2
read-write
B_0x0
Hardware trigger detection disabled (conversions can be started by software)
0x0
B_0x1
Hardware trigger detection on the rising edge
0x1
B_0x2
Hardware trigger detection on the falling edge
0x2
B_0x3
Hardware trigger detection on both the rising and falling edges
0x3
EXTSEL
External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
6
3
read-write
B_0x0
TRG0
0x0
B_0x1
TRG1
0x1
B_0x2
TRG2
0x2
B_0x3
TRG3
0x3
B_0x4
TRG4
0x4
B_0x5
TRG5
0x5
B_0x6
TRG6
0x6
B_0x7
TRG7
0x7
OVRMOD
Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
12
1
read-write
B_0x0
ADC_DR register is preserved with the old data when an overrun is detected.
0x0
B_0x1
ADC_DR register is overwritten with the last conversion result when an overrun is detected.
0x1
RES
Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADENÂ =Â 0.
3
2
read-write
B_0x0
12 bits
0x0
B_0x1
10 bits
0x1
B_0x2
8 bits
0x2
B_0x3
6 bits
0x3
SCANDIR
Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
2
1
read-write
B_0x0
Upward scan (from CHSEL0 to CHSEL18)
0x0
B_0x1
Backward scan (from CHSEL18 to CHSEL0)
0x1
WAIT
Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
14
1
read-write
B_0x0
Wait conversion mode off
0x0
B_0x1
Wait conversion mode on
0x1
CFGR2
ADC_CFGR2
ADC configuration register 2
0x10
32
read-write
n
0x0
0xFFFFFFFF
CKMODE
ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
30
2
read-write
B_0x0
ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
0x0
B_0x1
PCLK/2 (Synchronous clock mode)
0x1
B_0x2
PCLK/4 (Synchronous clock mode)
0x2
B_0x3
PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)
0x3
LFTRIG
Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
29
1
read-write
B_0x0
Low Frequency Trigger Mode disabled
0x0
B_0x1
Low Frequency Trigger Mode enabled
0x1
OVSE
Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0
1
read-write
B_0x0
Oversampler disabled
0x0
B_0x1
Oversampler enabled
0x1
OVSR
Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
2
3
read-write
B_0x0
2x
0x0
B_0x1
4x
0x1
B_0x2
8x
0x2
B_0x3
16x
0x3
B_0x4
32x
0x4
B_0x5
64x
0x5
B_0x6
128x
0x6
B_0x7
256x
0x7
OVSS
Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
5
4
read-write
B_0x0
No shift
0x0
B_0x1
Shift 1-bit
0x1
B_0x2
Shift 2-bits
0x2
B_0x3
Shift 3-bits
0x3
B_0x4
Shift 4-bits
0x4
B_0x5
Shift 5-bits
0x5
B_0x6
Shift 6-bits
0x6
B_0x7
Shift 7-bits
0x7
B_0x8
Shift 8-bits
0x8
TOVS
Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
9
1
read-write
B_0x0
All oversampled conversions for a channel are done consecutively after a trigger
0x0
B_0x1
Each oversampled conversion for a channel needs a trigger
0x1
CHSELRMOD0
ADC_CHSELRMOD0
ADC channel selection register
0x28
32
read-write
n
0x0
0xFFFFFFFF
CHSEL0
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL1
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
1
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL10
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
10
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL11
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
11
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL12
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
12
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL13
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
13
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL14
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
14
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL15
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
15
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL16
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
16
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL17
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
17
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL18
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
18
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL2
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
2
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL3
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
3
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL4
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
4
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL5
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
5
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL6
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
6
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL7
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
7
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL8
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
8
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSEL9
Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
9
1
read-write
B_0x0
Input Channel-x is not selected for conversion
0x0
B_0x1
Input Channel-x is selected for conversion
0x1
CHSELRMOD1
ADC_CHSELRMOD1
ADC channel selection register
ADC_CHSELRMOD0
0x28
32
read-write
n
0x0
0xFFFFFFFF
SQ1
1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0
4
read-write
SQ2
2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
4
4
read-write
SQ3
3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
8
4
read-write
SQ4
4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
12
4
read-write
SQ5
5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
16
4
read-write
SQ6
6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
20
4
read-write
SQ7
7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
24
4
read-write
SQ8
8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
28
4
read-write
B_0x0
CH0
0x0
B_0x1
CH1
0x1
B_0xC
CH12
0xC
B_0xD
CH13
0xD
B_0xE
CH14
0xE
B_0xF
No channel selected (End of sequence)
0xF
CR
ADC_CR
ADC control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ADCAL
ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (ADC enabled and no conversion is ongoing).
31
1
read-write
B_0x0
Calibration complete
0x0
B_0x1
Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
0x1
ADDIS
ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1â is only effective when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)
1
1
read-write
B_0x0
No ADDIS command ongoing
0x0
B_0x1
Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
0x1
ADEN
ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCALÂ =Â 0, ADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)
0
1
read-write
B_0x0
ADC is disabled (OFF state)
0x0
B_0x1
Write 1 to enable the ADC.
0x1
ADSTART
ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONTÂ =Â 0, DISCENÂ =Â 0), when software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONTÂ =Â 0, DISCENÂ =Â 1), when the software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
2
1
read-write
B_0x0
No ADC conversion is ongoing.
0x0
B_0x1
Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
0x1
ADSTP
ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1â is only effective when ADSTARTÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
4
1
read-write
B_0x0
No ADC stop conversion command ongoing
0x0
B_0x1
Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
0x1
ADVREGEN
ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
28
1
read-write
B_0x0
ADC voltage regulator disabled
0x0
B_0x1
ADC voltage regulator enabled
0x1
DR
ADC_DR
ADC data register
0x40
32
read-only
n
0x0
0xFFFFFFFF
DATA
Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 389. Just after a calibration is complete, DATA[6:0] contains the calibration factor.
0
16
read-only
IER
ADC_IER
ADC interrupt enable register
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADRDYIE
ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0
1
read-write
B_0x0
ADRDY interrupt disabled.
0x0
B_0x1
ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
0x1
AWD1IE
Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
7
1
read-write
B_0x0
Analog watchdog interrupt disabled
0x0
B_0x1
Analog watchdog interrupt enabled
0x1
AWD2IE
Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
8
1
read-write
B_0x0
Analog watchdog interrupt disabled
0x0
B_0x1
Analog watchdog interrupt enabled
0x1
AWD3IE
Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
9
1
read-write
B_0x0
Analog watchdog interrupt disabled
0x0
B_0x1
Analog watchdog interrupt enabled
0x1
CCRDYIE
Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
13
1
read-write
B_0x0
Channel configuration ready interrupt disabled
0x0
B_0x1
Channel configuration ready interrupt enabled
0x1
EOCALIE
End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
11
1
read-write
B_0x0
End of calibration interrupt disabled
0x0
B_0x1
End of calibration interrupt enabled
0x1
EOCIE
End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
2
1
read-write
B_0x0
EOC interrupt disabled
0x0
B_0x1
EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
0x1
EOSIE
End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
3
1
read-write
B_0x0
EOS interrupt disabled
0x0
B_0x1
EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
0x1
EOSMPIE
End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
1
1
read-write
B_0x0
EOSMP interrupt disabled.
0x0
B_0x1
EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
0x1
OVRIE
Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
4
1
read-write
B_0x0
Overrun interrupt disabled
0x0
B_0x1
Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
0x1
ISR
ADC_ISR
ADC interrupt and status register
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADRDY
ADC ready This bit is set by hardware after the ADC has been enabled (ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
0
1
read-write
B_0x0
ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
ADC is ready to start conversion
0x1
AWD1
Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1.
7
1
read-write
B_0x0
No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
Analog watchdog event occurred
0x1
AWD2
Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.
8
1
read-write
B_0x0
No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
Analog watchdog event occurred
0x1
AWD3
Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.
9
1
read-write
B_0x0
No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
Analog watchdog event occurred
0x1
CCRDY
Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
13
1
read-write
B_0x0
Channel configuration update not applied.
0x0
B_0x1
Channel configuration update is applied.
0x1
EOC
End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
2
1
read-write
B_0x0
Channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
Channel conversion complete
0x1
EOCAL
End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
11
1
read-write
B_0x0
Calibration is not complete
0x0
B_0x1
Calibration is complete
0x1
EOS
End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
3
1
read-write
B_0x0
Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
Conversion sequence complete
0x1
EOSMP
End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1â.
1
1
read-write
B_0x0
Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
End of sampling phase reached
0x1
OVR
ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
4
1
read-write
B_0x0
No overrun occurred (or the flag event was already acknowledged and cleared by software)
0x0
B_0x1
Overrun has occurred
0x1
SMPR
ADC_SMPR
ADC sampling time register
0x14
32
read-write
n
0x0
0xFFFFFFFF
SMP1
Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0
3
read-write
B_0x0
1.5 ADC clock cycles
0x0
B_0x1
3.5 ADC clock cycles
0x1
B_0x2
7.5 ADC clock cycles
0x2
B_0x3
12.5 ADC clock cycles
0x3
B_0x4
19.5 ADC clock cycles
0x4
B_0x5
39.5 ADC clock cycles
0x5
B_0x6
79.5 ADC clock cycles
0x6
B_0x7
160.5 ADC clock cycles
0x7
SMP2
Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
4
3
read-write
B_0x0
1.5 ADC clock cycles
0x0
B_0x1
3.5 ADC clock cycles
0x1
B_0x2
7.5 ADC clock cycles
0x2
B_0x3
12.5 ADC clock cycles
0x3
B_0x4
19.5 ADC clock cycles
0x4
B_0x5
39.5 ADC clock cycles
0x5
B_0x6
79.5 ADC clock cycles
0x6
B_0x7
160.5 ADC clock cycles
0x7
SMPSEL0
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
8
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL1
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
9
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL10
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
18
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL11
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
19
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL12
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
20
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL13
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
21
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL14
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
22
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL15
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
23
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL16
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
24
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL17
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
25
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL18
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
26
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL2
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
10
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL3
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
11
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL4
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
12
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL5
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
13
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL6
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
14
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL7
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
15
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL8
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
16
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
SMPSEL9
Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
17
1
read-write
B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x0
B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
0x1
CRC
Cyclic redundancy check calculation unit
CRC
0x40023000
0x0
0x400
registers
n
CR
CRC_CR
Control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
POLYSIZE
Polynomial size These bits control the size of the polynomial.
3
2
read-write
B_0x0
32 bit polynomial
0x0
B_0x1
16 bit polynomial
0x1
B_0x2
8 bit polynomial
0x2
B_0x3
7 bit polynomial
0x3
RESET
RESET bit
0
1
write-only
REV_IN
Reverse input data These bits control the reversal of the bit order of the input data
5
2
read-write
B_0x0
Bit order not affected
0x0
B_0x1
Bit reversal done by byte
0x1
B_0x2
Bit reversal done by half-word
0x2
B_0x3
Bit reversal done by word
0x3
REV_OUT
Reverse output data This bit controls the reversal of the bit order of the output data.
7
1
read-write
B_0x0
Bit order not affected
0x0
B_0x1
Bit-reversed output format
0x1
DR
CRC_DR
Data register
0x0
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
DR
Data register bits
0
32
IDR
CRC_IDR
Independent data register
0x4
32
read-write
n
0x0
0xFFFFFFFF
IDR
General-purpose 32-bit data register bits
0
32
INIT
CRC_INIT
Initial CRC value
0x10
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
CRC_INIT
Programmable initial CRC value
0
32
POL
CRC_POL
polynomial
0x14
32
read-write
n
0x4C11DB7
0xFFFFFFFF
POL
Programmable polynomial
0
32
DAC
DAC
DAC
0x40007400
0x0
0x400
registers
n
CCR
DAC_CCR
DAC calibration control register
0x38
32
read-write
n
0x0
0xFFFFFFFF
OTRIM1
DAC channel1 offset trimming value
0
5
read-write
OTRIM2
DAC channel2 offset trimming value These bits are available only on dual-channel DACs. Refer to implementation.
16
5
read-write
CR
DAC_CR
DAC control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CEN1
DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.
14
1
read-write
B_0x0
DAC channel1 in Normal operating mode
0x0
B_0x1
DAC channel1 in calibration mode
0x1
CEN2
DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation.
30
1
read-write
B_0x0
DAC channel2 in Normal operating mode
0x0
B_0x1
DAC channel2 in calibration mode
0x1
DMAEN1
DAC channel1 DMA enable This bit is set and cleared by software.
12
1
read-write
B_0x0
DAC channel1 DMA mode disabled
0x0
B_0x1
DAC channel1 DMA mode enabled
0x1
DMAEN2
DAC channel2 DMA enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.
28
1
read-write
B_0x0
DAC channel2 DMA mode disabled
0x0
B_0x1
DAC channel2 DMA mode enabled
0x1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.
13
1
read-write
B_0x0
DAC channel1 DMA Underrun Interrupt disabled
0x0
B_0x1
DAC channel1 DMA Underrun Interrupt enabled
0x1
DMAUDRIE2
DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.
29
1
read-write
B_0x0
DAC channel2 DMA underrun interrupt disabled
0x0
B_0x1
DAC channel2 DMA underrun interrupt enabled
0x1
EN1
DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.
0
1
read-write
B_0x0
DAC channel1 disabled
0x0
B_0x1
DAC channel1 enabled
0x1
EN2
DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. Note: These bits are available only on dual-channel DACs. Refer to implementation.
16
1
read-write
B_0x0
DAC channel2 disabled
0x0
B_0x1
DAC channel2 enabled
0x1
MAMP1
DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
8
4
read-write
B_0x0
Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x0
B_0x1
Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x1
B_0x2
Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x2
B_0x3
Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x3
B_0x4
Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x4
B_0x5
Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x5
B_0x6
Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x6
B_0x7
Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x7
B_0x8
Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x8
B_0x9
Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0x9
B_0xA
Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
0xA
MAMP2
DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation.
24
4
read-write
B_0x0
Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x0
B_0x1
Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x1
B_0x2
Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x2
B_0x3
Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x3
B_0x4
Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x4
B_0x5
Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x5
B_0x6
Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x6
B_0x7
Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x7
B_0x8
Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x8
B_0x9
Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0x9
B_0xA
Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
0xA
TEN1
DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.
1
1
read-write
B_0x0
DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register
0x0
B_0x1
DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register
0x1
TEN2
DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation.
17
1
read-write
B_0x0
DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_pclk clock cycle later to the DAC_DOR2 register
0x0
B_0x1
DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_pclk clock cycles later to the DAC_DOR2 register
0x1
TSEL1
DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
2
4
read-write
B_0x0
SWTRIG1
0x0
B_0x1
dac_ch1_trg1
0x1
B_0x2
dac_ch1_trg2
0x2
B_0xF
dac_ch1_trg15
0xF
TSEL2
DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation.
18
4
read-write
B_0x0
SWTRIG2
0x0
B_0x1
dac_ch2_trg1
0x1
B_0x2
dac_ch2_trg2
0x2
B_0xF
dac_ch2_trg15
0xF
WAVE1
DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
6
2
read-write
B_0x0
wave generation disabled
0x0
B_0x1
Noise wave generation enabled
0x1
WAVE2
DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation.
22
2
read-write
B_0x0
wave generation disabled
0x0
B_0x1
Noise wave generation enabled
0x1
DHR12L1
DAC_DHR12L1
DAC channel1 12-bit left aligned data holding register
0xC
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1.
4
12
read-write
DHR12L2
DAC_DHR12L2
DAC channel2 12-bit left aligned data holding register
0x18
32
read-write
n
0x0
0xFFFFFFFF
DACC2DHR
DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.
4
12
read-write
DHR12LD
DAC_DHR12LD
DUAL DAC 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
4
12
read-write
DACC2DHR
DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
20
12
read-write
DHR12R1
DAC_DHR12R1
DAC channel1 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1.
0
12
read-write
DHR12R2
DAC_DHR12R2
DAC channel2 12-bit right aligned data holding register
0x14
32
read-write
n
0x0
0xFFFFFFFF
DACC2DHR
DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2.
0
12
read-write
DHR12RD
DAC_DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
0
12
read-write
DACC2DHR
DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
16
12
read-write
DHR8R1
DAC_DHR8R1
DAC channel1 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1.
0
8
read-write
DHR8R2
DAC_DHR8R2
DAC channel2 8-bit right-aligned data holding register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
DACC2DHR
DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
0
8
read-write
DHR8RD
DAC_DHR8RD
DUAL DAC 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
0
8
read-write
DACC2DHR
DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
8
8
read-write
DOR1
DAC_DOR1
DAC channel1 data output register
0x2C
32
read-only
n
0x0
0xFFFFFFFF
DACC1DOR
DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
0
12
read-only
DOR2
DAC_DOR2
DAC channel2 data output register
0x30
32
read-only
n
0x0
0xFFFFFFFF
DACC2DOR
DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.
0
12
read-only
MCR
DAC_MCR
DAC mode control register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
MODE1
DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample and hold mode Note: This register can be modified only when EN1=0.
0
3
read-write
B_0x0
DAC channel1 is connected to external pin with Buffer enabled
0x0
B_0x1
DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x1
B_0x2
DAC channel1 is connected to external pin with Buffer disabled
0x2
B_0x3
DAC channel1 is connected to on chip peripherals with Buffer disabled
0x3
B_0x4
DAC channel1 is connected to external pin with Buffer enabled
0x4
B_0x5
DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x5
B_0x6
DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled
0x6
B_0x7
DAC channel1 is connected to on chip peripherals with Buffer disabled
0x7
MODE2
DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel2 mode: DAC channel2 in Normal mode DAC channel2 in Sample and hold mode Note: This register can be modified only when EN2=0. Refer to for the availability of DAC channel2.
16
3
read-write
B_0x0
DAC channel2 is connected to external pin with Buffer enabled
0x0
B_0x1
DAC channel2 is connected to external pin and to on chip peripherals with buffer enabled
0x1
B_0x2
DAC channel2 is connected to external pin with buffer disabled
0x2
B_0x3
DAC channel2 is connected to on chip peripherals with Buffer disabled
0x3
B_0x4
DAC channel2 is connected to external pin with Buffer enabled
0x4
B_0x5
DAC channel2 is connected to external pin and to on chip peripherals with Buffer enabled
0x5
B_0x6
DAC channel2 is connected to external pin and to on chip peripherals with Buffer disabled
0x6
B_0x7
DAC channel2 is connected to on chip peripherals with Buffer disabled
0x7
SHHR
DAC_SHHR
DAC Sample and Hold hold time register
0x48
32
read-write
n
0x10001
0xFFFFFFFF
THOLD1
DAC channel1 hold time (only valid in Sample and hold mode) Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN1=0.
0
10
read-write
THOLD2
DAC channel2 hold time (only valid in Sample and hold mode). Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation.
16
10
read-write
SHRR
DAC_SHRR
DAC Sample and Hold refresh time register
0x4C
32
read-write
n
0x10001
0xFFFFFFFF
TREFRESH1
DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN1=0.
0
8
read-write
TREFRESH2
DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation.
16
8
read-write
SHSR1
DAC_SHSR1
DAC Sample and Hold sample time register 1
0x40
32
read-write
n
0x0
0xFFFFFFFF
TSAMPLE1
DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1=1, the write operation is ignored.
0
10
read-write
SHSR2
DAC_SHSR2
DAC Sample and Hold sample time register 2
0x44
32
read-write
n
0x0
0xFFFFFFFF
TSAMPLE2
DAC channel2 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is low, if BWST2=1, the write operation is ignored.
0
10
read-write
SR
DAC_SR
DAC status register
0x34
32
read-write
n
0x0
0xFFFFFFFF
BWST1
DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
15
1
read-only
B_0x0
There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
0x0
B_0x1
There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
0x1
BWST2
DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation.
31
1
read-only
B_0x0
There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
0x0
B_0x1
There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written
0x1
CAL_FLAG1
DAC channel1 calibration offset status This bit is set and cleared by hardware
14
1
read-only
B_0x0
calibration trimming value is lower than the offset correction value
0x0
B_0x1
calibration trimming value is equal or greater than the offset correction value
0x1
CAL_FLAG2
DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation.
30
1
read-only
B_0x0
calibration trimming value is lower than the offset correction value
0x0
B_0x1
calibration trimming value is equal or greater than the offset correction value
0x1
DMAUDR1
DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
13
1
read-write
B_0x0
No DMA underrun error condition occurred for DAC channel1
0x0
B_0x1
DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
0x1
DMAUDR2
DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation.
29
1
read-write
B_0x0
No DMA underrun error condition occurred for DAC channel2
0x0
B_0x1
DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate).
0x1
SWTRGR
DAC_SWTRGR
DAC software trigger register
0x4
32
write-only
n
0x0
0xFFFFFFFF
SWTRIG1
DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.
0
1
write-only
B_0x0
No trigger
0x0
B_0x1
Trigger
0x1
SWTRIG2
DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation.
1
1
write-only
B_0x0
No trigger
0x0
B_0x1
Trigger
0x1
DMAMUX
DMAMUX
DMAMUX
0x40020800
0x0
0x800
registers
n
DMA_Channel4_5_6_7
DMA channel 4, 5, 6 and 7 and DMAMUX
11
C0CR
DMAMUX_C0CR
DMAMUX request line multiplexer channel x configuration register
0x0
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0
6
read-write
EGE
Event generation enable
9
1
read-write
B_0x0
event generation disabled
0x0
B_0x1
event generation enabled
0x1
NBREQ
Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
19
5
read-write
SE
Synchronization enable
16
1
read-write
B_0x0
synchronization disabled
0x0
B_0x1
synchronization enabled
0x1
SOIE
Synchronization overrun interrupt enable
8
1
read-write
B_0x0
interrupt disabled
0x0
B_0x1
interrupt enabled
0x1
SPOL
Synchronization polarity Defines the edge polarity of the selected synchronization input:
17
2
read-write
B_0x0
no event, i.e. no synchronization nor detection.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
SYNC_ID
Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
24
5
read-write
C1CR
DMAMUX_C1CR
DMAMUX request line multiplexer channel x configuration register
0x4
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0
6
read-write
EGE
Event generation enable
9
1
read-write
B_0x0
event generation disabled
0x0
B_0x1
event generation enabled
0x1
NBREQ
Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
19
5
read-write
SE
Synchronization enable
16
1
read-write
B_0x0
synchronization disabled
0x0
B_0x1
synchronization enabled
0x1
SOIE
Synchronization overrun interrupt enable
8
1
read-write
B_0x0
interrupt disabled
0x0
B_0x1
interrupt enabled
0x1
SPOL
Synchronization polarity Defines the edge polarity of the selected synchronization input:
17
2
read-write
B_0x0
no event, i.e. no synchronization nor detection.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
SYNC_ID
Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
24
5
read-write
C2CR
DMAMUX_C2CR
DMAMUX request line multiplexer channel x configuration register
0x8
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0
6
read-write
EGE
Event generation enable
9
1
read-write
B_0x0
event generation disabled
0x0
B_0x1
event generation enabled
0x1
NBREQ
Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
19
5
read-write
SE
Synchronization enable
16
1
read-write
B_0x0
synchronization disabled
0x0
B_0x1
synchronization enabled
0x1
SOIE
Synchronization overrun interrupt enable
8
1
read-write
B_0x0
interrupt disabled
0x0
B_0x1
interrupt enabled
0x1
SPOL
Synchronization polarity Defines the edge polarity of the selected synchronization input:
17
2
read-write
B_0x0
no event, i.e. no synchronization nor detection.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
SYNC_ID
Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
24
5
read-write
C3CR
DMAMUX_C3CR
DMAMUX request line multiplexer channel x configuration register
0xC
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0
6
read-write
EGE
Event generation enable
9
1
read-write
B_0x0
event generation disabled
0x0
B_0x1
event generation enabled
0x1
NBREQ
Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
19
5
read-write
SE
Synchronization enable
16
1
read-write
B_0x0
synchronization disabled
0x0
B_0x1
synchronization enabled
0x1
SOIE
Synchronization overrun interrupt enable
8
1
read-write
B_0x0
interrupt disabled
0x0
B_0x1
interrupt enabled
0x1
SPOL
Synchronization polarity Defines the edge polarity of the selected synchronization input:
17
2
read-write
B_0x0
no event, i.e. no synchronization nor detection.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
SYNC_ID
Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
24
5
read-write
C4CR
DMAMUX_C4CR
DMAMUX request line multiplexer channel x configuration register
0x10
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0
6
read-write
EGE
Event generation enable
9
1
read-write
B_0x0
event generation disabled
0x0
B_0x1
event generation enabled
0x1
NBREQ
Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
19
5
read-write
SE
Synchronization enable
16
1
read-write
B_0x0
synchronization disabled
0x0
B_0x1
synchronization enabled
0x1
SOIE
Synchronization overrun interrupt enable
8
1
read-write
B_0x0
interrupt disabled
0x0
B_0x1
interrupt enabled
0x1
SPOL
Synchronization polarity Defines the edge polarity of the selected synchronization input:
17
2
read-write
B_0x0
no event, i.e. no synchronization nor detection.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
SYNC_ID
Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
24
5
read-write
C5CR
DMAMUX_C5CR
DMAMUX request line multiplexer channel x configuration register
0x14
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0
6
read-write
EGE
Event generation enable
9
1
read-write
B_0x0
event generation disabled
0x0
B_0x1
event generation enabled
0x1
NBREQ
Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
19
5
read-write
SE
Synchronization enable
16
1
read-write
B_0x0
synchronization disabled
0x0
B_0x1
synchronization enabled
0x1
SOIE
Synchronization overrun interrupt enable
8
1
read-write
B_0x0
interrupt disabled
0x0
B_0x1
interrupt enabled
0x1
SPOL
Synchronization polarity Defines the edge polarity of the selected synchronization input:
17
2
read-write
B_0x0
no event, i.e. no synchronization nor detection.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
SYNC_ID
Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
24
5
read-write
C6CR
DMAMUX_C6CR
DMAMUX request line multiplexer channel x configuration register
0x18
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0
6
read-write
EGE
Event generation enable
9
1
read-write
B_0x0
event generation disabled
0x0
B_0x1
event generation enabled
0x1
NBREQ
Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
19
5
read-write
SE
Synchronization enable
16
1
read-write
B_0x0
synchronization disabled
0x0
B_0x1
synchronization enabled
0x1
SOIE
Synchronization overrun interrupt enable
8
1
read-write
B_0x0
interrupt disabled
0x0
B_0x1
interrupt enabled
0x1
SPOL
Synchronization polarity Defines the edge polarity of the selected synchronization input:
17
2
read-write
B_0x0
no event, i.e. no synchronization nor detection.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
SYNC_ID
Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
24
5
read-write
CFR
DMAMUX_CFR
DMAMUX request line multiplexer interrupt clear flag register
0x84
32
write-only
n
0x0
0xFFFFFFFF
CSOF0
Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0
1
write-only
CSOF1
Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
1
1
write-only
CSOF2
Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
2
1
write-only
CSOF3
Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
3
1
write-only
CSOF4
Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
4
1
write-only
CSOF5
Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
5
1
write-only
CSOF6
Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
6
1
write-only
CSR
DMAMUX_CSR
DMAMUX request line multiplexer interrupt channel status register
0x80
32
read-only
n
0x0
0xFFFFFFFF
SOF0
Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0
1
read-only
SOF1
Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
1
1
read-only
SOF2
Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
2
1
read-only
SOF3
Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
3
1
read-only
SOF4
Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
4
1
read-only
SOF5
Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
5
1
read-only
SOF6
Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
6
1
read-only
RG0CR
DMAMUX_RG0CR
DMAMUX request generator channel x configuration register
0x100
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel x enable
16
1
read-write
B_0x0
DMA request generator channel x disabled
0x0
B_0x1
DMA request generator channel x enabled
0x1
GNBREQ
Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
19
5
read-write
GPOL
DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
17
2
read-write
B_0x0
no event. I.e. none trigger detection nor generation.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
OIE
Trigger overrun interrupt enable
8
1
read-write
B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x0
B_0x1
interrupt on a trigger overrun event occurrence is enabled
0x1
SIG_ID
Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0
5
read-write
RG1CR
DMAMUX_RG1CR
DMAMUX request generator channel x configuration register
0x104
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel x enable
16
1
read-write
B_0x0
DMA request generator channel x disabled
0x0
B_0x1
DMA request generator channel x enabled
0x1
GNBREQ
Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
19
5
read-write
GPOL
DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
17
2
read-write
B_0x0
no event. I.e. none trigger detection nor generation.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
OIE
Trigger overrun interrupt enable
8
1
read-write
B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x0
B_0x1
interrupt on a trigger overrun event occurrence is enabled
0x1
SIG_ID
Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0
5
read-write
RG2CR
DMAMUX_RG2CR
DMAMUX request generator channel x configuration register
0x108
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel x enable
16
1
read-write
B_0x0
DMA request generator channel x disabled
0x0
B_0x1
DMA request generator channel x enabled
0x1
GNBREQ
Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
19
5
read-write
GPOL
DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
17
2
read-write
B_0x0
no event. I.e. none trigger detection nor generation.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
OIE
Trigger overrun interrupt enable
8
1
read-write
B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x0
B_0x1
interrupt on a trigger overrun event occurrence is enabled
0x1
SIG_ID
Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0
5
read-write
RG3CR
DMAMUX_RG3CR
DMAMUX request generator channel x configuration register
0x10C
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel x enable
16
1
read-write
B_0x0
DMA request generator channel x disabled
0x0
B_0x1
DMA request generator channel x enabled
0x1
GNBREQ
Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
19
5
read-write
GPOL
DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
17
2
read-write
B_0x0
no event. I.e. none trigger detection nor generation.
0x0
B_0x1
rising edge
0x1
B_0x2
falling edge
0x2
B_0x3
rising and falling edge
0x3
OIE
Trigger overrun interrupt enable
8
1
read-write
B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x0
B_0x1
interrupt on a trigger overrun event occurrence is enabled
0x1
SIG_ID
Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0
5
read-write
RGCFR
DMAMUX_RGCFR
DMAMUX request generator interrupt clear flag register
0x144
32
write-only
n
0x0
0xFFFFFFFF
COF0
Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
0
1
write-only
COF1
Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
1
1
write-only
COF2
Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
2
1
write-only
COF3
Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
3
1
write-only
RGSR
DMAMUX_RGSR
DMAMUX request generator interrupt status register
0x140
32
read-only
n
0x0
0xFFFFFFFF
OF0
Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
0
1
read-only
OF1
Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
1
1
read-only
OF2
Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
2
1
read-only
OF3
Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
3
1
read-only
HDMI_CEC
HDMI-CEC
CEC
0x40007800
0x0
0x400
registers
n
CEC
CEC global interrupt
30
CEC_CFGR
CEC_CFGR
This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.
0x4
32
read-write
n
0x0
0xFFFFFFFF
BRDNOGEN
Avoid error-bit generation in broadcast The BRDNOGEN bit is set and cleared by software. error-bit on the CEC line. LBPE detection with LBPEGEN = 0 on a broadcast message generates an error-bit on the CEC line.
7
1
read-write
B_0x0
BRE detection with BRESTP = 1 and BREGEN = 0 on a broadcast message generates an
0x0
B_0x1
Error-bit is not generated in the same condition as above. An error-bit is not generated even in case of an SBPE detection in a broadcast message if listen mode is set.
0x1
BREGEN
Generate error-bit on bit rising error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon BRE detection with BRESTP = 1 in broadcast even if BREGEN = 0.
5
1
read-write
B_0x0
BRE detection does not generate an error-bit on the CEC line.
0x0
B_0x1
BRE detection generates an error-bit on the CEC line (if BRESTP is set).
0x1
BRESTP
Rx-stop on bit rising error The BRESTP bit is set and cleared by software.
4
1
read-write
B_0x0
BRE detection does not stop reception of the CEC message. Data bit is sampled at 1.05 ms.
0x0
B_0x1
BRE detection stops message reception.
0x1
LBPEGEN
Generate error-bit on long bit period error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon LBPE detection in broadcast even if LBPEGEN = 0.
6
1
read-write
B_0x0
LBPE detection does not generate an error-bit on the CEC line.
0x0
B_0x1
LBPE detection generates an error-bit on the CEC line.
0x1
LSTN
Listen mode LSTN bit is set and cleared by software.
31
1
read-write
B_0x0
CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.
0x0
B_0x1
CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.
0x1
OAR
Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN = 1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.
16
15
read-write
RXTOL
Rx-tolerance The RXTOL bit is set and cleared by software. Start-bit, +/- 200 µs rise, +/- 200 µs fall Data-bit: +/- 200 µs rise. +/- 350 µs fall Start-bit: +/- 400 µs rise, +/- 400 µs fall Data-bit: +/-300 µs rise, +/- 500 µs fall
3
1
read-write
B_0x0
Standard tolerance margin:
0x0
B_0x1
Extended tolerance
0x1
SFT
Signal free time SFT bits are set by software. In the SFT = 0x0 configuration, the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. 0x0 2.5 data-bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST = 1, TXERR = 1, TXUDR = 1 or TXACKE = 1) 4 data-bit periods if CEC is the new bus initiator 6 data-bit periods if CEC is the last bus initiator with successful transmission (TXEOM = 1)
0
3
read-write
B_0x1
0.5 nominal data bit periods
0x1
B_0x2
1.5 nominal data bit periods
0x2
B_0x3
2.5 nominal data bit periods
0x3
B_0x4
3.5 nominal data bit periods
0x4
B_0x5
4.5 nominal data bit periods
0x5
B_0x6
5.5 nominal data bit periods
0x6
B_0x7
6.5 nominal data bit periods
0x7
SFTOP
SFT option bit The SFTOPT bit is set and cleared by software.
8
1
read-write
B_0x0
SFT timer starts when TXSOM is set by software.
0x0
B_0x1
SFT timer starts automatically at the end of message transmission/reception.
0x1
CEC_CR
CEC_CR
CEC control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CECEN
CEC enable The CECEN bit is set and cleared by software. CECEN = 1 starts message reception and enables the TXSOM control. CECEN = 0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.
0
1
read-write
B_0x0
CEC peripheral is off.
0x0
B_0x1
CEC peripheral is on.
0x1
TXEOM
Tx end of message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN = 1. TXEOM must be set before writing transmission data to TXDR. If TXEOM is set when TXSOM = 0, transmitted message consists of 1 byte (HEADER) only (PING message).
2
1
read-write
B_0x0
TXDR data byte is transmitted with EOM = 0
0x0
B_0x1
TXDR data byte is transmitted with EOM = 1
0x1
TXSOM
Tx start of message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission starts after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND = 1), in case of transmission underrun (TXUDR = 1), negative acknowledge (TXACKE = 1), and transmission error (TXERR = 1). It is also cleared by CECEN = 0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST = 1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN = 1. TXSOM must be set when transmission data is available into TXDR. HEADER first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR that is used only for reception.
1
1
read-write
B_0x0
No CEC transmission is on-going
0x0
B_0x1
CEC transmission command
0x1
CEC_IER
CEC_IER
CEC interrupt enable register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ARBLSTIE
Arbitration lost interrupt enable The ARBLSTIE bit is set and cleared by software.
7
1
read-write
B_0x0
ARBLST interrupt disabled
0x0
B_0x1
ARBLST interrupt enabled
0x1
BREIE
Bit rising error interrupt enable The BREIE bit is set and cleared by software.
3
1
read-write
B_0x0
BRE interrupt disabled
0x0
B_0x1
BRE interrupt enabled
0x1
LBPEIE
Long bit period error interrupt enable The LBPEIE bit is set and cleared by software.
5
1
read-write
B_0x0
LBPE interrupt disabled
0x0
B_0x1
LBPE interrupt enabled
0x1
RXACKIE
Rx-missing acknowledge error interrupt enable The RXACKIE bit is set and cleared by software.
6
1
read-write
B_0x0
RXACKE interrupt disabled
0x0
B_0x1
RXACKE interrupt enabled
0x1
RXBRIE
Rx-byte received interrupt enable The RXBRIE bit is set and cleared by software.
0
1
read-write
B_0x0
RXBR interrupt disabled
0x0
B_0x1
RXBR interrupt enabled
0x1
RXENDIE
End of reception interrupt enable The RXENDIE bit is set and cleared by software.
1
1
read-write
B_0x0
RXEND interrupt disabled
0x0
B_0x1
RXEND interrupt enabled
0x1
RXOVRIE
Rx-buffer overrun interrupt enable The RXOVRIE bit is set and cleared by software.
2
1
read-write
B_0x0
RXOVR interrupt disabled
0x0
B_0x1
RXOVR interrupt enabled
0x1
SBPEIE
Short bit period error interrupt enable The SBPEIE bit is set and cleared by software.
4
1
read-write
B_0x0
SBPE interrupt disabled
0x0
B_0x1
SBPE interrupt enabled
0x1
TXACKIE
Tx-missing acknowledge error interrupt enable The TXACKEIE bit is set and cleared by software.
12
1
read-write
B_0x0
TXACKE interrupt disabled
0x0
B_0x1
TXACKE interrupt enabled
0x1
TXBRIE
Tx-byte request interrupt enable The TXBRIE bit is set and cleared by software.
8
1
read-write
B_0x0
TXBR interrupt disabled
0x0
B_0x1
TXBR interrupt enabled
0x1
TXENDIE
Tx-end of message interrupt enable The TXENDIE bit is set and cleared by software.
9
1
read-write
B_0x0
TXEND interrupt disabled
0x0
B_0x1
TXEND interrupt enabled
0x1
TXERRIE
Tx-error interrupt enable The TXERRIE bit is set and cleared by software.
11
1
read-write
B_0x0
TXERR interrupt disabled
0x0
B_0x1
TXERR interrupt enabled
0x1
TXUDRIE
Tx-underrun interrupt enable The TXUDRIE bit is set and cleared by software.
10
1
read-write
B_0x0
TXUDR interrupt disabled
0x0
B_0x1
TXUDR interrupt enabled
0x1
CEC_ISR
CEC_ISR
CEC Interrupt and Status Register
0x10
32
read-write
n
0x0
0xFFFFFFFF
ARBLST
Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1.
7
1
BRE
Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1.
3
1
LBPE
Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1.
5
1
RXACKE
Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1.
6
1
RXBR
Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1.
0
1
RXEND
End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1.
1
1
RXOVR
Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1.
2
1
SBPE
Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1.
4
1
TXACKE
Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1.
12
1
TXBR
Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1.
8
1
TXEND
End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1.
9
1
TXERR
Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1.
11
1
TXUDR
Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1
10
1
CEC_RXDR
CEC_RXDR
CEC Rx Data Register
0xC
32
read-only
n
0x0
0xFFFFFFFF
RXD
Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line.
0
8
CEC_TXDR
CEC_TXDR
CEC Tx data register
0x8
32
write-only
n
0x0
0xFFFFFFFF
TXD
Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1
0
8
I2C1
Inter-integrated circuit
I2C
0x40005400
0x0
0x400
registers
n
I2C1
I2C1 global interrupt
23
I2C_CR1
I2C_CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADDRIE
Address match Interrupt enable (slave only)
3
1
read-write
B_0x0
Address match (ADDR) interrupts disabled
0x0
B_0x1
Address match (ADDR) interrupts enabled
0x1
ALERTEN
SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
22
1
read-write
B_0x0
The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK).
0x0
B_0x1
The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK).
0x1
ANFOFF
Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
12
1
read-write
B_0x0
Analog noise filter enabled
0x0
B_0x1
Analog noise filter disabled
0x1
DNF
Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
8
4
read-write
B_0x0
Digital filter disabled
0x0
B_0x1
Digital filter enabled and filtering capability up to 1 tI2CCLK
0x1
B_0xF
digital filter enabled and filtering capability up to15 tI2CCLK
0xF
ERRIE
Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
7
1
read-write
B_0x0
Error detection interrupts disabled
0x0
B_0x1
Error detection interrupts enabled
0x1
GCEN
General call enable
19
1
read-write
B_0x0
General call disabled. Address 0b00000000 is NACKed.
0x0
B_0x1
General call enabled. Address 0b00000000 is ACKed.
0x1
NACKIE
Not acknowledge received Interrupt enable
4
1
read-write
B_0x0
Not acknowledge (NACKF) received interrupts disabled
0x0
B_0x1
Not acknowledge (NACKF) received interrupts enabled
0x1
NOSTRETCH
Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
17
1
read-write
B_0x0
Clock stretching enabled
0x0
B_0x1
Clock stretching disabled
0x1
PE
Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
0
1
read-write
B_0x0
Peripheral disable
0x0
B_0x1
Peripheral enable
0x1
PECEN
PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
23
1
read-write
B_0x0
PEC calculation disabled
0x0
B_0x1
PEC calculation enabled
0x1
RXDMAEN
DMA reception requests enable
15
1
read-write
B_0x0
DMA mode disabled for reception
0x0
B_0x1
DMA mode enabled for reception
0x1
RXIE
RX Interrupt enable
2
1
read-write
B_0x0
Receive (RXNE) interrupt disabled
0x0
B_0x1
Receive (RXNE) interrupt enabled
0x1
SBC
Slave byte control This bit is used to enable hardware byte control in slave mode.
16
1
read-write
B_0x0
Slave byte control disabled
0x0
B_0x1
Slave byte control enabled
0x1
SMBDEN
SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
21
1
read-write
B_0x0
Device Default Address disabled. Address 0b1100001x is NACKed.
0x0
B_0x1
Device Default Address enabled. Address 0b1100001x is ACKed.
0x1
SMBHEN
SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
20
1
read-write
B_0x0
Host Address disabled. Address 0b0001000x is NACKed.
0x0
B_0x1
Host Address enabled. Address 0b0001000x is ACKed.
0x1
STOPIE
Stop detection Interrupt enable
5
1
read-write
B_0x0
Stop detection (STOPF) interrupt disabled
0x0
B_0x1
Stop detection (STOPF) interrupt enabled
0x1
TCIE
Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
6
1
read-write
B_0x0
Transfer Complete interrupt disabled
0x0
B_0x1
Transfer Complete interrupt enabled
0x1
TXDMAEN
DMA transmission requests enable
14
1
read-write
B_0x0
DMA mode disabled for transmission
0x0
B_0x1
DMA mode enabled for transmission
0x1
TXIE
TX Interrupt enable
1
1
read-write
B_0x0
Transmit (TXIS) interrupt disabled
0x0
B_0x1
Transmit (TXIS) interrupt enabled
0x1
WUPEN
Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â
18
1
read-write
B_0x0
Wakeup from Stop mode disable.
0x0
B_0x1
Wakeup from Stop mode enable.
0x1
I2C_CR2
I2C_CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADD10
10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
11
1
read-write
B_0x0
The master operates in 7-bit addressing mode,
0x0
B_0x1
The master operates in 10-bit addressing mode
0x1
AUTOEND
Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
25
1
read-write
B_0x0
software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
0x0
B_0x1
Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.
0x1
HEAD10R
10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
12
1
read-write
B_0x0
The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
0x0
B_0x1
The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
0x1
NACK
NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
15
1
read-write
B_0x0
an ACK is sent after current received byte.
0x0
B_0x1
a NACK is sent after current received byte.
0x1
NBYTES
Number of bytes The number of bytes to be transmitted/received is programmed there. This field is donât care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
16
8
read-write
PECBYTE
Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
26
1
read-write
B_0x0
No PEC transfer.
0x0
B_0x1
PEC transmission/reception is requested
0x1
RD_WRN
Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
10
1
read-write
B_0x0
Master requests a write transfer.
0x0
B_0x1
Master requests a read transfer.
0x1
RELOAD
NBYTES reload mode This bit is set and cleared by software.
24
1
read-write
B_0x0
The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
0x0
B_0x1
The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.
0x1
SADD
Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0
10
read-write
START
Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
13
1
read-write
B_0x0
No Start generation.
0x0
B_0x1
Restart/Start generation:
0x1
STOP
Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0â to this bit has no effect.
14
1
read-write
B_0x0
No Stop generation.
0x0
B_0x1
Stop generation after current byte transfer.
0x1
I2C_ICR
I2C_ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0xFFFFFFFF
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
I2C_ISR
I2C_ISR
Interrupt and Status register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
16
1
read-only
B_0x0
Write transfer, slave enters receiver mode.
0x0
B_0x1
Read transfer, slave enters transmitter mode.
0x1
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
I2C_OAR1
I2C_OAR1
Own address register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
OA1
Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
0
10
read-write
OA1EN
Own Address 1 enable
15
1
read-write
B_0x0
Own address 1 disabled. The received slave address OA1 is NACKed.
0x0
B_0x1
Own address 1 enabled. The received slave address OA1 is ACKed.
0x1
OA1MODE
Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
10
1
read-write
B_0x0
Own address 1 is a 7-bit address.
0x0
B_0x1
Own address 1 is a 10-bit address.
0x1
I2C_OAR2
I2C_OAR2
Own address register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
OA2
Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
1
7
read-write
OA2EN
Own Address 2 enable
15
1
read-write
B_0x0
Own address 2 disabled. The received slave address OA2 is NACKed.
0x0
B_0x1
Own address 2 enabled. The received slave address OA2 is ACKed.
0x1
OA2MSK
Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
8
3
read-write
B_0x0
No mask
0x0
B_0x1
OA2[1] is masked and donât care. Only OA2[7:2] are compared.
0x1
B_0x2
OA2[2:1] are masked and donât care. Only OA2[7:3] are compared.
0x2
B_0x3
OA2[3:1] are masked and donât care. Only OA2[7:4] are compared.
0x3
B_0x4
OA2[4:1] are masked and donât care. Only OA2[7:5] are compared.
0x4
B_0x5
OA2[5:1] are masked and donât care. Only OA2[7:6] are compared.
0x5
B_0x6
OA2[6:1] are masked and donât care. Only OA2[7] is compared.
0x6
B_0x7
OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.
0x7
I2C_PECR
I2C_PECR
PEC register
0x20
32
read-only
n
0x0
0xFFFFFFFF
PEC
Packet error checking register
0
8
I2C_RXDR
I2C_RXDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RXDATA
8-bit receive data
0
8
I2C_TIMEOUTR
I2C_TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
TEXTEN
Extended clock timeout enable
31
1
read-write
B_0x0
Extended clock timeout detection is disabled
0x0
B_0x1
Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1).
0x1
TIDLE
Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
12
1
read-write
B_0x0
TIMEOUTA is used to detect SCL low timeout
0x0
B_0x1
TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
0x1
TIMEOUTA
Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
0
12
read-write
TIMEOUTB
Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
16
12
read-write
TIMOUTEN
Clock timeout enable
15
1
read-write
B_0x0
SCL timeout detection is disabled
0x0
B_0x1
SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1).
0x1
I2C_TIMINGR
I2C_TIMINGR
Timing register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
I2C_TXDR
I2C_TXDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TXDATA
8-bit transmit data
0
8
I2C2
Inter-integrated circuit
I2C
0x40005800
0x0
0x400
registers
n
I2C2
I2C2 global interrupt
24
I2C_CR1
I2C_CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADDRIE
Address match Interrupt enable (slave only)
3
1
read-write
B_0x0
Address match (ADDR) interrupts disabled
0x0
B_0x1
Address match (ADDR) interrupts enabled
0x1
ALERTEN
SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
22
1
read-write
B_0x0
The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK).
0x0
B_0x1
The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK).
0x1
ANFOFF
Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
12
1
read-write
B_0x0
Analog noise filter enabled
0x0
B_0x1
Analog noise filter disabled
0x1
DNF
Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
8
4
read-write
B_0x0
Digital filter disabled
0x0
B_0x1
Digital filter enabled and filtering capability up to 1 tI2CCLK
0x1
B_0xF
digital filter enabled and filtering capability up to15 tI2CCLK
0xF
ERRIE
Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
7
1
read-write
B_0x0
Error detection interrupts disabled
0x0
B_0x1
Error detection interrupts enabled
0x1
GCEN
General call enable
19
1
read-write
B_0x0
General call disabled. Address 0b00000000 is NACKed.
0x0
B_0x1
General call enabled. Address 0b00000000 is ACKed.
0x1
NACKIE
Not acknowledge received Interrupt enable
4
1
read-write
B_0x0
Not acknowledge (NACKF) received interrupts disabled
0x0
B_0x1
Not acknowledge (NACKF) received interrupts enabled
0x1
NOSTRETCH
Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
17
1
read-write
B_0x0
Clock stretching enabled
0x0
B_0x1
Clock stretching disabled
0x1
PE
Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
0
1
read-write
B_0x0
Peripheral disable
0x0
B_0x1
Peripheral enable
0x1
PECEN
PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
23
1
read-write
B_0x0
PEC calculation disabled
0x0
B_0x1
PEC calculation enabled
0x1
RXDMAEN
DMA reception requests enable
15
1
read-write
B_0x0
DMA mode disabled for reception
0x0
B_0x1
DMA mode enabled for reception
0x1
RXIE
RX Interrupt enable
2
1
read-write
B_0x0
Receive (RXNE) interrupt disabled
0x0
B_0x1
Receive (RXNE) interrupt enabled
0x1
SBC
Slave byte control This bit is used to enable hardware byte control in slave mode.
16
1
read-write
B_0x0
Slave byte control disabled
0x0
B_0x1
Slave byte control enabled
0x1
SMBDEN
SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
21
1
read-write
B_0x0
Device Default Address disabled. Address 0b1100001x is NACKed.
0x0
B_0x1
Device Default Address enabled. Address 0b1100001x is ACKed.
0x1
SMBHEN
SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
20
1
read-write
B_0x0
Host Address disabled. Address 0b0001000x is NACKed.
0x0
B_0x1
Host Address enabled. Address 0b0001000x is ACKed.
0x1
STOPIE
Stop detection Interrupt enable
5
1
read-write
B_0x0
Stop detection (STOPF) interrupt disabled
0x0
B_0x1
Stop detection (STOPF) interrupt enabled
0x1
TCIE
Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
6
1
read-write
B_0x0
Transfer Complete interrupt disabled
0x0
B_0x1
Transfer Complete interrupt enabled
0x1
TXDMAEN
DMA transmission requests enable
14
1
read-write
B_0x0
DMA mode disabled for transmission
0x0
B_0x1
DMA mode enabled for transmission
0x1
TXIE
TX Interrupt enable
1
1
read-write
B_0x0
Transmit (TXIS) interrupt disabled
0x0
B_0x1
Transmit (TXIS) interrupt enabled
0x1
WUPEN
Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â
18
1
read-write
B_0x0
Wakeup from Stop mode disable.
0x0
B_0x1
Wakeup from Stop mode enable.
0x1
I2C_CR2
I2C_CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADD10
10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
11
1
read-write
B_0x0
The master operates in 7-bit addressing mode,
0x0
B_0x1
The master operates in 10-bit addressing mode
0x1
AUTOEND
Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
25
1
read-write
B_0x0
software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
0x0
B_0x1
Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.
0x1
HEAD10R
10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
12
1
read-write
B_0x0
The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
0x0
B_0x1
The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
0x1
NACK
NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
15
1
read-write
B_0x0
an ACK is sent after current received byte.
0x0
B_0x1
a NACK is sent after current received byte.
0x1
NBYTES
Number of bytes The number of bytes to be transmitted/received is programmed there. This field is donât care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
16
8
read-write
PECBYTE
Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to .
26
1
read-write
B_0x0
No PEC transfer.
0x0
B_0x1
PEC transmission/reception is requested
0x1
RD_WRN
Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
10
1
read-write
B_0x0
Master requests a write transfer.
0x0
B_0x1
Master requests a read transfer.
0x1
RELOAD
NBYTES reload mode This bit is set and cleared by software.
24
1
read-write
B_0x0
The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
0x0
B_0x1
The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.
0x1
SADD
Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0
10
read-write
START
Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
13
1
read-write
B_0x0
No Start generation.
0x0
B_0x1
Restart/Start generation:
0x1
STOP
Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0â to this bit has no effect.
14
1
read-write
B_0x0
No Stop generation.
0x0
B_0x1
Stop generation after current byte transfer.
0x1
I2C_ICR
I2C_ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0xFFFFFFFF
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
I2C_ISR
I2C_ISR
Interrupt and Status register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
16
1
read-only
B_0x0
Write transfer, slave enters receiver mode.
0x0
B_0x1
Read transfer, slave enters transmitter mode.
0x1
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
I2C_OAR1
I2C_OAR1
Own address register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
OA1
Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
0
10
read-write
OA1EN
Own Address 1 enable
15
1
read-write
B_0x0
Own address 1 disabled. The received slave address OA1 is NACKed.
0x0
B_0x1
Own address 1 enabled. The received slave address OA1 is ACKed.
0x1
OA1MODE
Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
10
1
read-write
B_0x0
Own address 1 is a 7-bit address.
0x0
B_0x1
Own address 1 is a 10-bit address.
0x1
I2C_OAR2
I2C_OAR2
Own address register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
OA2
Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
1
7
read-write
OA2EN
Own Address 2 enable
15
1
read-write
B_0x0
Own address 2 disabled. The received slave address OA2 is NACKed.
0x0
B_0x1
Own address 2 enabled. The received slave address OA2 is ACKed.
0x1
OA2MSK
Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
8
3
read-write
B_0x0
No mask
0x0
B_0x1
OA2[1] is masked and donât care. Only OA2[7:2] are compared.
0x1
B_0x2
OA2[2:1] are masked and donât care. Only OA2[7:3] are compared.
0x2
B_0x3
OA2[3:1] are masked and donât care. Only OA2[7:4] are compared.
0x3
B_0x4
OA2[4:1] are masked and donât care. Only OA2[7:5] are compared.
0x4
B_0x5
OA2[5:1] are masked and donât care. Only OA2[7:6] are compared.
0x5
B_0x6
OA2[6:1] are masked and donât care. Only OA2[7] is compared.
0x6
B_0x7
OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.
0x7
I2C_PECR
I2C_PECR
PEC register
0x20
32
read-only
n
0x0
0xFFFFFFFF
PEC
Packet error checking register
0
8
I2C_RXDR
I2C_RXDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RXDATA
8-bit receive data
0
8
I2C_TIMEOUTR
I2C_TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
TEXTEN
Extended clock timeout enable
31
1
read-write
B_0x0
Extended clock timeout detection is disabled
0x0
B_0x1
Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1).
0x1
TIDLE
Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
12
1
read-write
B_0x0
TIMEOUTA is used to detect SCL low timeout
0x0
B_0x1
TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
0x1
TIMEOUTA
Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
0
12
read-write
TIMEOUTB
Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
16
12
read-write
TIMOUTEN
Clock timeout enable
15
1
read-write
B_0x0
SCL timeout detection is disabled
0x0
B_0x1
SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1).
0x1
I2C_TIMINGR
I2C_TIMINGR
Timing register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
I2C_TXDR
I2C_TXDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TXDATA
8-bit transmit data
0
8
IWDG
Independent watchdog
IWDG
0x40003000
0x0
0x400
registers
n
KR
IWDG_KR
Key register
0x0
32
write-only
n
0x0
0xFFFFFFFF
KEY
Key value (write only, read 0x0000)
0
16
PR
IWDG_PR
Prescaler register
0x4
32
read-write
n
0x0
0xFFFFFFFF
PR
Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset.
0
3
read-write
B_0x0
divider /4
0x0
B_0x1
divider /8
0x1
B_0x2
divider /16
0x2
B_0x3
divider /32
0x3
B_0x4
divider /64
0x4
B_0x5
divider /128
0x5
B_0x6
divider /256
0x6
B_0x7
divider /256
0x7
RLR
IWDG_RLR
Reload register
0x8
32
read-write
n
0xFFF
0xFFFFFFFF
RL
Watchdog counter reload value
0
12
SR
IWDG_SR
Status register
0xC
32
read-only
n
0x0
0xFFFFFFFF
PVU
Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset.
0
1
read-only
RVU
Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset.
1
1
read-only
WVU
Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset.
2
1
read-only
WINR
IWDG_WINR
Window register
0x10
32
read-write
n
0xFFF
0xFFFFFFFF
WIN
Watchdog counter window value
0
12
LPTIM1
Low power timer
LPTIM
0x40007C00
0x0
0x400
registers
n
LPTIM_ARR
LPTIM_ARR
Autoreload Register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ARR
Auto reload value
0
16
LPTIM_CFGR
LPTIM_CFGR
Configuration Register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CKFLT
Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature
3
2
read-write
B_0x0
any external clock signal level change is considered as a valid transition
0x0
B_0x1
external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition.
0x1
B_0x2
external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition.
0x2
B_0x3
external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition.
0x3
CKPOL
Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.
1
2
read-write
B_0x0
the rising edge is the active edge used for counting.
0x0
B_0x1
the falling edge is the active edge used for counting
0x1
B_0x2
both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
0x2
B_0x3
not allowed
0x3
CKSEL
Clock selector The CKSEL bit selects which clock source the LPTIM will use:
0
1
read-write
B_0x0
LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
0x0
B_0x1
LPTIM is clocked by an external clock source through the LPTIM external Input1
0x1
COUNTMODE
counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
23
1
read-write
B_0x0
the counter is incremented following each internal clock pulse
0x0
B_0x1
the counter is incremented following each valid clock pulse on the LPTIM external Input1
0x1
ENC
Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
24
1
read-write
B_0x0
Encoder mode disabled
0x0
B_0x1
Encoder mode enabled
0x1
PRELOAD
Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality
22
1
read-write
B_0x0
Registers are updated after each APB bus write access
0x0
B_0x1
Registers are updated at the end of the current LPTIM period
0x1
PRESC
Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:
9
3
read-write
B_0x0
/1
0x0
B_0x1
/2
0x1
B_0x2
/4
0x2
B_0x3
/8
0x3
B_0x4
/16
0x4
B_0x5
/32
0x5
B_0x6
/64
0x6
B_0x7
/128
0x7
TIMOUT
Timeout enable The TIMOUT bit controls the Timeout feature
19
1
read-write
B_0x0
A trigger event arriving when the timer is already started will be ignored
0x0
B_0x1
A trigger event arriving when the timer is already started will reset and restart the counter
0x1
TRGFLT
Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature
6
2
read-write
B_0x0
any trigger active level change is considered as a valid trigger
0x0
B_0x1
trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger.
0x1
B_0x2
trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.
0x2
B_0x3
trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger.
0x3
TRIGEN
Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:
17
2
read-write
B_0x0
software trigger (counting start is initiated by software)
0x0
B_0x1
rising edge is the active edge
0x1
B_0x2
falling edge is the active edge
0x2
B_0x3
both edges are active edges
0x3
TRIGSEL
Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details.
13
3
read-write
B_0x0
lptim_ext_trig0
0x0
B_0x1
lptim_ext_trig1
0x1
B_0x2
lptim_ext_trig2
0x2
B_0x3
lptim_ext_trig3
0x3
B_0x4
lptim_ext_trig4
0x4
B_0x5
lptim_ext_trig5
0x5
B_0x6
lptim_ext_trig6
0x6
B_0x7
lptim_ext_trig7
0x7
WAVE
Waveform shape The WAVE bit controls the output shape
20
1
read-write
B_0x0
Deactivate Set-once mode, PWM or One Pulse waveform depending on how the timer was started, CNTSTRT for PWM or SNGSTRT for One Pulse waveform.
0x0
B_0x1
Activate the Set-once mode
0x1
WAVPOL
Waveform shape polarity The WAVEPOL bit controls the output polarity
21
1
read-write
B_0x0
The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP registers
0x0
B_0x1
The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers
0x1
LPTIM_CFGR2
LPTIM_CFGR2
LPTIM configuration register 2
0x24
32
read-write
n
0x0
0xFFFFFFFF
IN1SEL
LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to .
0
2
read-write
B_0x0
lptim_in1_mux0
0x0
B_0x1
lptim_in1_mux1
0x1
B_0x2
lptim_in1_mux2
0x2
B_0x3
lptim_in1_mux3
0x3
IN2SEL
LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to .
4
2
read-write
B_0x0
lptim_in2_mux0
0x0
B_0x1
lptim_in2_mux1
0x1
B_0x2
lptim_in2_mux2
0x2
B_0x3
lptim_in2_mux3
0x3
LPTIM_CMP
LPTIM_CMP
Compare Register
0x14
32
read-write
n
0x0
0xFFFFFFFF
CMP
Compare value
0
16
LPTIM_CNT
LPTIM_CNT
Counter Register
0x1C
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
16
LPTIM_CR
LPTIM_CR
Control Register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CNTSTRT
Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
2
1
read-write
COUNTRST
Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.
3
1
read-write
ENABLE
LPTIM enable The ENABLE bit is set and cleared by software.
0
1
read-write
B_0x0
LPTIM is disabled
0x0
B_0x1
LPTIM is enabled
0x1
RSTARE
Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.
4
1
read-write
SNGSTRT
LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
1
1
read-write
LPTIM_ICR
LPTIM_ICR
Interrupt Clear Register
0x4
32
write-only
n
0x0
0xFFFFFFFF
ARRMCF
Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register
1
1
write-only
ARROKCF
Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register
4
1
write-only
CMPMCF
Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register
0
1
write-only
CMPOKCF
Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register
3
1
write-only
DOWNCF
Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
6
1
write-only
EXTTRIGCF
External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register
2
1
write-only
UPCF
Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
5
1
write-only
LPTIM_IER
LPTIM_IER
Interrupt Enable Register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ARRMIE
Autoreload match Interrupt Enable
1
1
read-write
B_0x0
ARRM interrupt disabled
0x0
B_0x1
ARRM interrupt enabled
0x1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
read-write
B_0x0
ARROK interrupt disabled
0x0
B_0x1
ARROK interrupt enabled
0x1
CMPMIE
Compare match Interrupt Enable
0
1
read-write
B_0x0
CMPM interrupt disabled
0x0
B_0x1
CMPM interrupt enabled
0x1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
read-write
B_0x0
CMPOK interrupt disabled
0x0
B_0x1
CMPOK interrupt enabled
0x1
DOWNIE
Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
6
1
read-write
B_0x0
DOWN interrupt disabled
0x0
B_0x1
DOWN interrupt enabled
0x1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
read-write
B_0x0
EXTTRIG interrupt disabled
0x0
B_0x1
EXTTRIG interrupt enabled
0x1
UPIE
Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
5
1
read-write
B_0x0
UP interrupt disabled
0x0
B_0x1
UP interrupt enabled
0x1
LPTIM_ISR
LPTIM_ISR
Interrupt and Status Register
0x0
32
read-only
n
0x0
0xFFFFFFFF
ARRM
Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT registerâs value reached the LPTIM_ARR registerâs value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
1
1
read-only
ARROK
Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
4
1
read-only
CMPM
Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP registerâs value.
0
1
read-only
CMPOK
Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed.
3
1
read-only
DOWN
Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
6
1
read-only
EXTTRIG
External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
2
1
read-only
UP
Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
5
1
read-only
LPTIM2
Low power timer
LPTIM
0x40009400
0x0
0x400
registers
n
LPTIM_ARR
LPTIM_ARR
Autoreload Register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ARR
Auto reload value
0
16
LPTIM_CFGR
LPTIM_CFGR
Configuration Register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CKFLT
Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature
3
2
read-write
B_0x0
any external clock signal level change is considered as a valid transition
0x0
B_0x1
external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition.
0x1
B_0x2
external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition.
0x2
B_0x3
external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition.
0x3
CKPOL
Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.
1
2
read-write
B_0x0
the rising edge is the active edge used for counting.
0x0
B_0x1
the falling edge is the active edge used for counting
0x1
B_0x2
both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
0x2
B_0x3
not allowed
0x3
CKSEL
Clock selector The CKSEL bit selects which clock source the LPTIM will use:
0
1
read-write
B_0x0
LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
0x0
B_0x1
LPTIM is clocked by an external clock source through the LPTIM external Input1
0x1
COUNTMODE
counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
23
1
read-write
B_0x0
the counter is incremented following each internal clock pulse
0x0
B_0x1
the counter is incremented following each valid clock pulse on the LPTIM external Input1
0x1
ENC
Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
24
1
read-write
B_0x0
Encoder mode disabled
0x0
B_0x1
Encoder mode enabled
0x1
PRELOAD
Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality
22
1
read-write
B_0x0
Registers are updated after each APB bus write access
0x0
B_0x1
Registers are updated at the end of the current LPTIM period
0x1
PRESC
Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:
9
3
read-write
B_0x0
/1
0x0
B_0x1
/2
0x1
B_0x2
/4
0x2
B_0x3
/8
0x3
B_0x4
/16
0x4
B_0x5
/32
0x5
B_0x6
/64
0x6
B_0x7
/128
0x7
TIMOUT
Timeout enable The TIMOUT bit controls the Timeout feature
19
1
read-write
B_0x0
A trigger event arriving when the timer is already started will be ignored
0x0
B_0x1
A trigger event arriving when the timer is already started will reset and restart the counter
0x1
TRGFLT
Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature
6
2
read-write
B_0x0
any trigger active level change is considered as a valid trigger
0x0
B_0x1
trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger.
0x1
B_0x2
trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.
0x2
B_0x3
trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger.
0x3
TRIGEN
Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:
17
2
read-write
B_0x0
software trigger (counting start is initiated by software)
0x0
B_0x1
rising edge is the active edge
0x1
B_0x2
falling edge is the active edge
0x2
B_0x3
both edges are active edges
0x3
TRIGSEL
Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details.
13
3
read-write
B_0x0
lptim_ext_trig0
0x0
B_0x1
lptim_ext_trig1
0x1
B_0x2
lptim_ext_trig2
0x2
B_0x3
lptim_ext_trig3
0x3
B_0x4
lptim_ext_trig4
0x4
B_0x5
lptim_ext_trig5
0x5
B_0x6
lptim_ext_trig6
0x6
B_0x7
lptim_ext_trig7
0x7
WAVE
Waveform shape The WAVE bit controls the output shape
20
1
read-write
B_0x0
Deactivate Set-once mode, PWM or One Pulse waveform depending on how the timer was started, CNTSTRT for PWM or SNGSTRT for One Pulse waveform.
0x0
B_0x1
Activate the Set-once mode
0x1
WAVPOL
Waveform shape polarity The WAVEPOL bit controls the output polarity
21
1
read-write
B_0x0
The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP registers
0x0
B_0x1
The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers
0x1
LPTIM_CFGR2
LPTIM_CFGR2
LPTIM configuration register 2
0x24
32
read-write
n
0x0
0xFFFFFFFF
IN1SEL
LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to .
0
2
read-write
B_0x0
lptim_in1_mux0
0x0
B_0x1
lptim_in1_mux1
0x1
B_0x2
lptim_in1_mux2
0x2
B_0x3
lptim_in1_mux3
0x3
IN2SEL
LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to .
4
2
read-write
B_0x0
lptim_in2_mux0
0x0
B_0x1
lptim_in2_mux1
0x1
B_0x2
lptim_in2_mux2
0x2
B_0x3
lptim_in2_mux3
0x3
LPTIM_CMP
LPTIM_CMP
Compare Register
0x14
32
read-write
n
0x0
0xFFFFFFFF
CMP
Compare value
0
16
LPTIM_CNT
LPTIM_CNT
Counter Register
0x1C
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
16
LPTIM_CR
LPTIM_CR
Control Register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CNTSTRT
Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
2
1
read-write
COUNTRST
Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.
3
1
read-write
ENABLE
LPTIM enable The ENABLE bit is set and cleared by software.
0
1
read-write
B_0x0
LPTIM is disabled
0x0
B_0x1
LPTIM is enabled
0x1
RSTARE
Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.
4
1
read-write
SNGSTRT
LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
1
1
read-write
LPTIM_ICR
LPTIM_ICR
Interrupt Clear Register
0x4
32
write-only
n
0x0
0xFFFFFFFF
ARRMCF
Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register
1
1
write-only
ARROKCF
Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register
4
1
write-only
CMPMCF
Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register
0
1
write-only
CMPOKCF
Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register
3
1
write-only
DOWNCF
Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
6
1
write-only
EXTTRIGCF
External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register
2
1
write-only
UPCF
Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
5
1
write-only
LPTIM_IER
LPTIM_IER
Interrupt Enable Register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ARRMIE
Autoreload match Interrupt Enable
1
1
read-write
B_0x0
ARRM interrupt disabled
0x0
B_0x1
ARRM interrupt enabled
0x1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
read-write
B_0x0
ARROK interrupt disabled
0x0
B_0x1
ARROK interrupt enabled
0x1
CMPMIE
Compare match Interrupt Enable
0
1
read-write
B_0x0
CMPM interrupt disabled
0x0
B_0x1
CMPM interrupt enabled
0x1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
read-write
B_0x0
CMPOK interrupt disabled
0x0
B_0x1
CMPOK interrupt enabled
0x1
DOWNIE
Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
6
1
read-write
B_0x0
DOWN interrupt disabled
0x0
B_0x1
DOWN interrupt enabled
0x1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
read-write
B_0x0
EXTTRIG interrupt disabled
0x0
B_0x1
EXTTRIG interrupt enabled
0x1
UPIE
Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
5
1
read-write
B_0x0
UP interrupt disabled
0x0
B_0x1
UP interrupt enabled
0x1
LPTIM_ISR
LPTIM_ISR
Interrupt and Status Register
0x0
32
read-only
n
0x0
0xFFFFFFFF
ARRM
Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT registerâs value reached the LPTIM_ARR registerâs value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
1
1
read-only
ARROK
Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
4
1
read-only
CMPM
Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP registerâs value.
0
1
read-only
CMPOK
Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed.
3
1
read-only
DOWN
Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
6
1
read-only
EXTTRIG
External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
2
1
read-only
UP
Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
5
1
read-only
TIM1
Advanced-timers
TIM
0x40012C00
0x0
0x400
registers
n
TIM1_BRK_UP_TRG_COM
TIM1 break, update, trigger
13
TIM1_CC
TIM1 Capture Compare interrupt
14
AF1
TIM1_AF1
DMA address for full transfer
0x60
32
read-write
n
0x1
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1
1
read-write
B_0x0
COMP1 input disabled
0x0
B_0x1
COMP1 input enabled
0x1
BKCMP1P
BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x0
B_0x1
COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1)
0x1
BKCMP2E
BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2
1
read-write
B_0x0
COMP2 input disabled
0x0
B_0x1
COMP2 input enabled
0x1
BKCMP2P
BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x0
B_0x1
COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1)
0x1
BKINE
BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0
1
read-write
B_0x0
BKIN input disabled
0x0
B_0x1
BKIN input enabled
0x1
BKINP
BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x0
B_0x1
BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1)
0x1
ETRSEL
ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
14
4
read-write
B_0x0
ETR legacy mode
0x0
B_0x1
COMP1 output
0x1
B_0x2
COMP2 output
0x2
B_0x3
ADC1 AWD1
0x3
B_0x4
ADC1 AWD2
0x4
B_0x5
ADC1 AWD3
0x5
AF2
TIM1_AF2
DMA address for full transfer
0x64
32
read-write
n
0x1
0xFFFFFFFF
BK2CMP1E
BRK2 COMP1 enable This bit enables the COMP1 for the timerâs BRK2 input. COMP1 output is 'ORedâ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1
1
read-write
B_0x0
COMP1 input disabled
0x0
B_0x1
COMP1 input enabled
0x1
BK2CMP1P
BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x0
B_0x1
COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
0x1
BK2CMP2E
BRK2 COMP2 enable This bit enables the COMP2 for the timerâs BRK2 input. COMP2 output is 'ORedâ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2
1
read-write
B_0x0
COMP2 input disabled
0x0
B_0x1
COMP2 input enabled
0x1
BK2CMP2P
BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
COMP2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x0
B_0x1
COMP2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
0x1
BK2INE
BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timerâs BRK2 input. BKIN2 input is 'ORedâ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0
1
read-write
B_0x0
BKIN2 input disabled
0x0
B_0x1
BKIN2 input enabled
0x1
BK2INP
BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x0
B_0x1
BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
0x1
ARR
TIM1_ARR
auto-reload register
0x2C
32
read-write
n
0xFFFF
0xFFFFFFFF
ARR
Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0
16
read-write
BDTR
TIM1_BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
14
1
read-write
B_0x0
MOE can be set only by software
0x0
B_0x1
MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
0x1
BK2BID
Break2 bidirectional Refer to BKBID description
29
1
read-write
BK2DSRM
Break2 Disarm Refer to BKDSRM description
27
1
read-write
BK2E
Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
24
1
read-write
B_0x0
Break input BRK2 disabled
0x0
B_0x1
Break input BRK2 enabled
0x1
BK2F
Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
20
4
read-write
B_0x0
No filter, BRK2 acts asynchronously
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
BK2P
Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
25
1
read-write
B_0x0
Break input BRK2 is active low
0x0
B_0x1
Break input BRK2 is active high
0x1
BKBID
Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
28
1
read-write
B_0x0
Break input BRK in input mode
0x0
B_0x1
Break input BRK in bidirectional mode
0x1
BKDSRM
Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
26
1
read-write
B_0x0
Break input BRK is armed
0x0
B_0x1
Break input BRK is disarmed
0x1
BKE
Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
12
1
read-write
B_0x0
Break function disabled
0x0
B_0x1
Break function enabled
0x1
BKF
Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
16
4
read-write
B_0x0
No filter, BRK acts asynchronously
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
BKP
Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
13
1
read-write
B_0x0
Break input BRK is active low
0x0
B_0x1
Break input BRK is active high
0x1
DTG
Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tDTG with tDTG=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtDTG with tDTG=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtDTG with tDTG=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtDTG with tDTG=16xtDTS. Example if tDTS=125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0
8
read-write
LOCK
Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
8
2
read-write
B_0x0
LOCK OFF - No bit is write protected.
0x0
B_0x1
LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written.
0x1
B_0x2
LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x2
B_0x3
LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
0x3
MOE
Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A).
15
1
read-write
B_0x0
In response to a break 2 event. OC and OCN outputs are disabled
0x0
B_0x1
OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).
0x1
OSSI
Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state).
0x0
B_0x1
When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output.
0x1
OSSR
Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state).
0x0
B_0x1
When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
0x1
CCER
TIM1_CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated.
0
1
read-write
B_0x0
Capture mode disabled / OC1 is not active (see below)
0x0
B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
0x1
CC1NE
Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated.
2
1
read-write
B_0x0
Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x0
B_0x1
On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1
CC1NP
Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.
3
1
read-write
B_0x0
OC1N active high.
0x0
B_0x1
OC1N active low.
0x1
CC1P
Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
1
1
read-write
B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x0
B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
0x1
CC2E
Capture/Compare 2 output enable Refer to CC1E description
4
1
read-write
CC2NE
Capture/Compare 2 complementary output enable Refer to CC1NE description
6
1
read-write
CC2NP
Capture/Compare 2 complementary output polarity Refer to CC1NP description
7
1
read-write
CC2P
Capture/Compare 2 output polarity Refer to CC1P description
5
1
read-write
CC3E
Capture/Compare 3 output enable Refer to CC1E description
8
1
read-write
CC3NE
Capture/Compare 3 complementary output enable Refer to CC1NE description
10
1
read-write
CC3NP
Capture/Compare 3 complementary output polarity Refer to CC1NP description
11
1
read-write
CC3P
Capture/Compare 3 output polarity Refer to CC1P description
9
1
read-write
CC4E
Capture/Compare 4 output enable Refer to CC1E description
12
1
read-write
CC4NP
Capture/Compare 4 complementary output polarity Refer to CC1NP description
15
1
read-write
CC4P
Capture/Compare 4 output polarity Refer to CC1P description
13
1
read-write
CC5E
Capture/Compare 5 output enable Refer to CC1E description
16
1
read-write
CC5P
Capture/Compare 5 output polarity Refer to CC1P description
17
1
read-write
CC6E
Capture/Compare 6 output enable Refer to CC1E description
20
1
read-write
CC6P
Capture/Compare 6 output polarity Refer to CC1P description
21
1
read-write
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (output mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2
0x2
B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC2S
Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER).
8
2
read-write
B_0x0
CC2 channel is configured as output
0x0
B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2
0x1
B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1
0x2
B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
IC1F
Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
4
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
IC1PSC
Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register).
2
2
read-write
B_0x0
no prescaler, capture is done each time an edge is detected on the capture input
0x0
B_0x1
capture is done once every 2 events
0x1
B_0x2
capture is done once every 4 events
0x2
B_0x3
capture is done once every 8 events
0x3
IC2F
Input capture 2 filter Refer to IC1F[3:0] description.
12
4
read-write
IC2PSC
Input capture 2 prescaler Refer to IC1PSC[1:0] description.
10
2
read-write
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2
0x2
B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC2S
Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER).
8
2
read-write
B_0x0
CC2 channel is configured as output
0x0
B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2
0x1
B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1
0x2
B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
0x3
OC1CE
Output Compare 1 clear enable
7
1
read-write
B_0x0
OC1Ref is not affected by the ocref_clr_int signal
0x0
B_0x1
OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal (OCREF_CLR input or ETRF input)
0x1
OC1FE
Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
2
1
read-write
B_0x0
CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x0
B_0x1
An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
0x1
OC1M1
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16.
4
3
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=â1â).
0x6
B_0x7
PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive.
0x7
B_0x8
Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x8
B_0x9
Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0x9
B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xC
B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
0xD
B_0xE
Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xE
B_0xF
Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xF
OC1M2
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16.
16
1
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=â1â).
0x6
B_0x7
PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive.
0x7
B_0x8
Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x8
B_0x9
Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0x9
B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xC
B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
0xD
B_0xE
Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xE
B_0xF
Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xF
OC1PE
Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
3
1
read-write
B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x0
B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
0x1
OC2CE
Output Compare 2 clear enable Refer to OC1CE description.
15
1
read-write
OC2FE
Output Compare 2 fast enable Refer to OC1FE description.
10
1
read-write
OC2M1
Output Compare 2 mode Refer to OC1M[3:0] description.
12
3
read-write
OC2M2
Output Compare 2 mode Refer to OC1M[3:0] description.
24
1
read-write
OC2PE
Output Compare 2 preload enable Refer to OC1PE description.
11
1
read-write
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (output mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC3 channel is configured as output
0x0
B_0x1
CC3 channel is configured as input, IC3 is mapped on TI3
0x1
B_0x2
CC3 channel is configured as input, IC3 is mapped on TI4
0x2
B_0x3
CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC4S
Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0â in TIMx_CCER).
8
2
read-write
B_0x0
CC4 channel is configured as output
0x0
B_0x1
CC4 channel is configured as input, IC4 is mapped on TI4
0x1
B_0x2
CC4 channel is configured as input, IC4 is mapped on TI3
0x2
B_0x3
CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
IC3F
Input capture 3 filter Refer to IC1F[3:0] description.
4
4
read-write
IC3PSC
Input capture 3 prescaler Refer to IC1PSC[1:0] description.
2
2
read-write
IC4F
Input capture 4 filter Refer to IC1F[3:0] description.
12
4
read-write
IC4PSC
Input capture 4 prescaler Refer to IC1PSC[1:0] description.
10
2
read-write
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC3 channel is configured as output
0x0
B_0x1
CC3 channel is configured as input, IC3 is mapped on TI3
0x1
B_0x2
CC3 channel is configured as input, IC3 is mapped on TI4
0x2
B_0x3
CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC4S
Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0â in TIMx_CCER).
8
2
read-write
B_0x0
CC4 channel is configured as output
0x0
B_0x1
CC4 channel is configured as input, IC4 is mapped on TI4
0x1
B_0x2
CC4 channel is configured as input, IC4 is mapped on TI3
0x2
B_0x3
CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
OC3CE
Output compare 3 clear enable Refer to OC1CE description.
7
1
read-write
OC3FE
Output compare 3 fast enable Refer to OC1FE description.
2
1
read-write
OC3M1
Output compare 3 mode Refer to OC1M[3:0] description.
4
3
read-write
OC3M2
Output compare 3 mode Refer to OC1M[3:0] description.
16
1
read-write
OC3PE
Output compare 3 preload enable Refer to OC1PE description.
3
1
read-write
OC4CE
Output compare 4 clear enable Refer to OC1CE description.
15
1
read-write
OC4FE
Output compare 4 fast enable Refer to OC1FE description.
10
1
read-write
OC4M1
Output compare 4 mode Refer to OC3M[3:0] description.
12
3
read-write
OC4M2
Output compare 4 mode Refer to OC3M[3:0] description.
24
1
read-write
OC4PE
Output compare 4 preload enable Refer to OC1PE description.
11
1
read-write
CCMR3_Output
CCMR3_Output
capture/compare mode register 2 (output mode)
0x54
32
read-write
n
0x0
0xFFFFFFFF
OC5CE
Output compare 5 clear enable
7
1
OC5FE
Output compare 5 fast enable
2
1
OC5M
Output compare 5 mode
4
3
OC5M_bit3
Output Compare 5 mode bit 3
16
1
OC5PE
Output compare 5 preload enable
3
1
OC6CE
Output compare 6 clear enable
15
1
OC6FE
Output compare 6 fast enable
10
1
OC6M
Output compare 6 mode
12
3
OC6M_bit3
Output Compare 6 mode bit 3
24
1
OC6PE
Output compare 6 preload enable
11
1
CCR1
TIM1_CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CCR2
TIM1_CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2
Capture/Compare 2 value
0
16
CCR3
TIM1_CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3
Capture/Compare value
0
16
CCR4
TIM1_CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4
Capture/Compare value
0
16
CCR5
TIM1_CCR5
capture/compare register 4
0x58
32
read-write
n
0x0
0xFFFFFFFF
CCR5
Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output.
0
16
read-write
GC5C1
Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
29
1
read-write
B_0x0
No effect of OC5REF on OC1REFC5
0x0
B_0x1
OC1REFC is the logical AND of OC1REFC and OC5REF
0x1
GC5C2
Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
30
1
read-write
B_0x0
No effect of OC5REF on OC2REFC
0x0
B_0x1
OC2REFC is the logical AND of OC2REFC and OC5REF
0x1
GC5C3
Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals.
31
1
read-write
B_0x0
No effect of OC5REF on OC3REFC
0x0
B_0x1
OC3REFC is the logical AND of OC3REFC and OC5REF
0x1
CCR6
TIM1_CCR6
capture/compare register 4
0x5C
32
read-write
n
0x0
0xFFFFFFFF
CCR6
Capture/Compare value
0
16
CNT
TIM1_CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
Counter value
0
16
read-write
UIFCPY
UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
31
1
read-only
CR1
TIM1_CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered
0x0
B_0x1
TIMx_ARR register is buffered
0x1
CEN
Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
CKD
Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT.
8
2
read-write
B_0x0
tDTS=tCK_INT
0x0
B_0x1
tDTS=2*tCK_INT
0x1
B_0x2
tDTS=4*tCK_INT
0x2
B_0x3
Reserved, do not program this value
0x3
CMS
Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed
5
2
read-write
B_0x0
Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x0
B_0x1
Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x1
B_0x2
Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x2
B_0x3
Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
0x3
DIR
Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
4
1
read-write
B_0x0
Counter used as upcounter
0x0
B_0x1
Counter used as downcounter
0x1
OPM
One pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
0x1
CR2
TIM1_CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
read-write
B_0x0
CCx DMA request sent when CCx event occurs
0x0
B_0x1
CCx DMA requests sent when update event occurs
0x1
CCPC
Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0
1
read-write
B_0x0
CCxE, CCxNE and OCxM bits are not preloaded
0x0
B_0x1
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
0x1
CCUS
Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
2
1
read-write
B_0x0
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
0x0
B_0x1
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
0x1
MMS
Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
4
3
read-write
B_0x0
Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x0
B_0x1
Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x1
B_0x2
Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x2
B_0x3
Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x3
B_0x4
Compare - OC1REFC signal is used as trigger output (TRGO)
0x4
B_0x5
Compare - OC2REFC signal is used as trigger output (TRGO)
0x5
B_0x6
Compare - OC3REFC signal is used as trigger output (TRGO)
0x6
B_0x7
Compare - OC4REFC signal is used as trigger output (TRGO)
0x7
MMS2
Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
20
4
read-write
B_0x0
Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset.
0x0
B_0x1
Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x1
B_0x2
Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer.
0x2
B_0x3
Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2).
0x3
B_0x4
Compare - OC1REFC signal is used as trigger output (TRGO2)
0x4
B_0x5
Compare - OC2REFC signal is used as trigger output (TRGO2)
0x5
B_0x6
Compare - OC3REFC signal is used as trigger output (TRGO2)
0x6
B_0x7
Compare - OC4REFC signal is used as trigger output (TRGO2)
0x7
B_0x8
Compare - OC5REFC signal is used as trigger output (TRGO2)
0x8
B_0x9
Compare - OC6REFC signal is used as trigger output (TRGO2)
0x9
B_0xA
Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2
0xA
B_0xB
Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2
0xB
B_0xC
Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2
0xC
B_0xD
Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2
0xD
B_0xE
Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2
0xE
B_0xF
Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2
0xF
OIS1
Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
8
1
read-write
B_0x0
OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x0
B_0x1
OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
0x1
OIS1N
Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
OC1N=0 after a dead-time when MOE=0
0x0
B_0x1
OC1N=1 after a dead-time when MOE=0
0x1
OIS2
Output Idle state 2 (OC2 output) Refer to OIS1 bit
10
1
read-write
OIS2N
Output Idle state 2 (OC2N output) Refer to OIS1N bit
11
1
read-write
OIS3
Output Idle state 3 (OC3 output) Refer to OIS1 bit
12
1
read-write
OIS3N
Output Idle state 3 (OC3N output) Refer to OIS1N bit
13
1
read-write
OIS4
Output Idle state 4 (OC4 output) Refer to OIS1 bit
14
1
read-write
OIS5
Output Idle state 5 (OC5 output) Refer to OIS1 bit
16
1
read-write
OIS6
Output Idle state 6 (OC6 output) Refer to OIS1 bit
18
1
read-write
TI1S
TI1 selection
7
1
read-write
B_0x0
The TIMx_CH1 pin is connected to TI1 input
0x0
B_0x1
The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
0x1
DCR
TIM1_DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
0
5
read-write
B_0x0
TIMx_CR1,
0x0
B_0x1
TIMx_CR2,
0x1
B_0x2
TIMx_SMCR,
0x2
DBL
DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes and DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA.
8
5
read-write
B_0x0
1 transfer
0x0
B_0x1
2 transfers
0x1
B_0x11
18 transfers
0x11
B_0x2
3 transfers
0x2
DIER
TIM1_DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
read-write
B_0x0
Break interrupt disabled
0x0
B_0x1
Break interrupt enabled
0x1
CC1DE
Capture/Compare 1 DMA request enable
9
1
read-write
B_0x0
CC1 DMA request disabled
0x0
B_0x1
CC1 DMA request enabled
0x1
CC1IE
Capture/Compare 1 interrupt enable
1
1
read-write
B_0x0
CC1 interrupt disabled
0x0
B_0x1
CC1 interrupt enabled
0x1
CC2DE
Capture/Compare 2 DMA request enable
10
1
read-write
B_0x0
CC2 DMA request disabled
0x0
B_0x1
CC2 DMA request enabled
0x1
CC2IE
Capture/Compare 2 interrupt enable
2
1
read-write
B_0x0
CC2 interrupt disabled
0x0
B_0x1
CC2 interrupt enabled
0x1
CC3DE
Capture/Compare 3 DMA request enable
11
1
read-write
B_0x0
CC3 DMA request disabled
0x0
B_0x1
CC3 DMA request enabled
0x1
CC3IE
Capture/Compare 3 interrupt enable
3
1
read-write
B_0x0
CC3 interrupt disabled
0x0
B_0x1
CC3 interrupt enabled
0x1
CC4DE
Capture/Compare 4 DMA request enable
12
1
read-write
B_0x0
CC4 DMA request disabled
0x0
B_0x1
CC4 DMA request enabled
0x1
CC4IE
Capture/Compare 4 interrupt enable
4
1
read-write
B_0x0
CC4 interrupt disabled
0x0
B_0x1
CC4 interrupt enabled
0x1
COMDE
COM DMA request enable
13
1
read-write
B_0x0
COM DMA request disabled
0x0
B_0x1
COM DMA request enabled
0x1
COMIE
COM interrupt enable
5
1
read-write
B_0x0
COM interrupt disabled
0x0
B_0x1
COM interrupt enabled
0x1
TDE
Trigger DMA request enable
14
1
read-write
B_0x0
Trigger DMA request disabled
0x0
B_0x1
Trigger DMA request enabled
0x1
TIE
Trigger interrupt enable
6
1
read-write
B_0x0
Trigger interrupt disabled
0x0
B_0x1
Trigger interrupt enabled
0x1
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled
0x0
B_0x1
Update DMA request enabled
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled
0x0
B_0x1
Update interrupt enabled
0x1
DMAR
TIM1_DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
0
32
read-write
EGR
TIM1_EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
B2G
Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
8
1
write-only
B_0x0
No action
0x0
B_0x1
A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled.
0x1
BG
Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
7
1
write-only
B_0x0
No action
0x0
B_0x1
A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
0x1
CC1G
Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
1
1
write-only
B_0x0
No action
0x0
B_0x1
A capture/compare event is generated on channel 1:
0x1
CC2G
Capture/Compare 2 generation Refer to CC1G description
2
1
write-only
CC3G
Capture/Compare 3 generation Refer to CC1G description
3
1
write-only
CC4G
Capture/Compare 4 generation Refer to CC1G description
4
1
write-only
COMG
Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output.
5
1
write-only
B_0x0
No action
0x0
B_0x1
When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated.
0x1
TG
Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
6
1
write-only
B_0x0
No action
0x0
B_0x1
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
0x1
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action
0x0
B_0x1
Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
0x1
OR1
TIM1_OR1
option register 1
0x50
32
read-write
n
0x0
0xFFFFFFFF
OCREF_CLR
Ocref_clr source selection This bit selects the ocref_clr input source.
0
1
read-write
B_0x0
COMP1 output is connected to the OCREF_CLR input
0x0
B_0x1
COMP2 output is connected to the OCREF_CLR input
0x1
PSC
TIM1_PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in âreset modeâ).
0
16
read-write
RCR
TIM1_RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
16
SMCR
TIM1_SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
14
1
read-write
B_0x0
External clock mode 2 disabled
0x0
B_0x1
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
0x1
ETF
External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
8
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
ETP
External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
15
1
read-write
B_0x0
ETR is non-inverted, active at high level or rising edge.
0x0
B_0x1
ETR is inverted, active at low level or falling edge.
0x1
ETPS
External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
12
2
read-write
B_0x0
Prescaler OFF
0x0
B_0x1
ETRP frequency divided by 2
0x1
B_0x2
ETRP frequency divided by 4
0x2
B_0x3
ETRP frequency divided by 8
0x3
MSM
Master/slave mode
7
1
read-write
B_0x0
No action
0x0
B_0x1
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
0x1
OCCS
OCREF clear selection This bit is used to select the OCREF clear source.
3
1
read-write
B_0x0
OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIM1_OR1.OCREF_CLR
0x0
B_0x1
OCREF_CLR_INT is connected to ETRF
0x1
SMS1
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0
3
read-write
B_0x0
Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock.
0x0
B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x1
B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x2
B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x3
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.Codes above 1000: Reserved.
0x8
SMS2
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
16
1
read-write
B_0x0
Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock.
0x0
B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x1
B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x2
B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x3
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.Codes above 1000: Reserved.
0x8
TS1
Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
4
3
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
B_0x7
External Trigger input (ETRF)
0x7
TS2
Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
20
2
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
B_0x7
External Trigger input (ETRF)
0x7
SR
TIM1_SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
B2IF
Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.
8
1
read-write
B_0x0
No break event occurred.
0x0
B_0x1
An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register.
0x1
BIF
Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
7
1
read-write
B_0x0
No break event occurred.
0x0
B_0x1
An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register.
0x1
CC1IF
Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
1
1
read-write
B_0x0
No compare match / No input capture occurred
0x0
B_0x1
A compare match or an input capture occurred.
0x1
CC1OF
Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
9
1
read-write
B_0x0
No overcapture has been detected.
0x0
B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
0x1
CC2IF
Capture/Compare 2 interrupt flag Refer to CC1IF description
2
1
read-write
CC2OF
Capture/Compare 2 overcapture flag Refer to CC1OF description
10
1
read-write
CC3IF
Capture/Compare 3 interrupt flag Refer to CC1IF description
3
1
read-write
CC3OF
Capture/Compare 3 overcapture flag Refer to CC1OF description
11
1
read-write
CC4IF
Capture/Compare 4 interrupt flag Refer to CC1IF description
4
1
read-write
CC4OF
Capture/Compare 4 overcapture flag Refer to CC1OF description
12
1
read-write
CC5IF
Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)
16
1
read-write
CC6IF
Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)
17
1
read-write
COMIF
COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software.
5
1
read-write
B_0x0
No COM event occurred.
0x0
B_0x1
COM interrupt pending.
0x1
SBIF
System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation.
13
1
read-write
B_0x0
No break event occurred.
0x0
B_0x1
An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register.
0x1
TIF
Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
6
1
read-write
B_0x0
No trigger event occurred.
0x0
B_0x1
Trigger interrupt pending.
0x1
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred.
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TISEL
TIM1_TISEL
TIM1 timer input selection register
0x68
32
read-write
n
0x0
0xFFFFFFFF
TI1SEL
selects TI1[0] to TI1[15] input Others: Reserved
0
4
read-write
B_0x0
TIM1_CH1 input
0x0
B_0x1
COMP1 output
0x1
TI2SEL
selects TI2[0] to TI2[15] input Others: Reserved
8
4
read-write
B_0x0
TIM1_CH2 input
0x0
B_0x1
COMP2 output
0x1
TI3SEL
selects TI3[0] to TI3[15] input Others: Reserved
16
4
read-write
B_0x0
TIM1_CH3 input
0x0
TI4SEL
selects TI4[0] to TI4[15] input Others: Reserved
24
4
read-write
B_0x0
TIM1_CH4 input
0x0
TIM14
General purpose timers
TIM
0x40002000
0x0
0x400
registers
n
TIM14
TIM14 global interrupt
19
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable.
0
1
read-write
B_0x0
Capture mode disabled / OC1 is not active
0x0
B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
0x1
CC1NP
Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description).
3
1
read-write
CC1P
Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used.
1
1
read-write
B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x0
B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
0x1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
IC1F
Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
4
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
IC1PSC
Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register).
2
2
read-write
B_0x0
no prescaler, capture is done each time an edge is detected on the capture input
0x0
B_0x1
capture is done once every 2 events
0x1
B_0x2
capture is done once every 4 events
0x2
B_0x3
capture is done once every 8 events
0x3
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output.
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1.
0x1
OC1FE
Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
2
1
read-write
B_0x0
CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x0
B_0x1
An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.
0x1
OC1M1
Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
4
3
read-write
B_0x0
Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active
0x7
OC1M2
Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
16
1
read-write
B_0x0
Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active
0x7
OC1PE
Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
3
1
read-write
B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x0
B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
0x1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Low Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
low counter value
0
16
UIFCPY
UIF Copy
31
1
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered
0x0
B_0x1
TIMx_ARR register is buffered
0x1
CEN
Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
CKD
Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
8
2
read-write
B_0x0
tDTS = tCK_INT
0x0
B_0x1
tDTS = 2 Ã tCK_INT
0x1
B_0x2
tDTS = 4 Ã tCK_INT
0x2
OPM
One-pulse mode
3
1
read-write
B_0x0
Counter is not stopped on the update event
0x0
B_0x1
Counter stops counting on the next update event (clearing the CEN bit).
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. An UEV is generated by one of the following events:
0x0
B_0x1
UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
2
1
read-write
B_0x0
Any of the following events generate an UEV if enabled:
0x0
B_0x1
Only counter overflow generates an UEV if enabled.
0x1
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CC1IE
Capture/Compare 1 interrupt enable
1
1
read-write
B_0x0
CC1 interrupt disabled
0x0
B_0x1
CC1 interrupt enabled
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled
0x0
B_0x1
Update interrupt enabled
0x1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
CC1G
Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
1
1
write-only
B_0x0
No action
0x0
B_0x1
A capture/compare event is generated on channel 1:
0x1
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action
0x0
B_0x1
Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CC1IF
Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
1
1
read-write
B_0x0
No compare match / No input capture occurred
0x0
B_0x1
A compare match or an input capture occurred.
0x1
CC1OF
Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
9
1
read-write
B_0x0
No overcapture has been detected.
0x0
B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
0x1
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=â0â in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=â0â and UDIS=â0â in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred.
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TISEL
TISEL
TIM timer input selection register
0x68
32
read-write
n
0x0
0xFFFFFFFF
TI1SEL
selects TI1[0] to TI1[15] input Others: Reserved
0
4
read-write
B_0x0
TIM14_CH1 input
0x0
B_0x1
RTC CLK
0x1
B_0x2
HSE/32
0x2
B_0x3
MCO
0x3
TIM15
General purpose timers
TIM
0x40014000
0x0
0x400
registers
n
TIM15
Timer 15 global interrupt
20
AF1
AF1
TIM15 alternate register 1
0x60
32
read-write
n
0x1
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1
1
read-write
B_0x0
COMP1 input disabled
0x0
B_0x1
COMP1 input enabled
0x1
BKCMP1P
BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
COMP1 input is active low
0x0
B_0x1
COMP1 input is active high
0x1
BKCMP2E
BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2
1
read-write
B_0x0
COMP2 input disabled
0x0
B_0x1
COMP2 input enabled
0x1
BKCMP2P
BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
COMP2 input is active low
0x0
B_0x1
COMP2 input is active high
0x1
BKINE
BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0
1
read-write
B_0x0
BKIN input disabled
0x0
B_0x1
BKIN input enabled
0x1
BKINP
BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
BKIN input is active low
0x0
B_0x1
BKIN input is active high
0x1
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0xFFFF
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
14
1
read-write
B_0x0
MOE can be set only by software
0x0
B_0x1
MOE can be set by software or automatically at the next update event (if the break input is not be active)
0x1
BKBID
Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
28
1
read-write
B_0x0
Break input BRK in input mode
0x0
B_0x1
Break input BRK in bidirectional mode
0x1
BKDSRM
Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
26
1
read-write
B_0x0
Break input BRK is armed
0x0
B_0x1
Break input BRK is disarmed
0x1
BKE
Break enable 1 Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
12
1
read-write
B_0x0
Break inputs (BRK and CCS clock failure event) disabled
0x0
BKF
Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
16
4
read-write
B_0x0
No filter, BRK acts asynchronously
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
BKP
Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
13
1
read-write
B_0x0
Break input BRK is active low
0x0
B_0x1
Break input BRK is active high
0x1
DTG
Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0
8
read-write
LOCK
Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
8
2
read-write
B_0x0
LOCK OFF - No bit is write protected
0x0
B_0x1
LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
0x1
B_0x2
LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x2
B_0x3
LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
0x3
MOE
Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
15
1
read-write
B_0x0
OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x0
B_0x1
OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)
0x1
OSSI
Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x0
B_0x1
When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
0x1
OSSR
Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x0
B_0x1
When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
0x1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details.
0
1
read-write
B_0x0
Capture mode disabled / OC1 is not active (see below)
0x0
B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
0x1
CC1NE
Capture/Compare 1 complementary output enable
2
1
read-write
B_0x0
Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x0
B_0x1
On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1
CC1NP
Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.
3
1
read-write
B_0x0
OC1N active high
0x0
B_0x1
OC1N active low
0x1
CC1P
Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
1
1
read-write
B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x0
B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
0x1
CC2E
Capture/Compare 2 output enable Refer to CC1E description
4
1
read-write
CC2NP
Capture/Compare 2 complementary output polarity Refer to CC1NP description
7
1
read-write
CC2P
Capture/Compare 2 output polarity Refer to CC1P description
5
1
read-write
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2
0x2
B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC2S
Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER).
8
2
read-write
B_0x0
CC2 channel is configured as output
0x0
B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2
0x1
B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1
0x2
B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
IC1F
Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
4
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
IC1PSC
Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register).
2
2
read-write
B_0x0
no prescaler, capture is done each time an edge is detected on the capture input
0x0
B_0x1
capture is done once every 2 events
0x1
B_0x2
capture is done once every 4 events
0x2
B_0x3
capture is done once every 8 events
0x3
IC2F
Input capture 2 filter
12
4
read-write
IC2PSC
Input capture 2 prescaler
10
2
read-write
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output.
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1.
0x1
B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2.
0x2
B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC2S
Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER).
8
2
read-write
B_0x0
CC2 channel is configured as output.
0x0
B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2.
0x1
B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1.
0x2
B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
0x3
OC1FE
Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
2
1
read-write
B_0x0
CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x0
B_0x1
An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
0x1
OC1M1
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.
4
3
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x7
B_0x8
Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x8
B_0x9
Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0x9
B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xC
B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
0xD
OC1M2
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.
16
1
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x7
B_0x8
Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x8
B_0x9
Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0x9
B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xC
B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
0xD
OC1PE
Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
3
1
read-write
B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x0
B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
0x1
OC2FE
Output Compare 2 fast enable
10
1
read-write
OC2M1
Output Compare 2 mode
12
3
read-write
OC2M2
Output Compare 2 mode
24
1
read-write
OC2PE
Output Compare 2 preload enable
11
1
read-write
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered
0x0
B_0x1
TIMx_ARR register is buffered
0x1
CEN
Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
CKD
Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx)
8
2
read-write
B_0x0
tDTS = tCK_INT
0x0
B_0x1
tDTS = 2*tCK_INT
0x1
B_0x2
tDTS = 4*tCK_INT
0x2
B_0x3
Reserved, do not program this value
0x3
OPM
One-pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generate an update interrupt if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt if enabled
0x1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
read-write
B_0x0
CCx DMA request sent when CCx event occurs
0x0
B_0x1
CCx DMA requests sent when update event occurs
0x1
CCPC
Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0
1
read-write
B_0x0
CCxE, CCxNE and OCxM bits are not preloaded
0x0
B_0x1
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
0x1
CCUS
Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
2
1
read-write
B_0x0
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x0
B_0x1
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
0x1
MMS
Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
4
3
read-write
B_0x0
Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x0
B_0x1
Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x1
B_0x2
Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x2
B_0x3
Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x3
B_0x4
Compare - OC1REFC signal is used as trigger output (TRGO).
0x4
B_0x5
Compare - OC2REFC signal is used as trigger output (TRGO).
0x5
OIS1
Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
8
1
read-write
B_0x0
OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x0
B_0x1
OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
0x1
OIS1N
Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
9
1
read-write
B_0x0
OC1N=0 after a dead-time when MOE=0
0x0
B_0x1
OC1N=1 after a dead-time when MOE=0
0x1
OIS2
Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).
10
1
read-write
B_0x0
OC2=0 when MOE=0
0x0
B_0x1
OC2=1 when MOE=0
0x1
TI1S
TI1 selection
7
1
read-write
B_0x0
The TIMx_CH1 pin is connected to TI1 input
0x0
B_0x1
The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination)
0x1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
0
5
read-write
B_0x0
TIMx_CR1,
0x0
B_0x1
TIMx_CR2,
0x1
B_0x2
TIMx_SMCR,
0x2
DBL
DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
8
5
read-write
B_0x0
1 transfer,
0x0
B_0x1
2 transfers,
0x1
B_0x11
18 transfers.
0x11
B_0x2
3 transfers,
0x2
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
read-write
B_0x0
Break interrupt disabled
0x0
B_0x1
Break interrupt enabled
0x1
CC1DE
Capture/Compare 1 DMA request enable
9
1
read-write
B_0x0
CC1 DMA request disabled
0x0
B_0x1
CC1 DMA request enabled
0x1
CC1IE
Capture/Compare 1 interrupt enable
1
1
read-write
B_0x0
CC1 interrupt disabled
0x0
B_0x1
CC1 interrupt enabled
0x1
CC2DE
Capture/Compare 2 DMA request enable
10
1
read-write
B_0x0
CC2 DMA request disabled
0x0
B_0x1
CC2 DMA request enabled
0x1
CC2IE
Capture/Compare 2 interrupt enable
2
1
read-write
B_0x0
CC2 interrupt disabled
0x0
B_0x1
CC2 interrupt enabled
0x1
COMDE
COM DMA request enable
13
1
read-write
B_0x0
COM DMA request disabled
0x0
B_0x1
COM DMA request enabled
0x1
COMIE
COM interrupt enable
5
1
read-write
B_0x0
COM interrupt disabled
0x0
B_0x1
COM interrupt enabled
0x1
TDE
Trigger DMA request enable
14
1
read-write
B_0x0
Trigger DMA request disabled
0x0
B_0x1
Trigger DMA request enabled
0x1
TIE
Trigger interrupt enable
6
1
read-write
B_0x0
Trigger interrupt disabled
0x0
B_0x1
Trigger interrupt enabled
0x1
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled
0x0
B_0x1
Update DMA request enabled
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled
0x0
B_0x1
Update interrupt enabled
0x1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
7
1
write-only
B_0x0
No action
0x0
B_0x1
A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
0x1
CC1G
Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
1
1
write-only
B_0x0
No action
0x0
B_0x1
A capture/compare event is generated on channel 1:
0x1
CC2G
Capture/Compare 2 generation Refer to CC1G description
2
1
write-only
COMG
Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
5
1
read-write
B_0x0
No action
0x0
B_0x1
When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
0x1
TG
Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
6
1
write-only
B_0x0
No action
0x0
B_0x1
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled
0x1
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action
0x0
B_0x1
Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
MSM
Master/slave mode
7
1
read-write
B_0x0
No action
0x0
B_0x1
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
0x1
SMS1
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0
3
read-write
B_0x0
Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock.
0x0
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.
0x8
SMS2
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
16
1
read-write
B_0x0
Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock.
0x0
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.
0x8
TS1
Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
4
3
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
TS2
Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
20
2
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
7
1
read-write
B_0x0
No break event occurred
0x0
B_0x1
An active level has been detected on the break input
0x1
CC1IF
Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
1
1
read-write
B_0x0
No compare match / No input capture occurred
0x0
B_0x1
A compare match or an input capture occurred
0x1
CC1OF
Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
9
1
read-write
B_0x0
No overcapture has been detected
0x0
B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
0x1
CC2IF
Capture/Compare 2 interrupt flag refer to CC1IF description
2
1
read-write
CC2OF
Capture/Compare 2 overcapture flag Refer to CC1OF description
10
1
read-write
COMIF
COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software.
5
1
read-write
B_0x0
No COM event occurred
0x0
B_0x1
COM interrupt pending
0x1
TIF
Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
6
1
read-write
B_0x0
No trigger event occurred
0x0
B_0x1
Trigger interrupt pending
0x1
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred.
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TISEL
TISEL
input selection register
0x68
32
read-write
n
0x0
0xFFFFFFFF
TI1SEL
selects TI1[0] to TI1[15] input Others: Reserved
0
4
read-write
B_0x0
TIM15_CH1 input
0x0
B_0x1
TIM2_IC1
0x1
B_0x2
TIM3_IC1
0x2
TI2SEL
selects TI2[0] to TI2[15] input Others: Reserved
8
4
read-write
B_0x0
TIM15_CH2 input
0x0
B_0x1
TIM2_IC2
0x1
B_0x2
TIM3_IC2
0x2
TIM16
General purpose timers
TIM
0x40014400
0x0
0x400
registers
n
TIM16
TIM16 global interrupt
21
AF1
AF1
TIM17 option register 1
0x60
32
read-write
n
0x1
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1
1
read-write
B_0x0
COMP1 input disabled
0x0
B_0x1
COMP1 input enabled
0x1
BKCMP1P
BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
COMP1 input is active low
0x0
B_0x1
COMP1 input is active high
0x1
BKCMP2E
BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2
1
read-write
B_0x0
COMP2 input disabled
0x0
B_0x1
COMP2 input enabled
0x1
BKCMP2P
BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
COMP2 input is active low
0x0
B_0x1
COMP2 input is active high
0x1
BKINE
BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0
1
read-write
B_0x0
BKIN input disabled
0x0
B_0x1
BKIN input enabled
0x1
BKINP
BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
BKIN input is active low
0x0
B_0x1
BKIN input is active high
0x1
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0xFFFF
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
14
1
read-write
B_0x0
MOE can be set only by software
0x0
B_0x1
MOE can be set by software or automatically at the next update event (if the break input is not be active)
0x1
BKBID
Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
28
1
read-write
B_0x0
Break input BRK in input mode
0x0
B_0x1
Break input BRK in bidirectional mode
0x1
BKDSRM
Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
26
1
read-write
B_0x0
Break input BRK is armed
0x0
B_0x1
Break input BRK is disarmed
0x1
BKE
Break enable 1 Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
12
1
read-write
B_0x0
Break inputs (BRK and CCS clock failure event) disabled
0x0
BKF
Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
16
4
read-write
B_0x0
No filter, BRK acts asynchronously
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
BKP
Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
13
1
read-write
B_0x0
Break input BRK is active low
0x0
B_0x1
Break input BRK is active high
0x1
DTG
Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0
8
read-write
LOCK
Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
8
2
read-write
B_0x0
LOCK OFF - No bit is write protected
0x0
B_0x1
LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
0x1
B_0x2
LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x2
B_0x3
LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
0x3
MOE
Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846).
15
1
read-write
B_0x0
OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x0
B_0x1
OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (
0x1
OSSI
Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x0
B_0x1
When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
0x1
OSSR
Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x0
B_0x1
When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
0x1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details.
0
1
read-write
B_0x0
Capture mode disabled / OC1 is not active (see below)
0x0
B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
0x1
CC1NE
Capture/Compare 1 complementary output enable
2
1
read-write
B_0x0
Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x0
B_0x1
On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1
CC1NP
Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated.
3
1
read-write
B_0x0
OC1N active high
0x0
B_0x1
OC1N active low
0x1
CC1P
Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
1
1
read-write
B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x0
B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
0x1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
IC1F
Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
4
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
IC1PSC
Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register).
2
2
read-write
B_0x0
no prescaler, capture is done each time an edge is detected on the capture input.
0x0
B_0x1
capture is done once every 2 events
0x1
B_0x2
capture is done once every 4 events
0x2
B_0x3
capture is done once every 8 events
0x3
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
OC1FE
Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
2
1
read-write
B_0x0
CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x0
B_0x1
An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.
0x1
OC1M1
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16.
4
3
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x7
OC1M2
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16.
16
1
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x7
OC1PE
Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
3
1
read-write
B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x0
B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
0x1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered
0x0
B_0x1
TIMx_ARR register is buffered
0x1
CEN
Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
CKD
Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
8
2
read-write
B_0x0
tDTS=tCK_INT
0x0
B_0x1
tDTS=2*tCK_INT
0x1
B_0x2
tDTS=4*tCK_INT
0x2
B_0x3
Reserved, do not program this value
0x3
OPM
One pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
0x1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
read-write
B_0x0
CCx DMA request sent when CCx event occurs
0x0
B_0x1
CCx DMA requests sent when update event occurs
0x1
CCPC
Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0
1
read-write
B_0x0
CCxE, CCxNE and OCxM bits are not preloaded
0x0
B_0x1
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.
0x1
CCUS
Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
2
1
read-write
B_0x0
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x0
B_0x1
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
0x1
OIS1
Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
8
1
read-write
B_0x0
OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x0
B_0x1
OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
0x1
OIS1N
Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
OC1N=0 after a dead-time when MOE=0
0x0
B_0x1
OC1N=1 after a dead-time when MOE=0
0x1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0
5
read-write
B_0x0
TIMx_CR1,
0x0
B_0x1
TIMx_CR2,
0x1
B_0x2
TIMx_SMCR,
0x2
DBL
DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
8
5
read-write
B_0x0
1 transfer,
0x0
B_0x1
2 transfers,
0x1
B_0x11
18 transfers.
0x11
B_0x2
3 transfers,
0x2
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
read-write
B_0x0
Break interrupt disabled
0x0
B_0x1
Break interrupt enabled
0x1
CC1DE
Capture/Compare 1 DMA request enable
9
1
read-write
B_0x0
CC1 DMA request disabled
0x0
B_0x1
CC1 DMA request enabled
0x1
CC1IE
Capture/Compare 1 interrupt enable
1
1
read-write
B_0x0
CC1 interrupt disabled
0x0
B_0x1
CC1 interrupt enabled
0x1
COMIE
COM interrupt enable
5
1
read-write
B_0x0
COM interrupt disabled
0x0
B_0x1
COM interrupt enabled
0x1
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled
0x0
B_0x1
Update DMA request enabled
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled
0x0
B_0x1
Update interrupt enabled
0x1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
7
1
write-only
B_0x0
No action.
0x0
B_0x1
A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
0x1
CC1G
Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
1
1
write-only
B_0x0
No action.
0x0
B_0x1
A capture/compare event is generated on channel 1:
0x1
COMG
Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
5
1
write-only
B_0x0
No action
0x0
B_0x1
When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
0x1
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action.
0x0
B_0x1
Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
7
1
read-write
B_0x0
No break event occurred
0x0
B_0x1
An active level has been detected on the break input
0x1
CC1IF
Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
1
1
read-write
B_0x0
No compare match / No input capture occurred
0x0
B_0x1
A compare match or an input capture occurred
0x1
CC1OF
Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
9
1
read-write
B_0x0
No overcapture has been detected
0x0
B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
0x1
COMIF
COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software.
5
1
read-write
B_0x0
No COM event occurred
0x0
B_0x1
COM interrupt pending
0x1
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred.
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TISEL
TISEL
input selection register
0x68
32
read-write
n
0x0
0xFFFFFFFF
TI1SEL
selects TI1[0] to TI1[15] input Others: Reserved
0
4
read-write
B_0x0
TIM16_CH1 input
0x0
B_0x1
LSI
0x1
B_0x2
LSE
0x2
B_0x3
RTC wakeup
0x3
TIM17
General purpose timers
TIM
0x40014800
0x0
0x400
registers
n
TIM17
TIM17 global interrupt
22
AF1
AF1
TIM17 option register 1
0x60
32
read-write
n
0x1
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1
1
read-write
B_0x0
COMP1 input disabled
0x0
B_0x1
COMP1 input enabled
0x1
BKCMP1P
BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
COMP1 input is active low
0x0
B_0x1
COMP1 input is active high
0x1
BKCMP2E
BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2
1
read-write
B_0x0
COMP2 input disabled
0x0
B_0x1
COMP2 input enabled
0x1
BKCMP2P
BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
COMP2 input is active low
0x0
B_0x1
COMP2 input is active high
0x1
BKINE
BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0
1
read-write
B_0x0
BKIN input disabled
0x0
B_0x1
BKIN input enabled
0x1
BKINP
BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
BKIN input is active low
0x0
B_0x1
BKIN input is active high
0x1
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0xFFFF
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
14
1
read-write
B_0x0
MOE can be set only by software
0x0
B_0x1
MOE can be set by software or automatically at the next update event (if the break input is not be active)
0x1
BKBID
Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
28
1
read-write
B_0x0
Break input BRK in input mode
0x0
B_0x1
Break input BRK in bidirectional mode
0x1
BKDSRM
Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
26
1
read-write
B_0x0
Break input BRK is armed
0x0
B_0x1
Break input BRK is disarmed
0x1
BKE
Break enable 1 Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
12
1
read-write
B_0x0
Break inputs (BRK and CCS clock failure event) disabled
0x0
BKF
Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
16
4
read-write
B_0x0
No filter, BRK acts asynchronously
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
BKP
Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
13
1
read-write
B_0x0
Break input BRK is active low
0x0
B_0x1
Break input BRK is active high
0x1
DTG
Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0
8
read-write
LOCK
Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
8
2
read-write
B_0x0
LOCK OFF - No bit is write protected
0x0
B_0x1
LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
0x1
B_0x2
LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x2
B_0x3
LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
0x3
MOE
Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846).
15
1
read-write
B_0x0
OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x0
B_0x1
OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (
0x1
OSSI
Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
10
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x0
B_0x1
When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
0x1
OSSR
Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
11
1
read-write
B_0x0
When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x0
B_0x1
When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
0x1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details.
0
1
read-write
B_0x0
Capture mode disabled / OC1 is not active (see below)
0x0
B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
0x1
CC1NE
Capture/Compare 1 complementary output enable
2
1
read-write
B_0x0
Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x0
B_0x1
On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1
CC1NP
Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated.
3
1
read-write
B_0x0
OC1N active high
0x0
B_0x1
OC1N active low
0x1
CC1P
Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
1
1
read-write
B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x0
B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
0x1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
IC1F
Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
4
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
IC1PSC
Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register).
2
2
read-write
B_0x0
no prescaler, capture is done each time an edge is detected on the capture input.
0x0
B_0x1
capture is done once every 2 events
0x1
B_0x2
capture is done once every 4 events
0x2
B_0x3
capture is done once every 8 events
0x3
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
OC1FE
Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
2
1
read-write
B_0x0
CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x0
B_0x1
An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.
0x1
OC1M1
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16.
4
3
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x7
OC1M2
Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16.
16
1
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x6
B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x7
OC1PE
Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
3
1
read-write
B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x0
B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
0x1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered
0x0
B_0x1
TIMx_ARR register is buffered
0x1
CEN
Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
CKD
Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
8
2
read-write
B_0x0
tDTS=tCK_INT
0x0
B_0x1
tDTS=2*tCK_INT
0x1
B_0x2
tDTS=4*tCK_INT
0x2
B_0x3
Reserved, do not program this value
0x3
OPM
One pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
0x1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
read-write
B_0x0
CCx DMA request sent when CCx event occurs
0x0
B_0x1
CCx DMA requests sent when update event occurs
0x1
CCPC
Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0
1
read-write
B_0x0
CCxE, CCxNE and OCxM bits are not preloaded
0x0
B_0x1
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.
0x1
CCUS
Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
2
1
read-write
B_0x0
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x0
B_0x1
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
0x1
OIS1
Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
8
1
read-write
B_0x0
OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x0
B_0x1
OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
0x1
OIS1N
Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
9
1
read-write
B_0x0
OC1N=0 after a dead-time when MOE=0
0x0
B_0x1
OC1N=1 after a dead-time when MOE=0
0x1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0
5
read-write
B_0x0
TIMx_CR1,
0x0
B_0x1
TIMx_CR2,
0x1
B_0x2
TIMx_SMCR,
0x2
DBL
DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
8
5
read-write
B_0x0
1 transfer,
0x0
B_0x1
2 transfers,
0x1
B_0x11
18 transfers.
0x11
B_0x2
3 transfers,
0x2
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
read-write
B_0x0
Break interrupt disabled
0x0
B_0x1
Break interrupt enabled
0x1
CC1DE
Capture/Compare 1 DMA request enable
9
1
read-write
B_0x0
CC1 DMA request disabled
0x0
B_0x1
CC1 DMA request enabled
0x1
CC1IE
Capture/Compare 1 interrupt enable
1
1
read-write
B_0x0
CC1 interrupt disabled
0x0
B_0x1
CC1 interrupt enabled
0x1
COMIE
COM interrupt enable
5
1
read-write
B_0x0
COM interrupt disabled
0x0
B_0x1
COM interrupt enabled
0x1
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled
0x0
B_0x1
Update DMA request enabled
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled
0x0
B_0x1
Update interrupt enabled
0x1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
7
1
write-only
B_0x0
No action.
0x0
B_0x1
A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
0x1
CC1G
Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
1
1
write-only
B_0x0
No action.
0x0
B_0x1
A capture/compare event is generated on channel 1:
0x1
COMG
Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
5
1
write-only
B_0x0
No action
0x0
B_0x1
When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
0x1
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action.
0x0
B_0x1
Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
7
1
read-write
B_0x0
No break event occurred
0x0
B_0x1
An active level has been detected on the break input
0x1
CC1IF
Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
1
1
read-write
B_0x0
No compare match / No input capture occurred
0x0
B_0x1
A compare match or an input capture occurred
0x1
CC1OF
Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
9
1
read-write
B_0x0
No overcapture has been detected
0x0
B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
0x1
COMIF
COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software.
5
1
read-write
B_0x0
No COM event occurred
0x0
B_0x1
COM interrupt pending
0x1
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred.
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TISEL
TISEL
input selection register
0x68
32
read-write
n
0x0
0xFFFFFFFF
TI1SEL
selects TI1[0] to TI1[15] input Others: Reserved
0
4
read-write
B_0x0
TIM16_CH1 input
0x0
B_0x1
LSI
0x1
B_0x2
LSE
0x2
B_0x3
RTC wakeup
0x3
TIM2
General-purpose-timers
TIM
0x40000000
0x0
0x400
registers
n
TIM2
TIM2 global interrupt
15
AF1
AF1
TIM alternate function option register 1
0x60
32
read-write
n
0x0
0xFFFFFFFF
ETRSEL
ETR source selection These bits select the ETR input source. Others: Reserved
14
4
read-write
B_0x0
ETR legacy mode
0x0
B_0x1
COMP1
0x1
B_0x2
COMP2
0x2
B_0x3
LSE
0x3
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
ARR
High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0
32
read-write
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable.
0
1
read-write
B_0x0
Capture mode disabled / OC1 is not active
0x0
B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
0x1
CC1NP
Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description.
3
1
read-write
CC1P
Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used.
1
1
read-write
B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x0
B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
0x1
CC2E
Capture/Compare 2 output enable. Refer to CC1E description
4
1
read-write
CC2NP
Capture/Compare 2 output Polarity. Refer to CC1NP description
7
1
read-write
CC2P
Capture/Compare 2 output Polarity. refer to CC1P description
5
1
read-write
CC3E
Capture/Compare 3 output enable. Refer to CC1E description
8
1
read-write
CC3NP
Capture/Compare 3 output Polarity. Refer to CC1NP description
11
1
read-write
CC3P
Capture/Compare 3 output Polarity. Refer to CC1P description
9
1
read-write
CC4E
Capture/Compare 4 output enable. refer to CC1E description
12
1
read-write
CC4NP
Capture/Compare 4 output Polarity. Refer to CC1NP description
15
1
read-write
CC4P
Capture/Compare 4 output Polarity. Refer to CC1P description
13
1
read-write
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2
0x2
B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC2S
Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
8
2
read-write
B_0x0
CC2 channel is configured as output.
0x0
B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2.
0x1
B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1.
0x2
B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
OC1CE
Output compare 1 clear enable
7
1
read-write
B_0x0
OC1Ref is not affected by the ETRF input
0x0
B_0x1
OC1Ref is cleared as soon as a High level is detected on ETRF input
0x1
OC1FE
Output compare 1 fast enable
2
1
OC1M1
Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
4
3
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=1).
0x6
B_0x7
PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive.
0x7
B_0x8
Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x8
B_0x9
Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0x9
B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xC
B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
0xD
B_0xE
Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xE
B_0xF
Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xF
OC1M_3
Output Compare 1 mode - bit 3
16
1
OC1PE
Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
3
1
read-write
B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x0
B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
0x1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2M_3
Output Compare 2 mode - bit 3
24
1
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0
2
read-write
B_0x0
CC3 channel is configured as output
0x0
B_0x1
CC3 channel is configured as input, IC3 is mapped on TI3
0x1
B_0x2
CC3 channel is configured as input, IC3 is mapped on TI4
0x2
B_0x3
CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC4S
Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
8
2
read-write
B_0x0
CC4 channel is configured as output
0x0
B_0x1
CC4 channel is configured as input, IC4 is mapped on TI4
0x1
B_0x2
CC4 channel is configured as input, IC4 is mapped on TI3
0x2
B_0x3
CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3M_3
Output Compare 3 mode - bit 3
16
1
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4M_3
Output Compare 4 mode - bit 3
24
1
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed.
0
32
read-write
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2
High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed.
0
32
read-write
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3
High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed.
0
32
read-write
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4
High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed.
0
32
read-write
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CNT_ALTERNATE5
CNT_ALTERNATE5
counter
CNT
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
Most significant part counter value (TIM2) nullLeast significant part of counter value
0
31
read-write
UIFCPY
UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register
31
1
read-write
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered
0x0
B_0x1
TIMx_ARR register is buffered
0x1
CEN
Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
CKD
Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
8
2
read-write
B_0x0
tDTS = tCK_INT
0x0
B_0x1
tDTS = 2 Ã tCK_INT
0x1
B_0x2
tDTS = 4 Ã tCK_INT
0x2
CMS
Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
5
2
read-write
B_0x0
Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x0
B_0x1
Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x1
B_0x2
Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x2
B_0x3
Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
0x3
DIR
Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
4
1
read-write
B_0x0
Counter used as upcounter
0x0
B_0x1
Counter used as downcounter
0x1
OPM
One-pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
0x1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
read-write
B_0x0
CCx DMA request sent when CCx event occurs
0x0
B_0x1
CCx DMA requests sent when update event occurs
0x1
MMS
Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
4
3
read-write
B_0x0
Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x0
B_0x1
Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.
0x1
B_0x2
Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x2
B_0x3
Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
0x3
B_0x4
Compare - OC1REFC signal is used as trigger output (TRGO)
0x4
B_0x5
Compare - OC2REFC signal is used as trigger output (TRGO)
0x5
B_0x6
Compare - OC3REFC signal is used as trigger output (TRGO)
0x6
B_0x7
Compare - OC4REFC signal is used as trigger output (TRGO)
0x7
TI1S
TI1 selection
7
1
read-write
B_0x0
The TIMx_CH1 pin is connected to TI1 input
0x0
B_0x1
The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also
0x1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0
5
read-write
B_0x0
TIMx_CR1
0x0
B_0x1
TIMx_CR2
0x1
B_0x2
TIMx_SMCR
0x2
DBL
DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
8
5
read-write
B_0x0
1 transfer,
0x0
B_0x1
2 transfers,
0x1
B_0x11
18 transfers.
0x11
B_0x2
3 transfers,
0x2
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CC1DE
Capture/Compare 1 DMA request enable
9
1
read-write
B_0x0
CC1 DMA request disabled.
0x0
B_0x1
CC1 DMA request enabled.
0x1
CC1IE
Capture/Compare 1 interrupt enable
1
1
read-write
B_0x0
CC1 interrupt disabled.
0x0
B_0x1
CC1 interrupt enabled.
0x1
CC2DE
Capture/Compare 2 DMA request enable
10
1
read-write
B_0x0
CC2 DMA request disabled.
0x0
B_0x1
CC2 DMA request enabled.
0x1
CC2IE
Capture/Compare 2 interrupt enable
2
1
read-write
B_0x0
CC2 interrupt disabled.
0x0
B_0x1
CC2 interrupt enabled.
0x1
CC3DE
Capture/Compare 3 DMA request enable
11
1
read-write
B_0x0
CC3 DMA request disabled.
0x0
B_0x1
CC3 DMA request enabled.
0x1
CC3IE
Capture/Compare 3 interrupt enable
3
1
read-write
B_0x0
CC3 interrupt disabled.
0x0
B_0x1
CC3 interrupt enabled.
0x1
CC4DE
Capture/Compare 4 DMA request enable
12
1
read-write
B_0x0
CC4 DMA request disabled.
0x0
B_0x1
CC4 DMA request enabled.
0x1
CC4IE
Capture/Compare 4 interrupt enable
4
1
read-write
B_0x0
CC4 interrupt disabled.
0x0
B_0x1
CC4 interrupt enabled.
0x1
TDE
Trigger DMA request enable
14
1
read-write
B_0x0
Trigger DMA request disabled.
0x0
B_0x1
Trigger DMA request enabled.
0x1
TIE
Trigger interrupt enable
6
1
read-write
B_0x0
Trigger interrupt disabled.
0x0
B_0x1
Trigger interrupt enabled.
0x1
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled.
0x0
B_0x1
Update DMA request enabled.
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled.
0x0
B_0x1
Update interrupt enabled.
0x1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
CC1G
Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
1
1
write-only
B_0x0
No action
0x0
B_0x1
A capture/compare event is generated on channel 1:
0x1
CC2G
Capture/compare 2 generation Refer to CC1G description
2
1
write-only
CC3G
Capture/compare 3 generation Refer to CC1G description
3
1
write-only
CC4G
Capture/compare 4 generation Refer to CC1G description
4
1
write-only
TG
Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
6
1
write-only
B_0x0
No action
0x0
B_0x1
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
0x1
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action
0x0
B_0x1
Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
0x1
OR1
OR1
TIM option register
0x50
32
read-write
n
0x0
0xFFFFFFFF
OCREF_CLR
Ocref_clr source selection This bit selects the ocref_clr input source.
0
1
read-write
B_0x0
COMP1 output is connected to the OCREF_CLR input
0x0
B_0x1
COMP2 output is connected to the OCREF_CLR input
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
14
1
read-write
B_0x0
External clock mode 2 disabled
0x0
B_0x1
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
0x1
ETF
External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
8
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
ETP
External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
15
1
read-write
B_0x0
ETR is non-inverted, active at high level or rising edge
0x0
B_0x1
ETR is inverted, active at low level or falling edge
0x1
ETPS
External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
12
2
read-write
B_0x0
Prescaler OFF
0x0
B_0x1
ETRP frequency divided by 2
0x1
B_0x2
ETRP frequency divided by 4
0x2
B_0x3
ETRP frequency divided by 8
0x3
MSM
Master/Slave mode
7
1
read-write
B_0x0
No action
0x0
B_0x1
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
0x1
OCCS
OCREF clear selection This bit is used to select the OCREF clear source
3
1
read-write
B_0x0
OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1.OCREF_CLR
0x0
B_0x1
OCREF_CLR_INT is connected to ETRF
0x1
SMS1
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0
3
read-write
B_0x0
Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.
0x0
B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x1
B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x2
B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x3
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
0x8
SMS2
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
16
1
read-write
B_0x0
Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.
0x0
B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x1
B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x2
B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x3
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
0x8
TS1
Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
4
3
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
B_0x7
External Trigger input (ETRF)
0x7
B_0x8
Internal Trigger 4 (ITR4)
0x8
B_0x9
Internal Trigger 5 (ITR5)
0x9
B_0xA
Internal Trigger 6 (ITR6)
0xA
B_0xB
Internal Trigger 7 (ITR7)
0xB
B_0xC
Internal Trigger 8 (ITR8)
0xC
TS2
Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
20
2
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
B_0x7
External Trigger input (ETRF)
0x7
B_0x8
Internal Trigger 4 (ITR4)
0x8
B_0x9
Internal Trigger 5 (ITR5)
0x9
B_0xA
Internal Trigger 6 (ITR6)
0xA
B_0xB
Internal Trigger 7 (ITR7)
0xB
B_0xC
Internal Trigger 8 (ITR8)
0xC
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CC1IF
Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
1
1
read-write
B_0x0
No compare match / No input capture occurred
0x0
B_0x1
A compare match or an input capture occurred
0x1
CC1OF
Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
9
1
read-write
B_0x0
No overcapture has been detected.
0x0
B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
0x1
CC2IF
Capture/Compare 2 interrupt flag Refer to CC1IF description
2
1
read-write
CC2OF
Capture/compare 2 overcapture flag refer to CC1OF description
10
1
read-write
CC3IF
Capture/Compare 3 interrupt flag Refer to CC1IF description
3
1
read-write
CC3OF
Capture/Compare 3 overcapture flag refer to CC1OF description
11
1
read-write
CC4IF
Capture/Compare 4 interrupt flag Refer to CC1IF description
4
1
read-write
CC4OF
Capture/Compare 4 overcapture flag refer to CC1OF description
12
1
read-write
TIF
Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
6
1
read-write
B_0x0
No trigger event occurred.
0x0
B_0x1
Trigger interrupt pending.
0x1
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TISEL
TISEL
TIM alternate function option register 1
0x68
32
read-write
n
0x0
0xFFFFFFFF
TI1SEL
TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved
0
4
read-write
B_0x0
TIM2_CH1 input
0x0
B_0x1
COMP1 output
0x1
TI2SEL
TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved
8
4
read-write
B_0x0
TIM2_CH2 input
0x0
B_0x1
COMP2 output
0x1
TIM3
General-purpose-timers
TIM
0x40000400
0x0
0x400
registers
n
TIM3
TIM3 global interrupt
16
AF1
AF1
TIM alternate function option register 1
0x60
32
read-write
n
0x0
0xFFFFFFFF
ETRSEL
ETR source selection These bits select the ETR input source. Others: Reserved
14
4
read-write
B_0x0
ETR legacy mode
0x0
B_0x1
COMP1
0x1
B_0x2
COMP2
0x2
B_0x3
LSE
0x3
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
ARR
High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0
32
read-write
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable.
0
1
read-write
B_0x0
Capture mode disabled / OC1 is not active
0x0
B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
0x1
CC1NP
Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description.
3
1
read-write
CC1P
Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used.
1
1
read-write
B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x0
B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
0x1
CC2E
Capture/Compare 2 output enable. Refer to CC1E description
4
1
read-write
CC2NP
Capture/Compare 2 output Polarity. Refer to CC1NP description
7
1
read-write
CC2P
Capture/Compare 2 output Polarity. refer to CC1P description
5
1
read-write
CC3E
Capture/Compare 3 output enable. Refer to CC1E description
8
1
read-write
CC3NP
Capture/Compare 3 output Polarity. Refer to CC1NP description
11
1
read-write
CC3P
Capture/Compare 3 output Polarity. Refer to CC1P description
9
1
read-write
CC4E
Capture/Compare 4 output enable. refer to CC1E description
12
1
read-write
CC4NP
Capture/Compare 4 output Polarity. Refer to CC1NP description
15
1
read-write
CC4P
Capture/Compare 4 output Polarity. Refer to CC1P description
13
1
read-write
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0
2
read-write
B_0x0
CC1 channel is configured as output
0x0
B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x1
B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2
0x2
B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC2S
Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
8
2
read-write
B_0x0
CC2 channel is configured as output.
0x0
B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2.
0x1
B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1.
0x2
B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
OC1CE
Output compare 1 clear enable
7
1
read-write
B_0x0
OC1Ref is not affected by the ETRF input
0x0
B_0x1
OC1Ref is cleared as soon as a High level is detected on ETRF input
0x1
OC1FE
Output compare 1 fast enable
2
1
OC1M1
Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
4
3
read-write
B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
0x0
B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x1
B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2
B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x3
B_0x4
Force inactive level - OC1REF is forced low.
0x4
B_0x5
Force active level - OC1REF is forced high.
0x5
B_0x6
PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=1).
0x6
B_0x7
PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive.
0x7
B_0x8
Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x8
B_0x9
Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0x9
B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xC
B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
0xD
B_0xE
Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xE
B_0xF
Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.
0xF
OC1M_3
Output Compare 1 mode - bit 3
16
1
OC1PE
Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
3
1
read-write
B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x0
B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
0x1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2M_3
Output Compare 2 mode - bit 3
24
1
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0
2
read-write
B_0x0
CC3 channel is configured as output
0x0
B_0x1
CC3 channel is configured as input, IC3 is mapped on TI3
0x1
B_0x2
CC3 channel is configured as input, IC3 is mapped on TI4
0x2
B_0x3
CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
CC4S
Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
8
2
read-write
B_0x0
CC4 channel is configured as output
0x0
B_0x1
CC4 channel is configured as input, IC4 is mapped on TI4
0x1
B_0x2
CC4 channel is configured as input, IC4 is mapped on TI3
0x2
B_0x3
CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
0x3
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3M_3
Output Compare 3 mode - bit 3
16
1
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4M_3
Output Compare 4 mode - bit 3
24
1
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed.
0
32
read-write
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2
High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed.
0
32
read-write
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3
High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed.
0
32
read-write
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4
High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed.
0
32
read-write
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CNT_ALTERNATE5
CNT_ALTERNATE5
counter
CNT
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
Most significant part counter value (TIM2) nullLeast significant part of counter value
0
31
read-write
UIFCPY
UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register
31
1
read-write
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered
0x0
B_0x1
TIMx_ARR register is buffered
0x1
CEN
Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
CKD
Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
8
2
read-write
B_0x0
tDTS = tCK_INT
0x0
B_0x1
tDTS = 2 Ã tCK_INT
0x1
B_0x2
tDTS = 4 Ã tCK_INT
0x2
CMS
Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
5
2
read-write
B_0x0
Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x0
B_0x1
Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x1
B_0x2
Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x2
B_0x3
Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
0x3
DIR
Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
4
1
read-write
B_0x0
Counter used as upcounter
0x0
B_0x1
Counter used as downcounter
0x1
OPM
One-pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
0x1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
read-write
B_0x0
CCx DMA request sent when CCx event occurs
0x0
B_0x1
CCx DMA requests sent when update event occurs
0x1
MMS
Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
4
3
read-write
B_0x0
Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x0
B_0x1
Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.
0x1
B_0x2
Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x2
B_0x3
Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
0x3
B_0x4
Compare - OC1REFC signal is used as trigger output (TRGO)
0x4
B_0x5
Compare - OC2REFC signal is used as trigger output (TRGO)
0x5
B_0x6
Compare - OC3REFC signal is used as trigger output (TRGO)
0x6
B_0x7
Compare - OC4REFC signal is used as trigger output (TRGO)
0x7
TI1S
TI1 selection
7
1
read-write
B_0x0
The TIMx_CH1 pin is connected to TI1 input
0x0
B_0x1
The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also
0x1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0
5
read-write
B_0x0
TIMx_CR1
0x0
B_0x1
TIMx_CR2
0x1
B_0x2
TIMx_SMCR
0x2
DBL
DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
8
5
read-write
B_0x0
1 transfer,
0x0
B_0x1
2 transfers,
0x1
B_0x11
18 transfers.
0x11
B_0x2
3 transfers,
0x2
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CC1DE
Capture/Compare 1 DMA request enable
9
1
read-write
B_0x0
CC1 DMA request disabled.
0x0
B_0x1
CC1 DMA request enabled.
0x1
CC1IE
Capture/Compare 1 interrupt enable
1
1
read-write
B_0x0
CC1 interrupt disabled.
0x0
B_0x1
CC1 interrupt enabled.
0x1
CC2DE
Capture/Compare 2 DMA request enable
10
1
read-write
B_0x0
CC2 DMA request disabled.
0x0
B_0x1
CC2 DMA request enabled.
0x1
CC2IE
Capture/Compare 2 interrupt enable
2
1
read-write
B_0x0
CC2 interrupt disabled.
0x0
B_0x1
CC2 interrupt enabled.
0x1
CC3DE
Capture/Compare 3 DMA request enable
11
1
read-write
B_0x0
CC3 DMA request disabled.
0x0
B_0x1
CC3 DMA request enabled.
0x1
CC3IE
Capture/Compare 3 interrupt enable
3
1
read-write
B_0x0
CC3 interrupt disabled.
0x0
B_0x1
CC3 interrupt enabled.
0x1
CC4DE
Capture/Compare 4 DMA request enable
12
1
read-write
B_0x0
CC4 DMA request disabled.
0x0
B_0x1
CC4 DMA request enabled.
0x1
CC4IE
Capture/Compare 4 interrupt enable
4
1
read-write
B_0x0
CC4 interrupt disabled.
0x0
B_0x1
CC4 interrupt enabled.
0x1
TDE
Trigger DMA request enable
14
1
read-write
B_0x0
Trigger DMA request disabled.
0x0
B_0x1
Trigger DMA request enabled.
0x1
TIE
Trigger interrupt enable
6
1
read-write
B_0x0
Trigger interrupt disabled.
0x0
B_0x1
Trigger interrupt enabled.
0x1
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled.
0x0
B_0x1
Update DMA request enabled.
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled.
0x0
B_0x1
Update interrupt enabled.
0x1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
CC1G
Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
1
1
write-only
B_0x0
No action
0x0
B_0x1
A capture/compare event is generated on channel 1:
0x1
CC2G
Capture/compare 2 generation Refer to CC1G description
2
1
write-only
CC3G
Capture/compare 3 generation Refer to CC1G description
3
1
write-only
CC4G
Capture/compare 4 generation Refer to CC1G description
4
1
write-only
TG
Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
6
1
write-only
B_0x0
No action
0x0
B_0x1
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
0x1
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action
0x0
B_0x1
Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
0x1
OR1
OR1
TIM option register
0x50
32
read-write
n
0x0
0xFFFFFFFF
OCREF_CLR
Ocref_clr source selection This bit selects the ocref_clr input source.
0
1
read-write
B_0x0
COMP1 output is connected to the OCREF_CLR input
0x0
B_0x1
COMP2 output is connected to the OCREF_CLR input
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
14
1
read-write
B_0x0
External clock mode 2 disabled
0x0
B_0x1
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
0x1
ETF
External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
8
4
read-write
B_0x0
No filter, sampling is done at fDTS
0x0
B_0x1
fSAMPLING=fCK_INT, N=2
0x1
B_0x2
fSAMPLING=fCK_INT, N=4
0x2
B_0x3
fSAMPLING=fCK_INT, N=8
0x3
B_0x4
fSAMPLING=fDTS/2, N=6
0x4
B_0x5
fSAMPLING=fDTS/2, N=8
0x5
B_0x6
fSAMPLING=fDTS/4, N=6
0x6
B_0x7
fSAMPLING=fDTS/4, N=8
0x7
B_0x8
fSAMPLING=fDTS/8, N=6
0x8
B_0x9
fSAMPLING=fDTS/8, N=8
0x9
B_0xA
fSAMPLING=fDTS/16, N=5
0xA
B_0xB
fSAMPLING=fDTS/16, N=6
0xB
B_0xC
fSAMPLING=fDTS/16, N=8
0xC
B_0xD
fSAMPLING=fDTS/32, N=5
0xD
B_0xE
fSAMPLING=fDTS/32, N=6
0xE
B_0xF
fSAMPLING=fDTS/32, N=8
0xF
ETP
External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
15
1
read-write
B_0x0
ETR is non-inverted, active at high level or rising edge
0x0
B_0x1
ETR is inverted, active at low level or falling edge
0x1
ETPS
External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
12
2
read-write
B_0x0
Prescaler OFF
0x0
B_0x1
ETRP frequency divided by 2
0x1
B_0x2
ETRP frequency divided by 4
0x2
B_0x3
ETRP frequency divided by 8
0x3
MSM
Master/Slave mode
7
1
read-write
B_0x0
No action
0x0
B_0x1
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
0x1
OCCS
OCREF clear selection This bit is used to select the OCREF clear source
3
1
read-write
B_0x0
OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1.OCREF_CLR
0x0
B_0x1
OCREF_CLR_INT is connected to ETRF
0x1
SMS1
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0
3
read-write
B_0x0
Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.
0x0
B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x1
B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x2
B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x3
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
0x8
SMS2
Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
16
1
read-write
B_0x0
Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.
0x0
B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x1
B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x2
B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x3
B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x4
B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x5
B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x6
B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x7
B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
0x8
TS1
Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
4
3
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
B_0x7
External Trigger input (ETRF)
0x7
B_0x8
Internal Trigger 4 (ITR4)
0x8
B_0x9
Internal Trigger 5 (ITR5)
0x9
B_0xA
Internal Trigger 6 (ITR6)
0xA
B_0xB
Internal Trigger 7 (ITR7)
0xB
B_0xC
Internal Trigger 8 (ITR8)
0xC
TS2
Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
20
2
read-write
B_0x0
Internal Trigger 0 (ITR0)
0x0
B_0x1
Internal Trigger 1 (ITR1)
0x1
B_0x2
Internal Trigger 2 (ITR2)
0x2
B_0x3
Internal Trigger 3 (ITR3)
0x3
B_0x4
TI1 Edge Detector (TI1F_ED)
0x4
B_0x5
Filtered Timer Input 1 (TI1FP1)
0x5
B_0x6
Filtered Timer Input 2 (TI2FP2)
0x6
B_0x7
External Trigger input (ETRF)
0x7
B_0x8
Internal Trigger 4 (ITR4)
0x8
B_0x9
Internal Trigger 5 (ITR5)
0x9
B_0xA
Internal Trigger 6 (ITR6)
0xA
B_0xB
Internal Trigger 7 (ITR7)
0xB
B_0xC
Internal Trigger 8 (ITR8)
0xC
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CC1IF
Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
1
1
read-write
B_0x0
No compare match / No input capture occurred
0x0
B_0x1
A compare match or an input capture occurred
0x1
CC1OF
Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
9
1
read-write
B_0x0
No overcapture has been detected.
0x0
B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
0x1
CC2IF
Capture/Compare 2 interrupt flag Refer to CC1IF description
2
1
read-write
CC2OF
Capture/compare 2 overcapture flag refer to CC1OF description
10
1
read-write
CC3IF
Capture/Compare 3 interrupt flag Refer to CC1IF description
3
1
read-write
CC3OF
Capture/Compare 3 overcapture flag refer to CC1OF description
11
1
read-write
CC4IF
Capture/Compare 4 interrupt flag Refer to CC1IF description
4
1
read-write
CC4OF
Capture/Compare 4 overcapture flag refer to CC1OF description
12
1
read-write
TIF
Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
6
1
read-write
B_0x0
No trigger event occurred.
0x0
B_0x1
Trigger interrupt pending.
0x1
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TISEL
TISEL
TIM alternate function option register 1
0x68
32
read-write
n
0x0
0xFFFFFFFF
TI1SEL
TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved
0
4
read-write
B_0x0
TIM2_CH1 input
0x0
B_0x1
COMP1 output
0x1
TI2SEL
TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved
8
4
read-write
B_0x0
TIM2_CH2 input
0x0
B_0x1
COMP2 output
0x1
TIM6
Basic timers
TIM
0x40001000
0x0
0x400
registers
n
TIM6_DAC
TIM6 + LPTIM1 and DAC global interrupt
17
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0xFFFF
0xFFFFFFFF
ARR
Prescaler value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
Counter value
0
16
read-write
UIFCPY
UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered.
0x0
B_0x1
TIMx_ARR register is buffered.
0x1
CEN
Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
OPM
One-pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the CEN bit).
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generates an update interrupt or DMA request if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
0x1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
MMS
Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
4
3
read-write
B_0x0
Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x0
B_0x1
Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
0x1
B_0x2
Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x2
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled.
0x0
B_0x1
Update DMA request enabled.
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled.
0x0
B_0x1
Update interrupt enabled.
0x1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action.
0x0
B_0x1
Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred.
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
TIM7
Basic timers
TIM
0x40001400
0x0
0x400
registers
n
TIM7
TIM7 + LPTIM2 global interrupt
18
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0xFFFF
0xFFFFFFFF
ARR
Prescaler value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
Counter value
0
16
read-write
UIFCPY
UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
read-write
B_0x0
TIMx_ARR register is not buffered.
0x0
B_0x1
TIMx_ARR register is buffered.
0x1
CEN
Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0
1
read-write
B_0x0
Counter disabled
0x0
B_0x1
Counter enabled
0x1
OPM
One-pulse mode
3
1
read-write
B_0x0
Counter is not stopped at update event
0x0
B_0x1
Counter stops counting at the next update event (clearing the CEN bit).
0x1
UDIS
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
1
1
read-write
B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x0
B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
0x1
UIFREMAP
UIF status bit remapping
11
1
read-write
B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x0
B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
0x1
URS
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
2
1
read-write
B_0x0
Any of the following events generates an update interrupt or DMA request if enabled. These events can be:
0x0
B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
0x1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
MMS
Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
4
3
read-write
B_0x0
Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x0
B_0x1
Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
0x1
B_0x2
Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x2
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
UDE
Update DMA request enable
8
1
read-write
B_0x0
Update DMA request disabled.
0x0
B_0x1
Update DMA request enabled.
0x1
UIE
Update interrupt enable
0
1
read-write
B_0x0
Update interrupt disabled.
0x0
B_0x1
Update interrupt enabled.
0x1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
UG
Update generation This bit can be set by software, it is automatically cleared by hardware.
0
1
write-only
B_0x0
No action.
0x0
B_0x1
Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).
0x1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
UIF
Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.
0
1
read-write
B_0x0
No update occurred.
0x0
B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
0x1
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x40013800
0x0
0x400
registers
n
USART1
USART1 global interrupt
27
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR
USART baud rate
0
16
read-write
CR1_FIFO_DISABLED
CR1_FIFO_DISABLED
Control register 1
CR1_FIFO_ENABLED
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable This bit is set and cleared by software.
14
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the CMF bit is set in the USART_ISR register.
0x1
DEAT
Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
21
5
read-write
DEDT
Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
16
5
read-write
EOBIE
End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
27
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the EOBF flag is set in the USART_ISR register
0x1
FIFOEN
FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
29
1
read-write
B_0x0
FIFO mode is disabled.
0x0
B_0x1
FIFO mode is enabled.
0x1
IDLEIE
IDLE interrupt enable This bit is set and cleared by software.
4
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever IDLE = 1 in the USART_ISR register
0x1
M0
Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
12
1
read-write
M1
Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
28
1
read-write
MME
Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
13
1
read-write
B_0x0
Receiver in active mode permanently
0x0
B_0x1
Receiver can switch between Mute mode and active mode.
0x1
OVER8
Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
15
1
read-write
B_0x0
Oversampling by 16
0x0
B_0x1
Oversampling by 8
0x1
PCE
Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
10
1
read-write
B_0x0
Parity control disabled
0x0
B_0x1
Parity control enabled
0x1
PEIE
PE interrupt enable This bit is set and cleared by software.
8
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever PE = 1 in the USART_ISR register
0x1
PS
Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
9
1
read-write
B_0x0
Even parity
0x0
B_0x1
Odd parity
0x1
RE
Receiver enable This bit enables the receiver. It is set and cleared by software.
2
1
read-write
B_0x0
Receiver is disabled
0x0
B_0x1
Receiver is enabled and begins searching for a start bit
0x1
RTOIE
Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
26
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the RTOF bit is set in the USART_ISR register.
0x1
RXNEIE
Receive data register not empty This bit is set and cleared by software.
5
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register
0x1
TCIE
Transmission complete interrupt enable This bit is set and cleared by software.
6
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TC = 1 in the USART_ISR register
0x1
TE
Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
3
1
read-write
B_0x0
Transmitter is disabled
0x0
B_0x1
Transmitter is enabled
0x1
TXEIE
Transmit data register empty This bit is set and cleared by software.
7
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TXE =1 in the USART_ISR register
0x1
UE
USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0
1
read-write
B_0x0
USART prescaler and outputs disabled, low-power mode
0x0
B_0x1
USART enabled
0x1
UESM
USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
1
1
read-write
B_0x0
USART not able to wake up the MCU from low-power mode.
0x0
B_0x1
USART able to wake up the MCU from low-power mode.
0x1
WAKE
Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
11
1
read-write
B_0x0
Idle line
0x0
B_0x1
Address mark
0x1
CR1_FIFO_ENABLED
CR1_FIFO_ENABLED
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable This bit is set and cleared by software.
14
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the CMF bit is set in the USART_ISR register.
0x1
DEAT
Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
21
5
read-write
DEDT
Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
16
5
read-write
EOBIE
End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
27
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the EOBF flag is set in the USART_ISR register
0x1
FIFOEN
FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
29
1
read-write
B_0x0
FIFO mode is disabled.
0x0
B_0x1
FIFO mode is enabled.
0x1
IDLEIE
IDLE interrupt enable This bit is set and cleared by software.
4
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever IDLE = 1 in the USART_ISR register
0x1
M0
Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
12
1
read-write
M1
Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
28
1
read-write
MME
Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
13
1
read-write
B_0x0
Receiver in active mode permanently
0x0
B_0x1
Receiver can switch between Mute mode and active mode.
0x1
OVER8
Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
15
1
read-write
B_0x0
Oversampling by 16
0x0
B_0x1
Oversampling by 8
0x1
PCE
Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
10
1
read-write
B_0x0
Parity control disabled
0x0
B_0x1
Parity control enabled
0x1
PEIE
PE interrupt enable This bit is set and cleared by software.
8
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever PE = 1 in the USART_ISR register
0x1
PS
Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
9
1
read-write
B_0x0
Even parity
0x0
B_0x1
Odd parity
0x1
RE
Receiver enable This bit enables the receiver. It is set and cleared by software.
2
1
read-write
B_0x0
Receiver is disabled
0x0
B_0x1
Receiver is enabled and begins searching for a start bit
0x1
RTOIE
Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
26
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the RTOF bit is set in the USART_ISR register.
0x1
RXFFIE
RXFIFO Full interrupt enable This bit is set and cleared by software.
31
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when RXFF = 1 in the USART_ISR register
0x1
RXFNEIE
RXFIFO not empty interrupt enable This bit is set and cleared by software.
5
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register
0x1
TCIE
Transmission complete interrupt enable This bit is set and cleared by software.
6
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TC = 1 in the USART_ISR register
0x1
TE
Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
3
1
read-write
B_0x0
Transmitter is disabled
0x0
B_0x1
Transmitter is enabled
0x1
TXFEIE
TXFIFO empty interrupt enable This bit is set and cleared by software.
30
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when TXFE = 1 in the USART_ISR register
0x1
TXFNFIE
TXFIFO not full interrupt enable This bit is set and cleared by software.
7
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TXFNF =1 in the USART_ISR register
0x1
UE
USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0
1
read-write
B_0x0
USART prescaler and outputs disabled, low-power mode
0x0
B_0x1
USART enabled
0x1
UESM
USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
1
1
read-write
B_0x0
USART not able to wake up the MCU from low-power mode.
0x0
B_0x1
USART able to wake up the MCU from low-power mode.
0x1
WAKE
Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
11
1
read-write
B_0x0
Idle line
0x0
B_0x1
Address mark
0x1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ABREN
Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
20
1
read-write
B_0x0
Auto baud rate detection is disabled.
0x0
B_0x1
Auto baud rate detection is enabled.
0x1
ABRMOD
Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
21
2
read-write
B_0x0
Measurement of the start bit is used to detect the baud rate.
0x0
B_0x1
Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x1
B_0x2
0x7F frame detection.
0x2
B_0x3
0x55 frame detection
0x3
ADD
Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0).
24
8
read-write
ADDM7
7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
4
1
read-write
B_0x0
4-bit address detection
0x0
B_0x1
7-bit address detection (in 8-bit data mode)
0x1
CLKEN
Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
11
1
read-write
B_0x0
SCLK pin disabled
0x0
B_0x1
SCLK pin enabled
0x1
CPHA
Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
9
1
read-write
B_0x0
The first clock transition is the first data capture edge
0x0
B_0x1
The second clock transition is the first data capture edge
0x1
CPOL
Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
10
1
read-write
B_0x0
Steady low value on SCLK pin outside transmission window
0x0
B_0x1
Steady high value on SCLK pin outside transmission window
0x1
DATAINV
Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
18
1
read-write
B_0x0
Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x0
B_0x1
Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
0x1
DIS_NSS
When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
3
1
read-write
B_0x0
SPI slave selection depends on NSS input pin.
0x0
B_0x1
SPI slave is always selected and NSS input pin is ignored.
0x1
LBCL
Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
1
read-write
B_0x0
The clock pulse of the last data bit is not output to the SCLK pin
0x0
B_0x1
The clock pulse of the last data bit is output to the SCLK pin
0x1
LBDIE
LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
6
1
read-write
B_0x0
Interrupt is inhibited
0x0
B_0x1
An interrupt is generated whenever LBDF = 1 in the USART_ISR register
0x1
LBDL
LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
5
1
read-write
B_0x0
10-bit break detection
0x0
B_0x1
11-bit break detection
0x1
LINEN
LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
14
1
read-write
B_0x0
LIN mode disabled
0x0
B_0x1
LIN mode enabled
0x1
MSBFIRST
Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
19
1
read-write
B_0x0
data is transmitted/received with data bit 0 first, following the start bit.
0x0
B_0x1
data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
0x1
RTOEN
Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
23
1
read-write
B_0x0
Receiver timeout feature disabled.
0x0
B_0x1
Receiver timeout feature enabled.
0x1
RXINV
RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
16
1
read-write
B_0x0
RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x0
B_0x1
RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
0x1
SLVEN
Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0
1
read-write
B_0x0
Slave mode disabled.
0x0
B_0x1
Slave mode enabled.
0x1
STOP
stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
12
2
read-write
B_0x0
1 stop bit
0x0
B_0x1
0.5 stop bit.
0x1
B_0x2
2 stop bits
0x2
B_0x3
1.5 stop bits
0x3
SWAP
Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
15
1
read-write
B_0x0
TX/RX pins are used as defined in standard pinout
0x0
B_0x1
The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
0x1
TXINV
TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
17
1
read-write
B_0x0
TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x0
B_0x1
TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
0x1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
9
1
read-write
B_0x0
CTS hardware flow control disabled
0x0
B_0x1
CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
0x1
CTSIE
CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
10
1
read-write
B_0x0
Interrupt is inhibited
0x0
B_0x1
An interrupt is generated whenever CTSIF = 1 in the USART_ISR register
0x1
DDRE
DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
13
1
read-write
B_0x0
DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x0
B_0x1
DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
0x1
DEM
Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
14
1
read-write
B_0x0
DE function is disabled.
0x0
B_0x1
DE function is enabled. The DE signal is output on the RTS pin.
0x1
DEP
Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
15
1
read-write
B_0x0
DE signal is active high.
0x0
B_0x1
DE signal is active low.
0x1
DMAR
DMA enable receiver This bit is set/reset by software
6
1
read-write
B_0x0
DMA mode is disabled for reception
0x0
B_0x1
DMA mode is enabled for reception
0x1
DMAT
DMA enable transmitter This bit is set/reset by software
7
1
read-write
B_0x0
DMA mode is disabled for transmission
0x0
B_0x1
DMA mode is enabled for transmission
0x1
EIE
Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register).
0
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
0x1
HDSEL
Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0).
3
1
read-write
B_0x0
Half duplex mode is not selected
0x0
B_0x1
Half duplex mode is selected
0x1
IREN
IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
1
1
read-write
B_0x0
IrDA disabled
0x0
B_0x1
IrDA enabled
0x1
IRLP
IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
2
1
read-write
B_0x0
Normal mode
0x0
B_0x1
Low-power mode
0x1
NACK
Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
4
1
read-write
B_0x0
NACK transmission in case of parity error is disabled
0x0
B_0x1
NACK transmission during parity error is enabled
0x1
ONEBIT
One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0).
11
1
read-write
B_0x0
Three sample bit method
0x0
B_0x1
One sample bit method
0x1
OVRDIS
Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data
12
1
read-write
B_0x0
Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x0
B_0x1
Overrun functionality is disabled. If new data is received while the RXNE flag is still set
0x1
RTSE
RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
1
read-write
B_0x0
RTS hardware flow control disabled
0x0
B_0x1
RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
0x1
RXFTCFG
Receive FIFO threshold configuration Remaining combinations: Reserved
25
3
read-write
B_0x0
Receive FIFO reaches 1/8 of its depth
0x0
B_0x1
Receive FIFO reaches 1/4 of its depth
0x1
B_0x2
Receive FIFO reaches 1/2 of its depth
0x2
B_0x3
Receive FIFO reaches 3/4 of its depth
0x3
B_0x4
Receive FIFO reaches 7/8 of its depth
0x4
B_0x5
Receive FIFO becomes full
0x5
RXFTIE
RXFIFO threshold interrupt enable This bit is set and cleared by software.
28
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.
0x1
SCARCNT
Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
17
3
read-write
B_0x0
retransmission disabled - No automatic retransmission in transmit mode.
0x0
B_0x1
number of automatic retransmission attempts (before signaling error)
0x1
B_0x2
number of automatic retransmission attempts (before signaling error)
0x2
B_0x3
number of automatic retransmission attempts (before signaling error)
0x3
B_0x4
number of automatic retransmission attempts (before signaling error)
0x4
B_0x5
number of automatic retransmission attempts (before signaling error)
0x5
B_0x6
number of automatic retransmission attempts (before signaling error)
0x6
B_0x7
number of automatic retransmission attempts (before signaling error)
0x7
SCEN
Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
5
1
read-write
B_0x0
Smartcard Mode disabled
0x0
B_0x1
Smartcard Mode enabled
0x1
TCBGTIE
Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
24
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TCBGT=1 in the USART_ISR register
0x1
TXFTCFG
TXFIFO threshold configuration Remaining combinations: Reserved
29
3
read-write
B_0x0
TXFIFO reaches 1/8 of its depth
0x0
B_0x1
TXFIFO reaches 1/4 of its depth
0x1
B_0x2
TXFIFO reaches 1/2 of its depth
0x2
B_0x3
TXFIFO reaches 3/4 of its depth
0x3
B_0x4
TXFIFO reaches 7/8 of its depth
0x4
B_0x5
TXFIFO becomes empty
0x5
TXFTIE
TXFIFO threshold interrupt enable This bit is set and cleared by software.
23
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.
0x1
WUFIE
Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
22
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever WUF = 1 in the USART_ISR register
0x1
WUS
Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
20
2
read-write
B_0x0
WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x0
B_0x2
WUF active on start bit detection
0x2
B_0x3
WUF active on RXNE/RXFNE.
0x3
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0xFFFFFFFF
GT
Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
8
read-write
PSC
Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to .
0
8
read-write
B_0x0
Reserved - do not program this value
0x0
B_0x1
Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x1
B_0x1F
Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
0x1F
B_0x2
Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x2
B_0x3
Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x3
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
17
1
write-only
CTSCF
CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
9
1
write-only
EOBCF
End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
12
1
write-only
FECF
Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
1
1
write-only
IDLECF
Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
4
1
write-only
LBDCF
LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
1
write-only
NECF
Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
2
1
write-only
ORECF
Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
3
1
write-only
PECF
Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0
1
write-only
RTOCF
Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835.
11
1
write-only
TCBGTCF
Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
7
1
write-only
TCCF
Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
6
1
write-only
TXFECF
TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
5
1
write-only
UDRCF
SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
13
1
write-only
WUCF
Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
20
1
write-only
ISR_FIFO_DISABLED
ISR_FIFO_DISABLED
Interrupt and status register
ISR_FIFO_ENABLED
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
ABRE
Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
14
1
read-only
ABRF
Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
15
1
read-only
BUSY
Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
16
1
read-only
B_0x0
USART is idle (no reception)
0x0
B_0x1
Reception on going
0x1
CMF
Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
17
1
read-only
B_0x0
No Character match detected
0x0
B_0x1
Character Match detected
0x1
CTS
CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
10
1
read-only
B_0x0
nCTS line set
0x0
B_0x1
nCTS line reset
0x1
CTSIF
CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
9
1
read-only
B_0x0
No change occurred on the nCTS status line
0x0
B_0x1
A change occurred on the nCTS status line
0x1
EOBF
End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
12
1
read-only
B_0x0
End of Block not reached
0x0
B_0x1
End of Block (number of characters) reached
0x1
FE
Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register.
1
1
read-only
B_0x0
No Framing error is detected
0x0
B_0x1
Framing error or break character is detected
0x1
IDLE
Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
4
1
read-only
B_0x0
No Idle line is detected
0x0
B_0x1
Idle line is detected
0x1
LBDF
LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
8
1
read-only
B_0x0
LIN Break not detected
0x0
B_0x1
LIN break detected
0x1
NE
Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861).
2
1
read-only
B_0x0
No noise is detected
0x0
B_0x1
Noise is detected
0x1
ORE
Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
3
1
read-only
B_0x0
No overrun error
0x0
B_0x1
Overrun error is detected
0x1
PE
Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0
1
read-only
B_0x0
No parity error
0x0
B_0x1
Parity error
0x1
REACK
Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
22
1
read-only
RTOF
Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
11
1
read-only
B_0x0
Timeout value not reached
0x0
B_0x1
Timeout value reached without any data reception
0x1
RWU
Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
19
1
read-only
B_0x0
Receiver in active mode
0x0
B_0x1
Receiver in Mute mode
0x1
RXNE
Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register.
5
1
read-only
B_0x0
Data is not received
0x0
B_0x1
Received data is ready to be read.
0x1
SBKF
Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
18
1
read-only
B_0x0
Break character transmitted
0x0
B_0x1
Break character requested by setting SBKRQ bit in USART_RQR register
0x1
TC
Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
6
1
read-only
B_0x0
Transmission is not complete
0x0
B_0x1
Transmission is complete
0x1
TCBGT
Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835.
25
1
read-only
B_0x0
Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x0
B_0x1
Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
0x1
TEACK
Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
21
1
read-only
TXE
Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register.
7
1
read-only
B_0x0
Data register full
0x0
B_0x1
Data register not full
0x1
UDR
SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
13
1
read-only
B_0x0
No underrun error
0x0
B_0x1
underrun error
0x1
WUF
Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
20
1
read-only
ISR_FIFO_ENABLED
ISR_FIFO_ENABLED
Interrupt and status register
0x1C
32
read-only
n
0x8000C0
0xFFFFFFFF
ABRE
Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
14
1
read-only
ABRF
Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
15
1
read-only
BUSY
Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
16
1
read-only
B_0x0
USART is idle (no reception)
0x0
B_0x1
Reception on going
0x1
CMF
Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
17
1
read-only
B_0x0
No Character match detected
0x0
B_0x1
Character Match detected
0x1
CTS
CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
10
1
read-only
B_0x0
nCTS line set
0x0
B_0x1
nCTS line reset
0x1
CTSIF
CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
9
1
read-only
B_0x0
No change occurred on the nCTS status line
0x0
B_0x1
A change occurred on the nCTS status line
0x1
EOBF
End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
12
1
read-only
B_0x0
End of Block not reached
0x0
B_0x1
End of Block (number of characters) reached
0x1
FE
Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
1
1
read-only
B_0x0
No Framing error is detected
0x0
B_0x1
Framing error or break character is detected
0x1
IDLE
Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
4
1
read-only
B_0x0
No Idle line is detected
0x0
B_0x1
Idle line is detected
0x1
LBDF
LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
8
1
read-only
B_0x0
LIN Break not detected
0x0
B_0x1
LIN break detected
0x1
NE
Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR.
2
1
read-only
B_0x0
No noise is detected
0x0
B_0x1
Noise is detected
0x1
ORE
Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
3
1
read-only
B_0x0
No overrun error
0x0
B_0x1
Overrun error is detected
0x1
PE
Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0
1
read-only
B_0x0
No parity error
0x0
B_0x1
Parity error
0x1
REACK
Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
22
1
read-only
RTOF
Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
11
1
read-only
B_0x0
Timeout value not reached
0x0
B_0x1
Timeout value reached without any data reception
0x1
RWU
Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
19
1
read-only
B_0x0
Receiver in active mode
0x0
B_0x1
Receiver in Mute mode
0x1
RXFF
RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register.
24
1
read-only
B_0x0
RXFIFO not full.
0x0
B_0x1
RXFIFO Full.
0x1
RXFNE
RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register.
5
1
read-only
B_0x0
Data is not received
0x0
B_0x1
Received data is ready to be read.
0x1
RXFT
RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
26
1
read-only
B_0x0
Receive FIFO does not reach the programmed threshold.
0x0
B_0x1
Receive FIFO reached the programmed threshold.
0x1
SBKF
Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
18
1
read-only
B_0x0
Break character transmitted
0x0
B_0x1
Break character requested by setting SBKRQ bit in USART_RQR register
0x1
TC
Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
6
1
read-only
B_0x0
Transmission is not complete
0x0
B_0x1
Transmission is complete
0x1
TCBGT
Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835.
25
1
read-only
B_0x0
Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x0
B_0x1
Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
0x1
TEACK
Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
21
1
read-only
TXFE
TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register.
23
1
read-only
B_0x0
TXFIFO not empty.
0x0
B_0x1
TXFIFO empty.
0x1
TXFNF
TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
7
1
read-only
B_0x0
Transmit FIFO is full
0x0
B_0x1
Transmit FIFO is not full
0x1
TXFT
TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register.
27
1
read-only
B_0x0
TXFIFO does not reach the programmed threshold.
0x0
B_0x1
TXFIFO reached the programmed threshold.
0x1
UDR
SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
13
1
read-only
B_0x0
No underrun error
0x0
B_0x1
underrun error
0x1
WUF
Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
20
1
read-only
PRESC
PRESC
Prescaler register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0
4
read-write
B_0x0
input clock not divided
0x0
B_0x1
input clock divided by 2
0x1
B_0x2
input clock divided by 4
0x2
B_0x3
input clock divided by 6
0x3
B_0x4
input clock divided by 8
0x4
B_0x5
input clock divided by 10
0x5
B_0x6
input clock divided by 12
0x6
B_0x7
input clock divided by 16
0x7
B_0x8
input clock divided by 32
0x8
B_0x9
input clock divided by 64
0x9
B_0xA
input clock divided by 128
0xA
B_0xB
input clock divided by 256
0xB
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
ABRRQ
Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0
1
write-only
MMRQ
Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
2
1
write-only
RXFRQ
Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
3
1
write-only
SBKRQ
Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
1
1
write-only
TXFRQ
Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
4
1
write-only
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x40004400
0x0
0x400
registers
n
USART2
USART2 global interrupt
28
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR
USART baud rate
0
16
read-write
CR1_FIFO_DISABLED
CR1_FIFO_DISABLED
Control register 1
CR1_FIFO_ENABLED
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable This bit is set and cleared by software.
14
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the CMF bit is set in the USART_ISR register.
0x1
DEAT
Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
21
5
read-write
DEDT
Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
16
5
read-write
EOBIE
End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
27
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the EOBF flag is set in the USART_ISR register
0x1
FIFOEN
FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
29
1
read-write
B_0x0
FIFO mode is disabled.
0x0
B_0x1
FIFO mode is enabled.
0x1
IDLEIE
IDLE interrupt enable This bit is set and cleared by software.
4
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever IDLE = 1 in the USART_ISR register
0x1
M0
Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
12
1
read-write
M1
Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
28
1
read-write
MME
Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
13
1
read-write
B_0x0
Receiver in active mode permanently
0x0
B_0x1
Receiver can switch between Mute mode and active mode.
0x1
OVER8
Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
15
1
read-write
B_0x0
Oversampling by 16
0x0
B_0x1
Oversampling by 8
0x1
PCE
Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
10
1
read-write
B_0x0
Parity control disabled
0x0
B_0x1
Parity control enabled
0x1
PEIE
PE interrupt enable This bit is set and cleared by software.
8
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever PE = 1 in the USART_ISR register
0x1
PS
Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
9
1
read-write
B_0x0
Even parity
0x0
B_0x1
Odd parity
0x1
RE
Receiver enable This bit enables the receiver. It is set and cleared by software.
2
1
read-write
B_0x0
Receiver is disabled
0x0
B_0x1
Receiver is enabled and begins searching for a start bit
0x1
RTOIE
Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
26
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the RTOF bit is set in the USART_ISR register.
0x1
RXNEIE
Receive data register not empty This bit is set and cleared by software.
5
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register
0x1
TCIE
Transmission complete interrupt enable This bit is set and cleared by software.
6
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TC = 1 in the USART_ISR register
0x1
TE
Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
3
1
read-write
B_0x0
Transmitter is disabled
0x0
B_0x1
Transmitter is enabled
0x1
TXEIE
Transmit data register empty This bit is set and cleared by software.
7
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TXE =1 in the USART_ISR register
0x1
UE
USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0
1
read-write
B_0x0
USART prescaler and outputs disabled, low-power mode
0x0
B_0x1
USART enabled
0x1
UESM
USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
1
1
read-write
B_0x0
USART not able to wake up the MCU from low-power mode.
0x0
B_0x1
USART able to wake up the MCU from low-power mode.
0x1
WAKE
Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
11
1
read-write
B_0x0
Idle line
0x0
B_0x1
Address mark
0x1
CR1_FIFO_ENABLED
CR1_FIFO_ENABLED
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable This bit is set and cleared by software.
14
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the CMF bit is set in the USART_ISR register.
0x1
DEAT
Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
21
5
read-write
DEDT
Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
16
5
read-write
EOBIE
End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
27
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the EOBF flag is set in the USART_ISR register
0x1
FIFOEN
FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
29
1
read-write
B_0x0
FIFO mode is disabled.
0x0
B_0x1
FIFO mode is enabled.
0x1
IDLEIE
IDLE interrupt enable This bit is set and cleared by software.
4
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever IDLE = 1 in the USART_ISR register
0x1
M0
Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
12
1
read-write
M1
Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
28
1
read-write
MME
Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
13
1
read-write
B_0x0
Receiver in active mode permanently
0x0
B_0x1
Receiver can switch between Mute mode and active mode.
0x1
OVER8
Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
15
1
read-write
B_0x0
Oversampling by 16
0x0
B_0x1
Oversampling by 8
0x1
PCE
Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
10
1
read-write
B_0x0
Parity control disabled
0x0
B_0x1
Parity control enabled
0x1
PEIE
PE interrupt enable This bit is set and cleared by software.
8
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever PE = 1 in the USART_ISR register
0x1
PS
Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
9
1
read-write
B_0x0
Even parity
0x0
B_0x1
Odd parity
0x1
RE
Receiver enable This bit enables the receiver. It is set and cleared by software.
2
1
read-write
B_0x0
Receiver is disabled
0x0
B_0x1
Receiver is enabled and begins searching for a start bit
0x1
RTOIE
Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
26
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when the RTOF bit is set in the USART_ISR register.
0x1
RXFFIE
RXFIFO Full interrupt enable This bit is set and cleared by software.
31
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when RXFF = 1 in the USART_ISR register
0x1
RXFNEIE
RXFIFO not empty interrupt enable This bit is set and cleared by software.
5
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register
0x1
TCIE
Transmission complete interrupt enable This bit is set and cleared by software.
6
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TC = 1 in the USART_ISR register
0x1
TE
Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
3
1
read-write
B_0x0
Transmitter is disabled
0x0
B_0x1
Transmitter is enabled
0x1
TXFEIE
TXFIFO empty interrupt enable This bit is set and cleared by software.
30
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when TXFE = 1 in the USART_ISR register
0x1
TXFNFIE
TXFIFO not full interrupt enable This bit is set and cleared by software.
7
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TXFNF =1 in the USART_ISR register
0x1
UE
USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0
1
read-write
B_0x0
USART prescaler and outputs disabled, low-power mode
0x0
B_0x1
USART enabled
0x1
UESM
USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
1
1
read-write
B_0x0
USART not able to wake up the MCU from low-power mode.
0x0
B_0x1
USART able to wake up the MCU from low-power mode.
0x1
WAKE
Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
11
1
read-write
B_0x0
Idle line
0x0
B_0x1
Address mark
0x1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ABREN
Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
20
1
read-write
B_0x0
Auto baud rate detection is disabled.
0x0
B_0x1
Auto baud rate detection is enabled.
0x1
ABRMOD
Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
21
2
read-write
B_0x0
Measurement of the start bit is used to detect the baud rate.
0x0
B_0x1
Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x1
B_0x2
0x7F frame detection.
0x2
B_0x3
0x55 frame detection
0x3
ADD
Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0).
24
8
read-write
ADDM7
7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
4
1
read-write
B_0x0
4-bit address detection
0x0
B_0x1
7-bit address detection (in 8-bit data mode)
0x1
CLKEN
Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
11
1
read-write
B_0x0
SCLK pin disabled
0x0
B_0x1
SCLK pin enabled
0x1
CPHA
Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
9
1
read-write
B_0x0
The first clock transition is the first data capture edge
0x0
B_0x1
The second clock transition is the first data capture edge
0x1
CPOL
Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
10
1
read-write
B_0x0
Steady low value on SCLK pin outside transmission window
0x0
B_0x1
Steady high value on SCLK pin outside transmission window
0x1
DATAINV
Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
18
1
read-write
B_0x0
Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x0
B_0x1
Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
0x1
DIS_NSS
When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
3
1
read-write
B_0x0
SPI slave selection depends on NSS input pin.
0x0
B_0x1
SPI slave is always selected and NSS input pin is ignored.
0x1
LBCL
Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
1
read-write
B_0x0
The clock pulse of the last data bit is not output to the SCLK pin
0x0
B_0x1
The clock pulse of the last data bit is output to the SCLK pin
0x1
LBDIE
LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
6
1
read-write
B_0x0
Interrupt is inhibited
0x0
B_0x1
An interrupt is generated whenever LBDF = 1 in the USART_ISR register
0x1
LBDL
LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
5
1
read-write
B_0x0
10-bit break detection
0x0
B_0x1
11-bit break detection
0x1
LINEN
LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
14
1
read-write
B_0x0
LIN mode disabled
0x0
B_0x1
LIN mode enabled
0x1
MSBFIRST
Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
19
1
read-write
B_0x0
data is transmitted/received with data bit 0 first, following the start bit.
0x0
B_0x1
data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
0x1
RTOEN
Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
23
1
read-write
B_0x0
Receiver timeout feature disabled.
0x0
B_0x1
Receiver timeout feature enabled.
0x1
RXINV
RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
16
1
read-write
B_0x0
RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x0
B_0x1
RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
0x1
SLVEN
Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0
1
read-write
B_0x0
Slave mode disabled.
0x0
B_0x1
Slave mode enabled.
0x1
STOP
stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
12
2
read-write
B_0x0
1 stop bit
0x0
B_0x1
0.5 stop bit.
0x1
B_0x2
2 stop bits
0x2
B_0x3
1.5 stop bits
0x3
SWAP
Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
15
1
read-write
B_0x0
TX/RX pins are used as defined in standard pinout
0x0
B_0x1
The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
0x1
TXINV
TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
17
1
read-write
B_0x0
TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x0
B_0x1
TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
0x1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
9
1
read-write
B_0x0
CTS hardware flow control disabled
0x0
B_0x1
CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
0x1
CTSIE
CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
10
1
read-write
B_0x0
Interrupt is inhibited
0x0
B_0x1
An interrupt is generated whenever CTSIF = 1 in the USART_ISR register
0x1
DDRE
DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
13
1
read-write
B_0x0
DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x0
B_0x1
DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
0x1
DEM
Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
14
1
read-write
B_0x0
DE function is disabled.
0x0
B_0x1
DE function is enabled. The DE signal is output on the RTS pin.
0x1
DEP
Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
15
1
read-write
B_0x0
DE signal is active high.
0x0
B_0x1
DE signal is active low.
0x1
DMAR
DMA enable receiver This bit is set/reset by software
6
1
read-write
B_0x0
DMA mode is disabled for reception
0x0
B_0x1
DMA mode is enabled for reception
0x1
DMAT
DMA enable transmitter This bit is set/reset by software
7
1
read-write
B_0x0
DMA mode is disabled for transmission
0x0
B_0x1
DMA mode is enabled for transmission
0x1
EIE
Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register).
0
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
0x1
HDSEL
Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0).
3
1
read-write
B_0x0
Half duplex mode is not selected
0x0
B_0x1
Half duplex mode is selected
0x1
IREN
IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
1
1
read-write
B_0x0
IrDA disabled
0x0
B_0x1
IrDA enabled
0x1
IRLP
IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
2
1
read-write
B_0x0
Normal mode
0x0
B_0x1
Low-power mode
0x1
NACK
Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
4
1
read-write
B_0x0
NACK transmission in case of parity error is disabled
0x0
B_0x1
NACK transmission during parity error is enabled
0x1
ONEBIT
One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0).
11
1
read-write
B_0x0
Three sample bit method
0x0
B_0x1
One sample bit method
0x1
OVRDIS
Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data
12
1
read-write
B_0x0
Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x0
B_0x1
Overrun functionality is disabled. If new data is received while the RXNE flag is still set
0x1
RTSE
RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
1
read-write
B_0x0
RTS hardware flow control disabled
0x0
B_0x1
RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
0x1
RXFTCFG
Receive FIFO threshold configuration Remaining combinations: Reserved
25
3
read-write
B_0x0
Receive FIFO reaches 1/8 of its depth
0x0
B_0x1
Receive FIFO reaches 1/4 of its depth
0x1
B_0x2
Receive FIFO reaches 1/2 of its depth
0x2
B_0x3
Receive FIFO reaches 3/4 of its depth
0x3
B_0x4
Receive FIFO reaches 7/8 of its depth
0x4
B_0x5
Receive FIFO becomes full
0x5
RXFTIE
RXFIFO threshold interrupt enable This bit is set and cleared by software.
28
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.
0x1
SCARCNT
Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
17
3
read-write
B_0x0
retransmission disabled - No automatic retransmission in transmit mode.
0x0
B_0x1
number of automatic retransmission attempts (before signaling error)
0x1
B_0x2
number of automatic retransmission attempts (before signaling error)
0x2
B_0x3
number of automatic retransmission attempts (before signaling error)
0x3
B_0x4
number of automatic retransmission attempts (before signaling error)
0x4
B_0x5
number of automatic retransmission attempts (before signaling error)
0x5
B_0x6
number of automatic retransmission attempts (before signaling error)
0x6
B_0x7
number of automatic retransmission attempts (before signaling error)
0x7
SCEN
Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
5
1
read-write
B_0x0
Smartcard Mode disabled
0x0
B_0x1
Smartcard Mode enabled
0x1
TCBGTIE
Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
24
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever TCBGT=1 in the USART_ISR register
0x1
TXFTCFG
TXFIFO threshold configuration Remaining combinations: Reserved
29
3
read-write
B_0x0
TXFIFO reaches 1/8 of its depth
0x0
B_0x1
TXFIFO reaches 1/4 of its depth
0x1
B_0x2
TXFIFO reaches 1/2 of its depth
0x2
B_0x3
TXFIFO reaches 3/4 of its depth
0x3
B_0x4
TXFIFO reaches 7/8 of its depth
0x4
B_0x5
TXFIFO becomes empty
0x5
TXFTIE
TXFIFO threshold interrupt enable This bit is set and cleared by software.
23
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.
0x1
WUFIE
Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
22
1
read-write
B_0x0
Interrupt inhibited
0x0
B_0x1
USART interrupt generated whenever WUF = 1 in the USART_ISR register
0x1
WUS
Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
20
2
read-write
B_0x0
WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x0
B_0x2
WUF active on start bit detection
0x2
B_0x3
WUF active on RXNE/RXFNE.
0x3
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0xFFFFFFFF
GT
Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
8
read-write
PSC
Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to .
0
8
read-write
B_0x0
Reserved - do not program this value
0x0
B_0x1
Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x1
B_0x1F
Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
0x1F
B_0x2
Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x2
B_0x3
Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x3
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
17
1
write-only
CTSCF
CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
9
1
write-only
EOBCF
End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
12
1
write-only
FECF
Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
1
1
write-only
IDLECF
Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
4
1
write-only
LBDCF
LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
8
1
write-only
NECF
Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
2
1
write-only
ORECF
Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
3
1
write-only
PECF
Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0
1
write-only
RTOCF
Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835.
11
1
write-only
TCBGTCF
Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
7
1
write-only
TCCF
Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
6
1
write-only
TXFECF
TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
5
1
write-only
UDRCF
SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
13
1
write-only
WUCF
Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
20
1
write-only
ISR_FIFO_DISABLED
ISR_FIFO_DISABLED
Interrupt and status register
ISR_FIFO_ENABLED
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
ABRE
Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
14
1
read-only
ABRF
Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
15
1
read-only
BUSY
Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
16
1
read-only
B_0x0
USART is idle (no reception)
0x0
B_0x1
Reception on going
0x1
CMF
Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
17
1
read-only
B_0x0
No Character match detected
0x0
B_0x1
Character Match detected
0x1
CTS
CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
10
1
read-only
B_0x0
nCTS line set
0x0
B_0x1
nCTS line reset
0x1
CTSIF
CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
9
1
read-only
B_0x0
No change occurred on the nCTS status line
0x0
B_0x1
A change occurred on the nCTS status line
0x1
EOBF
End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
12
1
read-only
B_0x0
End of Block not reached
0x0
B_0x1
End of Block (number of characters) reached
0x1
FE
Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register.
1
1
read-only
B_0x0
No Framing error is detected
0x0
B_0x1
Framing error or break character is detected
0x1
IDLE
Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
4
1
read-only
B_0x0
No Idle line is detected
0x0
B_0x1
Idle line is detected
0x1
LBDF
LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
8
1
read-only
B_0x0
LIN Break not detected
0x0
B_0x1
LIN break detected
0x1
NE
Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861).
2
1
read-only
B_0x0
No noise is detected
0x0
B_0x1
Noise is detected
0x1
ORE
Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
3
1
read-only
B_0x0
No overrun error
0x0
B_0x1
Overrun error is detected
0x1
PE
Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0
1
read-only
B_0x0
No parity error
0x0
B_0x1
Parity error
0x1
REACK
Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
22
1
read-only
RTOF
Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
11
1
read-only
B_0x0
Timeout value not reached
0x0
B_0x1
Timeout value reached without any data reception
0x1
RWU
Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
19
1
read-only
B_0x0
Receiver in active mode
0x0
B_0x1
Receiver in Mute mode
0x1
RXNE
Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register.
5
1
read-only
B_0x0
Data is not received
0x0
B_0x1
Received data is ready to be read.
0x1
SBKF
Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
18
1
read-only
B_0x0
Break character transmitted
0x0
B_0x1
Break character requested by setting SBKRQ bit in USART_RQR register
0x1
TC
Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
6
1
read-only
B_0x0
Transmission is not complete
0x0
B_0x1
Transmission is complete
0x1
TCBGT
Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835.
25
1
read-only
B_0x0
Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x0
B_0x1
Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
0x1
TEACK
Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
21
1
read-only
TXE
Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register.
7
1
read-only
B_0x0
Data register full
0x0
B_0x1
Data register not full
0x1
UDR
SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
13
1
read-only
B_0x0
No underrun error
0x0
B_0x1
underrun error
0x1
WUF
Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
20
1
read-only
ISR_FIFO_ENABLED
ISR_FIFO_ENABLED
Interrupt and status register
0x1C
32
read-only
n
0x8000C0
0xFFFFFFFF
ABRE
Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
14
1
read-only
ABRF
Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
15
1
read-only
BUSY
Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
16
1
read-only
B_0x0
USART is idle (no reception)
0x0
B_0x1
Reception on going
0x1
CMF
Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
17
1
read-only
B_0x0
No Character match detected
0x0
B_0x1
Character Match detected
0x1
CTS
CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
10
1
read-only
B_0x0
nCTS line set
0x0
B_0x1
nCTS line reset
0x1
CTSIF
CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
9
1
read-only
B_0x0
No change occurred on the nCTS status line
0x0
B_0x1
A change occurred on the nCTS status line
0x1
EOBF
End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
12
1
read-only
B_0x0
End of Block not reached
0x0
B_0x1
End of Block (number of characters) reached
0x1
FE
Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
1
1
read-only
B_0x0
No Framing error is detected
0x0
B_0x1
Framing error or break character is detected
0x1
IDLE
Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
4
1
read-only
B_0x0
No Idle line is detected
0x0
B_0x1
Idle line is detected
0x1
LBDF
LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
8
1
read-only
B_0x0
LIN Break not detected
0x0
B_0x1
LIN break detected
0x1
NE
Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR.
2
1
read-only
B_0x0
No noise is detected
0x0
B_0x1
Noise is detected
0x1
ORE
Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
3
1
read-only
B_0x0
No overrun error
0x0
B_0x1
Overrun error is detected
0x1
PE
Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0
1
read-only
B_0x0
No parity error
0x0
B_0x1
Parity error
0x1
REACK
Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
22
1
read-only
RTOF
Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
11
1
read-only
B_0x0
Timeout value not reached
0x0
B_0x1
Timeout value reached without any data reception
0x1
RWU
Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
19
1
read-only
B_0x0
Receiver in active mode
0x0
B_0x1
Receiver in Mute mode
0x1
RXFF
RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register.
24
1
read-only
B_0x0
RXFIFO not full.
0x0
B_0x1
RXFIFO Full.
0x1
RXFNE
RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register.
5
1
read-only
B_0x0
Data is not received
0x0
B_0x1
Received data is ready to be read.
0x1
RXFT
RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
26
1
read-only
B_0x0
Receive FIFO does not reach the programmed threshold.
0x0
B_0x1
Receive FIFO reached the programmed threshold.
0x1
SBKF
Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
18
1
read-only
B_0x0
Break character transmitted
0x0
B_0x1
Break character requested by setting SBKRQ bit in USART_RQR register
0x1
TC
Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
6
1
read-only
B_0x0
Transmission is not complete
0x0
B_0x1
Transmission is complete
0x1
TCBGT
Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835.
25
1
read-only
B_0x0
Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x0
B_0x1
Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
0x1
TEACK
Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
21
1
read-only
TXFE
TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register.
23
1
read-only
B_0x0
TXFIFO not empty.
0x0
B_0x1
TXFIFO empty.
0x1
TXFNF
TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
7
1
read-only
B_0x0
Transmit FIFO is full
0x0
B_0x1
Transmit FIFO is not full
0x1
TXFT
TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register.
27
1
read-only
B_0x0
TXFIFO does not reach the programmed threshold.
0x0
B_0x1
TXFIFO reached the programmed threshold.
0x1
UDR
SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
13
1
read-only
B_0x0
No underrun error
0x0
B_0x1
underrun error
0x1
WUF
Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
20
1
read-only
PRESC
PRESC
Prescaler register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0
4
read-write
B_0x0
input clock not divided
0x0
B_0x1
input clock divided by 2
0x1
B_0x2
input clock divided by 4
0x2
B_0x3
input clock divided by 6
0x3
B_0x4
input clock divided by 8
0x4
B_0x5
input clock divided by 10
0x5
B_0x6
input clock divided by 12
0x6
B_0x7
input clock divided by 16
0x7
B_0x8
input clock divided by 32
0x8
B_0x9
input clock divided by 64
0x9
B_0xA
input clock divided by 128
0xA
B_0xB
input clock divided by 256
0xB
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
ABRRQ
Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0
1
write-only
MMRQ
Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
2
1
write-only
RXFRQ
Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
3
1
write-only
SBKRQ
Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
1
1
write-only
TXFRQ
Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
4
1
write-only
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
VREFBUF
System configuration controller
VREFBUF
0x40010030
0x0
0x400
registers
n
CCR
VREFBUF_CCR
VREFBUF calibration control register
0x4
32
read-write
n
0x0
0xFFFFFFFF
TRIM
Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows the tuning of the internal reference buffer voltage.
0
6
read-write
CSR
VREFBUF_CSR
VREFBUF control and status register
0x0
32
read-write
n
0x2
0xFFFFFFFF
ENVR
Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.
0
1
read-write
B_0x0
Internal voltage reference mode disable (external voltage reference mode).
0x0
B_0x1
Internal voltage reference mode (reference buffer enable or hold mode) enable.
0x1
HIZ
High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration.
1
1
read-write
B_0x0
VREF+ pin is internally connected to the voltage reference buffer output.
0x0
B_0x1
VREF+ pin is high impedance.
0x1
VRR
Voltage reference buffer ready
3
1
read-only
B_0x0
the voltage reference buffer output is not ready.
0x0
B_0x1
the voltage reference buffer output reached the requested level.
0x1
VRS
Voltage reference scale This bit selects the value generated by the voltage reference buffer.
2
1
read-write
B_0x0
Voltage reference set to VREF_OUT1 (around 2.048 V).
0x0
B_0x1
Voltage reference set to VREF_OUT2 (around 2.5 V).
0x1
WWDG
System window watchdog
WWDG
0x40002C00
0x0
0x400
registers
n
WWDG
Window Watchdog interrupt
0
CFR
WWDG_CFR
Configuration register
0x4
32
read-write
n
0x7F
0xFFFFFFFF
EWI
Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
9
1
read-write
W
7-bit window value These bits contain the window value to be compared with the down-counter.
0
7
read-write
WDGTB
Timer base The timebase of the prescaler can be modified as follows:
11
3
read-write
B_0x0
CK Counter Clock (PCLK div 4096) div 1
0x0
B_0x1
CK Counter Clock (PCLK div 4096) div 2
0x1
B_0x2
CK Counter Clock (PCLK div 4096) div 4
0x2
B_0x3
CK Counter Clock (PCLK div 4096) div 8
0x3
B_0x4
CK Counter Clock (PCLK div 4096) div 16
0x4
B_0x5
CK Counter Clock (PCLK div 4096) div 32
0x5
B_0x6
CK Counter Clock (PCLK div 4096) div 64
0x6
B_0x7
CK Counter Clock (PCLK div 4096) div 128
0x7
CR
WWDG_CR
Control register
0x0
32
read-write
n
0x7F
0xFFFFFFFF
T
7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
0
7
read-write
WDGA
Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGAÂ =Â 1, the watchdog can generate a reset.
7
1
read-write
B_0x0
Watchdog disabled
0x0
B_0x1
Watchdog enabled
0x1
SR
WWDG_SR
Status register
0x8
32
read-write
n
0x0
0xFFFFFFFF
EWIF
Early wakeup interrupt flag
0
1