STMicroelectronics STM32G071KB 2024.04.27 STM32G071KB false 0 0 ADC Analog to Digital Converter instance 1 ADC 0x0 0x0 0x400 registers n ADC_COMP ADC and COMP interrupts 12 AWD1TR AWD1TR watchdog threshold register 0x20 32 read-write n 0x0 0x0 HT1 ADC analog watchdog 1 threshold high 16 12 LT1 ADC analog watchdog 1 threshold low 0 12 AWD2CR AWD2CR ADC analog watchdog 2 configuration register 0xA0 32 read-write n 0x0 0x0 AWD2CH ADC analog watchdog 2 monitored channel selection 0 19 AWD2TR AWD2TR watchdog threshold register 0x24 32 read-write n 0x0 0x0 HT2 ADC analog watchdog 2 threshold high 16 12 LT2 ADC analog watchdog 2 threshold low 0 12 AWD3CR AWD3CR ADC analog watchdog 3 configuration register 0xA4 32 read-write n 0x0 0x0 AWD3CH ADC analog watchdog 3 monitored channel selection 0 19 AWD3TR AWD3TR watchdog threshold register 0x2C 32 read-write n 0x0 0x0 HT3 ADC analog watchdog 3 threshold high 16 12 LT3 ADC analog watchdog 3 threshold high 0 12 CALFACT CALFACT ADC calibration factors register 0xB4 32 read-write n 0x0 0x0 CALFACT ADC calibration factor in single-ended mode 0 7 CCR CCR ADC common control register 0x308 32 read-write n 0x0 0x0 PRESC ADC prescaler 18 4 TSEN Temperature sensor enable 23 1 VBATEN VBAT enable 24 1 VREFEN VREFINT enable 22 1 CFGR1 CFGR1 ADC configuration register 1 0xC 32 read-write n 0x0 0x0 ALIGN ADC data alignement 5 1 AUTOFF Auto-off mode 15 1 AWD1EN ADC analog watchdog 1 enable on scope ADC group regular 23 1 AWD1SGL ADC analog watchdog 1 monitoring a single channel or all channels 22 1 AWDCH1CH ADC analog watchdog 1 monitored channel selection 26 5 CHSELRMOD Mode selection of the ADC_CHSELR register 21 1 CONT ADC group regular continuous conversion mode 13 1 DISCEN ADC group regular sequencer discontinuous mode 16 1 DMACFG ADC DMA transfer configuration 1 1 DMAEN ADC DMA transfer enable 0 1 EXTEN ADC group regular external trigger polarity 10 2 EXTSEL ADC group regular external trigger source 6 3 OVRMOD ADC group regular overrun configuration 12 1 RES ADC data resolution 3 2 SCANDIR Scan sequence direction 2 1 WAIT Wait conversion mode 14 1 CFGR2 CFGR2 ADC configuration register 2 0x10 32 read-write n 0x0 0x0 CKMODE ADC clock mode 30 2 LFTRIG Low frequency trigger mode enable 29 1 OVSE ADC oversampler enable on scope ADC group regular 0 1 OVSR ADC oversampling ratio 2 3 OVSS ADC oversampling shift 5 4 TOVS ADC oversampling discontinuous mode (triggered mode) for ADC group regular 9 1 CHSELR CHSELR channel selection register 0x28 32 read-write n 0x0 0x0 CHSEL Channel-x selection 0 19 CHSELR_1 CHSELR_1 channel selection register CHSELRMOD = 1 in ADC_CFGR1 CHSELR 0x28 32 read-write n 0x0 0x0 SQ1 conversion of the sequence 0 4 SQ2 conversion of the sequence 4 4 SQ3 conversion of the sequence 8 4 SQ4 conversion of the sequence 12 4 SQ5 conversion of the sequence 16 4 SQ6 conversion of the sequence 20 4 SQ7 conversion of the sequence 24 4 SQ8 conversion of the sequence 28 4 CR CR ADC control register 0x8 32 read-write n 0x0 0x0 ADCAL ADC calibration 31 1 ADDIS ADC disable 1 1 ADEN ADC enable 0 1 ADSTART ADC group regular conversion start 2 1 ADSTP ADC group regular conversion stop 4 1 ADVREGEN ADC voltage regulator enable 28 1 DR DR ADC group regular conversion data register 0x40 32 read-only n 0x0 0x0 regularDATA ADC group regular conversion data 0 16 HWCFGR0 HWCFGR0 Hardware Configuration Register 0x3F0 32 read-only n 0x0 0x0 EXTRA_AWDS Extra analog watchdog 4 4 NUM_CHAN_24 NUM_CHAN_24 0 4 OVS Oversampling 8 4 HWCFGR1 HWCFGR1 Hardware Configuration Register 0x3EC 32 read-write n 0x0 0x0 CHMAP0 Input channel mapping 24 5 CHMAP1 Input channel mapping 16 5 CHMAP2 Input channel mapping 8 5 CHMAP3 Input channel mapping 0 5 HWCFGR2 HWCFGR2 Hardware Configuration Register 0x3E8 32 read-write n 0x0 0x0 CHMAP4 Input channel mapping 24 5 CHMAP5 Input channel mapping 16 5 CHMAP6 Input channel mapping 8 5 CHMAP7 Input channel mapping 0 5 HWCFGR3 HWCFGR3 Hardware Configuration Register 0x3E4 32 read-write n 0x0 0x0 CHMAP10 Input channel mapping 8 5 CHMAP11 Input channel mapping 0 5 CHMAP8 Input channel mapping 24 5 CHMAP9 Input channel mapping 16 5 HWCFGR4 HWCFGR4 Hardware Configuration Register 0x3E0 32 read-write n 0x0 0x0 CHMAP12 Input channel mapping 24 5 CHMAP13 Input channel mapping 16 5 CHMAP14 Input channel mapping 8 5 CHMAP15 Input channel mapping 0 5 HWCFGR5 HWCFGR5 Hardware Configuration Register 0x3DC 32 read-write n 0x0 0x0 CHMAP16 Input channel mapping 24 5 CHMAP17 Input channel mapping 16 5 CHMAP18 Input channel mapping 8 5 CHMAP19 Input channel mapping 0 5 HWCFGR6 HWCFGR6 Hardware Configuration Register 0x3D8 32 read-write n 0x0 0x0 CHMAP20 Input channel mapping 0 5 CHMAP21 Input channel mapping 8 5 CHMAP22 Input channel mapping 16 5 CHMAP23 Input channel mapping 24 5 IER IER ADC interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADC ready interrupt 0 1 AWD1IE ADC analog watchdog 1 interrupt 7 1 AWD2IE ADC analog watchdog 2 interrupt 8 1 AWD3IE ADC analog watchdog 3 interrupt 9 1 CCRDYIE Channel Configuration Ready Interrupt enable 13 1 EOCALIE End of calibration interrupt enable 11 1 EOCIE ADC group regular end of unitary conversion interrupt 2 1 EOSIE ADC group regular end of sequence conversions interrupt 3 1 EOSMPIE ADC group regular end of sampling interrupt 1 1 OVRIE ADC group regular overrun interrupt 4 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR ADC interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADC ready flag 0 1 AWD1 ADC analog watchdog 1 flag 7 1 AWD2 ADC analog watchdog 2 flag 8 1 AWD3 ADC analog watchdog 3 flag 9 1 CCRDY Channel Configuration Ready flag 13 1 EOC ADC group regular end of unitary conversion flag 2 1 EOCAL End Of Calibration flag 11 1 EOS ADC group regular end of sequence conversions flag 3 1 EOSMP ADC group regular end of sampling flag 1 1 OVR ADC group regular overrun flag 4 1 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SMPR SMPR ADC sampling time register 0x14 32 read-write n 0x0 0x0 SMP1 Sampling time selection 0 3 SMP2 Sampling time selection 4 3 SMPSEL Channel sampling time selection 8 19 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 COMP COMP1 COMP1 0x0 0x0 0x200 registers n COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 32 read-write n 0x0 0x0 BLANKSEL Comparator 2 blanking source selector 20 5 EN COMP channel 1 enable bit 0 1 HYST Comparator 2 hysteresis selector 16 2 INMSEL Comparator 2 signal selector for inverting input INM 4 4 INPSEL Comparator 2 signal selector for non-inverting input 8 2 LOCK COMP2_CSR register lock 31 1 POLARITY Comparator 2 polarity selector 15 1 PWRMODE Comparator 2 power mode selector 18 2 VALUE Comparator 2 output status 30 1 WINMODE Comparator 2 non-inverting input selector for window mode 11 1 WINOUT Comparator 2 output selector 14 1 COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 32 read-write n 0x0 0x0 BLANKSEL Comparator 2 blanking source selector 20 5 EN COMP channel 1 enable bit 0 1 HYST Comparator 2 hysteresis selector 16 2 INMSEL Comparator 2 signal selector for inverting input INM 4 4 INPSEL Comparator 2 signal selector for non-inverting input 8 2 LOCK COMP2_CSR register lock 31 1 POLARITY Comparator 2 polarity selector 15 1 PWRMODE Comparator 2 power mode selector 18 2 VALUE Comparator 2 output status 30 1 WINMODE Comparator 2 non-inverting input selector for window mode 11 1 WINOUT Comparator 2 output selector 14 1 CRC Cyclic redundancy check calculation unit CRC 0x0 0x0 0x400 registers n CEC CEC global interrupt 30 CR CR Control register 0x8 32 read-write n 0x0 0x0 POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only REV_IN Reverse input data 5 2 read-write REV_OUT Reverse output data 7 1 read-write DR DR Data register 0x0 32 read-write n 0x0 0x0 DR Data register bits 0 32 IDR IDR Independent data register 0x4 32 read-write n 0x0 0x0 IDR General-purpose 32-bit data register bits 0 32 INIT INIT Initial CRC value 0x10 32 read-write n 0x0 0x0 CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 32 read-write n 0x0 0x0 POL Programmable polynomial 0 32 DAC DAC DAC 0x0 0x0 0x400 registers n CCR DAC_CCR DAC calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 CR DAC_CR DAC control register 0x0 32 read-write n 0x0 0x0 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 TEN1 DAC channel1 trigger enable 1 1 TEN2 DAC channel2 trigger enable 17 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DOR2 DAC_DOR2 DAC channel2 data output register 0x30 32 read-only n 0x0 0x0 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 IP_HWCFGR0 IP_HWCFGR0 DAC IP Hardware Configuration Register 0x3F0 32 read-write n 0x0 0x0 DUAL Dual DAC capability 0 4 LFSR Pseudonoise wave generation capability 4 4 OR_CFG option register bit width 16 8 SAMPLE Sample and hold mode capability 12 4 TRIANGLE Triangle wave generation capability 8 4 MCR DAC_MCR DAC mode control register 0x3C 32 read-write n 0x0 0x0 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample and amp hold mode 0 3 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample and amp hold mode 16 3 SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 DAC Channel 1 hold Time (only valid in sample and amp hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample and amp hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample and amp hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample and amp hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 32 read-write n 0x0 0x0 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample and amp hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 32 read-write n 0x0 0x0 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample and amp hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR DAC_SR DAC status register 0x34 32 read-write n 0x0 0x0 BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample and Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample and Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write SWTRGR DAC_SWTRGR DAC software trigger register 0x4 32 write-only n 0x0 0x0 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 DBG Debug support DBG 0x0 0x0 0x400 registers n APB_FZ1 APB_FZ1 DBG APB freeze register 1 0x8 32 read-write n 0x0 0x0 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_LPTIM1_STOP Clocking of LPTIMER1 counter when the core is halted 31 1 DBG_LPTIM2_STOP Clocking of LPTIMER2 counter when the core is halted 30 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 APB_FZ2 APB_FZ2 DBG APB freeze register 2 0xC 32 read-write n 0x0 0x0 DBG_TIM14_STOP DBG_TIM14_STOP 15 1 DBG_TIM15_STOP DBG_TIM15_STOP 16 1 DBG_TIM16_STOP DBG_TIM16_STOP 17 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 DBG_TIM1_STOP DBG_TIM1_STOP 11 1 CR CR Debug MCU Configuration Register 0x4 32 read-write n 0x0 0x0 DBG_STANDBY Debug Standby Mode 2 1 DBG_STOP Debug Stop Mode 1 1 IDCODE IDCODE MCU Device ID Code Register 0x0 32 read-only n 0x0 0x0 DEV_ID Device Identifier 0 16 REV_ID Revision Identifier 16 16 DMA DMA controller DMA 0x0 0x0 0x400 registers n DMA_Channel1 DMA channel 1 interrupt 9 DMA_Channel2_3 DMA channel 2 and 3 interrupts 10 CCR1 CCR1 DMA channel x configuration register 0x8 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR2 CCR2 DMA channel x configuration register 0x1C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR3 CCR3 DMA channel x configuration register 0x30 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR4 CCR4 DMA channel x configuration register 0x44 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR5 CCR5 DMA channel x configuration register 0x58 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR6 CCR6 DMA channel x configuration register 0x6C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR7 CCR7 DMA channel x configuration register 0x80 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CMAR1 CMAR1 DMA channel x memory address register 0x14 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR2 CMAR2 DMA channel x memory address register 0x28 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR3 CMAR3 DMA channel x memory address register 0x3C 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR4 CMAR4 DMA channel x memory address register 0x50 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR5 CMAR5 DMA channel x memory address register 0x64 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR6 CMAR6 DMA channel x memory address register 0x78 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR7 CMAR7 DMA channel x memory address register 0x8C 32 read-write n 0x0 0x0 MA Memory address 0 32 CNDTR1 CNDTR1 DMA channel x number of data register 0xC 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR2 CNDTR2 DMA channel x number of data register 0x20 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR3 CNDTR3 DMA channel x configuration register 0x34 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR4 CNDTR4 DMA channel x configuration register 0x48 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR5 CNDTR5 DMA channel x configuration register 0x5C 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR6 CNDTR6 DMA channel x configuration register 0x70 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR7 CNDTR7 DMA channel x configuration register 0x84 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CPAR1 CPAR1 DMA channel x peripheral address register 0x10 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR2 CPAR2 DMA channel x peripheral address register 0x24 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR3 CPAR3 DMA channel x peripheral address register 0x38 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR4 CPAR4 DMA channel x peripheral address register 0x4C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR5 CPAR5 DMA channel x peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR6 CPAR6 DMA channel x peripheral address register 0x74 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR7 CPAR7 DMA channel x peripheral address register 0x88 32 read-write n 0x0 0x0 PA Peripheral address 0 32 IFCR IFCR high interrupt status register 0x4 32 read-only n 0x0 0x0 CGIF0 Channel global interrupt flag 0 1 CGIF12 Channel global interrupt flag 12 1 CGIF16 Channel global interrupt flag 16 1 CGIF20 Channel global interrupt flag 20 1 CGIF24 Channel global interrupt flag 24 1 CGIF4 Channel global interrupt flag 4 1 CGIF8 Channel global interrupt flag 8 1 CHTIF10 Channel half transfer flag 10 1 CHTIF14 Channel half transfer flag 14 1 CHTIF18 Channel half transfer flag 18 1 CHTIF2 Channel half transfer flag 2 1 CHTIF22 Channel half transfer flag 22 1 CHTIF26 Channel half transfer flag 26 1 CHTIF6 Channel half transfer flag 6 1 CTCIF1 Channel transfer complete flag 1 1 CTCIF13 Channel transfer complete flag 13 1 CTCIF17 Channel transfer complete flag 17 1 CTCIF21 Channel transfer complete flag 21 1 CTCIF25 Channel transfer complete flag 25 1 CTCIF5 Channel transfer complete flag 5 1 CTCIF9 Channel transfer complete flag 9 1 CTEIF11 Channel transfer error flag 11 1 CTEIF15 Channel transfer error flag 15 1 CTEIF19 Channel transfer error flag 19 1 CTEIF23 Channel transfer error flag 23 1 CTEIF27 Channel transfer error flag 27 1 CTEIF3 Channel transfer error flag 3 1 CTEIF7 Channel transfer error flag 7 1 ISR ISR low interrupt status register 0x0 32 read-only n 0x0 0x0 GIF1 global interrupt flag for channel 1 0 1 read-only GIF2 global interrupt flag for channel 2 4 1 read-only GIF3 global interrupt flag for channel 3 8 1 read-only GIF4 global interrupt flag for channel 4 12 1 read-only GIF5 global interrupt flag for channel 5 16 1 read-only GIF6 global interrupt flag for channel 6 20 1 read-only GIF7 global interrupt flag for channel 7 24 1 read-only HTIF1 half transfer (HT) flag for channel 1 2 1 read-only HTIF2 half transfer (HT) flag for channel 2 6 1 read-only HTIF3 half transfer (HT) flag for channel 3 10 1 read-only HTIF4 half transfer (HT) flag for channel 4 14 1 read-only HTIF5 half transfer (HT) flag for channel 5 18 1 read-only HTIF6 half transfer (HT) flag for channel 6 22 1 read-only HTIF7 half transfer (HT) flag for channel 7 26 1 read-only TCIF1 transfer complete (TC) flag for channel 1 1 1 read-only TCIF2 transfer complete (TC) flag for channel 2 5 1 read-only TCIF3 transfer complete (TC) flag for channel 3 9 1 read-only TCIF4 transfer complete (TC) flag for channel 4 13 1 read-only TCIF5 transfer complete (TC) flag for channel 5 17 1 read-only TCIF6 transfer complete (TC) flag for channel 6 21 1 read-only TCIF7 transfer complete (TC) flag for channel 7 25 1 read-only TEIF1 transfer error (TE) flag for channel 1 3 1 read-only TEIF2 transfer error (TE) flag for channel 2 7 1 read-only TEIF3 transfer error (TE) flag for channel 3 11 1 read-only TEIF4 transfer error (TE) flag for channel 4 15 1 read-only TEIF5 transfer error (TE) flag for channel 5 19 1 read-only TEIF6 transfer error (TE) flag for channel 6 23 1 read-only TEIF7 transfer error (TE) flag for channel 7 27 1 read-only DMAMUX DMAMUX DMAMUX 0x0 0x0 0x400 registers n DMA_Channel4_5_6_7 DMA channel 4, 5, 6 and 7 and DMAMUX 11 C0CR DMAMUX_C0CR DMAMux - DMA request line multiplexer channel x control register 0x0 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 8 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C1CR DMAMUX_C1CR DMAMux - DMA request line multiplexer channel x control register 0x4 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 8 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C2CR DMAMUX_C2CR DMAMux - DMA request line multiplexer channel x control register 0x8 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 8 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C3CR DMAMUX_C3CR DMAMux - DMA request line multiplexer channel x control register 0xC 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 8 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C4CR DMAMUX_C4CR DMAMux - DMA request line multiplexer channel x control register 0x10 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 8 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C5CR DMAMUX_C5CR DMAMux - DMA request line multiplexer channel x control register 0x14 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 8 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C6CR DMAMUX_C6CR DMAMux - DMA request line multiplexer channel x control register 0x18 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 8 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 CFR DMAMUX_CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 32 write-only n 0x0 0x0 CSOF Clear synchronization overrun event flag 0 7 CSR DMAMUX_CSR DMAMUX request line multiplexer interrupt channel status register 0x80 32 read-only n 0x0 0x0 SOF Synchronization overrun event flag 0 7 HWCFGR1 DMAMUX_HWCFGR1 DMAMUX hardware configuration 1 register 0x3F0 32 read-only n 0x0 0x0 NUM_DMA_PERIPH_REQ number of DMA request lines from peripherals 8 8 NUM_DMA_REQGEN number of DMA request generator channels 24 8 NUM_DMA_STREAMS number of DMA request line multiplexer (output) channels 0 8 NUM_DMA_TRIG number of synchronization inputs 16 8 HWCFGR2 DMAMUX_HWCFGR2 DMAMUX hardware configuration 2 register 0x3EC 32 read-only n 0x0 0x0 NUM_DMA_EXT_REQ Number of DMA request trigger inputs 0 8 IPIDR DMAMUX_IPIDR DMAMUX IP identification register 0x3F8 32 read-only n 0x0 0x0 ID IP identification 0 32 RG0CR DMAMUX_RG0CR DMAMux - DMA request generator channel x control register 0x100 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RG1CR DMAMUX_RG1CR DMAMux - DMA request generator channel x control register 0x104 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RG2CR DMAMUX_RG2CR DMAMux - DMA request generator channel x control register 0x108 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RG3CR DMAMUX_RG3CR DMAMux - DMA request generator channel x control register 0x10C 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RGCFR DMAMUX_RGCFR DMAMux - DMA request generator clear flag register 0x144 32 write-only n 0x0 0x0 COF Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. 0 4 RGSR DMAMUX_RGSR DMAMux - DMA request generator status register 0x140 32 read-only n 0x0 0x0 OF Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. 0 4 SIDR DMAMUX_SIDR DMAMUX size identification register 0x3FC 32 read-only n 0x0 0x0 SID Size identification 0 32 VERR DMAMUX_VERR DMAMUX version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major IP revision 4 4 MINREV Minor IP revision 0 4 EXTI External interrupt/event controller EXTI 0x0 0x0 0x400 registers n EXTI0_1 EXTI line 0 and 1 interrupt 5 EXTI2_3 EXTI line 2 and 3 interrupt 6 EXTI4_15 EXTI line 4 to 15 interrupt 7 EMR1 EMR1 EXTI CPU wakeup with event mask register IMR1 0x80 32 read-write n 0x0 0x0 EM0 CPU wakeup with event mask on event input 0 1 EM1 CPU wakeup with event mask on event input 1 1 EM10 CPU wakeup with event mask on event input 10 1 EM11 CPU wakeup with event mask on event input 11 1 EM12 CPU wakeup with event mask on event input 12 1 EM13 CPU wakeup with event mask on event input 13 1 EM14 CPU wakeup with event mask on event input 14 1 EM15 CPU wakeup with event mask on event input 15 1 EM16 CPU wakeup with event mask on event input 16 1 EM17 CPU wakeup with event mask on event input 17 1 EM18 CPU wakeup with event mask on event input 18 1 EM19 CPU wakeup with event mask on event input 19 1 EM2 CPU wakeup with event mask on event input 2 1 EM21 CPU wakeup with event mask on event input 21 1 EM23 CPU wakeup with event mask on event input 23 1 EM25 CPU wakeup with event mask on event input 25 1 EM26 CPU wakeup with event mask on event input 26 1 EM27 CPU wakeup with event mask on event input 27 1 EM28 CPU wakeup with event mask on event input 28 1 EM29 CPU wakeup with event mask on event input 29 1 EM3 CPU wakeup with event mask on event input 3 1 EM30 CPU wakeup with event mask on event input 30 1 EM31 CPU wakeup with event mask on event input 31 1 EM4 CPU wakeup with event mask on event input 4 1 EM5 CPU wakeup with event mask on event input 5 1 EM6 CPU wakeup with event mask on event input 6 1 EM7 CPU wakeup with event mask on event input 7 1 EM8 CPU wakeup with event mask on event input 8 1 EM9 CPU wakeup with event mask on event input 9 1 EMR2 EMR2 EXTI CPU wakeup with event mask register 0x94 32 read-write n 0x0 0x0 EM32 CPU wakeup with event mask on event input 0 1 EM33 CPU wakeup with event mask on event input 1 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 FPR1 FPR1 EXTI falling edge pending register 0x10 32 read-write n 0x0 0x0 FPIF0 configurable event inputs x falling edge pending bit. 0 1 FPIF1 configurable event inputs x falling edge pending bit. 1 1 FPIF10 configurable event inputs x falling edge pending bit. 10 1 FPIF11 configurable event inputs x falling edge pending bit. 11 1 FPIF12 configurable event inputs x falling edge pending bit. 12 1 FPIF13 configurable event inputs x falling edge pending bit. 13 1 FPIF14 configurable event inputs x falling edge pending bit. 14 1 FPIF15 configurable event inputs x falling edge pending bit. 15 1 FPIF16 configurable event inputs x falling edge pending bit. 16 1 FPIF17 configurable event inputs x falling edge pending bit. 17 1 FPIF18 configurable event inputs x falling edge pending bit. 18 1 FPIF2 configurable event inputs x falling edge pending bit. 2 1 FPIF3 configurable event inputs x falling edge pending bit. 3 1 FPIF4 configurable event inputs x falling edge pending bit. 4 1 FPIF5 configurable event inputs x falling edge pending bit. 5 1 FPIF6 configurable event inputs x falling edge pending bit. 6 1 FPIF7 configurable event inputs x falling edge pending bit. 7 1 FPIF8 configurable event inputs x falling edge pending bit. 8 1 FPIF9 configurable event inputs x falling edge pending bit. 9 1 FTSR1 FTSR1 EXTI falling trigger selection register 0x4 32 read-write n 0x0 0x0 TR0 Rising trigger event configuration bit of Configurable Event input 0 1 TR1 Rising trigger event configuration bit of Configurable Event input 1 1 TR10 Rising trigger event configuration bit of Configurable Event input 10 1 TR11 Rising trigger event configuration bit of Configurable Event input 11 1 TR12 Rising trigger event configuration bit of Configurable Event input 12 1 TR13 Rising trigger event configuration bit of Configurable Event input 13 1 TR14 Rising trigger event configuration bit of Configurable Event input 14 1 TR15 Rising trigger event configuration bit of Configurable Event input 15 1 TR16 Rising trigger event configuration bit of Configurable Event input 16 1 TR17 Rising trigger event configuration bit of Configurable Event input 17 1 TR18 Rising trigger event configuration bit of Configurable Event input 18 1 TR2 Rising trigger event configuration bit of Configurable Event input 2 1 TR3 Rising trigger event configuration bit of Configurable Event input 3 1 TR4 Rising trigger event configuration bit of Configurable Event input 4 1 TR5 Rising trigger event configuration bit of Configurable Event input 5 1 TR6 Rising trigger event configuration bit of Configurable Event input 6 1 TR7 Rising trigger event configuration bit of Configurable Event input 7 1 TR8 Rising trigger event configuration bit of Configurable Event input 8 1 TR9 Rising trigger event configuration bit of Configurable Event input 9 1 HWCFGR1 HWCFGR1 Hardware configuration registers 0x3F0 32 read-only n 0x0 0x0 CPUEVTEN HW configuration of CPU event output enable 12 4 NBCPUS configuration number of CPUs 8 4 NBEVENTS configuration number of event 0 8 NBIOPORT HW configuration of number of IO ports 16 8 HWCFGR2 HWCFGR2 Hardware configuration registers 0x3EC 32 read-write n 0x0 0x0 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR3 HWCFGR3 Hardware configuration registers 0x3E8 32 read-write n 0x0 0x0 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR4 HWCFGR4 Hardware configuration registers 0x3E4 32 read-write n 0x0 0x0 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR5 HWCFGR5 Hardware configuration registers 0x3E0 32 read-write n 0x0 0x0 CPUEVENT HW configuration CPU event generation 0 32 HWCFGR6 HWCFGR6 Hardware configuration registers 0x3DC 32 read-write n 0x0 0x0 CPUEVENT HW configuration CPU event generation 0 32 HWCFGR7 HWCFGR7 Hardware configuration registers 0x3D8 32 read-write n 0x0 0x0 CPUEVENT HW configuration CPU event generation 0 32 IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 32 read-write n 0x0 0x0 IM0 CPU wakeup with interrupt mask on event input 0 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM16 CPU wakeup with interrupt mask on event input 16 1 IM17 CPU wakeup with interrupt mask on event input 17 1 IM18 CPU wakeup with interrupt mask on event input 18 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM20 CPU wakeup with interrupt mask on event input 20 1 IM21 CPU wakeup with interrupt mask on event input 21 1 IM22 CPU wakeup with interrupt mask on event input 22 1 IM23 CPU wakeup with interrupt mask on event input 23 1 IM24 CPU wakeup with interrupt mask on event input 24 1 IM25 CPU wakeup with interrupt mask on event input 25 1 IM26 CPU wakeup with interrupt mask on event input 26 1 IM27 CPU wakeup with interrupt mask on event input 27 1 IM28 CPU wakeup with interrupt mask on event input 28 1 IM29 CPU wakeup with interrupt mask on event input 29 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM30 CPU wakeup with interrupt mask on event input 30 1 IM31 CPU wakeup with interrupt mask on event input 31 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM9 CPU wakeup with interrupt mask on event input 9 1 IMR2 IMR2 EXTI CPU wakeup with interrupt mask register 0x90 32 read-write n 0x0 0x0 IM32 CPU wakeup with interrupt mask on event input 0 1 IM33 CPU wakeup with interrupt mask on event input 1 1 IPIDR IPIDR AES identification register 0x3F8 32 read-only n 0x0 0x0 ID Identification code 0 32 RPR1 RPR1 EXTI rising edge pending register 0xC 32 read-write n 0x0 0x0 RPIF0 configurable event inputs x rising edge Pending bit. 0 1 RPIF1 configurable event inputs x rising edge Pending bit. 1 1 RPIF10 configurable event inputs x rising edge Pending bit. 10 1 RPIF11 configurable event inputs x rising edge Pending bit. 11 1 RPIF12 configurable event inputs x rising edge Pending bit. 12 1 RPIF13 configurable event inputs x rising edge Pending bit. 13 1 RPIF14 configurable event inputs x rising edge Pending bit. 14 1 RPIF15 configurable event inputs x rising edge Pending bit. 15 1 RPIF16 configurable event inputs x rising edge Pending bit. 16 1 RPIF17 configurable event inputs x rising edge Pending bit. 17 1 RPIF18 configurable event inputs x rising edge Pending bit. 18 1 RPIF2 configurable event inputs x rising edge Pending bit. 2 1 RPIF3 configurable event inputs x rising edge Pending bit. 3 1 RPIF4 configurable event inputs x rising edge Pending bit. 4 1 RPIF5 configurable event inputs x rising edge Pending bit 5 1 RPIF6 configurable event inputs x rising edge Pending bit. 6 1 RPIF7 configurable event inputs x rising edge Pending bit. 7 1 RPIF8 configurable event inputs x rising edge Pending bit. 8 1 RPIF9 configurable event inputs x rising edge Pending bit. 9 1 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 32 read-write n 0x0 0x0 TR0 Rising trigger event configuration bit of Configurable Event input 0 1 TR1 Rising trigger event configuration bit of Configurable Event input 1 1 TR10 Rising trigger event configuration bit of Configurable Event input 10 1 TR11 Rising trigger event configuration bit of Configurable Event input 11 1 TR12 Rising trigger event configuration bit of Configurable Event input 12 1 TR13 Rising trigger event configuration bit of Configurable Event input 13 1 TR14 Rising trigger event configuration bit of Configurable Event input 14 1 TR15 Rising trigger event configuration bit of Configurable Event input 15 1 TR16 Rising trigger event configuration bit of Configurable Event input 16 1 TR17 Rising trigger event configuration bit of Configurable Event input 17 1 TR18 Rising trigger event configuration bit of Configurable Event input 18 1 TR2 Rising trigger event configuration bit of Configurable Event input 2 1 TR3 Rising trigger event configuration bit of Configurable Event input 3 1 TR4 Rising trigger event configuration bit of Configurable Event input 4 1 TR5 Rising trigger event configuration bit of Configurable Event input 5 1 TR6 Rising trigger event configuration bit of Configurable Event input 6 1 TR7 Rising trigger event configuration bit of Configurable Event input 7 1 TR8 Rising trigger event configuration bit of Configurable Event input 8 1 TR9 Rising trigger event configuration bit of Configurable Event input 9 1 SIDR SIDR AES size ID register 0x3FC 32 read-only n 0x0 0x0 ID Size Identification code 0 32 SWIER1 SWIER1 EXTI software interrupt event register 0x8 32 read-write n 0x0 0x0 SWIER0 Rising trigger event configuration bit of Configurable Event input 0 1 SWIER1 Rising trigger event configuration bit of Configurable Event input 1 1 SWIER10 Rising trigger event configuration bit of Configurable Event input 10 1 SWIER11 Rising trigger event configuration bit of Configurable Event input 11 1 SWIER12 Rising trigger event configuration bit of Configurable Event input 12 1 SWIER13 Rising trigger event configuration bit of Configurable Event input 13 1 SWIER14 Rising trigger event configuration bit of Configurable Event input 14 1 SWIER15 Rising trigger event configuration bit of Configurable Event input 15 1 SWIER16 Rising trigger event configuration bit of Configurable Event input 16 1 SWIER17 Rising trigger event configuration bit of Configurable Event input 17 1 SWIER18 Rising trigger event configuration bit of Configurable Event input 18 1 SWIER2 Rising trigger event configuration bit of Configurable Event input 2 1 SWIER3 Rising trigger event configuration bit of Configurable Event input 3 1 SWIER4 Rising trigger event configuration bit of Configurable Event input 4 1 SWIER5 Rising trigger event configuration bit of Configurable Event input 5 1 SWIER6 Rising trigger event configuration bit of Configurable Event input 6 1 SWIER7 Rising trigger event configuration bit of Configurable Event input 7 1 SWIER8 Rising trigger event configuration bit of Configurable Event input 8 1 SWIER9 Rising trigger event configuration bit of Configurable Event input 9 1 VERR VERR AES version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major revision 4 4 MINREV Minor revision 0 4 FLASH Flash Flash 0x0 0x0 0x400 registers n FLASH Flash global interrupt 3 ACR ACR Access control register 0x0 32 read-write n 0x0 0x0 DBG_SWEN Debug access software enable 18 1 EMPTY Flash User area empty 16 1 ICEN Instruction cache enable 9 1 ICRST Instruction cache reset 11 1 LATENCY Latency 0 3 PRFTEN Prefetch enable 8 1 CR CR Flash control register 0x14 32 read-write n 0x0 0x0 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 FSTPG Fast programming 18 1 LOCK FLASH_CR Lock 31 1 MER Mass erase 2 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 OPTSTRT Options modification start 17 1 PER Page erase 1 1 PG Programming 0 1 PNB Page number 3 6 RDERRIE PCROP read error interrupt enable 26 1 SEC_PROT Securable memory area protection enable 28 1 STRT Start 16 1 ECCR ECCR Flash ECC register 0x18 32 read-write n 0x0 0x0 ADDR_ECC ECC fail address 0 14 read-only ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write ECCIE ECC correction interrupt enable 24 1 read-write SYSF_ECC ECC fail for Corrected ECC Error or Double ECC Error in info block 20 1 read-only KEYR KEYR Flash key register 0x8 32 write-only n 0x0 0x0 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 32 write-only n 0x0 0x0 OPTKEYR Option byte key 0 32 OPTR OPTR Flash option register 0x20 32 read-write n 0x0 0x0 BOREN BOR reset Level 8 1 BORF_LEV These bits contain the VDD supply level threshold that activates the reset 9 2 BORR_LEV These bits contain the VDD supply level threshold that releases the reset. 11 2 IDWG_SW Independent watchdog selection 16 1 IRHEN Internal reset holder enable bit 29 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 nBOOT0 nBOOT0 option bit 26 1 nBOOT1 Boot configuration 25 1 nBOOT_SEL nBOOT_SEL 24 1 nRSTS_HDW nRSTS_HDW 15 1 NRST_MODE NRST_MODE 27 2 nRST_STDBY nRST_STDBY 14 1 nRST_STOP nRST_STOP 13 1 RAM_PARITY_CHECK SRAM parity check control 22 1 RDP Read protection level 0 8 WWDG_SW Window watchdog selection 19 1 PCROP1AER PCROP1AER Flash PCROP zone A End address register 0x28 32 read-only n 0x0 0x0 PCROP1A_END PCROP1A area end offset 0 8 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 PCROP1ASR PCROP1ASR Flash PCROP zone A Start address register 0x24 32 read-only n 0x0 0x0 PCROP1A_STRT PCROP1A area start offset 0 8 PCROP1BER PCROP1BER Flash PCROP zone B End address register 0x38 32 read-only n 0x0 0x0 PCROP1B_END PCROP1B area end offset 0 8 PCROP1BSR PCROP1BSR Flash PCROP zone B Start address register 0x34 32 read-only n 0x0 0x0 PCROP1B_STRT PCROP1B area start offset 0 8 SECR SECR Flash Security register 0x80 32 read-only n 0x0 0x0 BOOT_LOCK used to force boot from user area 16 1 SEC_SIZE Securable memory area size 0 7 SR SR Status register 0x10 32 read-write n 0x0 0x0 BSY Busy 16 1 CFGBSY Programming or erase configuration busy. 18 1 EOP End of operation 0 1 FASTERR Fast programming error 9 1 MISERR Fast programming data miss error 8 1 OPERR Operation error 1 1 OPTVERR Option and Engineering bits loading validity error 15 1 PGAERR Programming alignment error 5 1 PGSERR Programming sequence error 7 1 PROGERR Programming error 3 1 RDERR PCROP read error 14 1 SIZERR Size error 6 1 WRPERR Write protected error 4 1 WRP1AR WRP1AR Flash WRP area A address register 0x2C 32 read-only n 0x0 0x0 WRP1A_END WRP area A end offset 16 6 WRP1A_STRT WRP area A start offset 0 6 WRP1BR WRP1BR Flash WRP area B address register 0x30 32 read-only n 0x0 0x0 WRP1B_END WRP area B end offset 16 6 WRP1B_STRT WRP area B start offset 0 6 GPIOA General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOB General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOC General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOD General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOF General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 HDMI_CEC HDMI-CEC CEC 0x0 0x0 0x400 registers n CEC_CFGR CEC_CFGR This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. 0x4 32 read-write n 0x0 0x0 BRDNOGEN Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software. 7 1 BREGEN Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0 5 1 BRESTP Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software. 4 1 LBPEGEN Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0 6 1 LSTN Listen mode LSTN bit is set and cleared by software. 31 1 OAR Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received. 16 15 RXTOL Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall 3 1 SFT Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods 0 3 SFTOPT SFT Option Bit The SFTOPT bit is set and cleared by software. 8 1 CEC_CR CEC_CR CEC control register 0x0 32 read-write n 0x0 0x0 CECEN CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. 0 1 TXEOM Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message) 2 1 TXSOM Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception 1 1 CEC_IER CEC_IER CEC interrupt enable register 0x14 32 read-write n 0x0 0x0 ARBLSTIE Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software. 7 1 BREIE Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software. 3 1 LBPEIE Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software. 5 1 RXACKIE Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software. 6 1 RXBRIE Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software. 0 1 RXENDIE End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software. 1 1 RXOVRIE Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software. 2 1 SBPEIE Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software. 4 1 TXACKIE Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software. 12 1 TXBRIE Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software. 8 1 TXENDIE Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software. 9 1 TXERRIE Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software. 11 1 TXUDRIE Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software. 10 1 CEC_ISR CEC_ISR CEC Interrupt and Status Register 0x10 32 read-write n 0x0 0x0 ARBLST Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1. 7 1 BRE Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1. 3 1 LBPE Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1. 5 1 RXACKE Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1. 6 1 RXBR Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1. 0 1 RXEND End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1. 1 1 RXOVR Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1. 2 1 SBPE Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1. 4 1 TXACKE Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1. 12 1 TXBR Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1. 8 1 TXEND End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1. 9 1 TXERR Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1. 11 1 TXUDR Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1 10 1 CEC_RXDR CEC_RXDR CEC Rx Data Register 0xC 32 read-only n 0x0 0x0 RXD Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line. 0 8 CEC_TXDR CEC_TXDR CEC Tx data register 0x8 32 write-only n 0x0 0x0 TXD Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1 0 8 I2C1 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C1 I2C1 global interrupt 23 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C2 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C2 I2C2 global interrupt 24 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 IWDG Independent watchdog IWDG 0x0 0x0 0x400 registers n HWCFGR HWCFGR hardware configuration register 0x3F0 32 read-write n 0x0 0x0 PR_DEFAULT Prescaler default value 4 4 WINDOW Support of Window function 0 4 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 KR KR Key register 0x0 32 write-only n 0x0 0x0 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 32 read-write n 0x0 0x0 RL Watchdog counter reload value 0 12 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR Status register 0xC 32 read-only n 0x0 0x0 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WVU Watchdog counter window value update 2 1 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 WINR WINR Window register 0x10 32 read-write n 0x0 0x0 WIN Watchdog counter window value 0 12 LPTIM1 Low power timer LPTIM 0x0 0x0 0x400 registers n ARR ARR Autoreload Register 0x18 32 read-write n 0x0 0x0 ARR Auto reload value 0 16 CFGR CFGR Configuration Register 0xC 32 read-write n 0x0 0x0 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 COUNTMODE counter mode enabled 23 1 ENC Encoder mode enable 24 1 PRELOAD Registers update mode 22 1 PRESC Clock prescaler 9 3 TIMOUT Timeout enable 19 1 TRGFLT Configurable digital filter for trigger 6 2 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 WAVE Waveform shape 20 1 WAVPOL Waveform shape polarity 21 1 CFGR2 CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL LPTIMx Input 1 selection 0 2 IN2SEL LPTIM1 Input 2 selection 4 2 CMP CMP Compare Register 0x14 32 read-write n 0x0 0x0 CMP Compare value 0 16 CNT CNT Counter Register 0x1C 32 read-only n 0x0 0x0 CNT Counter value 0 16 CR CR Control Register 0x10 32 read-write n 0x0 0x0 CNTSTRT Timer start in continuous mode 2 1 COUNTRST Counter reset 3 1 ENABLE LPTIM Enable 0 1 RSTARE Reset after read enable 4 1 SNGSTRT LPTIM start in single mode 1 1 ICR ICR Interrupt Clear Register 0x4 32 write-only n 0x0 0x0 ARRMCF Autoreload match Clear Flag 1 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPMCF compare match Clear Flag 0 1 CMPOKCF Compare register update OK Clear Flag 3 1 DOWNCF Direction change to down Clear Flag 6 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 UPCF Direction change to UP Clear Flag 5 1 IER IER Interrupt Enable Register 0x8 32 read-write n 0x0 0x0 ARRMIE Autoreload match Interrupt Enable 1 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPMIE Compare match Interrupt Enable 0 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 DOWNIE Direction change to down Interrupt Enable 6 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 UPIE Direction change to UP Interrupt Enable 5 1 ISR ISR Interrupt and Status Register 0x0 32 read-only n 0x0 0x0 ARRM Autoreload match 1 1 ARROK Autoreload register update OK 4 1 CMPM Compare match 0 1 CMPOK Compare register update OK 3 1 DOWN Counter direction change up to down 6 1 EXTTRIG External trigger edge event 2 1 UP Counter direction change down to up 5 1 LPTIM2 Low power timer LPTIM 0x0 0x0 0x400 registers n ARR ARR Autoreload Register 0x18 32 read-write n 0x0 0x0 ARR Auto reload value 0 16 CFGR CFGR Configuration Register 0xC 32 read-write n 0x0 0x0 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 COUNTMODE counter mode enabled 23 1 ENC Encoder mode enable 24 1 PRELOAD Registers update mode 22 1 PRESC Clock prescaler 9 3 TIMOUT Timeout enable 19 1 TRGFLT Configurable digital filter for trigger 6 2 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 WAVE Waveform shape 20 1 WAVPOL Waveform shape polarity 21 1 CFGR2 CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL LPTIMx Input 1 selection 0 2 IN2SEL LPTIM1 Input 2 selection 4 2 CMP CMP Compare Register 0x14 32 read-write n 0x0 0x0 CMP Compare value 0 16 CNT CNT Counter Register 0x1C 32 read-only n 0x0 0x0 CNT Counter value 0 16 CR CR Control Register 0x10 32 read-write n 0x0 0x0 CNTSTRT Timer start in continuous mode 2 1 COUNTRST Counter reset 3 1 ENABLE LPTIM Enable 0 1 RSTARE Reset after read enable 4 1 SNGSTRT LPTIM start in single mode 1 1 ICR ICR Interrupt Clear Register 0x4 32 write-only n 0x0 0x0 ARRMCF Autoreload match Clear Flag 1 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPMCF compare match Clear Flag 0 1 CMPOKCF Compare register update OK Clear Flag 3 1 DOWNCF Direction change to down Clear Flag 6 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 UPCF Direction change to UP Clear Flag 5 1 IER IER Interrupt Enable Register 0x8 32 read-write n 0x0 0x0 ARRMIE Autoreload match Interrupt Enable 1 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPMIE Compare match Interrupt Enable 0 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 DOWNIE Direction change to down Interrupt Enable 6 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 UPIE Direction change to UP Interrupt Enable 5 1 ISR ISR Interrupt and Status Register 0x0 32 read-only n 0x0 0x0 ARRM Autoreload match 1 1 ARROK Autoreload register update OK 4 1 CMPM Compare match 0 1 CMPOK Compare register update OK 3 1 DOWN Counter direction change up to down 6 1 EXTTRIG External trigger edge event 2 1 UP Counter direction change down to up 5 1 LPUART Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR BRR 0 20 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT0 21 5 DEDT0 DEDT0 16 5 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 MSBFIRST Most significant bit first 19 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 HWCFGR1 HWCFGR1 LPUART Hardware Configuration register 1 0x3F0 32 read-write n 0x0 0x0 CFG1 LUART hardware configuration 1 0 4 CFG2 LUART hardware configuration 2 4 4 CFG3 LUART hardware configuration 1 8 4 CFG4 LUART hardware configuration 2 12 4 CFG5 LUART hardware configuration 2 16 4 CFG6 LUART hardware configuration 2 20 4 CFG7 LUART hardware configuration 2 24 4 CFG8 LUART hardware configuration 2 28 4 HWCFGR2 HWCFGR2 LPUART Hardware Configuration register 2 0x3EC 32 read-write n 0x0 0x0 CFG1 LUART hardware configuration 1 0 4 CFG2 LUART hardware configuration 2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 FE FE 1 1 IDLE IDLE 4 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 MPU Memory protection unit MPU 0x0 0x0 0x15 registers n CTRL MPU_CTRL MPU control register 0x4 32 read-write n 0x0 0x0 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 RASR MPU_RASR MPU region attribute and size register 0x10 32 read-write n 0x0 0x0 AP Access permission 24 3 B memory attribute 16 1 C memory attribute 17 1 ENABLE Region enable bit. 0 1 S Shareable memory attribute 18 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 TEX memory attribute 19 3 XN Instruction access disable bit 28 1 RBAR MPU_RBAR MPU region base address register 0xC 32 read-write n 0x0 0x0 ADDR Region base address field 5 27 REGION MPU region field 0 4 VALID MPU region number valid 4 1 RNR MPU_RNR MPU region number register 0x8 32 read-write n 0x0 0x0 REGION MPU region 0 8 TYPER MPU_TYPER MPU type register 0x0 32 read-only n 0x0 0x0 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 SEPARATE Separate flag 0 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0x33D registers n ICER ICER Interrupt Clear Enable Register 0x80 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICPR ICPR Interrupt Clear-Pending Register 0x180 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 IPR0 IPR0 Interrupt Priority Register 0 0x300 32 read-write n 0x0 0x0 PRI_0 priority for interrupt 0 0 8 PRI_1 priority for interrupt 1 8 8 PRI_2 priority for interrupt 2 16 8 PRI_3 priority for interrupt 3 24 8 IPR1 IPR1 Interrupt Priority Register 1 0x304 32 read-write n 0x0 0x0 PRI_4 priority for interrupt n 0 8 PRI_5 priority for interrupt n 8 8 PRI_6 priority for interrupt n 16 8 PRI_7 priority for interrupt n 24 8 IPR2 IPR2 Interrupt Priority Register 2 0x308 32 read-write n 0x0 0x0 PRI_10 priority for interrupt n 16 8 PRI_11 priority for interrupt n 24 8 PRI_8 priority for interrupt n 0 8 PRI_9 priority for interrupt n 8 8 IPR3 IPR3 Interrupt Priority Register 3 0x30C 32 read-write n 0x0 0x0 PRI_12 priority for interrupt n 0 8 PRI_13 priority for interrupt n 8 8 PRI_14 priority for interrupt n 16 8 PRI_15 priority for interrupt n 24 8 IPR4 IPR4 Interrupt Priority Register 4 0x310 32 read-write n 0x0 0x0 PRI_16 priority for interrupt n 0 8 PRI_17 priority for interrupt n 8 8 PRI_18 priority for interrupt n 16 8 PRI_19 priority for interrupt n 24 8 IPR5 IPR5 Interrupt Priority Register 5 0x314 32 read-write n 0x0 0x0 PRI_20 priority for interrupt n 0 8 PRI_21 priority for interrupt n 8 8 PRI_22 priority for interrupt n 16 8 PRI_23 priority for interrupt n 24 8 IPR6 IPR6 Interrupt Priority Register 6 0x318 32 read-write n 0x0 0x0 PRI_24 priority for interrupt n 0 8 PRI_25 priority for interrupt n 8 8 PRI_26 priority for interrupt n 16 8 PRI_27 priority for interrupt n 24 8 IPR7 IPR7 Interrupt Priority Register 7 0x31C 32 read-write n 0x0 0x0 PRI_28 priority for interrupt n 0 8 PRI_29 priority for interrupt n 8 8 PRI_30 priority for interrupt n 16 8 PRI_31 priority for interrupt n 24 8 ISER ISER Interrupt Set Enable Register 0x0 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISPR ISPR Interrupt Set-Pending Register 0x100 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 PWR Power control PWR 0x0 0x0 0x400 registers n PVD Power voltage detector interrupt 1 CR1 CR1 Power control register 1 0x0 32 read-write n 0x0 0x0 DBP Disable backup domain write protection 8 1 FPD_LPRUN Flash memory powered down during Low-power run mode 4 1 FPD_LPSLP Flash memory powered down during Low-power sleep mode 5 1 FPD_STOP Flash memory powered down during Stop mode 3 1 LPMS Low-power mode selection 0 3 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 CR2 CR2 Power control register 2 0x4 32 read-write n 0x0 0x0 PVDE Power voltage detector enable 0 1 PVDFT Power voltage detector falling threshold selection 1 3 PVDRT Power voltage detector rising threshold selection 4 3 CR3 CR3 Power control register 3 0x8 32 read-write n 0x0 0x0 APC Apply pull-up and pull-down configuration 10 1 EIWUL Enable internal wakeup line 15 1 EWUP1 Enable Wakeup pin WKUP1 0 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP5 Enable WKUP5 wakeup pin 4 1 EWUP6 Enable WKUP6 wakeup pin 5 1 RRS SRAM retention in Standby mode 8 1 ULPEN Enable the periodical sampling mode for PDR detection 9 1 CR4 CR4 Power control register 4 0xC 32 read-write n 0x0 0x0 VBE VBAT battery charging enable 8 1 VBRS VBAT battery charging resistor selection 9 1 WP1 Wakeup pin WKUP1 polarity 0 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP4 Wakeup pin WKUP4 polarity 3 1 WP5 Wakeup pin WKUP5 polarity 4 1 WP6 WKUP6 wakeup pin polarity 5 1 PDCRA PDCRA Power Port A pull-down control register 0x24 32 read-write n 0x0 0x0 PD0 Port A pull-down bit y (y=0..15) 0 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD13 Port A pull-down bit y (y=0..15) 13 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD15 Port A pull-down bit y (y=0..15) 15 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 32 read-write n 0x0 0x0 PD0 Port B pull-down bit y (y=0..15) 0 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD15 Port B pull-down bit y (y=0..15) 15 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD4 Port B pull-down bit y (y=0..15) 4 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PDCRC PDCRC Power Port C pull-down control register 0x34 32 read-write n 0x0 0x0 PD0 Port C pull-down bit y (y=0..15) 0 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD15 Port C pull-down bit y (y=0..15) 15 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 32 read-write n 0x0 0x0 PD0 Port D pull-down bit y (y=0..15) 0 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 32 read-write n 0x0 0x0 PD0 Port F pull-down bit y (y=0..15) 0 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PUCRA PUCRA Power Port A pull-up control register 0x20 32 read-write n 0x0 0x0 PU0 Port A pull-up bit y (y=0..15) 0 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU14 Port A pull-up bit y (y=0..15) 14 1 PU15 Port A pull-up bit y (y=0..15) 15 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PUCRB PUCRB Power Port B pull-up control register 0x28 32 read-write n 0x0 0x0 PU0 Port B pull-up bit y (y=0..15) 0 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU15 Port B pull-up bit y (y=0..15) 15 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PUCRC PUCRC Power Port C pull-up control register 0x30 32 read-write n 0x0 0x0 PU0 Port C pull-up bit y (y=0..15) 0 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU15 Port C pull-up bit y (y=0..15) 15 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PUCRD PUCRD Power Port D pull-up control register 0x38 32 read-write n 0x0 0x0 PU0 Port D pull-up bit y (y=0..15) 0 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PUCRF PUCRF Power Port F pull-up control register 0x48 32 read-write n 0x0 0x0 PU0 Port F pull-up bit y (y=0..15) 0 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU2 Port F pull-up bit y (y=0..15) 2 1 SCR SCR Power status clear register 0x18 32 write-only n 0x0 0x0 CSBF Clear standby flag 8 1 CWUF1 Clear wakeup flag 1 0 1 CWUF2 Clear wakeup flag 2 1 1 CWUF4 Clear wakeup flag 4 3 1 CWUF5 Clear wakeup flag 5 4 1 CWUF6 Clear wakeup flag 6 5 1 SR1 SR1 Power status register 1 0x10 32 read-only n 0x0 0x0 SBF Standby flag 8 1 WUF1 Wakeup flag 1 0 1 WUF2 Wakeup flag 2 1 1 WUF4 Wakeup flag 4 3 1 WUF5 Wakeup flag 5 4 1 WUF6 Wakeup flag 6 5 1 WUFI Wakeup flag internal 15 1 SR2 SR2 Power status register 2 0x14 32 read-only n 0x0 0x0 FLASH_RDY Flash ready flag 7 1 PVDO Power voltage detector output 11 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 VOSF Voltage scaling flag 10 1 RCC Reset and clock control RCC 0x0 0x0 0x400 registers n RCC RCC global interrupt 4 AHBENR AHBENR AHB peripheral clock enable register 0x38 32 read-write n 0x0 0x0 AESEN AES hardware accelerator 16 1 CRCEN CRC clock enable 12 1 DMAEN DMA clock enable 0 1 FLASHEN Flash memory interface clock enable 8 1 RNGEN Random number generator clock enable 18 1 AHBRSTR AHBRSTR AHB peripheral reset register 0x28 32 read-write n 0x0 0x0 AESRST AES hardware accelerator reset 16 1 CRCRST CRC reset 12 1 DMARST DMA1 reset 0 1 FLASHRST FLITF reset 8 1 RNGRST Random number generator reset 18 1 AHBSMENR AHBSMENR AHB peripheral clock enable in Sleep mode register 0x48 32 read-write n 0x0 0x0 AESSMEN AES hardware accelerator clock enable during Sleep mode 16 1 CRCSMEN CRC clock enable during Sleep mode 12 1 DMASMEN DMA clock enable during Sleep mode 0 1 FLASHSMEN Flash memory interface clock enable during Sleep mode 8 1 RNGSMEN Random number generator clock enable during Sleep mode 18 1 SRAMSMEN SRAM clock enable during Sleep mode 9 1 APBENR1 APBENR1 APB peripheral clock enable register 1 0x3C 32 read-write n 0x0 0x0 CECEN HDMI CEC clock enable 24 1 DAC1EN DAC1 interface clock enable 29 1 DBGEN Debug support clock enable 27 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 LPTIM1EN LPTIM1 clock enable 31 1 LPTIM2EN LPTIM2 clock enable 30 1 LPUART1EN LPUART1 clock enable 20 1 PWREN Power interface clock enable 28 1 RTCAPBEN RTC APB clock enable 10 1 SPI2EN SPI2 clock enable 14 1 TIM2EN TIM2 timer clock enable 0 1 TIM3EN TIM3 timer clock enable 1 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 UCPD1EN UCPD1 clock enable 25 1 UCPD2EN UCPD2 clock enable 26 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 USART4EN USART4 clock enable 19 1 WWDGEN WWDG clock enable 11 1 APBENR2 APBENR2 APB peripheral clock enable register 2 0x40 32 read-write n 0x0 0x0 ADCEN ADC clock enable 20 1 SPI1EN SPI1 clock enable 12 1 SYSCFGEN SYSCFG, COMP and VREFBUF clock enable 0 1 TIM14EN TIM14 timer clock enable 15 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM16 timer clock enable 18 1 TIM1EN TIM1 timer clock enable 11 1 USART1EN USART1 clock enable 14 1 APBRSTR1 APBRSTR1 APB peripheral reset register 1 0x2C 32 read-write n 0x0 0x0 CECRST HDMI CEC reset 24 1 DAC1RST DAC1 interface reset 29 1 DBGRST Debug support reset 27 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 LPTIM1RST Low Power Timer 1 reset 31 1 LPTIM2RST Low Power Timer 2 reset 30 1 LPUART1RST LPUART1 reset 20 1 PWRRST Power interface reset 28 1 SPI2RST SPI2 reset 14 1 TIM2RST TIM2 timer reset 0 1 TIM3RST TIM3 timer reset 1 1 TIM6RST TIM6 timer reset 4 1 TIM7RST TIM7 timer reset 5 1 UCPD1RST UCPD1 reset 25 1 UCPD2RST UCPD2 reset 26 1 USART2RST USART2 reset 17 1 USART3RST USART3 reset 18 1 USART4RST USART4 reset 19 1 APBRSTR2 APBRSTR2 APB peripheral reset register 2 0x30 32 read-write n 0x0 0x0 ADCRST ADC reset 20 1 SPI1RST SPI1 reset 12 1 SYSCFGRST SYSCFG, COMP and VREFBUF reset 0 1 TIM14RST TIM14 timer reset 15 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 TIM1RST TIM1 timer reset 11 1 USART1RST USART1 reset 14 1 APBSMENR1 APBSMENR1 APB peripheral clock enable in Sleep mode register 1 0x4C 32 read-write n 0x0 0x0 CECSMEN HDMI CEC clock enable during Sleep mode 24 1 DAC1SMEN DAC1 interface clock enable during Sleep mode 29 1 DBGSMEN Debug support clock enable during Sleep mode 27 1 I2C1SMEN I2C1 clock enable during Sleep mode 21 1 I2C2SMEN I2C2 clock enable during Sleep mode 22 1 LPTIM1SMEN Low Power Timer 1 clock enable during Sleep mode 31 1 LPTIM2SMEN Low Power Timer 2 clock enable during Sleep mode 30 1 LPUART1SMEN LPUART1 clock enable during Sleep mode 20 1 PWRSMEN Power interface clock enable during Sleep mode 28 1 RTCAPBSMEN RTC APB clock enable during Sleep mode 10 1 SPI2SMEN SPI2 clock enable during Sleep mode 14 1 TIM2SMEN TIM2 timer clock enable during Sleep mode 0 1 TIM3SMEN TIM3 timer clock enable during Sleep mode 1 1 TIM6SMEN TIM6 timer clock enable during Sleep mode 4 1 TIM7SMEN TIM7 timer clock enable during Sleep mode 5 1 UCPD1SMEN UCPD1 clock enable during Sleep mode 25 1 UCPD2SMEN UCPD2 clock enable during Sleep mode 26 1 USART2SMEN USART2 clock enable during Sleep mode 17 1 USART3SMEN USART3 clock enable during Sleep mode 18 1 USART4SMEN USART4 clock enable during Sleep mode 19 1 WWDGSMEN WWDG clock enable during Sleep mode 11 1 APBSMENR2 APBSMENR2 APB peripheral clock enable in Sleep mode register 2 0x50 32 read-write n 0x0 0x0 ADCSMEN ADC clock enable during Sleep mode 20 1 SPI1SMEN SPI1 clock enable during Sleep mode 12 1 SYSCFGSMEN SYSCFG, COMP and VREFBUF clock enable during Sleep mode 0 1 TIM14SMEN TIM14 timer clock enable during Sleep mode 15 1 TIM15SMEN TIM15 timer clock enable during Sleep mode 16 1 TIM16SMEN TIM16 timer clock enable during Sleep mode 17 1 TIM17SMEN TIM16 timer clock enable during Sleep mode 18 1 TIM1SMEN TIM1 timer clock enable during Sleep mode 11 1 USART1SMEN USART1 clock enable during Sleep mode 14 1 BDCR BDCR RTC domain control register 0x5C 32 read-write n 0x0 0x0 BDRST RTC domain software reset 16 1 LSCOEN Low-speed clock output (LSCO) enable 24 1 LSCOSEL Low-speed clock output selection 25 1 LSEBYP LSE oscillator bypass 2 1 LSECSSD CSS on LSE failure Detection 6 1 LSECSSON CSS on LSE enable 5 1 LSEDRV LSE oscillator drive capability 3 2 LSEON LSE oscillator enable 0 1 LSERDY LSE oscillator ready 1 1 RTCEN RTC clock enable 15 1 RTCSEL RTC clock source selection 8 2 CCIPR CCIPR Peripherals independent clock configuration register 0x54 32 read-write n 0x0 0x0 ADCSEL ADCs clock source selection 30 2 CECSEL HDMI CEC clock source selection 6 1 I2C1SEL I2C1 clock source selection 12 2 I2S2SEL I2S1 clock source selection 14 2 LPTIM1SEL LPTIM1 clock source selection 18 2 LPTIM2SEL LPTIM2 clock source selection 20 2 LPUART1SEL LPUART1 clock source selection 10 2 RNGDIV Division factor of RNG clock divider 28 2 RNGSEL RNG clock source selection 26 2 TIM15SEL TIM15 clock source selection 24 1 TIM1SEL TIM1 clock source selection 22 1 USART1SEL USART1 clock source selection 0 2 USART2SEL USART2 clock source selection 2 2 CFGR CFGR Clock configuration register 0x8 32 read-write n 0x0 0x0 HPRE AHB prescaler 8 4 read-write MCOPRE Microcontroller clock output prescaler 28 3 read-only MCOSEL Microcontroller clock output 24 3 read-write PPRE APB prescaler 12 3 read-write SW System clock switch 0 3 read-write SWS System clock switch status 3 3 read-only CICR CICR Clock interrupt clear register 0x20 32 write-only n 0x0 0x0 CSSC Clock security system interrupt clear 8 1 HSERDYC HSE ready interrupt clear 4 1 HSIRDYC HSI ready interrupt clear 3 1 LSECSSC LSE Clock security system interrupt clear 9 1 LSERDYC LSE ready interrupt clear 1 1 LSIRDYC LSI ready interrupt clear 0 1 PLLSYSRDYC PLL ready interrupt clear 5 1 CIER CIER Clock interrupt enable register 0x18 32 read-write n 0x0 0x0 HSERDYIE HSE ready interrupt enable 4 1 HSIRDYIE HSI ready interrupt enable 3 1 LSERDYIE LSE ready interrupt enable 1 1 LSIRDYIE LSI ready interrupt enable 0 1 PLLSYSRDYIE PLL ready interrupt enable 5 1 CIFR CIFR Clock interrupt flag register 0x1C 32 read-only n 0x0 0x0 CSSF Clock security system interrupt flag 8 1 HSERDYF HSE ready interrupt flag 4 1 HSIRDYF HSI ready interrupt flag 3 1 LSECSSF LSE Clock security system interrupt flag 9 1 LSERDYF LSE ready interrupt flag 1 1 LSIRDYF LSI ready interrupt flag 0 1 PLLSYSRDYF PLL ready interrupt flag 5 1 CR CR Clock control register 0x0 32 read-write n 0x0 0x0 CSSON Clock security system enable 19 1 HSEBYP HSE crystal oscillator bypass 18 1 HSEON HSE clock enable 16 1 HSERDY HSE clock ready flag 17 1 HSIDIV HSI16 clock division factor 11 3 HSIKERON HSI16 always enable for peripheral kernels 9 1 HSION HSI16 clock enable 8 1 HSIRDY HSI16 clock ready flag 10 1 PLLON PLL enable 24 1 PLLRDY PLL clock ready flag 25 1 CSR CSR Control/status register 0x60 32 read-write n 0x0 0x0 IWDGRSTF Independent window watchdog reset flag 29 1 LPWRRSTF Low-power reset flag 31 1 LSION LSI oscillator enable 0 1 LSIRDY LSI oscillator ready 1 1 OBLRSTF Option byte loader reset flag 25 1 PINRSTF Pin reset flag 26 1 PWRRSTF BOR or POR/PDR flag 27 1 RMVF Remove reset flags 23 1 SFTRSTF Software reset flag 28 1 WWDGRSTF Window watchdog reset flag 30 1 ICSCR ICSCR Internal clock sources calibration register 0x4 32 read-write n 0x0 0x0 HSICAL HSI16 clock calibration 0 8 read-only HSITRIM HSI16 clock trimming 8 7 read-write IOPENR IOPENR GPIO clock enable register 0x34 32 read-write n 0x0 0x0 IOPAEN I/O port A clock enable 0 1 IOPBEN I/O port B clock enable 1 1 IOPCEN I/O port C clock enable 2 1 IOPDEN I/O port D clock enable 3 1 IOPFEN I/O port F clock enable 5 1 IOPRSTR IOPRSTR GPIO reset register 0x24 32 read-write n 0x0 0x0 IOPARST I/O port A reset 0 1 IOPBRST I/O port B reset 1 1 IOPCRST I/O port C reset 2 1 IOPDRST I/O port D reset 3 1 IOPFRST I/O port F reset 5 1 IOPSMENR IOPSMENR GPIO in Sleep mode clock enable register 0x44 32 read-write n 0x0 0x0 IOPASMEN I/O port A clock enable during Sleep mode 0 1 IOPBSMEN I/O port B clock enable during Sleep mode 1 1 IOPCSMEN I/O port C clock enable during Sleep mode 2 1 IOPDSMEN I/O port D clock enable during Sleep mode 3 1 IOPFSMEN I/O port F clock enable during Sleep mode 5 1 PLLSYSCFGR PLLSYSCFGR PLL configuration register 0xC 32 read-write n 0x0 0x0 PLLM Division factor M of the PLL input clock divider 4 3 PLLN PLL frequency multiplication factor N 8 7 PLLP PLL VCO division factor P for PLLPCLK clock output 17 5 PLLPEN PLLPCLK clock output enable 16 1 PLLQ PLL VCO division factor Q for PLLQCLK clock output 25 3 PLLQEN PLLQCLK clock output enable 24 1 PLLR PLL VCO division factor R for PLLRCLK clock output 29 3 PLLREN PLLRCLK clock output enable 28 1 PLLSRC PLL input clock source 0 2 RNG Random number generator RNG 0x0 0x0 0x400 registers n CR CR control register 0x0 32 read-write n 0x0 0x0 BYP Bypass mode enable 6 1 CED Clock error detection 5 1 IE Interrupt enable 3 1 RNGEN Random number generator enable 2 1 DR DR data register 0x8 32 read-only n 0x0 0x0 RNDATA Random data 0 32 SR SR status register 0x4 32 read-write n 0x0 0x0 CECS Clock error current status 1 1 read-only CEIS Clock error interrupt status 5 1 read-write DRDY Data ready 0 1 read-only SECS Seed error current status 2 1 read-only SEIS Seed error interrupt status 6 1 read-write RTC Real-time clock RTC 0x0 0x0 0x400 registers n RTC_STAMP RTC and TAMP interrupts 2 ALRMAR ALRMAR alarm A register 0x40 32 read-write n 0x0 0x0 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 MSK2 Alarm A minutes mask 15 1 MSK3 Alarm A hours mask 23 1 MSK4 Alarm A date mask 31 1 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WDSEL Week day selection 30 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 32 read-write n 0x0 0x0 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBR ALRMBR alarm B register 0x48 32 read-write n 0x0 0x0 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 MSK2 Alarm B minutes mask 15 1 MSK3 Alarm B hours mask 23 1 MSK4 Alarm B date mask 31 1 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WDSEL Week day selection 30 1 ALRMBSSR ALRMBSSR alarm B sub second register 0x4C 32 read-write n 0x0 0x0 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 CALR CALR calibration register 0x28 32 read-write n 0x0 0x0 CALM Calibration minus 0 9 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW8 Use an 8-second calibration cycle period 14 1 CR CR control register 0x18 32 read-write n 0x0 0x0 ADD1H ADD1H 16 1 ALRAE ALRAE 8 1 ALRAIE ALRAIE 12 1 ALRBE ALRBE 9 1 ALRBIE ALRBIE 13 1 BKP BKP 18 1 BYPSHAD BYPSHAD 5 1 COE COE 23 1 COSEL COSEL 19 1 FMT FMT 6 1 ITSE ITSE 24 1 OSEL OSEL 21 2 OUT2EN OUT2EN 31 1 POL POL 20 1 REFCKON REFCKON 4 1 SUB1H SUB1H 17 1 TAMPALRM_PU TAMPALRM_PU 29 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 TAMPOE TAMPOE 26 1 TAMPTS TAMPTS 25 1 TSE TSE 11 1 TSEDGE TSEDGE 3 1 TSIE TSIE 15 1 WUCKSEL WUCKSEL 0 3 WUTE WUTE 10 1 WUTIE WUTIE 14 1 DR DR date register 0x4 32 read-write n 0x0 0x0 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 WDU Week day units 13 3 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 HWCFGR HWCFGR hardware configuration register 0x3F0 32 read-write n 0x0 0x0 ALARMB ALARMB 0 4 OPTIONREG_OUT OPTIONREG_OUT 16 8 SMOOTH_CALIB SMOOTH_CALIB 8 4 TIMESTAMP TIMESTAMP 12 4 TRUST_ZONE TRUST_ZONE 24 4 WAKEUP WAKEUP 4 4 ICSR ICSR initialization and status register 0xC 32 read-write n 0x0 0x0 ALRAWF Alarm A write flag 0 1 read-only ALRBWF Alarm B write flag 1 1 read-only INIT Initialization mode 7 1 read-write INITF Initialization flag 6 1 read-only INITS Initialization status flag 4 1 read-only RECALPF Recalibration pending Flag 16 1 read-only RSF Registers synchronization flag 5 1 read-write SHPF Shift operation pending 3 1 read-write WUTWF Wakeup timer write flag 2 1 read-only IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 MISR MISR masked interrupt status register 0x54 32 read-only n 0x0 0x0 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 ITSMF ITSMF 5 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 WUTMF WUTMF 2 1 PRER PRER prescaler register 0x10 32 read-write n 0x0 0x0 PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 SCR SCR status clear register 0x5C 32 read-write n 0x0 0x0 CALRAF CALRAF 0 1 CALRBF CALRBF 1 1 CITSF CITSF 5 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CWUTF CWUTF 2 1 SHIFTR SHIFTR shift control register 0x2C 32 write-only n 0x0 0x0 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x50 32 read-only n 0x0 0x0 ALRAF ALRAF 0 1 ALRBF ALRBF 1 1 ITSF ITSF 5 1 TSF TSF 3 1 TSOVF TSOVF 4 1 WUTF WUTF 2 1 SSR SSR sub second register 0x8 32 read-only n 0x0 0x0 SS Sub second value 0 16 TR TR time register 0x0 32 read-write n 0x0 0x0 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 TSDR TSDR time stamp date register 0x34 32 read-only n 0x0 0x0 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 WDU Week day units 13 3 TSSSR TSSSR timestamp sub second register 0x38 32 read-only n 0x0 0x0 SS Sub second value 0 16 TSTR TSTR time stamp time register 0x30 32 read-only n 0x0 0x0 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 WPR WPR write protection register 0x24 32 write-only n 0x0 0x0 KEY Write protection key 0 8 WUTR WUTR wakeup timer register 0x14 32 read-write n 0x0 0x0 WUT Wakeup auto-reload value bits 0 16 SCB System control block SCB 0x0 0x0 0x41 registers n AIRCR AIRCR Application interrupt and reset control register 0xC 32 read-write n 0x0 0x0 ENDIANESS ENDIANESS 15 1 SYSRESETREQ SYSRESETREQ 2 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 VECTKEYSTAT Register key 16 16 CCR CCR Configuration and control register 0x14 32 read-write n 0x0 0x0 BFHFNMIGN BFHFNMIGN 8 1 DIV_0_TRP DIV_0_TRP 4 1 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 STKALIGN STKALIGN 9 1 UNALIGN__TRP UNALIGN_ TRP 3 1 USERSETMPEND USERSETMPEND 1 1 CPUID CPUID CPUID base register 0x0 32 read-only n 0x0 0x0 Architecture Reads as 0xF 16 4 Implementer Implementer code 24 8 PartNo Part number of the processor 4 12 Revision Revision number 0 4 Variant Variant number 20 4 ICSR ICSR Interrupt control and state register 0x4 32 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag 22 1 NMIPENDSET NMI set-pending bit. 31 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 RETTOBASE Return to base level 11 1 VECTACTIVE Active vector 0 9 VECTPENDING Pending vector 12 7 SCR SCR System control register 0x10 32 read-write n 0x0 0x0 SEVEONPEND Send Event on Pending bit 4 1 SLEEPDEEP SLEEPDEEP 2 1 SLEEPONEXIT SLEEPONEXIT 1 1 SHPR2 SHPR2 System handler priority registers 0x1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 VTOR VTOR Vector table offset register 0x8 32 read-write n 0x0 0x0 TBLOFF Vector table base offset field 7 25 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI1 SPI1 global interrupt 25 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 HWCFGR HWCFGR hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRC capable at SPI mode 0 4 DSCFG SPI data size configuration 12 4 I2SCFG I2S mode implementation 4 4 I2SCKCFG I2S master clock generator at I2S mode 8 4 NSSCFG NSS pulse feature enhancement at SPI master 16 4 I2SCFGR I2SCFGR configuration register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPOL Inactive state clock polarity 3 1 DATLEN Data length to be transferred 1 2 I2SCFG I2S configuration mode 8 2 I2SMOD I2S mode selection 11 1 I2SSTD standard selection 4 2 PCMSYNC PCM frame synchronization 7 1 SE2 I2S enable 10 1 I2SPR I2SPR prescaler register 0x20 32 read-write n 0x0 0x0 I2SDIV linear prescaler 0 8 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CHSIDE Channel side 2 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only UDR Underrun flag 3 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 SPI2 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI2 SPI2 global interrupt 60 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 HWCFGR HWCFGR hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRC capable at SPI mode 0 4 DSCFG SPI data size configuration 12 4 I2SCFG I2S mode implementation 4 4 I2SCKCFG I2S master clock generator at I2S mode 8 4 NSSCFG NSS pulse feature enhancement at SPI master 16 4 I2SCFGR I2SCFGR configuration register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPOL Inactive state clock polarity 3 1 DATLEN Data length to be transferred 1 2 I2SCFG I2S configuration mode 8 2 I2SMOD I2S mode selection 11 1 I2SSTD standard selection 4 2 PCMSYNC PCM frame synchronization 7 1 SE2 I2S enable 10 1 I2SPR I2SPR prescaler register 0x20 32 read-write n 0x0 0x0 I2SDIV linear prescaler 0 8 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CHSIDE Channel side 2 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only UDR Underrun flag 3 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 STK SysTick timer STK 0x0 0x0 0x11 registers n CALIB CALIB SysTick calibration value register 0xC 32 read-write n 0x0 0x0 NOREF NOREF flag. Reads as zero 31 1 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 TENMS Calibration value 0 24 CSR CSR SysTick control and status register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CVR CVR SysTick current value register 0x8 32 read-write n 0x0 0x0 CURRENT Current counter value 0 24 RVR RVR SysTick reload value register 0x4 32 read-write n 0x0 0x0 RELOAD RELOAD value 0 24 SYSCFG_VREFBUF System configuration controller SYSCFG 0x0 0x0 0x100 registers n CFGR1 CFGR1 SYSCFG configuration register 1 0x0 32 read-write n 0x0 0x0 BOOSTEN I/O analog switch voltage booster enable 8 1 I2C1_FMP FM+ driving capability activation for I2C1 20 1 I2C2_FMP FM+ driving capability activation for I2C2 21 1 I2C_PAx_FMP Fast Mode Plus (FM+) driving capability activation bits 22 2 I2C_PBx_FMP Fast Mode Plus (FM+) driving capability activation bits 16 4 IR_MOD IR Modulation Envelope signal selection. 6 2 IR_POL IR output polarity selection 5 1 MEM_MODE Memory mapping selection bits 0 2 PA11_PA12_RMP PA11 and PA12 remapping bit. 4 1 UCPD1_STROBE Strobe signal bit for UCPD1 9 1 UCPD2_STROBE Strobe signal bit for UCPD2 10 1 CFGR2 CFGR2 SYSCFG configuration register 1 0x18 32 read-write n 0x0 0x0 ECC_LOCK ECC error lock bit 3 1 LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit 0 1 PVD_LOCK PVD lock enable bit 2 1 SRAM_PARITY_LOCK SRAM parity lock bit 1 1 SRAM_PEF SRAM parity error flag 8 1 ITLINE0 ITLINE0 interrupt line 0 status register 0x80 32 read-only n 0x0 0x0 WWDG Window watchdog interrupt pending flag 0 1 ITLINE1 ITLINE1 interrupt line 1 status register 0x84 32 read-only n 0x0 0x0 PVDOUT PVD supply monitoring interrupt request pending (EXTI line 16). 0 1 ITLINE10 ITLINE10 interrupt line 10 status register 0xA8 32 read-only n 0x0 0x0 DMA1_CH2 DMA1_CH1 0 1 DMA1_CH3 DMA1_CH3 1 1 ITLINE11 ITLINE11 interrupt line 11 status register 0xAC 32 read-only n 0x0 0x0 DMA1_CH4 DMA1_CH4 1 1 DMA1_CH5 DMA1_CH5 2 1 DMA1_CH6 DMA1_CH6 3 1 DMA1_CH7 DMA1_CH7 4 1 DMAMUX DMAMUX 0 1 ITLINE12 ITLINE12 interrupt line 12 status register 0xB0 32 read-only n 0x0 0x0 ADC ADC 0 1 COMP1 COMP1 1 1 COMP2 COMP2 2 1 ITLINE13 ITLINE13 interrupt line 13 status register 0xB4 32 read-only n 0x0 0x0 TIM1_BRK TIM1_BRK 3 1 TIM1_CCU TIM1_CCU 0 1 TIM1_TRG TIM1_TRG 1 1 TIM1_UPD TIM1_UPD 2 1 ITLINE14 ITLINE14 interrupt line 14 status register 0xB8 32 read-only n 0x0 0x0 TIM1_CC TIM1_CC 0 1 ITLINE15 ITLINE15 interrupt line 15 status register 0xBC 32 read-only n 0x0 0x0 TIM2 TIM2 0 1 ITLINE16 ITLINE16 interrupt line 16 status register 0xC0 32 read-only n 0x0 0x0 TIM3 TIM3 0 1 ITLINE17 ITLINE17 interrupt line 17 status register 0xC4 32 read-only n 0x0 0x0 DAC DAC 1 1 LPTIM1 LPTIM1 2 1 TIM6 TIM6 0 1 ITLINE18 ITLINE18 interrupt line 18 status register 0xC8 32 read-only n 0x0 0x0 LPTIM2 LPTIM2 1 1 TIM7 TIM7 0 1 ITLINE19 ITLINE19 interrupt line 19 status register 0xCC 32 read-only n 0x0 0x0 TIM14 TIM14 0 1 ITLINE2 ITLINE2 interrupt line 2 status register 0x88 32 read-only n 0x0 0x0 RTC RTC 1 1 TAMP TAMP 0 1 ITLINE20 ITLINE20 interrupt line 20 status register 0xD0 32 read-only n 0x0 0x0 TIM15 TIM15 0 1 ITLINE21 ITLINE21 interrupt line 21 status register 0xD4 32 read-only n 0x0 0x0 TIM16 TIM16 0 1 ITLINE22 ITLINE22 interrupt line 22 status register 0xD8 32 read-only n 0x0 0x0 TIM17 TIM17 0 1 ITLINE23 ITLINE23 interrupt line 23 status register 0xDC 32 read-only n 0x0 0x0 I2C1 I2C1 0 1 ITLINE24 ITLINE24 interrupt line 24 status register 0xE0 32 read-only n 0x0 0x0 I2C2 I2C2 0 1 ITLINE25 ITLINE25 interrupt line 25 status register 0xE4 32 read-only n 0x0 0x0 SPI1 SPI1 0 1 ITLINE26 ITLINE26 interrupt line 26 status register 0xE8 32 read-only n 0x0 0x0 SPI2 SPI2 0 1 ITLINE27 ITLINE27 interrupt line 27 status register 0xEC 32 read-only n 0x0 0x0 USART1 USART1 0 1 ITLINE28 ITLINE28 interrupt line 28 status register 0xF0 32 read-only n 0x0 0x0 USART2 USART2 0 1 ITLINE29 ITLINE29 interrupt line 29 status register 0xF4 32 read-only n 0x0 0x0 USART3 USART3 0 1 USART4 USART4 1 1 USART5 USART5 2 1 ITLINE3 ITLINE3 interrupt line 3 status register 0x8C 32 read-only n 0x0 0x0 FLASH_ECC FLASH_ECC 1 1 FLASH_ITF FLASH_ITF 0 1 ITLINE30 ITLINE30 interrupt line 30 status register 0xF8 32 read-only n 0x0 0x0 USART2 CEC 0 1 ITLINE31 ITLINE31 interrupt line 31 status register 0xFC 32 read-only n 0x0 0x0 AES AES 1 1 RNG RNG 0 1 ITLINE4 ITLINE4 interrupt line 4 status register 0x90 32 read-only n 0x0 0x0 RCC RCC 0 1 ITLINE5 ITLINE5 interrupt line 5 status register 0x94 32 read-only n 0x0 0x0 EXTI0 EXTI0 0 1 EXTI1 EXTI1 1 1 ITLINE6 ITLINE6 interrupt line 6 status register 0x98 32 read-only n 0x0 0x0 EXTI2 EXTI2 0 1 EXTI3 EXTI3 1 1 ITLINE7 ITLINE7 interrupt line 7 status register 0x9C 32 read-only n 0x0 0x0 EXTI10 EXTI10 6 1 EXTI11 EXTI11 7 1 EXTI12 EXTI12 8 1 EXTI13 EXTI13 9 1 EXTI14 EXTI14 10 1 EXTI15 EXTI15 11 1 EXTI4 EXTI4 0 1 EXTI5 EXTI5 1 1 EXTI6 EXTI6 2 1 EXTI7 EXTI7 3 1 EXTI8 EXTI8 4 1 EXTI9 EXTI9 5 1 ITLINE8 ITLINE8 interrupt line 8 status register 0xA0 32 read-only n 0x0 0x0 UCPD1 UCPD1 0 1 UCPD2 UCPD2 1 1 ITLINE9 ITLINE9 interrupt line 9 status register 0xA4 32 read-only n 0x0 0x0 DMA1_CH1 DMA1_CH1 0 1 VREFBUF_CCR VREFBUF_CCR VREFBUF calibration control register 0x34 32 read-write n 0x0 0x0 TRIM Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. 0 6 VREFBUF_CSR VREFBUF_CSR VREFBUF control and status register 0x30 32 read-write n 0x0 0x0 ENVR Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. 0 1 read-write HIZ High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved 4 3 read-write TAMP Tamper and backup registers TAMP 0x0 0x0 0x400 registers n BKP0R BKP0R TAMP backup register 0x100 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP1R BKP1R TAMP backup register 0x104 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP2R BKP2R TAMP backup register 0x108 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP3R BKP3R TAMP backup register 0x10C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP4R BKP4R TAMP backup register 0x110 32 read-write n 0x0 0x0 BKP BKP 0 32 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ITAMP1E ITAMP1E 16 1 ITAMP3E ITAMP3E 18 1 ITAMP4E ITAMP4E 19 1 ITAMP5E ITAMP5E 20 1 ITAMP6E ITAMP6E 21 1 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TAMP1MSK TAMP1MSK 16 1 TAMP1NOER TAMP1NOER 0 1 TAMP1TRG TAMP1TRG 24 1 TAMP2MSK TAMP2MSK 17 1 TAMP2NOER TAMP2NOER 1 1 TAMP2TRG TAMP2TRG 25 1 FLTCR FLTCR TAMP filter control register 0xC 32 read-write n 0x0 0x0 TAMPFLT TAMPFLT 3 2 TAMPFREQ TAMPFREQ 0 3 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 HWCFGR1 HWCFGR1 TAMP hardware configuration register 1 0x3F0 32 read-only n 0x0 0x0 ACTIVE_TAMPER ACTIVE_TAMPER 12 4 BACKUP_REGS BACKUP_REGS 0 8 INT_TAMPER INT_TAMPER 16 16 TAMPER TAMPER 8 4 HWCFGR2 HWCFGR2 TAMP hardware configuration register 2 0x3EC 32 read-only n 0x0 0x0 PTIONREG_OUT PTIONREG_OUT 0 8 TRUST_ZONE TRUST_ZONE 8 4 IER IER TAMP interrupt enable register 0x2C 32 read-write n 0x0 0x0 ITAMP1IE ITAMP1IE 16 1 ITAMP3IE ITAMP3IE 18 1 ITAMP4IE ITAMP4IE 19 1 ITAMP5IE ITAMP5IE 20 1 ITAMP6IE ITAMP6IE 21 1 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 MISR MISR TAMP masked interrupt status register 0x34 32 read-only n 0x0 0x0 ITAMP1MF ITAMP1MF 16 1 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP6MF ITAMP6MF 21 1 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 SCR SCR TAMP status clear register 0x3C 32 write-only n 0x0 0x0 CITAMP1F CITAMP1F 16 1 CITAMP3F CITAMP3F 18 1 CITAMP4F CITAMP4F 19 1 CITAMP5F CITAMP5F 20 1 CITAMP6F CITAMP6F 21 1 CITAMP7F CITAMP7F 22 1 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR TAMP status register 0x30 32 read-only n 0x0 0x0 ITAMP1F ITAMP1F 16 1 ITAMP3F ITAMP3F 18 1 ITAMP4F ITAMP4F 19 1 ITAMP5F ITAMP5F 20 1 ITAMP6F ITAMP6F 21 1 ITAMP7F ITAMP7F 22 1 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 TIM1 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM1_BRK_UP_TRG_COMP TIM1 break, update, trigger 13 TIM1_CC TIM1 Capture Compare interrupt 14 AF1 AF1 DMA address for full transfer 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 3 AF2 AF2 DMA address for full transfer 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INE BRK2 BKIN input enable 0 1 BK2INP BRK2 BKIN input polarity 9 1 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BK2DSRM Break2 Disarm 27 1 BK2E Break 2 enable 24 1 BK2F Break 2 filter 20 4 BK2ID Break2 bidirectional 29 1 BK2P Break 2 polarity 25 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (output mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (output mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 1 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x58 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x5C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 MMS2 Master mode selection 2 20 4 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS6 Output Idle state 6 (OC6 output) 18 1 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 B2G Break 2 generation 8 1 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 OR1 OR1 option register 1 0x50 32 read-write n 0x0 0x0 OCREF_CLR Ocref_clr source selection 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 20 2 TS_4 Trigger selection 4 3 SR SR status register 0x10 32 read-write n 0x0 0x0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 COMIF COM interrupt flag 5 1 SBIF System Break interrupt flag 13 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM14 General purpose timers TIM 0x0 0x0 0x400 registers n TIM14 TIM14 global interrupt 19 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 OC1CE OC1CE 7 1 OC1FE OC1FE 2 1 OC1M OC1M 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE OC1PE 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Low Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT low counter value 0 16 UIFCPY UIF Copy 31 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SR SR status register 0x10 32 read-write n 0x0 0x0 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x68 32 read-write n 0x0 0x0 TISEL TI1[0] to TI1[15] input selection 0 4 TIM15 General purpose timers TIM 0x0 0x0 0x400 registers n TIM15 Timer 15 global interrupt 20 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write B_0x0 MOE can be set only by software 0x0 B_0x1 MOE can be set by software or automatically at the next update event (if the break input is not be active) 0x1 BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write B_0x0 Break input BRK in input mode 0x0 B_0x1 Break input BRK in bidirectional mode 0x1 BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write B_0x0 Break input BRK is armed 0x0 B_0x1 Break input BRK is disarmed 0x1 BKE Break enable 1 Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write B_0x0 Break inputs (BRK and CCS clock failure event) disabled 0x0 BKF Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write B_0x0 No filter, BRK acts asynchronously 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write B_0x0 Break input BRK is active low 0x0 B_0x1 Break input BRK is active high 0x1 DTG Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 8 read-write LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write B_0x0 LOCK OFF - No bit is write protected 0x0 B_0x1 LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written 0x1 B_0x2 LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 0x2 B_0x3 LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. 0x3 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). 15 1 read-write B_0x0 OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 0x0 B_0x1 OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) 0x1 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 0x0 B_0x1 When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) 0x1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write B_0x0 When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 0x0 B_0x1 When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). 0x1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. 0 1 read-write B_0x0 Capture mode disabled / OC1 is not active (see below) 0x0 B_0x1 Capture mode enabled / OC1 signal is output on the corresponding output pin 0x1 CC1NE Capture/Compare 1 complementary output enable 2 1 read-write B_0x0 Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x0 B_0x1 On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 0x1 CC1NP Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. 3 1 read-write B_0x0 OC1N active high 0x0 B_0x1 OC1N active low 0x1 CC1P Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. 1 1 read-write B_0x0 OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 0x0 B_0x1 OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) 0x1 CC2E Capture/Compare 2 output enable Refer to CC1E description 4 1 read-write CC2NP Capture/Compare 2 complementary output polarity Refer to CC1NP description 7 1 read-write CC2P Capture/Compare 2 output polarity Refer to CC1P description 5 1 read-write CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 4 4 read-write B_0x0 No filter, sampling is done at fDTS 0x0 B_0x1 fSAMPLING=fCK_INT, N=2 0x1 B_0x2 fSAMPLING=fCK_INT, N=4 0x2 B_0x3 fSAMPLING=fCK_INT, N=8 0x3 B_0x4 fSAMPLING=fDTS/2, N=6 0x4 B_0x5 fSAMPLING=fDTS/2, N=8 0x5 B_0x6 fSAMPLING=fDTS/4, N=6 0x6 B_0x7 fSAMPLING=fDTS/4, N=8 0x7 B_0x8 fSAMPLING=fDTS/8, N=6 0x8 B_0x9 fSAMPLING=fDTS/8, N=8 0x9 B_0xA fSAMPLING=fDTS/16, N=5 0xA B_0xB fSAMPLING=fDTS/16, N=6 0xB B_0xC fSAMPLING=fDTS/16, N=8 0xC B_0xD fSAMPLING=fDTS/32, N=5 0xD B_0xE fSAMPLING=fDTS/32, N=6 0xE B_0xF fSAMPLING=fDTS/32, N=8 0xF IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 2 2 read-write B_0x0 no prescaler, capture is done each time an edge is detected on the capture input 0x0 B_0x1 capture is done once every 2 events 0x1 B_0x2 capture is done once every 4 events 0x2 B_0x3 capture is done once every 8 events 0x3 IC2F Input capture 2 filter 12 4 read-write IC2PSC Input capture 2 prescaler 10 2 read-write CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). 0 2 read-write B_0x0 CC1 channel is configured as output. 0x0 B_0x1 CC1 channel is configured as input, IC1 is mapped on TI1. 0x1 B_0x2 CC1 channel is configured as input, IC1 is mapped on TI2. 0x2 B_0x3 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) 0x3 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). 8 2 read-write B_0x0 CC2 channel is configured as output. 0x0 B_0x1 CC2 channel is configured as input, IC2 is mapped on TI2. 0x1 B_0x2 CC2 channel is configured as input, IC2 is mapped on TI1. 0x2 B_0x3 CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) 0x3 OC1FE Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. 2 1 read-write B_0x0 CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 0x0 B_0x1 An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. 0x1 OC1M1 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16. 4 3 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD OC1M2 Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16. 16 1 read-write B_0x0 Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0x0 B_0x1 Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x1 B_0x2 Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0x2 B_0x3 Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0x3 B_0x4 Force inactive level - OC1REF is forced low. 0x4 B_0x5 Force active level - OC1REF is forced high. 0x5 B_0x6 PWM mode 1 - Channel 1 is active as long as TIMx_CNT 0x6 B_0x7 PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT 0x7 B_0x8 Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 0x8 B_0x9 Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 0x9 B_0xC Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 0xC B_0xD Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 0xD OC1PE Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 3 1 read-write B_0x0 Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 0x0 B_0x1 Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. 0x1 OC2FE Output Compare 2 fast enable 10 1 read-write OC2M1 Output Compare 2 mode 12 3 read-write OC2M2 Output Compare 2 mode 24 1 read-write OC2PE Output Compare 2 preload enable 11 1 read-write CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 read-write B_0x0 TIMx_ARR register is not buffered 0x0 B_0x1 TIMx_ARR register is buffered 0x1 CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write B_0x0 Counter disabled 0x0 B_0x1 Counter enabled 0x1 CKD Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx) 8 2 read-write B_0x0 tDTS = tCK_INT 0x0 B_0x1 tDTS = 2*tCK_INT 0x1 B_0x2 tDTS = 4*tCK_INT 0x2 B_0x3 Reserved, do not program this value 0x3 OPM One-pulse mode 3 1 read-write B_0x0 Counter is not stopped at update event 0x0 B_0x1 Counter stops counting at the next update event (clearing the bit CEN) 0x1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write B_0x0 UEV enabled. The Update (UEV) event is generated by one of the following events: 0x0 B_0x1 UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 0x1 UIFREMAP UIF status bit remapping 11 1 read-write B_0x0 No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 0x0 B_0x1 Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. 0x1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write B_0x0 Any of the following events generate an update interrupt if enabled. These events can be: 0x0 B_0x1 Only counter overflow/underflow generates an update interrupt if enabled 0x1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 read-write B_0x0 CCx DMA request sent when CCx event occurs 0x0 B_0x1 CCx DMA requests sent when update event occurs 0x1 CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write B_0x0 CCxE, CCxNE and OCxM bits are not preloaded 0x0 B_0x1 CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). 0x1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write B_0x0 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 0x0 B_0x1 When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. 0x1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 4 3 read-write B_0x0 Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 0x0 B_0x1 Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 0x1 B_0x2 Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 0x2 B_0x3 Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 0x3 B_0x4 Compare - OC1REFC signal is used as trigger output (TRGO). 0x4 B_0x5 Compare - OC2REFC signal is used as trigger output (TRGO). 0x5 OIS1 Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 8 1 read-write B_0x0 OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 0x0 B_0x1 OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 0x1 OIS1N Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 9 1 read-write B_0x0 OC1N=0 after a dead-time when MOE=0 0x0 B_0x1 OC1N=1 after a dead-time when MOE=0 0x1 OIS2 Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register). 10 1 read-write B_0x0 OC2=0 when MOE=0 0x0 B_0x1 OC2=1 when MOE=0 0x1 TI1S TI1 selection 7 1 read-write B_0x0 The TIMx_CH1 pin is connected to TI1 input 0x0 B_0x1 The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) 0x1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write B_0x0 TIMx_CR1, 0x0 B_0x1 TIMx_CR2, 0x1 B_0x2 TIMx_SMCR, 0x2 DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write B_0x0 1 transfer, 0x0 B_0x1 2 transfers, 0x1 B_0x11 18 transfers. 0x11 B_0x2 3 transfers, 0x2 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 read-write B_0x0 Break interrupt disabled 0x0 B_0x1 Break interrupt enabled 0x1 CC1DE Capture/Compare 1 DMA request enable 9 1 read-write B_0x0 CC1 DMA request disabled 0x0 B_0x1 CC1 DMA request enabled 0x1 CC1IE Capture/Compare 1 interrupt enable 1 1 read-write B_0x0 CC1 interrupt disabled 0x0 B_0x1 CC1 interrupt enabled 0x1 CC2DE Capture/Compare 2 DMA request enable 10 1 read-write B_0x0 CC2 DMA request disabled 0x0 B_0x1 CC2 DMA request enabled 0x1 CC2IE Capture/Compare 2 interrupt enable 2 1 read-write B_0x0 CC2 interrupt disabled 0x0 B_0x1 CC2 interrupt enabled 0x1 COMDE COM DMA request enable 13 1 read-write B_0x0 COM DMA request disabled 0x0 B_0x1 COM DMA request enabled 0x1 COMIE COM interrupt enable 5 1 read-write B_0x0 COM interrupt disabled 0x0 B_0x1 COM interrupt enabled 0x1 TDE Trigger DMA request enable 14 1 read-write B_0x0 Trigger DMA request disabled 0x0 B_0x1 Trigger DMA request enabled 0x1 TIE Trigger interrupt enable 6 1 read-write B_0x0 Trigger interrupt disabled 0x0 B_0x1 Trigger interrupt enabled 0x1 UDE Update DMA request enable 8 1 read-write B_0x0 Update DMA request disabled 0x0 B_0x1 Update DMA request enabled 0x1 UIE Update interrupt enable 0 1 read-write B_0x0 Update interrupt disabled 0x0 B_0x1 Update interrupt enabled 0x1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only B_0x0 No action 0x0 B_0x1 A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 0x1 CC1G Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 write-only B_0x0 No action 0x0 B_0x1 A capture/compare event is generated on channel 1: 0x1 CC2G Capture/Compare 2 generation Refer to CC1G description 2 1 write-only COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 read-write B_0x0 No action 0x0 B_0x1 When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits 0x1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only B_0x0 No action 0x0 B_0x1 The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled 0x1 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only B_0x0 No action 0x0 B_0x1 Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 0x1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 MSM Master/slave mode 7 1 read-write B_0x0 No action 0x0 B_0x1 The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 0x1 SMS1 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 0x8 SMS2 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write B_0x0 Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. 0x0 B_0x4 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0x4 B_0x5 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0x5 B_0x6 Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0x6 B_0x7 External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 0x7 B_0x8 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 0x8 TS1 Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 TS2 Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write B_0x0 Internal Trigger 0 (ITR0) 0x0 B_0x1 Internal Trigger 1 (ITR1) 0x1 B_0x2 Internal Trigger 2 (ITR2) 0x2 B_0x3 Internal Trigger 3 (ITR3) 0x3 B_0x4 TI1 Edge Detector (TI1F_ED) 0x4 B_0x5 Filtered Timer Input 1 (TI1FP1) 0x5 B_0x6 Filtered Timer Input 2 (TI2FP2) 0x6 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write B_0x0 No break event occurred 0x0 B_0x1 An active level has been detected on the break input 0x1 CC1IF Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 1 1 read-write B_0x0 No compare match / No input capture occurred 0x0 B_0x1 A compare match or an input capture occurred 0x1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. 9 1 read-write B_0x0 No overcapture has been detected 0x0 B_0x1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 0x1 CC2IF Capture/Compare 2 interrupt flag refer to CC1IF description 2 1 read-write CC2OF Capture/Compare 2 overcapture flag Refer to CC1OF description 10 1 read-write COMIF COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 5 1 read-write B_0x0 No COM event occurred 0x0 B_0x1 COM interrupt pending 0x1 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write B_0x0 No trigger event occurred 0x0 B_0x1 Trigger interrupt pending 0x1 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write B_0x0 No update occurred. 0x0 B_0x1 Update interrupt pending. This bit is set by hardware when the registers are updated: 0x1 TIM16 General purpose timers TIM 0x0 0x0 0x400 registers n TIM16 TIM16 global interrupt 21 AF1 AF1 TIM17 option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarit 11 1 BKDFBK1E BRK DFSDM_BREAK1 enable 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_2 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 COMG Capture/Compare control update generation 5 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 COMIF COM interrupt flag 5 1 UIF Update interrupt flag 0 1 TISEL TISEL input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL selects input 0 4 TI2SEL selects input 8 4 TIM17 General purpose timers TIM 0x0 0x0 0x400 registers n TIM17 TIM17 global interrupt 22 AF1 AF1 TIM17 option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarit 11 1 BKDFBK1E BRK DFSDM_BREAK1 enable 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_2 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 COMG Capture/Compare control update generation 5 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 COMIF COM interrupt flag 5 1 UIF Update interrupt flag 0 1 TISEL TISEL input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL selects input 0 4 TI2SEL selects input 8 4 TIM2 General-purpose-timers TIM 0x0 0x0 0x400 registers n TIM2 TIM2 global interrupt 15 TIM3 TIM3 global interrupt 16 AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 ETRSEL External trigger source selection 14 4 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 OR1 OR1 TIM option register 0x50 32 read-write n 0x0 0x0 IOCREF_CLR IOCREF_CLR 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM alternate function option register 1 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TIM3 General-purpose-timers TIM 0x0 0x0 0x400 registers n AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 ETRSEL External trigger source selection 14 4 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 OR1 OR1 TIM option register 0x50 32 read-write n 0x0 0x0 IOCREF_CLR IOCREF_CLR 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM alternate function option register 1 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TIM6 Basic timers TIM 0x0 0x0 0x400 registers n TIM6_DAC_LPTIM1 TIM6 + LPTIM1 and DAC global interrupt 17 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 UIFCPY UIF Copy 31 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SR SR status register 0x10 32 read-write n 0x0 0x0 UIF Update interrupt flag 0 1 TIM7 Basic timers TIM 0x0 0x0 0x400 registers n TIM7_LPTIM2 TIM7 + LPTIM2 global interrupt 18 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 UIFCPY UIF Copy 31 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SR SR status register 0x10 32 read-write n 0x0 0x0 UIF Update interrupt flag 0 1 UCPD1 USB Power Delivery interface UCPD 0x0 0x0 0x400 registers n UCPD1_UCPD2 UCPD global interrupt 8 CFG1 CFG1 UCPD configuration register 0x0 32 read-write n 0x0 0x0 HBITCLKDIV HBITCLKDIV 0 6 IFRGAP IFRGAP 6 5 PSC_USBPDCLK PSC_USBPDCLK 17 3 RXDMAEN RXDMAEN: 30 1 RXORDSETEN RXORDSETEN 20 9 TRANSWIN TRANSWIN 11 5 TXDMAEN TXDMAEN 29 1 UCPDEN UCPDEN 31 1 CFG2 CFG2 UCPD configuration register 2 0x4 32 read-write n 0x0 0x0 FORCECLK FORCECLK 2 1 RXFILT2N3 RXFILT2N3 1 1 RXFILTDIS RXFILTDIS 0 1 WUPEN WUPEN 3 1 CFG3 CFG3 UCPD configuration register 3 0x8 32 read-write n 0x0 0x0 TRIM1_NG_CC1A5 TRIM1_NG_CC1A5 4 5 TRIM1_NG_CC3A0 TRIM1_NG_CC3A0 9 4 TRIM1_NG_CCRPD TRIM1_NG_CCRPD 0 4 TRIM2_NG_CC1A5 TRIM2_NG_CC1A5 20 5 TRIM2_NG_CC3A0 TRIM2_NG_CC3A0 25 4 TRIM2_NG_CCRPD TRIM2_NG_CCRPD 16 4 CR CR UCPD control register 0xC 32 read-write n 0x0 0x0 ANAMODE ANAMODE 9 1 ANASUBMODE ANASUBMODE 7 2 CC1TCDIS CC1TCDIS 20 1 CC2TCDIS CC2TCDIS 21 1 CCENABLE CCENABLE 10 2 DBATTEN DBATTEN 15 1 FRSRXEN FRSRXEN 16 1 FRSTX FRSTX 17 1 PHYCCSEL PHYCCSEL 6 1 PHYRXEN PHYRXEN 5 1 RDCH RDCH 18 1 RXMODE RXMODE 4 1 TXHRST TXHRST 3 1 TXMODE TXMODE 0 2 TXSEND TXSEND 2 1 ICR ICR UCPD Interrupt Clear Register 0x18 32 read-write n 0x0 0x0 FRSEVTCF FRSEVTCF 20 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXMSGENDCF RXMSGENDCF 12 1 RXORDDETCF RXORDDETCF 9 1 RXOVRCF RXOVRCF 11 1 TXMSGABTCF TXMSGABTCF 3 1 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXUNDCF TXUNDCF 6 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 IMR IMR UCPD Interrupt Mask Register 0x10 32 read-write n 0x0 0x0 FRSEVTIE FRSEVTIE 20 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXMSGENDIE RXMSGENDIE 12 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXOVRIE RXOVRIE 11 1 TXISIE TXISIE 0 1 TXMSGABTIE TXMSGABTIE 3 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXUNDIE TXUNDIE 6 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 IPID IPID UCPD IP ID register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 IPVER IPVER UCPD IP ID register 0x3F4 32 read-only n 0x0 0x0 IPVER IPVER 0 32 MID MID UCPD IP ID register 0x3FC 32 read-only n 0x0 0x0 IPID IPID 0 32 RXDR RXDR UCPD Receive Data Register 0x30 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 RX_ORDEXT1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 0x34 32 read-write n 0x0 0x0 RXSOPX1 RXSOPX1 0 20 RX_ORDEXT2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 0x38 32 read-write n 0x0 0x0 RXSOPX2 RXSOPX2 0 20 RX_ORDSET RX_ORDSET UCPD Rx Ordered Set Register 0x28 32 read-only n 0x0 0x0 RXORDSET RXORDSET 0 3 RXSOP3OF4 RXSOP3OF4 3 1 RXSOPKINVALID RXSOPKINVALID 4 3 RX_PAYSZ RX_PAYSZ UCPD Rx Paysize Register 0x2C 32 read-write n 0x0 0x0 RXPAYSZ RXPAYSZ 0 10 SR SR UCPD Status Register 0x14 32 read-only n 0x0 0x0 FRSEVT FRSEVT 20 1 HRSTDISC HRSTDISC 4 1 HRSTSENT HRSTSENT 5 1 RXERR RXERR 13 1 RXHRSTDET RXHRSTDET 10 1 RXMSGEND RXMSGEND 12 1 RXNE RXNE 8 1 RXORDDET RXORDDET 9 1 RXOVR RXOVR 11 1 TXIS TXIS 0 1 TXMSGABT TXMSGABT 3 1 TXMSGDISC TXMSGDISC 1 1 TXMSGSENT TXMSGSENT 2 1 TXUND TXUND 6 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 TXDR TXDR UCPD Tx Data Register 0x24 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 TX_ORDSET TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 32 read-write n 0x0 0x0 TXORDSET TXORDSET 0 20 TX_PAYSZ TX_PAYSZ UCPD Tx Paysize Register 0x20 32 read-write n 0x0 0x0 TXPAYSZ TXPAYSZ 0 10 UCPD2 USB Power Delivery interface UCPD 0x0 0x0 0x400 registers n CFG1 CFG1 UCPD configuration register 0x0 32 read-write n 0x0 0x0 HBITCLKDIV HBITCLKDIV 0 6 IFRGAP IFRGAP 6 5 PSC_USBPDCLK PSC_USBPDCLK 17 3 RXDMAEN RXDMAEN: 30 1 RXORDSETEN RXORDSETEN 20 9 TRANSWIN TRANSWIN 11 5 TXDMAEN TXDMAEN 29 1 UCPDEN UCPDEN 31 1 CFG2 CFG2 UCPD configuration register 2 0x4 32 read-write n 0x0 0x0 FORCECLK FORCECLK 2 1 RXFILT2N3 RXFILT2N3 1 1 RXFILTDIS RXFILTDIS 0 1 WUPEN WUPEN 3 1 CFG3 CFG3 UCPD configuration register 3 0x8 32 read-write n 0x0 0x0 TRIM1_NG_CC1A5 TRIM1_NG_CC1A5 4 5 TRIM1_NG_CC3A0 TRIM1_NG_CC3A0 9 4 TRIM1_NG_CCRPD TRIM1_NG_CCRPD 0 4 TRIM2_NG_CC1A5 TRIM2_NG_CC1A5 20 5 TRIM2_NG_CC3A0 TRIM2_NG_CC3A0 25 4 TRIM2_NG_CCRPD TRIM2_NG_CCRPD 16 4 CR CR UCPD control register 0xC 32 read-write n 0x0 0x0 ANAMODE ANAMODE 9 1 ANASUBMODE ANASUBMODE 7 2 CC1TCDIS CC1TCDIS 20 1 CC2TCDIS CC2TCDIS 21 1 CCENABLE CCENABLE 10 2 DBATTEN DBATTEN 15 1 FRSRXEN FRSRXEN 16 1 FRSTX FRSTX 17 1 PHYCCSEL PHYCCSEL 6 1 PHYRXEN PHYRXEN 5 1 RDCH RDCH 18 1 RXMODE RXMODE 4 1 TXHRST TXHRST 3 1 TXMODE TXMODE 0 2 TXSEND TXSEND 2 1 ICR ICR UCPD Interrupt Clear Register 0x18 32 read-write n 0x0 0x0 FRSEVTCF FRSEVTCF 20 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXMSGENDCF RXMSGENDCF 12 1 RXORDDETCF RXORDDETCF 9 1 RXOVRCF RXOVRCF 11 1 TXMSGABTCF TXMSGABTCF 3 1 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXUNDCF TXUNDCF 6 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 IMR IMR UCPD Interrupt Mask Register 0x10 32 read-write n 0x0 0x0 FRSEVTIE FRSEVTIE 20 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXMSGENDIE RXMSGENDIE 12 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXOVRIE RXOVRIE 11 1 TXISIE TXISIE 0 1 TXMSGABTIE TXMSGABTIE 3 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXUNDIE TXUNDIE 6 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 IPID IPID UCPD IP ID register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 IPVER IPVER UCPD IP ID register 0x3F4 32 read-only n 0x0 0x0 IPVER IPVER 0 32 MID MID UCPD IP ID register 0x3FC 32 read-only n 0x0 0x0 IPID IPID 0 32 RXDR RXDR UCPD Receive Data Register 0x30 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 RX_ORDEXT1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 0x34 32 read-write n 0x0 0x0 RXSOPX1 RXSOPX1 0 20 RX_ORDEXT2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 0x38 32 read-write n 0x0 0x0 RXSOPX2 RXSOPX2 0 20 RX_ORDSET RX_ORDSET UCPD Rx Ordered Set Register 0x28 32 read-only n 0x0 0x0 RXORDSET RXORDSET 0 3 RXSOP3OF4 RXSOP3OF4 3 1 RXSOPKINVALID RXSOPKINVALID 4 3 RX_PAYSZ RX_PAYSZ UCPD Rx Paysize Register 0x2C 32 read-write n 0x0 0x0 RXPAYSZ RXPAYSZ 0 10 SR SR UCPD Status Register 0x14 32 read-only n 0x0 0x0 FRSEVT FRSEVT 20 1 HRSTDISC HRSTDISC 4 1 HRSTSENT HRSTSENT 5 1 RXERR RXERR 13 1 RXHRSTDET RXHRSTDET 10 1 RXMSGEND RXMSGEND 12 1 RXNE RXNE 8 1 RXORDDET RXORDDET 9 1 RXOVR RXOVR 11 1 TXIS TXIS 0 1 TXMSGABT TXMSGABT 3 1 TXMSGDISC TXMSGDISC 1 1 TXMSGSENT TXMSGSENT 2 1 TXUND TXUND 6 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 TXDR TXDR UCPD Tx Data Register 0x24 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 TX_ORDSET TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 32 read-write n 0x0 0x0 TXORDSET TXORDSET 0 20 TX_PAYSZ TX_PAYSZ UCPD Tx Paysize Register 0x20 32 read-write n 0x0 0x0 TXPAYSZ TXPAYSZ 0 10 USART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART1 USART1 global interrupt 27 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART2 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART2 USART2 global interrupt 28 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART3 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART3_USART4_LPUART1 USART3 + USART4 + LPUART1 29 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART4 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 WWDG System window watchdog WWDG 0x0 0x0 0x400 registers n WWDG Window Watchdog interrupt 0 CFR CFR Configuration register 0x4 32 read-write n 0x0 0x0 EWI Early wakeup interrupt 9 1 W 7-bit window value 0 7 WDGTB Timer base 11 3 CR CR Control register 0x0 32 read-write n 0x0 0x0 T 7-bit counter (MSB to LSB) 0 7 WDGA Activation bit 7 1 SR SR Status register 0x8 32 read-write n 0x0 0x0 EWIF Early wakeup interrupt flag 0 1